Involve an new and common mathod to send pme_turn_off() message. Previously
pme_turn_off() implement by platform related special register to trigge
it.
But Yoshihiro give good idea by using iATU to send out message. Previously
Yoshihiro provide patches to raise INTx message by dummy write to outbound
iATU.
Use similar mathod to send out pme_turn_off message.
Previous two patches is picked from Yoshihiro' big patch serialise.
PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
PCI: Add INTx Mechanism Messages macros
PCI: Add PME_TURN_OFF message macro
dt-bindings: PCI: dwc: Add 'msg" register region, Add "msg" region to use
to map PCI msg.
PCI: dwc: Add common pme_turn_off message method
Using common pme_turn_off() message if platform have not define their.
Signed-off-by: Frank Li <[email protected]>
---
Frank Li (3):
PCI: Add PME_TURN_OFF message macro
dt-bindings: PCI: dwc: Add 'msg" register region
PCI: dwc: Add common send pme_turn_off message method
Yoshihiro Shimoda (3):
PCI: Add INTx Mechanism Messages macros
PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
PCI: dwc: Add outbound MSG TLPs support
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 4 +
drivers/pci/controller/dwc/pcie-designware-ep.c | 21 +++--
drivers/pci/controller/dwc/pcie-designware-host.c | 103 +++++++++++++++++----
drivers/pci/controller/dwc/pcie-designware.c | 62 ++++++-------
drivers/pci/controller/dwc/pcie-designware.h | 22 ++++-
drivers/pci/pci.h | 20 ++++
6 files changed, 168 insertions(+), 64 deletions(-)
---
base-commit: e08fc59eee9991afa467d406d684d46d543299a9
change-id: 20240130-pme_msg-dd2d81ee9886
Best regards,
--
Frank Li <[email protected]>
From: Yoshihiro Shimoda <[email protected]>
Add "Message Routing" and "INTx Mechanism Messages" macros to enable
a PCIe driver to send messages for INTx Interrupt Signaling.
The "Message Routing" is from Table 2-17, and the "INTx Mechanism
Messages" is from Table 2-18 on the PCI Express Base Specification,
Rev. 4.0 Version 1.0.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Reviewed-by: Serge Semin <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/pci.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 2336a8d1edab2..fe42f5d10b010 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -22,6 +22,24 @@
*/
#define PCIE_PME_TO_L2_TIMEOUT_US 10000
+/* Message Routing (r[2:0]) */
+#define PCI_MSG_TYPE_R_RC 0
+#define PCI_MSG_TYPE_R_ADDR 1
+#define PCI_MSG_TYPE_R_ID 2
+#define PCI_MSG_TYPE_R_BC 3
+#define PCI_MSG_TYPE_R_LOCAL 4
+#define PCI_MSG_TYPE_R_GATHER 5
+
+/* INTx Mechanism Messages */
+#define PCI_MSG_CODE_ASSERT_INTA 0x20
+#define PCI_MSG_CODE_ASSERT_INTB 0x21
+#define PCI_MSG_CODE_ASSERT_INTC 0x22
+#define PCI_MSG_CODE_ASSERT_INTD 0x23
+#define PCI_MSG_CODE_DEASSERT_INTA 0x24
+#define PCI_MSG_CODE_DEASSERT_INTB 0x25
+#define PCI_MSG_CODE_DEASSERT_INTC 0x26
+#define PCI_MSG_CODE_DEASSERT_INTD 0x27
+
extern const unsigned char pcie_link_speed[];
extern bool pci_early_dump;
--
2.34.1
From: Yoshihiro Shimoda <[email protected]>
This is a preparation before adding the Msg-type outbound iATU
mapping. The respective update will require two more arguments added
to __dw_pcie_prog_outbound_atu(). That will make the already
complicated function prototype even more hard to comprehend accepting
_eight_ arguments. In order to prevent that and keep the code
more-or-less readable all the outbound iATU-related arguments are
moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
is supposed to be locally defined and populated with the outbound iATU
settings implied by the caller context.
As a result of the denoted change there is no longer need in having
the two distinctive methods for the Host and End-point outbound iATU
setups since the corresponding code can directly call the
dw_pcie_prog_outbound_atu() method with the config-structure
populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Reviewed-by: Serge Semin <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 21 +++++----
drivers/pci/controller/dwc/pcie-designware-host.c | 52 ++++++++++++++++-------
drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++++-------------
drivers/pci/controller/dwc/pcie-designware.h | 15 +++++--
4 files changed, 77 insertions(+), 60 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 5befed2dc02b7..27956b2a73be7 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -159,9 +159,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
return 0;
}
-static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
- phys_addr_t phys_addr,
- u64 pci_addr, size_t size)
+static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
+ struct dw_pcie_ob_atu_cfg *atu)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 free_win;
@@ -173,13 +172,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
return -EINVAL;
}
- ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
- phys_addr, pci_addr, size);
+ atu->index = free_win;
+ ret = dw_pcie_prog_outbound_atu(pci, atu);
if (ret)
return ret;
set_bit(free_win, ep->ob_window_map);
- ep->outbound_addr[free_win] = phys_addr;
+ ep->outbound_addr[free_win] = atu->cpu_addr;
return 0;
}
@@ -279,8 +278,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
int ret;
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
+
+ atu.func_no = func_no;
+ atu.type = PCIE_ATU_TYPE_MEM;
+ atu.cpu_addr = addr;
+ atu.pci_addr = pci_addr;
+ atu.size = size;
+ ret = dw_pcie_ep_outbound_atu(ep, &atu);
if (ret) {
dev_err(pci->dev, "Failed to enable address\n");
return ret;
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index d5fc31f8345f7..267687ab33cbc 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
{
struct dw_pcie_rp *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
int type, ret;
u32 busdev;
@@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
else
type = PCIE_ATU_TYPE_CFG1;
- ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
- pp->cfg0_size);
+ atu.type = type;
+ atu.cpu_addr = pp->cfg0_base;
+ atu.pci_addr = busdev;
+ atu.size = pp->cfg0_size;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret)
return NULL;
@@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
{
struct dw_pcie_rp *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
int ret;
ret = pci_generic_config_read(bus, devfn, where, size, val);
@@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
return ret;
if (pp->cfg0_io_shared) {
- ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
- pp->io_base, pp->io_bus_addr,
- pp->io_size);
+ atu.type = PCIE_ATU_TYPE_IO;
+ atu.cpu_addr = pp->io_base;
+ atu.pci_addr = pp->io_bus_addr;
+ atu.size = pp->io_size;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret)
return PCIBIOS_SET_FAILED;
}
@@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
{
struct dw_pcie_rp *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
int ret;
ret = pci_generic_config_write(bus, devfn, where, size, val);
@@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
return ret;
if (pp->cfg0_io_shared) {
- ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
- pp->io_base, pp->io_bus_addr,
- pp->io_size);
+ atu.type = PCIE_ATU_TYPE_IO;
+ atu.cpu_addr = pp->io_base;
+ atu.pci_addr = pp->io_bus_addr;
+ atu.size = pp->io_size;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret)
return PCIBIOS_SET_FAILED;
}
@@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = {
static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
struct resource_entry *entry;
int i, ret;
@@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
if (pci->num_ob_windows <= ++i)
break;
- ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
- entry->res->start,
- entry->res->start - entry->offset,
- resource_size(entry->res));
+ atu.index = i;
+ atu.type = PCIE_ATU_TYPE_MEM;
+ atu.cpu_addr = entry->res->start;
+ atu.pci_addr = entry->res->start - entry->offset;
+ atu.size = resource_size(entry->res);
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret) {
dev_err(pci->dev, "Failed to set MEM range %pr\n",
entry->res);
@@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
if (pp->io_size) {
if (pci->num_ob_windows > ++i) {
- ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
- pp->io_base,
- pp->io_bus_addr,
- pp->io_size);
+ atu.index = i;
+ atu.type = PCIE_ATU_TYPE_IO;
+ atu.cpu_addr = pp->io_base;
+ atu.pci_addr = pp->io_bus_addr;
+ atu.size = pp->io_size;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret) {
dev_err(pci->dev, "Failed to set IO range %pr\n",
entry->res);
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 250cf7f40b858..df2575ec5f44c 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -465,56 +465,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
return val | PCIE_ATU_TD;
}
-static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
- int index, int type, u64 cpu_addr,
- u64 pci_addr, u64 size)
+int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
+ const struct dw_pcie_ob_atu_cfg *atu)
{
+ u64 cpu_addr = atu->cpu_addr;
u32 retries, val;
u64 limit_addr;
if (pci->ops && pci->ops->cpu_addr_fixup)
cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
- limit_addr = cpu_addr + size - 1;
+ limit_addr = cpu_addr + atu->size - 1;
if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
!IS_ALIGNED(cpu_addr, pci->region_align) ||
- !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
+ !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
return -EINVAL;
}
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
lower_32_bits(cpu_addr));
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
upper_32_bits(cpu_addr));
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
lower_32_bits(limit_addr));
if (dw_pcie_ver_is_ge(pci, 460A))
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
upper_32_bits(limit_addr));
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
- lower_32_bits(pci_addr));
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
- upper_32_bits(pci_addr));
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
+ lower_32_bits(atu->pci_addr));
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
+ upper_32_bits(atu->pci_addr));
- val = type | PCIE_ATU_FUNC_NUM(func_no);
+ val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
dw_pcie_ver_is_ge(pci, 460A))
val |= PCIE_ATU_INCREASE_REGION_SIZE;
if (dw_pcie_ver_is(pci, 490A))
val = dw_pcie_enable_ecrc(val);
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
/*
* Make sure ATU enable takes effect before any subsequent config
* and I/O accesses.
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
- val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
+ val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
if (val & PCIE_ATU_ENABLE)
return 0;
@@ -526,21 +526,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
return -ETIMEDOUT;
}
-int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u64 size)
-{
- return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
- cpu_addr, pci_addr, size);
-}
-
-int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
- int type, u64 cpu_addr, u64 pci_addr,
- u64 size)
-{
- return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
- cpu_addr, pci_addr, size);
-}
-
static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
{
return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 26dae48374627..d21db82e586d5 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -299,6 +299,15 @@ enum dw_pcie_ltssm {
DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
};
+struct dw_pcie_ob_atu_cfg {
+ int index;
+ int type;
+ u8 func_no;
+ u64 cpu_addr;
+ u64 pci_addr;
+ u64 size;
+};
+
struct dw_pcie_host_ops {
int (*init)(struct dw_pcie_rp *pp);
void (*deinit)(struct dw_pcie_rp *pp);
@@ -434,10 +443,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
int dw_pcie_link_up(struct dw_pcie *pci);
void dw_pcie_upconfig_setup(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
-int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u64 size);
-int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
- int type, u64 cpu_addr, u64 pci_addr, u64 size);
+int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
+ const struct dw_pcie_ob_atu_cfg *atu);
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
u64 cpu_addr, u64 pci_addr, u64 size);
int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
--
2.34.1
From: Yoshihiro Shimoda <[email protected]>
Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering
INTx IRQs by iATU in the PCIe endpoint mode in near the future.
PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
MsgD. So, this implementation supports the data-less messages only
for now.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Reviewed-by: Serge Semin <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index df2575ec5f44c..ba909fade9db1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
upper_32_bits(atu->pci_addr));
- val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
+ val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
dw_pcie_ver_is_ge(pci, 460A))
val |= PCIE_ATU_INCREASE_REGION_SIZE;
@@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
val = dw_pcie_enable_ecrc(val);
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
- dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+ val = PCIE_ATU_ENABLE;
+ if (atu->type == PCIE_ATU_TYPE_MSG) {
+ /* The data-less messages only for now */
+ val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
+ }
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
/*
* Make sure ATU enable takes effect before any subsequent config
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index d21db82e586d5..703b50bc5e0f1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -148,11 +148,13 @@
#define PCIE_ATU_TYPE_IO 0x2
#define PCIE_ATU_TYPE_CFG0 0x4
#define PCIE_ATU_TYPE_CFG1 0x5
+#define PCIE_ATU_TYPE_MSG 0x10
#define PCIE_ATU_TD BIT(8)
#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
#define PCIE_ATU_REGION_CTRL2 0x004
#define PCIE_ATU_ENABLE BIT(31)
#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
+#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
#define PCIE_ATU_LOWER_BASE 0x008
#define PCIE_ATU_UPPER_BASE 0x00C
@@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg {
int index;
int type;
u8 func_no;
+ u8 code;
+ u8 routing;
u64 cpu_addr;
u64 pci_addr;
u64 size;
--
2.34.1
Add PME_TURN_OFF macros to enable a PCIe host driver to send PME messages.
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/pci.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index fe42f5d10b010..46bbd815efccf 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -40,6 +40,8 @@
#define PCI_MSG_CODE_DEASSERT_INTC 0x26
#define PCI_MSG_CODE_DEASSERT_INTD 0x27
+#define PCI_MSG_CODE_PME_TURN_OFF 0x19
+
extern const unsigned char pcie_link_speed[];
extern bool pci_early_dump;
--
2.34.1
Add a outbound iATU-capable memory-region which will be use to send PCI
message (such as pme-turn-off) to peripheral. So all platforms can use
common method to send out pme-turn-off message by using one outbound iATU.
Signed-off-by: Frank Li <[email protected]>
---
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
index 022055edbf9e6..e27d81b6a131c 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -101,6 +101,10 @@ properties:
Outbound iATU-capable memory-region which will be used to access
the peripheral PCIe devices configuration space.
const: config
+ - description:
+ Outbound iATU-capable memory-region which will be use to send
+ PCI message (such as pme-turn-off) to peripheral.
+ const: msg
- description:
Vendor-specific CSR names. Consider using the generic names above
for new bindings.
--
2.34.1
Set outbound ATU map memory write to send PCI message. So one MMIO write
can trigger a PCI message, such as pme_turn_off.
Add common dw_pcie_send_pme_turn_off_by_atu() function.
Call dw_pcie_send_pme_turn_off_by_atu() to send out pme_turn_off message in
general dw_pcie_suspend_noirq() if there are not platform callback
pme_turn_off() exist.
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 51 +++++++++++++++++++++--
drivers/pci/controller/dwc/pcie-designware.c | 8 ++++
drivers/pci/controller/dwc/pcie-designware.h | 3 ++
3 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 267687ab33cbc..2a281060f3aad 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -728,6 +728,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
pci->num_ob_windows);
+ pci->msg_atu_index = i;
+
i = 0;
resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
if (resource_type(entry->res) != IORESOURCE_MEM)
@@ -833,11 +835,49 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
}
EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
+static int dw_pcie_send_pme_turn_off_by_atu(struct dw_pcie *pci)
+{
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
+ void __iomem *m;
+ int ret = 0;
+
+ if (pci->num_ob_windows <= pci->msg_atu_index)
+ return -EINVAL;
+
+ atu.code = PCI_MSG_CODE_PME_TURN_OFF;
+ atu.routing = PCI_MSG_TYPE_R_BC;
+ atu.type = PCIE_ATU_TYPE_MSG;
+ atu.size = pci->msg_io_size;
+
+ if (!atu.size) {
+ dev_dbg(pci->dev,
+ "atu memory map windows is zero, please check 'msg' reg in dts\n");
+ return -ENOMEM;
+ }
+
+ atu.cpu_addr = pci->msg_io_base;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
+ if (ret)
+ return ret;
+
+ m = ioremap(atu.cpu_addr, PAGE_SIZE);
+ if (!m)
+ return -ENOMEM;
+
+ /* A dummy write is converted to a Msg TLP */
+ writel(0, m);
+
+ iounmap(m);
+
+ return ret;
+}
+
int dw_pcie_suspend_noirq(struct dw_pcie *pci)
{
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
u32 val;
- int ret;
+ int ret = 0;
/*
* If L1SS is supported, then do not put the link into L2 as some
@@ -849,10 +889,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
return 0;
- if (!pci->pp.ops->pme_turn_off)
- return 0;
+ if (pci->pp.ops->pme_turn_off)
+ pci->pp.ops->pme_turn_off(&pci->pp);
+ else
+ ret = dw_pcie_send_pme_turn_off_by_atu(pci);
- pci->pp.ops->pme_turn_off(&pci->pp);
+ if (ret)
+ return ret;
ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
PCIE_PME_TO_L2_TIMEOUT_US/10,
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index ba909fade9db1..eb24362009bb6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -155,6 +155,14 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
}
}
+ if (!pci->msg_io_base) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg");
+ if (res) {
+ pci->msg_io_base = res->start;
+ pci->msg_io_size = res->end - res->start + 1;
+ }
+ }
+
/* LLDD is supposed to manually switch the clocks and resets state */
if (dw_pcie_cap_is(pci, REQ_RES)) {
ret = dw_pcie_get_clocks(pci);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 703b50bc5e0f1..866ab44df9fd1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -424,6 +424,9 @@ struct dw_pcie {
struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];
struct gpio_desc *pe_rst;
bool suspended;
+ int msg_atu_index;
+ phys_addr_t msg_io_base;
+ size_t msg_io_size;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
--
2.34.1
On Tue, Jan 30, 2024 at 07:45:26PM -0500, Frank Li wrote:
> From: Yoshihiro Shimoda <[email protected]>
>
> Add "Message Routing" and "INTx Mechanism Messages" macros to enable
> a PCIe driver to send messages for INTx Interrupt Signaling.
>
> The "Message Routing" is from Table 2-17, and the "INTx Mechanism
> Messages" is from Table 2-18 on the PCI Express Base Specification,
> Rev. 4.0 Version 1.0.
Please cite a newer spec revision, e.g., PCIe r6.0 or r6.1.
Also, please cite section numbers instead of table numbers because the
table numbers are hard to find (you can't navigate to them from
"Contents") and they change a lot between spec revisions. "INTx
Mechanism Messages" is Table 2-21 in r6.0, but it's in sec 2.2.8.1 in
both r4.0 and r6.0.
> Signed-off-by: Yoshihiro Shimoda <[email protected]>
> Reviewed-by: Serge Semin <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
With these updates:
Acked-by: Bjorn Helgaas <[email protected]>
> ---
> drivers/pci/pci.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 2336a8d1edab2..fe42f5d10b010 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -22,6 +22,24 @@
> */
> #define PCIE_PME_TO_L2_TIMEOUT_US 10000
>
> +/* Message Routing (r[2:0]) */
Add citation to the comment: "PCIe r6.0, sec 2.2.8"
> +#define PCI_MSG_TYPE_R_RC 0
I think I would prefix all these with "PCIE" instead of "PCI", since
they are specific to PCIe and we already use "PCIE" for some of the
PCIe-specific timeouts.
> +#define PCI_MSG_TYPE_R_ADDR 1
> +#define PCI_MSG_TYPE_R_ID 2
> +#define PCI_MSG_TYPE_R_BC 3
> +#define PCI_MSG_TYPE_R_LOCAL 4
> +#define PCI_MSG_TYPE_R_GATHER 5
> +
> +/* INTx Mechanism Messages */
Add "PCIe r6.0, sec 2.2.8.1"
> +#define PCI_MSG_CODE_ASSERT_INTA 0x20
> +#define PCI_MSG_CODE_ASSERT_INTB 0x21
> +#define PCI_MSG_CODE_ASSERT_INTC 0x22
> +#define PCI_MSG_CODE_ASSERT_INTD 0x23
> +#define PCI_MSG_CODE_DEASSERT_INTA 0x24
> +#define PCI_MSG_CODE_DEASSERT_INTB 0x25
> +#define PCI_MSG_CODE_DEASSERT_INTC 0x26
> +#define PCI_MSG_CODE_DEASSERT_INTD 0x27
> +
> extern const unsigned char pcie_link_speed[];
> extern bool pci_early_dump;
>
>
> --
> 2.34.1
>
On Wed, Jan 31, 2024 at 09:41:15AM -0600, Bjorn Helgaas wrote:
> Nit: could the subject line be more specific than "change arguments"?
> E.g., something about collecting dw_pcie_prog_outbound_atu() arguments
> in a struct? If you know that's the fundamental change, it's a lot
> easier to read the commit log and the patch because you know the goal.
How about
"Consolidate arguments of dw_pcie_prog_outbound_atu() into a structure"
Frank
>
> On Tue, Jan 30, 2024 at 07:45:27PM -0500, Frank Li wrote:
> > From: Yoshihiro Shimoda <[email protected]>
> >
> > This is a preparation before adding the Msg-type outbound iATU
> > mapping. The respective update will require two more arguments added
> > to __dw_pcie_prog_outbound_atu(). That will make the already
> > complicated function prototype even more hard to comprehend accepting
> > _eight_ arguments. In order to prevent that and keep the code
> > more-or-less readable all the outbound iATU-related arguments are
> > moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
> > to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
> > is supposed to be locally defined and populated with the outbound iATU
> > settings implied by the caller context.
> >
> > As a result of the denoted change there is no longer need in having
> > the two distinctive methods for the Host and End-point outbound iATU
> > setups since the corresponding code can directly call the
> > dw_pcie_prog_outbound_atu() method with the config-structure
> > populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
> >
> > Signed-off-by: Yoshihiro Shimoda <[email protected]>
> > Reviewed-by: Serge Semin <[email protected]>
> > Reviewed-by: Manivannan Sadhasivam <[email protected]>
> > Signed-off-by: Frank Li <[email protected]>
> > ...
Nit: could the subject line be more specific than "change arguments"?
E.g., something about collecting dw_pcie_prog_outbound_atu() arguments
in a struct? If you know that's the fundamental change, it's a lot
easier to read the commit log and the patch because you know the goal.
On Tue, Jan 30, 2024 at 07:45:27PM -0500, Frank Li wrote:
> From: Yoshihiro Shimoda <[email protected]>
>
> This is a preparation before adding the Msg-type outbound iATU
> mapping. The respective update will require two more arguments added
> to __dw_pcie_prog_outbound_atu(). That will make the already
> complicated function prototype even more hard to comprehend accepting
> _eight_ arguments. In order to prevent that and keep the code
> more-or-less readable all the outbound iATU-related arguments are
> moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
> to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
> is supposed to be locally defined and populated with the outbound iATU
> settings implied by the caller context.
>
> As a result of the denoted change there is no longer need in having
> the two distinctive methods for the Host and End-point outbound iATU
> setups since the corresponding code can directly call the
> dw_pcie_prog_outbound_atu() method with the config-structure
> populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
>
> Signed-off-by: Yoshihiro Shimoda <[email protected]>
> Reviewed-by: Serge Semin <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ...
Super nit: use matching quotes in subject.
On Tue, Jan 30, 2024 at 07:45:30PM -0500, Frank Li wrote:
> Add a outbound iATU-capable memory-region which will be use to send PCI
> message (such as pme-turn-off) to peripheral. So all platforms can use
> common method to send out pme-turn-off message by using one outbound iATU.
s/Add a outbound/Add an outbound/
s/will be use/will be used/ (also below)
s/PCI/PCIe/ (also below)
s/pme-turn-off/PME_Turn_Off/ to make it more searchable in spec (also below)
> Signed-off-by: Frank Li <[email protected]>
> ---
> Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> index 022055edbf9e6..e27d81b6a131c 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> @@ -101,6 +101,10 @@ properties:
> Outbound iATU-capable memory-region which will be used to access
> the peripheral PCIe devices configuration space.
> const: config
> + - description:
> + Outbound iATU-capable memory-region which will be use to send
> + PCI message (such as pme-turn-off) to peripheral.
> + const: msg
> - description:
> Vendor-specific CSR names. Consider using the generic names above
> for new bindings.
>
> --
> 2.34.1
>
On Wed, Jan 31, 2024 at 10:56:01AM -0500, Frank Li wrote:
> On Wed, Jan 31, 2024 at 09:41:15AM -0600, Bjorn Helgaas wrote:
> > Nit: could the subject line be more specific than "change arguments"?
> > E.g., something about collecting dw_pcie_prog_outbound_atu() arguments
> > in a struct? If you know that's the fundamental change, it's a lot
> > easier to read the commit log and the patch because you know the goal.
>
> How about
> "Consolidate arguments of dw_pcie_prog_outbound_atu() into a structure"
Sounds good!
Hi Frank,
> From: Frank Li, Sent: Wednesday, January 31, 2024 9:45 AM
>
> From: Yoshihiro Shimoda <[email protected]>
>
> Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering
> INTx IRQs by iATU in the PCIe endpoint mode in near the future.
> PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
> MsgD. So, this implementation supports the data-less messages only
> for now.
>
> Signed-off-by: Yoshihiro Shimoda <[email protected]>
> Reviewed-by: Serge Semin <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
Perhaps, your Signed-off-by is needed here?
Best regards,
Yoshihiro Shimoda
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index df2575ec5f44c..ba909fade9db1 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> upper_32_bits(atu->pci_addr));
>
> - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
> if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> dw_pcie_ver_is_ge(pci, 460A))
> val |= PCIE_ATU_INCREASE_REGION_SIZE;
> @@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> val = dw_pcie_enable_ecrc(val);
> dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
>
> - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> + val = PCIE_ATU_ENABLE;
> + if (atu->type == PCIE_ATU_TYPE_MSG) {
> + /* The data-less messages only for now */
> + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
> + }
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
>
> /*
> * Make sure ATU enable takes effect before any subsequent config
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index d21db82e586d5..703b50bc5e0f1 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -148,11 +148,13 @@
> #define PCIE_ATU_TYPE_IO 0x2
> #define PCIE_ATU_TYPE_CFG0 0x4
> #define PCIE_ATU_TYPE_CFG1 0x5
> +#define PCIE_ATU_TYPE_MSG 0x10
> #define PCIE_ATU_TD BIT(8)
> #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
> #define PCIE_ATU_REGION_CTRL2 0x004
> #define PCIE_ATU_ENABLE BIT(31)
> #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
> +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
> #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
> #define PCIE_ATU_LOWER_BASE 0x008
> #define PCIE_ATU_UPPER_BASE 0x00C
> @@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg {
> int index;
> int type;
> u8 func_no;
> + u8 code;
> + u8 routing;
> u64 cpu_addr;
> u64 pci_addr;
> u64 size;
>
> --
> 2.34.1
On Thu, Feb 01, 2024 at 03:07:24AM +0000, Yoshihiro Shimoda wrote:
> Hi Frank,
>
> > From: Frank Li, Sent: Wednesday, January 31, 2024 9:45 AM
> >
> > From: Yoshihiro Shimoda <[email protected]>
> >
> > Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering
> > INTx IRQs by iATU in the PCIe endpoint mode in near the future.
> > PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
> > MsgD. So, this implementation supports the data-less messages only
> > for now.
> >
> > Signed-off-by: Yoshihiro Shimoda <[email protected]>
> > Reviewed-by: Serge Semin <[email protected]>
> > Reviewed-by: Manivannan Sadhasivam <[email protected]>
>
> Perhaps, your Signed-off-by is needed here?
Yes, I will add at next version.
Frank
>
> Best regards,
> Yoshihiro Shimoda
>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> > drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> > 2 files changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index df2575ec5f44c..ba909fade9db1 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > upper_32_bits(atu->pci_addr));
> >
> > - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
> > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > dw_pcie_ver_is_ge(pci, 460A))
> > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > @@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > val = dw_pcie_enable_ecrc(val);
> > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> >
> > - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > + val = PCIE_ATU_ENABLE;
> > + if (atu->type == PCIE_ATU_TYPE_MSG) {
> > + /* The data-less messages only for now */
> > + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
> > + }
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
> >
> > /*
> > * Make sure ATU enable takes effect before any subsequent config
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index d21db82e586d5..703b50bc5e0f1 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -148,11 +148,13 @@
> > #define PCIE_ATU_TYPE_IO 0x2
> > #define PCIE_ATU_TYPE_CFG0 0x4
> > #define PCIE_ATU_TYPE_CFG1 0x5
> > +#define PCIE_ATU_TYPE_MSG 0x10
> > #define PCIE_ATU_TD BIT(8)
> > #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
> > #define PCIE_ATU_REGION_CTRL2 0x004
> > #define PCIE_ATU_ENABLE BIT(31)
> > #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
> > +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
> > #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
> > #define PCIE_ATU_LOWER_BASE 0x008
> > #define PCIE_ATU_UPPER_BASE 0x00C
> > @@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg {
> > int index;
> > int type;
> > u8 func_no;
> > + u8 code;
> > + u8 routing;
> > u64 cpu_addr;
> > u64 pci_addr;
> > u64 size;
> >
> > --
> > 2.34.1
>
On Wed, Jan 31, 2024 at 09:37:48AM -0600, Bjorn Helgaas wrote:
> On Tue, Jan 30, 2024 at 07:45:26PM -0500, Frank Li wrote:
> ...
> With these updates:
>
> Acked-by: Bjorn Helgaas <[email protected]>
Sorry, I should have mentioned that there were more comments below.
> > ---
> > drivers/pci/pci.h | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index 2336a8d1edab2..fe42f5d10b010 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -22,6 +22,24 @@
> > */
> > #define PCIE_PME_TO_L2_TIMEOUT_US 10000
> >
> > +/* Message Routing (r[2:0]) */
>
> Add citation to the comment: "PCIe r6.0, sec 2.2.8"
>
> > +#define PCI_MSG_TYPE_R_RC 0
>
> I think I would prefix all these with "PCIE" instead of "PCI", since
> they are specific to PCIe and we already use "PCIE" for some of the
> PCIe-specific timeouts.
>
> > +#define PCI_MSG_TYPE_R_ADDR 1
> > +#define PCI_MSG_TYPE_R_ID 2
> > +#define PCI_MSG_TYPE_R_BC 3
> > +#define PCI_MSG_TYPE_R_LOCAL 4
> > +#define PCI_MSG_TYPE_R_GATHER 5
> > +
> > +/* INTx Mechanism Messages */
>
> Add "PCIe r6.0, sec 2.2.8.1"
>
> > +#define PCI_MSG_CODE_ASSERT_INTA 0x20
> > +#define PCI_MSG_CODE_ASSERT_INTB 0x21
> > +#define PCI_MSG_CODE_ASSERT_INTC 0x22
> > +#define PCI_MSG_CODE_ASSERT_INTD 0x23
> > +#define PCI_MSG_CODE_DEASSERT_INTA 0x24
> > +#define PCI_MSG_CODE_DEASSERT_INTB 0x25
> > +#define PCI_MSG_CODE_DEASSERT_INTC 0x26
> > +#define PCI_MSG_CODE_DEASSERT_INTD 0x27
> > +
> > extern const unsigned char pcie_link_speed[];
> > extern bool pci_early_dump;
> >
> >
> > --
> > 2.34.1
> >