The original patch series "Basic StarFive JH7110 RISC-V SoC support" [1]
is split into 3 patch series. They respectively add basic clock&reset,
pinctrl and device tree support for StarFive JH7110 SoC. These patch
series are independent, but the Visionfive2 board can boot up successfully
only if all these patches series applied. This one adds basic device
tree support. This patch series is pulled out from the patch 1~6 and
patch 27~30 of v1 [1]. You can simply get or review the patches at the
link [2].
[1]: https://lore.kernel.org/all/[email protected]/
[2]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
Changes since v1:
- Rebased on tag v6.1-rc5.
- Added blank line in patch 1. (by Krzysztof)
- Rebased patch 4 and 6 on the newest code. (by Conor)
- Dropped patch 5. (by Conor)
- Removed the quirk of JH7100 in patch 6, considering this patch series
should only add support for JH7110.
- For patch 27, added Co-developed-by tag for Jianlong and me. Renamed
cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style
of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts.
Rewrote clock-controller nodes and deleted reset-controller nodes for
using auxiliary bus. Rewrote gpio nodes following generic pinctrl
bindings. Removed the redundant second reset entry of uart nodes.
- For patch 28, added Co-developed-by tag for Jianlong and me. Added a
chosen node. Removed reserved-memory node. Added fixed frequency clock
nodes for overriding the "clock-frequency" properties. Rewrote the gpio
nodes following generic pinctrl bindings.
- Dropped patch 30. (by Conor)
- Reworded the commit messages.
v1: https://lore.kernel.org/all/[email protected]/
Emil Renner Berthing (7):
dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive2 board
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
soc: sifive: ccache: Add StarFive JH7110 support
riscv: dts: starfive: Add initial StarFive JH7110 device tree
riscv: dts: starfive: Add StarFive JH7110 VisionFive2 board device
tree
Hal Feng (1):
RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
.../sifive,plic-1.0.0.yaml | 1 +
.../bindings/riscv/sifive,ccache0.yaml | 7 +-
.../devicetree/bindings/riscv/starfive.yaml | 4 +
.../bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/Kconfig.socs | 1 +
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../jh7110-starfive-visionfive-v2.dts | 116 +++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 ++++++++++++++++++
arch/riscv/configs/defconfig | 1 +
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
drivers/soc/sifive/sifive_ccache.c | 1 +
12 files changed, 571 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
base-commit: 094226ad94f471a9f19e8f8e7140a09c2625abaa
prerequisite-patch-id: 6b1b43a55b9773bec61ab6c1bbaa54dccbac0837
prerequisite-patch-id: 09c98554df52d17ba5fd604125f8cdd62cbe80d1
prerequisite-patch-id: 29fe0b0c19b6f0cd31114ee9fe17fe9732047f33
prerequisite-patch-id: c59d9908de90e09ba2b9a81aadbf9fb9f00c8f04
prerequisite-patch-id: 94ac03d518993921bcfc9cc9f58d7da0c3528b51
prerequisite-patch-id: 694f7400375f5b85581fc1821e427334507826f2
prerequisite-patch-id: 699d49c4439dadb4b7cf900857f027d050cd6093
prerequisite-patch-id: 40d773f5a19912f731ee5fd4739ed2e3c2157b07
prerequisite-patch-id: 2bc3fd6df5dda116efe882045863d6c88aa81b3a
prerequisite-patch-id: 735e62255c75801bdc4c0b4107850bce821ff7f5
prerequisite-patch-id: b2a923b922e661fa6085185f33c1f1e733db9110
prerequisite-patch-id: b2bbc28354075432f059344eba5a127a653475cf
prerequisite-patch-id: 70eab7b7eee728afcd90e40f6743d1356f6d81ab
prerequisite-patch-id: 6276b2a23818c65ff2ad3d65b562615690cffee9
prerequisite-patch-id: d834ece14ffb525b8c3e661e78736692f33fca9b
prerequisite-patch-id: 4c17a3ce4dae9b788795d915bf775630f5c43c53
prerequisite-patch-id: dabb913fd478e97593e45c23fee4be9fd807f851
prerequisite-patch-id: 22fa141f7f0f80a5d619e9f3f4cf161ad06f108e
prerequisite-patch-id: f306819c257ea73aff8e06b17b5731053cdddfc8
--
2.38.1
From: Emil Renner Berthing <[email protected]>
Add device tree bindings for the StarFive JH7110 RISC-V SoC [1]
and the VisionFive2 board [2] equipped with it.
[1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
[2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 5b36243fd674..64008c57e31f 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -22,6 +22,10 @@ properties:
- const: beagle,beaglev-starlight-jh7100-r0
- const: starfive,jh7100
+ - items:
+ - const: starfive,visionfive-v2
+ - const: starfive,jh7110
+
additionalProperties: true
...
--
2.38.1
Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
StarFive JH7110 and JH7100 SoCs to boot with serial ports.
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..a23d022974ad 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
--
2.38.1
From: Emil Renner Berthing <[email protected]>
This cache controller is also used on the StarFive JH7110 SoC.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../devicetree/bindings/riscv/sifive,ccache0.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index bf3f07421f7e..262d1d49ce25 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -25,6 +25,7 @@ select:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - starfive,jh7110-ccache
required:
- compatible
@@ -37,6 +38,7 @@ properties:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - starfive,jh7110-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
@@ -86,6 +88,7 @@ allOf:
enum:
- sifive,fu740-c000-ccache
- microchip,mpfs-ccache
+ - starfive,jh7110-ccache
then:
properties:
@@ -105,7 +108,9 @@ allOf:
properties:
compatible:
contains:
- const: sifive,fu740-c000-ccache
+ enum:
+ - sifive,fu740-c000-ccache
+ - starfive,jh7110-ccache
then:
properties:
--
2.38.1
From: Emil Renner Berthing <[email protected]>
Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.
Signed-off-by: Emil Renner Berthing <[email protected]>
Co-developed-by: Jianlong Huang <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
1 file changed, 437 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
new file mode 100644
index 000000000000..c22e8f1d2640
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive-jh7110.h>
+#include <dt-bindings/reset/starfive-jh7110.h>
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S76_0: cpu@0 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <8192>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imac";
+ tlb-split;
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_4: cpu@4 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <4>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&S76_0>;
+ };
+
+ core1 {
+ cpu = <&U74_1>;
+ };
+
+ core2 {
+ cpu = <&U74_2>;
+ };
+
+ core3 {
+ cpu = <&U74_3>;
+ };
+
+ core4 {
+ cpu = <&U74_4>;
+ };
+ };
+ };
+ };
+
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ clk_rtc: clk_rtc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ gmac0_rmii_refin: gmac0_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ gmac1_rmii_refin: gmac1_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ i2stx_bclk_ext: i2stx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ i2stx_lrck_ext: i2stx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ i2srx_bclk_ext: i2srx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ i2srx_lrck_ext: i2srx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ tdm_ext: tdm_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ mclk_ext: mclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clint: clint@2000000 {
+ compatible = "starfive,jh7110-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
+ };
+
+ plic: plic@c000000 {
+ compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ riscv,ndev = <136>;
+ };
+
+ ccache: cache-controller@2010000 {
+ compatible = "starfive,jh7110-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x4000>;
+ interrupts = <1>, <3>, <4>, <2>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
+ syscrg: clock-controller@13020000 {
+ compatible = "starfive,jh7110-syscrg";
+ reg = <0x0 0x13020000 0x0 0x10000>;
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ aoncrg: clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ reg = <0x0 0x17000000 0x0 0x10000>;
+ clocks = <&osc>, <&clk_rtc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+ clock-names = "osc", "clk_rtc", "gmac0_rmii_refin",
+ "gmac0_rgmii_rxin", "stg_axiahb",
+ "apb_bus_func", "gmac0_gtxclk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpio: gpio@13040000 {
+ compatible = "starfive,jh7110-sys-pinctrl";
+ reg = <0x0 0x13040000 0x0 0x10000>;
+ reg-names = "control";
+ clocks = <&syscrg JH7110_SYSCLK_IOMUX>;
+ resets = <&syscrg JH7110_SYSRST_IOMUX>;
+ interrupts = <86>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioa: gpio@17020000 {
+ compatible = "starfive,jh7110-aon-pinctrl";
+ reg = <0x0 0x17020000 0x0 0x10000>;
+ reg-names = "control";
+ resets = <&aoncrg JH7110_AONRST_AON_IOMUX>;
+ interrupts = <85>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ uart0: serial@10000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+ <&syscrg JH7110_SYSCLK_UART0_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+ interrupts = <32>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@10010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+ <&syscrg JH7110_SYSCLK_UART1_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+ interrupts = <33>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@10020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+ <&syscrg JH7110_SYSCLK_UART2_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+ interrupts = <34>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@12000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+ <&syscrg JH7110_SYSCLK_UART3_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+ interrupts = <45>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@12010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+ <&syscrg JH7110_SYSCLK_UART4_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+ interrupts = <46>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@12020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+ <&syscrg JH7110_SYSCLK_UART5_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+ interrupts = <47>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+};
--
2.38.1
From: Emil Renner Berthing <[email protected]>
Add compatible string for StarFive JH7110 plic.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 99e01f4d0a69..571700d5cb9e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -60,6 +60,7 @@ properties:
- enum:
- sifive,fu540-c000-plic
- starfive,jh7100-plic
+ - starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
--
2.38.1
From: Emil Renner Berthing <[email protected]>
This adds support for the StarFive JH7110 SoC which also
features this SiFive cache controller.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/Kconfig.socs | 1 +
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
drivers/soc/sifive/sifive_ccache.c | 1 +
4 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..5a40e05f8cab 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,7 @@ config SOC_STARFIVE
bool "StarFive SoCs"
select PINCTRL
select RESET_CONTROLLER
+ select SIFIVE_CCACHE
select SIFIVE_PLIC
help
This enables support for StarFive SoC platform hardware.
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 69ba6508cf2c..534669840858 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -26,7 +26,7 @@ obj-y += qcom/
obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
-obj-$(CONFIG_SOC_SIFIVE) += sifive/
+obj-y += sifive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index ed4c571f8771..e86870be34c9 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE
config SIFIVE_CCACHE
bool "Sifive Composable Cache controller"
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 1c171150e878..9489d1a90fbc 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
{ .compatible = "sifive,ccache0" },
+ { .compatible = "starfive,jh7110-ccache" },
{ /* end of table */ }
};
--
2.38.1
From: Emil Renner Berthing <[email protected]>
Add compatible string for the StarFive JH7110 clint.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index bbad24165837..a9580191f78b 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -27,6 +27,7 @@ properties:
- enum:
- sifive,fu540-c000-clint
- starfive,jh7100-clint
+ - starfive,jh7110-clint
- canaan,k210-clint
- const: sifive,clint0
- items:
--
2.38.1
From: Emil Renner Berthing <[email protected]>
Add a minimal device tree for StarFive JH7110 VisionFive2 board.
Support booting and basic clock/reset/pinctrl/uart drivers.
Signed-off-by: Emil Renner Berthing <[email protected]>
Co-developed-by: Jianlong Huang <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../jh7110-starfive-visionfive-v2.dts | 116 ++++++++++++++++++
2 files changed, 117 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 0ea1bc15ab30..e1237dbc6aac 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
new file mode 100644
index 000000000000..c8946cf3a268
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+
+/ {
+ model = "StarFive VisionFive V2";
+ compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ linux,initrd-start = <0x46100000>;
+ linux,initrd-end = <0x4c000000>;
+ stdout-path = "serial0:115200";
+ };
+
+ cpus {
+ timebase-frequency = <4000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&clk_rtc {
+ clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&tdm_ext {
+ clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&gpio {
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
--
2.38.1
On Fri, 18 Nov 2022 09:17:06 +0800, Hal Feng wrote:
> The original patch series "Basic StarFive JH7110 RISC-V SoC support" [1]
> is split into 3 patch series. They respectively add basic clock&reset,
> pinctrl and device tree support for StarFive JH7110 SoC. These patch
> series are independent, but the Visionfive2 board can boot up successfully
Note that this patch series depends on the patch series [1] and [2].
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
> only if all these patches series applied. This one adds basic device
Reviewed-by: Conor Dooley <[email protected]>
Hey Emil/Hal,
On Fri, Nov 18, 2022 at 09:17:11AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> This adds support for the StarFive JH7110 SoC which also
> features this SiFive cache controller.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> arch/riscv/Kconfig.socs | 1 +
> drivers/soc/Makefile | 2 +-
> drivers/soc/sifive/Kconfig | 2 +-
> drivers/soc/sifive/sifive_ccache.c | 1 +
> 4 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..5a40e05f8cab 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,7 @@ config SOC_STARFIVE
> bool "StarFive SoCs"
> select PINCTRL
> select RESET_CONTROLLER
> + select SIFIVE_CCACHE
Please no. I am trying to get rid of these selects + I cannot figure out
why this driver is so important that you *need* to select it. Surely the
SoC is useable without it?
Is this a hang over from your vendor tree that uses the driver to do
non-coherent stuff for the jh7100?
> select SIFIVE_PLIC
> help
> This enables support for StarFive SoC platform hardware.
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 69ba6508cf2c..534669840858 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -26,7 +26,7 @@ obj-y += qcom/
> obj-y += renesas/
> obj-y += rockchip/
> obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> -obj-$(CONFIG_SOC_SIFIVE) += sifive/
> +obj-y += sifive/
This bit is fine.
> obj-y += sunxi/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-y += ti/
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index ed4c571f8771..e86870be34c9 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -if SOC_SIFIVE
> +if SOC_SIFIVE || SOC_STARFIVE
As I suppose is this - but hardly scalable. I suppose it doesn't really
matter.
> config SIFIVE_CCACHE
> bool "Sifive Composable Cache controller"
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 1c171150e878..9489d1a90fbc 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
> { .compatible = "sifive,fu540-c000-ccache" },
> { .compatible = "sifive,fu740-c000-ccache" },
> { .compatible = "sifive,ccache0" },
> + { .compatible = "starfive,jh7110-ccache" },
Per my second reply to the previous patch, I am not sure why you do not
just have a fallback compatible in the binding/dt for the fu740 ccache
since you appear to have identical configuration?
Thanks,
Conor.
On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> This cache controller is also used on the StarFive JH7110 SoC.
"... and configured identically to that of the FU740"?
Anyways,
Reviewed-by: Conor Dooley <[email protected]>
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../devicetree/bindings/riscv/sifive,ccache0.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> index bf3f07421f7e..262d1d49ce25 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> @@ -25,6 +25,7 @@ select:
> - sifive,ccache0
> - sifive,fu540-c000-ccache
> - sifive,fu740-c000-ccache
> + - starfive,jh7110-ccache
>
> required:
> - compatible
> @@ -37,6 +38,7 @@ properties:
> - sifive,ccache0
> - sifive,fu540-c000-ccache
> - sifive,fu740-c000-ccache
> + - starfive,jh7110-ccache
> - const: cache
> - items:
> - const: microchip,mpfs-ccache
> @@ -86,6 +88,7 @@ allOf:
> enum:
> - sifive,fu740-c000-ccache
> - microchip,mpfs-ccache
> + - starfive,jh7110-ccache
>
> then:
> properties:
> @@ -105,7 +108,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: sifive,fu740-c000-ccache
> + enum:
> + - sifive,fu740-c000-ccache
> + - starfive,jh7110-ccache
>
> then:
> properties:
> --
> 2.38.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Fri, Nov 18, 2022 at 09:17:12AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Co-developed-by: Jianlong Huang <[email protected]>
> Signed-off-by: Jianlong Huang <[email protected]>
> Co-developed-by: Hal Feng <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
> 1 file changed, 437 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..c22e8f1d2640
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -0,0 +1,437 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
@Emil, I feel like I have to ask given the 2022 date, but should this
stuff be attributed to your canonical address or is this fine?
Other than that, a cursory check /looks/ fine, other than the:
> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
If you remove the clock-frequency = <0> bit, dtb validation will force
people to set the value in jh7110-board.dts which I'd prefer to rely on
than a comment.
Glad to see you sorted out the clock/reset stuff too!
Thanks,
Conor.
On Fri, Nov 18, 2022 at 09:17:07AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add device tree bindings for the StarFive JH7110 RISC-V SoC [1]
> and the VisionFive2 board [2] equipped with it.
>
> [1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> [2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
Could you make these two into "Link:" tags please?
Otherwise,
Reviewed-by: Conor Dooley <[email protected]>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index 5b36243fd674..64008c57e31f 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -22,6 +22,10 @@ properties:
> - const: beagle,beaglev-starlight-jh7100-r0
> - const: starfive,jh7100
>
> + - items:
> + - const: starfive,visionfive-v2
> + - const: starfive,jh7110
> +
> additionalProperties: true
>
> ...
> --
> 2.38.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Hey Palmer,
Can you take this patch for v6.2 please, as it kinda just equalises
things for the existing jh7100 stuff? Everyone else can boot defconfig
other than the visionfive v1/beagle v.
Thanks,
Conor.
On Fri, Nov 18, 2022 at 09:17:14AM +0800, Hal Feng wrote:
> Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> StarFive JH7110 and JH7100 SoCs to boot with serial ports.
>
> Reviewed-by: Conor Dooley <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> arch/riscv/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 05fd5fcf24f9..a23d022974ad 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
> CONFIG_INPUT_MOUSEDEV=y
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_DW=y
> CONFIG_SERIAL_OF_PLATFORM=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> --
> 2.38.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Conor Dooley <[email protected]>
On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > This cache controller is also used on the StarFive JH7110 SoC.
>
> "... and configured identically to that of the FU740"?
> Anyways,
> Reviewed-by: Conor Dooley <[email protected]>
Actually, after looking at the next patch - why can you not fall back to
the fu740 one since you appear to have the same configuration as it?
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > .../devicetree/bindings/riscv/sifive,ccache0.yaml | 7 ++++++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> > index bf3f07421f7e..262d1d49ce25 100644
> > --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> > @@ -25,6 +25,7 @@ select:
> > - sifive,ccache0
> > - sifive,fu540-c000-ccache
> > - sifive,fu740-c000-ccache
> > + - starfive,jh7110-ccache
> >
> > required:
> > - compatible
> > @@ -37,6 +38,7 @@ properties:
> > - sifive,ccache0
> > - sifive,fu540-c000-ccache
> > - sifive,fu740-c000-ccache
> > + - starfive,jh7110-ccache
> > - const: cache
> > - items:
> > - const: microchip,mpfs-ccache
> > @@ -86,6 +88,7 @@ allOf:
> > enum:
> > - sifive,fu740-c000-ccache
> > - microchip,mpfs-ccache
> > + - starfive,jh7110-ccache
> >
> > then:
> > properties:
> > @@ -105,7 +108,9 @@ allOf:
> > properties:
> > compatible:
> > contains:
> > - const: sifive,fu740-c000-ccache
> > + enum:
> > + - sifive,fu740-c000-ccache
> > + - starfive,jh7110-ccache
> >
> > then:
> > properties:
> > --
> > 2.38.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 18/11/2022 02:17, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add device tree bindings for the StarFive JH7110 RISC-V SoC [1]
> and the VisionFive2 board [2] equipped with it.
>
> [1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
As Conor said, I think Links are preferred. With that:
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
>
> From: Emil Renner Berthing <[email protected]>
>
> Add a minimal device tree for StarFive JH7110 VisionFive2 board.
Missing space between VisionFive and 2.
> Support booting and basic clock/reset/pinctrl/uart drivers.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Co-developed-by: Jianlong Huang <[email protected]>
> Signed-off-by: Jianlong Huang <[email protected]>
> Co-developed-by: Hal Feng <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/Makefile | 1 +
> .../jh7110-starfive-visionfive-v2.dts | 116 ++++++++++++++++++
> 2 files changed, 117 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 0ea1bc15ab30..e1237dbc6aac 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> new file mode 100644
> index 000000000000..c8946cf3a268
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> +/ {
> + model = "StarFive VisionFive V2";
> + compatible = "starfive,visionfive-v2", "starfive,jh7110";
Again, please consult your colleagues if you're calling the board
"VisionFive 2" or "VisionFive V2" and name the file, model and board
accordingly.
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + linux,initrd-start = <0x46100000>;
> + linux,initrd-end = <0x4c000000>;
These two lines don't belong here. They're added by the bootloader dynamically.
> + stdout-path = "serial0:115200";
You're missing a n8.
> + };
> +
> + cpus {
> + timebase-frequency = <4000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
> + };
> +
> + gpio-restart {
> + compatible = "gpio-restart";
> + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
> + priority = <224>;
> + };
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&clk_rtc {
> + clock-frequency = <32768>;
> +};
> +
> +&gmac0_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac0_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&gmac1_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac1_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&i2stx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2stx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&i2srx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2srx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&tdm_ext {
> + clock-frequency = <49152000>;
> +};
> +
> +&mclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&gpio {
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
> + bias-disable;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
> + bias-pull-up;
There are external pull-ups, so maybe change this line to
bias-disable; /* external pull-up */
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> --
> 2.38.1
>
On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
>
> From: Emil Renner Berthing <[email protected]>
>
> Add device tree bindings for the StarFive JH7110 RISC-V SoC [1]
> and the VisionFive2 board [2] equipped with it.
>
> [1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> [2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index 5b36243fd674..64008c57e31f 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -22,6 +22,10 @@ properties:
> - const: beagle,beaglev-starlight-jh7100-r0
> - const: starfive,jh7100
>
> + - items:
> + - const: starfive,visionfive-v2
I think StarFive has switched to just calling it VisionFive 2 and not
V2. Please check up on this before committing to the compatible
string.
Also there are going to be different revisions of the VisionFive 2
board, so maybe consider adding eg. starfive,visionfive-2-v1.1 and
starfive,visionfive-2-v1,2b early.
> + - const: starfive,jh7110
> +
> additionalProperties: true
>
> ...
> --
> 2.38.1
>
On Fri, 18 Nov 2022 at 13:01, Conor Dooley <[email protected]> wrote:
>
> On Fri, Nov 18, 2022 at 09:17:12AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Co-developed-by: Jianlong Huang <[email protected]>
> > Signed-off-by: Jianlong Huang <[email protected]>
> > Co-developed-by: Hal Feng <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
> > 1 file changed, 437 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > new file mode 100644
> > index 000000000000..c22e8f1d2640
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -0,0 +1,437 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
>
> @Emil, I feel like I have to ask given the 2022 date, but should this
> stuff be attributed to your canonical address or is this fine?
Yeah, this is fine. I did this on my own time before I was actually
tasked with working on the JH7110 based boards.
> Other than that, a cursory check /looks/ fine, other than the:
>
> > + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
> > + };
>
> If you remove the clock-frequency = <0> bit, dtb validation will force
> people to set the value in jh7110-board.dts which I'd prefer to rely on
> than a comment.
>
> Glad to see you sorted out the clock/reset stuff too!
>
> Thanks,
> Conor.
>
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On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
>
> From: Emil Renner Berthing <[email protected]>
>
> This adds support for the StarFive JH7110 SoC which also
> features this SiFive cache controller.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
I'm fine with this, but it would be great if you could add the jh7100
support at the same time like the original patch did.
> arch/riscv/Kconfig.socs | 1 +
> drivers/soc/Makefile | 2 +-
> drivers/soc/sifive/Kconfig | 2 +-
> drivers/soc/sifive/sifive_ccache.c | 1 +
> 4 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..5a40e05f8cab 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,7 @@ config SOC_STARFIVE
> bool "StarFive SoCs"
> select PINCTRL
> select RESET_CONTROLLER
> + select SIFIVE_CCACHE
> select SIFIVE_PLIC
> help
> This enables support for StarFive SoC platform hardware.
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 69ba6508cf2c..534669840858 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -26,7 +26,7 @@ obj-y += qcom/
> obj-y += renesas/
> obj-y += rockchip/
> obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> -obj-$(CONFIG_SOC_SIFIVE) += sifive/
> +obj-y += sifive/
> obj-y += sunxi/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-y += ti/
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index ed4c571f8771..e86870be34c9 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -if SOC_SIFIVE
> +if SOC_SIFIVE || SOC_STARFIVE
>
> config SIFIVE_CCACHE
> bool "Sifive Composable Cache controller"
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 1c171150e878..9489d1a90fbc 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
> { .compatible = "sifive,fu540-c000-ccache" },
> { .compatible = "sifive,fu740-c000-ccache" },
> { .compatible = "sifive,ccache0" },
> + { .compatible = "starfive,jh7110-ccache" },
> { /* end of table */ }
> };
>
> --
> 2.38.1
>
On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
>
> From: Emil Renner Berthing <[email protected]>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Co-developed-by: Jianlong Huang <[email protected]>
> Signed-off-by: Jianlong Huang <[email protected]>
> Co-developed-by: Hal Feng <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
> 1 file changed, 437 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..c22e8f1d2640
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -0,0 +1,437 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/clock/starfive-jh7110.h>
> +#include <dt-bindings/reset/starfive-jh7110.h>
> +
> +/ {
> + compatible = "starfive,jh7110";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + S76_0: cpu@0 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <8192>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <16384>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imac";
> + tlb-split;
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_1: cpu@1 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <1>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_2: cpu@2 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <2>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_3: cpu@3 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <3>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_4: cpu@4 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <4>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&S76_0>;
> + };
> +
> + core1 {
> + cpu = <&U74_1>;
> + };
> +
> + core2 {
> + cpu = <&U74_2>;
> + };
> +
> + core3 {
> + cpu = <&U74_3>;
> + };
> +
> + core4 {
> + cpu = <&U74_4>;
> + };
> + };
> + };
> + };
> +
> + osc: osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + clk_rtc: clk_rtc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + gmac0_rmii_refin: gmac0_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + gmac1_rmii_refin: gmac1_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + i2stx_bclk_ext: i2stx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + i2stx_lrck_ext: i2stx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + i2srx_bclk_ext: i2srx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + i2srx_lrck_ext: i2srx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + tdm_ext: tdm_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + mclk_ext: mclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + soc {
Please sort these nodes after their address like the jh7100.dtsi.
That is sort the nodes after @<number>.
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clint: clint@2000000 {
> + compatible = "starfive,jh7110-clint", "sifive,clint0";
> + reg = <0x0 0x2000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>;
> + };
> +
> + plic: plic@c000000 {
> + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + riscv,ndev = <136>;
> + };
> +
> + ccache: cache-controller@2010000 {
> + compatible = "starfive,jh7110-ccache", "cache";
> + reg = <0x0 0x2010000 0x0 0x4000>;
> + interrupts = <1>, <3>, <4>, <2>;
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <2097152>;
> + cache-unified;
> + };
> +
> + syscrg: clock-controller@13020000 {
> + compatible = "starfive,jh7110-syscrg";
> + reg = <0x0 0x13020000 0x0 0x10000>;
> + clocks = <&osc>, <&gmac1_rmii_refin>,
> + <&gmac1_rgmii_rxin>,
> + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> + <&tdm_ext>, <&mclk_ext>;
> + clock-names = "osc", "gmac1_rmii_refin",
> + "gmac1_rgmii_rxin",
> + "i2stx_bclk_ext", "i2stx_lrck_ext",
> + "i2srx_bclk_ext", "i2srx_lrck_ext",
> + "tdm_ext", "mclk_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + aoncrg: clock-controller@17000000 {
> + compatible = "starfive,jh7110-aoncrg";
> + reg = <0x0 0x17000000 0x0 0x10000>;
> + clocks = <&osc>, <&clk_rtc>,
> + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
> + <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
> + <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>,
> + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
> + clock-names = "osc", "clk_rtc", "gmac0_rmii_refin",
> + "gmac0_rgmii_rxin", "stg_axiahb",
> + "apb_bus_func", "gmac0_gtxclk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + gpio: gpio@13040000 {
> + compatible = "starfive,jh7110-sys-pinctrl";
> + reg = <0x0 0x13040000 0x0 0x10000>;
> + reg-names = "control";
> + clocks = <&syscrg JH7110_SYSCLK_IOMUX>;
> + resets = <&syscrg JH7110_SYSRST_IOMUX>;
> + interrupts = <86>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + gpioa: gpio@17020000 {
> + compatible = "starfive,jh7110-aon-pinctrl";
> + reg = <0x0 0x17020000 0x0 0x10000>;
> + reg-names = "control";
> + resets = <&aoncrg JH7110_AONRST_AON_IOMUX>;
> + interrupts = <85>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + uart0: serial@10000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10000000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
> + <&syscrg JH7110_SYSCLK_UART0_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART0_APB>;
> + interrupts = <32>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@10010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10010000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
> + <&syscrg JH7110_SYSCLK_UART1_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART1_APB>;
> + interrupts = <33>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@10020000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10020000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
> + <&syscrg JH7110_SYSCLK_UART2_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART2_APB>;
> + interrupts = <34>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@12000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12000000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
> + <&syscrg JH7110_SYSCLK_UART3_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART3_APB>;
> + interrupts = <45>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@12010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12010000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
> + <&syscrg JH7110_SYSCLK_UART4_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART4_APB>;
> + interrupts = <46>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart5: serial@12020000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12020000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
> + <&syscrg JH7110_SYSCLK_UART5_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART5_APB>;
> + interrupts = <47>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> +};
> --
> 2.38.1
>
On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
> On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> > On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > > From: Emil Renner Berthing <[email protected]>
> > >
> > > This cache controller is also used on the StarFive JH7110 SoC.
> >
> > "... and configured identically to that of the FU740"?
> > Anyways,
> > Reviewed-by: Conor Dooley <[email protected]>
>
> Actually, after looking at the next patch - why can you not fall back to
> the fu740 one since you appear to have the same configuration as it?
Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
compatible in dts.
Best regards,
Hal
On Sat, 19 Nov 2022 01:32:10 +0800, Emil Renner Berthing wrote:
> On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
> >
> > From: Emil Renner Berthing <[email protected]>
> >
> > This adds support for the StarFive JH7110 SoC which also
> > features this SiFive cache controller.
> >
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
>
> I'm fine with this, but it would be great if you could add the jh7100
> support at the same time like the original patch did.
I think this patch series should only add support for JH7110. Maybe
we can make a new patch series to do this.
Best regards,
Hal
On Tue, Nov 22, 2022 at 04:40:23PM +0800, Hal Feng wrote:
> On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
> > On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> > > On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > > > From: Emil Renner Berthing <[email protected]>
> > > >
> > > > This cache controller is also used on the StarFive JH7110 SoC.
> > >
> > > "... and configured identically to that of the FU740"?
> > > Anyways,
> > > Reviewed-by: Conor Dooley <[email protected]>
> >
> > Actually, after looking at the next patch - why can you not fall back to
> > the fu740 one since you appear to have the same configuration as it?
>
> Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
> compatible in dts.
Uh, that's not quite what I was suggesting. Rather than using that one
in isolation, you can do the following in your dt:
"starfive,jh7110-ccache", "sifive,fu740-c000-ccache"
And then in the driver we need to make no changes - unless down the line
we find some sort of issue that requires special handling etc. There's
no harm in having a "starfive,jh7110-ccache" IMO.
Thanks,
Conor.
On Tue, 22 Nov 2022 09:07:26 +0000, Conor Dooley wrote:
> On Tue, Nov 22, 2022 at 04:40:23PM +0800, Hal Feng wrote:
> > On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
> > > On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> > > > On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > > > > From: Emil Renner Berthing <[email protected]>
> > > > >
> > > > > This cache controller is also used on the StarFive JH7110 SoC.
> > > >
> > > > "... and configured identically to that of the FU740"?
> > > > Anyways,
> > > > Reviewed-by: Conor Dooley <[email protected]>
> > >
> > > Actually, after looking at the next patch - why can you not fall back to
> > > the fu740 one since you appear to have the same configuration as it?
> >
> > Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
> > compatible in dts.
>
> Uh, that's not quite what I was suggesting. Rather than using that one
> in isolation, you can do the following in your dt:
> "starfive,jh7110-ccache", "sifive,fu740-c000-ccache"
>
> And then in the driver we need to make no changes - unless down the line
> we find some sort of issue that requires special handling etc. There's
> no harm in having a "starfive,jh7110-ccache" IMO.
Just like what microchip did as blow?
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
properties:
compatible:
oneOf:
- items:
- enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- starfive,jh7110-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
Best regards,
Hal
On Tue, 22 Nov 2022 at 10:03, Hal Feng <[email protected]> wrote:
>
> On Fri, 18 Nov 2022 19:45:57 +0800, Conor Dooley wrote:
> > Hey Emil/Hal,
> >
> > On Fri, Nov 18, 2022 at 09:17:11AM +0800, Hal Feng wrote:
> > > From: Emil Renner Berthing <[email protected]>
> > >
> > > This adds support for the StarFive JH7110 SoC which also
> > > features this SiFive cache controller.
> > >
> > > Signed-off-by: Emil Renner Berthing <[email protected]>
> > > Signed-off-by: Hal Feng <[email protected]>
> > > ---
> > > arch/riscv/Kconfig.socs | 1 +
> > > drivers/soc/Makefile | 2 +-
> > > drivers/soc/sifive/Kconfig | 2 +-
> > > drivers/soc/sifive/sifive_ccache.c | 1 +
> > > 4 files changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index 69774bb362d6..5a40e05f8cab 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -22,6 +22,7 @@ config SOC_STARFIVE
> > > bool "StarFive SoCs"
> > > select PINCTRL
> > > select RESET_CONTROLLER
> > > + select SIFIVE_CCACHE
> >
> > Please no. I am trying to get rid of these selects + I cannot figure out
> > why this driver is so important that you *need* to select it. Surely the
> > SoC is useable without it>
> > Is this a hang over from your vendor tree that uses the driver to do
> > non-coherent stuff for the jh7100?
>
> I have tested that the board can successfully boot up without the cache
> driver. The `select` can be removed for JH7110. @Emil, what do you think
> of this?
Yes, for the JH7110 this is not strictly needed, just like the
Unmatched board. For the StarFive JH7100 it is though.
So if you're only adding support for the JH7110 then it's not needed.
> >
> > > select SIFIVE_PLIC
> > > help
> > > This enables support for StarFive SoC platform hardware.
> > > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> > > index 69ba6508cf2c..534669840858 100644
> > > --- a/drivers/soc/Makefile
> > > +++ b/drivers/soc/Makefile
> > > @@ -26,7 +26,7 @@ obj-y += qcom/
> > > obj-y += renesas/
> > > obj-y += rockchip/
> > > obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> > > -obj-$(CONFIG_SOC_SIFIVE) += sifive/
> > > +obj-y += sifive/
> >
> > This bit is fine.
> >
> > > obj-y += sunxi/
> > > obj-$(CONFIG_ARCH_TEGRA) += tegra/
> > > obj-y += ti/
> > > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> > > index ed4c571f8771..e86870be34c9 100644
> > > --- a/drivers/soc/sifive/Kconfig
> > > +++ b/drivers/soc/sifive/Kconfig
> > > @@ -1,6 +1,6 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > >
> > > -if SOC_SIFIVE
> > > +if SOC_SIFIVE || SOC_STARFIVE
> >
> > As I suppose is this - but hardly scalable. I suppose it doesn't really
> > matter.
> >
> > > config SIFIVE_CCACHE
> > > bool "Sifive Composable Cache controller"
> > > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > > index 1c171150e878..9489d1a90fbc 100644
> > > --- a/drivers/soc/sifive/sifive_ccache.c
> > > +++ b/drivers/soc/sifive/sifive_ccache.c
> > > @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
> > > { .compatible = "sifive,fu540-c000-ccache" },
> > > { .compatible = "sifive,fu740-c000-ccache" },
> > > { .compatible = "sifive,ccache0" },
> > > + { .compatible = "starfive,jh7110-ccache" },
> >
> > Per my second reply to the previous patch, I am not sure why you do not
> > just have a fallback compatible in the binding/dt for the fu740 ccache
> > since you appear to have identical configuration?
>
> Yeah, I will use the compatible of fu740 and modify this patch.
No, the JH7110 should not pretend to be a fu740, but if you add
compatible = "starfive,jh7110-ccache", "sifive,ccache0";
then this driver should still match "sifive,ccache0" without adding
the "starfive,jh7110-ccache" entry.
>
> Best regards,
> Hal
On Tue, 22 Nov 2022 10:01:30 +0000, Conor Dooley wrote:
> On Tue, Nov 22, 2022 at 05:55:57PM +0800, Hal Feng wrote:
> > On Tue, 22 Nov 2022 09:07:26 +0000, Conor Dooley wrote:
> > > On Tue, Nov 22, 2022 at 04:40:23PM +0800, Hal Feng wrote:
> > > > On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
> > > > > On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> > > > > > On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > > > > > > From: Emil Renner Berthing <[email protected]>
> > > > > > >
> > > > > > > This cache controller is also used on the StarFive JH7110 SoC.
> > > > > >
> > > > > > "... and configured identically to that of the FU740"?
> > > > > > Anyways,
> > > > > > Reviewed-by: Conor Dooley <[email protected]>
> > > > >
> > > > > Actually, after looking at the next patch - why can you not fall back to
> > > > > the fu740 one since you appear to have the same configuration as it?
> > > >
> > > > Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
> > > > compatible in dts.
> > >
> > > Uh, that's not quite what I was suggesting. Rather than using that one
> > > in isolation, you can do the following in your dt:
> > > "starfive,jh7110-ccache", "sifive,fu740-c000-ccache"
> > >
> > > And then in the driver we need to make no changes - unless down the line
> > > we find some sort of issue that requires special handling etc. There's
> > > no harm in having a "starfive,jh7110-ccache" IMO.
> >
> > Just like what microchip did as blow?
below
> >
> > Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
> > properties:
> > compatible:
> > oneOf:
> > - items:
> > - enum:
> > - sifive,ccache0
> > - sifive,fu540-c000-ccache
> > - sifive,fu740-c000-ccache
> > - starfive,jh7110-ccache
> > - const: cache
> > - items:
> > - const: microchip,mpfs-ccache
> > - const: sifive,fu540-c000-ccache
> > - const: cache
>
> No, I don't think this is correct either. You'd do something like:
>
> > - items:
> > - const: starfive,jh7110-ccache
> > - const: sifive,fu740-c000-ccache
> > - const: cache
Yeah, this is what I mean. Thanks.
Best regards,
Hal
>
> And then the driver needs no changes.
On Fri, 18 Nov 2022 19:45:57 +0800, Conor Dooley wrote:
> Hey Emil/Hal,
>
> On Fri, Nov 18, 2022 at 09:17:11AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > This adds support for the StarFive JH7110 SoC which also
> > features this SiFive cache controller.
> >
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > arch/riscv/Kconfig.socs | 1 +
> > drivers/soc/Makefile | 2 +-
> > drivers/soc/sifive/Kconfig | 2 +-
> > drivers/soc/sifive/sifive_ccache.c | 1 +
> > 4 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 69774bb362d6..5a40e05f8cab 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -22,6 +22,7 @@ config SOC_STARFIVE
> > bool "StarFive SoCs"
> > select PINCTRL
> > select RESET_CONTROLLER
> > + select SIFIVE_CCACHE
>
> Please no. I am trying to get rid of these selects + I cannot figure out
> why this driver is so important that you *need* to select it. Surely the
> SoC is useable without it>
> Is this a hang over from your vendor tree that uses the driver to do
> non-coherent stuff for the jh7100?
I have tested that the board can successfully boot up without the cache
driver. The `select` can be removed for JH7110. @Emil, what do you think
of this?
>
> > select SIFIVE_PLIC
> > help
> > This enables support for StarFive SoC platform hardware.
> > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> > index 69ba6508cf2c..534669840858 100644
> > --- a/drivers/soc/Makefile
> > +++ b/drivers/soc/Makefile
> > @@ -26,7 +26,7 @@ obj-y += qcom/
> > obj-y += renesas/
> > obj-y += rockchip/
> > obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> > -obj-$(CONFIG_SOC_SIFIVE) += sifive/
> > +obj-y += sifive/
>
> This bit is fine.
>
> > obj-y += sunxi/
> > obj-$(CONFIG_ARCH_TEGRA) += tegra/
> > obj-y += ti/
> > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> > index ed4c571f8771..e86870be34c9 100644
> > --- a/drivers/soc/sifive/Kconfig
> > +++ b/drivers/soc/sifive/Kconfig
> > @@ -1,6 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> >
> > -if SOC_SIFIVE
> > +if SOC_SIFIVE || SOC_STARFIVE
>
> As I suppose is this - but hardly scalable. I suppose it doesn't really
> matter.
>
> > config SIFIVE_CCACHE
> > bool "Sifive Composable Cache controller"
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > index 1c171150e878..9489d1a90fbc 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
> > { .compatible = "sifive,fu540-c000-ccache" },
> > { .compatible = "sifive,fu740-c000-ccache" },
> > { .compatible = "sifive,ccache0" },
> > + { .compatible = "starfive,jh7110-ccache" },
>
> Per my second reply to the previous patch, I am not sure why you do not
> just have a fallback compatible in the binding/dt for the fu740 ccache
> since you appear to have identical configuration?
Yeah, I will use the compatible of fu740 and modify this patch.
Best regards,
Hal
On 22/11/2022 09:07, Conor Dooley wrote:
> On Tue, Nov 22, 2022 at 04:40:23PM +0800, Hal Feng wrote:
>> On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
>>> On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
>>>> On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
>>>>> From: Emil Renner Berthing <[email protected]>
>>>>>
>>>>> This cache controller is also used on the StarFive JH7110 SoC.
>>>>
>>>> "... and configured identically to that of the FU740"?
>>>> Anyways,
>>>> Reviewed-by: Conor Dooley <[email protected]>
>>>
>>> Actually, after looking at the next patch - why can you not fall back to
>>> the fu740 one since you appear to have the same configuration as it?
>>
>> Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
>> compatible in dts.
>
> Uh, that's not quite what I was suggesting. Rather than using that one
> in isolation, you can do the following in your dt:
> "starfive,jh7110-ccache", "sifive,fu740-c000-ccache"
>
> And then in the driver we need to make no changes - unless down the line
> we find some sort of issue that requires special handling etc. There's
> no harm in having a "starfive,jh7110-ccache" IMO.
Yeah, sifive,ccache0 is probably the generic one which would get
this working.
--
Ben
On Tue, Nov 22, 2022 at 10:54:34AM +0100, Emil Renner Berthing wrote:
> On Tue, 22 Nov 2022 at 10:03, Hal Feng <[email protected]> wrote:
> > On Fri, 18 Nov 2022 19:45:57 +0800, Conor Dooley wrote:
> > > Hey Emil/Hal,
> > > On Fri, Nov 18, 2022 at 09:17:11AM +0800, Hal Feng wrote:
> > > > From: Emil Renner Berthing <[email protected]>
> > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > > index 69774bb362d6..5a40e05f8cab 100644
> > > > --- a/arch/riscv/Kconfig.socs
> > > > +++ b/arch/riscv/Kconfig.socs
> > > > @@ -22,6 +22,7 @@ config SOC_STARFIVE
> > > > bool "StarFive SoCs"
> > > > select PINCTRL
> > > > select RESET_CONTROLLER
> > > > + select SIFIVE_CCACHE
> > >
> > > Please no. I am trying to get rid of these selects + I cannot figure out
> > > why this driver is so important that you *need* to select it. Surely the
> > > SoC is useable without it>
> > > Is this a hang over from your vendor tree that uses the driver to do
> > > non-coherent stuff for the jh7100?
> >
> > I have tested that the board can successfully boot up without the cache
> > driver. The `select` can be removed for JH7110. @Emil, what do you think
> > of this?
>
> Yes, for the JH7110 this is not strictly needed, just like the
> Unmatched board. For the StarFive JH7100 it is though.
> So if you're only adding support for the JH7110 then it's not needed.
Even for the JH7100 there are other ways to do this than selects in
arch/riscv - for example
config SIFIVE_CCACHE
default SOC_STARFIVE
But you don't need that either if you're not adding the JH7100 :)
> > > > config SIFIVE_CCACHE
> > > > bool "Sifive Composable Cache controller"
> > > > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > > > index 1c171150e878..9489d1a90fbc 100644
> > > > --- a/drivers/soc/sifive/sifive_ccache.c
> > > > +++ b/drivers/soc/sifive/sifive_ccache.c
> > > > @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
> > > > { .compatible = "sifive,fu540-c000-ccache" },
> > > > { .compatible = "sifive,fu740-c000-ccache" },
> > > > { .compatible = "sifive,ccache0" },
> > > > + { .compatible = "starfive,jh7110-ccache" },
> > >
> > > Per my second reply to the previous patch, I am not sure why you do not
> > > just have a fallback compatible in the binding/dt for the fu740 ccache
> > > since you appear to have identical configuration?
> >
> > Yeah, I will use the compatible of fu740 and modify this patch.
>
> No, the JH7110 should not pretend to be a fu740, but if you add
>
> compatible = "starfive,jh7110-ccache", "sifive,ccache0";
>
> then this driver should still match "sifive,ccache0" without adding
> the "starfive,jh7110-ccache" entry.
Either works for me :) If you go for "sifive,ccache0", just make sure to
add the correct property enforcement - you can just copy the fu740 by
the looks of things (although that'd imply that it is compatible and can
fall back to it...)
Thanks,
Conor.
On Tue, 22 Nov 2022 at 11:16, Hal Feng <[email protected]> wrote:
>
> On Tue, 22 Nov 2022 10:01:30 +0000, Conor Dooley wrote:
> > On Tue, Nov 22, 2022 at 05:55:57PM +0800, Hal Feng wrote:
> > > On Tue, 22 Nov 2022 09:07:26 +0000, Conor Dooley wrote:
> > > > On Tue, Nov 22, 2022 at 04:40:23PM +0800, Hal Feng wrote:
> > > > > On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
> > > > > > On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> > > > > > > On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > > > > > > > From: Emil Renner Berthing <[email protected]>
> > > > > > > >
> > > > > > > > This cache controller is also used on the StarFive JH7110 SoC.
> > > > > > >
> > > > > > > "... and configured identically to that of the FU740"?
> > > > > > > Anyways,
> > > > > > > Reviewed-by: Conor Dooley <[email protected]>
> > > > > >
> > > > > > Actually, after looking at the next patch - why can you not fall back to
> > > > > > the fu740 one since you appear to have the same configuration as it?
> > > > >
> > > > > Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
> > > > > compatible in dts.
> > > >
> > > > Uh, that's not quite what I was suggesting. Rather than using that one
> > > > in isolation, you can do the following in your dt:
> > > > "starfive,jh7110-ccache", "sifive,fu740-c000-ccache"
> > > >
> > > > And then in the driver we need to make no changes - unless down the line
> > > > we find some sort of issue that requires special handling etc. There's
> > > > no harm in having a "starfive,jh7110-ccache" IMO.
> > >
> > > Just like what microchip did as blow?
>
> below
>
> > >
> > > Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
> > > properties:
> > > compatible:
> > > oneOf:
> > > - items:
> > > - enum:
> > > - sifive,ccache0
> > > - sifive,fu540-c000-ccache
> > > - sifive,fu740-c000-ccache
> > > - starfive,jh7110-ccache
> > > - const: cache
> > > - items:
> > > - const: microchip,mpfs-ccache
> > > - const: sifive,fu540-c000-ccache
> > > - const: cache
> >
> > No, I don't think this is correct either. You'd do something like:
> >
> > > - items:
> > > - const: starfive,jh7110-ccache
> > > - const: sifive,fu740-c000-ccache
For the record I don't think the line above should be there. The
fu7400-c000 is a specific tapeout and pretending the JH7110 is that
tapeout is not right. Especially when there is already the
"sifive,ccache0" string for the generic IP.
> > > - const: cache
>
> Yeah, this is what I mean. Thanks.
>
> Best regards,
> Hal
>
> >
> > And then the driver needs no changes.
>
On Tue, Nov 22, 2022 at 05:55:57PM +0800, Hal Feng wrote:
> On Tue, 22 Nov 2022 09:07:26 +0000, Conor Dooley wrote:
> > On Tue, Nov 22, 2022 at 04:40:23PM +0800, Hal Feng wrote:
> > > On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
> > > > On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> > > > > On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > > > > > From: Emil Renner Berthing <[email protected]>
> > > > > >
> > > > > > This cache controller is also used on the StarFive JH7110 SoC.
> > > > >
> > > > > "... and configured identically to that of the FU740"?
> > > > > Anyways,
> > > > > Reviewed-by: Conor Dooley <[email protected]>
> > > >
> > > > Actually, after looking at the next patch - why can you not fall back to
> > > > the fu740 one since you appear to have the same configuration as it?
> > >
> > > Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
> > > compatible in dts.
> >
> > Uh, that's not quite what I was suggesting. Rather than using that one
> > in isolation, you can do the following in your dt:
> > "starfive,jh7110-ccache", "sifive,fu740-c000-ccache"
> >
> > And then in the driver we need to make no changes - unless down the line
> > we find some sort of issue that requires special handling etc. There's
> > no harm in having a "starfive,jh7110-ccache" IMO.
>
> Just like what microchip did as blow?
>
> Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
> properties:
> compatible:
> oneOf:
> - items:
> - enum:
> - sifive,ccache0
> - sifive,fu540-c000-ccache
> - sifive,fu740-c000-ccache
> - starfive,jh7110-ccache
> - const: cache
> - items:
> - const: microchip,mpfs-ccache
> - const: sifive,fu540-c000-ccache
> - const: cache
No, I don't think this is correct either. You'd do something like:
> - items:
> - const: starfive,jh7110-ccache
> - const: sifive,fu740-c000-ccache
> - const: cache
And then the driver needs no changes.
Thanks,
Conor.
On Tue, 22 Nov 2022 11:35:28 +0100, Emil Renner Berthing wrote:
> On Tue, 22 Nov 2022 at 11:16, Hal Feng <[email protected]> wrote:
> >
> > On Tue, 22 Nov 2022 10:01:30 +0000, Conor Dooley wrote:
> > > On Tue, Nov 22, 2022 at 05:55:57PM +0800, Hal Feng wrote:
> > > > On Tue, 22 Nov 2022 09:07:26 +0000, Conor Dooley wrote:
> > > > > On Tue, Nov 22, 2022 at 04:40:23PM +0800, Hal Feng wrote:
> > > > > > On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
> > > > > > > On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> > > > > > > > On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > > > > > > > > From: Emil Renner Berthing <[email protected]>
> > > > > > > > >
> > > > > > > > > This cache controller is also used on the StarFive JH7110 SoC.
> > > > > > > >
> > > > > > > > "... and configured identically to that of the FU740"?
> > > > > > > > Anyways,
> > > > > > > > Reviewed-by: Conor Dooley <[email protected]>
> > > > > > >
> > > > > > > Actually, after looking at the next patch - why can you not fall back to
> > > > > > > the fu740 one since you appear to have the same configuration as it?
> > > > > >
> > > > > > Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
> > > > > > compatible in dts.
> > > > >
> > > > > Uh, that's not quite what I was suggesting. Rather than using that one
> > > > > in isolation, you can do the following in your dt:
> > > > > "starfive,jh7110-ccache", "sifive,fu740-c000-ccache"
> > > > >
> > > > > And then in the driver we need to make no changes - unless down the line
> > > > > we find some sort of issue that requires special handling etc. There's
> > > > > no harm in having a "starfive,jh7110-ccache" IMO.
> > > >
> > > > Just like what microchip did as blow?
> >
> > below
> >
> > > >
> > > > Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
> > > > properties:
> > > > compatible:
> > > > oneOf:
> > > > - items:
> > > > - enum:
> > > > - sifive,ccache0
> > > > - sifive,fu540-c000-ccache
> > > > - sifive,fu740-c000-ccache
> > > > - starfive,jh7110-ccache
> > > > - const: cache
> > > > - items:
> > > > - const: microchip,mpfs-ccache
> > > > - const: sifive,fu540-c000-ccache
> > > > - const: cache
> > >
> > > No, I don't think this is correct either. You'd do something like:
> > >
> > > > - items:
> > > > - const: starfive,jh7110-ccache
> > > > - const: sifive,fu740-c000-ccache
>
> For the record I don't think the line above should be there. The
> fu7400-c000 is a specific tapeout and pretending the JH7110 is that
> tapeout is not right. Especially when there is already the
> "sifive,ccache0" string for the generic IP.
I will change this line to
- const: sifive,ccache0
Thanks for your suggestion.
>
> > > > - const: cache
> >
> > Yeah, this is what I mean. Thanks.
> >
> > Best regards,
> > Hal
> >
> > >
> > > And then the driver needs no changes.
> >
On Fri, 18 Nov 2022 20:01:28 +0800, Conor Dooley wrote:
> On Fri, Nov 18, 2022 at 09:17:12AM +0800, Hal Feng wrote:
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > new file mode 100644
> > index 000000000000..c22e8f1d2640
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -0,0 +1,437 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
>
> @Emil, I feel like I have to ask given the 2022 date, but should this
> stuff be attributed to your canonical address or is this fine?
>
> Other than that, a cursory check /looks/ fine, other than the:
>
> > + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
> > + };
>
> If you remove the clock-frequency = <0> bit, dtb validation will force
> people to set the value in jh7110-board.dts which I'd prefer to rely on
> than a comment.
Okay, will remove the `clock-frequency = <0>` in this file.
Best regards,
Hal
On Sat, 19 Nov 2022 01:41:41 +0800, Emil Renner Berthing wrote:
> On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
> >
> > From: Emil Renner Berthing <[email protected]>
> >
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Co-developed-by: Jianlong Huang <[email protected]>
> > Signed-off-by: Jianlong Huang <[email protected]>
> > Co-developed-by: Hal Feng <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
> > 1 file changed, 437 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > new file mode 100644
> > index 000000000000..c22e8f1d2640
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -0,0 +1,437 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
> > + */
> > +
[...]
> > +
> > + soc {
>
> Please sort these nodes after their address like the jh7100.dtsi.
> That is sort the nodes after @<number>.
Okay, will fix it.
Best regards,
Hal
On Tue, Nov 22, 2022 at 11:35:28AM +0100, Emil Renner Berthing wrote:
> On Tue, 22 Nov 2022 at 11:16, Hal Feng <[email protected]> wrote:
> >
> > On Tue, 22 Nov 2022 10:01:30 +0000, Conor Dooley wrote:
> > > On Tue, Nov 22, 2022 at 05:55:57PM +0800, Hal Feng wrote:
> > > > On Tue, 22 Nov 2022 09:07:26 +0000, Conor Dooley wrote:
> > > > > On Tue, Nov 22, 2022 at 04:40:23PM +0800, Hal Feng wrote:
> > > > > > On Fri, 18 Nov 2022 19:39:52 +0800, Conor Dooley wrote:
> > > > > > > On Fri, Nov 18, 2022 at 11:37:50AM +0000, Conor Dooley wrote:
> > > > > > > > On Fri, Nov 18, 2022 at 09:17:10AM +0800, Hal Feng wrote:
> > > > > > > > > From: Emil Renner Berthing <[email protected]>
> > > > > > > > >
> > > > > > > > > This cache controller is also used on the StarFive JH7110 SoC.
> > > > > > > >
> > > > > > > > "... and configured identically to that of the FU740"?
> > > > > > > > Anyways,
> > > > > > > > Reviewed-by: Conor Dooley <[email protected]>
> > > > > > >
> > > > > > > Actually, after looking at the next patch - why can you not fall back to
> > > > > > > the fu740 one since you appear to have the same configuration as it?
> > > > > >
> > > > > > Right, I will drop this patch and use "sifive,fu740-c000-ccache" as
> > > > > > compatible in dts.
> > > > >
> > > > > Uh, that's not quite what I was suggesting. Rather than using that one
> > > > > in isolation, you can do the following in your dt:
> > > > > "starfive,jh7110-ccache", "sifive,fu740-c000-ccache"
> > > > >
> > > > > And then in the driver we need to make no changes - unless down the line
> > > > > we find some sort of issue that requires special handling etc. There's
> > > > > no harm in having a "starfive,jh7110-ccache" IMO.
> > > >
> > > > Just like what microchip did as blow?
> >
> > below
> >
> > > >
> > > > Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
> > > > properties:
> > > > compatible:
> > > > oneOf:
> > > > - items:
> > > > - enum:
> > > > - sifive,ccache0
> > > > - sifive,fu540-c000-ccache
> > > > - sifive,fu740-c000-ccache
> > > > - starfive,jh7110-ccache
> > > > - const: cache
> > > > - items:
> > > > - const: microchip,mpfs-ccache
> > > > - const: sifive,fu540-c000-ccache
> > > > - const: cache
> > >
> > > No, I don't think this is correct either. You'd do something like:
> > >
> > > > - items:
> > > > - const: starfive,jh7110-ccache
> > > > - const: sifive,fu740-c000-ccache
>
> For the record I don't think the line above should be there. The
> fu7400-c000 is a specific tapeout and pretending the JH7110 is that
> tapeout is not right. Especially when there is already the
> "sifive,ccache0" string for the generic IP.
All it really says is that this h/w will work with any client (OS)
that understands 'sifive,fu740-c000-ccache'. Maybe 'sifive,ccache0' is
sufficient too, IDK.
Rob
On Fri, 18 Nov 2022 19:31:36 +0800, Conor Dooley wrote:
> On Fri, Nov 18, 2022 at 09:17:07AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > Add device tree bindings for the StarFive JH7110 RISC-V SoC [1]
> > and the VisionFive2 board [2] equipped with it.
> >
> > [1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> > [2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
>
> Could you make these two into "Link:" tags please?
> Otherwise,
> Reviewed-by: Conor Dooley <[email protected]>
OK, will fix it in the next version. Thanks.
Best regards,
Hal
On Sat, 19 Nov 2022 01:28:48 +0800, Emil Renner Berthing wrote:
> On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
> >
> > From: Emil Renner Berthing <[email protected]>
> >
> > Add device tree bindings for the StarFive JH7110 RISC-V SoC [1]
> > and the VisionFive2 board [2] equipped with it.
> >
> > [1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> > [2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> >
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > index 5b36243fd674..64008c57e31f 100644
> > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > @@ -22,6 +22,10 @@ properties:
> > - const: beagle,beaglev-starlight-jh7100-r0
> > - const: starfive,jh7100
> >
> > + - items:
> > + - const: starfive,visionfive-v2
>
> I think StarFive has switched to just calling it VisionFive 2 and not
> V2. Please check up on this before committing to the compatible
> string.
>
> Also there are going to be different revisions of the VisionFive 2
> board, so maybe consider adding eg. starfive,visionfive-2-v1.1 and
> starfive,visionfive-2-v1,2b early.
I checked that the official name of this board is "VisionFive 2". The
board has version A and version B, which are different in gmac and phy
chip. The version A board has one 1000M and one 100M Ethernet ports
while the version B board has two 1000M Ethernet ports. In dts, they
have different configuration parameters for gmac. So I would like to
distinguish them by two compatibles as below in the next version.
- items:
- enum:
- starfive,visionfive-2-va
- starfive,visionfive-2-vb
- const: starfive,jh7110
Best regards,
Hal
>
> > + - const: starfive,jh7110
> > +
> > additionalProperties: true
On Sat, 19 Nov 2022 01:55:40 +0800, Emil Renner Berthing wrote:
> On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
>>
>> From: Emil Renner Berthing <[email protected]>
>>
>> Add a minimal device tree for StarFive JH7110 VisionFive2 board.
> Missing space between VisionFive and 2.
Will fix accordingly.
>
>> Support booting and basic clock/reset/pinctrl/uart drivers.
>>
>> Signed-off-by: Emil Renner Berthing <[email protected]>
>> Co-developed-by: Jianlong Huang <[email protected]>
>> Signed-off-by: Jianlong Huang <[email protected]>
>> Co-developed-by: Hal Feng <[email protected]>
>> Signed-off-by: Hal Feng <[email protected]>
>> ---
>> arch/riscv/boot/dts/starfive/Makefile | 1 +
>> .../jh7110-starfive-visionfive-v2.dts | 116 ++++++++++++++++++
>> 2 files changed, 117 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
>>
>> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
>> index 0ea1bc15ab30..e1237dbc6aac 100644
>> --- a/arch/riscv/boot/dts/starfive/Makefile
>> +++ b/arch/riscv/boot/dts/starfive/Makefile
>> @@ -1,2 +1,3 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
>> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
>> new file mode 100644
>> index 000000000000..c8946cf3a268
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
>> @@ -0,0 +1,116 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
>> +
>> +/ {
>> + model = "StarFive VisionFive V2";
>> + compatible = "starfive,visionfive-v2", "starfive,jh7110";
>
> Again, please consult your colleagues if you're calling the board
> "VisionFive 2" or "VisionFive V2" and name the file, model and board
> accordingly.
Will fix accordingly. Please see the record of patch 1.
>
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + chosen {
>> + linux,initrd-start = <0x46100000>;
>> + linux,initrd-end = <0x4c000000>;
>
> These two lines don't belong here. They're added by the bootloader dynamically.
OK, will delete. Thanks.
>
>> + stdout-path = "serial0:115200";
>
> You're missing a n8.
Will fix.
>
>> + };
>> +
>> + cpus {
>> + timebase-frequency = <4000000>;
>> + };
>> +
>> + memory@40000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x40000000 0x1 0x0>;
>> + };
>> +
>> + gpio-restart {
>> + compatible = "gpio-restart";
>> + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
>> + priority = <224>;
>> + };
>> +};
>> +
>> +&osc {
>> + clock-frequency = <24000000>;
>> +};
>> +
>> +&clk_rtc {
>> + clock-frequency = <32768>;
>> +};
>> +
>> +&gmac0_rmii_refin {
>> + clock-frequency = <50000000>;
>> +};
>> +
>> +&gmac0_rgmii_rxin {
>> + clock-frequency = <125000000>;
>> +};
>> +
>> +&gmac1_rmii_refin {
>> + clock-frequency = <50000000>;
>> +};
>> +
>> +&gmac1_rgmii_rxin {
>> + clock-frequency = <125000000>;
>> +};
>> +
>> +&i2stx_bclk_ext {
>> + clock-frequency = <12288000>;
>> +};
>> +
>> +&i2stx_lrck_ext {
>> + clock-frequency = <192000>;
>> +};
>> +
>> +&i2srx_bclk_ext {
>> + clock-frequency = <12288000>;
>> +};
>> +
>> +&i2srx_lrck_ext {
>> + clock-frequency = <192000>;
>> +};
>> +
>> +&tdm_ext {
>> + clock-frequency = <49152000>;
>> +};
>> +
>> +&mclk_ext {
>> + clock-frequency = <12288000>;
>> +};
>> +
>> +&gpio {
>> + uart0_pins: uart0-0 {
>> + tx-pins {
>> + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
>> + bias-disable;
>> + drive-strength = <12>;
>> + input-disable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> +
>> + rx-pins {
>> + pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
>> + bias-pull-up;
>
> There are external pull-ups, so maybe change this line to
>
> bias-disable; /* external pull-up */
Good job. Will fix it later.
Best regards,
Hal
>
>> + drive-strength = <2>;
>> + input-enable;
>> + input-schmitt-enable;
>> + slew-rate = <0>;
>> + };
>> + };
>> +};
>> +
>> +&uart0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_pins>;
>> + status = "okay";
>> +};
On Thu, 24 Nov 2022 10:20:32 +0100, Emil Renner Berthing wrote:
> On Thu, 24 Nov 2022 at 06:56, Hal Feng <[email protected]> wrote:
> >
> > On Sat, 19 Nov 2022 01:28:48 +0800, Emil Renner Berthing wrote:
> > > On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
> > > >
> > > > From: Emil Renner Berthing <[email protected]>
> > > >
> > > > Add device tree bindings for the StarFive JH7110 RISC-V SoC [1]
> > > > and the VisionFive2 board [2] equipped with it.
> > > >
> > > > [1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> > > > [2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> > > >
> > > > Signed-off-by: Emil Renner Berthing <[email protected]>
> > > > Signed-off-by: Hal Feng <[email protected]>
> > > > ---
> > > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
> > > > 1 file changed, 4 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > > index 5b36243fd674..64008c57e31f 100644
> > > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > > @@ -22,6 +22,10 @@ properties:
> > > > - const: beagle,beaglev-starlight-jh7100-r0
> > > > - const: starfive,jh7100
> > > >
> > > > + - items:
> > > > + - const: starfive,visionfive-v2
> > >
> > > I think StarFive has switched to just calling it VisionFive 2 and not
> > > V2. Please check up on this before committing to the compatible
> > > string.
> > >
> > > Also there are going to be different revisions of the VisionFive 2
> > > board, so maybe consider adding eg. starfive,visionfive-2-v1.1 and
> > > starfive,visionfive-2-v1,2b early.
> >
> > I checked that the official name of this board is "VisionFive 2". The
> > board has version A and version B, which are different in gmac and phy
> > chip. The version A board has one 1000M and one 100M Ethernet ports
> > while the version B board has two 1000M Ethernet ports. In dts, they
> > have different configuration parameters for gmac. So I would like to
> > distinguish them by two compatibles as below in the next version.
> >
> > - items:
> > - enum:
> > - starfive,visionfive-2-va
> > - starfive,visionfive-2-vb
> > - const: starfive,jh7110
>
> Cool. Though the silkscreen on my board says "VisionFive 2 V1.2B" so I
> think it would be less confusing if you used that as the model, and
> "starfive,visionfive-2-v1.2b" as the compatible string for the board.
As far as I know, VisionFive 2 V1.3B is coming and all version B boards
use the same configuration. It's unnecessary to add the detailed number
of PCB version.
>
>
> > Best regards,
> > Hal
> >
> > >
> > > > + - const: starfive,jh7110
> > > > +
> > > > additionalProperties: true
> >
On Thu, 24 Nov 2022 at 06:56, Hal Feng <[email protected]> wrote:
>
> On Sat, 19 Nov 2022 01:28:48 +0800, Emil Renner Berthing wrote:
> > On Fri, 18 Nov 2022 at 02:17, Hal Feng <[email protected]> wrote:
> > >
> > > From: Emil Renner Berthing <[email protected]>
> > >
> > > Add device tree bindings for the StarFive JH7110 RISC-V SoC [1]
> > > and the VisionFive2 board [2] equipped with it.
> > >
> > > [1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> > > [2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> > >
> > > Signed-off-by: Emil Renner Berthing <[email protected]>
> > > Signed-off-by: Hal Feng <[email protected]>
> > > ---
> > > Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > index 5b36243fd674..64008c57e31f 100644
> > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > @@ -22,6 +22,10 @@ properties:
> > > - const: beagle,beaglev-starlight-jh7100-r0
> > > - const: starfive,jh7100
> > >
> > > + - items:
> > > + - const: starfive,visionfive-v2
> >
> > I think StarFive has switched to just calling it VisionFive 2 and not
> > V2. Please check up on this before committing to the compatible
> > string.
> >
> > Also there are going to be different revisions of the VisionFive 2
> > board, so maybe consider adding eg. starfive,visionfive-2-v1.1 and
> > starfive,visionfive-2-v1,2b early.
>
> I checked that the official name of this board is "VisionFive 2". The
> board has version A and version B, which are different in gmac and phy
> chip. The version A board has one 1000M and one 100M Ethernet ports
> while the version B board has two 1000M Ethernet ports. In dts, they
> have different configuration parameters for gmac. So I would like to
> distinguish them by two compatibles as below in the next version.
>
> - items:
> - enum:
> - starfive,visionfive-2-va
> - starfive,visionfive-2-vb
> - const: starfive,jh7110
Cool. Though the silkscreen on my board says "VisionFive 2 V1.2B" so I
think it would be less confusing if you used that as the model, and
"starfive,visionfive-2-v1.2b" as the compatible string for the board.
> Best regards,
> Hal
>
> >
> > > + - const: starfive,jh7110
> > > +
> > > additionalProperties: true
>
On Fri, Dec 02, 2022 at 10:00:35AM -0800, Palmer Dabbelt wrote:
> On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:
> > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
> >
> > Reviewed-by: Conor Dooley <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > arch/riscv/configs/defconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index 05fd5fcf24f9..a23d022974ad 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
> > CONFIG_INPUT_MOUSEDEV=y
> > CONFIG_SERIAL_8250=y
> > CONFIG_SERIAL_8250_CONSOLE=y
> > +CONFIG_SERIAL_8250_DW=y
> > CONFIG_SERIAL_OF_PLATFORM=y
> > CONFIG_VIRTIO_CONSOLE=y
> > CONFIG_HW_RANDOM=y
>
> Acked-by: Palmer Dabbelt <[email protected]>
Hey Palmer, could you take this as v6.2 material instead of Acking it
please? It applies to the jh7100 stuff that's already in-tree.
Thanks!
On Fri, 02 Dec 2022 10:07:33 PST (-0800), Conor Dooley wrote:
> On Fri, Dec 02, 2022 at 10:00:35AM -0800, Palmer Dabbelt wrote:
>> On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:
>> > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
>> > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
>> >
>> > Reviewed-by: Conor Dooley <[email protected]>
>> > Signed-off-by: Hal Feng <[email protected]>
>> > ---
>> > arch/riscv/configs/defconfig | 1 +
>> > 1 file changed, 1 insertion(+)
>> >
>> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
>> > index 05fd5fcf24f9..a23d022974ad 100644
>> > --- a/arch/riscv/configs/defconfig
>> > +++ b/arch/riscv/configs/defconfig
>> > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
>> > CONFIG_INPUT_MOUSEDEV=y
>> > CONFIG_SERIAL_8250=y
>> > CONFIG_SERIAL_8250_CONSOLE=y
>> > +CONFIG_SERIAL_8250_DW=y
>> > CONFIG_SERIAL_OF_PLATFORM=y
>> > CONFIG_VIRTIO_CONSOLE=y
>> > CONFIG_HW_RANDOM=y
>>
>> Acked-by: Palmer Dabbelt <[email protected]>
>
> Hey Palmer, could you take this as v6.2 material instead of Acking it
> please? It applies to the jh7100 stuff that's already in-tree.
Ya, no problem. Just this patch, or the whole series?
On Fri, 02 Dec 2022 10:18:21 PST (-0800), Conor Dooley wrote:
> On Fri, Dec 02, 2022 at 10:13:40AM -0800, Palmer Dabbelt wrote:
>> On Fri, 02 Dec 2022 10:07:33 PST (-0800), Conor Dooley wrote:
>> > On Fri, Dec 02, 2022 at 10:00:35AM -0800, Palmer Dabbelt wrote:
>> > > On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:
>> > > > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
>> > > > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
>> > > > > Reviewed-by: Conor Dooley <[email protected]>
>> > > > Signed-off-by: Hal Feng <[email protected]>
>> > > > ---
>> > > > arch/riscv/configs/defconfig | 1 +
>> > > > 1 file changed, 1 insertion(+)
>> > > > > diff --git a/arch/riscv/configs/defconfig
>> > > b/arch/riscv/configs/defconfig
>> > > > index 05fd5fcf24f9..a23d022974ad 100644
>> > > > --- a/arch/riscv/configs/defconfig
>> > > > +++ b/arch/riscv/configs/defconfig
>> > > > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
>> > > > CONFIG_INPUT_MOUSEDEV=y
>> > > > CONFIG_SERIAL_8250=y
>> > > > CONFIG_SERIAL_8250_CONSOLE=y
>> > > > +CONFIG_SERIAL_8250_DW=y
>> > > > CONFIG_SERIAL_OF_PLATFORM=y
>> > > > CONFIG_VIRTIO_CONSOLE=y
>> > > > CONFIG_HW_RANDOM=y
>> > >
>> > > Acked-by: Palmer Dabbelt <[email protected]>
>> >
>> > Hey Palmer, could you take this as v6.2 material instead of Acking it
>> > please? It applies to the jh7100 stuff that's already in-tree.
>>
>> Ya, no problem. Just this patch, or the whole series?
>
> Just this one defconfig patch please, the rest is not ready.
> Sorry that that was not clear,
No problem. It's staged, it'll end up on for-next when it builds (it's
behind some other stuff right now).
On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:
> Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> StarFive JH7110 and JH7100 SoCs to boot with serial ports.
>
> Reviewed-by: Conor Dooley <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> arch/riscv/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 05fd5fcf24f9..a23d022974ad 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
> CONFIG_INPUT_MOUSEDEV=y
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_DW=y
> CONFIG_SERIAL_OF_PLATFORM=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
Acked-by: Palmer Dabbelt <[email protected]>
On Fri, Dec 02, 2022 at 10:13:40AM -0800, Palmer Dabbelt wrote:
> On Fri, 02 Dec 2022 10:07:33 PST (-0800), Conor Dooley wrote:
> > On Fri, Dec 02, 2022 at 10:00:35AM -0800, Palmer Dabbelt wrote:
> > > On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:
> > > > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> > > > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
> > > > > Reviewed-by: Conor Dooley <[email protected]>
> > > > Signed-off-by: Hal Feng <[email protected]>
> > > > ---
> > > > arch/riscv/configs/defconfig | 1 +
> > > > 1 file changed, 1 insertion(+)
> > > > > diff --git a/arch/riscv/configs/defconfig
> > > b/arch/riscv/configs/defconfig
> > > > index 05fd5fcf24f9..a23d022974ad 100644
> > > > --- a/arch/riscv/configs/defconfig
> > > > +++ b/arch/riscv/configs/defconfig
> > > > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
> > > > CONFIG_INPUT_MOUSEDEV=y
> > > > CONFIG_SERIAL_8250=y
> > > > CONFIG_SERIAL_8250_CONSOLE=y
> > > > +CONFIG_SERIAL_8250_DW=y
> > > > CONFIG_SERIAL_OF_PLATFORM=y
> > > > CONFIG_VIRTIO_CONSOLE=y
> > > > CONFIG_HW_RANDOM=y
> > >
> > > Acked-by: Palmer Dabbelt <[email protected]>
> >
> > Hey Palmer, could you take this as v6.2 material instead of Acking it
> > please? It applies to the jh7100 stuff that's already in-tree.
>
> Ya, no problem. Just this patch, or the whole series?
Just this one defconfig patch please, the rest is not ready.
Sorry that that was not clear,
Conor.
On Fri, 02 Dec 2022 11:00:17 PST (-0800), [email protected] wrote:
> Hello:
>
> This series was applied to riscv/linux.git (for-next)
> by Palmer Dabbelt <[email protected]>:
>
> On Fri, 18 Nov 2022 09:17:06 +0800 you wrote:
>> The original patch series "Basic StarFive JH7110 RISC-V SoC support" [1]
>> is split into 3 patch series. They respectively add basic clock&reset,
>> pinctrl and device tree support for StarFive JH7110 SoC. These patch
>> series are independent, but the Visionfive2 board can boot up successfully
>> only if all these patches series applied. This one adds basic device
>> tree support. This patch series is pulled out from the patch 1~6 and
>> patch 27~30 of v1 [1]. You can simply get or review the patches at the
>> link [2].
>>
>> [...]
>
> Here is the summary with links:
> - [v2,1/8] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive2 board
> (no matching commit)
> - [v2,2/8] dt-bindings: timer: Add StarFive JH7110 clint
> (no matching commit)
> - [v2,3/8] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> (no matching commit)
> - [v2,4/8] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
> (no matching commit)
> - [v2,5/8] soc: sifive: ccache: Add StarFive JH7110 support
> (no matching commit)
> - [v2,6/8] riscv: dts: starfive: Add initial StarFive JH7110 device tree
> (no matching commit)
> - [v2,7/8] riscv: dts: starfive: Add StarFive JH7110 VisionFive2 board device tree
> (no matching commit)
> - [v2,8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
> https://git.kernel.org/riscv/c/6925ba3d9b8c
>
> You are awesome, thank you!
Looks like the bot is a little confused here, it's just that last patch
that's been merged.
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:
On Fri, 18 Nov 2022 09:17:06 +0800 you wrote:
> The original patch series "Basic StarFive JH7110 RISC-V SoC support" [1]
> is split into 3 patch series. They respectively add basic clock&reset,
> pinctrl and device tree support for StarFive JH7110 SoC. These patch
> series are independent, but the Visionfive2 board can boot up successfully
> only if all these patches series applied. This one adds basic device
> tree support. This patch series is pulled out from the patch 1~6 and
> patch 27~30 of v1 [1]. You can simply get or review the patches at the
> link [2].
>
> [...]
Here is the summary with links:
- [v2,1/8] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive2 board
(no matching commit)
- [v2,2/8] dt-bindings: timer: Add StarFive JH7110 clint
(no matching commit)
- [v2,3/8] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
(no matching commit)
- [v2,4/8] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
(no matching commit)
- [v2,5/8] soc: sifive: ccache: Add StarFive JH7110 support
(no matching commit)
- [v2,6/8] riscv: dts: starfive: Add initial StarFive JH7110 device tree
(no matching commit)
- [v2,7/8] riscv: dts: starfive: Add StarFive JH7110 VisionFive2 board device tree
(no matching commit)
- [v2,8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
https://git.kernel.org/riscv/c/6925ba3d9b8c
You are awesome, thank you!
--
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https://korg.docs.kernel.org/patchwork/pwbot.html
On Fri, 18 Nov 2022 09:17:14 +0800, Hal Feng wrote:
> Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> StarFive JH7110 and JH7100 SoCs to boot with serial ports.
>
>
Applied, thanks!
[8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
https://git.kernel.org/palmer/c/6925ba3d9b8c
Best regards,
--
Palmer Dabbelt <[email protected]>
On Fri, 02 Dec 2022 10:43:06 -0800, Palmer Dabbelt wrote:
> On Fri, 18 Nov 2022 09:17:14 +0800, Hal Feng wrote:
> > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
> >
> >
>
> Applied, thanks!
Thank you so much!
Best regards,
Hal
>
> [8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
> https://git.kernel.org/palmer/c/6925ba3d9b8c