2021-06-03 14:28:22

by Grzegorz Szymaszek

Subject: [PATCH] ARM: dts: stm32: set stm32mp157c-odyssey DCMI pins

The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output.
stm32mp15-pinctrl.dtsi contains one pin state definition for the DCMI
interface, dcmi-0, AKA phandle dcmi_pins_a. This definition is
incompatible with the pins used on the Odyssey board, where:
- there are 8 data pins instead of 12,
- DCMI_HSYNC is available at PA4 instead of PH8,
- DCMI_D0 is at PC6 instead of PH9,
- DCMI_D3 is at PE1 instead of PH12,
- DCMI_D4 is at PE11 instead of PH14,
- DCMI_D5 is at PD3 instead of PI4,
- DCMI_D6 is at PE13 instead of PB8,
- DCMI_D7 is at PB9 instead of PE6.

Override the dcmi_pins_a definition (as well as dcmi_sleep_pins_a) in
the Odyssey device tree.

Signed-off-by: Grzegorz Szymaszek <[email protected]>
---
arch/arm/boot/dts/stm32mp157c-odyssey.dts | 32 +++++++++++++++++++++++
1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
index be1dd5e9e744..2d6cf70ca623 100644
--- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
@@ -22,6 +22,38 @@ chosen {
};
};

+&dcmi_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
+ };
+};
+
+&dcmi_sleep_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
+ };
+};
+
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
--
2.30.2

2021-06-03 14:29:24

by Ahmad Fatoum

Subject: Re: [PATCH] ARM: dts: stm32: set stm32mp157c-odyssey DCMI pins

Hello Grzegorz,

On 03.06.21 16:23, Grzegorz Szymaszek wrote:
> The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output.
> stm32mp15-pinctrl.dtsi contains one pin state definition for the DCMI
> interface, dcmi-0, AKA phandle dcmi_pins_a. This definition is
> incompatible with the pins used on the Odyssey board, where:
> - there are 8 data pins instead of 12,
> - DCMI_HSYNC is available at PA4 instead of PH8,
> - DCMI_D0 is at PC6 instead of PH9,
> - DCMI_D3 is at PE1 instead of PH12,
> - DCMI_D4 is at PE11 instead of PH14,
> - DCMI_D5 is at PD3 instead of PI4,
> - DCMI_D6 is at PE13 instead of PB8,
> - DCMI_D7 is at PB9 instead of PE6.
>
> Override the dcmi_pins_a definition (as well as dcmi_sleep_pins_a) in
> the Odyssey device tree.

Rather define a new pinctrl group (e.g. &dcmi_pins_b) and use that
instead of overriding an existing one.

Current convention is also to place all STM32MP1 pinctrl nodes into
a central file, not in the individual board device trees.

Cheers,
Ahmad

>
> Signed-off-by: Grzegorz Szymaszek <[email protected]>
> ---
> arch/arm/boot/dts/stm32mp157c-odyssey.dts | 32 +++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
> index be1dd5e9e744..2d6cf70ca623 100644
> --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts
> +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
> @@ -22,6 +22,38 @@ chosen {
> };
> };
>
> +&dcmi_pins_a {
> + pins {
> + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
> + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
> + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
> + <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
> + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
> + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
> + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
> + <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
> + <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
> + <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
> + <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
> + };
> +};
> +
> +&dcmi_sleep_pins_a {
> + pins {
> + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
> + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
> + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
> + <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
> + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
> + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
> + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
> + <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
> + <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
> + <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
> + <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
> + };
> +};
> +
> &ethernet0 {
> status = "okay";
> pinctrl-0 = <&ethernet0_rgmii_pins_a>;
>

--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

2021-06-03 14:53:15

by Grzegorz Szymaszek

Subject: Re: [PATCH] ARM: dts: stm32: set stm32mp157c-odyssey DCMI pins

Hello Ahmad,

On Thu, Jun 03, 2021 at 04:26:59PM +0200, Ahmad Fatoum wrote:
> On 03.06.21 16:23, Grzegorz Szymaszek wrote:
> > The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output.
> > stm32mp15-pinctrl.dtsi contains one pin state definition for the DCMI
> > interface, dcmi-0, AKA phandle dcmi_pins_a. This definition is
> > incompatible with the pins used on the Odyssey board, where:
> > - there are 8 data pins instead of 12,
> > - […]
> >
> > Override the dcmi_pins_a definition (as well as dcmi_sleep_pins_a) in
> > the Odyssey device tree.
>
> Rather define a new pinctrl group (e.g. &dcmi_pins_b) and use that
> instead of overriding an existing one.

Can I simply use dcmi_pins_b (as the first unused identifier) or is
there some way to match specific pin groups to an identifier (b, c, d,
and so on)?

> Current convention is also to place all STM32MP1 pinctrl nodes into
> a central file, not in the individual board device trees.

Sure, I will update the patch.

Thanks for your comments!

--
Grzegorz

2021-06-03 15:01:26

by Ahmad Fatoum

Subject: Re: [PATCH] ARM: dts: stm32: set stm32mp157c-odyssey DCMI pins

On 03.06.21 16:49, Grzegorz Szymaszek wrote:
> Hello Ahmad,
>
> On Thu, Jun 03, 2021 at 04:26:59PM +0200, Ahmad Fatoum wrote:
>> On 03.06.21 16:23, Grzegorz Szymaszek wrote:
>>> The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output.
>>> stm32mp15-pinctrl.dtsi contains one pin state definition for the DCMI
>>> interface, dcmi-0, AKA phandle dcmi_pins_a. This definition is
>>> incompatible with the pins used on the Odyssey board, where:
>>> - there are 8 data pins instead of 12,
>>> - […]
>>>
>>> Override the dcmi_pins_a definition (as well as dcmi_sleep_pins_a) in
>>> the Odyssey device tree.
>>
>> Rather define a new pinctrl group (e.g. &dcmi_pins_b) and use that
>> instead of overriding an existing one.
>
> Can I simply use dcmi_pins_b (as the first unused identifier) or is
> there some way to match specific pin groups to an identifier (b, c, d,
> and so on)?

Just take the next available. That's how I did it so far.

>> Current convention is also to place all STM32MP1 pinctrl nodes into
>> a central file, not in the individual board device trees.
>
> Sure, I will update the patch.
>
> Thanks for your comments!

Cheers,
Ahmad

--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

2021-06-03 15:37:00

by Grzegorz Szymaszek

Subject: [PATCH v2] ARM: dts: stm32: add a new DCMI pins group

The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output.
stm32mp15-pinctrl.dtsi contained one pin state definition for the DCMI
interface, dcmi-0, AKA phandle dcmi_pins_a. This definition was
incompatible with the pins used on the Odyssey board, where:
- there are 8 data pins instead of 12,
- DCMI_HSYNC is available at PA4 instead of PH8,
- DCMI_D0 is at PC6 instead of PH9,
- DCMI_D3 is at PE1 instead of PH12,
- DCMI_D4 is at PE11 instead of PH14,
- DCMI_D5 is at PD3 instead of PI4,
- DCMI_D6 is at PE13 instead of PB8,
- DCMI_D7 is at PB9 instead of PE6.

Add the DCMI pins used on the Odyssey board as a new DCMI pin state
definition, dcmi-1, AKA phandle dcmi_pins_b.

Signed-off-by: Grzegorz Szymaszek <[email protected]>
---
V1 -> V2: Removed the pinctrl override from the Odyssey device tree,
added a new pinctrl in stm32mp15-pinctrl.dtsi instead

arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 33 ++++++++++++++++++++++++
1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index 060baa8b7e9d..5b60ecbd718f 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -118,6 +118,39 @@ pins {
};
};

+ dcmi_pins_b: dcmi-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_b: dcmi-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
+ };
+ };
+
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
--
2.30.2

2021-06-10 13:37:31

by Alexandre TORGUE

Subject: Re: [PATCH v2] ARM: dts: stm32: add a new DCMI pins group

Hi

On 6/3/21 5:34 PM, Grzegorz Szymaszek wrote:
> The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output.
> stm32mp15-pinctrl.dtsi contained one pin state definition for the DCMI
> interface, dcmi-0, AKA phandle dcmi_pins_a. This definition was
> incompatible with the pins used on the Odyssey board, where:
> - there are 8 data pins instead of 12,
> - DCMI_HSYNC is available at PA4 instead of PH8,
> - DCMI_D0 is at PC6 instead of PH9,
> - DCMI_D3 is at PE1 instead of PH12,
> - DCMI_D4 is at PE11 instead of PH14,
> - DCMI_D5 is at PD3 instead of PI4,
> - DCMI_D6 is at PE13 instead of PB8,
> - DCMI_D7 is at PB9 instead of PE6.
>
> Add the DCMI pins used on the Odyssey board as a new DCMI pin state
> definition, dcmi-1, AKA phandle dcmi_pins_b.
>
> Signed-off-by: Grzegorz Szymaszek <[email protected]>
> ---
> V1 -> V2: Removed the pinctrl override from the Odyssey device tree,
> added a new pinctrl in stm32mp15-pinctrl.dtsi instead
>
> arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 33 ++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>

Applied on stm32-next. I just updated the commit title by
"ARM: dts: stm32: add a new DCMI pins group on stm32mp15"

Thanks.
Alex


> diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> index 060baa8b7e9d..5b60ecbd718f 100644
> --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> @@ -118,6 +118,39 @@ pins {
> };
> };
>
> + dcmi_pins_b: dcmi-1 {
> + pins {
> + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
> + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
> + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
> + <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
> + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
> + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
> + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
> + <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
> + <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
> + <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
> + <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
> + bias-disable;
> + };
> + };
> +
> + dcmi_sleep_pins_b: dcmi-sleep-1 {
> + pins {
> + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
> + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
> + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
> + <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
> + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
> + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
> + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
> + <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
> + <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
> + <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
> + <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
> + };
> + };
> +
> ethernet0_rgmii_pins_a: rgmii-0 {
> pins1 {
> pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
>