by Jonathan McDowell

[permalink] [raw]

Subject: Re: [PATCH v2 00/18] Multiple addition to ipq8064 dtsi

On Fri, Feb 18, 2022 at 01:29:38AM +0100, Ansuel Smith wrote:
> This try to complete the ipq8064 dtsi and introduce 2 new dtsi
> ipq8064-v2 and ipq8065. While some node are still missing (cpufreq node,
> l2 scale node, fab scale node) this would add most of the missing node
> to make ipq8064 actually usable.
>
> Some of the changes are the fix for the pci IO that cause any secondary
> wifi card with ath10k to fail init.
> Adds regulators definition for RPM.
> Adds many missing gsbi nodes used by all the devices.
> Enable the usb phy by default as they are actually enabled internally by
> xlate only if the dwc3 driver is used.
> Add opp table and declare idle state for ipq8064.
> Fix some dtc warning.
>
> This also add the ipq8064-v2.0 dtsi and the ipq8065 dtsi used by more
> recent devices based on this SoC.

A couple of comments directly on 2 patches, but otherwise for the set:

Tested-by: Jonathan McDowell <[email protected]>

> v2:
> - Added missing patch
> - Added additional gsbi6 spi
> - Added extra description for L2 cache opp
> - Fxied smb208 enabled by default that is problematic for rb3011 devices
>
> Ansuel Smith (18):
> ARM: dts: qcom: add multiple missing pin definition for ipq8064
> ARM: dts: qcom: add gsbi6 missing definition for ipq8064
> ARM: dts: qcom: add missing rpm regulators and cells for ipq8064
> ARM: dts: qcom: disable smb208 regulators for ipq8064-rb3011
> ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064
> ARM: dts: qcom: enable usb phy by default for ipq8064
> ARM: dts: qcom: reduce pci IO size to 64K for ipq8064
> ARM: dts: qcom: fix dtc warning for missing #address-cells for ipq8064
> ARM: dts: qcom: add smem node for ipq8064
> ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064
> ARM: dts: qcom: add sic non secure node for ipq8064
> ARM: dts: qcom: fix and add some missing gsbi node for ipq8064
> ARM: dts: qcom: add opp table for cpu and l2 for ipq8064
> ARM: dts: qcom: add speedbin efuse nvmem binding
> ARM: dts: qcom: add multiple missing binding for cpu and l2 for
> ipq8064
> ARM: dts: qcom: remove redundant binding from ipq8064 rb3011 dts
> ARM: dts: qcom: add ipq8064-v2.0 dtsi
> ARM: dts: qcom: add ipq8065 dtsi
>
> arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 21 +-
> arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 70 ++++
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 375 +++++++++++++++++++++-
> arch/arm/boot/dts/qcom-ipq8065.dtsi | 168 ++++++++++
> 4 files changed, 603 insertions(+), 31 deletions(-)
> create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
> create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi
>
> --
> 2.34.1
>

J.

--
"evilwm - we sold our souls to the window manager" --
http://www.6809.org.uk/evilwm/

2022-02-25 06:49:33

by Christian Marangi

[permalink] [raw]

Subject: Re: [PATCH v2 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064

On Tue, Feb 22, 2022 at 08:01:41PM +0000, Jonathan McDowell wrote:
> On Fri, Feb 18, 2022 at 01:29:48AM +0100, Ansuel Smith wrote:
> > Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
> > Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
> > for the secondary mux.
> >
> > Signed-off-by: Ansuel Smith <[email protected]>
> > ---
> > arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
> > 1 file changed, 32 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > index c579fb09e768..7df1c1482220 100644
> > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > @@ -298,6 +298,12 @@ smem: smem@41000000 {
> > };
> >
> > clocks {
> > + qsb: qsb {
> > + compatible = "fixed-clock";
> > + clock-frequency = <384000000>;
> > + #clock-cells = <0>;
> > + };
> > +
> > cxo_board {
> > compatible = "fixed-clock";
> > #clock-cells = <0>;
> > @@ -504,11 +510,19 @@ IRQ_TYPE_EDGE_RISING)>,
> > acc0: clock-controller@2088000 {
> > compatible = "qcom,kpss-acc-v1";
> > reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
> > + clock-output-names = "acpu0_aux";
> > + clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
>
> You need to add the pxo_board: label to the clock above or we get:
>
> arch/arm/boot/dts/qcom-ipq8064.dtsi:645.34-652.5: ERROR (phandle_references): /soc/clock-controller@2088000: Reference to non-existent node or label "pxo_board"
>
> arch/arm/boot/dts/qcom-ipq8064.dtsi:654.34-661.5: ERROR (phandle_references): /soc/clock-controller@2098000: Reference to non-existent node or label "pxo_board"
>

There is another series that introduce the label. Ideally it should be
merged before this. It's almost all reviewed so we should be good.

> > + clock-names = "pll8_vote", "pxo";
> > + #clock-cells = <0>;
> > };
> >
> > acc1: clock-controller@2098000 {
> > compatible = "qcom,kpss-acc-v1";
> > reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
> > + clock-output-names = "acpu1_aux";
> > + clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
> > + clock-names = "pll8_vote", "pxo";
> > + #clock-cells = <0>;
> > };
> >
> > adm_dma: dma-controller@18300000 {
> > @@ -532,17 +546,23 @@ adm_dma: dma-controller@18300000 {
> > };
> >
> > saw0: regulator@2089000 {
> > - compatible = "qcom,saw2";
> > + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
> > reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
> > regulator;
> > };
> >
> > saw1: regulator@2099000 {
> > - compatible = "qcom,saw2";
> > + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
> > reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
> > regulator;
> > };
> >
> > + saw_l2: regulator@02012000 {
> > + compatible = "qcom,saw2", "syscon";
> > + reg = <0x02012000 0x1000>;
> > + regulator;
> > + };
> > +
> > gsbi2: gsbi@12480000 {
> > compatible = "qcom,gsbi-v1.0.0";
> > cell-index = <2>;
> > @@ -899,6 +919,16 @@ l2cc: clock-controller@2011000 {
> > clock-output-names = "acpu_l2_aux";
> > };
> >
> > + kraitcc: clock-controller {
> > + compatible = "qcom,krait-cc-v1";
> > + clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
> > + <&acc0>, <&acc1>, <&l2cc>, <&qsb>;
> > + clock-names = "hfpll0", "hfpll1", "hfpll_l2",
> > + "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
> > + "qsb";
> > + #clock-cells = <1>;
> > + };
> > +
> > lcc: clock-controller@28000000 {
> > compatible = "qcom,lcc-ipq8064";
> > reg = <0x28000000 0x1000>;
> > --
> > 2.34.1
> >
>
> J.
>
> --
> Hats off to the insane. | .''`. Debian GNU/Linux Developer
> | : :' : Happy to accept PGP signed
> | `. `' or encrypted mail - RSA
> | `- key on the keyservers.

--
Ansuel