AMD processors based on Zen 2 and later microarchitectures do not
support PMCx087 (instruction pipe stalls) which is used as the backing
event for "stalled-cycles-frontend" and "stalled-cycles-backend". Use
PMCx0A9 (cycles where micro-op queue is empty) instead to count frontend
stalls and remove the entry for backend stalls since there is no direct
replacement.
Signed-off-by: Sandipan Das <[email protected]>
---
arch/x86/events/amd/core.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index aec16e581f5b..afe4a809f2ed 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
/*
* AMD Performance Monitor Family 17h and later:
*/
-static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
+static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =
{
[PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
@@ -262,10 +262,24 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187,
};
+static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
+{
+ [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
+ [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
+ [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
+ [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
+};
+
static u64 amd_pmu_event_map(int hw_event)
{
- if (boot_cpu_data.x86 >= 0x17)
- return amd_f17h_perfmon_event_map[hw_event];
+ if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
+ return amd_zen2_perfmon_event_map[hw_event];
+
+ if (cpu_feature_enabled(X86_FEATURE_ZEN1))
+ return amd_zen1_perfmon_event_map[hw_event];
return amd_perfmon_event_map[hw_event];
}
--
2.34.1
On Mon, Mar 25, 2024 at 12:48 AM Sandipan Das <[email protected]> wrote:
>
> AMD processors based on Zen 2 and later microarchitectures do not
> support PMCx087 (instruction pipe stalls) which is used as the backing
> event for "stalled-cycles-frontend" and "stalled-cycles-backend". Use
> PMCx0A9 (cycles where micro-op queue is empty) instead to count frontend
> stalls and remove the entry for backend stalls since there is no direct
> replacement.
>
> Signed-off-by: Sandipan Das <[email protected]>
This looks good to me. Should there be a Fixes tag for the sake of backports?
Reviewed-by: Ian Rogers <[email protected]>
Thanks,
Ian
> ---
> arch/x86/events/amd/core.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index aec16e581f5b..afe4a809f2ed 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
> /*
> * AMD Performance Monitor Family 17h and later:
> */
> -static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
> +static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =
> {
> [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
> [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
> @@ -262,10 +262,24 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
> [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187,
> };
>
> +static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
> +{
> + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
> + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
> + [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
> + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
> + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
> + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
> + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
> +};
> +
> static u64 amd_pmu_event_map(int hw_event)
> {
> - if (boot_cpu_data.x86 >= 0x17)
> - return amd_f17h_perfmon_event_map[hw_event];
> + if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
> + return amd_zen2_perfmon_event_map[hw_event];
> +
> + if (cpu_feature_enabled(X86_FEATURE_ZEN1))
> + return amd_zen1_perfmon_event_map[hw_event];
>
> return amd_perfmon_event_map[hw_event];
> }
> --
> 2.34.1
>
On 3/25/2024 8:04 PM, Ian Rogers wrote:
> On Mon, Mar 25, 2024 at 12:48 AM Sandipan Das <[email protected]> wrote:
>>
>> AMD processors based on Zen 2 and later microarchitectures do not
>> support PMCx087 (instruction pipe stalls) which is used as the backing
>> event for "stalled-cycles-frontend" and "stalled-cycles-backend". Use
>> PMCx0A9 (cycles where micro-op queue is empty) instead to count frontend
>> stalls and remove the entry for backend stalls since there is no direct
>> replacement.
>>
>> Signed-off-by: Sandipan Das <[email protected]>
>
> This looks good to me. Should there be a Fixes tag for the sake of backports?
>
My bad. Yes, there should a fixes tag.
Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h")
Ingo, I see that you have already pushed this to the perf/urgent branch.
Should I send a v2?
> Reviewed-by: Ian Rogers <[email protected]>
>
> Thanks,
> Ian
>
>> ---
>> arch/x86/events/amd/core.c | 20 +++++++++++++++++---
>> 1 file changed, 17 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
>> index aec16e581f5b..afe4a809f2ed 100644
>> --- a/arch/x86/events/amd/core.c
>> +++ b/arch/x86/events/amd/core.c
>> @@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> /*
>> * AMD Performance Monitor Family 17h and later:
>> */
>> -static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> +static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> {
>> [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
>> [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
>> @@ -262,10 +262,24 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187,
>> };
>>
>> +static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> +{
>> + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
>> + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
>> + [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
>> + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
>> + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
>> + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
>> + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
>> +};
>> +
>> static u64 amd_pmu_event_map(int hw_event)
>> {
>> - if (boot_cpu_data.x86 >= 0x17)
>> - return amd_f17h_perfmon_event_map[hw_event];
>> + if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
>> + return amd_zen2_perfmon_event_map[hw_event];
>> +
>> + if (cpu_feature_enabled(X86_FEATURE_ZEN1))
>> + return amd_zen1_perfmon_event_map[hw_event];
>>
>> return amd_perfmon_event_map[hw_event];
>> }
>> --
>> 2.34.1
>>
* Sandipan Das <[email protected]> wrote:
> On 3/25/2024 8:04 PM, Ian Rogers wrote:
> > On Mon, Mar 25, 2024 at 12:48 AM Sandipan Das <[email protected]> wrote:
> >>
> >> AMD processors based on Zen 2 and later microarchitectures do not
> >> support PMCx087 (instruction pipe stalls) which is used as the backing
> >> event for "stalled-cycles-frontend" and "stalled-cycles-backend". Use
> >> PMCx0A9 (cycles where micro-op queue is empty) instead to count frontend
> >> stalls and remove the entry for backend stalls since there is no direct
> >> replacement.
> >>
> >> Signed-off-by: Sandipan Das <[email protected]>
> >
> > This looks good to me. Should there be a Fixes tag for the sake of backports?
> >
>
> My bad. Yes, there should a fixes tag.
>
> Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h")
>
> Ingo, I see that you have already pushed this to the perf/urgent branch.
> Should I send a v2?
That's OK, no need, I've amended the commits in perf/urgent. 2019 is quite
a way back for a Fixes tag though. :-)
Thanks,
Ingo