This patch series adds support for the second version of the Marvell
hardware overlay for the Cadence xSPI IP block. The overlay is a hardware
change made around the original xSPI block. It extends xSPI features with
clock configuration, interrupt masking, and full-duplex, variable-length SPI
operations.
These functionalities allow the xSPI block to operate not only with memory
devices but also with simple SPI devices and TPM devices.
Changes:
v8:
Rename xferbase to xfer
Rework DLL reset, to return non inverted boolean value
Rework STIG and SDMA status check, to return non inverted boolean value
v7:
Rebase patches to latest sources, changes in "Allow to read basic xSPI configuration
from ACPI"
Removed bugfix, as it was integrated to next tree from v6
v6:
Fix item order in cdns,xspi.yaml
v5:
Rework cdns,xspi.yaml file
Reword commit messages
Move mamory mapping to ACPI patch
Use devm_platform_ioremap_resource instead of two step mapping
v4:
Rename new Marvell registers to keep naming conventions
Rename mrvl,xspi-nor to marvell,cnxx,xspi-nor
Various fixed for cdns,xspi.yaml file:
- Remove unnecesary parameters
- Link register xferbase with marvell,cn10-xspi-nor
- Move default values to .c file from device-tree
Clock configuration optimization
ACPI fixes:
- Remove incorrect ACPI match table
Added .data field to device_id, fixes for matching in ACPI and dtb case
Minor style comment changes
v3:
Removed all kconfig changes
Added device-tree mrvl,xspi-nor tag
v2:
Support for second overlay iteration
v1:
-
v0:
Initial support for v1 overlay
Piyush Malgujar (1):
spi: cadence: Allow to read basic xSPI configuration from ACPI
Witold Sadowski (3):
spi: dt-bindings: cadence: Add Marvell overlay bindings documentation
for Cadence XSPI
spi: cadence: Add Marvell xSPI IP overlay changes
spi: cadence: Add MRVL overlay xfer operation support
.../devicetree/bindings/spi/cdns,xspi.yaml | 32 +-
drivers/spi/spi-cadence-xspi.c | 603 +++++++++++++++++-
2 files changed, 620 insertions(+), 15 deletions(-)
--
2.43.0
From: Piyush Malgujar <[email protected]>
These changes enable reading the configurations from ACPI tables as
required for successful probing in an ACPI UEFI environment. In the
case of an ACPI-disabled or DTS-based environment, it will continue
to read configurations from DTS as before.
Signed-off-by: Piyush Malgujar <[email protected]>
Signed-off-by: Witold Sadowski <[email protected]>
---
drivers/spi/spi-cadence-xspi.c | 88 +++++++++++++++++++++++++++++++---
1 file changed, 82 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 566db2591d34..36c6c25aaea0 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -2,6 +2,7 @@
// Cadence XSPI flash controller driver
// Copyright (C) 2020-21 Cadence
+#include <linux/acpi.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
@@ -14,6 +15,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/property.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
#include <linux/bitfield.h>
@@ -652,6 +654,67 @@ static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
(dir != SPI_MEM_NO_DATA));
}
+#ifdef CONFIG_ACPI
+static bool cdns_xspi_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct spi_device *spi = mem->spi;
+ const union acpi_object *obj;
+ struct acpi_device *adev;
+
+ adev = ACPI_COMPANION(&spi->dev);
+
+ if (!acpi_dev_get_property(adev, "spi-tx-bus-width", ACPI_TYPE_INTEGER,
+ &obj)) {
+ switch (obj->integer.value) {
+ case 1:
+ break;
+ case 2:
+ spi->mode |= SPI_TX_DUAL;
+ break;
+ case 4:
+ spi->mode |= SPI_TX_QUAD;
+ break;
+ case 8:
+ spi->mode |= SPI_TX_OCTAL;
+ break;
+ default:
+ dev_warn(&spi->dev,
+ "spi-tx-bus-width %lld not supported\n",
+ obj->integer.value);
+ break;
+ }
+ }
+
+ if (!acpi_dev_get_property(adev, "spi-rx-bus-width", ACPI_TYPE_INTEGER,
+ &obj)) {
+ switch (obj->integer.value) {
+ case 1:
+ break;
+ case 2:
+ spi->mode |= SPI_RX_DUAL;
+ break;
+ case 4:
+ spi->mode |= SPI_RX_QUAD;
+ break;
+ case 8:
+ spi->mode |= SPI_RX_OCTAL;
+ break;
+ default:
+ dev_warn(&spi->dev,
+ "spi-rx-bus-width %lld not supported\n",
+ obj->integer.value);
+ break;
+ }
+ }
+
+ if (!spi_mem_default_supports_op(mem, op))
+ return false;
+
+ return true;
+}
+#endif
+
static int cdns_xspi_mem_op_execute(struct spi_mem *mem,
const struct spi_mem_op *op)
{
@@ -675,6 +738,9 @@ static int cdns_xspi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *
}
static const struct spi_controller_mem_ops cadence_xspi_mem_ops = {
+#ifdef CONFIG_ACPI
+ .supports_op = cdns_xspi_supports_op,
+#endif
.exec_op = cdns_xspi_mem_op_execute,
.adjust_op_size = cdns_xspi_adjust_mem_op_size,
};
@@ -726,15 +792,20 @@ static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
{
- struct device_node *node_prop = pdev->dev.of_node;
+ struct fwnode_handle *fwnode_child;
unsigned int cs;
- for_each_available_child_of_node_scoped(node_prop, node_child) {
- if (of_property_read_u32(node_child, "reg", &cs)) {
+ device_for_each_child_node(&pdev->dev, fwnode_child) {
+ if (!fwnode_device_is_available(fwnode_child))
+ continue;
+
+ if (fwnode_property_read_u32(fwnode_child, "reg", &cs)) {
dev_err(&pdev->dev, "Couldn't get memory chip select\n");
+ fwnode_handle_put(fwnode_child);
return -ENXIO;
} else if (cs >= CDNS_XSPI_MAX_BANKS) {
dev_err(&pdev->dev, "reg (cs) parameter value too large\n");
+ fwnode_handle_put(fwnode_child);
return -ENXIO;
}
}
@@ -788,6 +859,11 @@ static int cdns_xspi_probe(struct platform_device *pdev)
SPI_MODE_0 | SPI_MODE_3;
drv_data = of_device_get_match_data(dev);
+ if (!drv_data) {
+ drv_data = acpi_device_get_match_data(dev);
+ if (!drv_data)
+ return -ENODEV;
+ }
host->mem_ops = &cadence_xspi_mem_ops;
host->dev.of_node = pdev->dev.of_node;
@@ -814,19 +890,19 @@ static int cdns_xspi_probe(struct platform_device *pdev)
if (ret)
return -ENODEV;
- cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev, "io");
+ cdns_xspi->iobase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(cdns_xspi->iobase)) {
dev_err(dev, "Failed to remap controller base address\n");
return PTR_ERR(cdns_xspi->iobase);
}
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma");
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
cdns_xspi->sdmabase = devm_ioremap_resource(dev, res);
if (IS_ERR(cdns_xspi->sdmabase))
return PTR_ERR(cdns_xspi->sdmabase);
cdns_xspi->sdmasize = resource_size(res);
- cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev, "aux");
+ cdns_xspi->auxbase = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(cdns_xspi->auxbase)) {
dev_err(dev, "Failed to remap AUX address\n");
return PTR_ERR(cdns_xspi->auxbase);
--
2.43.0
This commit adds support for the basic v2 Marvell overlay block. Key
features included are:
- Clock configuration
- PHY configuration
- Interrupt configuration (enabling)
The clock divider block, built on top of the Cadence xSPI IP,
divides an external 800MHz clock. It supports a limited range of clock
speeds from 6.25MHz to 200MHz.
To manage interrupts correctly, the driver needs to clear both the MSI-X
interrupt bit and the xSPI interrupt bit. Additionally, interrupt
masking must be disabled.
Signed-off-by: Witold Sadowski <[email protected]>
---
drivers/spi/spi-cadence-xspi.c | 270 ++++++++++++++++++++++++++++++++-
1 file changed, 265 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 2e3eacd46b72..566db2591d34 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -193,6 +193,43 @@
((op)->data.dir == SPI_MEM_DATA_IN) ? \
CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE))
+/* PHY default values */
+#define REGS_DLL_PHY_CTRL 0x00000707
+#define CTB_RFILE_PHY_CTRL 0x00004000
+#define RFILE_PHY_TSEL 0x00000000
+#define RFILE_PHY_DQ_TIMING 0x00000101
+#define RFILE_PHY_DQS_TIMING 0x00700404
+#define RFILE_PHY_GATE_LPBK_CTRL 0x00200030
+#define RFILE_PHY_DLL_MASTER_CTRL 0x00800000
+#define RFILE_PHY_DLL_SLAVE_CTRL 0x0000ff01
+
+/* PHY config registers */
+#define CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL 0x1034
+#define CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL 0x0080
+#define CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL 0x0084
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING 0x0000
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING 0x0004
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL 0x0008
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL 0x000c
+#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL 0x0010
+#define CDNS_XSPI_DATASLICE_RFILE_PHY_DLL_OBS_REG_0 0x001c
+
+#define CDNS_XSPI_DLL_RST_N BIT(24)
+#define CDNS_XSPI_DLL_LOCK BIT(0)
+
+/* Marvell overlay registers - clock */
+#define MRVL_XSPI_CLK_CTRL_AUX_REG 0x2020
+#define MRVL_XSPI_CLK_ENABLE BIT(0)
+#define MRVL_XSPI_CLK_DIV GENMASK(4, 1)
+#define MRVL_XSPI_IRQ_ENABLE BIT(6)
+#define MRVL_XSPI_CLOCK_IO_HZ 800000000
+#define MRVL_XSPI_CLOCK_DIVIDED(div) ((MRVL_XSPI_CLOCK_IO_HZ) / (div))
+#define MRVL_DEFAULT_CLK 25000000
+
+/* Marvell overlay registers - MSI-X */
+#define MRVL_XSPI_SPIX_INTR_AUX 0x2000
+#define MRVL_MSIX_CLEAR_IRQ 0x01
+
enum cdns_xspi_stig_instr_type {
CDNS_XSPI_STIG_INSTR_TYPE_0,
CDNS_XSPI_STIG_INSTR_TYPE_1,
@@ -212,6 +249,7 @@ enum cdns_xspi_stig_cmd_dir {
struct cdns_xspi_dev {
struct platform_device *pdev;
struct device *dev;
+ bool mrvl_hw_overlay;
void __iomem *iobase;
void __iomem *auxbase;
@@ -232,6 +270,123 @@ struct cdns_xspi_dev {
u8 hw_num_banks;
};
+struct cdns_xspi_driver_data {
+ bool mrvl_hw_overlay;
+};
+
+static struct cdns_xspi_driver_data mrvl_driver_data = {
+ .mrvl_hw_overlay = true,
+};
+
+static struct cdns_xspi_driver_data cdns_driver_data = {
+ .mrvl_hw_overlay = false,
+};
+
+const int cdns_mrvl_xspi_clk_div_list[] = {
+ 4, //0x0 = Divide by 4. SPI clock is 200 MHz.
+ 6, //0x1 = Divide by 6. SPI clock is 133.33 MHz.
+ 8, //0x2 = Divide by 8. SPI clock is 100 MHz.
+ 10, //0x3 = Divide by 10. SPI clock is 80 MHz.
+ 12, //0x4 = Divide by 12. SPI clock is 66.666 MHz.
+ 16, //0x5 = Divide by 16. SPI clock is 50 MHz.
+ 18, //0x6 = Divide by 18. SPI clock is 44.44 MHz.
+ 20, //0x7 = Divide by 20. SPI clock is 40 MHz.
+ 24, //0x8 = Divide by 24. SPI clock is 33.33 MHz.
+ 32, //0x9 = Divide by 32. SPI clock is 25 MHz.
+ 40, //0xA = Divide by 40. SPI clock is 20 MHz.
+ 50, //0xB = Divide by 50. SPI clock is 16 MHz.
+ 64, //0xC = Divide by 64. SPI clock is 12.5 MHz.
+ 128 //0xD = Divide by 128. SPI clock is 6.25 MHz.
+};
+
+static void cdns_xspi_reset_dll(struct cdns_xspi_dev *cdns_xspi)
+{
+ u32 dll_cntrl = readl(cdns_xspi->iobase +
+ CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+
+ /* Reset DLL */
+ dll_cntrl |= CDNS_XSPI_DLL_RST_N;
+ writel(dll_cntrl, cdns_xspi->iobase +
+ CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+}
+
+static bool cdns_xspi_is_dll_locked(struct cdns_xspi_dev *cdns_xspi)
+{
+ u32 dll_lock;
+
+ return !readl_relaxed_poll_timeout(cdns_xspi->iobase +
+ CDNS_XSPI_INTR_STATUS_REG,
+ dll_lock, ((dll_lock & CDNS_XSPI_DLL_LOCK) == 1), 10, 10000);
+}
+
+/* Static configuration of PHY */
+static bool cdns_xspi_configure_phy(struct cdns_xspi_dev *cdns_xspi)
+{
+ writel(REGS_DLL_PHY_CTRL,
+ cdns_xspi->iobase + CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL);
+ writel(CTB_RFILE_PHY_CTRL,
+ cdns_xspi->auxbase + CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL);
+ writel(RFILE_PHY_TSEL,
+ cdns_xspi->auxbase + CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL);
+ writel(RFILE_PHY_DQ_TIMING,
+ cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING);
+ writel(RFILE_PHY_DQS_TIMING,
+ cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING);
+ writel(RFILE_PHY_GATE_LPBK_CTRL,
+ cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL);
+ writel(RFILE_PHY_DLL_MASTER_CTRL,
+ cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL);
+ writel(RFILE_PHY_DLL_SLAVE_CTRL,
+ cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL);
+
+ cdns_xspi_reset_dll(cdns_xspi);
+
+ return cdns_xspi_is_dll_locked(cdns_xspi);
+}
+
+/* Find max avalible clock */
+static bool cdns_mrvl_xspi_setup_clock(struct cdns_xspi_dev *cdns_xspi,
+ int requested_clk)
+{
+ int i = 0;
+ int clk_val;
+ u32 clk_reg;
+ bool update_clk = false;
+
+ while (i < ARRAY_SIZE(cdns_mrvl_xspi_clk_div_list)) {
+ clk_val = MRVL_XSPI_CLOCK_DIVIDED(
+ cdns_mrvl_xspi_clk_div_list[i]);
+ if (clk_val <= requested_clk)
+ break;
+ i++;
+ }
+
+ dev_dbg(cdns_xspi->dev, "Found clk div: %d, clk val: %d\n",
+ cdns_mrvl_xspi_clk_div_list[i],
+ MRVL_XSPI_CLOCK_DIVIDED(
+ cdns_mrvl_xspi_clk_div_list[i]));
+
+ clk_reg = readl(cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG);
+
+ if (FIELD_GET(MRVL_XSPI_CLK_DIV, clk_reg) != i) {
+ clk_reg &= ~MRVL_XSPI_CLK_ENABLE;
+ writel(clk_reg,
+ cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG);
+ clk_reg = FIELD_PREP(MRVL_XSPI_CLK_DIV, i);
+ clk_reg &= ~MRVL_XSPI_CLK_DIV;
+ clk_reg |= FIELD_PREP(MRVL_XSPI_CLK_DIV, i);
+ clk_reg |= MRVL_XSPI_CLK_ENABLE;
+ clk_reg |= MRVL_XSPI_IRQ_ENABLE;
+ update_clk = true;
+ }
+
+ if (update_clk)
+ writel(clk_reg,
+ cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG);
+
+ return update_clk;
+}
+
static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi)
{
u32 ctrl_stat;
@@ -295,6 +450,10 @@ static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi,
bool enabled)
{
u32 intr_enable;
+ u32 irq_status;
+
+ irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
+ writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
if (enabled)
@@ -319,6 +478,9 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
return -EIO;
}
+ writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
+ cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
+
ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG);
cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features);
cdns_xspi_set_interrupts(cdns_xspi, false);
@@ -326,6 +488,70 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
return 0;
}
+static void mrvl_ioreadq(void __iomem *addr, void *buf, int len)
+{
+ int i = 0;
+ int rcount = len / 8;
+ int rcount_nf = len % 8;
+ uint64_t tmp;
+ uint64_t *buf64 = (uint64_t *)buf;
+
+ if (((uint64_t)buf % 8) == 0) {
+ for (i = 0; i < rcount; i++)
+ *buf64++ = readq(addr);
+ } else {
+ for (i = 0; i < rcount; i++) {
+ tmp = readq(addr);
+ memcpy(buf+(i*8), &tmp, 8);
+ }
+ }
+
+ if (rcount_nf != 0) {
+ tmp = readq(addr);
+ memcpy(buf+(i*8), &tmp, rcount_nf);
+ }
+}
+
+static void mrvl_iowriteq(void __iomem *addr, const void *buf, int len)
+{
+ int i = 0;
+ int rcount = len / 8;
+ int rcount_nf = len % 8;
+ uint64_t tmp;
+ uint64_t *buf64 = (uint64_t *)buf;
+
+ if (((uint64_t)buf % 8) == 0) {
+ for (i = 0; i < rcount; i++)
+ writeq(*buf64++, addr);
+ } else {
+ for (i = 0; i < rcount; i++) {
+ memcpy(&tmp, buf+(i*8), 8);
+ writeq(tmp, addr);
+ }
+ }
+
+ if (rcount_nf != 0) {
+ memcpy(&tmp, buf+(i*8), rcount_nf);
+ writeq(tmp, addr);
+ }
+}
+
+static void cdns_xspi_sdma_memread(struct cdns_xspi_dev *cdns_xspi, int len)
+{
+ if (cdns_xspi->mrvl_hw_overlay)
+ mrvl_ioreadq(cdns_xspi->sdmabase, cdns_xspi->in_buffer, len);
+ else
+ ioread8_rep(cdns_xspi->sdmabase, cdns_xspi->in_buffer, len);
+}
+
+static void cdns_xspi_sdma_memwrite(struct cdns_xspi_dev *cdns_xspi, int len)
+{
+ if (cdns_xspi->mrvl_hw_overlay)
+ mrvl_iowriteq(cdns_xspi->sdmabase, cdns_xspi->out_buffer, len);
+ else
+ iowrite8_rep(cdns_xspi->sdmabase, cdns_xspi->out_buffer, len);
+}
+
static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
{
u32 sdma_size, sdma_trd_info;
@@ -337,13 +563,11 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
switch (sdma_dir) {
case CDNS_XSPI_SDMA_DIR_READ:
- ioread8_rep(cdns_xspi->sdmabase,
- cdns_xspi->in_buffer, sdma_size);
+ cdns_xspi_sdma_memread(cdns_xspi, sdma_size);
break;
case CDNS_XSPI_SDMA_DIR_WRITE:
- iowrite8_rep(cdns_xspi->sdmabase,
- cdns_xspi->out_buffer, sdma_size);
+ cdns_xspi_sdma_memwrite(cdns_xspi, sdma_size);
break;
}
}
@@ -421,6 +645,9 @@ static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
if (cdns_xspi->cur_cs != spi_get_chipselect(mem->spi, 0))
cdns_xspi->cur_cs = spi_get_chipselect(mem->spi, 0);
+ if (cdns_xspi->mrvl_hw_overlay)
+ cdns_mrvl_xspi_setup_clock(cdns_xspi, mem->spi->max_speed_hz);
+
return cdns_xspi_send_stig_command(cdns_xspi, op,
(dir != SPI_MEM_NO_DATA));
}
@@ -461,6 +688,10 @@ static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
+ if (cdns_xspi->mrvl_hw_overlay)
+ writel(MRVL_MSIX_CLEAR_IRQ,
+ cdns_xspi->auxbase + MRVL_XSPI_SPIX_INTR_AUX);
+
if (irq_status &
(CDNS_XSPI_SDMA_ERROR | CDNS_XSPI_SDMA_TRIGGER |
CDNS_XSPI_STIG_DONE)) {
@@ -528,11 +759,23 @@ static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi)
readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL));
}
+static int cdns_xspi_setup(struct spi_device *spi_dev)
+{
+ struct cdns_xspi_dev *cdns_xspi = spi_controller_get_devdata(
+ spi_dev->controller);
+
+ if (cdns_xspi->mrvl_hw_overlay)
+ cdns_mrvl_xspi_setup_clock(cdns_xspi, spi_dev->max_speed_hz);
+
+ return 0;
+}
+
static int cdns_xspi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct spi_controller *host = NULL;
struct cdns_xspi_dev *cdns_xspi = NULL;
+ const struct cdns_xspi_driver_data *drv_data;
struct resource *res;
int ret;
@@ -544,10 +787,16 @@ static int cdns_xspi_probe(struct platform_device *pdev)
SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL | SPI_RX_OCTAL |
SPI_MODE_0 | SPI_MODE_3;
+ drv_data = of_device_get_match_data(dev);
+
host->mem_ops = &cadence_xspi_mem_ops;
host->dev.of_node = pdev->dev.of_node;
+ host->dev.fwnode = pdev->dev.fwnode;
host->bus_num = -1;
+ if (drv_data->mrvl_hw_overlay)
+ host->setup = cdns_xspi_setup;
+
platform_set_drvdata(pdev, host);
cdns_xspi = spi_controller_get_devdata(host);
@@ -559,6 +808,8 @@ static int cdns_xspi_probe(struct platform_device *pdev)
init_completion(&cdns_xspi->auto_cmd_complete);
init_completion(&cdns_xspi->sdma_complete);
+ cdns_xspi->mrvl_hw_overlay = drv_data->mrvl_hw_overlay;
+
ret = cdns_xspi_of_get_plat_data(pdev);
if (ret)
return -ENODEV;
@@ -592,8 +843,12 @@ static int cdns_xspi_probe(struct platform_device *pdev)
return ret;
}
- cdns_xspi_print_phy_config(cdns_xspi);
+ if (drv_data->mrvl_hw_overlay) {
+ cdns_mrvl_xspi_setup_clock(cdns_xspi, MRVL_DEFAULT_CLK);
+ cdns_xspi_configure_phy(cdns_xspi);
+ }
+ cdns_xspi_print_phy_config(cdns_xspi);
ret = cdns_xspi_controller_init(cdns_xspi);
if (ret) {
dev_err(dev, "Failed to initialize controller\n");
@@ -616,6 +871,11 @@ static int cdns_xspi_probe(struct platform_device *pdev)
static const struct of_device_id cdns_xspi_of_match[] = {
{
.compatible = "cdns,xspi-nor",
+ .data = &cdns_driver_data,
+ },
+ {
+ .compatible = "marvell,cn10-xspi-nor",
+ .data = &mrvl_driver_data,
},
{ /* end of table */}
};
--
2.43.0
MRVL Xfer overlay extends xSPI capabilities to support non-memory SPI
operations. The Marvell overlay, combined with a generic command, allows
for full-duplex SPI transactions. It also enables transactions with
undetermined lengths using the cs_hold parameter and the ability to
extend CS signal assertion, even if the xSPI block requests CS signal
de-assertion.
Signed-off-by: Witold Sadowski <[email protected]>
---
drivers/spi/spi-cadence-xspi.c | 245 +++++++++++++++++++++++++++++++++
1 file changed, 245 insertions(+)
diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 36c6c25aaea0..186a781371a9 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -219,6 +219,7 @@
#define CDNS_XSPI_DLL_RST_N BIT(24)
#define CDNS_XSPI_DLL_LOCK BIT(0)
+
/* Marvell overlay registers - clock */
#define MRVL_XSPI_CLK_CTRL_AUX_REG 0x2020
#define MRVL_XSPI_CLK_ENABLE BIT(0)
@@ -232,6 +233,22 @@
#define MRVL_XSPI_SPIX_INTR_AUX 0x2000
#define MRVL_MSIX_CLEAR_IRQ 0x01
+/* Marvell overlay registers - xfer */
+#define MRVL_XFER_FUNC_CTRL 0x210
+#define MRVL_XFER_FUNC_CTRL_READ_DATA(i) (0x000 + 8 * (i))
+#define MRVL_XFER_SOFT_RESET BIT(11)
+#define MRVL_XFER_CS_N_HOLD GENMASK(9, 6)
+#define MRVL_XFER_RECEIVE_ENABLE BIT(4)
+#define MRVL_XFER_FUNC_ENABLE BIT(3)
+#define MRVL_XFER_CLK_CAPTURE_POL BIT(2)
+#define MRVL_XFER_CLK_DRIVE_POL BIT(1)
+#define MRVL_XFER_FUNC_START BIT(0)
+#define MRVL_XFER_QWORD_COUNT 32
+#define MRVL_XFER_QWORD_BYTECOUNT 8
+
+#define MRVL_XSPI_POLL_TIMEOUT_US 1000
+#define MRVL_XSPI_POLL_DELAY_US 10
+
enum cdns_xspi_stig_instr_type {
CDNS_XSPI_STIG_INSTR_TYPE_0,
CDNS_XSPI_STIG_INSTR_TYPE_1,
@@ -256,6 +273,7 @@ struct cdns_xspi_dev {
void __iomem *iobase;
void __iomem *auxbase;
void __iomem *sdmabase;
+ void __iomem *xferbase;
int irq;
int cur_cs;
@@ -270,6 +288,9 @@ struct cdns_xspi_dev {
const void *out_buffer;
u8 hw_num_banks;
+
+ bool xfer_in_progress;
+ int current_xfer_qword;
};
struct cdns_xspi_driver_data {
@@ -841,6 +862,220 @@ static int cdns_xspi_setup(struct spi_device *spi_dev)
return 0;
}
+static int cdns_xspi_prepare_generic(int cs, const void *dout, int len, int glue, u32 *cmd_regs)
+{
+ u8 *data = (u8 *)dout;
+ int i;
+ int data_counter = 0;
+
+ memset(cmd_regs, 0x00, 6*4);
+
+ if (len > 7) {
+ for (i = (len >= 10 ? 2 : len - 8); i >= 0 ; i--)
+ cmd_regs[3] |= data[data_counter++] << (8*i);
+ }
+ if (len > 3) {
+ for (i = (len >= 7 ? 3 : len - 4); i >= 0; i--)
+ cmd_regs[2] |= data[data_counter++] << (8*i);
+ }
+ for (i = (len >= 3 ? 2 : len - 1); i >= 0 ; i--)
+ cmd_regs[1] |= data[data_counter++] << (8 + 8*i);
+
+ cmd_regs[1] |= 96;
+ cmd_regs[3] |= len << 24;
+ cmd_regs[4] |= cs << 12;
+
+ if (glue == 1)
+ cmd_regs[4] |= 1 << 28;
+
+ return 0;
+}
+
+static unsigned char reverse_bits(unsigned char num)
+{
+ unsigned int count = sizeof(num) * 8 - 1;
+ unsigned int reverse_num = num;
+
+ num >>= 1;
+ while (num) {
+ reverse_num <<= 1;
+ reverse_num |= num & 1;
+ num >>= 1;
+ count--;
+ }
+ reverse_num <<= count;
+ return reverse_num;
+}
+
+static void cdns_xspi_read_single_qword(struct cdns_xspi_dev *cdns_xspi, u8 **buffer)
+{
+ u64 d = readq(cdns_xspi->xferbase +
+ MRVL_XFER_FUNC_CTRL_READ_DATA(cdns_xspi->current_xfer_qword));
+ u8 *ptr = (u8 *)&d;
+ int k;
+
+ for (k = 0; k < 8; k++) {
+ u8 val = reverse_bits((ptr[k]));
+ **buffer = val;
+ *buffer = *buffer + 1;
+ }
+
+ cdns_xspi->current_xfer_qword++;
+ cdns_xspi->current_xfer_qword %= MRVL_XFER_QWORD_COUNT;
+}
+
+static void cdns_xspi_finish_read(struct cdns_xspi_dev *cdns_xspi, u8 **buffer, u32 data_count)
+{
+ u64 d = readq(cdns_xspi->xferbase +
+ MRVL_XFER_FUNC_CTRL_READ_DATA(cdns_xspi->current_xfer_qword));
+ u8 *ptr = (u8 *)&d;
+ int k;
+
+ for (k = 0; k < data_count % MRVL_XFER_QWORD_BYTECOUNT; k++) {
+ u8 val = reverse_bits((ptr[k]));
+ **buffer = val;
+ *buffer = *buffer + 1;
+ }
+
+ cdns_xspi->current_xfer_qword++;
+ cdns_xspi->current_xfer_qword %= MRVL_XFER_QWORD_COUNT;
+}
+
+static int cdns_xspi_prepare_transfer(int cs, int dir, int len, u32 *cmd_regs)
+{
+ memset(cmd_regs, 0x00, 6*4);
+
+ cmd_regs[1] |= 127;
+ cmd_regs[2] |= len << 16;
+ cmd_regs[4] |= dir << 4; //dir = 0 read, dir =1 write
+ cmd_regs[4] |= cs << 12;
+
+ return 0;
+}
+
+static bool cdns_xspi_is_stig_ready(struct cdns_xspi_dev *cdns_xspi, bool sleep)
+{
+ u32 ctrl_stat;
+
+ return !readl_relaxed_poll_timeout
+ (cdns_xspi->iobase + CDNS_XSPI_CTRL_STATUS_REG,
+ ctrl_stat,
+ ((ctrl_stat & BIT(3)) == 0),
+ sleep ? MRVL_XSPI_POLL_DELAY_US : 0,
+ sleep ? MRVL_XSPI_POLL_TIMEOUT_US : 0);
+}
+
+static bool cdns_xspi_is_sdma_ready(struct cdns_xspi_dev *cdns_xspi, bool sleep)
+{
+ u32 ctrl_stat;
+
+ return !readl_relaxed_poll_timeout
+ (cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG,
+ ctrl_stat,
+ (ctrl_stat & CDNS_XSPI_SDMA_TRIGGER),
+ sleep ? MRVL_XSPI_POLL_DELAY_US : 0,
+ sleep ? MRVL_XSPI_POLL_TIMEOUT_US : 0);
+}
+
+static int cdns_xspi_transfer_one_message_b0(struct spi_controller *controller,
+ struct spi_message *m)
+{
+ struct cdns_xspi_dev *cdns_xspi = spi_controller_get_devdata(controller);
+ struct spi_device *spi = m->spi;
+ struct spi_transfer *t = NULL;
+
+ const int max_len = MRVL_XFER_QWORD_BYTECOUNT * MRVL_XFER_QWORD_COUNT;
+ int current_cycle_count;
+ int cs = spi_get_chipselect(spi, 0);
+ int cs_change = 0;
+
+ /* Enable xfer state machine */
+ if (!cdns_xspi->xfer_in_progress) {
+ u32 xfer_control = readl(cdns_xspi->xferbase + MRVL_XFER_FUNC_CTRL);
+
+ cdns_xspi->current_xfer_qword = 0;
+ cdns_xspi->xfer_in_progress = true;
+ xfer_control |= (MRVL_XFER_RECEIVE_ENABLE |
+ MRVL_XFER_CLK_CAPTURE_POL |
+ MRVL_XFER_FUNC_START |
+ MRVL_XFER_SOFT_RESET |
+ FIELD_PREP(MRVL_XFER_CS_N_HOLD, (1 << cs)));
+ xfer_control &= ~(MRVL_XFER_FUNC_ENABLE | MRVL_XFER_CLK_DRIVE_POL);
+ writel(xfer_control, cdns_xspi->xferbase + MRVL_XFER_FUNC_CTRL);
+ }
+
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+ u8 *txd = (u8 *) t->tx_buf;
+ u8 *rxd = (u8 *) t->rx_buf;
+ u8 data[10];
+ u32 cmd_regs[6];
+
+ if (!txd)
+ txd = data;
+
+ cdns_xspi->in_buffer = txd + 1;
+ cdns_xspi->out_buffer = txd + 1;
+
+ while (t->len) {
+
+ current_cycle_count = t->len > max_len ? max_len : t->len;
+
+ if (current_cycle_count < 10) {
+ cdns_xspi_prepare_generic(cs, txd, current_cycle_count,
+ false, cmd_regs);
+ cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
+ if (!cdns_xspi_is_stig_ready(cdns_xspi, true))
+ return -EIO;
+ } else {
+ cdns_xspi_prepare_generic(cs, txd, 1, true, cmd_regs);
+ cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
+ cdns_xspi_prepare_transfer(cs, 1, current_cycle_count - 1,
+ cmd_regs);
+ cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
+ if (!cdns_xspi_is_sdma_ready(cdns_xspi, true))
+ return -EIO;
+ cdns_xspi_sdma_handle(cdns_xspi);
+ if (!cdns_xspi_is_stig_ready(cdns_xspi, true))
+ return -EIO;
+
+ cdns_xspi->in_buffer += current_cycle_count;
+ cdns_xspi->out_buffer += current_cycle_count;
+ }
+
+ if (rxd) {
+ int j;
+
+ for (j = 0; j < current_cycle_count / 8; j++)
+ cdns_xspi_read_single_qword(cdns_xspi, &rxd);
+ cdns_xspi_finish_read(cdns_xspi, &rxd, current_cycle_count);
+ } else {
+ cdns_xspi->current_xfer_qword += current_cycle_count /
+ MRVL_XFER_QWORD_BYTECOUNT;
+ if (current_cycle_count % MRVL_XFER_QWORD_BYTECOUNT)
+ cdns_xspi->current_xfer_qword++;
+
+ cdns_xspi->current_xfer_qword %= MRVL_XFER_QWORD_COUNT;
+ }
+ cs_change = t->cs_change;
+ t->len -= current_cycle_count;
+ }
+ }
+
+ if (!cs_change) {
+ u32 xfer_control = readl(cdns_xspi->xferbase + MRVL_XFER_FUNC_CTRL);
+
+ xfer_control &= ~(MRVL_XFER_RECEIVE_ENABLE |
+ MRVL_XFER_SOFT_RESET);
+ writel(xfer_control, cdns_xspi->xferbase + MRVL_XFER_FUNC_CTRL);
+ cdns_xspi->xfer_in_progress = false;
+ }
+
+ m->status = 0;
+ spi_finalize_current_message(controller);
+
+ return 0;
+}
+
static int cdns_xspi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -908,6 +1143,15 @@ static int cdns_xspi_probe(struct platform_device *pdev)
return PTR_ERR(cdns_xspi->auxbase);
}
+ if (cdns_xspi->mrvl_hw_overlay) {
+ cdns_xspi->xferbase = devm_platform_ioremap_resource(pdev, 3);
+ if (IS_ERR(cdns_xspi->xferbase)) {
+ dev_info(dev, "XFER register base not found, set it\n");
+ // For compatibility with older firmware
+ cdns_xspi->xferbase = cdns_xspi->iobase + 0x8000;
+ }
+ }
+
cdns_xspi->irq = platform_get_irq(pdev, 0);
if (cdns_xspi->irq < 0)
return -ENXIO;
@@ -922,6 +1166,7 @@ static int cdns_xspi_probe(struct platform_device *pdev)
if (drv_data->mrvl_hw_overlay) {
cdns_mrvl_xspi_setup_clock(cdns_xspi, MRVL_DEFAULT_CLK);
cdns_xspi_configure_phy(cdns_xspi);
+ host->transfer_one_message = cdns_xspi_transfer_one_message_b0;
}
cdns_xspi_print_phy_config(cdns_xspi);
--
2.43.0
Add new bindings for the v2 Marvell xSPI overlay: marvell,cn10-xspi-nor
compatible string. This new compatible string distinguishes between the
original and modified xSPI block.
Also add an optional base for the xfer register set with an additional
reg field to allocate the xSPI Marvell overlay XFER block.
Signed-off-by: Witold Sadowski <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/spi/cdns,xspi.yaml | 32 ++++++++++++++++---
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
index eb0f92468185..38a5795589de 100644
--- a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml
@@ -15,24 +15,27 @@ description: |
single, dual, quad or octal wire transmission modes for
read/write access to slaves such as SPI-NOR flash.
-allOf:
- - $ref: spi-controller.yaml#
-
properties:
compatible:
- const: cdns,xspi-nor
+ enum:
+ - cdns,xspi-nor
+ - marvell,cn10-xspi-nor
reg:
items:
- description: address and length of the controller register set
- description: address and length of the Slave DMA data port
- description: address and length of the auxiliary registers
+ - description: address and length of the xfer registers
+ minItems: 3
reg-names:
items:
- const: io
- const: sdma
- const: aux
+ - const: xfer
+ minItems: 3
interrupts:
maxItems: 1
@@ -42,6 +45,27 @@ required:
- reg
- interrupts
+allOf:
+ - $ref: spi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,cn10-xspi-nor
+ then:
+ properties:
+ reg:
+ minItems: 4
+ reg-names:
+ minItems: 4
+ else:
+ properties:
+ reg:
+ maxItems: 3
+ reg-names:
+ maxItems: 3
+
unevaluatedProperties: false
examples:
--
2.43.0
On Fri, Jun 07, 2024 at 08:18:29AM -0700, Witold Sadowski wrote:
> This commit adds support for the basic v2 Marvell overlay block. Key
> features included are:
> - Clock configuration
> - PHY configuration
> - Interrupt configuration (enabling)
This feels like it could usefully be split up so these three bits are
separate, and there appear to be other changes buried in here as well.
I can't tell what changes either the PHY or interrupt configuration
might be referencing.
> @@ -295,6 +450,10 @@ static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi,
> bool enabled)
> {
> u32 intr_enable;
> + u32 irq_status;
> +
> + irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
> + writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
>
> intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
> if (enabled)
This seems like a separate change which applies to everything, not just
Marvell versions of the IP, and should be split out and explained.
> @@ -319,6 +478,9 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
> return -EIO;
> }
>
> + writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
> + cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
> +
This wasn't clearly mentioned in the changelog and is again being done
unconditionally for all instances of the IP, probably best to split out
and explain.
> +static void mrvl_ioreadq(void __iomem *addr, void *buf, int len)
> +{
> + int i = 0;
> + int rcount = len / 8;
> + int rcount_nf = len % 8;
> + uint64_t tmp;
> + uint64_t *buf64 = (uint64_t *)buf;
Any need to cast away from void * indicates a problem.
> @@ -337,13 +563,11 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
>
> switch (sdma_dir) {
> case CDNS_XSPI_SDMA_DIR_READ:
> - ioread8_rep(cdns_xspi->sdmabase,
> - cdns_xspi->in_buffer, sdma_size);
> + cdns_xspi_sdma_memread(cdns_xspi, sdma_size);
> break;
It's feeling like it might make sense to have an ops structure rather
than sprinkling checks for the Marvell overlay everywhere.
On Fri, Jun 07, 2024 at 08:18:30AM -0700, Witold Sadowski wrote:
> These changes enable reading the configurations from ACPI tables as
> required for successful probing in an ACPI UEFI environment. In the
> case of an ACPI-disabled or DTS-based environment, it will continue
> to read configurations from DTS as before.
This doesn't describe what the ACPI tables are supposed to look like or
anything, it's hard to review this...
> +#ifdef CONFIG_ACPI
> +static bool cdns_xspi_supports_op(struct spi_mem *mem,
> + const struct spi_mem_op *op)
> +{
> + if (!acpi_dev_get_property(adev, "spi-tx-bus-width", ACPI_TYPE_INTEGER,
> + &obj)) {
> + if (!acpi_dev_get_property(adev, "spi-rx-bus-width", ACPI_TYPE_INTEGER,
> + &obj)) {
Why is this Cadence specific?
> static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
> {
> - struct device_node *node_prop = pdev->dev.of_node;
> + struct fwnode_handle *fwnode_child;
> unsigned int cs;
>
> - for_each_available_child_of_node_scoped(node_prop, node_child) {
> - if (of_property_read_u32(node_child, "reg", &cs)) {
> + device_for_each_child_node(&pdev->dev, fwnode_child) {
> + if (!fwnode_device_is_available(fwnode_child))
> + continue;
> +
> + if (fwnode_property_read_u32(fwnode_child, "reg", &cs)) {
> dev_err(&pdev->dev, "Couldn't get memory chip select\n");
> + fwnode_handle_put(fwnode_child);
> return -ENXIO;
> } else if (cs >= CDNS_XSPI_MAX_BANKS) {
> dev_err(&pdev->dev, "reg (cs) parameter value too large\n");
> + fwnode_handle_put(fwnode_child);
> return -ENXIO;
> }
> }
This is just a general refactoring to fwnode and could be split out.
> @@ -814,19 +890,19 @@ static int cdns_xspi_probe(struct platform_device *pdev)
> if (ret)
> return -ENODEV;
>
> - cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev, "io");
> + cdns_xspi->iobase = devm_platform_ioremap_resource(pdev, 0);
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma");
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> - cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev, "aux");
> + cdns_xspi->auxbase = devm_platform_ioremap_resource(pdev, 2);
This causes us to ignore naming on resources, that's an ABI break for
other systems.
On Fri, Jun 07, 2024 at 08:18:31AM -0700, Witold Sadowski wrote:
> +static int cdns_xspi_prepare_generic(int cs, const void *dout, int len, int glue, u32 *cmd_regs)
> +{
> + u8 *data = (u8 *)dout;
> + int i;
> + int data_counter = 0;
> +
> + memset(cmd_regs, 0x00, 6*4);
The magic numbers here aren't great...
> +static unsigned char reverse_bits(unsigned char num)
> +{
> + unsigned int count = sizeof(num) * 8 - 1;
> + unsigned int reverse_num = num;
> +
> + num >>= 1;
> + while (num) {
> + reverse_num <<= 1;
> + reverse_num |= num & 1;
> + num >>= 1;
> + count--;
> + }
> + reverse_num <<= count;
> + return reverse_num;
> +}
I can't help but think there ought to be a helper for this though I
can't think what it is off the top of my head. If there isn't it
probably makes sense to add this as one.
> + /* Enable xfer state machine */
> + if (!cdns_xspi->xfer_in_progress) {
> + u32 xfer_control = readl(cdns_xspi->xferbase + MRVL_XFER_FUNC_CTRL);
> +
> + cdns_xspi->current_xfer_qword = 0;
> + cdns_xspi->xfer_in_progress = true;
> + xfer_control |= (MRVL_XFER_RECEIVE_ENABLE |
> + MRVL_XFER_CLK_CAPTURE_POL |
> + MRVL_XFER_FUNC_START |
> + MRVL_XFER_SOFT_RESET |
> + FIELD_PREP(MRVL_XFER_CS_N_HOLD, (1 << cs)));
> + xfer_control &= ~(MRVL_XFER_FUNC_ENABLE | MRVL_XFER_CLK_DRIVE_POL);
> + writel(xfer_control, cdns_xspi->xferbase + MRVL_XFER_FUNC_CTRL);
> + }
Could this just be a prepare_transfer_hardware() and we could just use
transfer_one()?
> + list_for_each_entry(t, &m->transfers, transfer_list) {
> + u8 *txd = (u8 *) t->tx_buf;
> + u8 *rxd = (u8 *) t->rx_buf;
> + u8 data[10];
> + u32 cmd_regs[6];
> +
> + if (!txd)
> + txd = data;
> +
> + cdns_xspi->in_buffer = txd + 1;
> + cdns_xspi->out_buffer = txd + 1;
Oh?
Hi
> On Fri, Jun 07, 2024 at 08:18:29AM -0700, Witold Sadowski wrote:
> > This commit adds support for the basic v2 Marvell overlay block. Key
> > features included are:
> > - Clock configuration
> > - PHY configuration
> > - Interrupt configuration (enabling)
>
> This feels like it could usefully be split up so these three bits are
> separate, and there appear to be other changes buried in here as well.
> I can't tell what changes either the PHY or interrupt configuration might
> be referencing.
That changes are in single commit as, using not all of them will result in
total xSPI failure. Configuring PHY makes no sense if clock is not enabled.
But I can try to split that into 3 separate commits.
>
> > @@ -295,6 +450,10 @@ static void cdns_xspi_set_interrupts(struct
> cdns_xspi_dev *cdns_xspi,
> > bool enabled)
> > {
> > u32 intr_enable;
> > + u32 irq_status;
> > +
> > + irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
> > + writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
> >
> > intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
> > if (enabled)
>
> This seems like a separate change which applies to everything, not just
> Marvell versions of the IP, and should be split out and explained.
I will move that to separate commit too. It is possible that previous
stage will not clear that register correctly, and that will lead to
interrupt fail - at least in Marvell implementation.
>
> > @@ -319,6 +478,9 @@ static int cdns_xspi_controller_init(struct
> cdns_xspi_dev *cdns_xspi)
> > return -EIO;
> > }
> >
> > + writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE,
> CDNS_XSPI_WORK_MODE_STIG),
> > + cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
> > +
>
> This wasn't clearly mentioned in the changelog and is again being done
> unconditionally for all instances of the IP, probably best to split out
> and explain.
Ok, I can move to separate commit too.
>
> > +static void mrvl_ioreadq(void __iomem *addr, void *buf, int len) {
> > + int i = 0;
> > + int rcount = len / 8;
> > + int rcount_nf = len % 8;
> > + uint64_t tmp;
> > + uint64_t *buf64 = (uint64_t *)buf;
>
> Any need to cast away from void * indicates a problem.
I will check that, but code is checking alignment of that pointer.
>
> > @@ -337,13 +563,11 @@ static void cdns_xspi_sdma_handle(struct
> > cdns_xspi_dev *cdns_xspi)
> >
> > switch (sdma_dir) {
> > case CDNS_XSPI_SDMA_DIR_READ:
> > - ioread8_rep(cdns_xspi->sdmabase,
> > - cdns_xspi->in_buffer, sdma_size);
> > + cdns_xspi_sdma_memread(cdns_xspi, sdma_size);
> > break;
>
> It's feeling like it might make sense to have an ops structure rather than
> sprinkling checks for the Marvell overlay everywhere.
Won't it cause big code duplication? There are some differences, but whole
Part of SPI stig mode configuration is the same.
Regards
Witek
Hi
> > These changes enable reading the configurations from ACPI tables as
> > required for successful probing in an ACPI UEFI environment. In the
> > case of an ACPI-disabled or DTS-based environment, it will continue to
> > read configurations from DTS as before.
>
> This doesn't describe what the ACPI tables are supposed to look like or
> anything, it's hard to review this...
There should be an example of ACPI table in commit message?
>
> > +#ifdef CONFIG_ACPI
> > +static bool cdns_xspi_supports_op(struct spi_mem *mem,
> > + const struct spi_mem_op *op)
> > +{
>
> > + if (!acpi_dev_get_property(adev, "spi-tx-bus-width",
> ACPI_TYPE_INTEGER,
> > + &obj)) {
>
> > + if (!acpi_dev_get_property(adev, "spi-rx-bus-width",
> ACPI_TYPE_INTEGER,
> > + &obj)) {
>
> Why is this Cadence specific?
So that part should do to generic spi? I think right now it is not
Supported to read tx/rx bus width from acpi.
>
> > static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
> > {
> > - struct device_node *node_prop = pdev->dev.of_node;
> > + struct fwnode_handle *fwnode_child;
> > unsigned int cs;
> >
> > - for_each_available_child_of_node_scoped(node_prop, node_child) {
> > - if (of_property_read_u32(node_child, "reg", &cs)) {
> > + device_for_each_child_node(&pdev->dev, fwnode_child) {
> > + if (!fwnode_device_is_available(fwnode_child))
> > + continue;
> > +
> > + if (fwnode_property_read_u32(fwnode_child, "reg", &cs)) {
> > dev_err(&pdev->dev, "Couldn't get memory chip
> select\n");
> > + fwnode_handle_put(fwnode_child);
> > return -ENXIO;
> > } else if (cs >= CDNS_XSPI_MAX_BANKS) {
> > dev_err(&pdev->dev, "reg (cs) parameter value too
> large\n");
> > + fwnode_handle_put(fwnode_child);
> > return -ENXIO;
> > }
> > }
>
> This is just a general refactoring to fwnode and could be split out.
Ok.
>
> > @@ -814,19 +890,19 @@ static int cdns_xspi_probe(struct platform_device
> *pdev)
> > if (ret)
> > return -ENODEV;
> >
> > - cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev,
> "io");
> > + cdns_xspi->iobase = devm_platform_ioremap_resource(pdev, 0);
>
> > - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma");
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>
> > - cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev,
> "aux");
> > + cdns_xspi->auxbase = devm_platform_ioremap_resource(pdev, 2);
>
> This causes us to ignore naming on resources, that's an ABI break for
> other systems.
In that case acpi tables are not able to find resource by name. Or at
least I wasn't able to find a way to handle that in different way.
Is there better solution for that part?
Regards
Witek
Hi
>
> > +static int cdns_xspi_prepare_generic(int cs, const void *dout, int
> > +len, int glue, u32 *cmd_regs) {
> > + u8 *data = (u8 *)dout;
> > + int i;
> > + int data_counter = 0;
> > +
> > + memset(cmd_regs, 0x00, 6*4);
>
> The magic numbers here aren't great...
That will be fixed.
>
> > +static unsigned char reverse_bits(unsigned char num) {
> > + unsigned int count = sizeof(num) * 8 - 1;
> > + unsigned int reverse_num = num;
> > +
> > + num >>= 1;
> > + while (num) {
> > + reverse_num <<= 1;
> > + reverse_num |= num & 1;
> > + num >>= 1;
> > + count--;
> > + }
> > + reverse_num <<= count;
> > + return reverse_num;
> > +}
>
> I can't help but think there ought to be a helper for this though I can't
> think what it is off the top of my head. If there isn't it probably makes
> sense to add this as one.
>
> > + /* Enable xfer state machine */
> > + if (!cdns_xspi->xfer_in_progress) {
> > + u32 xfer_control = readl(cdns_xspi->xferbase +
> > +MRVL_XFER_FUNC_CTRL);
> > +
> > + cdns_xspi->current_xfer_qword = 0;
> > + cdns_xspi->xfer_in_progress = true;
> > + xfer_control |= (MRVL_XFER_RECEIVE_ENABLE |
> > + MRVL_XFER_CLK_CAPTURE_POL |
> > + MRVL_XFER_FUNC_START |
> > + MRVL_XFER_SOFT_RESET |
> > + FIELD_PREP(MRVL_XFER_CS_N_HOLD, (1 << cs)));
> > + xfer_control &= ~(MRVL_XFER_FUNC_ENABLE |
> MRVL_XFER_CLK_DRIVE_POL);
> > + writel(xfer_control, cdns_xspi->xferbase +
> MRVL_XFER_FUNC_CTRL);
> > + }
>
> Could this just be a prepare_transfer_hardware() and we could just use
> transfer_one()?
I have to run some experiments, but it should be possible.
>
> > + list_for_each_entry(t, &m->transfers, transfer_list) {
> > + u8 *txd = (u8 *) t->tx_buf;
> > + u8 *rxd = (u8 *) t->rx_buf;
> > + u8 data[10];
> > + u32 cmd_regs[6];
> > +
> > + if (!txd)
> > + txd = data;
> > +
> > + cdns_xspi->in_buffer = txd + 1;
> > + cdns_xspi->out_buffer = txd + 1;
>
> Oh?
You are asking about that 1 byte offset? It is caused by way that
SDMA is handled in that specific case - all data except of first
byte is transferred via SDMA, the first byte is send in command, and
SDMA is not involved in that.
Regards
Witek
On Tue, Jun 11, 2024 at 09:57:09PM +0000, Witold Sadowski wrote:
> > > These changes enable reading the configurations from ACPI tables as
> > > required for successful probing in an ACPI UEFI environment. In the
> > > case of an ACPI-disabled or DTS-based environment, it will continue to
> > > read configurations from DTS as before.
> > This doesn't describe what the ACPI tables are supposed to look like or
> > anything, it's hard to review this...
> There should be an example of ACPI table in commit message?
No sign of one in the patch that got sent, nor in the cover letter.
> > > +#ifdef CONFIG_ACPI
> > > +static bool cdns_xspi_supports_op(struct spi_mem *mem,
> > > + const struct spi_mem_op *op)
> > > +{
> > > + if (!acpi_dev_get_property(adev, "spi-tx-bus-width",
> > ACPI_TYPE_INTEGER,
> > > + &obj)) {
> > > + if (!acpi_dev_get_property(adev, "spi-rx-bus-width",
> > ACPI_TYPE_INTEGER,
> > > + &obj)) {
> > Why is this Cadence specific?
> So that part should do to generic spi? I think right now it is not
> Supported to read tx/rx bus width from acpi.
I think I meant to say Marvell there rather than Cadence.
> > > - cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev,
> > "io");
> > > + cdns_xspi->iobase = devm_platform_ioremap_resource(pdev, 0);
> >
> > > - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma");
> > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> >
> > > - cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev,
> > "aux");
> > > + cdns_xspi->auxbase = devm_platform_ioremap_resource(pdev, 2);
> > This causes us to ignore naming on resources, that's an ABI break for
> > other systems.
> In that case acpi tables are not able to find resource by name. Or at
> least I wasn't able to find a way to handle that in different way.
> Is there better solution for that part?
Try by name and then fall back on numbers?
On Tue, Jun 11, 2024 at 10:02:33PM +0000, Witold Sadowski wrote:
> > > + cdns_xspi->in_buffer = txd + 1;
> > > + cdns_xspi->out_buffer = txd + 1;
> > Oh?
> You are asking about that 1 byte offset? It is caused by way that
> SDMA is handled in that specific case - all data except of first
> byte is transferred via SDMA, the first byte is send in command, and
> SDMA is not involved in that.
That needs a comment I think.
On Tue, Jun 11, 2024 at 09:51:58PM +0000, Witold Sadowski wrote:
> > On Fri, Jun 07, 2024 at 08:18:29AM -0700, Witold Sadowski wrote:
> > > features included are:
> > > - Clock configuration
> > > - PHY configuration
> > > - Interrupt configuration (enabling)
> > This feels like it could usefully be split up so these three bits are
> > separate, and there appear to be other changes buried in here as well.
> > I can't tell what changes either the PHY or interrupt configuration might
> > be referencing.
> That changes are in single commit as, using not all of them will result in
> total xSPI failure. Configuring PHY makes no sense if clock is not enabled.
> But I can try to split that into 3 separate commits.
They won't actually do anything until we detect the Marvell IP.
> > > +static void mrvl_ioreadq(void __iomem *addr, void *buf, int len) {
> > > + int i = 0;
> > > + int rcount = len / 8;
> > > + int rcount_nf = len % 8;
> > > + uint64_t tmp;
> > > + uint64_t *buf64 = (uint64_t *)buf;
> > Any need to cast away from void * indicates a problem.
> I will check that, but code is checking alignment of that pointer.
A cast won't do anything to fix alignment issues.
> > > case CDNS_XSPI_SDMA_DIR_READ:
> > > - ioread8_rep(cdns_xspi->sdmabase,
> > > - cdns_xspi->in_buffer, sdma_size);
> > > + cdns_xspi_sdma_memread(cdns_xspi, sdma_size);
> > > break;
> > It's feeling like it might make sense to have an ops structure rather than
> > sprinkling checks for the Marvell overlay everywhere.
> Won't it cause big code duplication? There are some differences, but whole
> Part of SPI stig mode configuration is the same.
No more than having a bunch of functions which are called a single time
with checks in them will?