MIPS MT ASE is only available on ISA between Release 1 and Release 5.
Add ISA level dependency to Kconfig to fix build.
Reported-by: Guenter Roeck <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
v0: https://lore.kernel.org/all/[email protected]/
---
arch/mips/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 797ae590ebdb..c44358a6d93e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB
config MIPS_MT_SMP
bool "MIPS MT SMP support (1 TC on each available VPE)"
default y
- depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
+ depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
+ depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select SYNC_R4K
--
2.43.0
On Fri, 2 Feb 2024, Jiaxun Yang wrote:
> MIPS MT ASE is only available on ISA between Release 1 and Release 5.
R2+ only actually, as also evident from Kconfig...
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB
> config MIPS_MT_SMP
> bool "MIPS MT SMP support (1 TC on each available VPE)"
> default y
> - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
> + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
> + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
> select CPU_MIPSR2_IRQ_VI
> select CPU_MIPSR2_IRQ_EI
^^^^^^
... here. I wish people looked beyond the line they change, sigh...
Maciej
在2024年5月14日五月 下午10:38，Maciej W. Rozycki写道：
> On Fri, 2 Feb 2024, Jiaxun Yang wrote:
>
>> MIPS MT ASE is only available on ISA between Release 1 and Release 5.
>
> R2+ only actually, as also evident from Kconfig...
Hi Maciej,
Long time no see :-)
There is nothing stopping us to run R1 kernel on R2 hardware, given that
those features are all detected at boot time. I understand MT was introduced
at 34K which is R2.
I tested booting R1 kernel with MT on 1004Kc.
I believe we should give users flexibility on enjoying optional features
on kernel targeting lower ISA Rev.
>
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB
>> config MIPS_MT_SMP
>> bool "MIPS MT SMP support (1 TC on each available VPE)"
>> default y
>> - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
>> + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
>> select CPU_MIPSR2_IRQ_VI
>> select CPU_MIPSR2_IRQ_EI
> ^^^^^^
> ... here. I wish people looked beyond the line they change, sigh...
Both features (VI and VEIC) are probed at boot time. Selecting
them doesn't necessarily mean that CPU has those functions.
Thanks
- Jiaxun
>
> Maciej
--
- Jiaxun
On Wed, 15 May 2024, Jiaxun Yang wrote:
> >> MIPS MT ASE is only available on ISA between Release 1 and Release 5.
> >
> > R2+ only actually, as also evident from Kconfig...
>
> Hi Maciej,
>
> Long time no see :-)
It's not so easy to get rid of me. ;)
> There is nothing stopping us to run R1 kernel on R2 hardware, given that
> those features are all detected at boot time. I understand MT was introduced
> at 34K which is R2.
We can certainly choose to support R2 features at run time with R1 kernel
configurations, but it's not what the change description says (left quoted
above for reference). And the MT ASE, indeed first implemented with the
34K (for which I was a member of the product development team back at MIPS
UK), is not a part of the R1 ISA specification set.
> >> --- a/arch/mips/Kconfig
> >> +++ b/arch/mips/Kconfig
> >> @@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB
> >> config MIPS_MT_SMP
> >> bool "MIPS MT SMP support (1 TC on each available VPE)"
> >> default y
> >> - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
> >> + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
> >> + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
> >> select CPU_MIPSR2_IRQ_VI
> >> select CPU_MIPSR2_IRQ_EI
> > ^^^^^^
> > ... here. I wish people looked beyond the line they change, sigh...
>
> Both features (VI and VEIC) are probed at boot time. Selecting
> them doesn't necessarily mean that CPU has those functions.
Both are optional for R2+, so necessarily they need to be probed for, but
they are not available in R1. The reverse dependency set here is another
indication that the MT ASE is an R2+ feature.
Maciej
在2024年5月15日五月 下午2:43，Maciej W. Rozycki写道：
> On Wed, 15 May 2024, Jiaxun Yang wrote:
>
>> >> MIPS MT ASE is only available on ISA between Release 1 and Release 5.
>> >
>> > R2+ only actually, as also evident from Kconfig...
>>
>> Hi Maciej,
>>
>> Long time no see :-)
>
> It's not so easy to get rid of me. ;)
>
>> There is nothing stopping us to run R1 kernel on R2 hardware, given that
>> those features are all detected at boot time. I understand MT was introduced
>> at 34K which is R2.
>
> We can certainly choose to support R2 features at run time with R1 kernel
> configurations, but it's not what the change description says (left quoted
> above for reference). And the MT ASE, indeed first implemented with the
> 34K (for which I was a member of the product development team back at MIPS
> UK), is not a part of the R1 ISA specification set.
>
Good to know!
The motivation behind this patch is to workaround some randconfig failures
that combines MT with early ISA release.
They are not trivial to fix, so I just ban them in Kconfig. I was a little bit
reluctant to admit that in commit message.
Anyway, thanks for bringing that up.
--
- Jiaxun
On Wed, 15 May 2024, Jiaxun Yang wrote:
> >> There is nothing stopping us to run R1 kernel on R2 hardware, given that
> >> those features are all detected at boot time. I understand MT was introduced
> >> at 34K which is R2.
> >
> > We can certainly choose to support R2 features at run time with R1 kernel
> > configurations, but it's not what the change description says (left quoted
> > above for reference). And the MT ASE, indeed first implemented with the
> > 34K (for which I was a member of the product development team back at MIPS
> > UK), is not a part of the R1 ISA specification set.
> >
> Good to know!
>
> The motivation behind this patch is to workaround some randconfig failures
> that combines MT with early ISA release.
I'd say it's an actual fix rather than just a workaround.
Originally intention was with the MIPS port that eventually we would
support a generic kernel configuration, such as original x86 Linux has
always had or the Alpha port has at one point gained, where you can have
respectively an i486 (or previously even i386) or EV4 CPU kernel binary
that runs everywhere, even on the most recent hardware available.
With the MIPS platform fragmentation it has proved too much of an effort
for the engineering resources we've had available and consequently never
happened. This is why we have retained numerous abstractions intended to
switch between handlers at boot time (and had even more in the past).
From R1 onwards the privileged architecture has become more uniform and
therefore easier to handle between ISA revisions and/or implementations
and the choice of the CPU to build for has become more of a balance
between backwards compatibility and optimisation stemming from a richer
architecture and FWIW I fully support striving to make an R1 kernel binary
run with any R1-R5 hardware. It can be especially useful with platforms
that have swappable CPU modules available at different ISA levels.
> They are not trivial to fix, so I just ban them in Kconfig. I was a little bit
> reluctant to admit that in commit message.
Please always state your genuine motivation in change descriptions. It
lets reviewers understand what a change is about and if there is any
concern about the description itself, then it can always be adjusted in
the review if needed.
Maciej