2022-11-14 12:00:03

by Liu Peibao

[permalink] [raw]
Subject: [PATCH v2 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how
the 14 IRQs are wired to the platform's internal interrupt controller by
devicetree.

Signed-off-by: Liu Peibao <[email protected]>
---
.../loongarch,cpu-interrupt-controller.yaml | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
new file mode 100644
index 000000000000..2a1cf885c99d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LoongArch CPU Interrupt Controller
+
+maintainers:
+ - Liu Peibao <[email protected]>
+
+properties:
+ compatible:
+ const: loongarch,cpu-interrupt-controller
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+
+examples:
+ - |
+ interrupt-controller {
+ compatible = "loongarch,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
--
2.20.1



2022-11-15 17:30:05

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH v2 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

On 14/11/2022 12:38, Liu Peibao wrote:
> Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how
> the 14 IRQs are wired to the platform's internal interrupt controller by
> devicetree.
>
> Signed-off-by: Liu Peibao <[email protected]>
> ---


Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof


Subject: [irqchip: irq/irqchip-next] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: 6b2748ada244c7597e9b677a0bdda4e8781a8d8f
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/6b2748ada244c7597e9b677a0bdda4e8781a8d8f
Author: Liu Peibao <[email protected]>
AuthorDate: Mon, 14 Nov 2022 19:38:24 +08:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Sat, 26 Nov 2022 11:54:11

dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how
the 14 IRQs are wired to the platform's internal interrupt controller by
devicetree.

Signed-off-by: Liu Peibao <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
new file mode 100644
index 0000000..2a1cf88
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LoongArch CPU Interrupt Controller
+
+maintainers:
+ - Liu Peibao <[email protected]>
+
+properties:
+ compatible:
+ const: loongarch,cpu-interrupt-controller
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+
+examples:
+ - |
+ interrupt-controller {
+ compatible = "loongarch,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };

2022-12-08 02:19:59

by Rob Herring (Arm)

[permalink] [raw]
Subject: Re: [PATCH v2 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

On Mon, Nov 14, 2022 at 07:38:24PM +0800, Liu Peibao wrote:
> Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how
> the 14 IRQs are wired to the platform's internal interrupt controller by
> devicetree.
>
> Signed-off-by: Liu Peibao <[email protected]>
> ---
> .../loongarch,cpu-interrupt-controller.yaml | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
> new file mode 100644
> index 000000000000..2a1cf885c99d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LoongArch CPU Interrupt Controller
> +
> +maintainers:
> + - Liu Peibao <[email protected]>
> +
> +properties:
> + compatible:
> + const: loongarch,cpu-interrupt-controller

This doesn't match what the kernel is using. It has loongson rather than
loongarch. Please send an incremental fix. (Don't forget the example)

Rob

2022-12-08 03:16:56

by Liu Peibao

[permalink] [raw]
Subject: Re: [PATCH v2 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

On 12/8/22 10:09 AM, Rob Herring wrote:
> On Mon, Nov 14, 2022 at 07:38:24PM +0800, Liu Peibao wrote:
>> Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how
>> the 14 IRQs are wired to the platform's internal interrupt controller by
>> devicetree.
>>
>> Signed-off-by: Liu Peibao <[email protected]>
>> ---
>> .../loongarch,cpu-interrupt-controller.yaml | 34 +++++++++++++++++++
>> 1 file changed, 34 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
>> new file mode 100644
>> index 000000000000..2a1cf885c99d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
>> @@ -0,0 +1,34 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: LoongArch CPU Interrupt Controller
>> +
>> +maintainers:
>> + - Liu Peibao <[email protected]>
>> +
>> +properties:
>> + compatible:
>> + const: loongarch,cpu-interrupt-controller
>
> This doesn't match what the kernel is using. It has loongson rather than
> loongarch. Please send an incremental fix. (Don't forget the example)
>
> Rob
>

I will send an incremental fix.

It is much embarrassed for my careless.
Thanks!

BR,
Peibao