Introduce an interrupt controller driver for Realtek DHC (Digital Home Center) SoCs.
James Tai (6):
dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
irqchip: Add interrupt controller support for Realtek DHC SoCs
irqchip: Introduce RTD1319 support using the Realtek Common Interrupt
Controller Driver
irqchip: Introduce RTD1319D support using the Realtek Common Interrupt
Controller Driver
irqchip: Introduce RTD1325 support using the Realtek Common Interrupt
Controller Driver
irqchip: Introduce RTD1619B support using the Realtek Common Interrupt
Controller Driver
.../interrupt-controller/realtek,intc.yaml | 146 +++++++++++
drivers/irqchip/Kconfig | 28 +++
drivers/irqchip/Makefile | 5 +
drivers/irqchip/irq-realtek-intc-common.c | 232 ++++++++++++++++++
drivers/irqchip/irq-realtek-intc-common.h | 75 ++++++
drivers/irqchip/irq-realtek-rtd1319.c | 204 +++++++++++++++
drivers/irqchip/irq-realtek-rtd1319d.c | 211 ++++++++++++++++
drivers/irqchip/irq-realtek-rtd1325.c | 214 ++++++++++++++++
drivers/irqchip/irq-realtek-rtd1619b.c | 201 +++++++++++++++
9 files changed, 1316 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml
create mode 100644 drivers/irqchip/irq-realtek-intc-common.c
create mode 100644 drivers/irqchip/irq-realtek-intc-common.h
create mode 100644 drivers/irqchip/irq-realtek-rtd1319.c
create mode 100644 drivers/irqchip/irq-realtek-rtd1319d.c
create mode 100644 drivers/irqchip/irq-realtek-rtd1325.c
create mode 100644 drivers/irqchip/irq-realtek-rtd1619b.c
--
2.25.1
Add support for the RTD1319 platform.
Signed-off-by: James Tai <[email protected]>
Change-Id: I78fcc5828c7b3bd32a498b1995daf76b91b17211
---
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtd1319.c | 204 ++++++++++++++++++++++++++
3 files changed, 211 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtd1319.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 267c3429b48d..05856ce885fa 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -222,6 +222,12 @@ config REALTEK_DHC_INTC
tristate
select IRQ_DOMAIN
+config REALTEK_RTD1319_INTC
+ tristate "Realtek RTD1319 interrupt controller"
+ select REALTEK_DHC_INTC
+ help
+ Support for Realtek RTD1319 Interrupt Controller.
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index f6774af7fde2..6a2650b0a924 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_IXP4XX_IRQ) += irq-ixp4xx.o
obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
+obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-rtd1319.c b/drivers/irqchip/irq-realtek-rtd1319.c
new file mode 100644
index 000000000000..6589465801d5
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtd1319.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1319 interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "irq-realtek-intc-common.h"
+
+enum rtd1319_iso_isr_bits {
+ RTD1319_ISO_ISR_TC3_SHIFT = 1,
+ RTD1319_ISO_ISR_UR0_SHIFT = 2,
+ RTD1319_ISO_ISR_LSADC0_SHIFT = 3,
+ RTD1319_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1319_ISO_ISR_SPI1_SHIFT = 6,
+ RTD1319_ISO_ISR_WDOG_NMI_SHIFT = 7,
+ RTD1319_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1319_ISO_ISR_TC4_SHIFT = 9,
+ RTD1319_ISO_ISR_TC7_SHIFT = 10,
+ RTD1319_ISO_ISR_I2C1_SHIFT = 11,
+ RTD1319_ISO_ISR_RTC_HSEC_SHIFT = 12,
+ RTD1319_ISO_ISR_RTC_ALARM_SHIFT = 13,
+ RTD1319_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1319_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1319_ISO_ISR_ISO_MISC_SHIFT = 21,
+ RTD1319_ISO_ISR_CBUS_SHIFT = 22,
+ RTD1319_ISO_ISR_ETN_SHIFT = 23,
+ RTD1319_ISO_ISR_USB_HOST_SHIFT = 24,
+ RTD1319_ISO_ISR_USB_U3_DRD_SHIFT = 25,
+ RTD1319_ISO_ISR_USB_U2_DRD_SHIFT = 26,
+ RTD1319_ISO_ISR_PORB_HV_SHIFT = 28,
+ RTD1319_ISO_ISR_PORB_DV_SHIFT = 29,
+ RTD1319_ISO_ISR_PORB_AV_SHIFT = 30,
+ RTD1319_ISO_ISR_I2C1_REQ_SHIFT = 31,
+};
+
+static const u32 rtd1319_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1319_ISO_ISR_SPI1_SHIFT] = BIT(1),
+ [RTD1319_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1319_ISO_ISR_LSADC0_SHIFT] = BIT(3),
+ [RTD1319_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1319_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1319_ISO_ISR_I2C1_SHIFT] = BIT(11),
+ [RTD1319_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12),
+ [RTD1319_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13),
+ [RTD1319_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1319_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1319_ISO_ISR_PORB_HV_SHIFT] = BIT(28),
+ [RTD1319_ISO_ISR_PORB_DV_SHIFT] = BIT(29),
+ [RTD1319_ISO_ISR_PORB_AV_SHIFT] = BIT(30),
+ [RTD1319_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31),
+};
+
+enum rtd1319_misc_isr_bits {
+ RTD1319_ISR_WDOG_NMI_SHIFT = 2,
+ RTD1319_ISR_UR1_SHIFT = 3,
+ RTD1319_ISR_TC5_SHIFT = 4,
+ RTD1319_ISR_UR1_TO_SHIFT = 5,
+ RTD1319_ISR_TC0_SHIFT = 6,
+ RTD1319_ISR_TC1_SHIFT = 7,
+ RTD1319_ISR_UR2_SHIFT = 8,
+ RTD1319_ISR_RTC_HSEC_SHIFT = 9,
+ RTD1319_ISR_RTC_MIN_SHIFT = 10,
+ RTD1319_ISR_RTC_HOUR_SHIFT = 11,
+ RTD1319_ISR_RTC_DATE_SHIFT = 12,
+ RTD1319_ISR_UR2_TO_SHIFT = 13,
+ RTD1319_ISR_I2C5_SHIFT = 14,
+ RTD1319_ISR_I2C3_SHIFT = 23,
+ RTD1319_ISR_SC0_SHIFT = 24,
+ RTD1319_ISR_SC1_SHIFT = 25,
+ RTD1319_ISR_SPI_SHIFT = 27,
+ RTD1319_ISR_FAN_SHIFT = 29,
+};
+
+static const u32 rtd1319_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1319_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1319_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1319_ISR_UR2_TO_SHIFT] = BIT(6),
+ [RTD1319_ISR_UR2_SHIFT] = BIT(7),
+ [RTD1319_ISR_RTC_MIN_SHIFT] = BIT(10),
+ [RTD1319_ISR_RTC_HOUR_SHIFT] = BIT(11),
+ [RTD1319_ISR_RTC_DATE_SHIFT] = BIT(12),
+ [RTD1319_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1319_ISR_SC0_SHIFT] = BIT(24),
+ [RTD1319_ISR_SC1_SHIFT] = BIT(25),
+ [RTD1319_ISR_SPI_SHIFT] = BIT(27),
+ [RTD1319_ISR_I2C3_SHIFT] = BIT(28),
+ [RTD1319_ISR_FAN_SHIFT] = BIT(29),
+ [RTD1319_ISR_WDOG_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+};
+
+static struct realtek_intc_subset_cfg rtd1319_intc_iso_cfgs[] = {
+ { 0xffffcffe, }, /* normal case */
+ { 0x00003001, }, /* rtc case */
+};
+
+static const struct realtek_intc_info rtd1319_intc_iso_info = {
+ .isr_offset = 0x0,
+ .umsk_isr_offset = 0x4,
+ .scpu_int_en_offset = 0x40,
+ .isr_to_scpu_int_en_mask = rtd1319_iso_isr_to_scpu_int_en_mask,
+ .cfg = rtd1319_intc_iso_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1319_intc_iso_cfgs),
+};
+
+static struct realtek_intc_subset_cfg rtd1319_intc_misc_cfgs[] = {
+ { 0xffffc0d2, }, /* normal case */
+ { 0x00000004, }, /* nmi watchdog case */
+ { 0x00000028, }, /* uart1 case */
+ { 0x00002100, }, /* uart2 case */
+};
+
+static const struct realtek_intc_info rtd1319_intc_misc_info = {
+ .umsk_isr_offset = 0x8,
+ .isr_offset = 0xc,
+ .scpu_int_en_offset = 0x80,
+ .isr_to_scpu_int_en_mask = rtd1319_misc_isr_to_scpu_int_en_mask,
+ .cfg = rtd1319_intc_misc_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1319_intc_misc_cfgs),
+};
+
+static const struct of_device_id realtek_intc_rtd1319_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1319-intc-iso",
+ .data = &rtd1319_intc_iso_info,
+ }, {
+ .compatible = "realtek,rtd1319-intc-misc",
+ .data = &rtd1319_intc_misc_info,
+ },
+ { /* sentinel */ }
+};
+
+static int realtek_intc_rtd1319_suspend(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ data->saved_en = readl(data->base + info->scpu_int_en_offset);
+
+ writel(DISABLE_INTC, data->base + info->scpu_int_en_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+
+ return 0;
+}
+
+static int realtek_intc_rtd1319_resume(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+ writel(data->saved_en, data->base + info->scpu_int_en_offset);
+
+ return 0;
+}
+
+const struct dev_pm_ops realtek_intc_rtd1319_pm_ops = {
+ .suspend_noirq = realtek_intc_rtd1319_suspend,
+ .resume_noirq = realtek_intc_rtd1319_resume,
+};
+
+static int rtd1319_intc_probe(struct platform_device *pdev)
+{
+ const struct realtek_intc_info *info;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -EINVAL;
+
+ return realtek_intc_probe(pdev, info);
+}
+
+static struct platform_driver realtek_intc_rtd1319_driver = {
+ .probe = rtd1319_intc_probe,
+ .driver = {
+ .name = "realtek_intc_rtd1319",
+ .of_match_table = realtek_intc_rtd1319_dt_matches,
+ .suppress_bind_attrs = true,
+ .pm = &realtek_intc_rtd1319_pm_ops,
+ },
+};
+
+static int __init realtek_intc_rtd1319_init(void)
+{
+ return platform_driver_register(&realtek_intc_rtd1319_driver);
+}
+core_initcall(realtek_intc_rtd1319_init);
+
+static void __exit realtek_intc_rtd1319_exit(void)
+{
+ platform_driver_unregister(&realtek_intc_rtd1319_driver);
+}
+module_exit(realtek_intc_rtd1319_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek RTD1319 Interrupt Controller Driver");
--
2.25.1
Realtek DHC (Digital Home Center) SoCs share a common interrupt controller design.
This universal interrupt controller driver provides support for various variants
within the Realtek DHC SoC family.
Each DHC SoC features two sets of extended interrupt controllers, each capable of
handling up to 32 interrupts. These expansion controllers are connected to the GIC
(Generic Interrupt Controller).
Signed-off-by: James Tai <[email protected]>
Change-Id: I1e711c70414c97c2c8497bd4ac9e8bbd964225c3
---
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-intc-common.c | 232 ++++++++++++++++++++++
drivers/irqchip/irq-realtek-intc-common.h | 75 +++++++
4 files changed, 312 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-intc-common.c
create mode 100644 drivers/irqchip/irq-realtek-intc-common.h
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f7149d0f3d45..267c3429b48d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -218,6 +218,10 @@ config RDA_INTC
bool
select IRQ_DOMAIN
+config REALTEK_DHC_INTC
+ tristate
+ select IRQ_DOMAIN
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ffd945fe71aa..f6774af7fde2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
obj-$(CONFIG_IXP4XX_IRQ) += irq-ixp4xx.o
obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
+obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-intc-common.c b/drivers/irqchip/irq-realtek-intc-common.c
new file mode 100644
index 000000000000..2bd174f2bc2c
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-intc-common.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek DHC SoCs interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "irq-realtek-intc-common.h"
+
+struct realtek_intc_data;
+
+static unsigned int realtek_intc_get_ints(struct realtek_intc_data *data)
+{
+ return readl(data->base + data->info->isr_offset);
+}
+
+static void realtek_intc_clear_ints_bit(struct realtek_intc_data *data, int bit)
+{
+ writel(BIT(bit) & ~1, data->base + data->info->isr_offset);
+}
+
+static unsigned int realtek_intc_get_inte(struct realtek_intc_data *data)
+{
+ unsigned int val;
+ unsigned long flags;
+
+ spin_lock_irqsave(&data->lock, flags);
+ val = readl(data->base + data->info->scpu_int_en_offset);
+ spin_unlock_irqrestore(&data->lock, flags);
+
+ return val;
+}
+
+static void realtek_intc_handler(struct irq_desc *desc)
+{
+ struct realtek_intc_subset_data *subset_data = irq_desc_get_handler_data(desc);
+ struct realtek_intc_data *data = subset_data->common;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 ints, inte, mask;
+ int irq;
+
+ chained_irq_enter(chip, desc);
+
+ ints = realtek_intc_get_ints(data) & subset_data->cfg->ints_mask;
+ inte = realtek_intc_get_inte(data);
+
+ while (ints) {
+ irq = __ffs(ints);
+ ints &= ~BIT(irq);
+
+ mask = data->info->isr_to_scpu_int_en_mask[irq];
+ if (mask != IRQ_ALWAYS_ENABLED && !(inte & mask))
+ continue;
+
+ generic_handle_irq(irq_find_mapping(data->domain, irq));
+ realtek_intc_clear_ints_bit(data, irq);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void realtek_intc_mask_irq(struct irq_data *data)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
+
+ writel(BIT(data->hwirq), intc_data->base + intc_data->info->isr_offset);
+}
+
+static void realtek_intc_unmask_irq(struct irq_data *data)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
+
+ writel(BIT(data->hwirq), intc_data->base + intc_data->info->umsk_isr_offset);
+}
+
+static void realtek_intc_enable_irq(struct irq_data *data)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
+ unsigned long flags;
+ u32 scpu_int_en, mask;
+
+ mask = intc_data->info->isr_to_scpu_int_en_mask[data->hwirq];
+ if (!mask)
+ return;
+
+ spin_lock_irqsave(&intc_data->lock, flags);
+
+ scpu_int_en = readl(intc_data->base + intc_data->info->scpu_int_en_offset);
+ scpu_int_en |= mask;
+ writel(scpu_int_en, intc_data->base + intc_data->info->umsk_isr_offset);
+
+ spin_unlock_irqrestore(&intc_data->lock, flags);
+}
+
+static void realtek_intc_disable_irq(struct irq_data *data)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
+ unsigned long flags;
+ u32 scpu_int_en, mask;
+
+ mask = intc_data->info->isr_to_scpu_int_en_mask[data->hwirq];
+ if (!mask)
+ return;
+
+ spin_lock_irqsave(&intc_data->lock, flags);
+
+ scpu_int_en = readl(intc_data->base + intc_data->info->scpu_int_en_offset);
+ scpu_int_en &= ~mask;
+ writel(scpu_int_en, intc_data->base + intc_data->info->umsk_isr_offset);
+
+ spin_unlock_irqrestore(&intc_data->lock, flags);
+}
+
+static int realtek_intc_lookup_parent_irq(struct realtek_intc_data *intc_data, struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq);
+ int i;
+
+ for (i = 0; i < intc_data->subset_data_num; i++)
+ if (intc_data->subset_data[i].cfg->ints_mask & mask)
+ return intc_data->subset_data[i].parent_irq;
+
+ return -EINVAL;
+}
+
+static int realtek_intc_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force)
+{
+ struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(d);
+ int irq;
+ struct irq_chip *chip;
+ struct irq_data *data;
+
+ irq = realtek_intc_lookup_parent_irq(intc_data, d);
+ if (irq < 0)
+ return irq;
+
+ chip = irq_get_chip(irq);
+ data = irq_get_irq_data(irq);
+
+ irq_data_update_effective_affinity(d, cpu_online_mask);
+ if (chip && chip->irq_set_affinity)
+ return chip->irq_set_affinity(data, mask_val, force);
+ else
+ return -EINVAL;
+}
+
+static struct irq_chip realtek_intc_chip = {
+ .name = "realtek-intc",
+ .irq_mask = realtek_intc_mask_irq,
+ .irq_unmask = realtek_intc_unmask_irq,
+ .irq_enable = realtek_intc_enable_irq,
+ .irq_disable = realtek_intc_disable_irq,
+ .irq_set_affinity = realtek_intc_set_affinity,
+};
+
+static int realtek_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+ struct realtek_intc_data *data = d->host_data;
+
+ irq_set_chip_and_handler(irq, &realtek_intc_chip, handle_level_irq);
+ irq_set_chip_data(irq, data);
+ irq_set_probe(irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops realtek_intc_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = realtek_intc_domain_map,
+};
+
+static int realtek_intc_subset(struct device_node *node, struct realtek_intc_data *data, int index)
+{
+ int irq;
+ struct realtek_intc_subset_data *subset_data = &data->subset_data[index];
+ const struct realtek_intc_subset_cfg *cfg = &data->info->cfg[index];
+
+ irq = irq_of_parse_and_map(node, index);
+ if (irq <= 0)
+ return irq;
+
+ subset_data->common = data;
+ subset_data->cfg = cfg;
+ subset_data->parent_irq = irq;
+ irq_set_chained_handler_and_data(irq, realtek_intc_handler, subset_data);
+
+ return 0;
+}
+
+int realtek_intc_probe(struct platform_device *pdev, const struct realtek_intc_info *info)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct realtek_intc_data *data;
+ int ret, i;
+
+ data = devm_kzalloc(dev, struct_size(data, subset_data, info->cfg_num), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->base = of_iomap(node, 0);
+ if (!data->base)
+ return -ENOMEM;
+
+ data->info = info;
+
+ spin_lock_init(&data->lock);
+
+ data->domain = irq_domain_add_linear(node, 32, &realtek_intc_domain_ops, data);
+ if (!data->domain)
+ return -ENOMEM;
+
+ data->subset_data_num = info->cfg_num;
+ for (i = 0; i < info->cfg_num; i++) {
+ ret = realtek_intc_subset(node, data, i);
+ WARN(ret, "failed to init subset %d: %d", i, ret);
+ }
+
+ platform_set_drvdata(pdev, data);
+
+ return 0;
+}
+EXPORT_SYMBOL(realtek_intc_probe);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek DHC SoC Interrupt Controller Driver");
diff --git a/drivers/irqchip/irq-realtek-intc-common.h b/drivers/irqchip/irq-realtek-intc-common.h
new file mode 100644
index 000000000000..8b1954a05b41
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-intc-common.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#ifndef _IRQ_REALTEK_COMMON_H
+#define _IRQ_REALTEK_COMMON_H
+
+#include <linux/spinlock_types.h>
+
+/**
+ * realtek_intc_subset_cfg - subset interrupt mask
+ * @ints_mask: inetrrupt mask
+ */
+struct realtek_intc_subset_cfg {
+ unsigned int ints_mask;
+};
+
+/**
+ * realtek_intc_info - interrupt controller data.
+ * @isr_offset: interrupt status register offset.
+ * @umsk_isr_offset: unmask interrupt status register offset.
+ * @scpu_int_en_offset: interrupt enable register offset.
+ * @cfg: cfg of the subset.
+ * @cfg_num: number of cfg.
+ */
+struct realtek_intc_info {
+ unsigned int isr_offset;
+ unsigned int umsk_isr_offset;
+ unsigned int scpu_int_en_offset;
+ const u32 *isr_to_scpu_int_en_mask;
+ const struct realtek_intc_subset_cfg *cfg;
+ int cfg_num;
+};
+
+/**
+ * realtek_intc_subset_data - handler of a interrupt source only handles ints
+ * bits in the mask.
+ * @cfg: cfg of the subset.
+ * @common: common data.
+ * @parent_irq: interrupt source.
+ */
+struct realtek_intc_subset_data {
+ const struct realtek_intc_subset_cfg *cfg;
+ struct realtek_intc_data *common;
+ int parent_irq;
+};
+
+/**
+ * realtek_intc_data - configuration data for realtek interrupt controller driver.
+ * @base: base of interrupt register
+ * @info: info of intc
+ * @domain: interrupt domain
+ * @lock: lock
+ * @saved_en: status of interrupt enable
+ * @subset_data_num: number of subset data
+ * @subset_data: subset data
+ */
+struct realtek_intc_data {
+ void __iomem *base;
+ const struct realtek_intc_info *info;
+ struct irq_domain *domain;
+ spinlock_t lock;
+ unsigned int saved_en;
+ int subset_data_num;
+ struct realtek_intc_subset_data subset_data[];
+};
+
+#define IRQ_ALWAYS_ENABLED (-1)
+#define DISABLE_INTC (0)
+#define CLEAN_INTC_STATUS (0xfffffffe)
+
+int realtek_intc_probe(struct platform_device *pdev, const struct realtek_intc_info *info);
+
+#endif /* _IRQ_REALTEK_COMMON_H */
--
2.25.1
Add support for the RTD1619B platform.
Signed-off-by: James Tai <[email protected]>
Change-Id: I1147a27add069b86c879d15003ded2e364f11ea9
---
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtd1619b.c | 201 +++++++++++++++++++++++++
3 files changed, 208 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtd1619b.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 65e2d67d1505..c5b2762df420 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -240,6 +240,12 @@ config REALTEK_RTD1325_INTC
help
Support for Realtek RTD1325 Interrupt Controller.
+config REALTEK_RTD1619B_INTC
+ tristate "Realtek RTD1619B interrupt controller"
+ select REALTEK_DHC_INTC
+ help
+ Support for Realtek RTD1619B Interrupt Controller.
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index eaa12928d60b..da308aefcb87 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o
obj-$(CONFIG_REALTEK_RTD1319D_INTC) += irq-realtek-rtd1319d.o
obj-$(CONFIG_REALTEK_RTD1325_INTC) += irq-realtek-rtd1325.o
+obj-$(CONFIG_REALTEK_RTD1619B_INTC) += irq-realtek-rtd1619b.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-rtd1619b.c b/drivers/irqchip/irq-realtek-rtd1619b.c
new file mode 100644
index 000000000000..d76c3f113984
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtd1619b.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1619B interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "irq-realtek-intc-common.h"
+
+enum rtd1619b_iso_isr_bits {
+ RTD1619B_ISO_ISR_TC3_SHIFT = 1,
+ RTD1619B_ISO_ISR_UR0_SHIFT = 2,
+ RTD1619B_ISO_ISR_LSADC0_SHIFT = 3,
+ RTD1619B_ISO_ISR_WDOG1_NMI_SHIFT = 4,
+ RTD1619B_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1619B_ISO_ISR_SPI1_SHIFT = 6,
+ RTD1619B_ISO_ISR_WDOG2_NMI_SHIFT = 7,
+ RTD1619B_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1619B_ISO_ISR_TC4_SHIFT = 9,
+ RTD1619B_ISO_ISR_TC7_SHIFT = 10,
+ RTD1619B_ISO_ISR_I2C1_SHIFT = 11,
+ RTD1619B_ISO_ISR_HIFI_WAKEUP_SHIFT = 14,
+ RTD1619B_ISO_ISR_WDOG4_NMI_SHIFT = 15,
+ RTD1619B_ISO_ISR_TC8_SHIFT = 16,
+ RTD1619B_ISO_ISR_VFD_SHIFT = 17,
+ RTD1619B_ISO_ISR_VTC_SHIFT = 18,
+ RTD1619B_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1619B_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1619B_ISO_ISR_ISO_MISC_SHIFT = 21,
+ RTD1619B_ISO_ISR_CBUS_SHIFT = 22,
+ RTD1619B_ISO_ISR_ETN_SHIFT = 23,
+ RTD1619B_ISO_ISR_USB_HOST_SHIFT = 24,
+ RTD1619B_ISO_ISR_USB_U3_DRD_SHIFT = 25,
+ RTD1619B_ISO_ISR_USB_U2_DRD_SHIFT = 26,
+ RTD1619B_ISO_ISR_WDOG3_NMI_SHIFT = 27,
+ RTD1619B_ISO_ISR_PORB_HV_CEN_SHIFT = 28,
+ RTD1619B_ISO_ISR_PORB_DV_CEN_SHIFT = 29,
+ RTD1619B_ISO_ISR_PORB_AV_CEN_SHIFT = 30,
+ RTD1619B_ISO_ISR_I2C1_REQ_SHIFT = 31,
+};
+static const u32 rtd1619b_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1619B_ISO_ISR_SPI1_SHIFT] = BIT(1),
+ [RTD1619B_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1619B_ISO_ISR_LSADC0_SHIFT] = BIT(3),
+ [RTD1619B_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1619B_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1619B_ISO_ISR_I2C1_SHIFT] = BIT(11),
+ [RTD1619B_ISO_ISR_VFD_SHIFT] = BIT(17),
+ [RTD1619B_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1619B_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1619B_ISO_ISR_PORB_HV_CEN_SHIFT] = BIT(28),
+ [RTD1619B_ISO_ISR_PORB_DV_CEN_SHIFT] = BIT(29),
+ [RTD1619B_ISO_ISR_PORB_AV_CEN_SHIFT] = BIT(30),
+ [RTD1619B_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31),
+ [RTD1619B_ISO_ISR_WDOG1_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1619B_ISO_ISR_WDOG2_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1619B_ISO_ISR_WDOG3_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1619B_ISO_ISR_WDOG4_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+};
+enum rtd1619b_misc_isr_bits {
+ RTD1619B_ISR_UR1_SHIFT = 3,
+ RTD1619B_ISR_TC5_SHIFT = 4,
+ RTD1619B_ISR_UR1_TO_SHIFT = 5,
+ RTD1619B_ISR_TC0_SHIFT = 6,
+ RTD1619B_ISR_TC1_SHIFT = 7,
+ RTD1619B_ISR_UR2_SHIFT = 8,
+ RTD1619B_ISR_UR2_TO_SHIFT = 13,
+ RTD1619B_ISR_I2C5_SHIFT = 14,
+ RTD1619B_ISR_I2C4_SHIFT = 15,
+ RTD1619B_ISR_I2C3_SHIFT = 23,
+ RTD1619B_ISR_SC0_SHIFT = 24,
+ RTD1619B_ISR_SC1_SHIFT = 25,
+ RTD1619B_ISR_SPI_SHIFT = 27,
+ RTD1619B_ISR_FAN_SHIFT = 29,
+};
+static const u32 rtd1619b_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1619B_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1619B_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1619B_ISR_UR2_TO_SHIFT] = BIT(6),
+ [RTD1619B_ISR_UR2_SHIFT] = BIT(7),
+ [RTD1619B_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1619B_ISR_I2C4_SHIFT] = BIT(15),
+ [RTD1619B_ISR_SC0_SHIFT] = BIT(24),
+ [RTD1619B_ISR_SC1_SHIFT] = BIT(25),
+ [RTD1619B_ISR_SPI_SHIFT] = BIT(27),
+ [RTD1619B_ISR_I2C3_SHIFT] = BIT(28),
+ [RTD1619B_ISR_FAN_SHIFT] = BIT(29),
+};
+
+static struct realtek_intc_subset_cfg rtd1619b_intc_iso_cfgs[] = {
+ { 0xf7ff7f6e, }, /* normal case */
+ { 0x08008090, }, /* nmi wathdog case */
+};
+
+static const struct realtek_intc_info rtd1619b_intc_iso_info = {
+ .isr_offset = 0x0,
+ .umsk_isr_offset = 0x4,
+ .scpu_int_en_offset = 0x40,
+ .isr_to_scpu_int_en_mask = rtd1619b_iso_isr_to_scpu_int_en_mask,
+ .cfg = rtd1619b_intc_iso_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1619b_intc_iso_cfgs),
+};
+
+static struct realtek_intc_subset_cfg rtd1619b_intc_misc_cfgs[] = {
+ { 0xffffded6, }, /* normal case */
+ { 0x00000028, }, /* uart1 case */
+ { 0x00002100, }, /* uart2 case */
+};
+
+static const struct realtek_intc_info rtd1619b_intc_misc_info = {
+ .umsk_isr_offset = 0x8,
+ .isr_offset = 0xc,
+ .scpu_int_en_offset = 0x80,
+ .isr_to_scpu_int_en_mask = rtd1619b_misc_isr_to_scpu_int_en_mask,
+ .cfg = rtd1619b_intc_misc_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1619b_intc_misc_cfgs),
+};
+
+static const struct of_device_id realtek_intc_rtd1619b_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1619b-intc-iso",
+ .data = &rtd1619b_intc_iso_info,
+ }, {
+ .compatible = "realtek,rtd1619b-intc-misc",
+ .data = &rtd1619b_intc_misc_info,
+ },
+ { /* sentinel */ }
+};
+
+static int realtek_intc_rtd1619b_suspend(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ data->saved_en = readl(data->base + info->scpu_int_en_offset);
+
+ writel(DISABLE_INTC, data->base + info->scpu_int_en_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+
+ return 0;
+}
+
+static int realtek_intc_rtd1619b_resume(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+ writel(data->saved_en, data->base + info->scpu_int_en_offset);
+
+ return 0;
+}
+
+const struct dev_pm_ops realtek_intc_rtd1619b_pm_ops = {
+ .suspend_noirq = realtek_intc_rtd1619b_suspend,
+ .resume_noirq = realtek_intc_rtd1619b_resume,
+};
+
+static int rtd1619b_intc_probe(struct platform_device *pdev)
+{
+ const struct realtek_intc_info *info;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -EINVAL;
+
+ return realtek_intc_probe(pdev, info);
+}
+
+static struct platform_driver realtek_intc_rtd1619b_driver = {
+ .probe = rtd1619b_intc_probe,
+ .driver = {
+ .name = "realtek_intc_rtd1619b",
+ .of_match_table = realtek_intc_rtd1619b_dt_matches,
+ .suppress_bind_attrs = true,
+ .pm = &realtek_intc_rtd1619b_pm_ops,
+ },
+};
+
+static int __init realtek_intc_rtd1619b_init(void)
+{
+ return platform_driver_register(&realtek_intc_rtd1619b_driver);
+}
+core_initcall(realtek_intc_rtd1619b_init);
+
+static void __exit realtek_intc_rtd1619b_exit(void)
+{
+ platform_driver_unregister(&realtek_intc_rtd1619b_driver);
+}
+module_exit(realtek_intc_rtd1619b_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek RTD1619B Interrupt Controller Driver");
--
2.25.1
Add support for the RTD1319D platform.
Signed-off-by: James Tai <[email protected]>
Change-Id: I866077f0ef81ad442e0ea4ffa5f4272f07ffd675
---
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtd1319d.c | 211 +++++++++++++++++++++++++
3 files changed, 218 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtd1319d.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 05856ce885fa..c6552c513442 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -228,6 +228,12 @@ config REALTEK_RTD1319_INTC
help
Support for Realtek RTD1319 Interrupt Controller.
+config REALTEK_RTD1319D_INTC
+ tristate "Realtek RTD1319D interrupt controller"
+ select REALTEK_DHC_INTC
+ help
+ Support for Realtek RTD1319D Interrupt Controller.
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 6a2650b0a924..c8adaed4c1b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o
+obj-$(CONFIG_REALTEK_RTD1319D_INTC) += irq-realtek-rtd1319d.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-rtd1319d.c b/drivers/irqchip/irq-realtek-rtd1319d.c
new file mode 100644
index 000000000000..c76f4949181a
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtd1319d.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1319D interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "irq-realtek-intc-common.h"
+
+enum rtd1319d_iso_isr_bits {
+ RTD1319D_ISO_ISR_TC3_SHIFT = 1,
+ RTD1319D_ISO_ISR_UR0_SHIFT = 2,
+ RTD1319D_ISO_ISR_LSADC0_SHIFT = 3,
+ RTD1319D_ISO_ISR_WDOG1_NMI_SHIFT = 4,
+ RTD1319D_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1319D_ISO_ISR_SPI1_SHIFT = 6,
+ RTD1319D_ISO_ISR_WDOG2_NMI_SHIFT = 7,
+ RTD1319D_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1319D_ISO_ISR_TC4_SHIFT = 9,
+ RTD1319D_ISO_ISR_TC7_SHIFT = 10,
+ RTD1319D_ISO_ISR_I2C1_SHIFT = 11,
+ RTD1319D_ISO_ISR_HIFI_WAKEUP_SHIFT = 14,
+ RTD1319D_ISO_ISR_WDOG4_NMI_SHIFT = 15,
+ RTD1319D_ISO_ISR_TC8_SHIFT = 16,
+ RTD1319D_ISO_ISR_VFD_SHIFT = 17,
+ RTD1319D_ISO_ISR_VTC_SHIFT = 18,
+ RTD1319D_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1319D_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1319D_ISO_ISR_ISO_MISC_SHIFT = 21,
+ RTD1319D_ISO_ISR_CBUS_SHIFT = 22,
+ RTD1319D_ISO_ISR_ETN_SHIFT = 23,
+ RTD1319D_ISO_ISR_USB_HOST_SHIFT = 24,
+ RTD1319D_ISO_ISR_USB_U3_DRD_SHIFT = 25,
+ RTD1319D_ISO_ISR_USB_U2_DRD_SHIFT = 26,
+ RTD1319D_ISO_ISR_WDOG3_NMI_SHIFT = 27,
+ RTD1319D_ISO_ISR_PORB_HV_CEN_SHIFT = 28,
+ RTD1319D_ISO_ISR_PORB_DV_CEN_SHIFT = 29,
+ RTD1319D_ISO_ISR_PORB_AV_CEN_SHIFT = 30,
+ RTD1319D_ISO_ISR_I2C1_REQ_SHIFT = 31,
+};
+static const u32 rtd1319d_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1319D_ISO_ISR_SPI1_SHIFT] = BIT(1),
+ [RTD1319D_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1319D_ISO_ISR_LSADC0_SHIFT] = BIT(3),
+ [RTD1319D_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1319D_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1319D_ISO_ISR_I2C1_SHIFT] = BIT(11),
+ [RTD1319D_ISO_ISR_VFD_SHIFT] = BIT(17),
+ [RTD1319D_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1319D_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1319D_ISO_ISR_PORB_HV_CEN_SHIFT] = BIT(28),
+ [RTD1319D_ISO_ISR_PORB_DV_CEN_SHIFT] = BIT(29),
+ [RTD1319D_ISO_ISR_PORB_AV_CEN_SHIFT] = BIT(30),
+ [RTD1319D_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31),
+ [RTD1319D_ISO_ISR_WDOG1_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1319D_ISO_ISR_WDOG2_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1319D_ISO_ISR_WDOG3_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1319D_ISO_ISR_WDOG4_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+};
+enum rtd1319d_misc_isr_bits {
+ RTD1319D_ISR_UR1_SHIFT = 3,
+ RTD1319D_ISR_TC5_SHIFT = 4,
+ RTD1319D_ISR_UR1_TO_SHIFT = 5,
+ RTD1319D_ISR_TC0_SHIFT = 6,
+ RTD1319D_ISR_TC1_SHIFT = 7,
+ RTD1319D_ISR_UR2_SHIFT = 8,
+ RTD1319D_ISR_UR2_TO_SHIFT = 13,
+ RTD1319D_ISR_I2C5_SHIFT = 14,
+ RTD1319D_ISR_I2C4_SHIFT = 15,
+ RTD1319D_ISR_DRTC_HSEC_SHIFT = 16,
+ RTD1319D_ISR_DRTC_MIN_SHIFT = 17,
+ RTD1319D_ISR_DRTC_HOUR_SHIFT = 18,
+ RTD1319D_ISR_DRTC_DATE_SHIFT = 19,
+ RTD1319D_ISR_DRTC_ALARM_SHIFT = 20,
+ RTD1319D_ISR_I2C3_SHIFT = 23,
+ RTD1319D_ISR_SC0_SHIFT = 24,
+ RTD1319D_ISR_SC1_SHIFT = 25,
+ RTD1319D_ISR_SPI_SHIFT = 27,
+ RTD1319D_ISR_FAN_SHIFT = 29,
+};
+static const u32 rtd1319d_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1319D_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1319D_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1319D_ISR_UR2_TO_SHIFT] = BIT(6),
+ [RTD1319D_ISR_UR2_SHIFT] = BIT(7),
+ [RTD1319D_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1319D_ISR_I2C4_SHIFT] = BIT(15),
+ [RTD1319D_ISR_DRTC_HSEC_SHIFT] = BIT(16),
+ [RTD1319D_ISR_DRTC_MIN_SHIFT] = BIT(17),
+ [RTD1319D_ISR_DRTC_HOUR_SHIFT] = BIT(18),
+ [RTD1319D_ISR_DRTC_DATE_SHIFT] = BIT(19),
+ [RTD1319D_ISR_DRTC_ALARM_SHIFT] = BIT(20),
+ [RTD1319D_ISR_SC0_SHIFT] = BIT(24),
+ [RTD1319D_ISR_SC1_SHIFT] = BIT(25),
+ [RTD1319D_ISR_SPI_SHIFT] = BIT(27),
+ [RTD1319D_ISR_I2C3_SHIFT] = BIT(28),
+ [RTD1319D_ISR_FAN_SHIFT] = BIT(29),
+};
+
+static struct realtek_intc_subset_cfg rtd1319d_intc_iso_cfgs[] = {
+ { 0xf7ff7f6e, }, /* normal case */
+ { 0x08008090, }, /* nmi wathdog case */
+};
+
+static const struct realtek_intc_info rtd1319d_intc_iso_info = {
+ .isr_offset = 0x0,
+ .umsk_isr_offset = 0x4,
+ .scpu_int_en_offset = 0x40,
+ .isr_to_scpu_int_en_mask = rtd1319d_iso_isr_to_scpu_int_en_mask,
+ .cfg = rtd1319d_intc_iso_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1319d_intc_iso_cfgs),
+};
+
+static struct realtek_intc_subset_cfg rtd1319d_intc_misc_cfgs[] = {
+ { 0xffe0ded6, }, /* normal case */
+ { 0x00000028, }, /* uart1 case */
+ { 0x00002100, }, /* uart2 case */
+};
+
+static const struct realtek_intc_info rtd1319d_intc_misc_info = {
+ .umsk_isr_offset = 0x8,
+ .isr_offset = 0xc,
+ .scpu_int_en_offset = 0x80,
+ .isr_to_scpu_int_en_mask = rtd1319d_misc_isr_to_scpu_int_en_mask,
+ .cfg = rtd1319d_intc_misc_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1319d_intc_misc_cfgs),
+};
+
+static const struct of_device_id realtek_intc_rtd1319d_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1319d-intc-iso",
+ .data = &rtd1319d_intc_iso_info,
+ }, {
+ .compatible = "realtek,rtd1319d-intc-misc",
+ .data = &rtd1319d_intc_misc_info,
+ },
+ { /* sentinel */ }
+};
+
+static int realtek_intc_rtd1319d_suspend(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ data->saved_en = readl(data->base + info->scpu_int_en_offset);
+
+ writel(DISABLE_INTC, data->base + info->scpu_int_en_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+
+ return 0;
+}
+
+static int realtek_intc_rtd1319d_resume(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+ writel(data->saved_en, data->base + info->scpu_int_en_offset);
+
+ return 0;
+}
+
+const struct dev_pm_ops realtek_intc_rtd1319d_pm_ops = {
+ .suspend_noirq = realtek_intc_rtd1319d_suspend,
+ .resume_noirq = realtek_intc_rtd1319d_resume,
+};
+
+static int rtd1319d_intc_probe(struct platform_device *pdev)
+{
+ const struct realtek_intc_info *info;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -EINVAL;
+
+ return realtek_intc_probe(pdev, info);
+}
+
+static struct platform_driver realtek_intc_rtd1319d_driver = {
+ .probe = rtd1319d_intc_probe,
+ .driver = {
+ .name = "realtek_intc_rtd1319d",
+ .of_match_table = realtek_intc_rtd1319d_dt_matches,
+ .suppress_bind_attrs = true,
+ .pm = &realtek_intc_rtd1319d_pm_ops,
+ },
+};
+
+static int __init realtek_intc_rtd1319d_init(void)
+{
+ return platform_driver_register(&realtek_intc_rtd1319d_driver);
+}
+core_initcall(realtek_intc_rtd1319d_init);
+
+static void __exit realtek_intc_rtd1319d_exit(void)
+{
+ platform_driver_unregister(&realtek_intc_rtd1319d_driver);
+}
+module_exit(realtek_intc_rtd1319d_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek RTD1319D Interrupt Controller Driver");
--
2.25.1
Add support for the RTD1325 platform.
Signed-off-by: James Tai <[email protected]>
Change-Id: I9f1f504aa02a86449ae010993da28dc57c79dc77
---
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtd1325.c | 214 ++++++++++++++++++++++++++
3 files changed, 221 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtd1325.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c6552c513442..65e2d67d1505 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -234,6 +234,12 @@ config REALTEK_RTD1319D_INTC
help
Support for Realtek RTD1319D Interrupt Controller.
+config REALTEK_RTD1325_INTC
+ tristate "Realtek RTD1325 interrupt controller"
+ select REALTEK_DHC_INTC
+ help
+ Support for Realtek RTD1325 Interrupt Controller.
+
config RENESAS_INTC_IRQPIN
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c8adaed4c1b2..eaa12928d60b 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o
obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o
obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o
obj-$(CONFIG_REALTEK_RTD1319D_INTC) += irq-realtek-rtd1319d.o
+obj-$(CONFIG_REALTEK_RTD1325_INTC) += irq-realtek-rtd1325.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
diff --git a/drivers/irqchip/irq-realtek-rtd1325.c b/drivers/irqchip/irq-realtek-rtd1325.c
new file mode 100644
index 000000000000..4e67f1ab5073
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtd1325.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1325 interrupt controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "irq-realtek-intc-common.h"
+
+enum rtd1325_iso_isr_bits {
+ RTD1325_ISO_ISR_TC3_SHIFT = 1,
+ RTD1325_ISO_ISR_UR0_SHIFT = 2,
+ RTD1325_ISO_ISR_LSADC0_SHIFT = 3,
+ RTD1325_ISO_ISR_WDOG1_NMI_SHIFT = 4,
+ RTD1325_ISO_ISR_IRDA_SHIFT = 5,
+ RTD1325_ISO_ISR_SPI1_SHIFT = 6,
+ RTD1325_ISO_ISR_WDOG2_NMI_SHIFT = 7,
+ RTD1325_ISO_ISR_I2C0_SHIFT = 8,
+ RTD1325_ISO_ISR_TC4_SHIFT = 9,
+ RTD1325_ISO_ISR_TC7_SHIFT = 10,
+ RTD1325_ISO_ISR_I2C1_SHIFT = 11,
+ RTD1325_ISO_ISR_HIFI_WAKEUP_SHIFT = 14,
+ RTD1325_ISO_ISR_WDOG4_NMI_SHIFT = 15,
+ RTD1325_ISO_ISR_TC8_SHIFT = 16,
+ RTD1325_ISO_ISR_VFD_SHIFT = 17,
+ RTD1325_ISO_ISR_VTC_SHIFT = 18,
+ RTD1325_ISO_ISR_GPIOA_SHIFT = 19,
+ RTD1325_ISO_ISR_GPIODA_SHIFT = 20,
+ RTD1325_ISO_ISR_ISO_MISC_SHIFT = 21,
+ RTD1325_ISO_ISR_CBUS_SHIFT = 22,
+ RTD1325_ISO_ISR_ETN_SHIFT = 23,
+ RTD1325_ISO_ISR_USB_HOST_SHIFT = 24,
+ RTD1325_ISO_ISR_USB_U3_DRD_SHIFT = 25,
+ RTD1325_ISO_ISR_USB_U2_DRD_SHIFT = 26,
+ RTD1325_ISO_ISR_WDOG3_NMI_SHIFT = 27,
+ RTD1325_ISO_ISR_PORB_HV_CEN_SHIFT = 28,
+ RTD1325_ISO_ISR_PORB_DV_CEN_SHIFT = 29,
+ RTD1325_ISO_ISR_PORB_AV_CEN_SHIFT = 30,
+ RTD1325_ISO_ISR_I2C1_REQ_SHIFT = 31,
+};
+
+static const u32 rtd1325_iso_isr_to_scpu_int_en_mask[32] = {
+ [RTD1325_ISO_ISR_SPI1_SHIFT] = BIT(1),
+ [RTD1325_ISO_ISR_UR0_SHIFT] = BIT(2),
+ [RTD1325_ISO_ISR_LSADC0_SHIFT] = BIT(3),
+ [RTD1325_ISO_ISR_IRDA_SHIFT] = BIT(5),
+ [RTD1325_ISO_ISR_I2C0_SHIFT] = BIT(8),
+ [RTD1325_ISO_ISR_I2C1_SHIFT] = BIT(11),
+ [RTD1325_ISO_ISR_VFD_SHIFT] = BIT(17),
+ [RTD1325_ISO_ISR_GPIOA_SHIFT] = BIT(19),
+ [RTD1325_ISO_ISR_GPIODA_SHIFT] = BIT(20),
+ [RTD1325_ISO_ISR_PORB_HV_CEN_SHIFT] = BIT(28),
+ [RTD1325_ISO_ISR_PORB_DV_CEN_SHIFT] = BIT(29),
+ [RTD1325_ISO_ISR_PORB_AV_CEN_SHIFT] = BIT(30),
+ [RTD1325_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31),
+ [RTD1325_ISO_ISR_WDOG1_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1325_ISO_ISR_WDOG2_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1325_ISO_ISR_WDOG3_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+ [RTD1325_ISO_ISR_WDOG4_NMI_SHIFT] = IRQ_ALWAYS_ENABLED,
+};
+
+enum rtd1325_misc_isr_bits {
+ RTD1325_ISR_UR1_SHIFT = 3,
+ RTD1325_ISR_TC5_SHIFT = 4,
+ RTD1325_ISR_UR1_TO_SHIFT = 5,
+ RTD1325_ISR_TC0_SHIFT = 6,
+ RTD1325_ISR_TC1_SHIFT = 7,
+ RTD1325_ISR_UR2_SHIFT = 8,
+ RTD1325_ISR_UR2_TO_SHIFT = 13,
+ RTD1325_ISR_I2C5_SHIFT = 14,
+ RTD1325_ISR_I2C4_SHIFT = 15,
+ RTD1325_ISR_DRTC_HSEC_SHIFT = 16,
+ RTD1325_ISR_DRTC_MIN_SHIFT = 17,
+ RTD1325_ISR_DRTC_HOUR_SHIFT = 18,
+ RTD1325_ISR_DRTC_DATE_SHIFT = 19,
+ RTD1325_ISR_DRTC_ALARM_SHIFT = 20,
+ RTD1325_ISR_I2C3_SHIFT = 23,
+ RTD1325_ISR_SC0_SHIFT = 24,
+ RTD1325_ISR_SC1_SHIFT = 25,
+ RTD1325_ISR_SPI_SHIFT = 27,
+ RTD1325_ISR_FAN_SHIFT = 29,
+};
+
+static const u32 rtd1325_misc_isr_to_scpu_int_en_mask[32] = {
+ [RTD1325_ISR_UR1_SHIFT] = BIT(3),
+ [RTD1325_ISR_UR1_TO_SHIFT] = BIT(5),
+ [RTD1325_ISR_UR2_TO_SHIFT] = BIT(6),
+ [RTD1325_ISR_UR2_SHIFT] = BIT(7),
+ [RTD1325_ISR_I2C5_SHIFT] = BIT(14),
+ [RTD1325_ISR_I2C4_SHIFT] = BIT(15),
+ [RTD1325_ISR_DRTC_HSEC_SHIFT] = BIT(16),
+ [RTD1325_ISR_DRTC_MIN_SHIFT] = BIT(17),
+ [RTD1325_ISR_DRTC_HOUR_SHIFT] = BIT(18),
+ [RTD1325_ISR_DRTC_DATE_SHIFT] = BIT(19),
+ [RTD1325_ISR_DRTC_ALARM_SHIFT] = BIT(20),
+ [RTD1325_ISR_SC0_SHIFT] = BIT(24),
+ [RTD1325_ISR_SC1_SHIFT] = BIT(25),
+ [RTD1325_ISR_SPI_SHIFT] = BIT(27),
+ [RTD1325_ISR_I2C3_SHIFT] = BIT(28),
+ [RTD1325_ISR_FAN_SHIFT] = BIT(29),
+};
+
+static struct realtek_intc_subset_cfg rtd1325_intc_iso_cfgs[] = {
+ { 0xf7ff7f6e, }, /* normal case */
+ { 0x08008090, }, /* nmi wathdog case */
+};
+
+static const struct realtek_intc_info rtd1325_intc_iso_info = {
+ .isr_offset = 0x0,
+ .umsk_isr_offset = 0x4,
+ .scpu_int_en_offset = 0x40,
+ .isr_to_scpu_int_en_mask = rtd1325_iso_isr_to_scpu_int_en_mask,
+ .cfg = rtd1325_intc_iso_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1325_intc_iso_cfgs),
+};
+
+static struct realtek_intc_subset_cfg rtd1325_intc_misc_cfgs[] = {
+ { 0xffe0ded6, }, /* normal case */
+ { 0x00000028, }, /* uart1 case */
+ { 0x00002100, }, /* uart2 case */
+};
+
+static const struct realtek_intc_info rtd1325_intc_misc_info = {
+ .umsk_isr_offset = 0x8,
+ .isr_offset = 0xc,
+ .scpu_int_en_offset = 0x80,
+ .isr_to_scpu_int_en_mask = rtd1325_misc_isr_to_scpu_int_en_mask,
+ .cfg = rtd1325_intc_misc_cfgs,
+ .cfg_num = ARRAY_SIZE(rtd1325_intc_misc_cfgs),
+};
+
+static const struct of_device_id realtek_intc_rtd1325_dt_matches[] = {
+ {
+ .compatible = "realtek,rtd1325-intc-iso",
+ .data = &rtd1325_intc_iso_info,
+ }, {
+ .compatible = "realtek,rtd1325-intc-misc",
+ .data = &rtd1325_intc_misc_info,
+ },
+ { /* sentinel */ }
+};
+
+static int realtek_intc_rtd1325_suspend(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ data->saved_en = readl(data->base + info->scpu_int_en_offset);
+
+ writel(DISABLE_INTC, data->base + info->scpu_int_en_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+
+ return 0;
+}
+
+static int realtek_intc_rtd1325_resume(struct device *dev)
+{
+ struct realtek_intc_data *data = dev_get_drvdata(dev);
+ const struct realtek_intc_info *info = data->info;
+
+ writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset);
+ writel(CLEAN_INTC_STATUS, data->base + info->isr_offset);
+ writel(data->saved_en, data->base + info->scpu_int_en_offset);
+
+ return 0;
+}
+
+const struct dev_pm_ops realtek_intc_rtd1325_pm_ops = {
+ .suspend_noirq = realtek_intc_rtd1325_suspend,
+ .resume_noirq = realtek_intc_rtd1325_resume,
+};
+
+static int rtd1325_intc_probe(struct platform_device *pdev)
+{
+ const struct realtek_intc_info *info;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -EINVAL;
+
+ return realtek_intc_probe(pdev, info);
+}
+
+static struct platform_driver realtek_intc_rtd1325_driver = {
+ .probe = rtd1325_intc_probe,
+ .driver = {
+ .name = "realtek_intc_rtd1325",
+ .of_match_table = realtek_intc_rtd1325_dt_matches,
+ .suppress_bind_attrs = true,
+ .pm = &realtek_intc_rtd1325_pm_ops,
+ },
+};
+
+static int __init realtek_intc_rtd1325_init(void)
+{
+ return platform_driver_register(&realtek_intc_rtd1325_driver);
+}
+core_initcall(realtek_intc_rtd1325_init);
+
+static void __exit realtek_intc_rtd1325_exit(void)
+{
+ platform_driver_unregister(&realtek_intc_rtd1325_driver);
+}
+module_exit(realtek_intc_rtd1325_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek RTD1325 Interrupt Controller Driver");
--
2.25.1
Add the YAML documentation for Realtek DHC SoCs.
Change-Id: Ia619582e34fef6b2dbd5f98ba3f5edf70cf11dbf
Signed-off-by: James Tai <[email protected]>
---
.../interrupt-controller/realtek,intc.yaml | 146 ++++++++++++++++++
1 file changed, 146 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml
new file mode 100644
index 000000000000..cf063dcdd0b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/realtek,intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC SoCs Interrupt Controller Device Tree Bindings
+
+description:
+ This interrupt controller is a component of Realtek DHC SoCs and
+ is designed to receive interrupts from peripheral devices.
+
+ Each DHC SoC has two sets of interrupt controllers, each capable of
+ handling up to 32 interrupts.
+
+maintainers:
+ - James Tai <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ "#interrupt-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - realtek,rtd1319-intc-iso
+ - realtek,rtd1319-intc-misc
+ - realtek,rtd1319d-intc-iso
+ - realtek,rtd1319d-intc-misc
+ - realtek,rtd1325-intc-iso
+ - realtek,rtd1325-intc-misc
+ - realtek,rtd1619b-intc-iso
+ - realtek,rtd1619b-intc-misc
+
+ "#address-cells":
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts-extended:
+ minItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - "#interrupt-cells"
+ - "#address-cells"
+ - compatible
+ - interrupt-controller
+ - interrupts-extended
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ iso_irq_mux: iso_irq_mux@40 {
+ compatible = "realtek,rtd1319-intc-iso";
+ reg = <0x00 0x40>;
+ interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ misc_irq_mux: misc_irq_mux@80 {
+ compatible = "realtek,rtd1319-intc-misc";
+ reg = <0x00 0x80>;
+ interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ iso_irq_mux: iso_irq_mux@40 {
+ compatible = "realtek,rtd1319d-intc-iso";
+ reg = <0x00 0x40>;
+ interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ misc_irq_mux: misc_irq_mux@80 {
+ compatible = "realtek,rtd1319d-intc-misc";
+ reg = <0x00 0x80>;
+ interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ iso_irq_mux: iso_irq_mux@40 {
+ compatible = "realtek,rtd1325-intc-iso";
+ reg = <0x00 0x40>;
+ interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ misc_irq_mux: misc_irq_mux@80 {
+ compatible = "realtek,rtd1325-intc-misc";
+ reg = <0x00 0x80>;
+ interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ iso_irq_mux: iso_irq_mux@40 {
+ compatible = "realtek,rtd1619b-intc-iso";
+ reg = <0x00 0x40>;
+ interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ misc_irq_mux: misc_irq_mux@80 {
+ compatible = "realtek,rtd1619b-intc-misc";
+ reg = <0x00 0x80>;
+ interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+...
--
2.25.1
On 02/11/2023 15:27, James Tai wrote:
> Add the YAML documentation for Realtek DHC SoCs.
>
> Change-Id: Ia619582e34fef6b2dbd5f98ba3f5edf70cf11dbf
Please run scripts/checkpatch.pl and fix reported warnings. Some
warnings can be ignored, but the code here looks like it needs a fix.
Feel free to get in touch if the warning is not clear.
> Signed-off-by: James Tai <[email protected]>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time, thus I will skip this patch entirely till you follow
the process allowing the patch to be tested.
Please kindly resend and include all necessary To/Cc entries.
> ---
> .../interrupt-controller/realtek,intc.yaml | 146 ++++++++++++++++++
> 1 file changed, 146 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml
> new file mode 100644
> index 000000000000..cf063dcdd0b4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,intc.yaml
> @@ -0,0 +1,146 @@
> +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/realtek,intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek DHC SoCs Interrupt Controller Device Tree Bindings
It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.
Best regards,
Krzysztof
Hi James,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tip/irq/core]
[also build test WARNING on linus/master v6.6 next-20231106]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/James-Tai/dt-bindings-interrupt-controller-Add-support-for-Realtek-DHC-SoCs/20231103-074117
base: tip/irq/core
patch link: https://lore.kernel.org/r/20231102142731.2087245-5-james.tai%40realtek.com
patch subject: [PATCH 4/6] irqchip: Introduce RTD1319D support using the Realtek Common Interrupt Controller Driver
config: i386-randconfig-061-20231106 (https://download.01.org/0day-ci/archive/20231106/[email protected]/config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231106/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
sparse warnings: (new ones prefixed by >>)
>> drivers/irqchip/irq-realtek-rtd1319d.c:172:25: sparse: sparse: symbol 'realtek_intc_rtd1319d_pm_ops' was not declared. Should it be static?
vim +/realtek_intc_rtd1319d_pm_ops +172 drivers/irqchip/irq-realtek-rtd1319d.c
171
> 172 const struct dev_pm_ops realtek_intc_rtd1319d_pm_ops = {
173 .suspend_noirq = realtek_intc_rtd1319d_suspend,
174 .resume_noirq = realtek_intc_rtd1319d_resume,
175 };
176
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi James,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tip/irq/core]
[also build test WARNING on linus/master v6.6 next-20231106]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/James-Tai/dt-bindings-interrupt-controller-Add-support-for-Realtek-DHC-SoCs/20231103-074117
base: tip/irq/core
patch link: https://lore.kernel.org/r/20231102142731.2087245-4-james.tai%40realtek.com
patch subject: [PATCH 3/6] irqchip: Introduce RTD1319 support using the Realtek Common Interrupt Controller Driver
config: i386-randconfig-062-20231106 (https://download.01.org/0day-ci/archive/20231106/[email protected]/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231106/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
sparse warnings: (new ones prefixed by >>)
>> drivers/irqchip/irq-realtek-rtd1319.c:165:25: sparse: sparse: symbol 'realtek_intc_rtd1319_pm_ops' was not declared. Should it be static?
vim +/realtek_intc_rtd1319_pm_ops +165 drivers/irqchip/irq-realtek-rtd1319.c
164
> 165 const struct dev_pm_ops realtek_intc_rtd1319_pm_ops = {
166 .suspend_noirq = realtek_intc_rtd1319_suspend,
167 .resume_noirq = realtek_intc_rtd1319_resume,
168 };
169
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi James,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tip/irq/core]
[also build test WARNING on linus/master v6.6 next-20231106]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/James-Tai/dt-bindings-interrupt-controller-Add-support-for-Realtek-DHC-SoCs/20231103-074117
base: tip/irq/core
patch link: https://lore.kernel.org/r/20231102142731.2087245-6-james.tai%40realtek.com
patch subject: [PATCH 5/6] irqchip: Introduce RTD1325 support using the Realtek Common Interrupt Controller Driver
config: i386-randconfig-061-20231106 (https://download.01.org/0day-ci/archive/20231106/[email protected]/config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231106/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
sparse warnings: (new ones prefixed by >>)
>> drivers/irqchip/irq-realtek-rtd1325.c:175:25: sparse: sparse: symbol 'realtek_intc_rtd1325_pm_ops' was not declared. Should it be static?
vim +/realtek_intc_rtd1325_pm_ops +175 drivers/irqchip/irq-realtek-rtd1325.c
174
> 175 const struct dev_pm_ops realtek_intc_rtd1325_pm_ops = {
176 .suspend_noirq = realtek_intc_rtd1325_suspend,
177 .resume_noirq = realtek_intc_rtd1325_resume,
178 };
179
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi James,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tip/irq/core]
[also build test WARNING on linus/master v6.6 next-20231106]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/James-Tai/dt-bindings-interrupt-controller-Add-support-for-Realtek-DHC-SoCs/20231103-074117
base: tip/irq/core
patch link: https://lore.kernel.org/r/20231102142731.2087245-7-james.tai%40realtek.com
patch subject: [PATCH 6/6] irqchip: Introduce RTD1619B support using the Realtek Common Interrupt Controller Driver
config: i386-randconfig-061-20231106 (https://download.01.org/0day-ci/archive/20231106/[email protected]/config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231106/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
sparse warnings: (new ones prefixed by >>)
>> drivers/irqchip/irq-realtek-rtd1619b.c:162:25: sparse: sparse: symbol 'realtek_intc_rtd1619b_pm_ops' was not declared. Should it be static?
vim +/realtek_intc_rtd1619b_pm_ops +162 drivers/irqchip/irq-realtek-rtd1619b.c
161
> 162 const struct dev_pm_ops realtek_intc_rtd1619b_pm_ops = {
163 .suspend_noirq = realtek_intc_rtd1619b_suspend,
164 .resume_noirq = realtek_intc_rtd1619b_resume,
165 };
166
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Thu, Nov 02 2023 at 22:27, James Tai wrote:
> Realtek DHC (Digital Home Center) SoCs share a common interrupt controller design.
> This universal interrupt controller driver provides support for various variants
> within the Realtek DHC SoC family.
>
> Each DHC SoC features two sets of extended interrupt controllers, each capable of
> handling up to 32 interrupts. These expansion controllers are connected to the GIC
> (Generic Interrupt Controller).
>
> Signed-off-by: James Tai <[email protected]>
> Change-Id: I1e711c70414c97c2c8497bd4ac9e8bbd964225c3
Please remove these internal change ids. They are not useful for anyone
outside realtek.
> +config REALTEK_DHC_INTC
> + tristate
> + select IRQ_DOMAIN
> +
> +static unsigned int realtek_intc_get_ints(struct realtek_intc_data *data)
static inline perhaps?
> +{
> + return readl(data->base + data->info->isr_offset);
> +}
> +
> +static void realtek_intc_clear_ints_bit(struct realtek_intc_data *data, int bit)
> +{
> + writel(BIT(bit) & ~1, data->base + data->info->isr_offset);
> +}
> +
> +static unsigned int realtek_intc_get_inte(struct realtek_intc_data *data)
> +{
> + unsigned int val;
> + unsigned long flags;
unsigned long flags;
unsigned int val;
https://www.kernel.org/doc/html/latest/process/maintainer-tip.html
Please fix the variable declarations all over the place.
> + spin_lock_irqsave(&data->lock, flags);
This needs to be a raw spinlock.
> + val = readl(data->base + data->info->scpu_int_en_offset);
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return val;
> +}
> +static void realtek_intc_enable_irq(struct irq_data *data)
> +{
> + struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
> + unsigned long flags;
> + u32 scpu_int_en, mask;
See above.
> +
> + mask = intc_data->info->isr_to_scpu_int_en_mask[data->hwirq];
> + if (!mask)
> + return;
> +
> + spin_lock_irqsave(&intc_data->lock, flags);
> +
> + scpu_int_en = readl(intc_data->base + intc_data->info->scpu_int_en_offset);
> + scpu_int_en |= mask;
> + writel(scpu_int_en, intc_data->base + intc_data->info->umsk_isr_offset);
> +
> + spin_unlock_irqrestore(&intc_data->lock, flags);
> +}
> +
> +static void realtek_intc_disable_irq(struct irq_data *data)
> +{
> + struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(data);
> + unsigned long flags;
> + u32 scpu_int_en, mask;
> +
> + mask = intc_data->info->isr_to_scpu_int_en_mask[data->hwirq];
> + if (!mask)
> + return;
> +
> + spin_lock_irqsave(&intc_data->lock, flags);
> +
> + scpu_int_en = readl(intc_data->base + intc_data->info->scpu_int_en_offset);
> + scpu_int_en &= ~mask;
> + writel(scpu_int_en, intc_data->base + intc_data->info->umsk_isr_offset);
> +
> + spin_unlock_irqrestore(&intc_data->lock, flags);
> +}
> +
> +static int realtek_intc_lookup_parent_irq(struct realtek_intc_data *intc_data, struct irq_data *d)
> +{
> + unsigned int mask = BIT(d->hwirq);
> + int i;
> +
> + for (i = 0; i < intc_data->subset_data_num; i++)
> + if (intc_data->subset_data[i].cfg->ints_mask & mask)
> + return intc_data->subset_data[i].parent_irq;
Lacks brackets around the for loop. See documentation.
> +
> + return -EINVAL;
> +}
> +
> +static int realtek_intc_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force)
> +{
> + struct realtek_intc_data *intc_data = irq_data_get_irq_chip_data(d);
> + int irq;
> + struct irq_chip *chip;
> + struct irq_data *data;
> +
> + irq = realtek_intc_lookup_parent_irq(intc_data, d);
> + if (irq < 0)
> + return irq;
> +
> + chip = irq_get_chip(irq);
> + data = irq_get_irq_data(irq);
So instead of two lookups you want to do:
data = irq_get_irq_data(irq);
if (!data)
return;
chip = irq_data_get_irq_chip(data);
...
> +
> + irq_data_update_effective_affinity(d, cpu_online_mask);
So you update the effective affinity even if it cannot be set or if the
parent irq returns an error code?
Aside of that setting it to cpu_online mask is just wrong. This is _NOT_
the effective affinity because the underlying GIC selects a single
target CPU out of the caller provides cpu mask.
That said, this is also completely inconsistent vs. the other interrupts
which share that GIC interrupt instance. I.e. /proc/irq/$N/affinity and
effective_affinity become random number generators. That'll confuse
existing userspace tools.
Having an affinity setter for demultiplexes interrupts is simply wrong.
> + if (chip && chip->irq_set_affinity)
> + return chip->irq_set_affinity(data, mask_val, force);
> + else
> + return -EINVAL;
> +}
> +
> +static struct irq_chip realtek_intc_chip = {
> + .name = "realtek-intc",
> + .irq_mask = realtek_intc_mask_irq,
> + .irq_unmask = realtek_intc_unmask_irq,
> + .irq_enable = realtek_intc_enable_irq,
> + .irq_disable = realtek_intc_disable_irq,
> + .irq_set_affinity = realtek_intc_set_affinity,
See docs vs. formatting of struct initializers.
> +};
> +
> +
> + data->subset_data_num = info->cfg_num;
> + for (i = 0; i < info->cfg_num; i++) {
> + ret = realtek_intc_subset(node, data, i);
> + WARN(ret, "failed to init subset %d: %d", i, ret);
If this fails, then you still expose the affected interrupts as
functional?
> +/**
> + * realtek_intc_subset_cfg - subset interrupt mask
> + * @ints_mask: inetrrupt mask
> + */
> +struct realtek_intc_subset_cfg {
> + unsigned int ints_mask;
> +};
> +
> +/**
> + * realtek_intc_info - interrupt controller data.
> + * @isr_offset: interrupt status register offset.
> + * @umsk_isr_offset: unmask interrupt status register offset.
> + * @scpu_int_en_offset: interrupt enable register offset.
> + * @cfg: cfg of the subset.
> + * @cfg_num: number of cfg.
> + */
> +struct realtek_intc_info {
> + unsigned int isr_offset;
> + unsigned int umsk_isr_offset;
> + unsigned int scpu_int_en_offset;
> + const u32 *isr_to_scpu_int_en_mask;
> + const struct realtek_intc_subset_cfg *cfg;
> + int cfg_num;
See formatting doc.
> +
> +#define IRQ_ALWAYS_ENABLED (-1)
U32_MAX ?
> +#define DISABLE_INTC (0)
> +#define CLEAN_INTC_STATUS (0xfffffffe)
That's what GENMASK() is for.
Thanks,
tglx
On Thu, Nov 02 2023 at 22:27, James Tai wrote:
> +
> +enum rtd1319_iso_isr_bits {
> + RTD1319_ISO_ISR_TC3_SHIFT = 1,
> + RTD1319_ISO_ISR_UR0_SHIFT = 2,
Please use tabular formatting all over the place.
> + RTD1319_ISO_ISR_LSADC0_SHIFT = 3,
> + RTD1319_ISO_ISR_IRDA_SHIFT = 5,
> +
> +static const struct realtek_intc_info rtd1319_intc_iso_info = {
> + .isr_offset = 0x0,
> + .umsk_isr_offset = 0x4,
> + .scpu_int_en_offset = 0x40,
Magic numbers. Defines exist for a reason.
Hi Krzysztof,
>
>Please run scripts/checkpatch.pl and fix reported warnings. Some warnings can
>be ignored, but the code here looks like it needs a fix.
>Feel free to get in touch if the warning is not clear.
>
I will run checkpatch.pl to address and fix the reported warnings.
>Please use scripts/get_maintainers.pl to get a list of necessary people and lists
>to CC. It might happen, that command when run on an older kernel, gives you
>outdated entries. Therefore please be sure you base your patches on recent
>Linux kernel.
>
>You missed at least devicetree list (maybe more), so this won't be tested by
>automated tooling. Performing review on untested code might be a waste of
>time, thus I will skip this patch entirely till you follow the process allowing the
>patch to be tested.
>
>Please kindly resend and include all necessary To/Cc entries.
I will fix it in the next patches.
>
>It does not look like you tested the bindings, at least after quick look. Please run
>`make dt_binding_check` (see
>Documentation/devicetree/bindings/writing-schema.rst for instructions).
>Maybe you need to update your dtschema and yamllint.
>
I will test the bindings using 'make dt_binding_check'.
Thank you for your feedback.
Regards,
James
On 16/11/2023 15:37, James Tai [戴志峰] wrote:
> Hi Krzysztof,
>
>>
>> Please run scripts/checkpatch.pl and fix reported warnings. Some warnings can
>> be ignored, but the code here looks like it needs a fix.
>> Feel free to get in touch if the warning is not clear.
>>
>
> I will run checkpatch.pl to address and fix the reported warnings.
>
>> Please use scripts/get_maintainers.pl to get a list of necessary people and lists
>> to CC. It might happen, that command when run on an older kernel, gives you
>> outdated entries. Therefore please be sure you base your patches on recent
>> Linux kernel.
>>
>> You missed at least devicetree list (maybe more), so this won't be tested by
>> automated tooling. Performing review on untested code might be a waste of
>> time, thus I will skip this patch entirely till you follow the process allowing the
>> patch to be tested.
>>
>> Please kindly resend and include all necessary To/Cc entries.
>
> I will fix it in the next patches.
>
>>
>> It does not look like you tested the bindings, at least after quick look. Please run
>> `make dt_binding_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>> Maybe you need to update your dtschema and yamllint.
>>
> I will test the bindings using 'make dt_binding_check'.
Please do all above before submitting patches.
Best regards,
Krzysztof
Hi Thomas,
>> Signed-off-by: James Tai <[email protected]>
>> Change-Id: I1e711c70414c97c2c8497bd4ac9e8bbd964225c3
>
>Please remove these internal change ids. They are not useful for anyone outside
>realtek.
>
I will fix it in the next patches.
>
>> +static unsigned int realtek_intc_get_ints(struct realtek_intc_data
>> +*data)
>
>static inline perhaps?
>
Yes. I will use 'static inline' to replace it.
>> +static unsigned int realtek_intc_get_inte(struct realtek_intc_data
>> +*data) {
>> + unsigned int val;
>> + unsigned long flags;
>
> unsigned long flags;
> unsigned int val;
>
>https://www.kernel.org/doc/html/latest/process/maintainer-tip.html
>
>Please fix the variable declarations all over the place.
>
I will fix it in the next patches.
>> + spin_lock_irqsave(&data->lock, flags);
>
>This needs to be a raw spinlock.
>
I will fix it in the next patches.
>
>
>> +static void realtek_intc_enable_irq(struct irq_data *data) {
>> + struct realtek_intc_data *intc_data =
>irq_data_get_irq_chip_data(data);
>> + unsigned long flags;
>> + u32 scpu_int_en, mask;
>
>See above.
>
I will fix it in the next patches.
>
>So you update the effective affinity even if it cannot be set or if the parent irq
>returns an error code?
>
>Aside of that setting it to cpu_online mask is just wrong. This is _NOT_ the
>effective affinity because the underlying GIC selects a single target CPU out of
>the caller provides cpu mask.
>
>That said, this is also completely inconsistent vs. the other interrupts which
>share that GIC interrupt instance. I.e. /proc/irq/$N/affinity and effective_affinity
>become random number generators. That'll confuse existing userspace tools.
>
>Having an affinity setter for demultiplexes interrupts is simply wrong.
>
I will use the 'irq_chip_set_affinity_parent' replace the 'realtek_intc_set_affinity'.
>> +static struct irq_chip realtek_intc_chip = {
>> + .name = "realtek-intc",
>> + .irq_mask = realtek_intc_mask_irq,
>> + .irq_unmask = realtek_intc_unmask_irq,
>> + .irq_enable = realtek_intc_enable_irq,
>> + .irq_disable = realtek_intc_disable_irq,
>> + .irq_set_affinity = realtek_intc_set_affinity,
>
>See docs vs. formatting of struct initializers.
>
I will fix it in the next patches.
>> +};
>> +
>> +
>> + data->subset_data_num = info->cfg_num;
>> + for (i = 0; i < info->cfg_num; i++) {
>> + ret = realtek_intc_subset(node, data, i);
>> + WARN(ret, "failed to init subset %d: %d", i, ret);
>
>If this fails, then you still expose the affected interrupts as functional?
I will modify the code to return an error code and stop the driver initialization.
>
>> +/**
>> + * realtek_intc_subset_cfg - subset interrupt mask
>> + * @ints_mask: inetrrupt mask
>> + */
>> +struct realtek_intc_subset_cfg {
>> + unsigned int ints_mask;
>> +};
>> +
>> +/**
>> + * realtek_intc_info - interrupt controller data.
>> + * @isr_offset: interrupt status register offset.
>> + * @umsk_isr_offset: unmask interrupt status register offset.
>> + * @scpu_int_en_offset: interrupt enable register offset.
>> + * @cfg: cfg of the subset.
>> + * @cfg_num: number of cfg.
>> + */
>> +struct realtek_intc_info {
>> + unsigned int isr_offset;
>> + unsigned int umsk_isr_offset;
>> + unsigned int scpu_int_en_offset;
>> + const u32 *isr_to_scpu_int_en_mask;
>> + const struct realtek_intc_subset_cfg *cfg;
>> + int cfg_num;
>
>See formatting doc.
I will fix it in the next patches.
>> +
>> +#define IRQ_ALWAYS_ENABLED (-1)
>
>U32_MAX ?
>
I will use 'U32_MAX' to replace '-1'.
>> +#define DISABLE_INTC (0)
>> +#define CLEAN_INTC_STATUS (0xfffffffe)
>
>That's what GENMASK() is for.
>
I will use ' GENMASK(31, 1) ' to replace '0xfffffffe '.
Thank you for your feedback.
Regards,
James
Hi Thomas,
>> +enum rtd1319_iso_isr_bits {
>> + RTD1319_ISO_ISR_TC3_SHIFT = 1,
>> + RTD1319_ISO_ISR_UR0_SHIFT = 2,
>
>Please use tabular formatting all over the place.
I will fix it in the next patches.
>
>> + RTD1319_ISO_ISR_LSADC0_SHIFT = 3,
>> + RTD1319_ISO_ISR_IRDA_SHIFT = 5,
>> +
>
>
>> +static const struct realtek_intc_info rtd1319_intc_iso_info = {
>> + .isr_offset = 0x0,
>> + .umsk_isr_offset = 0x4,
>> + .scpu_int_en_offset = 0x40,
>
>Magic numbers. Defines exist for a reason.
I will fix it in the next patches.
Thank you for your feedback.
Regards,
James
>>So you update the effective affinity even if it cannot be set or if the
>>parent irq returns an error code?
>>
>>Aside of that setting it to cpu_online mask is just wrong. This is
>>_NOT_ the effective affinity because the underlying GIC selects a
>>single target CPU out of the caller provides cpu mask.
>>
>>That said, this is also completely inconsistent vs. the other
>>interrupts which share that GIC interrupt instance. I.e.
>>/proc/irq/$N/affinity and effective_affinity become random number generators.
>That'll confuse existing userspace tools.
>>
>>Having an affinity setter for demultiplexes interrupts is simply wrong.
>>
>I will use the 'irq_chip_set_affinity_parent' replace the
>'realtek_intc_set_affinity'.
I will remove the capability to set CPU affinity.
Regards,
James