Set PLL0 rate to 1.5GHz. Change the parent of cpu_root clock
and the divider of cpu_core before setting.
Signed-off-by: Xingyu Wu <[email protected]>
---
Hi Stephen and Emil,
This patch sets PLL0 rate to 1.5GHz. In order not to affect the cpu
operation, the cpu_root's parent clock should be changed first.
And the divider of the cpu_core clock should be set to 2 so they
won't crash when setting 1.5GHz without voltage regulation.
This patch is based on linux-next which has merge PLL driver on
StarFive JH7110 SoC.
Thanks,
Xingyu Wu
---
.../clk/starfive/clk-starfive-jh7110-sys.c | 47 ++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 3884eff9fe93..b6b9e967dfc7 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -501,7 +501,52 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
if (ret)
return ret;
- return jh7110_reset_controller_register(priv, "rst-sys", 0);
+ ret = jh7110_reset_controller_register(priv, "rst-sys", 0);
+ if (ret)
+ return ret;
+
+ /*
+ * Set PLL0 rate to 1.5GHz
+ * In order to not affect the cpu when the PLL0 rate is changing,
+ * we need to switch the parent of cpu_root clock to osc clock first,
+ * and then switch back after setting the PLL0 rate.
+ */
+ pllclk = clk_get(priv->dev, "pll0_out");
+ if (!IS_ERR(pllclk)) {
+ struct clk *osc = clk_get(&pdev->dev, "osc");
+ struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
+ struct clk *cpu_core = priv->reg[JH7110_SYSCLK_CPU_CORE].hw.clk;
+
+ if (IS_ERR(osc)) {
+ clk_put(pllclk);
+ return PTR_ERR(osc);
+ }
+
+ /*
+ * CPU need voltage regulation by CPUfreq if set 1.5GHz.
+ * So in this driver, cpu_core need to be set the divider to be 2 first
+ * and will be 750M after setting parent.
+ */
+ ret = clk_set_rate(cpu_core, clk_get_rate(cpu_core) / 2);
+ if (ret)
+ goto failed_set;
+
+ ret = clk_set_parent(cpu_root, osc);
+ if (ret)
+ goto failed_set;
+
+ ret = clk_set_rate(pllclk, 1500000000);
+ if (ret)
+ goto failed_set;
+
+ ret = clk_set_parent(cpu_root, pllclk);
+
+failed_set:
+ clk_put(pllclk);
+ clk_put(osc);
+ }
+
+ return ret;
}
static const struct of_device_id jh7110_syscrg_match[] = {
--
2.25.1
On Fri, Aug 11, 2023 at 11:36:31AM +0800, Xingyu Wu wrote:
> Set PLL0 rate to 1.5GHz.
Why are you doing that though?
> Change the parent of cpu_root clock
> and the divider of cpu_core before setting.
>
> Signed-off-by: Xingyu Wu <[email protected]>
> ---
>
> Hi Stephen and Emil,
>
> This patch sets PLL0 rate to 1.5GHz. In order not to affect the cpu
> operation, the cpu_root's parent clock should be changed first.
> And the divider of the cpu_core clock should be set to 2 so they
> won't crash when setting 1.5GHz without voltage regulation.
>
> This patch is based on linux-next which has merge PLL driver on
> StarFive JH7110 SoC.
>
> Thanks,
> Xingyu Wu
On 2023/8/11 14:43, Conor Dooley wrote:
> On Fri, Aug 11, 2023 at 11:36:31AM +0800, Xingyu Wu wrote:
>> Set PLL0 rate to 1.5GHz.
>
> Why are you doing that though?
Because the CPU frequency scaling is based on 1.5GHz rate on JH7110 SoC.
And now the PLL clock driver has been accepted and PLL0 is just 1GHz[1].
[1] https://github.com/starfive-tech/VisionFive2/issues/55
We should set the PLL0 rate to a correct rate (1.5GHz) and then
the CPUfreq will work normally.
Best regards,
Xingyu Wu
>
>
>> Change the parent of cpu_root clock
>> and the divider of cpu_core before setting.
>>
>> Signed-off-by: Xingyu Wu <[email protected]>
>> ---
>>
>> Hi Stephen and Emil,
>>
>> This patch sets PLL0 rate to 1.5GHz. In order not to affect the cpu
>> operation, the cpu_root's parent clock should be changed first.
>> And the divider of the cpu_core clock should be set to 2 so they
>> won't crash when setting 1.5GHz without voltage regulation.
>>
>> This patch is based on linux-next which has merge PLL driver on
>> StarFive JH7110 SoC.
>>
>> Thanks,
>> Xingyu Wu
On Mon, Aug 14, 2023 at 11:06:05AM +0800, Xingyu Wu wrote:
> On 2023/8/11 14:43, Conor Dooley wrote:
> > On Fri, Aug 11, 2023 at 11:36:31AM +0800, Xingyu Wu wrote:
> >> Set PLL0 rate to 1.5GHz.
> >
> > Why are you doing that though?
>
> Because the CPU frequency scaling is based on 1.5GHz rate on JH7110 SoC.
> And now the PLL clock driver has been accepted and PLL0 is just 1GHz[1].
> [1] https://github.com/starfive-tech/VisionFive2/issues/55
>
> We should set the PLL0 rate to a correct rate (1.5GHz) and then
> the CPUfreq will work normally.
Please include an explanation in the commit message of the problem this
is addressing.
Also, a Fixes: tag + reported-by?
> Best regards,
> Xingyu Wu
>
> >
> >
> >> Change the parent of cpu_root clock
> >> and the divider of cpu_core before setting.
> >>
> >> Signed-off-by: Xingyu Wu <[email protected]>
> >> ---
> >>
> >> Hi Stephen and Emil,
> >>
> >> This patch sets PLL0 rate to 1.5GHz. In order not to affect the cpu
> >> operation, the cpu_root's parent clock should be changed first.
> >> And the divider of the cpu_core clock should be set to 2 so they
> >> won't crash when setting 1.5GHz without voltage regulation.
> >>
> >> This patch is based on linux-next which has merge PLL driver on
> >> StarFive JH7110 SoC.
> >>
> >> Thanks,
> >> Xingyu Wu
>
On 2023/8/14 14:57, Conor Dooley wrote:
> On Mon, Aug 14, 2023 at 11:06:05AM +0800, Xingyu Wu wrote:
>> On 2023/8/11 14:43, Conor Dooley wrote:
>> > On Fri, Aug 11, 2023 at 11:36:31AM +0800, Xingyu Wu wrote:
>> >> Set PLL0 rate to 1.5GHz.
>> >
>> > Why are you doing that though?
>>
>> Because the CPU frequency scaling is based on 1.5GHz rate on JH7110 SoC.
>> And now the PLL clock driver has been accepted and PLL0 is just 1GHz[1].
>> [1] https://github.com/starfive-tech/VisionFive2/issues/55
>>
>> We should set the PLL0 rate to a correct rate (1.5GHz) and then
>> the CPUfreq will work normally.
>
> Please include an explanation in the commit message of the problem this
> is addressing.
>
> Also, a Fixes: tag + reported-by?
>
OK, I will add the explanation in next version as a fixes patch.
Thanks,
Xingyu Wu
>> >
>> >
>> >> Change the parent of cpu_root clock
>> >> and the divider of cpu_core before setting.
>> >>
>> >> Signed-off-by: Xingyu Wu <[email protected]>
>> >> ---
>> >>
>> >> Hi Stephen and Emil,
>> >>
>> >> This patch sets PLL0 rate to 1.5GHz. In order not to affect the cpu
>> >> operation, the cpu_root's parent clock should be changed first.
>> >> And the divider of the cpu_core clock should be set to 2 so they
>> >> won't crash when setting 1.5GHz without voltage regulation.
>> >>
>> >> This patch is based on linux-next which has merge PLL driver on
>> >> StarFive JH7110 SoC.
>> >>
>> >> Thanks,
>> >> Xingyu Wu
>>
On Fri, 11 Aug 2023 11:36:31 +0800, Xingyu Wu wrote:
> Set PLL0 rate to 1.5GHz. Change the parent of cpu_root clock
> and the divider of cpu_core before setting.
>
> Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Hal Feng <[email protected]>