On Thu, Jun 1, 2017 at 1:37 AM,
<[email protected]> wrote:
> From: Kuppuswamy Sathyanarayanan <[email protected]>
>
> PMIC mfd driver only exports first level irq for thermal device.
> But currently we are reading the irqs from the second level irq
> chip, So this patch fixes this issue by adding support to use
> first level PMIC thermal irq.
>
Shouldn't be this squashed to patch 2?
> Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
> Acked-by: Zhang Rui <[email protected]>
> ---
> drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Changes since v1:
> * None
>
> Changes since v2:
> * Rebased on top of latest release.
>
> Changes since v3:
> * Rebased on top of latest release.
>
> diff --git a/drivers/thermal/intel_bxt_pmic_thermal.c b/drivers/thermal/intel_bxt_pmic_thermal.c
> index 0f19a39..ef6b322 100644
> --- a/drivers/thermal/intel_bxt_pmic_thermal.c
> +++ b/drivers/thermal/intel_bxt_pmic_thermal.c
> @@ -241,7 +241,7 @@ static int pmic_thermal_probe(struct platform_device *pdev)
> }
>
> regmap = pmic->regmap;
> - regmap_irq_chip = pmic->irq_chip_data_level2;
> + regmap_irq_chip = pmic->irq_chip_data;
>
> pmic_irq_count = 0;
> while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
> --
> 2.7.4
>
--
With Best Regards,
Andy Shevchenko
Hi,
On Sat, Jun 3, 2017 at 6:00 AM, Andy Shevchenko
<[email protected]> wrote:
> On Thu, Jun 1, 2017 at 1:37 AM,
> <[email protected]> wrote:
>> From: Kuppuswamy Sathyanarayanan <[email protected]>
>>
>> PMIC mfd driver only exports first level irq for thermal device.
>> But currently we are reading the irqs from the second level irq
>> chip, So this patch fixes this issue by adding support to use
>> first level PMIC thermal irq.
>>
>
> Shouldn't be this squashed to patch 2?
There is no compilation dependency between patch 2 and 3. But they are
functionally dependent.
Should we squash functionally dependent patches too ?
>
>> Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
>> Acked-by: Zhang Rui <[email protected]>
>> ---
>> drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> Changes since v1:
>> * None
>>
>> Changes since v2:
>> * Rebased on top of latest release.
>>
>> Changes since v3:
>> * Rebased on top of latest release.
>>
>> diff --git a/drivers/thermal/intel_bxt_pmic_thermal.c b/drivers/thermal/intel_bxt_pmic_thermal.c
>> index 0f19a39..ef6b322 100644
>> --- a/drivers/thermal/intel_bxt_pmic_thermal.c
>> +++ b/drivers/thermal/intel_bxt_pmic_thermal.c
>> @@ -241,7 +241,7 @@ static int pmic_thermal_probe(struct platform_device *pdev)
>> }
>>
>> regmap = pmic->regmap;
>> - regmap_irq_chip = pmic->irq_chip_data_level2;
>> + regmap_irq_chip = pmic->irq_chip_data;
>>
>> pmic_irq_count = 0;
>> while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
>> --
>> 2.7.4
>>
>
>
>
> --
> With Best Regards,
> Andy Shevchenko
--
Sathya
On Sat, Jun 3, 2017 at 8:28 PM, Sathyanarayanan Kuppuswamy Natarajan
<[email protected]> wrote:
> Hi,
>
> On Sat, Jun 3, 2017 at 6:00 AM, Andy Shevchenko
> <[email protected]> wrote:
>> On Thu, Jun 1, 2017 at 1:37 AM,
>> <[email protected]> wrote:
>>> From: Kuppuswamy Sathyanarayanan <[email protected]>
>>>
>>> PMIC mfd driver only exports first level irq for thermal device.
>>> But currently we are reading the irqs from the second level irq
>>> chip, So this patch fixes this issue by adding support to use
>>> first level PMIC thermal irq.
>>>
>>
>> Shouldn't be this squashed to patch 2?
>
> There is no compilation dependency between patch 2 and 3. But they are
> functionally dependent.
>
> Should we squash functionally dependent patches too ?
Let's assume we applied patches 1 and 2, does it mean the regression
to the existing behaviour?
(For example, device worked improperly in some cases -> stopped
working completely)
--
With Best Regards,
Andy Shevchenko
Hi,
On Sat, Jun 3, 2017 at 10:32 AM, Andy Shevchenko
<[email protected]> wrote:
> On Sat, Jun 3, 2017 at 8:28 PM, Sathyanarayanan Kuppuswamy Natarajan
> <[email protected]> wrote:
>> Hi,
>>
>> On Sat, Jun 3, 2017 at 6:00 AM, Andy Shevchenko
>> <[email protected]> wrote:
>>> On Thu, Jun 1, 2017 at 1:37 AM,
>>> <[email protected]> wrote:
>>>> From: Kuppuswamy Sathyanarayanan <[email protected]>
>>>>
>>>> PMIC mfd driver only exports first level irq for thermal device.
>>>> But currently we are reading the irqs from the second level irq
>>>> chip, So this patch fixes this issue by adding support to use
>>>> first level PMIC thermal irq.
>>>>
>>>
>>> Shouldn't be this squashed to patch 2?
>>
>> There is no compilation dependency between patch 2 and 3. But they are
>> functionally dependent.
>>
>> Should we squash functionally dependent patches too ?
>
> Let's assume we applied patches 1 and 2, does it mean the regression
> to the existing behaviour?
Yes, Just applying patch 1 & 2 and not apply patch 3 will create
regression in thermal driver.
Since there is no compilation dependency between patch 2 & 3 and they
are from two different domains, I submitted them separately to make it
easier for review.
>
> (For example, device worked improperly in some cases -> stopped
> working completely)
>
> --
> With Best Regards,
> Andy Shevchenko
--
Sathya
On Sat, Jun 3, 2017 at 8:53 PM, Sathyanarayanan Kuppuswamy Natarajan
<[email protected]> wrote:
> On Sat, Jun 3, 2017 at 10:32 AM, Andy Shevchenko
> <[email protected]> wrote:
>> On Sat, Jun 3, 2017 at 8:28 PM, Sathyanarayanan Kuppuswamy Natarajan
>> <[email protected]> wrote:
>> Let's assume we applied patches 1 and 2, does it mean the regression
>> to the existing behaviour?
>
> Yes, Just applying patch 1 & 2 and not apply patch 3 will create
> regression in thermal driver.
>
> Since there is no compilation dependency between patch 2 & 3 and they
> are from two different domains, I submitted them separately to make it
> easier for review.
And this is exactly bisectability (level 2 :-) ) issue.
Basically you confirmed you need to squash them like I said.
>> (For example, device worked improperly in some cases -> stopped
>> working completely)
--
With Best Regards,
Andy Shevchenko
From: Kuppuswamy Sathyanarayanan <[email protected]>
Currently in WCOVE PMIC MFD driver, all second level IRQ chips
are chained to the respective first level IRQs. So there is no
need for explicitly unmasking the first level IRQ in this
driver. This patches removes this level 1 IRQ unmask support.
Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
Reviewed-by: Darren Hart (VMware) <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
---
drivers/platform/x86/intel_bxtwc_tmu.c | 4 ----
1 file changed, 4 deletions(-)
Changes since v1:
* None
Changes since v2:
* Rebased on top of latest release.
Changes since v3:
* None
Changes since v4:
* Changed commit subject from "platform: x86:" "to platform/x86:"
Changes since v5:
* Changed irq->IRQ, mfd->MFD.
diff --git a/drivers/platform/x86/intel_bxtwc_tmu.c b/drivers/platform/x86/intel_bxtwc_tmu.c
index e202abd..ea865d4 100644
--- a/drivers/platform/x86/intel_bxtwc_tmu.c
+++ b/drivers/platform/x86/intel_bxtwc_tmu.c
@@ -92,10 +92,6 @@ static int bxt_wcove_tmu_probe(struct platform_device *pdev)
}
wctmu->irq = virq;
- /* Enable TMU interrupts */
- regmap_update_bits(wctmu->regmap, BXTWC_MIRQLVL1,
- BXTWC_MIRQLVL1_MTMU, 0);
-
/* Unmask TMU second level Wake & System alarm */
regmap_update_bits(wctmu->regmap, BXTWC_MTMUIRQ_REG,
BXTWC_TMU_ALRM_MASK, 0);
--
2.7.4
From: Kuppuswamy Sathyanarayanan <[email protected]>
Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
to mask/unmask individual interrupts belong each of this domain. For
example, in case of TMU, at first level we have TMU interrupt domain,
and at second level we have two interrupts, wake alarm, system alarm that
belong to the TMU interrupt domain.
Currently, in this driver all first level IRQs are registered as part of
IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ
chip from your driver, all IRQs in that chip will masked and can only be
enabled if that IRQ is requested using request_irq() call. This is the
default Linux IRQ behavior model. And whenever a dependent device that
belongs to PMIC requests only the second level IRQ and not explicitly
unmask the first level IRQ, then in essence the second level IRQ will
still be disabled. For example, if TMU device driver request wake_alarm
IRQ and not explicitly unmask TMU level 1 IRQ then according to the default
Linux IRQ model, wake_alarm IRQ will still be disabled. So the proper
solution to fix this issue is to use the chained IRQ chip concept. We
should chain all the second level chip IRQs to the corresponding first
level IRQ. To do this, we need to create separate IRQ chips for every
group of second level IRQs.
In case of TMU, when adding second level IRQ chip, instead of using PMIC
IRQ we should use the corresponding first level IRQ. So the following
code will change from
ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)
to,
virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ);
ret = regmap_add_irq_chip(pmic->regmap, virq, ...)
In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under
charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr)
to get the USBC virtual IRQ number.
Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
Acked-for-MFD-by: Lee Jones <[email protected]>
---
drivers/mfd/intel_soc_pmic_bxtwc.c | 168 ++++++++++++++++++++++++++++++-------
drivers/usb/typec/typec_wcove.c | 2 +-
include/linux/mfd/intel_soc_pmic.h | 5 +-
3 files changed, 143 insertions(+), 32 deletions(-)
Changes since v1:
* Rebased on top of dev_* cleanup patch.
* Fixed style & grammer issues reported by Lee Jones
Changes since v2:
* Rebased on top of latest release.
Changes since v3:
* None
Changes since v4:
* Merged typec driver fix to this patch to prevent branch bisect issue.
Changes since v5:
* Changed irq->IRQ and pmic -> PMIC.
* Rearranged tmu related changes to make the patch more readable.
* Modfied the virq request failure message to include chip name and pirq.
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index feeda6e..15bc052 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -82,20 +82,28 @@ enum bxtwc_irqs {
BXTWC_PWRBTN_IRQ,
};
-enum bxtwc_irqs_level2 {
- /* Level 2 */
+enum bxtwc_irqs_bcu {
BXTWC_BCU_IRQ = 0,
- BXTWC_ADC_IRQ,
- BXTWC_USBC_IRQ,
+};
+
+enum bxtwc_irqs_adc {
+ BXTWC_ADC_IRQ = 0,
+};
+
+enum bxtwc_irqs_chgr {
+ BXTWC_USBC_IRQ = 0,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
- BXTWC_CRIT_IRQ,
};
enum bxtwc_irqs_tmu {
BXTWC_TMU_IRQ = 0,
};
+enum bxtwc_irqs_crit {
+ BXTWC_CRIT_IRQ = 0,
+};
+
static const struct regmap_irq bxtwc_regmap_irqs[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
@@ -108,19 +116,28 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
};
-static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
+static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
- REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
- REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
- REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
- REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
- REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
+ REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
+ REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
+ REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
+ REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
};
static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
};
+static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
+ REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
+};
+
static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
.name = "bxtwc_irq_chip",
.status_base = BXTWC_IRQLVL1,
@@ -130,15 +147,6 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
.num_regs = 2,
};
-static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
- .name = "bxtwc_irq_chip_level2",
- .status_base = BXTWC_BCUIRQ,
- .mask_base = BXTWC_MBCUIRQ,
- .irqs = bxtwc_regmap_irqs_level2,
- .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
- .num_regs = 10,
-};
-
static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
.name = "bxtwc_irq_chip_tmu",
.status_base = BXTWC_TMUIRQ,
@@ -148,6 +156,42 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
.num_regs = 1,
};
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
+ .name = "bxtwc_irq_chip_bcu",
+ .status_base = BXTWC_BCUIRQ,
+ .mask_base = BXTWC_MBCUIRQ,
+ .irqs = bxtwc_regmap_irqs_bcu,
+ .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
+ .num_regs = 1,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
+ .name = "bxtwc_irq_chip_adc",
+ .status_base = BXTWC_ADCIRQ,
+ .mask_base = BXTWC_MADCIRQ,
+ .irqs = bxtwc_regmap_irqs_adc,
+ .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
+ .num_regs = 1,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
+ .name = "bxtwc_irq_chip_chgr",
+ .status_base = BXTWC_CHGR0IRQ,
+ .mask_base = BXTWC_MCHGR0IRQ,
+ .irqs = bxtwc_regmap_irqs_chgr,
+ .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
+ .num_regs = 2,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
+ .name = "bxtwc_irq_chip_crit",
+ .status_base = BXTWC_CRITIRQ,
+ .mask_base = BXTWC_MCRITIRQ,
+ .irqs = bxtwc_regmap_irqs_crit,
+ .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
+ .num_regs = 1,
+};
+
static struct resource gpio_resources[] = {
DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
};
@@ -357,6 +401,26 @@ static const struct regmap_config bxtwc_regmap_config = {
.reg_read = regmap_ipc_byte_reg_read,
};
+static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
+ struct regmap_irq_chip_data *pdata,
+ int pirq, int irq_flags,
+ const struct regmap_irq_chip *chip,
+ struct regmap_irq_chip_data **data)
+{
+ int irq;
+
+ irq = regmap_irq_get_virq(pdata, pirq);
+ if (irq < 0) {
+ dev_err(pmic->dev,
+ "Failed to get parent vIRQ(%d) for chip %s, ret:%d\n",
+ pirq, chip->name, irq);
+ return irq;
+ }
+
+ return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
+ 0, chip, data);
+}
+
static int bxtwc_probe(struct platform_device *pdev)
{
int ret;
@@ -408,21 +472,65 @@ static int bxtwc_probe(struct platform_device *pdev)
return ret;
}
- ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, &bxtwc_regmap_irq_chip_level2,
- &pmic->irq_chip_data_level2);
+ ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+ BXTWC_TMU_LVL1_IRQ,
+ IRQF_ONESHOT,
+ &bxtwc_regmap_irq_chip_tmu,
+ &pmic->irq_chip_data_tmu);
if (ret) {
- dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
+ dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
return ret;
}
- ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, &bxtwc_regmap_irq_chip_tmu,
- &pmic->irq_chip_data_tmu);
+ /* Add chained IRQ handler for BCU IRQs */
+ ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+ BXTWC_BCU_LVL1_IRQ,
+ IRQF_ONESHOT,
+ &bxtwc_regmap_irq_chip_bcu,
+ &pmic->irq_chip_data_bcu);
+
+
if (ret) {
- dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
+ dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
+ return ret;
+ }
+
+ /* Add chained IRQ handler for ADC IRQs */
+ ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+ BXTWC_ADC_LVL1_IRQ,
+ IRQF_ONESHOT,
+ &bxtwc_regmap_irq_chip_adc,
+ &pmic->irq_chip_data_adc);
+
+
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
+ return ret;
+ }
+
+ /* Add chained IRQ handler for CHGR IRQs */
+ ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+ BXTWC_CHGR_LVL1_IRQ,
+ IRQF_ONESHOT,
+ &bxtwc_regmap_irq_chip_chgr,
+ &pmic->irq_chip_data_chgr);
+
+
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
+ return ret;
+ }
+
+ /* Add chained IRQ handler for CRIT IRQs */
+ ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+ BXTWC_CRIT_LVL1_IRQ,
+ IRQF_ONESHOT,
+ &bxtwc_regmap_irq_chip_crit,
+ &pmic->irq_chip_data_crit);
+
+
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n");
return ret;
}
diff --git a/drivers/usb/typec/typec_wcove.c b/drivers/usb/typec/typec_wcove.c
index d5a7b21..00a4bd2 100644
--- a/drivers/usb/typec/typec_wcove.c
+++ b/drivers/usb/typec/typec_wcove.c
@@ -303,7 +303,7 @@ static int wcove_typec_probe(struct platform_device *pdev)
wcove->dev = &pdev->dev;
wcove->regmap = pmic->regmap;
- ret = regmap_irq_get_virq(pmic->irq_chip_data_level2,
+ ret = regmap_irq_get_virq(pmic->irq_chip_data_chgr,
platform_get_irq(pdev, 0));
if (ret < 0)
return ret;
diff --git a/include/linux/mfd/intel_soc_pmic.h b/include/linux/mfd/intel_soc_pmic.h
index 956caa0..5aacdb0 100644
--- a/include/linux/mfd/intel_soc_pmic.h
+++ b/include/linux/mfd/intel_soc_pmic.h
@@ -25,8 +25,11 @@ struct intel_soc_pmic {
int irq;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_chip_data;
- struct regmap_irq_chip_data *irq_chip_data_level2;
struct regmap_irq_chip_data *irq_chip_data_tmu;
+ struct regmap_irq_chip_data *irq_chip_data_bcu;
+ struct regmap_irq_chip_data *irq_chip_data_adc;
+ struct regmap_irq_chip_data *irq_chip_data_chgr;
+ struct regmap_irq_chip_data *irq_chip_data_crit;
struct device *dev;
};
--
2.7.4
From: Kuppuswamy Sathyanarayanan <[email protected]>
Following patch set adds chained IRQ support to WCOVE PMIC driver.
Changes since v3:
* Added fix for typec wcove driver.
Changes since v4:
* Squashed following two commits, to keep the patch set bisectable.
usb: typec: typec_wcove: Use charger irq chip to get usbc virq
mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips
Changes since v5:
* Changed irq->IRQ, pmic->PMIC in all commit messages.
* Squashed following two thermal driver related commits.
mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs
thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq
* Squashed following two GPIO driver related commits.
mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device
gpio: gpio-wcove: Use first level PMIC GPIO irq
Kuppuswamy Sathyanarayanan (6):
mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs
mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask
drivers/gpio/gpio-wcove.c | 14 +-
drivers/mfd/intel_soc_pmic_bxtwc.c | 232 +++++++++++++++++++++----------
drivers/platform/x86/intel_bxtwc_tmu.c | 4 -
drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
drivers/usb/typec/typec_wcove.c | 2 +-
include/linux/mfd/intel_soc_pmic.h | 5 +-
6 files changed, 175 insertions(+), 84 deletions(-)
--
2.7.4
From: Kuppuswamy Sathyanarayanan <[email protected]>
Cleanup the resource allocation/free code in probe function by using
devm_* calls.
Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
Acked-for-MFD-by: Lee Jones <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
---
drivers/mfd/intel_soc_pmic_bxtwc.c | 54 +++++++++++++-------------------------
1 file changed, 18 insertions(+), 36 deletions(-)
Changes since v1:
* None
Changes since v2:
* Rebased on top of latest release.
Changes since v3:
* None
Changes since v5:
* None
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index af11c43..feeda6e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -399,45 +399,44 @@ static int bxtwc_probe(struct platform_device *pdev)
return ret;
}
- ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, &bxtwc_regmap_irq_chip,
- &pmic->irq_chip_data);
+ ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
+ IRQF_ONESHOT | IRQF_SHARED,
+ 0, &bxtwc_regmap_irq_chip,
+ &pmic->irq_chip_data);
if (ret) {
dev_err(&pdev->dev, "Failed to add IRQ chip\n");
return ret;
}
- ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, &bxtwc_regmap_irq_chip_level2,
- &pmic->irq_chip_data_level2);
+ ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
+ IRQF_ONESHOT | IRQF_SHARED,
+ 0, &bxtwc_regmap_irq_chip_level2,
+ &pmic->irq_chip_data_level2);
if (ret) {
dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
- goto err_irq_chip_level2;
+ return ret;
}
- ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, &bxtwc_regmap_irq_chip_tmu,
- &pmic->irq_chip_data_tmu);
+ ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
+ IRQF_ONESHOT | IRQF_SHARED,
+ 0, &bxtwc_regmap_irq_chip_tmu,
+ &pmic->irq_chip_data_tmu);
if (ret) {
dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
- goto err_irq_chip_tmu;
+ return ret;
}
- ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
- ARRAY_SIZE(bxt_wc_dev), NULL, 0,
- NULL);
+ ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
+ ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
if (ret) {
dev_err(&pdev->dev, "Failed to add devices\n");
- goto err_mfd;
+ return ret;
}
ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
if (ret) {
dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
- goto err_sysfs;
+ return ret;
}
/*
@@ -451,28 +450,11 @@ static int bxtwc_probe(struct platform_device *pdev)
BXTWC_MIRQLVL1_MCHGR, 0);
return 0;
-
-err_sysfs:
- mfd_remove_devices(&pdev->dev);
-err_mfd:
- regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
-err_irq_chip_tmu:
- regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-err_irq_chip_level2:
- regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-
- return ret;
}
static int bxtwc_remove(struct platform_device *pdev)
{
- struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
-
sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
- mfd_remove_devices(&pdev->dev);
- regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
- regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
- regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
return 0;
}
--
2.7.4
From: Kuppuswamy Sathyanarayanan <[email protected]>
Since all second level thermal IRQs are consumed by the same
device(bxt_wcove_thermal), there is no need to expose them as separate
interrupts. We can just export only the first level IRQs for thermal and
let the device(bxt_wcove_thermal) driver handle the second level IRQs
based on thermal interrupt status register. Also, just using only the
first level IRQ will eliminate the bug involved in requesting only the
second level IRQ and not explicitly enable the first level IRQ. For
more info on this issue please read the details at,
https://lkml.org/lkml/2017/2/27/148
This patch also makes relevant change in bxt_wcove_thermal driver to use
only first level PMIC thermal IRQ.
Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
Acked-for-MFD-by: Lee Jones <[email protected]>
Acked-by: Zhang Rui <[email protected]>
---
drivers/mfd/intel_soc_pmic_bxtwc.c | 32 ++++++++++++--------------------
drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
2 files changed, 13 insertions(+), 21 deletions(-)
Changes since v1:
* None
Changes since v2:
* Rebased on top of latest release.
Changes since v3:
* Rebased on top of latest release.
Changes since v5:
* Squashed intel_bxt_pmic_thermal driver patch.
* Changed irq -> IRQ
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7cbaf1e..7c1ed27 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -84,10 +84,7 @@ enum bxtwc_irqs {
enum bxtwc_irqs_level2 {
/* Level 2 */
- BXTWC_THRM0_IRQ = 0,
- BXTWC_THRM1_IRQ,
- BXTWC_THRM2_IRQ,
- BXTWC_BCU_IRQ,
+ BXTWC_BCU_IRQ = 0,
BXTWC_ADC_IRQ,
BXTWC_USBC_IRQ,
BXTWC_CHGR0_IRQ,
@@ -114,17 +111,14 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
};
static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
- REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
- REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
- REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
- REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
- REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
- REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
- REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
- REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
- REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
- REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
- REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
+ REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
+ REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
+ REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
+ REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
+ REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
+ REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
+ REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
+ REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
};
static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
@@ -142,8 +136,8 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
.name = "bxtwc_irq_chip_level2",
- .status_base = BXTWC_THRM0IRQ,
- .mask_base = BXTWC_MTHRM0IRQ,
+ .status_base = BXTWC_BCUIRQ,
+ .mask_base = BXTWC_MBCUIRQ,
.irqs = bxtwc_regmap_irqs_level2,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
.num_regs = 10,
@@ -177,9 +171,7 @@ static struct resource charger_resources[] = {
};
static struct resource thermal_resources[] = {
- DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
- DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
- DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
+ DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
};
static struct resource bcu_resources[] = {
diff --git a/drivers/thermal/intel_bxt_pmic_thermal.c b/drivers/thermal/intel_bxt_pmic_thermal.c
index 0f19a39..ef6b322 100644
--- a/drivers/thermal/intel_bxt_pmic_thermal.c
+++ b/drivers/thermal/intel_bxt_pmic_thermal.c
@@ -241,7 +241,7 @@ static int pmic_thermal_probe(struct platform_device *pdev)
}
regmap = pmic->regmap;
- regmap_irq_chip = pmic->irq_chip_data_level2;
+ regmap_irq_chip = pmic->irq_chip_data;
pmic_irq_count = 0;
while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
--
2.7.4
From: Kuppuswamy Sathyanarayanan <[email protected]>
Currently all PMIC GPIO domain IRQs are consumed by the same
device(bxt_wcove_gpio), so there is no need to export them as
separate interrupts. We can just export only the first level
GPIO IRQ(BXTWC_GPIO_LVL1_IRQ) as an IRQ resource and let the
GPIO device driver(bxt_wcove_gpio) handle the GPIO sub domain
IRQs based on status value of GPIO level2 interrupt status
register. Also, just using only the first level IRQ will eliminate
the bug involved in requesting only the second level IRQ and not
explicitly enable the first level IRQ. For more info on this
issue please read the details at,
https://lkml.org/lkml/2017/2/27/148
This patch also makes relevant change in Whiskey cove GPIO driver to
use only first level PMIC GPIO IRQ.
Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
Acked-for-MFD-by: Lee Jones <[email protected]>
Acked-by: Linus Walleij <[email protected]>
---
drivers/gpio/gpio-wcove.c | 14 +++++++++++++-
drivers/mfd/intel_soc_pmic_bxtwc.c | 7 +------
2 files changed, 14 insertions(+), 7 deletions(-)
Changes since v1:
* None
Changes since v2:
* Rebased on top of latest release.
Changes since v3:
* None
Changes since v5:
* Squashed gpio driver patch.
* Changes irq -> IRQ.
diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
index 7b1bc20..bba7704 100644
--- a/drivers/gpio/gpio-wcove.c
+++ b/drivers/gpio/gpio-wcove.c
@@ -401,7 +401,7 @@ static int wcove_gpio_probe(struct platform_device *pdev)
if (!wg)
return -ENOMEM;
- wg->regmap_irq_chip = pmic->irq_chip_data_level2;
+ wg->regmap_irq_chip = pmic->irq_chip_data;
platform_set_drvdata(pdev, wg);
@@ -449,6 +449,18 @@ static int wcove_gpio_probe(struct platform_device *pdev)
gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
+ /* Enable GPIO0 interrupts */
+ ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
+ 0x00);
+ if (ret)
+ return ret;
+
+ /* Enable GPIO1 interrupts */
+ ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
+ 0x00);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7c1ed27..af11c43 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -89,8 +89,6 @@ enum bxtwc_irqs_level2 {
BXTWC_USBC_IRQ,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
- BXTWC_GPIO0_IRQ,
- BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
};
@@ -116,8 +114,6 @@ static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
- REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
- REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
};
@@ -153,8 +149,7 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
};
static struct resource gpio_resources[] = {
- DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
- DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
+ DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
};
static struct resource adc_resources[] = {
--
2.7.4
From: Kuppuswamy Sathyanarayanan <[email protected]>
TMU interrupts are registered as a separate interrupt chip, and
hence it should start its interrupt index(BXTWC_TMU_IRQ) number
from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
bxtwc_irqs_level2 and its index value is 11. Since this index
value is used when calculating .num_irqs of regmap_irq_chip_tmu,
it incorrectly reports number of IRQs as 12 instead of actual
value of 1.
This patch fixes this issue by creating new enum of tmu IRQs and
resetting its starting index to 0.
Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
Acked-for-MFD-by: Lee Jones <[email protected]>
---
drivers/mfd/intel_soc_pmic_bxtwc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
Changes since v1:
* Removed code from commit message.
Changes since v2:
* Rebased on top of latest release.
Changes sinve v3:
* Rebased on top of latest release.
Changes sinve v5:
* Changed irq to IRQ.
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 8c3cbf6..7cbaf1e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -95,7 +95,10 @@ enum bxtwc_irqs_level2 {
BXTWC_GPIO0_IRQ,
BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
- BXTWC_TMU_IRQ,
+};
+
+enum bxtwc_irqs_tmu {
+ BXTWC_TMU_IRQ = 0,
};
static const struct regmap_irq bxtwc_regmap_irqs[] = {
--
2.7.4
On Mon, Jun 05, 2017 at 12:08:05PM -0700, [email protected] wrote:
> From: Kuppuswamy Sathyanarayanan <[email protected]>
>
> Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
> At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
> CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
> to mask/unmask individual interrupts belong each of this domain. For
> example, in case of TMU, at first level we have TMU interrupt domain,
> and at second level we have two interrupts, wake alarm, system alarm that
> belong to the TMU interrupt domain.
>
> Currently, in this driver all first level IRQs are registered as part of
> IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ
> chip from your driver, all IRQs in that chip will masked and can only be
> enabled if that IRQ is requested using request_irq() call. This is the
> default Linux IRQ behavior model. And whenever a dependent device that
> belongs to PMIC requests only the second level IRQ and not explicitly
> unmask the first level IRQ, then in essence the second level IRQ will
> still be disabled. For example, if TMU device driver request wake_alarm
> IRQ and not explicitly unmask TMU level 1 IRQ then according to the default
> Linux IRQ model, wake_alarm IRQ will still be disabled. So the proper
> solution to fix this issue is to use the chained IRQ chip concept. We
> should chain all the second level chip IRQs to the corresponding first
> level IRQ. To do this, we need to create separate IRQ chips for every
> group of second level IRQs.
>
> In case of TMU, when adding second level IRQ chip, instead of using PMIC
> IRQ we should use the corresponding first level IRQ. So the following
> code will change from
>
> ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)
>
> to,
>
> virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ);
>
> ret = regmap_add_irq_chip(pmic->regmap, virq, ...)
>
> In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under
> charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr)
> to get the USBC virtual IRQ number.
>
> Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]>
> Acked-for-MFD-by: Lee Jones <[email protected]>
For the typec_wcove.c part:
Revieved-by: Heikki Krogerus <[email protected]>
Thanks,
--
heikki
On Mon, Jun 5, 2017 at 10:08 PM,
<[email protected]> wrote:
> From: Kuppuswamy Sathyanarayanan <[email protected]>
>
> Following patch set adds chained IRQ support to WCOVE PMIC driver.
Assuming it has been tested,
Reviewed-by: Andy Shevchenko <[email protected]>
to the patches which do not have it yet.
> Changes since v3:
> * Added fix for typec wcove driver.
>
> Changes since v4:
> * Squashed following two commits, to keep the patch set bisectable.
> usb: typec: typec_wcove: Use charger irq chip to get usbc virq
> mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips
>
> Changes since v5:
> * Changed irq->IRQ, pmic->PMIC in all commit messages.
> * Squashed following two thermal driver related commits.
> mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs
> thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq
> * Squashed following two GPIO driver related commits.
> mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device
> gpio: gpio-wcove: Use first level PMIC GPIO irq
>
> Kuppuswamy Sathyanarayanan (6):
> mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
> mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs
> mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
> mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
> mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
> platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask
>
> drivers/gpio/gpio-wcove.c | 14 +-
> drivers/mfd/intel_soc_pmic_bxtwc.c | 232 +++++++++++++++++++++----------
> drivers/platform/x86/intel_bxtwc_tmu.c | 4 -
> drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
> drivers/usb/typec/typec_wcove.c | 2 +-
> include/linux/mfd/intel_soc_pmic.h | 5 +-
> 6 files changed, 175 insertions(+), 84 deletions(-)
>
> --
> 2.7.4
>
--
With Best Regards,
Andy Shevchenko
Enjoy!
The following changes since commit 2ea659a9ef488125eb46da6eb571de5eae5c43f6:
Linux 4.12-rc1 (2017-05-13 13:19:49 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-x86-v4.13
for you to fetch changes up to 94d68594a7b4fd2eec457f22110de644e1c4ee57:
platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask (2017-06-19 15:45:30 +0100)
----------------------------------------------------------------
Immutable branch between MFD and X86 due for the v4.13 merge window
----------------------------------------------------------------
Kuppuswamy Sathyanarayanan (6):
mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs
mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask
drivers/gpio/gpio-wcove.c | 14 +-
drivers/mfd/intel_soc_pmic_bxtwc.c | 232 +++++++++++++++++++++----------
drivers/platform/x86/intel_bxtwc_tmu.c | 4 -
drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
drivers/usb/typec/typec_wcove.c | 2 +-
include/linux/mfd/intel_soc_pmic.h | 5 +-
6 files changed, 175 insertions(+), 84 deletions(-)
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Mon, Jun 19, 2017 at 5:48 PM, Lee Jones <[email protected]> wrote:
> Enjoy!
Thanks!
I suppose this one kbuild bot doesn't complain about :-)
Darren, do we need it or we can survive until v4.13-rc1?
>
> The following changes since commit 2ea659a9ef488125eb46da6eb571de5eae5c43f6:
>
> Linux 4.12-rc1 (2017-05-13 13:19:49 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-x86-v4.13
>
> for you to fetch changes up to 94d68594a7b4fd2eec457f22110de644e1c4ee57:
>
> platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask (2017-06-19 15:45:30 +0100)
>
> ----------------------------------------------------------------
> Immutable branch between MFD and X86 due for the v4.13 merge window
>
> ----------------------------------------------------------------
> Kuppuswamy Sathyanarayanan (6):
> mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
> mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs
> mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
> mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
> mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
> platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask
>
> drivers/gpio/gpio-wcove.c | 14 +-
> drivers/mfd/intel_soc_pmic_bxtwc.c | 232 +++++++++++++++++++++----------
> drivers/platform/x86/intel_bxtwc_tmu.c | 4 -
> drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
> drivers/usb/typec/typec_wcove.c | 2 +-
> include/linux/mfd/intel_soc_pmic.h | 5 +-
> 6 files changed, 175 insertions(+), 84 deletions(-)
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
--
With Best Regards,
Andy Shevchenko
On Mon, Jun 19, 2017 at 06:08:27PM +0300, Andy Shevchenko wrote:
> On Mon, Jun 19, 2017 at 5:48 PM, Lee Jones <[email protected]> wrote:
> > Enjoy!
>
> Thanks!
>
> I suppose this one kbuild bot doesn't complain about :-)
>
> Darren, do we need it or we can survive until v4.13-rc1?
I suggest merging it to a local branch for safe keeping and if we see
conflicts in subsequent patches, we can apply it. I doubt it will be a problem.
--
Darren Hart
VMware Open Source Technology Center