From: Lad Prabhakar <[email protected]>
Hi All,
This patch series does the following:
* Adds L2 cache node and marks the SoC as noncoherent
* Enables IP blocks which were explicitly disabled and for
which support is present
* Enables the configs required for RZ/Five SoC
Cheers,
Prabhakar
Lad Prabhakar (5):
riscv: dts: renesas: r9a07g043f: Add L2 cache node
riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
riscv: dts: renesas: rzfive-smarc: Enable the blocks which were
explicitly disabled
riscv: dts: renesas: rzfive-smarc: Drop dma properties from SSI1 node
riscv: configs: defconfig: Enable configs required for RZ/Five SoC
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 13 +++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 23 --------
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 55 +------------------
arch/riscv/configs/defconfig | 52 ++++++++++++++++++
4 files changed, 67 insertions(+), 76 deletions(-)
--
2.34.1
From: Lad Prabhakar <[email protected]>
With DMA enabled audio capture/playback has some echo noise. So for
now switch to PIO mode until fixed.
Signed-off-by: Lad Prabhakar <[email protected]>
---
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
index a8573fdfd8b1..85f96e24a96e 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -6,3 +6,8 @@
*/
#include <arm64/renesas/rzg2ul-smarc.dtsi>
+
+&ssi1 {
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+};
--
2.34.1
From: Lad Prabhakar <[email protected]>
Enable the configs required by the below IP blocks which are
present on RZ/Five SoC:
* ADC
* CANFD
* DMAC
* eMMC/SDHI
* OSTM
* RAVB (+ Micrel PHY)
* RIIC
* RSPI
* SSI (Sound+WM8978 codec)
* Thermal
* USB (PHY/RESET/OTG)
Along with the above some core configs are enabled too,
-> CPU frequency scaling as RZ/Five does support this.
-> MTD is enabled as RSPI can be connected to flash chips
-> Enabled I2C chardev so that it enables userspace to read/write
i2c devices (similar to arm64)
-> Thermal configs as RZ/Five SoC does have thermal unit
-> GPIO regulator as we might have IP blocks for which voltage
levels are controlled by GPIOs
-> OTG configs as RZ/Five USB can support host/function
-> Gadget configs so that we can test USB function (as done in arm64
all the gadget configs are enabled)
Signed-off-by: Lad Prabhakar <[email protected]>
---
arch/riscv/configs/defconfig | 52 ++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index ab86ec3b9eab..1e81c865a271 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -36,6 +36,13 @@ CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
CONFIG_CPU_IDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPUFREQ_DT=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_ACPI=y
@@ -94,6 +101,7 @@ CONFIG_NETLINK_DIAG=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
+CONFIG_CAN=m
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_HOST_GENERIC=y
@@ -101,6 +109,11 @@ CONFIG_PCIE_XILINX=y
CONFIG_PCIE_FU740=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_SPI_NOR=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_NVME=m
@@ -123,8 +136,11 @@ CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_E1000E=y
CONFIG_R8169=y
+CONFIG_RAVB=y
CONFIG_STMMAC_ETH=m
+CONFIG_MICREL_PHY=y
CONFIG_MICROSEMI_PHY=y
+CONFIG_CAN_RCAR_CANFD=m
CONFIG_INPUT_MOUSEDEV=y
CONFIG_KEYBOARD_SUN4I_LRADC=m
CONFIG_SERIAL_8250=y
@@ -135,16 +151,24 @@ CONFIG_SERIAL_SH_SCI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_CHARDEV=m
CONFIG_I2C_MV64XXX=m
+CONFIG_I2C_RIIC=y
CONFIG_SPI=y
+CONFIG_SPI_RSPI=m
CONFIG_SPI_SIFIVE=y
CONFIG_SPI_SUN6I=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_GPIO_SIFIVE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_RZG2L_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
+CONFIG_RENESAS_RZG2LWDT=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
CONFIG_DRM=m
CONFIG_DRM_RADEON=m
CONFIG_DRM_NOUVEAU=m
@@ -152,39 +176,67 @@ CONFIG_DRM_SUN4I=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_RZ=m
+CONFIG_SND_SOC_WM8978=m
+CONFIG_SND_SIMPLE_CARD=m
CONFIG_USB=y
+CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_RENESAS_USBHS=m
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
CONFIG_USB_MUSB_HDRC=m
CONFIG_USB_MUSB_SUNXI=m
CONFIG_NOP_USB_XCEIV=m
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SPI=y
+CONFIG_MMC_SDHI=y
CONFIG_MMC_SUNXI=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_SUN6I=y
CONFIG_DMADEVICES=y
CONFIG_DMA_SUN6I=m
+CONFIG_RZ_DMAC=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
+CONFIG_RENESAS_OSTM=y
CONFIG_SUN8I_DE2_CCU=m
CONFIG_SUN50I_IOMMU=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_VIRTIO=y
CONFIG_ARCH_R9A07G043=y
+CONFIG_IIO=y
+CONFIG_RZG2L_ADC=m
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_PHY_SUN4I_USB=m
+CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_LIBNVDIMM=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_EXT4_FS=y
--
2.34.1
Hi Prabhakar,
On 2023-09-28 7:07 PM, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> With DMA enabled audio capture/playback has some echo noise. So for
> now switch to PIO mode until fixed.
Is it really appropriate to work around a Linux software bug with a DT change
like this? Remember, the devicetrees are used by software other than Linux.
Regards,
Samuel
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> index a8573fdfd8b1..85f96e24a96e 100644
> --- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> @@ -6,3 +6,8 @@
> */
>
> #include <arm64/renesas/rzg2ul-smarc.dtsi>
> +
> +&ssi1 {
> + /delete-property/ dmas;
> + /delete-property/ dma-names;
> +};
On Fri, Sep 29, 2023 at 01:07:04AM +0100, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> Enable the configs required by the below IP blocks which are
> present on RZ/Five SoC:
> * ADC
> * CANFD
> * DMAC
> * eMMC/SDHI
> * OSTM
> * RAVB (+ Micrel PHY)
> * RIIC
> * RSPI
> * SSI (Sound+WM8978 codec)
> * Thermal
> * USB (PHY/RESET/OTG)
>
> Along with the above some core configs are enabled too,
> -> CPU frequency scaling as RZ/Five does support this.
> -> MTD is enabled as RSPI can be connected to flash chips
> -> Enabled I2C chardev so that it enables userspace to read/write
> i2c devices (similar to arm64)
> -> Thermal configs as RZ/Five SoC does have thermal unit
> -> GPIO regulator as we might have IP blocks for which voltage
> levels are controlled by GPIOs
You might or you do?
Either way, this stuff seems fine to me /shrug
Acked-by: Conor Dooley <[email protected]>
Thanks,
Conor.
> -> OTG configs as RZ/Five USB can support host/function
> -> Gadget configs so that we can test USB function (as done in arm64
> all the gadget configs are enabled)
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> arch/riscv/configs/defconfig | 52 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index ab86ec3b9eab..1e81c865a271 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -36,6 +36,13 @@ CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> CONFIG_PM=y
> CONFIG_CPU_IDLE=y
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_STAT=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=m
> +CONFIG_CPU_FREQ_GOV_USERSPACE=y
> +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
> +CONFIG_CPUFREQ_DT=y
> CONFIG_VIRTUALIZATION=y
> CONFIG_KVM=m
> CONFIG_ACPI=y
> @@ -94,6 +101,7 @@ CONFIG_NETLINK_DIAG=y
> CONFIG_CGROUP_NET_PRIO=y
> CONFIG_NET_9P=y
> CONFIG_NET_9P_VIRTIO=y
> +CONFIG_CAN=m
> CONFIG_PCI=y
> CONFIG_PCIEPORTBUS=y
> CONFIG_PCI_HOST_GENERIC=y
> @@ -101,6 +109,11 @@ CONFIG_PCIE_XILINX=y
> CONFIG_PCIE_FU740=y
> CONFIG_DEVTMPFS=y
> CONFIG_DEVTMPFS_MOUNT=y
> +CONFIG_MTD=y
> +CONFIG_MTD_BLOCK=y
> +CONFIG_MTD_CFI=y
> +CONFIG_MTD_CFI_ADV_OPTIONS=y
> +CONFIG_MTD_SPI_NOR=y
> CONFIG_BLK_DEV_LOOP=y
> CONFIG_VIRTIO_BLK=y
> CONFIG_BLK_DEV_NVME=m
> @@ -123,8 +136,11 @@ CONFIG_VIRTIO_NET=y
> CONFIG_MACB=y
> CONFIG_E1000E=y
> CONFIG_R8169=y
> +CONFIG_RAVB=y
> CONFIG_STMMAC_ETH=m
> +CONFIG_MICREL_PHY=y
> CONFIG_MICROSEMI_PHY=y
> +CONFIG_CAN_RCAR_CANFD=m
> CONFIG_INPUT_MOUSEDEV=y
> CONFIG_KEYBOARD_SUN4I_LRADC=m
> CONFIG_SERIAL_8250=y
> @@ -135,16 +151,24 @@ CONFIG_SERIAL_SH_SCI=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> +CONFIG_I2C_CHARDEV=m
> CONFIG_I2C_MV64XXX=m
> +CONFIG_I2C_RIIC=y
> CONFIG_SPI=y
> +CONFIG_SPI_RSPI=m
> CONFIG_SPI_SIFIVE=y
> CONFIG_SPI_SUN6I=y
> # CONFIG_PTP_1588_CLOCK is not set
> CONFIG_GPIO_SIFIVE=y
> +CONFIG_CPU_THERMAL=y
> +CONFIG_DEVFREQ_THERMAL=y
> +CONFIG_RZG2L_THERMAL=y
> CONFIG_WATCHDOG=y
> CONFIG_SUNXI_WATCHDOG=y
> +CONFIG_RENESAS_RZG2LWDT=y
> CONFIG_REGULATOR=y
> CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_REGULATOR_GPIO=y
> CONFIG_DRM=m
> CONFIG_DRM_RADEON=m
> CONFIG_DRM_NOUVEAU=m
> @@ -152,39 +176,67 @@ CONFIG_DRM_SUN4I=m
> CONFIG_DRM_VIRTIO_GPU=m
> CONFIG_FB=y
> CONFIG_FRAMEBUFFER_CONSOLE=y
> +CONFIG_SOUND=y
> +CONFIG_SND=y
> +CONFIG_SND_SOC=y
> +CONFIG_SND_SOC_RZ=m
> +CONFIG_SND_SOC_WM8978=m
> +CONFIG_SND_SIMPLE_CARD=m
> CONFIG_USB=y
> +CONFIG_USB_OTG=y
> CONFIG_USB_XHCI_HCD=y
> CONFIG_USB_XHCI_PLATFORM=y
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_EHCI_HCD_PLATFORM=y
> CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> +CONFIG_USB_RENESAS_USBHS=m
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> CONFIG_USB_MUSB_HDRC=m
> CONFIG_USB_MUSB_SUNXI=m
> CONFIG_NOP_USB_XCEIV=m
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_RENESAS_USBHS_UDC=m
> +CONFIG_USB_CONFIGFS=m
> +CONFIG_USB_CONFIGFS_SERIAL=y
> +CONFIG_USB_CONFIGFS_ACM=y
> +CONFIG_USB_CONFIGFS_OBEX=y
> +CONFIG_USB_CONFIGFS_NCM=y
> +CONFIG_USB_CONFIGFS_ECM=y
> +CONFIG_USB_CONFIGFS_ECM_SUBSET=y
> +CONFIG_USB_CONFIGFS_RNDIS=y
> +CONFIG_USB_CONFIGFS_EEM=y
> +CONFIG_USB_CONFIGFS_MASS_STORAGE=y
> +CONFIG_USB_CONFIGFS_F_FS=y
> CONFIG_MMC=y
> CONFIG_MMC_SDHCI=y
> CONFIG_MMC_SDHCI_PLTFM=y
> CONFIG_MMC_SDHCI_CADENCE=y
> CONFIG_MMC_SPI=y
> +CONFIG_MMC_SDHI=y
> CONFIG_MMC_SUNXI=y
> CONFIG_RTC_CLASS=y
> CONFIG_RTC_DRV_SUN6I=y
> CONFIG_DMADEVICES=y
> CONFIG_DMA_SUN6I=m
> +CONFIG_RZ_DMAC=y
> CONFIG_VIRTIO_PCI=y
> CONFIG_VIRTIO_BALLOON=y
> CONFIG_VIRTIO_INPUT=y
> CONFIG_VIRTIO_MMIO=y
> +CONFIG_RENESAS_OSTM=y
> CONFIG_SUN8I_DE2_CCU=m
> CONFIG_SUN50I_IOMMU=y
> CONFIG_RPMSG_CHAR=y
> CONFIG_RPMSG_CTRL=y
> CONFIG_RPMSG_VIRTIO=y
> CONFIG_ARCH_R9A07G043=y
> +CONFIG_IIO=y
> +CONFIG_RZG2L_ADC=m
> +CONFIG_RESET_RZG2L_USBPHY_CTRL=y
> CONFIG_PHY_SUN4I_USB=m
> +CONFIG_PHY_RCAR_GEN3_USB2=y
> CONFIG_LIBNVDIMM=y
> CONFIG_NVMEM_SUNXI_SID=y
> CONFIG_EXT4_FS=y
> --
> 2.34.1
>
Hi Conor,
Thank you for review.
On Fri, Sep 29, 2023 at 3:14 PM Conor Dooley <[email protected]> wrote:
>
> On Fri, Sep 29, 2023 at 01:07:04AM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > Enable the configs required by the below IP blocks which are
> > present on RZ/Five SoC:
> > * ADC
> > * CANFD
> > * DMAC
> > * eMMC/SDHI
> > * OSTM
> > * RAVB (+ Micrel PHY)
> > * RIIC
> > * RSPI
> > * SSI (Sound+WM8978 codec)
> > * Thermal
> > * USB (PHY/RESET/OTG)
> >
> > Along with the above some core configs are enabled too,
> > -> CPU frequency scaling as RZ/Five does support this.
> > -> MTD is enabled as RSPI can be connected to flash chips
> > -> Enabled I2C chardev so that it enables userspace to read/write
> > i2c devices (similar to arm64)
> > -> Thermal configs as RZ/Five SoC does have thermal unit
> > -> GPIO regulator as we might have IP blocks for which voltage
> > levels are controlled by GPIOs
>
> You might or you do?
>
Yes we do use the gpio regulator for SDHI.
Cheers,
Prabhakar
Hi Prabhakar,
On Fri, Sep 29, 2023 at 2:07 AM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> Enable the configs required by the below IP blocks which are
> present on RZ/Five SoC:
> * ADC
> * CANFD
> * DMAC
> * eMMC/SDHI
> * OSTM
> * RAVB (+ Micrel PHY)
> * RIIC
> * RSPI
> * SSI (Sound+WM8978 codec)
> * Thermal
> * USB (PHY/RESET/OTG)
>
> Along with the above some core configs are enabled too,
> -> CPU frequency scaling as RZ/Five does support this.
> -> MTD is enabled as RSPI can be connected to flash chips
> -> Enabled I2C chardev so that it enables userspace to read/write
> i2c devices (similar to arm64)
> -> Thermal configs as RZ/Five SoC does have thermal unit
> -> GPIO regulator as we might have IP blocks for which voltage
> levels are controlled by GPIOs
> -> OTG configs as RZ/Five USB can support host/function
> -> Gadget configs so that we can test USB function (as done in arm64
> all the gadget configs are enabled)
>
> Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
As I expect this to go in through the RISC-V tree, I will let the
RISC-V people handle any discussion about more options that should be
made modular instead of builtin.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Samuel,
On Fri, Sep 29, 2023 at 1:30 AM Samuel Holland
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> On 2023-09-28 7:07 PM, Prabhakar wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > With DMA enabled audio capture/playback has some echo noise. So for
> > now switch to PIO mode until fixed.
>
> Is it really appropriate to work around a Linux software bug with a DT change
> like this? Remember, the devicetrees are used by software other than Linux.
>
Agreed not a good idea, this worked with previous kernel version and I
wanted to make sure people using upstream kernel be aware of this
issue. As you mentioned this is not a correct approach Im happy for
this patch to be dropped from the series.
Cheers,
Prabhakar
> Regards,
> Samuel
>
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> > index a8573fdfd8b1..85f96e24a96e 100644
> > --- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> > @@ -6,3 +6,8 @@
> > */
> >
> > #include <arm64/renesas/rzg2ul-smarc.dtsi>
> > +
> > +&ssi1 {
> > + /delete-property/ dmas;
> > + /delete-property/ dma-names;
> > +};
>
On Tue, 03 Oct 2023 05:34:13 PDT (-0700), [email protected] wrote:
> Hi Prabhakar,
>
> On Fri, Sep 29, 2023 at 2:07 AM Prabhakar <[email protected]> wrote:
>> From: Lad Prabhakar <[email protected]>
>>
>> Enable the configs required by the below IP blocks which are
>> present on RZ/Five SoC:
>> * ADC
>> * CANFD
>> * DMAC
>> * eMMC/SDHI
>> * OSTM
>> * RAVB (+ Micrel PHY)
>> * RIIC
>> * RSPI
>> * SSI (Sound+WM8978 codec)
>> * Thermal
>> * USB (PHY/RESET/OTG)
>>
>> Along with the above some core configs are enabled too,
>> -> CPU frequency scaling as RZ/Five does support this.
>> -> MTD is enabled as RSPI can be connected to flash chips
>> -> Enabled I2C chardev so that it enables userspace to read/write
>> i2c devices (similar to arm64)
>> -> Thermal configs as RZ/Five SoC does have thermal unit
>> -> GPIO regulator as we might have IP blocks for which voltage
>> levels are controlled by GPIOs
>> -> OTG configs as RZ/Five USB can support host/function
>> -> Gadget configs so that we can test USB function (as done in arm64
>> all the gadget configs are enabled)
>>
>> Signed-off-by: Lad Prabhakar <[email protected]>
>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
>
> As I expect this to go in through the RISC-V tree, I will let the
> RISC-V people handle any discussion about more options that should be
> made modular instead of builtin.
I'm pretty much agnostic on that front, so I'm cool just picking up
this. I've got just patch 5 in my queue for testing, there's a few
other things in front of it but it should show up on for-next soon.
>
> Gr{oetje,eeting}s,
>
> Geert
Hi Palmer,
On 2023-10-27 5:11 PM, Palmer Dabbelt wrote:
> On Tue, 03 Oct 2023 05:34:13 PDT (-0700), [email protected] wrote:
>> Hi Prabhakar,
>>
>> On Fri, Sep 29, 2023 at 2:07 AM Prabhakar <[email protected]> wrote:
>>> From: Lad Prabhakar <[email protected]>
>>>
>>> Enable the configs required by the below IP blocks which are
>>> present on RZ/Five SoC:
>>> * ADC
>>> * CANFD
>>> * DMAC
>>> * eMMC/SDHI
>>> * OSTM
>>> * RAVB (+ Micrel PHY)
>>> * RIIC
>>> * RSPI
>>> * SSI (Sound+WM8978 codec)
>>> * Thermal
>>> * USB (PHY/RESET/OTG)
>>>
>>> Along with the above some core configs are enabled too,
>>> -> CPU frequency scaling as RZ/Five does support this.
>>> -> MTD is enabled as RSPI can be connected to flash chips
>>> -> Enabled I2C chardev so that it enables userspace to read/write
>>> i2c devices (similar to arm64)
>>> -> Thermal configs as RZ/Five SoC does have thermal unit
>>> -> GPIO regulator as we might have IP blocks for which voltage
>>> levels are controlled by GPIOs
>>> -> OTG configs as RZ/Five USB can support host/function
>>> -> Gadget configs so that we can test USB function (as done in arm64
>>> all the gadget configs are enabled)
>>>
>>> Signed-off-by: Lad Prabhakar <[email protected]>
>>
>> Reviewed-by: Geert Uytterhoeven <[email protected]>
>>
>> As I expect this to go in through the RISC-V tree, I will let the
>> RISC-V people handle any discussion about more options that should be
>> made modular instead of builtin.
>
> I'm pretty much agnostic on that front, so I'm cool just picking up this. I've
> got just patch 5 in my queue for testing, there's a few other things in front of
> it but it should show up on for-next soon.
Does it make sense to merge this, considering RZ/Five support depends on
NONPORTABLE, and therefore cannot be enabled in defconfig anyway?
Regards,
Samuel
Hi Samuel,
On Sat, Oct 28, 2023 at 11:27 PM Samuel Holland
<[email protected]> wrote:
> On 2023-10-27 5:11 PM, Palmer Dabbelt wrote:
> > On Tue, 03 Oct 2023 05:34:13 PDT (-0700), [email protected] wrote:
> >> On Fri, Sep 29, 2023 at 2:07 AM Prabhakar <[email protected]> wrote:
> >>> From: Lad Prabhakar <[email protected]>
> >>>
> >>> Enable the configs required by the below IP blocks which are
> >>> present on RZ/Five SoC:
> >>> * ADC
> >>> * CANFD
> >>> * DMAC
> >>> * eMMC/SDHI
> >>> * OSTM
> >>> * RAVB (+ Micrel PHY)
> >>> * RIIC
> >>> * RSPI
> >>> * SSI (Sound+WM8978 codec)
> >>> * Thermal
> >>> * USB (PHY/RESET/OTG)
> >>>
> >>> Along with the above some core configs are enabled too,
> >>> -> CPU frequency scaling as RZ/Five does support this.
> >>> -> MTD is enabled as RSPI can be connected to flash chips
> >>> -> Enabled I2C chardev so that it enables userspace to read/write
> >>> i2c devices (similar to arm64)
> >>> -> Thermal configs as RZ/Five SoC does have thermal unit
> >>> -> GPIO regulator as we might have IP blocks for which voltage
> >>> levels are controlled by GPIOs
> >>> -> OTG configs as RZ/Five USB can support host/function
> >>> -> Gadget configs so that we can test USB function (as done in arm64
> >>> all the gadget configs are enabled)
> >>>
> >>> Signed-off-by: Lad Prabhakar <[email protected]>
> >>
> >> Reviewed-by: Geert Uytterhoeven <[email protected]>
> >>
> >> As I expect this to go in through the RISC-V tree, I will let the
> >> RISC-V people handle any discussion about more options that should be
> >> made modular instead of builtin.
> >
> > I'm pretty much agnostic on that front, so I'm cool just picking up this. I've
> > got just patch 5 in my queue for testing, there's a few other things in front of
> > it but it should show up on for-next soon.
>
> Does it make sense to merge this, considering RZ/Five support depends on
> NONPORTABLE, and therefore cannot be enabled in defconfig anyway?
Indeed, that's a good point.
Note that this patch (and its review) predates the NONPORTABLE
dependency.
Palmer: are you open to adding a new rzfive_defconfig[*] instead?
I see there are already other configs, so riscv seems to follow the
arm rather than the arm64 (there can be only one ring^Wdefconfig) model.
Thanks!
[*] I do hope to reserve (possibly non-upstream) renesas_defconfig
for the army of future Renesas RISC-V SoCs that do not need a
dependency on NONPORTABLE ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:
On Fri, 29 Sep 2023 01:06:59 +0100 you wrote:
> From: Lad Prabhakar <[email protected]>
>
> Hi All,
>
> This patch series does the following:
> * Adds L2 cache node and marks the SoC as noncoherent
> * Enables IP blocks which were explicitly disabled and for
> which support is present
> * Enables the configs required for RZ/Five SoC
>
> [...]
Here is the summary with links:
- [1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node
(no matching commit)
- [2/5] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
(no matching commit)
- [3/5] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled
(no matching commit)
- [4/5] riscv: dts: renesas: rzfive-smarc: Drop dma properties from SSI1 node
(no matching commit)
- [5/5] riscv: configs: defconfig: Enable configs required for RZ/Five SoC
https://git.kernel.org/riscv/c/db38228c03d6
You are awesome, thank you!
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