The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
On platforms with Zhaoxin CPUs supporting this X86 feature, when
crc32c-intel and crc32c-generic are both registered, system will
use crc32c-intel because its .cra_priority is greater than
crc32c-generic.
When doing lmbench3 Create and Delete file test on partitions with
ext4 enabling metadata checksum, found using crc32c-generic driver
could get about 20% performance gain than using the driver crc32c-intel
on some Zhaoxin CPUs. Lower-level testing result is that with the same
input value the generic C implementation takes fewer time than the crc32c
instruction implementation on these CPUs. This case expect to use
crc32c-generic driver for these CPUs to get performance gain.
The presence of crc32c is enumerated by CPUID.01:ECX[SSE4.2] = 1, and
these CPUs other SSE4.2 instructions is ok.
Add a synthetic flag to indicates low performance CRC32C instruction
implementation, set this flag in Zhaoxin CPUs specific init phase,
and exclude CPUs which setting this flag from the driver crc32c-intel.
https://lkml.org/lkml/2020/12/21/789
Tony W Wang-oc (3):
x86/cpufeatures: Add low performance CRC32C instruction CPU feature
x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs
crypto: x86/crc32c-intel Exclude low performance CRC32C instruction
CPUs
arch/x86/crypto/crc32c-intel_glue.c | 5 +++++
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/centaur.c | 7 +++++++
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
arch/x86/kernel/cpu/zhaoxin.c | 6 ++++++
5 files changed, 20 insertions(+)
--
2.7.4
SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of
CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1.
Some Zhaoxin CPUs declare support SSE4.2 instruction sets but their
CRC32C instruction are working with low performance.
Add a synthetic CPU flag to indicates that the CRC32C instruction is
not working as intended. This low performance CRC32C instruction flag
is depend on X86_FEATURE_XMM4_2.
Signed-off-by: Tony W Wang-oc <[email protected]>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 84b8878..9e8151b 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -292,6 +292,7 @@
#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
#define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
#define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
+#define X86_FEATURE_CRC32C (11*32+ 8) /* "" Low performance CRC32C instruction */
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index 42af31b6..7d7fca7 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -72,6 +72,7 @@ static const struct cpuid_dep cpuid_deps[] = {
{ X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW },
{ X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES },
{ X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA },
+ { X86_FEATURE_CRC32C, X86_FEATURE_XMM4_2 },
{}
};
--
2.7.4
Some Zhaoxin CPUs declare support SSE4.2 instruction sets but
having a CRC32C instruction implementation that not working as
intended. Set low performance CRC32C flag on these CPUs for later
use.
Signed-off-by: Tony W Wang-oc <[email protected]>
---
arch/x86/kernel/cpu/centaur.c | 7 +++++++
arch/x86/kernel/cpu/zhaoxin.c | 6 ++++++
2 files changed, 13 insertions(+)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 345f7d9..13e6fbe 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -109,6 +109,13 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
+
+ /*
+ * These CPUs declare support SSE4.2 instruction sets but
+ * having low performance CRC32C instruction implementation.
+ */
+ if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
+ set_cpu_cap(c, X86_FEATURE_CRC32C);
}
static void init_centaur(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 05fa4ef..837ec65 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -79,6 +79,12 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)
c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
}
+ /*
+ * These CPUs declare support SSE4.2 instruction sets but
+ * having low performance CRC32C instruction implementation.
+ */
+ if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
+ set_cpu_cap(c, X86_FEATURE_CRC32C);
}
static void init_zhaoxin(struct cpuinfo_x86 *c)
--
2.7.4
On Thu, Jan 07, 2021 at 02:19:06PM +0800, Tony W Wang-oc wrote:
> SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of
> CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1.
> Some Zhaoxin CPUs declare support SSE4.2 instruction sets but their
> CRC32C instruction are working with low performance.
>
> Add a synthetic CPU flag to indicates that the CRC32C instruction is
> not working as intended. This low performance CRC32C instruction flag
> is depend on X86_FEATURE_XMM4_2.
>
> Signed-off-by: Tony W Wang-oc <[email protected]>
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/kernel/cpu/cpuid-deps.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 84b8878..9e8151b 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -292,6 +292,7 @@
> #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
> #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
> #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
> +#define X86_FEATURE_CRC32C (11*32+ 8) /* "" Low performance CRC32C instruction */
Didn't hpa say to create a BUG flag for it - X86_BUG...? Low performance
insn sounds like a bug and not a feature to me.
And call it X86_BUG_CRC32C_SLOW or ..._UNUSABLE to denote what it means.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On 07/01/2021 14:37, Borislav Petkov wrote:
> On Thu, Jan 07, 2021 at 02:19:06PM +0800, Tony W Wang-oc wrote:
>> SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of
>> CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1.
>> Some Zhaoxin CPUs declare support SSE4.2 instruction sets but their
>> CRC32C instruction are working with low performance.
>>
>> Add a synthetic CPU flag to indicates that the CRC32C instruction is
>> not working as intended. This low performance CRC32C instruction flag
>> is depend on X86_FEATURE_XMM4_2.
>>
>> Signed-off-by: Tony W Wang-oc <[email protected]>
>> ---
>> arch/x86/include/asm/cpufeatures.h | 1 +
>> arch/x86/kernel/cpu/cpuid-deps.c | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index 84b8878..9e8151b 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -292,6 +292,7 @@
>> #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
>> #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
>> #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
>> +#define X86_FEATURE_CRC32C (11*32+ 8) /* "" Low performance CRC32C instruction */
>
> Didn't hpa say to create a BUG flag for it - X86_BUG...? Low performance
> insn sounds like a bug and not a feature to me.
>
> And call it X86_BUG_CRC32C_SLOW or ..._UNUSABLE to denote what it means.
>
This issue will be enhanced by hardware and patch submit will be pending.
Sincerely
Tonyw
On 07/01/2021 23:52, Dave Hansen wrote:
> On 1/6/21 10:19 PM, Tony W Wang-oc wrote:
>> + /*
>> + * These CPUs declare support SSE4.2 instruction sets but
>> + * having low performance CRC32C instruction implementation.
>> + */
>> + if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
>> + set_cpu_cap(c, X86_FEATURE_CRC32C);
>> }
>
> On the Intel side, we've tried to move away from open-coded model
> numbers. Say another CPU is released that has a microarchitecture close
> to 0x3b, but has a model of 0x3c. It's a *LOT* easier to grep for
> INTEL_FAM6_NEHALEM (or whatever) than 0x3c. See:
>
> arch/x86/include/asm/intel-family.h
>
> for examples.
> .
>
Got it, thanks for your suggestion.
Sincerely
Tonyw
On Mon, Jan 11, 2021 at 06:51:59PM +0800, Tony W Wang-oc wrote:
> This issue will be enhanced by hardware and patch submit will be pending.
I have no clue what that has to do with your current patch... you might
need to explain more verbosely.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On January 6, 2021 10:37:50 PM PST, Borislav Petkov <[email protected]> wrote:
>On Thu, Jan 07, 2021 at 02:19:06PM +0800, Tony W Wang-oc wrote:
>> SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of
>> CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1.
>> Some Zhaoxin CPUs declare support SSE4.2 instruction sets but their
>> CRC32C instruction are working with low performance.
>>
>> Add a synthetic CPU flag to indicates that the CRC32C instruction is
>> not working as intended. This low performance CRC32C instruction flag
>> is depend on X86_FEATURE_XMM4_2.
>>
>> Signed-off-by: Tony W Wang-oc <[email protected]>
>> ---
>> arch/x86/include/asm/cpufeatures.h | 1 +
>> arch/x86/kernel/cpu/cpuid-deps.c | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h
>b/arch/x86/include/asm/cpufeatures.h
>> index 84b8878..9e8151b 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -292,6 +292,7 @@
>> #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in
>kernel entry SWAPGS path */
>> #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split
>lock */
>> #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread
>Memory Bandwidth Allocation */
>> +#define X86_FEATURE_CRC32C (11*32+ 8) /* "" Low performance CRC32C
>instruction */
>
>Didn't hpa say to create a BUG flag for it - X86_BUG...? Low
>performance
>insn sounds like a bug and not a feature to me.
>
>And call it X86_BUG_CRC32C_SLOW or ..._UNUSABLE to denote what it
>means.
>
>Thx.
Yes, it should be a BUG due to the inclusion properties of BUG v FEATURE.
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
On 11/01/2021 19:03, Borislav Petkov wrote:
> On Mon, Jan 11, 2021 at 06:51:59PM +0800, Tony W Wang-oc wrote:
>> This issue will be enhanced by hardware and patch submit will be pending.
>
> I have no clue what that has to do with your current patch... you might
> need to explain more verbosely.
>
After internal research, decided to fix the low performance crc32c
instruction issue on these Zhaoxin CPUs by microcode. So, do not need
this patch anymore.
Sincerely
Tonyw