Changes in v2:
- Dropped tomato-r1 PCIe0 enablement
- dp-intf aliases addition transferred to mt8195.dtsi
- Changed thermal zones names and critical trip point temperatures
for Linux to initiate thermal shutdown before HW protection kick-in.
This series adds support for the WiFi card on PCI-Express,
eDP (internal) and DP (external) displays and adds thermal
configuration for the "extra" thermistors present on Cherry boards.
All Cherry Chromebooks now have working display and wireless
connectivity!
At this point, the only missing component is vcodec decoders, but
that's to be done in mt8195.dtsi, globally, not machine specific.
Please note that in this series the eDP panel was put on aux-bus,
hence this depends on the series introducing support for it [1]
in the mtk-dp driver.
[1]: https://lore.kernel.org/lkml/[email protected]/
AngeloGioacchino Del Regno (4):
arm64: dts: mediatek: cherry: Add platform thermal configuration
arm64: dts: mediatek: mt8195: Assign dp-intf aliases
arm64: dts: mediatek: cherry: Configure eDP and internal display
arm64: dts: mediatek: cherry: Enable PCI-Express ports for WiFi
.../boot/dts/mediatek/mt8195-cherry.dtsi | 162 ++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +
2 files changed, 164 insertions(+)
--
2.40.0
On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected
over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports
to enable enumerating this chip.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index adbda4dccdd5..eca5df85fe33 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -565,6 +565,13 @@ flash@0 {
};
};
+&pcie1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins_default>;
+};
+
&pio {
mediatek,rsel-resistance-in-si-unit;
pinctrl-names = "default";
@@ -959,6 +966,24 @@ pins-vreg-en {
};
};
+ pcie0_pins_default: pcie0-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
+ <PINMUX_GPIO20__FUNC_PERSTN>,
+ <PINMUX_GPIO21__FUNC_CLKREQN>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_pins_default: pcie1-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
+ <PINMUX_GPIO23__FUNC_CLKREQN_1>,
+ <PINMUX_GPIO24__FUNC_WAKEN_1>;
+ bias-pull-up;
+ };
+ };
+
pio_default: pio-default-pins {
pins-wifi-enable {
pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
--
2.40.0
Add the required nodes to enable the DisplayPort interface, connected
to the Embedded DisplayPort port, where we have an internal display.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 4229f4f7dc2f..adbda4dccdd5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -47,6 +47,18 @@ memory@40000000 {
reg = <0 0x40000000 0 0x80000000>;
};
+ pp3300_disp_x: regulator-pp3300-disp-x {
+ compatible = "regulator-fixed";
+ regulator-name = "pp3300_disp_x";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 55 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_fixed_pins>;
+ regulator-always-on;
+ };
+
/* system wide LDO 3.3V power rail */
pp3300_z5: regulator-pp3300-ldo-z5 {
compatible = "regulator-fixed";
@@ -288,6 +300,20 @@ port@1 {
reg = <1>;
edp_out: endpoint {
data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&pp3300_disp_x>;
+ backlight = <&backlight_lcd0>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&edp_out>;
+ };
};
};
};
@@ -927,6 +953,12 @@ pins-cs {
};
};
+ panel_fixed_pins: panel-pwr-default-pins {
+ pins-vreg-en {
+ pinmux = <PINMUX_GPIO55__FUNC_GPIO55>;
+ };
+ };
+
pio_default: pio-default-pins {
pins-wifi-enable {
pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
--
2.40.0
On Mon, Apr 24, 2023 at 7:25 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> Add the required nodes to enable the DisplayPort interface, connected
> to the Embedded DisplayPort port, where we have an internal display.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 32 +++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 4229f4f7dc2f..adbda4dccdd5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -47,6 +47,18 @@ memory@40000000 {
> reg = <0 0x40000000 0 0x80000000>;
> };
>
> + pp3300_disp_x: regulator-pp3300-disp-x {
> + compatible = "regulator-fixed";
> + regulator-name = "pp3300_disp_x";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&pio 55 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&panel_fixed_pins>;
> + regulator-always-on;
I think you missed my comment on v1 about this regulator's supplier and
enable delay.
ChenYu
> + };
> +
> /* system wide LDO 3.3V power rail */
> pp3300_z5: regulator-pp3300-ldo-z5 {
> compatible = "regulator-fixed";
> @@ -288,6 +300,20 @@ port@1 {
> reg = <1>;
> edp_out: endpoint {
> data-lanes = <0 1 2 3>;
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> +
> + aux-bus {
> + panel {
> + compatible = "edp-panel";
> + power-supply = <&pp3300_disp_x>;
> + backlight = <&backlight_lcd0>;
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&edp_out>;
> + };
> };
> };
> };
> @@ -927,6 +953,12 @@ pins-cs {
> };
> };
>
> + panel_fixed_pins: panel-pwr-default-pins {
> + pins-vreg-en {
> + pinmux = <PINMUX_GPIO55__FUNC_GPIO55>;
> + };
> + };
> +
> pio_default: pio-default-pins {
> pins-wifi-enable {
> pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
> --
> 2.40.0
>
>
On Mon, Apr 24, 2023 at 7:25 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected
> over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports
> to enable enumerating this chip.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> Tested-by: Chen-Yu Tsai <[email protected]>
> ---
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index adbda4dccdd5..eca5df85fe33 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -565,6 +565,13 @@ flash@0 {
> };
> };
>
> +&pcie1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_pins_default>;
> +};
> +
> &pio {
> mediatek,rsel-resistance-in-si-unit;
> pinctrl-names = "default";
> @@ -959,6 +966,24 @@ pins-vreg-en {
> };
> };
>
> + pcie0_pins_default: pcie0-default-pins {
> + pins-bus {
> + pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
> + <PINMUX_GPIO20__FUNC_PERSTN>,
> + <PINMUX_GPIO21__FUNC_CLKREQN>;
> + bias-pull-up;
> + };
> + };
I think we should remove this. We can add it later with the actual device
that has NVMe.
Otherwise,
Reviewed-by: Chen-Yu Tsai <[email protected]>
> + pcie1_pins_default: pcie1-default-pins {
> + pins-bus {
> + pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
> + <PINMUX_GPIO23__FUNC_CLKREQN_1>,
> + <PINMUX_GPIO24__FUNC_WAKEN_1>;
> + bias-pull-up;
> + };
> + };
> +
> pio_default: pio-default-pins {
> pins-wifi-enable {
> pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
> --
> 2.40.0
>
On 24/04/2023 13:25, AngeloGioacchino Del Regno wrote:
> On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected
> over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports
> to enable enumerating this chip.
>
> Signed-off-by: AngeloGioacchino Del Regno<[email protected]>
> Tested-by: Chen-Yu Tsai<[email protected]>
Reviewed-by: Alexandre Mergnat <[email protected]>
Regards,
Alexandre
Il 25/04/23 10:24, Chen-Yu Tsai ha scritto:
> On Mon, Apr 24, 2023 at 7:25 PM AngeloGioacchino Del Regno
> <[email protected]> wrote:
>>
>> Add the required nodes to enable the DisplayPort interface, connected
>> to the Embedded DisplayPort port, where we have an internal display.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
>> ---
>> .../boot/dts/mediatek/mt8195-cherry.dtsi | 32 +++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> index 4229f4f7dc2f..adbda4dccdd5 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> @@ -47,6 +47,18 @@ memory@40000000 {
>> reg = <0 0x40000000 0 0x80000000>;
>> };
>>
>> + pp3300_disp_x: regulator-pp3300-disp-x {
>> + compatible = "regulator-fixed";
>> + regulator-name = "pp3300_disp_x";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + enable-active-high;
>> + gpio = <&pio 55 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&panel_fixed_pins>;
>> + regulator-always-on;
>
> I think you missed my comment on v1 about this regulator's supplier and
> enable delay.
>
Sorry, it wasn't my intention to ignore that. Will check that out and
push a v3 asap.
> ChenYu
>
>> + };
>> +
>> /* system wide LDO 3.3V power rail */
>> pp3300_z5: regulator-pp3300-ldo-z5 {
>> compatible = "regulator-fixed";
>> @@ -288,6 +300,20 @@ port@1 {
>> reg = <1>;
>> edp_out: endpoint {
>> data-lanes = <0 1 2 3>;
>> + remote-endpoint = <&panel_in>;
>> + };
>> + };
>> + };
>> +
>> + aux-bus {
>> + panel {
>> + compatible = "edp-panel";
>> + power-supply = <&pp3300_disp_x>;
>> + backlight = <&backlight_lcd0>;
>> + port {
>> + panel_in: endpoint {
>> + remote-endpoint = <&edp_out>;
>> + };
>> };
>> };
>> };
>> @@ -927,6 +953,12 @@ pins-cs {
>> };
>> };
>>
>> + panel_fixed_pins: panel-pwr-default-pins {
>> + pins-vreg-en {
>> + pinmux = <PINMUX_GPIO55__FUNC_GPIO55>;
>> + };
>> + };
>> +
>> pio_default: pio-default-pins {
>> pins-wifi-enable {
>> pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
>> --
>> 2.40.0
>>
>>
On 24/04/2023 13:25, AngeloGioacchino Del Regno wrote:
> On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected
> over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports
> to enable enumerating this chip.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> Tested-by: Chen-Yu Tsai <[email protected]>
Applied, thanks
> ---
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index adbda4dccdd5..eca5df85fe33 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -565,6 +565,13 @@ flash@0 {
> };
> };
>
> +&pcie1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_pins_default>;
> +};
> +
> &pio {
> mediatek,rsel-resistance-in-si-unit;
> pinctrl-names = "default";
> @@ -959,6 +966,24 @@ pins-vreg-en {
> };
> };
>
> + pcie0_pins_default: pcie0-default-pins {
> + pins-bus {
> + pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
> + <PINMUX_GPIO20__FUNC_PERSTN>,
> + <PINMUX_GPIO21__FUNC_CLKREQN>;
> + bias-pull-up;
> + };
> + };
> +
> + pcie1_pins_default: pcie1-default-pins {
> + pins-bus {
> + pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
> + <PINMUX_GPIO23__FUNC_CLKREQN_1>,
> + <PINMUX_GPIO24__FUNC_WAKEN_1>;
> + bias-pull-up;
> + };
> + };
> +
> pio_default: pio-default-pins {
> pins-wifi-enable {
> pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;