This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and
SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood.
The SoC specific stubs use the pinctrl-mvebu core driver that handles
pinctrl API and register accesses for common pinctrl registers.
As especially Dove has some pinctrl registers that do not match the
common pinctrl register layout the core driver has been extended by
some callbacks to allow uncommon Dove pinctrl registers.
DT binding documentation is added for all supported SoCs but as
Dove and Kirkwood are not yet ready for full DT support, the pinctrl
driver is only activated for Armada 370 and XP.
The driver has been tested on Dove, 88f6281 variant of Kirkwood,
Armada 370, and XP.
Sebastian Hesselbarth (3):
pinctrl: mvebu: pinctrl driver core
pinctrl: mvebu: dove pinctrl driver
pinctrl: mvebu: kirkwood pinctrl driver
Thomas Petazzoni (8):
pinctrl: mvebu: add pinctrl driver for Armada 370
pinctrl: mvebu: add pinctrl driver for Armada XP
ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs
ARM: mvebu: Add pinctrl support to Armada XP SoCs
ARM: mvebu: Add pinctrl support to Armada 370 SoC
ARM: mvebu: adjust Armada XP evaluation board DTS
arm: mvebu: enable PINCTRL usage
arm: mvebu: add pinctrl support in defconfig
.../pinctrl/marvell,armada-370-pinctrl.txt | 95 +++
.../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 100 +++
.../bindings/pinctrl/marvell,dove-pinctrl.txt | 71 ++
.../bindings/pinctrl/marvell,kirkwood-pinctrl.txt | 279 +++++++
.../bindings/pinctrl/marvell,mvebu-pinctrl.txt | 46 ++
arch/arm/Kconfig | 3 +
arch/arm/boot/dts/armada-370-xp.dtsi | 7 +
arch/arm/boot/dts/armada-370.dtsi | 4 +
arch/arm/boot/dts/armada-xp-db.dts | 4 +-
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 27 +
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 27 +
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 27 +
arch/arm/configs/mvebu_defconfig | 2 +
drivers/pinctrl/Kconfig | 34 +
drivers/pinctrl/Makefile | 5 +
drivers/pinctrl/pinctrl-armada-370.c | 421 +++++++++++
drivers/pinctrl/pinctrl-armada-xp.c | 466 ++++++++++++
drivers/pinctrl/pinctrl-dove.c | 622 ++++++++++++++++
drivers/pinctrl/pinctrl-kirkwood.c | 460 ++++++++++++
drivers/pinctrl/pinctrl-mvebu.c | 758 ++++++++++++++++++++
drivers/pinctrl/pinctrl-mvebu.h | 175 +++++
21 files changed, 3631 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
create mode 100644 drivers/pinctrl/pinctrl-dove.c
create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
create mode 100644 drivers/pinctrl/pinctrl-mvebu.h
Signed-off-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
--
1.7.10.4
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pinctrl/marvell,dove-pinctrl.txt | 71 +++
arch/arm/Kconfig | 1 +
drivers/pinctrl/Kconfig | 9 +-
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-dove.c | 622 ++++++++++++++++++++
5 files changed, 703 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-dove.c
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
new file mode 100644
index 0000000..9e6eea2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -0,0 +1,71 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name pins functions
+================================================================================
+mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+ uart1(rts)
+mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+ uart1(cts), lcd-spi(cs1)
+mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8 8 gpio, pmu, watchdog(rstout)
+mpp9 9 gpio, pmu, pex1(clkreq)
+mpp10 10 gpio, pmu, ssp(sclk)
+mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+ sdio1(ledctrl), pex0(clkreq)
+mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+ ssp(extclk)
+mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+ ac97-1(sysclko)
+mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+ ac97(sysclko)
+mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+ uart1(cts), ssp(sfrm)
+mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+ lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+ lcd-spi(sck), ssp(sclk)
+mpp_camera 24-39 gpio, camera
+mpp_sdio0 40-45 gpio, sdio0
+mpp_sdio1 46-51 gpio, sdio1
+mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+ ssp/twsi
+mpp_spi0 58-61 gpio, spi0
+mpp_uart1 62-63 gpio, uart1
+mpp_nand 64-71 gpo, nand
+audio0 - i2s, ac97
+twsi - none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+ - gpio : gpio on pins 52-57
+ - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+ - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
+ - spdifo : spdifo on pin 57, gpio on pins 52-55
+ - twsi : twsi on pins 56,57, gpio on pins 52-55
+ - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
+ - ssp : ssp on pins 52-55, gpio on pins 56,57
+ - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+ audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..cd3d827 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -584,6 +584,7 @@ config ARCH_DOVE
select GENERIC_CLOCKEVENTS
select NEED_MACH_IO_H
select PLAT_ORION
+ select PINCTRL
help
Support for the Marvell Dove SoC 88AP510
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b968335..e2427eb 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -147,7 +147,7 @@ config PINCTRL_COH901
config PINCTRL_MVEBU
bool "Marvell SoC pin controller drivers"
- depends on ARCH_MVEBU
+ depends on ARCH_MVEBU || ARCH_DOVE
select PINMUX
select PINCONF
help
@@ -155,6 +155,13 @@ config PINCTRL_MVEBU
This is only the driver core and additionally needs a SoC specific
driver.
+config PINCTRL_DOVE
+ bool "Support for Marvell Dove SoCs"
+ depends on PINCTRL_MVEBU
+ help
+ Say yes here to support pinctrl driver on Marvell Dove SoCs
+ (88AP510).
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 007ed32..d1327df 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c
new file mode 100644
index 0000000..b16de42
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-dove.c
@@ -0,0 +1,622 @@
+/*
+ * Marvell Dove pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
+#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
+#define DOVE_AU0_AC97_SEL (1 << 16)
+#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
+#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
+#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
+#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
+#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define DOVE_SSP_ON_AU1 (1 << 0)
+#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
+#define DOVE_NAND_GPIO_EN (1 << 0)
+#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
+#define DOVE_SPI_GPIO_SEL (1 << 5)
+#define DOVE_UART1_GPIO_SEL (1 << 4)
+#define DOVE_AU1_GPIO_SEL (1 << 3)
+#define DOVE_CAM_GPIO_SEL (1 << 2)
+#define DOVE_SD1_GPIO_SEL (1 << 1)
+#define DOVE_SD0_GPIO_SEL (1 << 0)
+
+static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned off = (ctrl->pid / 8) * 4;
+ unsigned shift = (ctrl->pid % 8) * 4;
+ unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+ unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+ if (pmu & (1 << ctrl->pid))
+ *config = 0x10;
+ else
+ *config = (mpp >> shift) & 0xf;
+ return 0;
+}
+
+static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned off = (ctrl->pid / 8) * 4;
+ unsigned shift = (ctrl->pid % 8) * 4;
+ unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+ unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+ if (config == 0x10)
+ writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+ else {
+ writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+ mpp &= ~(0xf << shift);
+ mpp |= config << shift;
+ writel(mpp, DOVE_MPP_VIRT_BASE + off);
+ }
+ return 0;
+}
+
+static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ unsigned long mask;
+
+ if (ctrl->pid == 24)
+ mask = DOVE_CAM_GPIO_SEL;
+ else if (ctrl->pid == 40)
+ mask = DOVE_SD0_GPIO_SEL;
+ else if (ctrl->pid == 46)
+ mask = DOVE_SD1_GPIO_SEL;
+ else if (ctrl->pid == 58)
+ mask = DOVE_SPI_GPIO_SEL;
+ else if (ctrl->pid == 62)
+ mask = DOVE_UART1_GPIO_SEL;
+ else
+ return -EINVAL;
+
+ *config = ((mpp4 & mask) != 0);
+
+ return 0;
+}
+
+static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ unsigned long mask;
+
+ if (ctrl->pid == 24)
+ mask = DOVE_CAM_GPIO_SEL;
+ else if (ctrl->pid == 40)
+ mask = DOVE_SD0_GPIO_SEL;
+ else if (ctrl->pid == 46)
+ mask = DOVE_SD1_GPIO_SEL;
+ else if (ctrl->pid == 58)
+ mask = DOVE_SPI_GPIO_SEL;
+ else if (ctrl->pid == 62)
+ mask = DOVE_UART1_GPIO_SEL;
+ else
+ return -EINVAL;
+
+ mpp4 &= ~mask;
+ if (config)
+ mpp4 |= mask;
+
+ writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+
+ return 0;
+}
+
+static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+ *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
+
+ return 0;
+}
+
+static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+ gmpp &= ~DOVE_NAND_GPIO_EN;
+ if (config)
+ gmpp |= DOVE_NAND_GPIO_EN;
+
+ writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+
+ return 0;
+}
+
+static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+ *config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
+
+ return 0;
+}
+
+static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+ pmu &= ~DOVE_AU0_AC97_SEL;
+ if (config)
+ pmu |= DOVE_AU0_AC97_SEL;
+ writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
+
+ return 0;
+}
+
+static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+ unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+ unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+ *config = 0;
+ if (mpp4 & DOVE_AU1_GPIO_SEL)
+ *config |= 0x8;
+ if (sspc1 & DOVE_SSP_ON_AU1)
+ *config |= 0x4;
+ if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
+ *config |= 0x2;
+ if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
+ *config |= 0x1;
+
+ /* SSP/TWSI only if I2S1 not set*/
+ if ((*config & 0x8) == 0)
+ *config &= ~(0x4 | 0x1);
+ /* TWSI only if SPDIFO not set*/
+ if ((*config & 0x2) == 0)
+ *config &= ~(0x1);
+ return 0;
+}
+
+static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+ unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+ unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+ if (config & 0x1)
+ gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+ if (config & 0x2)
+ gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
+ if (config & 0x4)
+ sspc1 |= DOVE_SSP_ON_AU1;
+ if (config & 0x8)
+ mpp4 |= DOVE_AU1_GPIO_SEL;
+
+ writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+ writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
+ writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+ writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+ return 0;
+}
+
+/* mpp[52:57] gpio pins depend heavily on current config;
+ * gpio_req does not try to mux in gpio capabilities to not
+ * break other functions. If you require all mpps as gpio
+ * enforce gpio setting by pinctrl mapping.
+ */
+static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
+{
+ unsigned long config;
+
+ dove_audio1_ctrl_get(ctrl, &config);
+
+ switch (config) {
+ /* mode 0x00 i2s1/spdifo : no gpio */
+ /* mode 0x0c ssp/spdifo : no gpio */
+ /* mode 0x0f ssp/twsi : no gpio */
+ case 0x00:
+ case 0x0c:
+ case 0x0f:
+ return -ENOTSUPP;
+
+ /* mode 0x02 i2s1 : gpio[56:57] */
+ /* mode 0x0e ssp : gpio[56:57] */
+ case 0x02:
+ case 0x0e:
+ if (pid >= 56)
+ return 0;
+
+ /* mode 0x08 spdifo : gpio[52:55] */
+ /* mode 0x0b twsi : gpio[52:55] */
+ case 0x08:
+ case 0x0b:
+ if (pid <= 55)
+ return 0;
+
+ /* mode 0x0a/gpio : all gpio */
+ case 0x0a:
+ return 0;
+ }
+
+ return -ENOTSUPP;
+}
+
+/* mpp[52:57] has gpio pins capable of in and out */
+static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
+ bool input)
+{
+ return 0;
+}
+
+static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+ unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+ *config = 0;
+ if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
+ *config = 0x1;
+ else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
+ *config = 0x2;
+ else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
+ *config = 0x3;
+
+ return 0;
+}
+
+static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+ unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+ gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
+ gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+
+ switch (config) {
+ case 1:
+ gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+ break;
+ case 2:
+ gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+ break;
+ case 3:
+ gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+ break;
+ }
+
+ writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
+ writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+ return 0;
+}
+
+static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
+ MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
+ MPP_REG_CTRL(16, 23),
+ MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
+ MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
+ MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
+ MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
+ MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
+ MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
+ MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
+ MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
+ MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
+};
+
+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "rts"),
+ MPP_FUNCTION(0x03, "sdio0", "cd"),
+ MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(1,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "cts"),
+ MPP_FUNCTION(0x03, "sdio0", "wp"),
+ MPP_FUNCTION(0x0f, "lcd1", "pwm"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(2,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "sata", "prsnt"),
+ MPP_FUNCTION(0x02, "uart2", "txd"),
+ MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+ MPP_FUNCTION(0x04, "uart1", "rts"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(3,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "sata", "act"),
+ MPP_FUNCTION(0x02, "uart2", "rxd"),
+ MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+ MPP_FUNCTION(0x04, "uart1", "cts"),
+ MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(4,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "rts"),
+ MPP_FUNCTION(0x03, "sdio1", "cd"),
+ MPP_FUNCTION(0x04, "spi1", "miso"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(5,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "cts"),
+ MPP_FUNCTION(0x03, "sdio1", "wp"),
+ MPP_FUNCTION(0x04, "spi1", "cs"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(6,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "txd"),
+ MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+ MPP_FUNCTION(0x04, "spi1", "mosi"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(7,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "rxd"),
+ MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+ MPP_FUNCTION(0x04, "spi1", "sck"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(8,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "watchdog", "rstout"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(9,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x05, "pex1", "clkreq"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(10,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x05, "ssp", "sclk"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(11,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "sata", "prsnt"),
+ MPP_FUNCTION(0x02, "sata-1", "act"),
+ MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+ MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+ MPP_FUNCTION(0x05, "pex0", "clkreq"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(12,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "sata", "act"),
+ MPP_FUNCTION(0x02, "uart2", "rts"),
+ MPP_FUNCTION(0x03, "audio0", "extclk"),
+ MPP_FUNCTION(0x04, "sdio1", "cd"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(13,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "cts"),
+ MPP_FUNCTION(0x03, "audio1", "extclk"),
+ MPP_FUNCTION(0x04, "sdio1", "wp"),
+ MPP_FUNCTION(0x05, "ssp", "extclk"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(14,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "txd"),
+ MPP_FUNCTION(0x04, "sdio1", "buspwr"),
+ MPP_FUNCTION(0x05, "ssp", "rxd"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(15,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "rxd"),
+ MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+ MPP_FUNCTION(0x05, "ssp", "sfrm"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(16,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "rts"),
+ MPP_FUNCTION(0x03, "sdio0", "cd"),
+ MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
+ MPP_FUNCTION(0x05, "ac97", "sdi1")),
+ MPP_MODE(17,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
+ MPP_FUNCTION(0x02, "uart3", "cts"),
+ MPP_FUNCTION(0x03, "sdio0", "wp"),
+ MPP_FUNCTION(0x04, "twsi", "sda"),
+ MPP_FUNCTION(0x05, "ac97", "sdi2")),
+ MPP_MODE(18,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "txd"),
+ MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+ MPP_FUNCTION(0x04, "lcd0", "pwm"),
+ MPP_FUNCTION(0x05, "ac97", "sdi3")),
+ MPP_MODE(19,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "rxd"),
+ MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+ MPP_FUNCTION(0x04, "twsi", "sck")),
+ MPP_MODE(20,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "ac97", "sysclko"),
+ MPP_FUNCTION(0x02, "lcd-spi", "miso"),
+ MPP_FUNCTION(0x03, "sdio1", "cd"),
+ MPP_FUNCTION(0x05, "sdio0", "cd"),
+ MPP_FUNCTION(0x06, "spi1", "miso")),
+ MPP_MODE(21,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "uart1", "rts"),
+ MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
+ MPP_FUNCTION(0x03, "sdio1", "wp"),
+ MPP_FUNCTION(0x04, "ssp", "sfrm"),
+ MPP_FUNCTION(0x05, "sdio0", "wp"),
+ MPP_FUNCTION(0x06, "spi1", "cs")),
+ MPP_MODE(22,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "uart1", "cts"),
+ MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
+ MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+ MPP_FUNCTION(0x04, "ssp", "txd"),
+ MPP_FUNCTION(0x05, "sdio0", "buspwr"),
+ MPP_FUNCTION(0x06, "spi1", "mosi")),
+ MPP_MODE(23,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "lcd-spi", "sck"),
+ MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+ MPP_FUNCTION(0x04, "ssp", "sclk"),
+ MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
+ MPP_FUNCTION(0x06, "spi1", "sck")),
+ MPP_MODE(24,
+ MPP_FUNCTION(0x00, "camera", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(40,
+ MPP_FUNCTION(0x00, "sdio0", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(46,
+ MPP_FUNCTION(0x00, "sdio1", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(52,
+ MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
+ MPP_FUNCTION(0x02, "i2s1", NULL),
+ MPP_FUNCTION(0x08, "spdifo", NULL),
+ MPP_FUNCTION(0x0a, "gpio", NULL),
+ MPP_FUNCTION(0x0b, "twsi", NULL),
+ MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
+ MPP_FUNCTION(0x0e, "ssp", NULL),
+ MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
+ MPP_MODE(58,
+ MPP_FUNCTION(0x00, "spi0", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(62,
+ MPP_FUNCTION(0x00, "uart1", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(64,
+ MPP_FUNCTION(0x00, "nand", NULL),
+ MPP_FUNCTION(0x01, "gpo", NULL)),
+ MPP_MODE(72,
+ MPP_FUNCTION(0x00, "i2s", NULL),
+ MPP_FUNCTION(0x01, "ac97", NULL)),
+ MPP_MODE(73,
+ MPP_FUNCTION(0x00, "none", NULL),
+ MPP_FUNCTION(0x01, "opt1", NULL),
+ MPP_FUNCTION(0x02, "opt2", NULL),
+ MPP_FUNCTION(0x03, "opt3", NULL)),
+};
+
+static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 32),
+ MPP_GPIO_RANGE(2, 64, 64, 8),
+};
+
+static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
+ .controls = dove_mpp_controls,
+ .ncontrols = ARRAY_SIZE(dove_mpp_controls),
+ .modes = dove_mpp_modes,
+ .nmodes = ARRAY_SIZE(dove_mpp_modes),
+ .gpioranges = dove_mpp_gpio_ranges,
+ .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
+ .variant = 0,
+};
+
+static struct clk *pdma_clk;
+
+static struct of_device_id dove_pinctrl_of_match[] __devinitdata = {
+ { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
+ { }
+};
+
+static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match =
+ of_match_device(dove_pinctrl_of_match, &pdev->dev);
+ int ret;
+
+ if (match)
+ pdev->dev.platform_data = match->data;
+
+ /*
+ * General MPP Configuration Register is part of pdma registers.
+ * grab clk to make sure it is clocked.
+ */
+ pdma_clk = clk_get_sys("dove-pdma", NULL);
+ if (IS_ERR(pdma_clk)) {
+ dev_err(&pdev->dev, "unable to get pdma clk\n");
+ return -ENODEV;
+ }
+
+ clk_prepare_enable(pdma_clk);
+ ret = mvebu_pinctrl_probe(pdev);
+ if (!ret)
+ return 0;
+
+ clk_disable_unprepare(pdma_clk);
+ clk_put(pdma_clk);
+ return ret;
+}
+
+static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = mvebu_pinctrl_remove(pdev);
+ if (!IS_ERR(pdma_clk)) {
+ clk_disable_unprepare(pdma_clk);
+ clk_put(pdma_clk);
+ }
+ return ret;
+}
+
+static struct platform_driver dove_pinctrl_driver = {
+ .driver = {
+ .name = "dove-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(dove_pinctrl_of_match),
+ },
+ .probe = dove_pinctrl_probe,
+ .remove = __devexit_p(dove_pinctrl_remove),
+};
+
+module_platform_driver(dove_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <[email protected]>");
+MODULE_DESCRIPTION("Marvell Dove pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.10.4
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pinctrl/marvell,kirkwood-pinctrl.txt | 279 ++++++++++++
arch/arm/Kconfig | 1 +
drivers/pinctrl/Kconfig | 9 +-
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-kirkwood.c | 460 ++++++++++++++++++++
5 files changed, 749 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
new file mode 100644
index 0000000..361bccb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+ "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+ "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6 6 sysrst(out), spi(mosi), ptp(trig)
+mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+ mii(col)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+ mii(crs)
+mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+ ptp-2(trig)
+mpp12 12 gpo, sdio(clk)
+mpp13 13 gpio, sdio(cmd), uart1(txd)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17 17 gpio, sdio(d3)
+mpp18 18 gpo, nand(io0)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, mii(rxerr)
+mpp21 21 gpio, audio(spdifi)
+mpp22 22 gpio, audio(spdifo)
+mpp23 23 gpio, audio(rmclk)
+mpp24 24 gpio, audio(bclk)
+mpp25 25 gpio, audio(sdo)
+mpp26 26 gpio, audio(lrclk)
+mpp27 27 gpio, audio(mclk)
+mpp28 28 gpio, audio(sdi)
+mpp29 29 gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6 6 sysrst(out), spi(mosi), ptp(trig)
+mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+ mii(col), mii-1(rxerr)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+ mii(crs), sata0(prsnt)
+mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+ ptp-2(trig), sata0(act)
+mpp12 12 gpo, sdio(clk)
+mpp13 13 gpio, sdio(cmd), uart1(txd)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17 17 gpio, sdio(d3), sata0(prsnt)
+mpp18 18 gpo, nand(io0)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, ge1(txd0)
+mpp21 21 gpio, ge1(txd1), sata0(act)
+mpp22 22 gpio, ge1(txd2)
+mpp23 23 gpio, ge1(txd3), sata0(prsnt)
+mpp24 24 gpio, ge1(rxd0)
+mpp25 25 gpio, ge1(rxd1)
+mpp26 26 gpio, ge1(rxd2)
+mpp27 27 gpio, ge1(rxd3)
+mpp28 28 gpio, ge1(col)
+mpp29 29 gpio, ge1(txclk)
+mpp30 30 gpio, ge1(rxclk)
+mpp31 31 gpio, ge1(rxclk)
+mpp32 32 gpio, ge1(txclko)
+mpp33 33 gpo, ge1(txclk)
+mpp34 34 gpio, ge1(txen)
+mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6 6 sysrst(out), spi(mosi), ptp(trig)
+mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+ mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+ mii(crs), sata0(prsnt)
+mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+ ptp-2(trig), sata0(act)
+mpp12 12 gpo, sdio(clk)
+mpp13 13 gpio, sdio(cmd), uart1(txd)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+ sata1(act)
+mpp17 17 gpio, sdio(d3), sata0(prsnt)
+mpp18 18 gpo, nand(io0)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+ sata1(act)
+mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+ audio(spdifo)
+mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+ sata1(prsnt)
+mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+ audio(bclk)
+mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33 33 gpo, ge1(txclk), tdm(drx)
+mpp34 34 gpio, ge1(txen), tdm(spi-cs1)
+mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6 6 sysrst(out), spi(mosi), ptp(trig)
+mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+ mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+ mii(crs), sata0(prsnt)
+mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+ ptp-2(trig), sata0(act)
+mpp12 12 gpio, sdio(clk)
+mpp13 13 gpio, sdio(cmd), uart1(txd)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+ sata1(act)
+mpp17 17 gpio, sdio(d3), sata0(prsnt)
+mpp18 18 gpo, nand(io0)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+ sata1(act)
+mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+ audio(spdifo)
+mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+ sata1(prsnt)
+mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+ audio(bclk)
+mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33 33 gpo, ge1(txclk), tdm(drx)
+mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45 45 gpio, ts(mp9), tdm(pclk)
+mpp46 46 gpio, ts(mp10), tdm(fs)
+mpp47 47 gpio, ts(mp11), tdm(drx)
+mpp48 48 gpio, ts(mp12), tdm(dtx)
+mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6 6 sysrst(out), spi(mosi)
+mpp7 7 gpo, spi(cs), lcd(pwm)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+ mii-1(rxerr), sata1(prsnt)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+ sata0(prsnt)
+mpp10 10 gpo, spi(sck), uart0(txd), sata1(act)
+mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+ audio(spdifi), audio-1(sdi)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+ spi(cs)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+ sata1(act), lcd(extclk)
+mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18 18 gpo, nand(io0), pex(clkreq)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+ sata1(act), lcd(d0)
+mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+ audio(spdifo), lcd(d1)
+mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+ sata1(prsnt), lcd(d2)
+mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+ audio(bclk), lcd(d3)
+mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+ lcd(d4)
+mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+ lcd(d5)
+mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+ lcd(d6)
+mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+ lcd(d7)
+mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+ lcd(d8)
+mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+ lcd(d15)
+mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cd3d827..361f513 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
select GENERIC_CLOCKEVENTS
select NEED_MACH_IO_H
select PLAT_ORION
+ select PINCTRL
help
Support for the following Marvell Kirkwood series SoCs:
88F6180, 88F6192 and 88F6281.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e2427eb..1f84090 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -147,7 +147,7 @@ config PINCTRL_COH901
config PINCTRL_MVEBU
bool "Marvell SoC pin controller drivers"
- depends on ARCH_MVEBU || ARCH_DOVE
+ depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
select PINMUX
select PINCONF
help
@@ -162,6 +162,13 @@ config PINCTRL_DOVE
Say yes here to support pinctrl driver on Marvell Dove SoCs
(88AP510).
+config PINCTRL_KIRKWOOD
+ bool "Support for Marvell Kirkwood SoCs"
+ depends on PINCTRL_MVEBU
+ help
+ Say yes here to support pinctrl driver on Marvell Kirkwood SoCs
+ (88f6180, 88f6190, 88f6192, 88f6281, 88f6282).
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d1327df..3006294 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-kirkwood.c b/drivers/pinctrl/pinctrl-kirkwood.c
new file mode 100644
index 0000000..ef07f28
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-kirkwood.c
@@ -0,0 +1,460 @@
+/*
+ * Marvell Kirkwood pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V(f6180, f6190, f6192, f6281, f6282) \
+ ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
+ (f6281 << 3) | (f6282 << 4))
+
+#define VARIANT_MV88F6180 V(1, 0, 0, 0, 0)
+#define VARIANT_MV88F6190 V(0, 1, 0, 0, 0)
+#define VARIANT_MV88F6192 V(0, 0, 1, 0, 0)
+#define VARIANT_MV88F6281 V(0, 0, 0, 1, 0)
+#define VARIANT_MV88F6282 V(0, 0, 0, 0, 1)
+
+static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1))),
+ MPP_MODE(1,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1))),
+ MPP_MODE(2,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1))),
+ MPP_MODE(3,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1))),
+ MPP_MODE(4,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0))),
+ MPP_MODE(5,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))),
+ MPP_MODE(6,
+ MPP_VAR_FUNCTION(0x0, "sysrst", "out", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "spi", "mosi", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "ptp", "trig", V(1, 1, 1, 1, 0))),
+ MPP_MODE(7,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))),
+ MPP_MODE(8,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))),
+ MPP_MODE(9,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))),
+ MPP_MODE(10,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0))),
+ MPP_MODE(11,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1))),
+ MPP_MODE(12,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1))),
+ MPP_MODE(13,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))),
+ MPP_MODE(14,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))),
+ MPP_MODE(15,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1))),
+ MPP_MODE(16,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))),
+ MPP_MODE(17,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1))),
+ MPP_MODE(18,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1))),
+ MPP_MODE(19,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1))),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0))),
+ MPP_MODE(21,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1))),
+ MPP_MODE(22,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1))),
+ MPP_MODE(23,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1))),
+ MPP_MODE(24,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1))),
+ MPP_MODE(25,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1))),
+ MPP_MODE(26,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1))),
+ MPP_MODE(27,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1))),
+ MPP_MODE(28,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1))),
+ MPP_MODE(29,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1))),
+ MPP_MODE(30,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1))),
+ MPP_MODE(31,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1))),
+ MPP_MODE(32,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1))),
+ MPP_MODE(33,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1))),
+ MPP_MODE(34,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1))),
+ MPP_MODE(35,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1))),
+ MPP_MODE(36,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1))),
+ MPP_MODE(37,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1))),
+ MPP_MODE(38,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1))),
+ MPP_MODE(39,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1))),
+ MPP_MODE(40,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1))),
+ MPP_MODE(41,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1))),
+ MPP_MODE(42,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1))),
+ MPP_MODE(43,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1))),
+ MPP_MODE(44,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1))),
+ MPP_MODE(45,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1))),
+ MPP_MODE(46,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1))),
+ MPP_MODE(47,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))),
+ MPP_MODE(48,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1))),
+ MPP_MODE(49,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0)),
+ MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1))),
+};
+
+static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
+ MPP_REG_CTRL(0, 29),
+};
+
+static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 30),
+};
+
+static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
+ MPP_REG_CTRL(0, 35),
+};
+
+static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 4),
+};
+
+static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
+ MPP_REG_CTRL(0, 49),
+};
+
+static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 18),
+};
+
+static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
+ { .compatible = "marvell,88f6180-pinctrl",
+ .data = (void *)VARIANT_MV88F6180 },
+ { .compatible = "marvell,88f6190-pinctrl",
+ .data = (void *)VARIANT_MV88F6190 },
+ { .compatible = "marvell,88f6192-pinctrl",
+ .data = (void *)VARIANT_MV88F6192 },
+ { .compatible = "marvell,88f6281-pinctrl",
+ .data = (void *)VARIANT_MV88F6281 },
+ { .compatible = "marvell,88f6282-pinctrl",
+ .data = (void *)VARIANT_MV88F6282 },
+ { }
+};
+
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
+ const struct of_device_id *match =
+ of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+
+ if (match) {
+ soc->variant = (unsigned)match->data & 0xff;
+ switch (soc->variant) {
+ case VARIANT_MV88F6180:
+ soc->controls = mv88f6180_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f6180_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
+ break;
+ case VARIANT_MV88F6190:
+ case VARIANT_MV88F6192:
+ soc->controls = mv88f619x_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f619x_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
+ break;
+ case VARIANT_MV88F6281:
+ case VARIANT_MV88F6282:
+ soc->controls = mv88f628x_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f628x_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
+ break;
+ }
+ pdev->dev.platform_data = soc;
+ }
+ return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit kirkwood_pinctrl_remove(struct platform_device *pdev)
+{
+ return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver kirkwood_pinctrl_driver = {
+ .driver = {
+ .name = "kirkwood-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(kirkwood_pinctrl_of_match),
+ },
+ .probe = kirkwood_pinctrl_probe,
+ .remove = __devexit_p(kirkwood_pinctrl_remove),
+};
+
+module_platform_driver(kirkwood_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <[email protected]>");
+MODULE_DESCRIPTION("Marvell Kirkwood pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
The Armada XP evaluation board is based on the MV78460 Armava XP
SoC. Now that we have separate .dtsi files for the three different
SoCs of the Armada XP family, use the appropriate one as include for
the Armada XP evaluation board .dts file.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/armada-xp-db.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d..b1fc728 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
*/
/dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Evaluation Board";
- compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+ compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../pinctrl/marvell,armada-370-pinctrl.txt | 95 +++++
drivers/pinctrl/Kconfig | 5 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-armada-370.c | 421 ++++++++++++++++++++
4 files changed, 522 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
new file mode 100644
index 0000000..01ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name pins functions
+================================================================================
+mpp0 0 gpio, uart0(rxd)
+mpp1 1 gpo, uart0(txd)
+mpp2 2 gpio, i2c0(sck), uart0(txd)
+mpp3 3 gpio, i2c0(sda), uart0(rxd)
+mpp4 4 gpio, cpu_pd(vdd)
+mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+ sata1(prsnt), spi1(cs1)
+mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+ audio(spdifi)
+mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+ audio(rmclk)
+mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+ spi0(cs2)
+mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+ spi0(cs3)
+mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17 17 gpo, ge(mdc)
+mpp18 18 gpio, ge(mdio)
+mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20 20 gpo, ge0(txd4), ge1(txd0)
+mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
+mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31 31 gpio, tclk, ge0(txerr)
+mpp32 32 gpio, spi0(cs0)
+mpp33 33 gpio, dev(bootcs), spi0(cs0)
+mpp34 34 gpo, dev(wen0), spi0(mosi)
+mpp35 35 gpo, dev(oen), spi0(sck)
+mpp36 36 gpo, dev(a1), spi0(miso)
+mpp37 37 gpo, dev(a0), sata0(prsnt)
+mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39 39 gpo, dev(ad0), audio(spdifo)
+mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41 41 gpio, dev(ad2), uart1(rxd)
+mpp42 42 gpo, dev(ad3), uart1(txd)
+mpp43 43 gpo, dev(ad4), audio(bclk)
+mpp44 44 gpo, dev(ad5), audio(mclk)
+mpp45 45 gpo, dev(ad6), audio(lrclk)
+mpp46 46 gpo, dev(ad7), audio(sdo)
+mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+ spi0(cs1)
+mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+ audio(spdifi)
+mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+ audio(rmclk)
+mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+ pcie(clkreq1)
+mpp54 54 gpo, dev(ad15), tdm(dtx)
+mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+ sata0(prsnt)
+mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+ pcie(clkreq0), spi1(cs1)
+mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+ audio(sdo)
+mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+ uart0(rts)
+mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+ audio(sdi)
+mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+ audio(mclk), uart0(cts)
+mpp63 63 gpo, spi0(sck), tclk
+mpp64 64 gpio, spi0(miso), spi0-1(cs1)
+mpp65 65 gpio, spi0(mosi), spi0-1(cs2)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1f84090..caa97cc 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -169,6 +169,11 @@ config PINCTRL_KIRKWOOD
Say yes here to support pinctrl driver on Marvell Kirkwood SoCs
(88f6180, 88f6190, 88f6192, 88f6281, 88f6282).
+config PINCTRL_ARMADA_370
+ bool "Support for Marvell Armada 370 SoCs"
+ depends on PINCTRL_MVEBU
+ depends on MACH_ARMADA_370_XP
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3006294..e6d6667 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-armada-370.c b/drivers/pinctrl/pinctrl-armada-370.c
new file mode 100644
index 0000000..b48f472
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-370.c
@@ -0,0 +1,421 @@
+/*
+ * Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "uart0", "rxd")),
+ MPP_MODE(1,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "uart0", "txd")),
+ MPP_MODE(2,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "i2c0", "sck"),
+ MPP_FUNCTION(0x2, "uart0", "txd")),
+ MPP_MODE(3,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "i2c0", "sda"),
+ MPP_FUNCTION(0x2, "uart0", "rxd")),
+ MPP_MODE(4,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
+ MPP_MODE(5,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txclko"),
+ MPP_FUNCTION(0x2, "uart1", "txd"),
+ MPP_FUNCTION(0x4, "spi1", "clk"),
+ MPP_FUNCTION(0x5, "audio", "mclk")),
+ MPP_MODE(6,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd0"),
+ MPP_FUNCTION(0x2, "sata0", "prsnt"),
+ MPP_FUNCTION(0x4, "tdm", "rst"),
+ MPP_FUNCTION(0x5, "audio", "sdo")),
+ MPP_MODE(7,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd1"),
+ MPP_FUNCTION(0x4, "tdm", "tdx"),
+ MPP_FUNCTION(0x5, "audio", "lrclk")),
+ MPP_MODE(8,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd2"),
+ MPP_FUNCTION(0x2, "uart0", "rts"),
+ MPP_FUNCTION(0x4, "tdm", "drx"),
+ MPP_FUNCTION(0x5, "audio", "bclk")),
+ MPP_MODE(9,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd3"),
+ MPP_FUNCTION(0x2, "uart1", "txd"),
+ MPP_FUNCTION(0x3, "sd0", "clk"),
+ MPP_FUNCTION(0x5, "audio", "spdifo")),
+ MPP_MODE(10,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txctl"),
+ MPP_FUNCTION(0x2, "uart0", "cts"),
+ MPP_FUNCTION(0x4, "tdm", "fsync"),
+ MPP_FUNCTION(0x5, "audio", "sdi")),
+ MPP_MODE(11,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd0"),
+ MPP_FUNCTION(0x2, "uart1", "rxd"),
+ MPP_FUNCTION(0x3, "sd0", "cmd"),
+ MPP_FUNCTION(0x4, "spi0", "cs1"),
+ MPP_FUNCTION(0x5, "sata1", "prsnt"),
+ MPP_FUNCTION(0x6, "spi1", "cs1")),
+ MPP_MODE(12,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd1"),
+ MPP_FUNCTION(0x2, "i2c1", "sda"),
+ MPP_FUNCTION(0x3, "sd0", "d0"),
+ MPP_FUNCTION(0x4, "spi1", "cs0"),
+ MPP_FUNCTION(0x5, "audio", "spdifi")),
+ MPP_MODE(13,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd2"),
+ MPP_FUNCTION(0x2, "i2c1", "sck"),
+ MPP_FUNCTION(0x3, "sd0", "d1"),
+ MPP_FUNCTION(0x4, "tdm", "pclk"),
+ MPP_FUNCTION(0x5, "audio", "rmclk")),
+ MPP_MODE(14,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd3"),
+ MPP_FUNCTION(0x2, "pcie", "clkreq0"),
+ MPP_FUNCTION(0x3, "sd0", "d2"),
+ MPP_FUNCTION(0x4, "spi1", "mosi"),
+ MPP_FUNCTION(0x5, "spi0", "cs2")),
+ MPP_MODE(15,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxctl"),
+ MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+ MPP_FUNCTION(0x3, "sd0", "d3"),
+ MPP_FUNCTION(0x4, "spi1", "miso"),
+ MPP_FUNCTION(0x5, "spi0", "cs3")),
+ MPP_MODE(16,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxclk"),
+ MPP_FUNCTION(0x2, "uart1", "rxd"),
+ MPP_FUNCTION(0x4, "tdm", "int"),
+ MPP_FUNCTION(0x5, "audio", "extclk")),
+ MPP_MODE(17,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge", "mdc")),
+ MPP_MODE(18,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge", "mdio")),
+ MPP_MODE(19,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txclk"),
+ MPP_FUNCTION(0x2, "ge1", "txclkout"),
+ MPP_FUNCTION(0x4, "tdm", "pclk")),
+ MPP_MODE(20,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd4"),
+ MPP_FUNCTION(0x2, "ge1", "txd0")),
+ MPP_MODE(21,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd5"),
+ MPP_FUNCTION(0x2, "ge1", "txd1"),
+ MPP_FUNCTION(0x4, "uart1", "txd")),
+ MPP_MODE(22,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd6"),
+ MPP_FUNCTION(0x2, "ge1", "txd2"),
+ MPP_FUNCTION(0x4, "uart0", "rts")),
+ MPP_MODE(23,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd7"),
+ MPP_FUNCTION(0x2, "ge1", "txd3"),
+ MPP_FUNCTION(0x4, "spi1", "mosi")),
+ MPP_MODE(24,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "col"),
+ MPP_FUNCTION(0x2, "ge1", "txctl"),
+ MPP_FUNCTION(0x4, "spi1", "cs0")),
+ MPP_MODE(25,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxerr"),
+ MPP_FUNCTION(0x2, "ge1", "rxd0"),
+ MPP_FUNCTION(0x4, "uart1", "rxd")),
+ MPP_MODE(26,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "crs"),
+ MPP_FUNCTION(0x2, "ge1", "rxd1"),
+ MPP_FUNCTION(0x4, "spi1", "miso")),
+ MPP_MODE(27,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd4"),
+ MPP_FUNCTION(0x2, "ge1", "rxd2"),
+ MPP_FUNCTION(0x4, "uart0", "cts")),
+ MPP_MODE(28,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd5"),
+ MPP_FUNCTION(0x2, "ge1", "rxd3")),
+ MPP_MODE(29,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd6"),
+ MPP_FUNCTION(0x2, "ge1", "rxctl"),
+ MPP_FUNCTION(0x4, "i2c1", "sda")),
+ MPP_MODE(30,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd7"),
+ MPP_FUNCTION(0x2, "ge1", "rxclk"),
+ MPP_FUNCTION(0x4, "i2c1", "sck")),
+ MPP_MODE(31,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x3, "tclk", NULL),
+ MPP_FUNCTION(0x4, "ge0", "txerr")),
+ MPP_MODE(32,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "spi0", "cs0")),
+ MPP_MODE(33,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "bootcs"),
+ MPP_FUNCTION(0x2, "spi0", "cs0")),
+ MPP_MODE(34,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "wen0"),
+ MPP_FUNCTION(0x2, "spi0", "mosi")),
+ MPP_MODE(35,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "oen"),
+ MPP_FUNCTION(0x2, "spi0", "sck")),
+ MPP_MODE(36,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "a1"),
+ MPP_FUNCTION(0x2, "spi0", "miso")),
+ MPP_MODE(37,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "a0"),
+ MPP_FUNCTION(0x2, "sata0", "prsnt")),
+ MPP_MODE(38,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ready"),
+ MPP_FUNCTION(0x2, "uart1", "cts"),
+ MPP_FUNCTION(0x3, "uart0", "cts")),
+ MPP_MODE(39,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad0"),
+ MPP_FUNCTION(0x2, "audio", "spdifo")),
+ MPP_MODE(40,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad1"),
+ MPP_FUNCTION(0x2, "uart1", "rts"),
+ MPP_FUNCTION(0x3, "uart0", "rts")),
+ MPP_MODE(41,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad2"),
+ MPP_FUNCTION(0x2, "uart1", "rxd")),
+ MPP_MODE(42,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad3"),
+ MPP_FUNCTION(0x2, "uart1", "txd")),
+ MPP_MODE(43,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad4"),
+ MPP_FUNCTION(0x2, "audio", "bclk")),
+ MPP_MODE(44,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad5"),
+ MPP_FUNCTION(0x2, "audio", "mclk")),
+ MPP_MODE(45,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad6"),
+ MPP_FUNCTION(0x2, "audio", "lrclk")),
+ MPP_MODE(46,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad7"),
+ MPP_FUNCTION(0x2, "audio", "sdo")),
+ MPP_MODE(47,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad8"),
+ MPP_FUNCTION(0x3, "sd0", "clk"),
+ MPP_FUNCTION(0x5, "audio", "spdifo")),
+ MPP_MODE(48,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad9"),
+ MPP_FUNCTION(0x2, "uart0", "rts"),
+ MPP_FUNCTION(0x3, "sd0", "cmd"),
+ MPP_FUNCTION(0x4, "sata1", "prsnt"),
+ MPP_FUNCTION(0x5, "spi0", "cs1")),
+ MPP_MODE(49,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad10"),
+ MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+ MPP_FUNCTION(0x3, "sd0", "d0"),
+ MPP_FUNCTION(0x4, "spi1", "cs0"),
+ MPP_FUNCTION(0x5, "audio", "spdifi")),
+ MPP_MODE(50,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad11"),
+ MPP_FUNCTION(0x2, "uart0", "cts"),
+ MPP_FUNCTION(0x3, "sd0", "d1"),
+ MPP_FUNCTION(0x4, "spi1", "miso"),
+ MPP_FUNCTION(0x5, "audio", "rmclk")),
+ MPP_MODE(51,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad12"),
+ MPP_FUNCTION(0x2, "i2c1", "sda"),
+ MPP_FUNCTION(0x3, "sd0", "d2"),
+ MPP_FUNCTION(0x4, "spi1", "mosi")),
+ MPP_MODE(52,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad13"),
+ MPP_FUNCTION(0x2, "i2c1", "sck"),
+ MPP_FUNCTION(0x3, "sd0", "d3"),
+ MPP_FUNCTION(0x4, "spi1", "sck")),
+ MPP_MODE(53,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad14"),
+ MPP_FUNCTION(0x2, "sd0", "clk"),
+ MPP_FUNCTION(0x3, "tdm", "pclk"),
+ MPP_FUNCTION(0x4, "spi0", "cs2"),
+ MPP_FUNCTION(0x5, "pcie", "clkreq1")),
+ MPP_MODE(54,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad15"),
+ MPP_FUNCTION(0x3, "tdm", "dtx")),
+ MPP_MODE(55,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "cs1"),
+ MPP_FUNCTION(0x2, "uart1", "txd"),
+ MPP_FUNCTION(0x3, "tdm", "rst"),
+ MPP_FUNCTION(0x4, "sata1", "prsnt"),
+ MPP_FUNCTION(0x5, "sata0", "prsnt")),
+ MPP_MODE(56,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "cs2"),
+ MPP_FUNCTION(0x2, "uart1", "cts"),
+ MPP_FUNCTION(0x3, "uart0", "cts"),
+ MPP_FUNCTION(0x4, "spi0", "cs3"),
+ MPP_FUNCTION(0x5, "pcie", "clkreq0"),
+ MPP_FUNCTION(0x6, "spi1", "cs1")),
+ MPP_MODE(57,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "cs3"),
+ MPP_FUNCTION(0x2, "uart1", "rxd"),
+ MPP_FUNCTION(0x3, "tdm", "fsync"),
+ MPP_FUNCTION(0x4, "sata0", "prsnt"),
+ MPP_FUNCTION(0x5, "audio", "sdo")),
+ MPP_MODE(58,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "cs0"),
+ MPP_FUNCTION(0x2, "uart1", "rts"),
+ MPP_FUNCTION(0x3, "tdm", "int"),
+ MPP_FUNCTION(0x5, "audio", "extclk"),
+ MPP_FUNCTION(0x6, "uart0", "rts")),
+ MPP_MODE(59,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ale0"),
+ MPP_FUNCTION(0x2, "uart1", "rts"),
+ MPP_FUNCTION(0x3, "uart0", "rts"),
+ MPP_FUNCTION(0x5, "audio", "bclk")),
+ MPP_MODE(60,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ale1"),
+ MPP_FUNCTION(0x2, "uart1", "rxd"),
+ MPP_FUNCTION(0x3, "sata0", "prsnt"),
+ MPP_FUNCTION(0x4, "pcie", "rst-out"),
+ MPP_FUNCTION(0x5, "audio", "sdi")),
+ MPP_MODE(61,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "wen1"),
+ MPP_FUNCTION(0x2, "uart1", "txd"),
+ MPP_FUNCTION(0x5, "audio", "rclk")),
+ MPP_MODE(62,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "a2"),
+ MPP_FUNCTION(0x2, "uart1", "cts"),
+ MPP_FUNCTION(0x3, "tdm", "drx"),
+ MPP_FUNCTION(0x4, "pcie", "clkreq0"),
+ MPP_FUNCTION(0x5, "audio", "mclk"),
+ MPP_FUNCTION(0x6, "uart0", "cts")),
+ MPP_MODE(63,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "spi0", "sck"),
+ MPP_FUNCTION(0x2, "tclk", NULL)),
+ MPP_MODE(64,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "spi0", "miso"),
+ MPP_FUNCTION(0x2, "spi0-1", "cs1")),
+ MPP_MODE(65,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "spi0", "mosi"),
+ MPP_FUNCTION(0x2, "spi0-1", "cs2")),
+};
+
+static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
+
+static struct of_device_id armada_370_pinctrl_of_match[] __devinitdata = {
+ { .compatible = "marvell,mv88f6710-pinctrl" },
+ { },
+};
+
+static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
+ MPP_REG_CTRL(0, 65),
+};
+
+static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 32),
+ MPP_GPIO_RANGE(2, 64, 64, 2),
+};
+
+static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
+
+ soc->variant = 0;
+ soc->controls = mv88f6710_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
+ soc->modes = mv88f6710_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
+ soc->gpioranges = mv88f6710_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
+
+ pdev->dev.platform_data = soc;
+
+ return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_370_pinctrl_remove(struct platform_device *pdev)
+{
+ return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_370_pinctrl_driver = {
+ .driver = {
+ .name = "armada-370-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(armada_370_pinctrl_of_match),
+ },
+ .probe = armada_370_pinctrl_probe,
+ .remove = __devexit_p(armada_370_pinctrl_remove),
+};
+
+module_platform_driver(armada_370_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <[email protected]>");
+MODULE_DESCRIPTION("Marvell Armada 370 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
Now that we have a proper pinctrl driver for Marvell EBU platforms,
enable PINCTRL support in ARCH_MVEBU.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 361f513..95317a9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -573,6 +573,7 @@ config ARCH_MVEBU
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select COMMON_CLK
+ select PINCTRL
help
Support for the Marvell SoC Family with device tree support
--
1.7.10.4
This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pinctrl/marvell,mvebu-pinctrl.txt | 46 ++
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-mvebu.c | 758 ++++++++++++++++++++
drivers/pinctrl/pinctrl-mvebu.h | 175 +++++
5 files changed, 990 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
create mode 100644 drivers/pinctrl/pinctrl-mvebu.h
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
new file mode 100644
index 0000000..b3e5066
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+ Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing to function to mux to for all
+ marvell,pins given in this pin configuration node. The function has to be
+ common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+ valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial@12100 {
+ compatible = "ns16550a";
+ reg = <0x12100 0x100>;
+ reg-shift = <2>;
+ interrupts = <7>;
+ clock-frequency = <166666667>;
+
+ pinctrl-0 = <&pmx_uart1_sw>;
+};
+
+pinctrl: pinctrl@d0200 {
+ compatible = "marvell,dove-pinctrl";
+ reg = <0xd0200 0x20>;
+
+ pmx_uart1_sw: pmx-uart1-sw {
+ marvell,pins = "mpp_uart1";
+ marvell,function = "uart1";
+ };
+};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..b968335 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -145,6 +145,16 @@ config PINCTRL_COH901
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
ports of 8 GPIO pins each.
+config PINCTRL_MVEBU
+ bool "Marvell SoC pin controller drivers"
+ depends on ARCH_MVEBU
+ select PINMUX
+ select PINCONF
+ help
+ Say yes here to support pinctrl driver on Marvell SoCs.
+ This is only the driver core and additionally needs a SoC specific
+ driver.
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..007ed32 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-mvebu.c b/drivers/pinctrl/pinctrl-mvebu.c
new file mode 100644
index 0000000..09172be
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.c
@@ -0,0 +1,758 @@
+/*
+ * Marvell MVEBU pinctrl core driver
+ *
+ * Authors: Sebastian Hesselbarth <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinctrl-mvebu.h"
+
+struct mvebu_pinctrl_function {
+ unsigned fid;
+ const char *name;
+ const char *setting;
+ const char **groups;
+ unsigned num_groups;
+};
+
+struct mvebu_pinctrl_group {
+ const char *name;
+ struct mvebu_mpp_ctrl *ctrl;
+ struct mvebu_mpp_ctrl_setting *settings;
+ unsigned num_settings;
+ unsigned gid;
+ unsigned *pins;
+ unsigned npins;
+};
+
+struct mvebu_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_desc desc;
+ void __iomem *base;
+ struct mvebu_pinctrl_group *groups;
+ unsigned num_groups;
+ struct mvebu_pinctrl_function *functions;
+ unsigned num_functions;
+ unsigned variant;
+};
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
+ struct mvebu_pinctrl *pctl, unsigned pid)
+{
+ unsigned n;
+ for (n = 0; n < pctl->num_groups; n++) {
+ if (pid >= pctl->groups[n].pins[0] &&
+ pid < pctl->groups[n].pins[0] +
+ pctl->groups[n].npins)
+ return &pctl->groups[n];
+ }
+ return NULL;
+}
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
+ struct mvebu_pinctrl *pctl, const char *name)
+{
+ unsigned n;
+ for (n = 0; n < pctl->num_groups; n++) {
+ if (strcmp(name, pctl->groups[n].name) == 0)
+ return &pctl->groups[n];
+ }
+ return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
+ struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+ unsigned long config)
+{
+ unsigned n;
+ for (n = 0; n < grp->num_settings; n++) {
+ if (config == grp->settings[n].val) {
+ if (!pctl->variant || (pctl->variant &
+ grp->settings[n].variant))
+ return &grp->settings[n];
+ }
+ }
+ return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
+ struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+ const char *name)
+{
+ unsigned n;
+ for (n = 0; n < grp->num_settings; n++) {
+ if (strcmp(name, grp->settings[n].name) == 0) {
+ if (!pctl->variant || (pctl->variant &
+ grp->settings[n].variant))
+ return &grp->settings[n];
+ }
+ }
+ return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
+ struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
+{
+ unsigned n;
+ for (n = 0; n < grp->num_settings; n++) {
+ if (grp->settings[n].flags &
+ (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+ if (!pctl->variant || (pctl->variant &
+ grp->settings[n].variant))
+ return &grp->settings[n];
+ }
+ }
+ return NULL;
+}
+
+struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
+ struct mvebu_pinctrl *pctl, const char *name)
+{
+ unsigned n;
+ for (n = 0; n < pctl->num_functions; n++) {
+ if (strcmp(name, pctl->functions[n].name) == 0)
+ return &pctl->functions[n];
+ }
+ return NULL;
+}
+
+static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
+ struct mvebu_pinctrl_group *grp,
+ unsigned long *config)
+{
+ unsigned pin = grp->gid;
+ unsigned off = (pin / 8) * 4;
+ unsigned shift = (pin % 8) * 4;
+
+ *config = readl(pctl->base + off);
+ *config >>= shift;
+ *config &= 0xf;
+
+ return 0;
+}
+
+static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
+ struct mvebu_pinctrl_group *grp,
+ unsigned long config)
+{
+ unsigned pin = grp->gid;
+ unsigned off = (pin / 8) * 4;
+ unsigned shift = (pin % 8) * 4;
+ unsigned long reg;
+
+ reg = readl(pctl->base + off);
+ reg &= ~(0xf << shift);
+ reg |= (config << shift);
+ writel(reg, pctl->base + off);
+
+ return 0;
+}
+
+static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned gid, unsigned long *config)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+ if (!grp->ctrl)
+ return -EINVAL;
+
+ if (grp->ctrl->mpp_get)
+ return grp->ctrl->mpp_get(grp->ctrl, config);
+
+ return mvebu_common_mpp_get(pctl, grp, config);
+}
+
+static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned gid, unsigned long config)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+ if (!grp->ctrl)
+ return -EINVAL;
+
+ if (grp->ctrl->mpp_set)
+ return grp->ctrl->mpp_set(grp->ctrl, config);
+
+ return mvebu_common_mpp_set(pctl, grp, config);
+}
+
+static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned gid)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+ struct mvebu_mpp_ctrl_setting *curr;
+ unsigned long config;
+ unsigned n;
+
+ if (mvebu_pinconf_group_get(pctldev, gid, &config))
+ return;
+
+ curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
+
+ if (curr) {
+ seq_printf(s, "current: %s", curr->name);
+ if (curr->subname)
+ seq_printf(s, "(%s)", curr->subname);
+ if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+ seq_printf(s, "(");
+ if (curr->flags & MVEBU_SETTING_GPI)
+ seq_printf(s, "i");
+ if (curr->flags & MVEBU_SETTING_GPO)
+ seq_printf(s, "o");
+ seq_printf(s, ")");
+ }
+ } else
+ seq_printf(s, "current: UNKNOWN");
+
+ if (grp->num_settings > 1) {
+ seq_printf(s, ", available = [");
+ for (n = 0; n < grp->num_settings; n++) {
+ if (curr == &grp->settings[n])
+ continue;
+
+ /* skip unsupported settings for this variant */
+ if (pctl->variant &&
+ !(pctl->variant & grp->settings[n].variant))
+ continue;
+
+ seq_printf(s, " %s", grp->settings[n].name);
+ if (grp->settings[n].subname)
+ seq_printf(s, "(%s)", grp->settings[n].subname);
+ if (grp->settings[n].flags &
+ (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+ seq_printf(s, "(");
+ if (grp->settings[n].flags & MVEBU_SETTING_GPI)
+ seq_printf(s, "i");
+ if (grp->settings[n].flags & MVEBU_SETTING_GPO)
+ seq_printf(s, "o");
+ seq_printf(s, ")");
+ }
+ }
+ seq_printf(s, " ]");
+ }
+ return;
+}
+
+struct pinconf_ops mvebu_pinconf_ops = {
+ .pin_config_group_get = mvebu_pinconf_group_get,
+ .pin_config_group_set = mvebu_pinconf_group_set,
+ .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
+};
+
+static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->num_functions;
+}
+
+static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned fid)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->functions[fid].name;
+}
+
+static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctl->functions[fid].groups;
+ *num_groups = pctl->functions[fid].num_groups;
+ return 0;
+}
+
+static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
+ unsigned gid)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_function *func = &pctl->functions[fid];
+ struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+ struct mvebu_mpp_ctrl_setting *setting;
+ int ret;
+
+ setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
+ func->setting);
+ if (!setting) {
+ dev_err(pctl->dev,
+ "unable to find setting %s in group %s\n",
+ func->setting, func->groups[gid]);
+ return -EINVAL;
+ }
+
+ ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+ if (ret) {
+ dev_err(pctl->dev, "cannot set group %s to %s\n",
+ func->groups[gid], func->setting);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp;
+ struct mvebu_mpp_ctrl_setting *setting;
+
+ grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+ if (!grp)
+ return -EINVAL;
+
+ if (grp->ctrl->mpp_gpio_req)
+ return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
+
+ setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+ if (!setting)
+ return -ENOTSUPP;
+
+ return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+}
+
+static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp;
+ struct mvebu_mpp_ctrl_setting *setting;
+
+ grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+ if (!grp)
+ return -EINVAL;
+
+ if (grp->ctrl->mpp_gpio_dir)
+ return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
+
+ setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+ if (!setting)
+ return -ENOTSUPP;
+
+ if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
+ (!input && (setting->flags & MVEBU_SETTING_GPO)))
+ return 0;
+
+ return -ENOTSUPP;
+}
+
+static struct pinmux_ops mvebu_pinmux_ops = {
+ .get_functions_count = mvebu_pinmux_get_funcs_count,
+ .get_function_name = mvebu_pinmux_get_func_name,
+ .get_function_groups = mvebu_pinmux_get_groups,
+ .gpio_request_enable = mvebu_pinmux_gpio_request_enable,
+ .gpio_set_direction = mvebu_pinmux_gpio_set_direction,
+ .enable = mvebu_pinmux_enable,
+};
+
+static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ return pctl->num_groups;
+}
+
+static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned gid)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ return pctl->groups[gid].name;
+}
+
+static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned gid, const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ *pins = pctl->groups[gid].pins;
+ *num_pins = pctl->groups[gid].npins;
+ return 0;
+}
+
+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned *num_maps)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct property *prop;
+ const char *function;
+ const char *group;
+ int ret, nmaps, n;
+
+ *map = NULL;
+ *num_maps = 0;
+
+ ret = of_property_read_string(np, "marvell,function", &function);
+ if (ret) {
+ dev_err(pctl->dev,
+ "missing marvell,function in node %s\n", np->name);
+ return 0;
+ }
+
+ nmaps = of_property_count_strings(np, "marvell,pins");
+ if (nmaps < 0) {
+ dev_err(pctl->dev,
+ "missing marvell,pins in node %s\n", np->name);
+ return 0;
+ }
+
+ *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
+ if (map == NULL) {
+ dev_err(pctl->dev,
+ "cannot allocate pinctrl_map memory for %s\n",
+ np->name);
+ return -ENOMEM;
+ }
+
+ n = 0;
+ of_property_for_each_string(np, "marvell,pins", prop, group) {
+ struct mvebu_pinctrl_group *grp =
+ mvebu_pinctrl_find_group_by_name(pctl, group);
+
+ if (!grp) {
+ dev_err(pctl->dev, "unknown pin %s", group);
+ continue;
+ }
+
+ if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+ dev_err(pctl->dev, "unsupported function %s on pin %s",
+ function, group);
+ continue;
+ }
+
+ (*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)[n].data.mux.group = group;
+ (*map)[n].data.mux.function = np->name;
+ n++;
+ }
+
+ *num_maps = nmaps;
+
+ return 0;
+}
+
+static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ kfree(map);
+}
+
+static struct pinctrl_ops mvebu_pinctrl_ops = {
+ .get_groups_count = mvebu_pinctrl_get_groups_count,
+ .get_group_name = mvebu_pinctrl_get_group_name,
+ .get_group_pins = mvebu_pinctrl_get_group_pins,
+ .dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
+ .dt_free_map = mvebu_pinctrl_dt_free_map,
+};
+
+static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,
+ struct device_node *np, unsigned idx)
+{
+ struct mvebu_pinctrl_function *func = &pctl->functions[idx];
+ struct property *prop;
+ const char *setting;
+ const char *group;
+ unsigned n = 0;
+ int ret, num_groups;
+
+ ret = of_property_read_string(np, "marvell,function", &setting);
+ if (ret) {
+ dev_err(pctl->dev,
+ "missing marvell,function in node %s\n", np->name);
+ return -EINVAL;
+ }
+
+ num_groups = of_property_count_strings(np, "marvell,pins");
+ if (num_groups <= 0) {
+ dev_err(pctl->dev,
+ "missing marvell,pins in node %s\n", np->name);
+ return -EINVAL;
+ }
+
+ func->fid = idx;
+ func->name = np->name;
+ func->setting = setting;
+ func->num_groups = num_groups;
+ func->groups = devm_kzalloc(pctl->dev, num_groups * sizeof(char *),
+ GFP_KERNEL);
+ if (!func->groups) {
+ dev_err(pctl->dev,
+ "unable to alloc function groups\n");
+ return -ENOMEM;
+ }
+
+ of_property_for_each_string(np, "marvell,pins", prop, group) {
+ struct mvebu_pinctrl_group *grp =
+ mvebu_pinctrl_find_group_by_name(pctl, group);
+
+ if (!grp) {
+ dev_err(pctl->dev, "unknown pin %s", group);
+ return -EINVAL;
+ }
+
+ if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, setting)) {
+ dev_err(pctl->dev, "unsupported function %s on pin %s",
+ setting, group);
+ return -EINVAL;
+ }
+
+ func->groups[n++] = group;
+ }
+ return 0;
+}
+
+static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
+ struct mvebu_pinctrl *pctl)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct device_node *np;
+ unsigned nfuncs = 0, n = 0;
+ int ret;
+
+ if (!node)
+ return -ENODEV;
+
+ nfuncs = of_get_child_count(node);
+ if (nfuncs <= 0) {
+ dev_warn(pctl->dev, "no function defined in device node\n");
+ return 0;
+ }
+
+ pctl->num_functions = nfuncs;
+ pctl->functions = devm_kzalloc(&pdev->dev, nfuncs *
+ sizeof(struct mvebu_pinctrl_function),
+ GFP_KERNEL);
+ if (!pctl->functions) {
+ dev_err(pctl->dev, "unable to alloc functions\n");
+ return -ENOMEM;
+ }
+
+ for_each_child_of_node(node, np) {
+ ret = mvebu_pinctrl_dt_parse_function(pctl, np, n++);
+ if (ret) {
+ dev_warn(pctl->dev, "failed to parse function %s\n",
+ np->name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+int __devinit mvebu_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
+ struct mvebu_pinctrl *pctl;
+ struct resource *res;
+ void __iomem *iomem;
+ struct pinctrl_pin_desc *pdesc;
+ unsigned gid, n, k;
+ int ret;
+
+ if (!soc || !soc->controls || !soc->modes) {
+ dev_err(&pdev->dev, "wrong pinctrl soc info\n");
+ return -EINVAL;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "unable to get resource\n");
+ return -ENODEV;
+ }
+
+ iomem = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!iomem) {
+ dev_err(&pdev->dev, "unable to ioremap\n");
+ return -ENODEV;
+ }
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
+ GFP_KERNEL);
+ if (!pctl) {
+ dev_err(&pdev->dev, "unable to alloc driver\n");
+ return -ENOMEM;
+ }
+
+ pctl->desc.name = dev_name(&pdev->dev);
+ pctl->desc.owner = THIS_MODULE;
+ pctl->desc.pctlops = &mvebu_pinctrl_ops;
+ pctl->desc.pmxops = &mvebu_pinmux_ops;
+ pctl->desc.confops = &mvebu_pinconf_ops;
+ pctl->variant = soc->variant;
+ pctl->base = iomem;
+ pctl->dev = &pdev->dev;
+ platform_set_drvdata(pdev, pctl);
+
+ /* count controls and create names for mvebu generic
+ register controls; also does sanity checks */
+ pctl->num_groups = 0;
+ pctl->desc.npins = 0;
+ for (n = 0; n < soc->ncontrols; n++) {
+ struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+ char *names;
+
+ pctl->desc.npins += ctrl->npins;
+ /* initial control pins */
+ for (k = 0; k < ctrl->npins; k++)
+ ctrl->pins[k] = ctrl->pid + k;
+
+ /* special soc specific control */
+ if (ctrl->mpp_get || ctrl->mpp_set) {
+ if (!ctrl->name || !ctrl->mpp_set || !ctrl->mpp_set) {
+ dev_err(&pdev->dev, "wrong soc control info\n");
+ return -EINVAL;
+ }
+ pctl->num_groups += 1;
+ continue;
+ }
+
+ /* generic mvebu register control */
+ names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
+ if (!names) {
+ dev_err(&pdev->dev, "failed to alloc mpp names\n");
+ return -ENOMEM;
+ }
+ for (k = 0; k < ctrl->npins; k++)
+ sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
+ ctrl->name = names;
+ pctl->num_groups += ctrl->npins;
+ }
+
+ pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
+ sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
+ if (!pdesc) {
+ dev_err(&pdev->dev, "failed to alloc pinctrl pins\n");
+ return -ENOMEM;
+ }
+
+ for (n = 0; n < pctl->desc.npins; n++)
+ pdesc[n].number = n;
+ pctl->desc.pins = pdesc;
+
+ pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
+ sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
+ if (!pctl->groups) {
+ dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
+ return -ENOMEM;
+ }
+
+ /* assign mpp controls to groups */
+ gid = 0;
+ for (n = 0; n < soc->ncontrols; n++) {
+ struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+ pctl->groups[gid].gid = gid;
+ pctl->groups[gid].ctrl = ctrl;
+ pctl->groups[gid].name = ctrl->name;
+ pctl->groups[gid].pins = ctrl->pins;
+ pctl->groups[gid].npins = ctrl->npins;
+
+ /* generic mvebu register control maps to a number of groups */
+ if (!ctrl->mpp_get && !ctrl->mpp_set) {
+ pctl->groups[gid].npins = 1;
+
+ for (k = 1; k < ctrl->npins; k++) {
+ gid++;
+ pctl->groups[gid].gid = gid;
+ pctl->groups[gid].ctrl = ctrl;
+ pctl->groups[gid].name = &ctrl->name[8*k];
+ pctl->groups[gid].pins = &ctrl->pins[k];
+ pctl->groups[gid].npins = 1;
+ }
+ }
+ gid++;
+ }
+
+ /* assign mpp modes to groups */
+ for (n = 0; n < soc->nmodes; n++) {
+ struct mvebu_mpp_mode *mode = &soc->modes[n];
+ struct mvebu_pinctrl_group *grp =
+ mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
+ unsigned num_settings;
+
+ if (!grp) {
+ dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
+ mode->pid);
+ continue;
+ }
+
+ for (num_settings = 0; ;) {
+ struct mvebu_mpp_ctrl_setting *set =
+ &mode->settings[num_settings];
+
+ if (!set->name)
+ break;
+ num_settings++;
+
+ /* skip unsupported settings for this variant */
+ if (pctl->variant && !(pctl->variant & set->variant))
+ continue;
+
+ /* find gpio/gpo/gpi settings */
+ if (strcmp(set->name, "gpio") == 0)
+ set->flags = MVEBU_SETTING_GPI |
+ MVEBU_SETTING_GPO;
+ else if (strcmp(set->name, "gpo") == 0)
+ set->flags = MVEBU_SETTING_GPO;
+ else if (strcmp(set->name, "gpi") == 0)
+ set->flags = MVEBU_SETTING_GPI;
+ }
+
+ grp->settings = mode->settings;
+ grp->num_settings = num_settings;
+ }
+
+ ret = mvebu_pinctrl_dt_parse(pdev, pctl);
+ if (ret) {
+ /* look for pinmux functions in platform_device data */
+ dev_err(&pdev->dev, "unable to parse device tree\n");
+ return ret;
+ }
+
+ pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
+ if (!pctl->pctldev) {
+ dev_err(&pdev->dev, "unable to register pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ dev_info(&pdev->dev, "registered pinctrl driver\n");
+
+ /* register gpio ranges */
+ for (n = 0; n < soc->ngpioranges; n++)
+ pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
+
+ return 0;
+}
+
+int __devexit mvebu_pinctrl_remove(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl *pctl = platform_get_drvdata(pdev);
+ pinctrl_unregister(pctl->pctldev);
+ return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-mvebu.h b/drivers/pinctrl/pinctrl-mvebu.h
new file mode 100644
index 0000000..ee8057a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.h
@@ -0,0 +1,175 @@
+/*
+ * Marvell MVEBU pinctrl driver
+ *
+ * Authors: Sebastian Hesselbarth <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_MVEBU_H__
+#define __PINCTRL_MVEBU_H__
+
+/*
+ * struct mvebu_mpp_ctrl - describe a mpp control
+ * @name: name of the control group
+ * @pid: first pin id handled by this control
+ * @npins: number of pins controlled by this control
+ * @mpp_get: (optional) special function to get mpp setting
+ * @mpp_set: (optional) special function to set mpp setting
+ * @mpp_gpio_req: (optional) special function to request gpio
+ * @mpp_gpio_dir: (optional) special function to set gpio direction
+ *
+ * if optional mpp_get/_set functions are set these
+ * are used to get/set a specific mode. Otherwise it is
+ * assumed that the mpp control is based on 4-bit groups
+ * in subsequent registers.
+ *
+ * mpp_gpio_req/_dir functions can be used to allow pin settings
+ * with varying gpio pins.
+ */
+struct mvebu_mpp_ctrl {
+ const char *name;
+ u8 pid;
+ u8 npins;
+ unsigned *pins;
+ int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
+ int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
+ int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
+ int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
+};
+
+/*
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
+ * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
+ * @subname: (optional) additional ctrl setting name, e.g. rts, cts
+ * @variant: (optional) variant identifier mask
+ * @flags: (private) flags to store gpi/gpo/gpio capabilities
+ *
+ * ctrl setting name will be used to switch to this setting in
+ * DT description, e.g. marvell,function = "uart2". subname
+ * is only for debugging purposes.
+ * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
+ * parsed during initialization.
+ */
+struct mvebu_mpp_ctrl_setting {
+ u8 val;
+ const char *name;
+ const char *subname;
+ u8 variant;
+ u8 flags;
+#define MVEBU_SETTING_GPO (1 << 0)
+#define MVEBU_SETTING_GPI (1 << 1)
+};
+
+/*
+ * struct mvebu_mpp_mode - link ctrl and settings
+ * @pid: first pin id handled by this mode
+ * @settings: list of settings available for this mode
+ */
+struct mvebu_mpp_mode {
+ u8 pid;
+ struct mvebu_mpp_ctrl_setting *settings;
+};
+
+/*
+ * struct mvebu_pinctrl_soc_info -
+ * SoC specific info passed to pinctrl-mvebu
+ * @variant: variant mask of soc_info
+ * @controls: list of available mvebu_mpp_ctrls
+ * @ncontrols: number of available mvebu_mpp_ctrls
+ * @modes: list of available mvebu_mpp_modes
+ * @nmodes: number of available mvebu_mpp_modes
+ * @gpioranges: list of pinctrl_gpio_ranges
+ * @ngpioranges: number of available pinctrl_gpio_ranges
+ */
+struct mvebu_pinctrl_soc_info {
+ u8 variant;
+ struct mvebu_mpp_ctrl *controls;
+ int ncontrols;
+ struct mvebu_mpp_mode *modes;
+ int nmodes;
+ struct pinctrl_gpio_range *gpioranges;
+ int ngpioranges;
+};
+
+#define MPP_REG_CTRL(_idl, _idh) \
+ { \
+ .name = NULL, \
+ .pid = _idl, \
+ .npins = _idh - _idl + 1, \
+ .pins = (unsigned[_idh - _idl + 1]) { }, \
+ .mpp_get = NULL, \
+ .mpp_set = NULL, \
+ .mpp_gpio_req = NULL, \
+ .mpp_gpio_dir = NULL, \
+ }
+
+#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \
+ { \
+ .name = _name, \
+ .pid = _idl, \
+ .npins = _idh - _idl + 1, \
+ .pins = (unsigned[_idh - _idl + 1]) { }, \
+ .mpp_get = _func ## _get, \
+ .mpp_set = _func ## _set, \
+ .mpp_gpio_req = NULL, \
+ .mpp_gpio_dir = NULL, \
+ }
+
+#define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \
+ { \
+ .name = _name, \
+ .pid = _idl, \
+ .npins = _idh - _idl + 1, \
+ .pins = (unsigned[_idh - _idl + 1]) { }, \
+ .mpp_get = _func ## _get, \
+ .mpp_set = _func ## _set, \
+ .mpp_gpio_req = _func ## _gpio_req, \
+ .mpp_gpio_dir = _func ## _gpio_dir, \
+ }
+
+#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
+ { \
+ .val = _val, \
+ .name = _name, \
+ .subname = _subname, \
+ .variant = _mask, \
+ .flags = 0, \
+ }
+
+#if defined(CONFIG_DEBUG_FS)
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
+ _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
+#else
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
+ _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
+#endif
+
+#define MPP_FUNCTION(_val, _name, _subname) \
+ MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
+
+#define MPP_MODE(_id, ...) \
+ { \
+ .pid = _id, \
+ .settings = (struct mvebu_mpp_ctrl_setting[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
+ { \
+ .name = "mvebu-gpio", \
+ .id = _id, \
+ .pin_base = _pinbase, \
+ .base = _gpiobase, \
+ .npins = _npins, \
+ }
+
+int mvebu_pinctrl_probe(struct platform_device *pdev);
+int mvebu_pinctrl_remove(struct platform_device *pdev);
+
+#endif
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada 370 SoC.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/armada-370.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..875fcd8 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -31,5 +31,9 @@
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x100>;
};
+
+ pinctrl@d0018000 {
+ compatible = "marvell,mv88f6710-pinctrl";
+ };
};
};
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada XP SoCs.
Until now, the device tree representation considered the Armada XP as
a single SoC. But in fact, there are three different SoCs in the
Armada XP families, with different number of CPU cores, different
number of Ethernet interfaces... and different number of muxable pins
or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
the three SoCs of the Armada XP family. The current armada-xp-db.dts
evaluation board uses the MV78460 variant of the SoC.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 27 +++++++++++++++++++++++++++
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 27 +++++++++++++++++++++++++++
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 27 +++++++++++++++++++++++++++
3 files changed, 81 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 0000000..69ad287
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP family SoC";
+ compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ soc {
+ pinctrl@d0018000 {
+ compatible = "marvell,mv78230-pinctrl";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 0000000..0f38fa9
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP family SoC";
+ compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ soc {
+ pinctrl@d0018000 {
+ compatible = "marvell,mv78260-pinctrl";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 0000000..9e61836
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP family SoC";
+ compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ soc {
+ pinctrl@d0018000 {
+ compatible = "marvell,mv78460-pinctrl";
+ };
+ };
+ };
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 100 +++++
drivers/pinctrl/Kconfig | 5 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-armada-xp.c | 466 ++++++++++++++++++++
4 files changed, 572 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
new file mode 100644
index 0000000..bfa0a2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+ "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name pins functions
+================================================================================
+mpp0 0 gpio, ge0(txclko), lcd(d0)
+mpp1 1 gpio, ge0(txd0), lcd(d1)
+mpp2 2 gpio, ge0(txd1), lcd(d2)
+mpp3 3 gpio, ge0(txd2), lcd(d3)
+mpp4 4 gpio, ge0(txd3), lcd(d4)
+mpp5 5 gpio, ge0(txctl), lcd(d5)
+mpp6 6 gpio, ge0(rxd0), lcd(d6)
+mpp7 7 gpio, ge0(rxd1), lcd(d7)
+mpp8 8 gpio, ge0(rxd2), lcd(d8)
+mpp9 9 gpio, ge0(rxd3), lcd(d9)
+mpp10 10 gpio, ge0(rxctl), lcd(d10)
+mpp11 11 gpio, ge0(rxclk), lcd(d11)
+mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30 30 gpio, tdm(int1), sd0(clk)
+mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36 36 gpio, spi(mosi)
+mpp37 37 gpio, spi(miso)
+mpp38 38 gpio, spi(sck)
+mpp39 39 gpio, spi(cs0)
+mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+ pcie(clkreq0)
+mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+ pcie(clkreq1)
+mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+ vdd(cpu0-pd)
+mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+ vdd(cpu2-3-pd){1}
+mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+ mem(bat)
+mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+ ref(clkout)
+mpp48 48 gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name pins functions
+================================================================================
+mpp49 49 gpio, dev(we3)
+mpp50 50 gpio, dev(we2)
+mpp51 51 gpio, dev(ad16)
+mpp52 52 gpio, dev(ad17)
+mpp53 53 gpio, dev(ad18)
+mpp54 54 gpio, dev(ad19)
+mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
+mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
+mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58 58 gpio, dev(ad23)
+mpp59 59 gpio, dev(ad24)
+mpp60 60 gpio, dev(ad25)
+mpp61 61 gpio, dev(ad26)
+mpp62 62 gpio, dev(ad27)
+mpp63 63 gpio, dev(ad28)
+mpp64 64 gpio, dev(ad29)
+mpp65 65 gpio, dev(ad30)
+mpp66 66 gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index caa97cc..5502539 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -174,6 +174,11 @@ config PINCTRL_ARMADA_370
depends on PINCTRL_MVEBU
depends on MACH_ARMADA_370_XP
+config PINCTRL_ARMADA_XP
+ bool "Support for Marvell Armada XP SoCs"
+ depends on PINCTRL_MVEBU
+ depends on MACH_ARMADA_370_XP
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e6d6667..f2ea050 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-armada-xp.c b/drivers/pinctrl/pinctrl-armada-xp.c
new file mode 100644
index 0000000..21befef
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-xp.c
@@ -0,0 +1,466 @@
+/*
+ * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file supports the three variants of Armada XP SoCs that are
+ * available: mv78230, mv78260 and mv78460. From a pin muxing
+ * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
+ * both have 67 MPP pins (more GPIOs and address lines for the memory
+ * bus mainly). The only difference between the mv78260 and the
+ * mv78460 in terms of pin muxing is the addition of two functions on
+ * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
+ * cores, mv78460 has four cores).
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V_MV78230 (1 << 0)
+#define V_MV78260 (1 << 1)
+#define V_MV78460 (1 << 2)
+
+#define V_MV78230_PLUS (V_MV78230 | V_MV78260 | V_MV78460)
+#define V_MV78260_PLUS (V_MV78260 | V_MV78460)
+
+static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txclko", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
+ MPP_MODE(1,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
+ MPP_MODE(2,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)),
+ MPP_MODE(3,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)),
+ MPP_MODE(4,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)),
+ MPP_MODE(5,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txctl", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)),
+ MPP_MODE(6,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)),
+ MPP_MODE(7,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)),
+ MPP_MODE(8,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)),
+ MPP_MODE(9,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)),
+ MPP_MODE(10,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxctl", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d10", V_MV78230_PLUS)),
+ MPP_MODE(11,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxclk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d11", V_MV78230_PLUS)),
+ MPP_MODE(12,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "clkout", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)),
+ MPP_MODE(13,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)),
+ MPP_MODE(14,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)),
+ MPP_MODE(15,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd7", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txd2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d15", V_MV78230_PLUS)),
+ MPP_MODE(16,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)),
+ MPP_MODE(17,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)),
+ MPP_MODE(18,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxerr", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxd0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "ptp", "trig", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d18", V_MV78230_PLUS)),
+ MPP_MODE(19,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "crs", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxd1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "ptp", "evreq", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d19", V_MV78230_PLUS)),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd4", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxd2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "ptp", "clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d20", V_MV78230_PLUS)),
+ MPP_MODE(21,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "mem", "bat", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)),
+ MPP_MODE(22,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd6", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxctl", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "sata0", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d22", V_MV78230_PLUS)),
+ MPP_MODE(23,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd7", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d23", V_MV78230_PLUS)),
+ MPP_MODE(24,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)),
+ MPP_MODE(25,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)),
+ MPP_MODE(26,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
+ MPP_MODE(27,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "dtx", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "e", V_MV78230_PLUS)),
+ MPP_MODE(28,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ptp", "evreq", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "drx", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "pwm", V_MV78230_PLUS)),
+ MPP_MODE(29,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
+ MPP_MODE(30,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int1", V_MV78230_PLUS)),
+ MPP_MODE(31,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
+ MPP_MODE(32,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
+ MPP_MODE(33,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS)),
+ MPP_MODE(34,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS)),
+ MPP_MODE(35,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sata1", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)),
+ MPP_MODE(36,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "mosi", V_MV78230_PLUS)),
+ MPP_MODE(37,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "miso", V_MV78230_PLUS)),
+ MPP_MODE(38,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "sck", V_MV78230_PLUS)),
+ MPP_MODE(39,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "cs0", V_MV78230_PLUS)),
+ MPP_MODE(40,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)),
+ MPP_MODE(41,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)),
+ MPP_MODE(42,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
+ MPP_MODE(43,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)),
+ MPP_MODE(44,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)),
+ MPP_MODE(45,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs5", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)),
+ MPP_MODE(46,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs6", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)),
+ MPP_MODE(47,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs7", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)),
+ MPP_MODE(48,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)),
+ MPP_MODE(49,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)),
+ MPP_MODE(50,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "we2", V_MV78260_PLUS)),
+ MPP_MODE(51,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad16", V_MV78260_PLUS)),
+ MPP_MODE(52,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad17", V_MV78260_PLUS)),
+ MPP_MODE(53,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad18", V_MV78260_PLUS)),
+ MPP_MODE(54,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),
+ MPP_MODE(55,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)),
+ MPP_MODE(56,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)),
+ MPP_MODE(57,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)),
+ MPP_MODE(58,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),
+ MPP_MODE(59,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad24", V_MV78260_PLUS)),
+ MPP_MODE(60,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad25", V_MV78260_PLUS)),
+ MPP_MODE(61,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad26", V_MV78260_PLUS)),
+ MPP_MODE(62,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad27", V_MV78260_PLUS)),
+ MPP_MODE(63,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad28", V_MV78260_PLUS)),
+ MPP_MODE(64,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad29", V_MV78260_PLUS)),
+ MPP_MODE(65,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad30", V_MV78260_PLUS)),
+ MPP_MODE(66,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)),
+};
+
+static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
+
+static struct of_device_id armada_xp_pinctrl_of_match[] __devinitdata = {
+ {
+ .compatible = "marvell,mv78230-pinctrl",
+ .data = (void *) V_MV78230,
+ },
+ {
+ .compatible = "marvell,mv78260-pinctrl",
+ .data = (void *) V_MV78260,
+ },
+ {
+ .compatible = "marvell,mv78460-pinctrl",
+ .data = (void *) V_MV78460,
+ },
+ { },
+};
+
+static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
+ MPP_REG_CTRL(0, 48),
+};
+
+static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 17),
+};
+
+static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
+ MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 32),
+ MPP_GPIO_RANGE(2, 64, 64, 3),
+};
+
+static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
+ MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 32),
+ MPP_GPIO_RANGE(2, 64, 64, 3),
+};
+
+static int __devinit armada_xp_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
+ const struct of_device_id *match =
+ of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
+
+ if (!match)
+ return -ENODEV;
+
+ soc->variant = (unsigned) match->data & 0xff;
+
+ switch (soc->variant) {
+ case V_MV78230:
+ soc->controls = mv78230_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
+ soc->modes = armada_xp_mpp_modes;
+ /* We don't necessarily want the full list of the
+ * armada_xp_mpp_modes, but only the first 'n' ones
+ * that are available on this SoC */
+ soc->nmodes = mv78230_mpp_controls[0].npins;
+ soc->gpioranges = mv78230_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
+ break;
+ case V_MV78260:
+ soc->controls = mv78260_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
+ soc->modes = armada_xp_mpp_modes;
+ /* We don't necessarily want the full list of the
+ * armada_xp_mpp_modes, but only the first 'n' ones
+ * that are available on this SoC */
+ soc->nmodes = mv78260_mpp_controls[0].npins;
+ soc->gpioranges = mv78260_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
+ break;
+ case V_MV78460:
+ soc->controls = mv78460_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
+ soc->modes = armada_xp_mpp_modes;
+ /* We don't necessarily want the full list of the
+ * armada_xp_mpp_modes, but only the first 'n' ones
+ * that are available on this SoC */
+ soc->nmodes = mv78460_mpp_controls[0].npins;
+ soc->gpioranges = mv78460_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
+ break;
+ }
+
+ pdev->dev.platform_data = soc;
+
+ return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_xp_pinctrl_remove(struct platform_device *pdev)
+{
+ return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_xp_pinctrl_driver = {
+ .driver = {
+ .name = "armada-xp-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(armada_xp_pinctrl_of_match),
+ },
+ .probe = armada_xp_pinctrl_probe,
+ .remove = __devexit_p(armada_xp_pinctrl_remove),
+};
+
+module_platform_driver(armada_xp_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <[email protected]>");
+MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
The Armada 370 and XP SoCs have configurable muxing for a certain
number of their pins, controlled through a pinctrl driver.
The 'compatible' property is defined in the SoC-specific .dtsi files,
since the compatible string identifies the number of pins and other
SoC-specific properties.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/armada-370-xp.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932..7c72a70 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,13 @@
reg = <0xd0020300 0x30>;
interrupts = <37>, <38>, <39>, <40>;
};
+
+ pinctrl@d0018000 {
+ reg = <0xd0018000 0x38>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
};
};
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
Signed-off-by: Thomas Petazzoni <[email protected]>
---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/configs/mvebu_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2e86b31..cb07e64 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_PINCTRL_ARMADA_370=y
+CONFIG_PINCTRL_ARMADA_XP=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
--
1.7.10.4
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and
> SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood.
> The SoC specific stubs use the pinctrl-mvebu core driver that handles
> pinctrl API and register accesses for common pinctrl registers.
Nice! I'll now go in and review it.
Please add Stephen Warren <[email protected]> on CC for
subsequent iterations.
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> This patch adds a pinctrl driver core for Marvell SoCs plus DT
> binding documentation. This core driver will be used by SoC family
> specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Thanks for dealing with this, much appreaciated!
Are you taking this patch series through some Marvell tree or do you want
me to carry it in the pinctrl tree?
(...)
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
> @@ -0,0 +1,46 @@
> +* Marvell SoC pinctrl core driver for mpp
> +
> +The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
> +(mpp) to a specific function. For each SoC family there is a SoC specific
> +driver using this core driver.
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +A Marvell SoC pin configuration node is a node of a group of pins which can
> +be used for a specific device or function. Each node requires one or more
> +mpp pins or group of pins and a mpp function common to all pins.
> +
> +Required properties for pinctrl driver:
> +- compatible: "marvell,<soc>-pinctrl"
> + Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
> +
> +Required properties for pin configuration node:
> +- marvell,pins: string array of mpp pins or group of pins to be muxed.
> +- marvell,function: string representing to function to mux to for all
> + marvell,pins given in this pin configuration node. The function has to be
> + common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
> + valid pin/pin group names and available function names for each SoC.
> +
> +Examples:
> +
> +uart1: serial@12100 {
> + compatible = "ns16550a";
> + reg = <0x12100 0x100>;
> + reg-shift = <2>;
> + interrupts = <7>;
> + clock-frequency = <166666667>;
It's got nothing to do with this patch, but getting a clock frequency
out of the DT instead of getting it from the clk_get_rate(clk) and
the clock tree seems absurd... (But maybe this platform does not
even have a clk implementation?)
> +
> + pinctrl-0 = <&pmx_uart1_sw>;
> +};
> +
> +pinctrl: pinctrl@d0200 {
> + compatible = "marvell,dove-pinctrl";
> + reg = <0xd0200 0x20>;
> +
> + pmx_uart1_sw: pmx-uart1-sw {
> + marvell,pins = "mpp_uart1";
> + marvell,function = "uart1";
> + };
> +};
This looks very good.
(...)
> +#include <linux/pinctrl/consumer.h>
Why are you including this header?
(There are valid reasons, state them in a comment,
e.g. /* to access pinctrl_gpio* in GPIO portions */)
> +struct mvebu_pinctrl_function {
> + unsigned fid;
> + const char *name;
> + const char *setting;
> + const char **groups;
> + unsigned num_groups;
> +};
> +
> +struct mvebu_pinctrl_group {
> + const char *name;
> + struct mvebu_mpp_ctrl *ctrl;
> + struct mvebu_mpp_ctrl_setting *settings;
> + unsigned num_settings;
> + unsigned gid;
> + unsigned *pins;
> + unsigned npins;
> +};
> +
> +struct mvebu_pinctrl {
> + struct device *dev;
> + struct pinctrl_dev *pctldev;
> + struct pinctrl_desc desc;
> + void __iomem *base;
> + struct mvebu_pinctrl_group *groups;
> + unsigned num_groups;
> + struct mvebu_pinctrl_function *functions;
> + unsigned num_functions;
> + unsigned variant;
> +};
There is some other "variant" field elsewhere that is
a u8, is this correct? In this and the other case, should
this "variant" rather be an enum?
> +struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
> + struct mvebu_pinctrl *pctl, unsigned pid)
> +{
> + unsigned n;
> + for (n = 0; n < pctl->num_groups; n++) {
> + if (pid >= pctl->groups[n].pins[0] &&
> + pid < pctl->groups[n].pins[0] +
> + pctl->groups[n].npins)
> + return &pctl->groups[n];
> + }
> + return NULL;
> +}
> +
> +struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
> + struct mvebu_pinctrl *pctl, const char *name)
> +{
> + unsigned n;
> + for (n = 0; n < pctl->num_groups; n++) {
> + if (strcmp(name, pctl->groups[n].name) == 0)
> + return &pctl->groups[n];
> + }
> + return NULL;
> +}
> +
> +struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
> + struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
> + unsigned long config)
> +{
> + unsigned n;
> + for (n = 0; n < grp->num_settings; n++) {
> + if (config == grp->settings[n].val) {
> + if (!pctl->variant || (pctl->variant &
> + grp->settings[n].variant))
> + return &grp->settings[n];
> + }
> + }
> + return NULL;
> +}
> +
> +struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
> + struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
> + const char *name)
> +{
> + unsigned n;
> + for (n = 0; n < grp->num_settings; n++) {
> + if (strcmp(name, grp->settings[n].name) == 0) {
> + if (!pctl->variant || (pctl->variant &
> + grp->settings[n].variant))
> + return &grp->settings[n];
> + }
> + }
> + return NULL;
> +}
> +
> +struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
> + struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
> +{
> + unsigned n;
> + for (n = 0; n < grp->num_settings; n++) {
> + if (grp->settings[n].flags &
> + (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
> + if (!pctl->variant || (pctl->variant &
> + grp->settings[n].variant))
> + return &grp->settings[n];
> + }
> + }
> + return NULL;
> +}
> +
> +struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
> + struct mvebu_pinctrl *pctl, const char *name)
> +{
> + unsigned n;
> + for (n = 0; n < pctl->num_functions; n++) {
> + if (strcmp(name, pctl->functions[n].name) == 0)
> + return &pctl->functions[n];
> + }
> + return NULL;
> +}
> +
> +static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
> + struct mvebu_pinctrl_group *grp,
> + unsigned long *config)
> +{
> + unsigned pin = grp->gid;
> + unsigned off = (pin / 8) * 4;
> + unsigned shift = (pin % 8) * 4;
Some magic numbers here. Either use relevant #define:s or
put an inline comment that explains what is going on.
> +
> + *config = readl(pctl->base + off);
> + *config >>= shift;
> + *config &= 0xf;
Here too...
> +
> + return 0;
> +}
> +
> +static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
> + struct mvebu_pinctrl_group *grp,
> + unsigned long config)
> +{
> + unsigned pin = grp->gid;
> + unsigned off = (pin / 8) * 4;
> + unsigned shift = (pin % 8) * 4;
> + unsigned long reg;
> +
> + reg = readl(pctl->base + off);
> + reg &= ~(0xf << shift);
> + reg |= (config << shift);
> + writel(reg, pctl->base + off);
> +
> + return 0;
> +}
Same comment as previous function.
(...)
> +static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
> + struct pinctrl_map *map, unsigned num_maps)
> +{
> + kfree(map);
> +}
Is it possible to use devm_* managed devm_kzalloc() for this map
so you don't need to free it explicitly?
(Maybe not, just checking.)
The rest of this file is looking so good that I find nothing to comment on.
(...)
> diff --git a/drivers/pinctrl/pinctrl-mvebu.h b/drivers/pinctrl/pinctrl-mvebu.h
(...)
> +/*
Kerneldoc begins with /** have you really tested to generate
kerneldoc?
> + * struct mvebu_mpp_ctrl - describe a mpp control
> + * @name: name of the control group
> + * @pid: first pin id handled by this control
> + * @npins: number of pins controlled by this control
> + * @mpp_get: (optional) special function to get mpp setting
> + * @mpp_set: (optional) special function to set mpp setting
> + * @mpp_gpio_req: (optional) special function to request gpio
> + * @mpp_gpio_dir: (optional) special function to set gpio direction
> + *
> + * if optional mpp_get/_set functions are set these
> + * are used to get/set a specific mode. Otherwise it is
> + * assumed that the mpp control is based on 4-bit groups
> + * in subsequent registers.
> + *
> + * mpp_gpio_req/_dir functions can be used to allow pin settings
> + * with varying gpio pins.
> + */
> +struct mvebu_mpp_ctrl {
> + const char *name;
> + u8 pid;
> + u8 npins;
So, there will never be > 256 pins on a Marvell platform?
Just checking...
> + unsigned *pins;
> + int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
> + int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
> + int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
> + int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
> +};
> +
> +/*
/**
> + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
> + * @val: ctrl setting value
It is not obvious to me what this means, it it possible to elaborate
on how this member is defined and used?
> + * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
> + * @subname: (optional) additional ctrl setting name, e.g. rts, cts
> + * @variant: (optional) variant identifier mask
This thing again, there are lots of "variants" around here.
Is it a candidate for an enum?
> + * @flags: (private) flags to store gpi/gpo/gpio capabilities
Write something about the two available flags and what they
mean maybe?
> + *
> + * ctrl setting name will be used to switch to this setting in
> + * DT description, e.g. marvell,function = "uart2". subname
> + * is only for debugging purposes.
> + * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
> + * parsed during initialization.
> + */
> +struct mvebu_mpp_ctrl_setting {
> + u8 val;
> + const char *name;
> + const char *subname;
> + u8 variant;
enum?
> + u8 flags;
> +#define MVEBU_SETTING_GPO (1 << 0)
> +#define MVEBU_SETTING_GPI (1 << 1)
So these are the possible flags I suspect. (Looking good.)
> +};
> +
> +/*
> + * struct mvebu_mpp_mode - link ctrl and settings
> + * @pid: first pin id handled by this mode
> + * @settings: list of settings available for this mode
> + */
> +struct mvebu_mpp_mode {
> + u8 pid;
> + struct mvebu_mpp_ctrl_setting *settings;
> +};
> +
> +/*
> + * struct mvebu_pinctrl_soc_info -
> + * SoC specific info passed to pinctrl-mvebu
> + * @variant: variant mask of soc_info
> + * @controls: list of available mvebu_mpp_ctrls
> + * @ncontrols: number of available mvebu_mpp_ctrls
> + * @modes: list of available mvebu_mpp_modes
> + * @nmodes: number of available mvebu_mpp_modes
> + * @gpioranges: list of pinctrl_gpio_ranges
> + * @ngpioranges: number of available pinctrl_gpio_ranges
> + */
> +struct mvebu_pinctrl_soc_info {
> + u8 variant;
Why is this an u8 rather than an enum?
> + struct mvebu_mpp_ctrl *controls;
> + int ncontrols;
> + struct mvebu_mpp_mode *modes;
> + int nmodes;
> + struct pinctrl_gpio_range *gpioranges;
> + int ngpioranges;
> +};
(...)
> +#if defined(CONFIG_DEBUG_FS)
> +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
> + _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
> +#else
> +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
> + _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
> +#endif
This looks a bit kludgy. Is the purpose to save memory
if debugfs is not used?
This looks good overall.
Yours,
Linus Walleij
On 8/20/12, Linus Walleij <[email protected]> wrote:
> Are you taking this patch series through some Marvell tree or do you want
> me to carry it in the pinctrl tree?
Hi Linus,
I think it would be better to take it through the Marvell tree of Jason
Cooper. It is only for Marvell SoCs anyway.
>> +uart1: serial@12100 {
>> + compatible = "ns16550a";
>> + reg = <0x12100 0x100>;
>> + reg-shift = <2>;
>> + interrupts = <7>;
>> + clock-frequency = <166666667>;
>
> It's got nothing to do with this patch, but getting a clock frequency
> out of the DT instead of getting it from the clk_get_rate(clk) and
> the clock tree seems absurd... (But maybe this platform does not
> even have a clk implementation?)
It's of_serial's implementation. I patched that once for getting
frequency out of "clocks" property but then I got busy with
porting mach-dove and pinctrl.. Marvell SoCs do have a clk
implementation and as soon as of_serial can handle "clocks"
property it will be used for sure. I can remove "clock-frequency"
from the example anyway as it is not really part of pinctrl
binding documentation.
> (...)
>> +#include <linux/pinctrl/consumer.h>
>
> Why are you including this header?
> (There are valid reasons, state them in a comment,
> e.g. /* to access pinctrl_gpio* in GPIO portions */)
I guess it was a left-over from my experiments with
default pinmux configuration until you pointed me to
the correct way of having the pinctrl itself hog muxes.
I'll remove that include.
>> +struct mvebu_pinctrl {
>> + struct device *dev;
>> + struct pinctrl_dev *pctldev;
>> + struct pinctrl_desc desc;
>> + void __iomem *base;
>> + struct mvebu_pinctrl_group *groups;
>> + unsigned num_groups;
>> + struct mvebu_pinctrl_function *functions;
>> + unsigned num_functions;
>> + unsigned variant;
>> +};
>
> There is some other "variant" field elsewhere that is
> a u8, is this correct? In this and the other case, should
> this "variant" rather be an enum?
I'll review the variant types but inside pinctrl-mvebu variant
is used as a bit mask to distinguish different variants. Anyway,
they should always be the same size.
>> +static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
>> + struct mvebu_pinctrl_group *grp,
>> + unsigned long *config)
>> +{
>> + unsigned pin = grp->gid;
>> + unsigned off = (pin / 8) * 4;
>> + unsigned shift = (pin % 8) * 4;
>
> Some magic numbers here. Either use relevant #define:s or
> put an inline comment that explains what is going on.
Ok.
>> +static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
>> + struct pinctrl_map *map, unsigned
>> num_maps)
>> +{
>> + kfree(map);
>> +}
>
> Is it possible to use devm_* managed devm_kzalloc() for this map
> so you don't need to free it explicitly?
>
> (Maybe not, just checking.)
Hmm, I guess not as I thought I've read not to use devm_kfree when
you allocate _and_ free stuff on runtime without removing the device
itself, right?
>> diff --git a/drivers/pinctrl/pinctrl-mvebu.h
>> b/drivers/pinctrl/pinctrl-mvebu.h
> (...)
>> +/*
>
> Kerneldoc begins with /** have you really tested to generate
> kerneldoc?
Nope, I wasn't even aware of that, sorry. I just copied it over
from some other pinctrl include. I'll check for compatibility with
kerneldoc.
>> +struct mvebu_mpp_ctrl {
>> + const char *name;
>> + u8 pid;
>> + u8 npins;
>
> So, there will never be > 256 pins on a Marvell platform?
Well, with all current platforms we are well below 100. I guess
256 max (muxable) pins will be enough.
>> + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
>> + * @val: ctrl setting value
>
> It is not obvious to me what this means, it it possible to elaborate
> on how this member is defined and used?
Well, I see if I can clarify the description but wrt the datasheet it
_should_ be quite obvious.
>> + * @variant: (optional) variant identifier mask
>
> This thing again, there are lots of "variants" around here.
> Is it a candidate for an enum?
As it is a mask, I don't think enum fits here.
>> + * @flags: (private) flags to store gpi/gpo/gpio capabilities
>
> Write something about the two available flags and what they
> mean maybe?
Ok.
>> +#define MVEBU_SETTING_GPO (1 << 0)
>> +#define MVEBU_SETTING_GPI (1 << 1)
>
> So these are the possible flags I suspect. (Looking good.)
Yes, some mpp pins on Marvell SoCs are out-only, while
normally they are in-out. I haven't seen in-only yet but better
to have the flags ready if someone stumbles upon one.
>> +#if defined(CONFIG_DEBUG_FS)
>> +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
>> + _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
>> +#else
>> +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
>> + _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
>> +#endif
>
> This looks a bit kludgy. Is the purpose to save memory
> if debugfs is not used?
Yes, that was the intention. Subnames are not used by pinctrl at all,
other for debugfs files. Although, there are some pins that have two different
settings for the same device name, e.g. sata(prsnt) and sata(act), I don't
think it is a good idea to use the subname but have sata(prsnt) and sata-1(act)
instead. Otherwise, you'll always have to look up the specific function for
each pin. OTOH, I could check for "sata" and take the subname into account
when it is given in marvell,function. But it will not help reducing the required
pinmux descriptions in DT because you still have to distinguish both and
there are only 2 out of ~50 groups that have them for Dove.
> This looks good overall.
Thanks!
In some internal review with Andrew I also added a spinlock to
mvebu_pinconf_get/_set that will protect all calls to generic and specific
_get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove
with the devm_ counterpart and removed the explicit clk_put.
Sebastian
Hello,
Le Mon, 20 Aug 2012 11:46:14 +0200,
Sebastian Hesselbarth <[email protected]> a écrit :
> >> +uart1: serial@12100 {
> >> + compatible = "ns16550a";
> >> + reg = <0x12100 0x100>;
> >> + reg-shift = <2>;
> >> + interrupts = <7>;
> >> + clock-frequency = <166666667>;
> >
> > It's got nothing to do with this patch, but getting a clock frequency
> > out of the DT instead of getting it from the clk_get_rate(clk) and
> > the clock tree seems absurd... (But maybe this platform does not
> > even have a clk implementation?)
>
> It's of_serial's implementation. I patched that once for getting
> frequency out of "clocks" property but then I got busy with
> porting mach-dove and pinctrl.. Marvell SoCs do have a clk
> implementation and as soon as of_serial can handle "clocks"
> property it will be used for sure. I can remove "clock-frequency"
> from the example anyway as it is not really part of pinctrl
> binding documentation.
We are also working on using the clk framework for the 370/XP support
(my colleague Grégory in Cc has started working on this last week), and
we also want to be able to get the serial clock-frequency from the clk
framework instead of an explicit value in the DT node. But that's a
separate topic :)
> > Is it possible to use devm_* managed devm_kzalloc() for this map
> > so you don't need to free it explicitly?
> >
> > (Maybe not, just checking.)
>
> Hmm, I guess not as I thought I've read not to use devm_kfree when
> you allocate _and_ free stuff on runtime without removing the device
> itself, right?
It is also my understanding that devm_*() functions should be used to
allocate things that should persist until the device is removed. But I
might be wrong here.
> >> +struct mvebu_mpp_ctrl {
> >> + const char *name;
> >> + u8 pid;
> >> + u8 npins;
> >
> > So, there will never be > 256 pins on a Marvell platform?
>
> Well, with all current platforms we are well below 100. I guess
> 256 max (muxable) pins will be enough.
Agreed, and this structure is completely internal to the kernel, so we
can easily change it in the future if needed.
> >> + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
> >> + * @val: ctrl setting value
> >
> > It is not obvious to me what this means, it it possible to elaborate
> > on how this member is defined and used?
>
> Well, I see if I can clarify the description but wrt the datasheet it
> _should_ be quite obvious.
I think the setting/function/group/control terminology would benefit
from an explanation, as it isn't very easy to figure out what all these
words mean in the context of the pinctrl-mvebu driver.
> In some internal review with Andrew I also added a spinlock to
> mvebu_pinconf_get/_set that will protect all calls to generic and specific
> _get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove
> with the devm_ counterpart and removed the explicit clk_put.
Yes, I had seen this discussion, but I am not sure it is needed: it
seems the pinctrl core calls all the pinconf_set/pinconf_get methods
with the pinctrl_mutex held. When I wrote an initial pinctrl driver for
370/XP I had the same question as Andrew and my conclusion was that the
locking done by the pinctrl subsystem core was sufficient.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
(...)
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> @@ -147,7 +147,7 @@ config PINCTRL_COH901
>
> config PINCTRL_MVEBU
> bool "Marvell SoC pin controller drivers"
> - depends on ARCH_MVEBU
> + depends on ARCH_MVEBU || ARCH_DOVE
Hmmmm.
Shouldn't this thing rather be:
depends on PLAT_ORION
else you end up lining up all Marvell machines here...
> select PINMUX
> select PINCONF
> help
> @@ -155,6 +155,13 @@ config PINCTRL_MVEBU
> This is only the driver core and additionally needs a SoC specific
> driver.
>
> +config PINCTRL_DOVE
> + bool "Support for Marvell Dove SoCs"
> + depends on PINCTRL_MVEBU
Shouldn't this rather be:
depends on ARCH_DOVE
select PINCTRL_MVEBU
since you call down into the mvebu driver, it definatley needs
to select that.
(...)
> diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c
> +#define DOVE_AU0_AC97_SEL (1 << 16)
It is way cleaner to say:
#include <linux/bitops.h>
#define DOVE_AU0_AC97_SEL BIT(16)
(...)
> +static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
> + unsigned long *config)
> +{
> + unsigned off = (ctrl->pid / 8) * 4;
> + unsigned shift = (ctrl->pid % 8) * 4;
> + unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
> + unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
> +
> + if (pmu & (1 << ctrl->pid))
> + *config = 0x10;
> + else
> + *config = (mpp >> shift) & 0xf;
> + return 0;
> +}
Same comments about the magic numbers as in the review of the first
patch.
> +static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
> + unsigned long config)
> +{
> + unsigned off = (ctrl->pid / 8) * 4;
> + unsigned shift = (ctrl->pid % 8) * 4;
> + unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
> + unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
> +
> + if (config == 0x10)
> + writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
> + else {
> + writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
> + mpp &= ~(0xf << shift);
> + mpp |= config << shift;
> + writel(mpp, DOVE_MPP_VIRT_BASE + off);
> + }
> + return 0;
> +}
Dito.
> +static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
> + unsigned long *config)
> +{
> + unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> + unsigned long mask;
> +
> + if (ctrl->pid == 24)
> + mask = DOVE_CAM_GPIO_SEL;
> + else if (ctrl->pid == 40)
> + mask = DOVE_SD0_GPIO_SEL;
> + else if (ctrl->pid == 46)
> + mask = DOVE_SD1_GPIO_SEL;
> + else if (ctrl->pid == 58)
> + mask = DOVE_SPI_GPIO_SEL;
> + else if (ctrl->pid == 62)
> + mask = DOVE_UART1_GPIO_SEL;
> + else
> + return -EINVAL;
Magic numbers, atleast provide a comment on what is so special about
these pins, and can you use a switch() statement instead?
(...)
> +static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
> + unsigned long config)
> +{
> + unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> + unsigned long mask;
> +
> + if (ctrl->pid == 24)
> + mask = DOVE_CAM_GPIO_SEL;
> + else if (ctrl->pid == 40)
> + mask = DOVE_SD0_GPIO_SEL;
> + else if (ctrl->pid == 46)
> + mask = DOVE_SD1_GPIO_SEL;
> + else if (ctrl->pid == 58)
> + mask = DOVE_SPI_GPIO_SEL;
> + else if (ctrl->pid == 62)
> + mask = DOVE_UART1_GPIO_SEL;
> + else
> + return -EINVAL;
Dito.
(...)
> +static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
> + unsigned long *config)
> +{
> + unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> + unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
> + unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
> + unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
> +
> + *config = 0;
> + if (mpp4 & DOVE_AU1_GPIO_SEL)
> + *config |= 0x8;
> + if (sspc1 & DOVE_SSP_ON_AU1)
> + *config |= 0x4;
> + if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
> + *config |= 0x2;
> + if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
> + *config |= 0x1;
More magic, but the flags make it clear what the set
bits are all about, so OK.
But I would have:
#include <linux/bitops.h>
*config |= BIT(0);
etc.
> + /* SSP/TWSI only if I2S1 not set*/
> + if ((*config & 0x8) == 0)
> + *config &= ~(0x4 | 0x1);
> + /* TWSI only if SPDIFO not set*/
> + if ((*config & 0x2) == 0)
> + *config &= ~(0x1);
> + return 0;
And that applies to these.
> +static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
> + unsigned long config)
> +{
> + unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> + unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
> + unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
> + unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
> +
> + if (config & 0x1)
> + gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
> + if (config & 0x2)
> + gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
> + if (config & 0x4)
> + sspc1 |= DOVE_SSP_ON_AU1;
> + if (config & 0x8)
> + mpp4 |= DOVE_AU1_GPIO_SEL;
Dito.
> +static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
> +{
> + unsigned long config;
> +
> + dove_audio1_ctrl_get(ctrl, &config);
> +
> + switch (config) {
> + /* mode 0x00 i2s1/spdifo : no gpio */
> + /* mode 0x0c ssp/spdifo : no gpio */
> + /* mode 0x0f ssp/twsi : no gpio */
> + case 0x00:
> + case 0x0c:
> + case 0x0f:
> + return -ENOTSUPP;
Nice with the comments (also before the function),
now I understand what's happening, this is pretty OK,
I would have put the comments on the same
line as the magic number but whatever.
However you could just delete these lines and let them
fall through to -ENOTSUPP at the bottom.
> +
> + /* mode 0x02 i2s1 : gpio[56:57] */
> + /* mode 0x0e ssp : gpio[56:57] */
> + case 0x02:
> + case 0x0e:
> + if (pid >= 56)
> + return 0;
> +
> + /* mode 0x08 spdifo : gpio[52:55] */
> + /* mode 0x0b twsi : gpio[52:55] */
> + case 0x08:
> + case 0x0b:
> + if (pid <= 55)
> + return 0;
> +
> + /* mode 0x0a/gpio : all gpio */
> + case 0x0a:
> + return 0;
> + }
> +
> + return -ENOTSUPP;
> +}
> +/* mpp[52:57] has gpio pins capable of in and out */
> +static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
> + bool input)
> +{
> + return 0;
> +}
So should this not return a -ENOTSUPP for
pin < 52 || pin > 57?
(...)
> +static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
> +{
> + const struct of_device_id *match =
> + of_match_device(dove_pinctrl_of_match, &pdev->dev);
> + int ret;
> +
> + if (match)
> + pdev->dev.platform_data = match->data;
> +
> + /*
> + * General MPP Configuration Register is part of pdma registers.
> + * grab clk to make sure it is clocked.
> + */
> + pdma_clk = clk_get_sys("dove-pdma", NULL);
First there is something really weird with the name of this
clock. Atleast call the variable holding the clk something
apropriate like just "clk".
Second why are you fetching a sys clock instead of using the clkdev
device binding in the clock tree so you could say:
clk = clk_get(&pdev->dev, NULL);
> + clk_prepare_enable(pdma_clk);
Good!
> + ret = mvebu_pinctrl_probe(pdev);
> + if (!ret)
> + return 0;
> +
> + clk_disable_unprepare(pdma_clk);
> + clk_put(pdma_clk);
> + return ret;
> +}
> +
> +static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
> +{
> + int ret;
> +
> + ret = mvebu_pinctrl_remove(pdev);
> + if (!IS_ERR(pdma_clk)) {
> + clk_disable_unprepare(pdma_clk);
> + clk_put(pdma_clk);
> + }
You don't need this (!IS_ERR()) clause, look in yout probe function:
you bail out if the clock is not found.
The rest looks good... atleast now, but I'm low on coffee FTM.
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
> plus DT binding documentation. This driver will use the mvebu pinctrl
> driver core.
Thanks for working on Kirkwood. Love this platform.
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index cd3d827..361f513 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
> select GENERIC_CLOCKEVENTS
> select NEED_MACH_IO_H
> select PLAT_ORION
> + select PINCTRL
select PINCTRL_KIRKWOOD too I think.
Then it's just automatic.
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index e2427eb..1f84090 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -147,7 +147,7 @@ config PINCTRL_COH901
>
> config PINCTRL_MVEBU
> bool "Marvell SoC pin controller drivers"
> - depends on ARCH_MVEBU || ARCH_DOVE
> + depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
As stated elsewhere I think this should be
depends on PLAT_ORION
> +config PINCTRL_KIRKWOOD
> + bool "Support for Marvell Kirkwood SoCs"
> + depends on PINCTRL_MVEBU
depends on ARCH_KIRKWOOD
select PINCTRL_MVEBU
(...)
> diff --git a/drivers/pinctrl/pinctrl-kirkwood.c b/drivers/pinctrl/pinctrl-kirkwood.c
> +static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
> +
> +static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
> + { .compatible = "marvell,88f6180-pinctrl",
> + .data = (void *)VARIANT_MV88F6180 },
> + { .compatible = "marvell,88f6190-pinctrl",
> + .data = (void *)VARIANT_MV88F6190 },
> + { .compatible = "marvell,88f6192-pinctrl",
> + .data = (void *)VARIANT_MV88F6192 },
> + { .compatible = "marvell,88f6281-pinctrl",
> + .data = (void *)VARIANT_MV88F6281 },
> + { .compatible = "marvell,88f6282-pinctrl",
> + .data = (void *)VARIANT_MV88F6282 },
> + { }
> +};
I'm thinking this variant should maybe be an enum... unless it is
strongly established somewhere in Orion/Marvell stuff.
> +static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
> +{
> + struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
> + const struct of_device_id *match =
> + of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
> +
> + if (match) {
> + soc->variant = (unsigned)match->data & 0xff;
> + switch (soc->variant) {
> + case VARIANT_MV88F6180:
> + soc->controls = mv88f6180_mpp_controls;
> + soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
> + soc->modes = mv88f6xxx_mpp_modes;
> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
> + soc->gpioranges = mv88f6180_gpio_ranges;
> + soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
> + break;
> + case VARIANT_MV88F6190:
> + case VARIANT_MV88F6192:
> + soc->controls = mv88f619x_mpp_controls;
> + soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
> + soc->modes = mv88f6xxx_mpp_modes;
> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
> + soc->gpioranges = mv88f619x_gpio_ranges;
> + soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
> + break;
> + case VARIANT_MV88F6281:
> + case VARIANT_MV88F6282:
> + soc->controls = mv88f628x_mpp_controls;
> + soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
> + soc->modes = mv88f6xxx_mpp_modes;
> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
> + soc->gpioranges = mv88f628x_gpio_ranges;
> + soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
> + break;
> + }
> + pdev->dev.platform_data = soc;
> + }
> + return mvebu_pinctrl_probe(pdev);
> +}
This is looking real good, clean & nice.
No further comments on this driver.
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> This patch adds a pinctrl driver core for Marvell SoCs plus DT
> binding documentation. This core driver will be used by SoC family
> specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
(...)
> +config PINCTRL_MVEBU
> + bool "Marvell SoC pin controller drivers"
> + depends on ARCH_MVEBU
So altering earlier statements I suspect this should be simply:
depends on PLAT_ORION
Yours,
Linus Walleij
On Mon, Aug 20, 2012 at 11:46 AM, Sebastian Hesselbarth
<[email protected]> wrote:
> On 8/20/12, Linus Walleij <[email protected]> wrote:
>> Are you taking this patch series through some Marvell tree or do you want
>> me to carry it in the pinctrl tree?
>
> I think it would be better to take it through the Marvell tree of Jason
> Cooper. It is only for Marvell SoCs anyway.
OK.
>> There is some other "variant" field elsewhere that is
>> a u8, is this correct? In this and the other case, should
>> this "variant" rather be an enum?
>
> I'll review the variant types but inside pinctrl-mvebu variant
> is used as a bit mask to distinguish different variants. Anyway,
> they should always be the same size.
Aha bitmask, seems you can only have 8 different variants of
the Marvell's then?
>> Is it possible to use devm_* managed devm_kzalloc() for this map
>> so you don't need to free it explicitly?
>>
>> (Maybe not, just checking.)
>
> Hmm, I guess not as I thought I've read not to use devm_kfree when
> you allocate _and_ free stuff on runtime without removing the device
> itself, right?
You're right.
>> So, there will never be > 256 pins on a Marvell platform?
>
> Well, with all current platforms we are well below 100. I guess
> 256 max (muxable) pins will be enough.
OK.
>>> + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
>>> + * @val: ctrl setting value
>>
>> It is not obvious to me what this means, it it possible to elaborate
>> on how this member is defined and used?
>
> Well, I see if I can clarify the description but wrt the datasheet it
> _should_ be quite obvious.
I mainly worry about being able to read the code and figure out
what's going on, if the datasheet is vital then pls include some
link to it or so in the header of the file (but preferrably the code
should speak for itself).
>>> + * @variant: (optional) variant identifier mask
>>
>> This thing again, there are lots of "variants" around here.
>> Is it a candidate for an enum?
>
> As it is a mask, I don't think enum fits here.
OK. No big deal anyway.
> In some internal review with Andrew I also added a spinlock to
> mvebu_pinconf_get/_set that will protect all calls to generic and specific
> _get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove
> with the devm_ counterpart and removed the explicit clk_put.
I had some separate comments on that clk thing...
Anyway, looking forward to v2, this is progressing quickly
I think.
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> This pinctrl driver is not a full-blown pinctrl driver from scratch:
> it relies on the common pinctrl-mvebu driver, which is used for all
> Marvell EBU SoCs.
Good!
> +config PINCTRL_ARMADA_370
> + bool "Support for Marvell Armada 370 SoCs"
> + depends on PINCTRL_MVEBU
> + depends on MACH_ARMADA_370_XP
select PINCTRL_MVEBU simply?
And then have the Armada Kconfig
select PINCTRL
select PINCTRL_ARMADA_370
This machine doesn't seem to depend in the MVEBU driver, I guess it's
the same ARCH as something else, oh well. Still suspect the
MVEBU driver should depend on PLAT_ORION until proven
wrong.
(...)
> +static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
> +{
> + struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
> +
> + soc->variant = 0;
Shouldn't this be a #defined thing or something. "variant 0" doesn't
tell me much.
No further comments, looking good.
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> From: Thomas Petazzoni <[email protected]>
>
> This pinctrl driver is not a full-blown pinctrl driver from scratch:
> it relies on the common pinctrl-mvebu driver, which is used for all
> Marvell EBU SoCs.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
Same comments as on the previous driver, no further comments,
and looking good.
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> From: Thomas Petazzoni <[email protected]>
>
> The Armada 370 and XP SoCs have configurable muxing for a certain
> number of their pins, controlled through a pinctrl driver.
>
> The 'compatible' property is defined in the SoC-specific .dtsi files,
> since the compatible string identifies the number of pins and other
> SoC-specific properties.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
FWIW:
Acked-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> From: Thomas Petazzoni <[email protected]>
>
> This commits adds the necessary device tree information to define the
> compatible property for the pinctrl driver instance of Armada XP SoCs.
>
> Until now, the device tree representation considered the Armada XP as
> a single SoC. But in fact, there are three different SoCs in the
> Armada XP families, with different number of CPU cores, different
> number of Ethernet interfaces... and different number of muxable pins
> or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
> the three SoCs of the Armada XP family. The current armada-xp-db.dts
> evaluation board uses the MV78460 variant of the SoC.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
FWIW:
Acked-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> From: Thomas Petazzoni <[email protected]>
>
> This commits adds the necessary device tree information to define the
> compatible property for the pinctrl driver instance of Armada 370 SoC.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
FWIW:
Acked-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> From: Thomas Petazzoni <[email protected]>
>
> The Armada XP evaluation board is based on the MV78460 Armava XP
> SoC. Now that we have separate .dtsi files for the three different
> SoCs of the Armada XP family, use the appropriate one as include for
> the Armada XP evaluation board .dts file.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
FWIW:
Acked-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> From: Thomas Petazzoni <[email protected]>
>
> Now that we have a proper pinctrl driver for Marvell EBU platforms,
> enable PINCTRL support in ARCH_MVEBU.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
(...)
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 361f513..95317a9 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -573,6 +573,7 @@ config ARCH_MVEBU
> select GENERIC_IRQ_CHIP
> select IRQ_DOMAIN
> select COMMON_CLK
> + select PINCTRL
> help
> Support for the Marvell SoC Family with device tree support
So this symbol collects all the DT-migrated platforms?
Probably OK but want to figure out if the PLAT_NOMADIK symbol
is applicable.
Yours,
Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<[email protected]> wrote:
> diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
> index 2e86b31..cb07e64 100644
> --- a/arch/arm/configs/mvebu_defconfig
> +++ b/arch/arm/configs/mvebu_defconfig
> @@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_PINCTRL_ARMADA_370=y
> +CONFIG_PINCTRL_ARMADA_XP=y
If the system is not even booting without pinctrl you should
(IMHO) select these from the machine's Kconfig entry insteaf.
If they boot fine without I'm fine with this ... the arch maintainer
gets to choose anyway.
Yours,
Linus Walleij
On 08/20/2012 03:43 PM, Linus Walleij wrote:
>> config PINCTRL_MVEBU
>> bool "Marvell SoC pin controller drivers"
>> - depends on ARCH_MVEBU
>> + depends on ARCH_MVEBU || ARCH_DOVE
>
> Hmmmm.
>
> Shouldn't this thing rather be:
> depends on PLAT_ORION
> else you end up lining up all Marvell machines here...
> (...)
>> +config PINCTRL_DOVE
>> + bool "Support for Marvell Dove SoCs"
>> + depends on PINCTRL_MVEBU
>
> Shouldn't this rather be:
>
> depends on ARCH_DOVE
> select PINCTRL_MVEBU
>
> since you call down into the mvebu driver, it definatley needs
> to select that.
Yes, this is a bit difficult but PLAT_ORION is basically all existing
Marvell SoCs of the Orion family. Armada 370/XP are two new SoCs
_and_ the approach to combine all into one mach-mvebu. The pinctrl
driver will only be made available to mach-mvebu as I am already close
to have at least mach-dove ported over.
After the review of Andrew, I already changed the Kconfig to have the
structure you are proposing.
>> +#define DOVE_AU0_AC97_SEL (1<< 16)
>
> It is way cleaner to say:
> #include<linux/bitops.h>
> #define DOVE_AU0_AC97_SEL BIT(16)
Ok.
> Same comments about the magic numbers as in the review of the first
> patch.
I just agree with all of these comments and will work them in.
>> + if (ctrl->pid == 24)
>> + mask = DOVE_CAM_GPIO_SEL;
>> + else if (ctrl->pid == 40)
>> + mask = DOVE_SD0_GPIO_SEL;
>> + else if (ctrl->pid == 46)
>> + mask = DOVE_SD1_GPIO_SEL;
>> + else if (ctrl->pid == 58)
>> + mask = DOVE_SPI_GPIO_SEL;
>> + else if (ctrl->pid == 62)
>> + mask = DOVE_UART1_GPIO_SEL;
>> + else
>> + return -EINVAL;
>
> Magic numbers, atleast provide a comment on what is so special about
> these pins, and can you use a switch() statement instead?
Sure.
>> +static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
>> +{
>> + unsigned long config;
>> +
>> + dove_audio1_ctrl_get(ctrl,&config);
>> +
>> + switch (config) {
>> + /* mode 0x00 i2s1/spdifo : no gpio */
>> + /* mode 0x0c ssp/spdifo : no gpio */
>> + /* mode 0x0f ssp/twsi : no gpio */
>> + case 0x00:
>> + case 0x0c:
>> + case 0x0f:
>> + return -ENOTSUPP;
>
> Nice with the comments (also before the function),
> now I understand what's happening, this is pretty OK,
> I would have put the comments on the same
> line as the magic number but whatever.
>
> However you could just delete these lines and let them
> fall through to -ENOTSUPP at the bottom.
Ok.
>> +/* mpp[52:57] has gpio pins capable of in and out */
>> +static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
>> + bool input)
>> +{
>> + return 0;
>> +}
>
> So should this not return a -ENOTSUPP for
> pin< 52 || pin> 57?
Well, as pinctrl-mvebu and pinctrl core are already checking for pin
ranges, I think it's ok not to do it here again. But I don't have a
strong opinion about that.
>> + /*
>> + * General MPP Configuration Register is part of pdma registers.
>> + * grab clk to make sure it is clocked.
>> + */
>> + pdma_clk = clk_get_sys("dove-pdma", NULL);
>
> First there is something really weird with the name of this
> clock. Atleast call the variable holding the clk something
> apropriate like just "clk".
>
> Second why are you fetching a sys clock instead of using the clkdev
> device binding in the clock tree so you could say:
>
> clk = clk_get(&pdev->dev, NULL);
pdma is the name of the clock gating control bit used in DS, IIRC it
stands for Peripheral DMA. Moreover, as I already mentioned it is now
using devm_clk_get. I think the time the pinctrl-dove driver patch was
posted there was no clock binding in 3.6.
>> +static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
>> +{
>> + int ret;
>> +
>> + ret = mvebu_pinctrl_remove(pdev);
>> + if (!IS_ERR(pdma_clk)) {
>> + clk_disable_unprepare(pdma_clk);
>> + clk_put(pdma_clk);
>> + }
>
> You don't need this (!IS_ERR()) clause, look in yout probe function:
> you bail out if the clock is not found.
Agree.
Sebastian
On 08/20/2012 04:18 PM, Linus Walleij wrote:
>> I'll review the variant types but inside pinctrl-mvebu variant
>> is used as a bit mask to distinguish different variants. Anyway,
>> they should always be the same size.
>
> Aha bitmask, seems you can only have 8 different variants of
> the Marvell's then?
Only 8 different variants of one SoC! Currently, there are 5 for
Kirkwood, none for Dove. I think there are two more Kirkwood's that
never appeared in public, but it is still < 8.
>> Well, I see if I can clarify the description but wrt the datasheet it
>> _should_ be quite obvious.
>
> I mainly worry about being able to read the code and figure out
> what's going on, if the datasheet is vital then pls include some
> link to it or so in the header of the file (but preferrably the code
> should speak for itself).
Ok, I clarify whats meant by mvebu_*_ctrl/ctrl_setting/mode. I am not
that happy with that names either, but honestly pinctrl core already
took all names that I'd have chosen. Therefore, I chose some that do
not interfere with pinctrl core as the meaning is different.
Sebastian
On 08/20/2012 04:31 PM, Linus Walleij wrote:
> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> <[email protected]> wrote:
>> +CONFIG_PINCTRL_ARMADA_370=y
>> +CONFIG_PINCTRL_ARMADA_XP=y
>
> If the system is not even booting without pinctrl you should
> (IMHO) select these from the machine's Kconfig entry insteaf.
I don't have a strong opinion on this but I think most systems
will boot just fine without pinctrl. The basic stuff is set up
by u-boot. Anyway, I think we should enable pinctrl for each soc
by default.
Sebastian
On 08/20/2012 04:25 PM, Linus Walleij wrote:
>> +config PINCTRL_ARMADA_370
>> + bool "Support for Marvell Armada 370 SoCs"
>> + depends on PINCTRL_MVEBU
>> + depends on MACH_ARMADA_370_XP
>
> select PINCTRL_MVEBU simply?
>
> And then have the Armada Kconfig
>
> select PINCTRL
> select PINCTRL_ARMADA_370
Linus, Thomas, Gregory,
this is really difficult here ;) I thought I could just add PINCTRL_DOVE
to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso.
But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.
If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and
you work it out if you ever have two distinct MACHs? Or it could remain
selectable in pinctrl/Kconfig but that will then be different with the
other stubs.
Sebastian
Le Mon, 20 Aug 2012 18:48:32 +0200,
Sebastian Hesselbarth <[email protected]> a écrit :
> this is really difficult here ;) I thought I could just add PINCTRL_DOVE
> to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso.
> But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.
>
> If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and
> you work it out if you ever have two distinct MACHs? Or it could remain
> selectable in pinctrl/Kconfig but that will then be different with the
> other stubs.
In order to keep the consistency with other SoC families, maybe we can
split the 370 and XP options in two separate MACH_ARMADA_370 and
MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are
converted to DT+mach-mvebu, we should have:
*) arch/arm/Kconfig defines MACH_MVEBU
*) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,
MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X
Then, an user is free to build a single kernel image that supports all,
or a selection of the supported Marvell EBU SoCs.
Would that be ok with you?
If that's fine with you, then I would prefer if we keep the single
MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of patches
does not depend on something else. We would do the small Kconfig option
refactoring as a follow-up set of patches. Thoughts?
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Le Mon, 20 Aug 2012 16:54:27 +0200,
Sebastian Hesselbarth <[email protected]> a écrit :
> On 08/20/2012 04:31 PM, Linus Walleij wrote:
> > On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> > <[email protected]> wrote:
> >> +CONFIG_PINCTRL_ARMADA_370=y
> >> +CONFIG_PINCTRL_ARMADA_XP=y
> >
> > If the system is not even booting without pinctrl you should
> > (IMHO) select these from the machine's Kconfig entry insteaf.
>
> I don't have a strong opinion on this but I think most systems
> will boot just fine without pinctrl. The basic stuff is set up
> by u-boot. Anyway, I think we should enable pinctrl for each soc
> by default.
Yes, the system boots fine without the pinctrl support. So I don't
think that MACH_ARMADA_370_XP should forcefully select the pinctrl
code, but it's nice to have the default defconfig for this platform
select the pinctrl support.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
On 08/20/2012 07:36 PM, Thomas Petazzoni wrote:
> In order to keep the consistency with other SoC families, maybe we can
> split the 370 and XP options in two separate MACH_ARMADA_370 and
> MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are
> converted to DT+mach-mvebu, we should have:
>
> *) arch/arm/Kconfig defines MACH_MVEBU
>
> *) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,
> MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X
>
> Then, an user is free to build a single kernel image that supports all,
> or a selection of the supported Marvell EBU SoCs.
>
> Would that be ok with you?
Yes!
> If that's fine with you, then I would prefer if we keep the single
> MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of patches
> does not depend on something else. We would do the small Kconfig option
> refactoring as a follow-up set of patches. Thoughts?
Despite any objections, I will remove all arch/arm/*/Kconfig patches
from pinctrl patch set.
Sebastian
Le Mon, 20 Aug 2012 15:43:11 +0200,
Linus Walleij <[email protected]> a écrit :
> > config PINCTRL_MVEBU
> > bool "Marvell SoC pin controller drivers"
> > - depends on ARCH_MVEBU
> > + depends on ARCH_MVEBU || ARCH_DOVE
>
> Hmmmm.
>
> Shouldn't this thing rather be:
>
> depends on PLAT_ORION
>
> else you end up lining up all Marvell machines here...
When we started working on this, ARCH_MVEBU was not a PLAT_ORION
platform, because PLAT_ORION includes its own custom pinmux code, gpio
code, etc, and what we're trying to achieve with Sebastian is to clean
all this. Ultimately, our goal is to have all Orion, Kirkwood, Dove,
Discovery and Armada 370/XP supported in mach-mvebu, and therefore
plat-orion would most likely disappear.
In the mean time, a patch got accepted that separates PLAT_ORION for
PLAT_ORION_LEGACY, and therefore MACH_MVEBU now selects PLAT_ORION to
access things that are still useful (address decoding code) while all
other platforms select PLAT_ORION_LEGACY to get the old pinmux code,
old gpio code, etc. All this is very much a work in progress.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Le Mon, 20 Aug 2012 20:01:51 +0200,
Sebastian Hesselbarth <[email protected]> a écrit :
> > If that's fine with you, then I would prefer if we keep the single
> > MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of
> > patches does not depend on something else. We would do the small
> > Kconfig option refactoring as a follow-up set of patches. Thoughts?
>
> Despite any objections, I will remove all arch/arm/*/Kconfig patches
> from pinctrl patch set.
Ok, fine with me, but we'll have to send separate patches for those,
then.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
On 08/20/2012 07:36 PM, Thomas Petazzoni wrote:
> Le Mon, 20 Aug 2012 18:48:32 +0200,
> Sebastian Hesselbarth <[email protected]> a écrit :
>
>> this is really difficult here ;) I thought I could just add PINCTRL_DOVE
>> to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso.
>> But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.
>>
>> If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and
>> you work it out if you ever have two distinct MACHs? Or it could remain
>> selectable in pinctrl/Kconfig but that will then be different with the
>> other stubs.
>
> In order to keep the consistency with other SoC families, maybe we can
> split the 370 and XP options in two separate MACH_ARMADA_370 and
> MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are
> converted to DT+mach-mvebu, we should have:
>
> *) arch/arm/Kconfig defines MACH_MVEBU
>
> *) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,
> MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X
>
> Then, an user is free to build a single kernel image that supports all,
> or a selection of the supported Marvell EBU SoCs.
I agree with Thomas
>
> Thomas
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and
SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood.
The SoC specific stubs use the pinctrl-mvebu core driver that handles
pinctrl API and register accesses for common pinctrl registers.
As especially Dove has some pinctrl registers that do not match the
common pinctrl register layout the core driver has been extended by
some callbacks to allow uncommon Dove pinctrl registers.
DT binding documentation is added for all supported SoCs but as
Dove and Kirkwood are not yet ready for full DT support, the pinctrl
driver is only activated for Armada 370 and XP.
The driver has been tested on Dove, 88f6281 variant of Kirkwood,
Armada 370, and XP.
Changelog:
v2:
- rebased on git://git.infradead.org/users/jcooper/linux.git boards-for-3.7
- removed arch/arm/*/Kconfig patches that enable PINCTRL_ on MACH_MVEBU
(those will be sent as a different patch set)
- reworked patches wrt reviews from Andrew Lunn and Linus Walleij
Sebastian Hesselbarth (3):
pinctrl: mvebu: pinctrl driver core
pinctrl: mvebu: dove pinctrl driver
pinctrl: mvebu: kirkwood pinctrl driver
Thomas Petazzoni (6):
pinctrl: mvebu: add pinctrl driver for Armada 370
pinctrl: mvebu: add pinctrl driver for Armada XP
ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs
ARM: mvebu: Add pinctrl support to Armada XP SoCs
ARM: mvebu: Add pinctrl support to Armada 370 SoC
ARM: mvebu: adjust Armada XP evaluation board DTS
.../pinctrl/marvell,armada-370-pinctrl.txt | 95 +++
.../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 100 +++
.../bindings/pinctrl/marvell,dove-pinctrl.txt | 72 ++
.../bindings/pinctrl/marvell,kirkwood-pinctrl.txt | 279 +++++++
.../bindings/pinctrl/marvell,mvebu-pinctrl.txt | 45 ++
arch/arm/Kconfig | 1 +
arch/arm/boot/dts/armada-370-xp.dtsi | 7 +
arch/arm/boot/dts/armada-370.dtsi | 4 +
arch/arm/boot/dts/armada-xp-db.dts | 4 +-
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 27 +
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 27 +
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 27 +
drivers/pinctrl/Kconfig | 22 +
drivers/pinctrl/Makefile | 5 +
drivers/pinctrl/pinctrl-armada-370.c | 421 +++++++++++
drivers/pinctrl/pinctrl-armada-xp.c | 468 ++++++++++++
drivers/pinctrl/pinctrl-dove.c | 622 ++++++++++++++++
drivers/pinctrl/pinctrl-kirkwood.c | 462 ++++++++++++
drivers/pinctrl/pinctrl-mvebu.c | 761 ++++++++++++++++++++
drivers/pinctrl/pinctrl-mvebu.h | 192 +++++
20 files changed, 3639 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
create mode 100644 drivers/pinctrl/pinctrl-dove.c
create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
create mode 100644 drivers/pinctrl/pinctrl-mvebu.h
---
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
v2:
- removed arch/arm/*/Kconfig changes and added note about variant = 0
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../pinctrl/marvell,armada-370-pinctrl.txt | 95 +++++
drivers/pinctrl/Kconfig | 4 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-armada-370.c | 421 ++++++++++++++++++++
4 files changed, 521 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
new file mode 100644
index 0000000..01ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name pins functions
+================================================================================
+mpp0 0 gpio, uart0(rxd)
+mpp1 1 gpo, uart0(txd)
+mpp2 2 gpio, i2c0(sck), uart0(txd)
+mpp3 3 gpio, i2c0(sda), uart0(rxd)
+mpp4 4 gpio, cpu_pd(vdd)
+mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+ sata1(prsnt), spi1(cs1)
+mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+ audio(spdifi)
+mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+ audio(rmclk)
+mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+ spi0(cs2)
+mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+ spi0(cs3)
+mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17 17 gpo, ge(mdc)
+mpp18 18 gpio, ge(mdio)
+mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20 20 gpo, ge0(txd4), ge1(txd0)
+mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
+mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31 31 gpio, tclk, ge0(txerr)
+mpp32 32 gpio, spi0(cs0)
+mpp33 33 gpio, dev(bootcs), spi0(cs0)
+mpp34 34 gpo, dev(wen0), spi0(mosi)
+mpp35 35 gpo, dev(oen), spi0(sck)
+mpp36 36 gpo, dev(a1), spi0(miso)
+mpp37 37 gpo, dev(a0), sata0(prsnt)
+mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39 39 gpo, dev(ad0), audio(spdifo)
+mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41 41 gpio, dev(ad2), uart1(rxd)
+mpp42 42 gpo, dev(ad3), uart1(txd)
+mpp43 43 gpo, dev(ad4), audio(bclk)
+mpp44 44 gpo, dev(ad5), audio(mclk)
+mpp45 45 gpo, dev(ad6), audio(lrclk)
+mpp46 46 gpo, dev(ad7), audio(sdo)
+mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+ spi0(cs1)
+mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+ audio(spdifi)
+mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+ audio(rmclk)
+mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+ pcie(clkreq1)
+mpp54 54 gpo, dev(ad15), tdm(dtx)
+mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+ sata0(prsnt)
+mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+ pcie(clkreq0), spi1(cs1)
+mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+ audio(sdo)
+mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+ uart0(rts)
+mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+ audio(sdi)
+mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+ audio(mclk), uart0(cts)
+mpp63 63 gpo, spi0(sck), tclk
+mpp64 64 gpio, spi0(miso), spi0-1(cs1)
+mpp65 65 gpio, spi0(mosi), spi0-1(cs2)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 31c0bba..e16b8b0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -159,6 +159,10 @@ config PINCTRL_KIRKWOOD
bool
select PINCTRL_MVEBU
+config PINCTRL_ARMADA_370
+ bool
+ select PINCTRL_MVEBU
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3006294..e6d6667 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-armada-370.c b/drivers/pinctrl/pinctrl-armada-370.c
new file mode 100644
index 0000000..c907647
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-370.c
@@ -0,0 +1,421 @@
+/*
+ * Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "uart0", "rxd")),
+ MPP_MODE(1,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "uart0", "txd")),
+ MPP_MODE(2,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "i2c0", "sck"),
+ MPP_FUNCTION(0x2, "uart0", "txd")),
+ MPP_MODE(3,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "i2c0", "sda"),
+ MPP_FUNCTION(0x2, "uart0", "rxd")),
+ MPP_MODE(4,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
+ MPP_MODE(5,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txclko"),
+ MPP_FUNCTION(0x2, "uart1", "txd"),
+ MPP_FUNCTION(0x4, "spi1", "clk"),
+ MPP_FUNCTION(0x5, "audio", "mclk")),
+ MPP_MODE(6,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd0"),
+ MPP_FUNCTION(0x2, "sata0", "prsnt"),
+ MPP_FUNCTION(0x4, "tdm", "rst"),
+ MPP_FUNCTION(0x5, "audio", "sdo")),
+ MPP_MODE(7,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd1"),
+ MPP_FUNCTION(0x4, "tdm", "tdx"),
+ MPP_FUNCTION(0x5, "audio", "lrclk")),
+ MPP_MODE(8,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd2"),
+ MPP_FUNCTION(0x2, "uart0", "rts"),
+ MPP_FUNCTION(0x4, "tdm", "drx"),
+ MPP_FUNCTION(0x5, "audio", "bclk")),
+ MPP_MODE(9,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd3"),
+ MPP_FUNCTION(0x2, "uart1", "txd"),
+ MPP_FUNCTION(0x3, "sd0", "clk"),
+ MPP_FUNCTION(0x5, "audio", "spdifo")),
+ MPP_MODE(10,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txctl"),
+ MPP_FUNCTION(0x2, "uart0", "cts"),
+ MPP_FUNCTION(0x4, "tdm", "fsync"),
+ MPP_FUNCTION(0x5, "audio", "sdi")),
+ MPP_MODE(11,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd0"),
+ MPP_FUNCTION(0x2, "uart1", "rxd"),
+ MPP_FUNCTION(0x3, "sd0", "cmd"),
+ MPP_FUNCTION(0x4, "spi0", "cs1"),
+ MPP_FUNCTION(0x5, "sata1", "prsnt"),
+ MPP_FUNCTION(0x6, "spi1", "cs1")),
+ MPP_MODE(12,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd1"),
+ MPP_FUNCTION(0x2, "i2c1", "sda"),
+ MPP_FUNCTION(0x3, "sd0", "d0"),
+ MPP_FUNCTION(0x4, "spi1", "cs0"),
+ MPP_FUNCTION(0x5, "audio", "spdifi")),
+ MPP_MODE(13,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd2"),
+ MPP_FUNCTION(0x2, "i2c1", "sck"),
+ MPP_FUNCTION(0x3, "sd0", "d1"),
+ MPP_FUNCTION(0x4, "tdm", "pclk"),
+ MPP_FUNCTION(0x5, "audio", "rmclk")),
+ MPP_MODE(14,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd3"),
+ MPP_FUNCTION(0x2, "pcie", "clkreq0"),
+ MPP_FUNCTION(0x3, "sd0", "d2"),
+ MPP_FUNCTION(0x4, "spi1", "mosi"),
+ MPP_FUNCTION(0x5, "spi0", "cs2")),
+ MPP_MODE(15,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxctl"),
+ MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+ MPP_FUNCTION(0x3, "sd0", "d3"),
+ MPP_FUNCTION(0x4, "spi1", "miso"),
+ MPP_FUNCTION(0x5, "spi0", "cs3")),
+ MPP_MODE(16,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxclk"),
+ MPP_FUNCTION(0x2, "uart1", "rxd"),
+ MPP_FUNCTION(0x4, "tdm", "int"),
+ MPP_FUNCTION(0x5, "audio", "extclk")),
+ MPP_MODE(17,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge", "mdc")),
+ MPP_MODE(18,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge", "mdio")),
+ MPP_MODE(19,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txclk"),
+ MPP_FUNCTION(0x2, "ge1", "txclkout"),
+ MPP_FUNCTION(0x4, "tdm", "pclk")),
+ MPP_MODE(20,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd4"),
+ MPP_FUNCTION(0x2, "ge1", "txd0")),
+ MPP_MODE(21,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd5"),
+ MPP_FUNCTION(0x2, "ge1", "txd1"),
+ MPP_FUNCTION(0x4, "uart1", "txd")),
+ MPP_MODE(22,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd6"),
+ MPP_FUNCTION(0x2, "ge1", "txd2"),
+ MPP_FUNCTION(0x4, "uart0", "rts")),
+ MPP_MODE(23,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "ge0", "txd7"),
+ MPP_FUNCTION(0x2, "ge1", "txd3"),
+ MPP_FUNCTION(0x4, "spi1", "mosi")),
+ MPP_MODE(24,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "col"),
+ MPP_FUNCTION(0x2, "ge1", "txctl"),
+ MPP_FUNCTION(0x4, "spi1", "cs0")),
+ MPP_MODE(25,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxerr"),
+ MPP_FUNCTION(0x2, "ge1", "rxd0"),
+ MPP_FUNCTION(0x4, "uart1", "rxd")),
+ MPP_MODE(26,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "crs"),
+ MPP_FUNCTION(0x2, "ge1", "rxd1"),
+ MPP_FUNCTION(0x4, "spi1", "miso")),
+ MPP_MODE(27,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd4"),
+ MPP_FUNCTION(0x2, "ge1", "rxd2"),
+ MPP_FUNCTION(0x4, "uart0", "cts")),
+ MPP_MODE(28,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd5"),
+ MPP_FUNCTION(0x2, "ge1", "rxd3")),
+ MPP_MODE(29,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd6"),
+ MPP_FUNCTION(0x2, "ge1", "rxctl"),
+ MPP_FUNCTION(0x4, "i2c1", "sda")),
+ MPP_MODE(30,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "ge0", "rxd7"),
+ MPP_FUNCTION(0x2, "ge1", "rxclk"),
+ MPP_FUNCTION(0x4, "i2c1", "sck")),
+ MPP_MODE(31,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x3, "tclk", NULL),
+ MPP_FUNCTION(0x4, "ge0", "txerr")),
+ MPP_MODE(32,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "spi0", "cs0")),
+ MPP_MODE(33,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "bootcs"),
+ MPP_FUNCTION(0x2, "spi0", "cs0")),
+ MPP_MODE(34,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "wen0"),
+ MPP_FUNCTION(0x2, "spi0", "mosi")),
+ MPP_MODE(35,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "oen"),
+ MPP_FUNCTION(0x2, "spi0", "sck")),
+ MPP_MODE(36,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "a1"),
+ MPP_FUNCTION(0x2, "spi0", "miso")),
+ MPP_MODE(37,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "a0"),
+ MPP_FUNCTION(0x2, "sata0", "prsnt")),
+ MPP_MODE(38,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ready"),
+ MPP_FUNCTION(0x2, "uart1", "cts"),
+ MPP_FUNCTION(0x3, "uart0", "cts")),
+ MPP_MODE(39,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad0"),
+ MPP_FUNCTION(0x2, "audio", "spdifo")),
+ MPP_MODE(40,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad1"),
+ MPP_FUNCTION(0x2, "uart1", "rts"),
+ MPP_FUNCTION(0x3, "uart0", "rts")),
+ MPP_MODE(41,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad2"),
+ MPP_FUNCTION(0x2, "uart1", "rxd")),
+ MPP_MODE(42,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad3"),
+ MPP_FUNCTION(0x2, "uart1", "txd")),
+ MPP_MODE(43,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad4"),
+ MPP_FUNCTION(0x2, "audio", "bclk")),
+ MPP_MODE(44,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad5"),
+ MPP_FUNCTION(0x2, "audio", "mclk")),
+ MPP_MODE(45,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad6"),
+ MPP_FUNCTION(0x2, "audio", "lrclk")),
+ MPP_MODE(46,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad7"),
+ MPP_FUNCTION(0x2, "audio", "sdo")),
+ MPP_MODE(47,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad8"),
+ MPP_FUNCTION(0x3, "sd0", "clk"),
+ MPP_FUNCTION(0x5, "audio", "spdifo")),
+ MPP_MODE(48,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad9"),
+ MPP_FUNCTION(0x2, "uart0", "rts"),
+ MPP_FUNCTION(0x3, "sd0", "cmd"),
+ MPP_FUNCTION(0x4, "sata1", "prsnt"),
+ MPP_FUNCTION(0x5, "spi0", "cs1")),
+ MPP_MODE(49,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad10"),
+ MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+ MPP_FUNCTION(0x3, "sd0", "d0"),
+ MPP_FUNCTION(0x4, "spi1", "cs0"),
+ MPP_FUNCTION(0x5, "audio", "spdifi")),
+ MPP_MODE(50,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad11"),
+ MPP_FUNCTION(0x2, "uart0", "cts"),
+ MPP_FUNCTION(0x3, "sd0", "d1"),
+ MPP_FUNCTION(0x4, "spi1", "miso"),
+ MPP_FUNCTION(0x5, "audio", "rmclk")),
+ MPP_MODE(51,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad12"),
+ MPP_FUNCTION(0x2, "i2c1", "sda"),
+ MPP_FUNCTION(0x3, "sd0", "d2"),
+ MPP_FUNCTION(0x4, "spi1", "mosi")),
+ MPP_MODE(52,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad13"),
+ MPP_FUNCTION(0x2, "i2c1", "sck"),
+ MPP_FUNCTION(0x3, "sd0", "d3"),
+ MPP_FUNCTION(0x4, "spi1", "sck")),
+ MPP_MODE(53,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad14"),
+ MPP_FUNCTION(0x2, "sd0", "clk"),
+ MPP_FUNCTION(0x3, "tdm", "pclk"),
+ MPP_FUNCTION(0x4, "spi0", "cs2"),
+ MPP_FUNCTION(0x5, "pcie", "clkreq1")),
+ MPP_MODE(54,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ad15"),
+ MPP_FUNCTION(0x3, "tdm", "dtx")),
+ MPP_MODE(55,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "cs1"),
+ MPP_FUNCTION(0x2, "uart1", "txd"),
+ MPP_FUNCTION(0x3, "tdm", "rst"),
+ MPP_FUNCTION(0x4, "sata1", "prsnt"),
+ MPP_FUNCTION(0x5, "sata0", "prsnt")),
+ MPP_MODE(56,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "cs2"),
+ MPP_FUNCTION(0x2, "uart1", "cts"),
+ MPP_FUNCTION(0x3, "uart0", "cts"),
+ MPP_FUNCTION(0x4, "spi0", "cs3"),
+ MPP_FUNCTION(0x5, "pcie", "clkreq0"),
+ MPP_FUNCTION(0x6, "spi1", "cs1")),
+ MPP_MODE(57,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "cs3"),
+ MPP_FUNCTION(0x2, "uart1", "rxd"),
+ MPP_FUNCTION(0x3, "tdm", "fsync"),
+ MPP_FUNCTION(0x4, "sata0", "prsnt"),
+ MPP_FUNCTION(0x5, "audio", "sdo")),
+ MPP_MODE(58,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "cs0"),
+ MPP_FUNCTION(0x2, "uart1", "rts"),
+ MPP_FUNCTION(0x3, "tdm", "int"),
+ MPP_FUNCTION(0x5, "audio", "extclk"),
+ MPP_FUNCTION(0x6, "uart0", "rts")),
+ MPP_MODE(59,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "ale0"),
+ MPP_FUNCTION(0x2, "uart1", "rts"),
+ MPP_FUNCTION(0x3, "uart0", "rts"),
+ MPP_FUNCTION(0x5, "audio", "bclk")),
+ MPP_MODE(60,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "ale1"),
+ MPP_FUNCTION(0x2, "uart1", "rxd"),
+ MPP_FUNCTION(0x3, "sata0", "prsnt"),
+ MPP_FUNCTION(0x4, "pcie", "rst-out"),
+ MPP_FUNCTION(0x5, "audio", "sdi")),
+ MPP_MODE(61,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "dev", "wen1"),
+ MPP_FUNCTION(0x2, "uart1", "txd"),
+ MPP_FUNCTION(0x5, "audio", "rclk")),
+ MPP_MODE(62,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "dev", "a2"),
+ MPP_FUNCTION(0x2, "uart1", "cts"),
+ MPP_FUNCTION(0x3, "tdm", "drx"),
+ MPP_FUNCTION(0x4, "pcie", "clkreq0"),
+ MPP_FUNCTION(0x5, "audio", "mclk"),
+ MPP_FUNCTION(0x6, "uart0", "cts")),
+ MPP_MODE(63,
+ MPP_FUNCTION(0x0, "gpo", NULL),
+ MPP_FUNCTION(0x1, "spi0", "sck"),
+ MPP_FUNCTION(0x2, "tclk", NULL)),
+ MPP_MODE(64,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "spi0", "miso"),
+ MPP_FUNCTION(0x2, "spi0-1", "cs1")),
+ MPP_MODE(65,
+ MPP_FUNCTION(0x0, "gpio", NULL),
+ MPP_FUNCTION(0x1, "spi0", "mosi"),
+ MPP_FUNCTION(0x2, "spi0-1", "cs2")),
+};
+
+static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
+
+static struct of_device_id armada_370_pinctrl_of_match[] __devinitdata = {
+ { .compatible = "marvell,mv88f6710-pinctrl" },
+ { },
+};
+
+static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
+ MPP_REG_CTRL(0, 65),
+};
+
+static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 32),
+ MPP_GPIO_RANGE(2, 64, 64, 2),
+};
+
+static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
+
+ soc->variant = 0; /* no variants for Armada 370 */
+ soc->controls = mv88f6710_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
+ soc->modes = mv88f6710_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
+ soc->gpioranges = mv88f6710_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
+
+ pdev->dev.platform_data = soc;
+
+ return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_370_pinctrl_remove(struct platform_device *pdev)
+{
+ return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_370_pinctrl_driver = {
+ .driver = {
+ .name = "armada-370-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(armada_370_pinctrl_of_match),
+ },
+ .probe = armada_370_pinctrl_probe,
+ .remove = __devexit_p(armada_370_pinctrl_remove),
+};
+
+module_platform_driver(armada_370_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <[email protected]>");
+MODULE_DESCRIPTION("Marvell Armada 370 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.10.4
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be
always selected by arch/arm/mach-mvebu/Kconfig
- use enum for kirkwood variants instead of defines
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pinctrl/marvell,kirkwood-pinctrl.txt | 279 ++++++++++++
drivers/pinctrl/Kconfig | 4 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-kirkwood.c | 462 ++++++++++++++++++++
4 files changed, 746 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
new file mode 100644
index 0000000..361bccb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+ "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+ "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6 6 sysrst(out), spi(mosi), ptp(trig)
+mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+ mii(col)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+ mii(crs)
+mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+ ptp-2(trig)
+mpp12 12 gpo, sdio(clk)
+mpp13 13 gpio, sdio(cmd), uart1(txd)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17 17 gpio, sdio(d3)
+mpp18 18 gpo, nand(io0)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, mii(rxerr)
+mpp21 21 gpio, audio(spdifi)
+mpp22 22 gpio, audio(spdifo)
+mpp23 23 gpio, audio(rmclk)
+mpp24 24 gpio, audio(bclk)
+mpp25 25 gpio, audio(sdo)
+mpp26 26 gpio, audio(lrclk)
+mpp27 27 gpio, audio(mclk)
+mpp28 28 gpio, audio(sdi)
+mpp29 29 gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6 6 sysrst(out), spi(mosi), ptp(trig)
+mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+ mii(col), mii-1(rxerr)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+ mii(crs), sata0(prsnt)
+mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+ ptp-2(trig), sata0(act)
+mpp12 12 gpo, sdio(clk)
+mpp13 13 gpio, sdio(cmd), uart1(txd)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17 17 gpio, sdio(d3), sata0(prsnt)
+mpp18 18 gpo, nand(io0)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, ge1(txd0)
+mpp21 21 gpio, ge1(txd1), sata0(act)
+mpp22 22 gpio, ge1(txd2)
+mpp23 23 gpio, ge1(txd3), sata0(prsnt)
+mpp24 24 gpio, ge1(rxd0)
+mpp25 25 gpio, ge1(rxd1)
+mpp26 26 gpio, ge1(rxd2)
+mpp27 27 gpio, ge1(rxd3)
+mpp28 28 gpio, ge1(col)
+mpp29 29 gpio, ge1(txclk)
+mpp30 30 gpio, ge1(rxclk)
+mpp31 31 gpio, ge1(rxclk)
+mpp32 32 gpio, ge1(txclko)
+mpp33 33 gpo, ge1(txclk)
+mpp34 34 gpio, ge1(txen)
+mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6 6 sysrst(out), spi(mosi), ptp(trig)
+mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+ mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+ mii(crs), sata0(prsnt)
+mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+ ptp-2(trig), sata0(act)
+mpp12 12 gpo, sdio(clk)
+mpp13 13 gpio, sdio(cmd), uart1(txd)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+ sata1(act)
+mpp17 17 gpio, sdio(d3), sata0(prsnt)
+mpp18 18 gpo, nand(io0)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+ sata1(act)
+mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+ audio(spdifo)
+mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+ sata1(prsnt)
+mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+ audio(bclk)
+mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33 33 gpo, ge1(txclk), tdm(drx)
+mpp34 34 gpio, ge1(txen), tdm(spi-cs1)
+mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6 6 sysrst(out), spi(mosi), ptp(trig)
+mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+ mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+ mii(crs), sata0(prsnt)
+mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+ ptp-2(trig), sata0(act)
+mpp12 12 gpio, sdio(clk)
+mpp13 13 gpio, sdio(cmd), uart1(txd)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+ sata1(act)
+mpp17 17 gpio, sdio(d3), sata0(prsnt)
+mpp18 18 gpo, nand(io0)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+ sata1(act)
+mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+ audio(spdifo)
+mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+ sata1(prsnt)
+mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+ audio(bclk)
+mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33 33 gpo, ge1(txclk), tdm(drx)
+mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45 45 gpio, ts(mp9), tdm(pclk)
+mpp46 46 gpio, ts(mp10), tdm(fs)
+mpp47 47 gpio, ts(mp11), tdm(drx)
+mpp48 48 gpio, ts(mp12), tdm(dtx)
+mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name pins functions
+================================================================================
+mpp0 0 gpio, nand(io2), spi(cs)
+mpp1 1 gpo, nand(io3), spi(mosi)
+mpp2 2 gpo, nand(io4), spi(sck)
+mpp3 3 gpo, nand(io5), spi(miso)
+mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6 6 sysrst(out), spi(mosi)
+mpp7 7 gpo, spi(cs), lcd(pwm)
+mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+ mii-1(rxerr), sata1(prsnt)
+mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+ sata0(prsnt)
+mpp10 10 gpo, spi(sck), uart0(txd), sata1(act)
+mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+ audio(spdifi), audio-1(sdi)
+mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+ spi(cs)
+mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+ sata1(act), lcd(extclk)
+mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18 18 gpo, nand(io0), pex(clkreq)
+mpp19 19 gpo, nand(io1)
+mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+ sata1(act), lcd(d0)
+mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+ audio(spdifo), lcd(d1)
+mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+ sata1(prsnt), lcd(d2)
+mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+ audio(bclk), lcd(d3)
+mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+ lcd(d4)
+mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+ lcd(d5)
+mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+ lcd(d6)
+mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+ lcd(d7)
+mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+ lcd(d8)
+mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+ lcd(d15)
+mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f15eba4..31c0bba 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -155,6 +155,10 @@ config PINCTRL_DOVE
bool
select PINCTRL_MVEBU
+config PINCTRL_KIRKWOOD
+ bool
+ select PINCTRL_MVEBU
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d1327df..3006294 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-kirkwood.c b/drivers/pinctrl/pinctrl-kirkwood.c
new file mode 100644
index 0000000..23f493a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-kirkwood.c
@@ -0,0 +1,462 @@
+/*
+ * Marvell Kirkwood pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V(f6180, f6190, f6192, f6281, f6282) \
+ ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
+ (f6281 << 3) | (f6282 << 4))
+
+enum kirkwood_variant {
+ VARIANT_MV88F6180 = V(1, 0, 0, 0, 0),
+ VARIANT_MV88F6190 = V(0, 1, 0, 0, 0),
+ VARIANT_MV88F6192 = V(0, 0, 1, 0, 0),
+ VARIANT_MV88F6281 = V(0, 0, 0, 1, 0),
+ VARIANT_MV88F6282 = V(0, 0, 0, 0, 1),
+};
+
+static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1))),
+ MPP_MODE(1,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1))),
+ MPP_MODE(2,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1))),
+ MPP_MODE(3,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1))),
+ MPP_MODE(4,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0))),
+ MPP_MODE(5,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))),
+ MPP_MODE(6,
+ MPP_VAR_FUNCTION(0x0, "sysrst", "out", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "spi", "mosi", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "ptp", "trig", V(1, 1, 1, 1, 0))),
+ MPP_MODE(7,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))),
+ MPP_MODE(8,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))),
+ MPP_MODE(9,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))),
+ MPP_MODE(10,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0))),
+ MPP_MODE(11,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1))),
+ MPP_MODE(12,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1))),
+ MPP_MODE(13,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))),
+ MPP_MODE(14,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))),
+ MPP_MODE(15,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1))),
+ MPP_MODE(16,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))),
+ MPP_MODE(17,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1))),
+ MPP_MODE(18,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1))),
+ MPP_MODE(19,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1))),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0))),
+ MPP_MODE(21,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1))),
+ MPP_MODE(22,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1))),
+ MPP_MODE(23,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1))),
+ MPP_MODE(24,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1))),
+ MPP_MODE(25,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1))),
+ MPP_MODE(26,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1))),
+ MPP_MODE(27,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1))),
+ MPP_MODE(28,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1))),
+ MPP_MODE(29,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1))),
+ MPP_MODE(30,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1))),
+ MPP_MODE(31,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1))),
+ MPP_MODE(32,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1))),
+ MPP_MODE(33,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1))),
+ MPP_MODE(34,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1))),
+ MPP_MODE(35,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1))),
+ MPP_MODE(36,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1))),
+ MPP_MODE(37,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1))),
+ MPP_MODE(38,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1))),
+ MPP_MODE(39,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1))),
+ MPP_MODE(40,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1))),
+ MPP_MODE(41,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1))),
+ MPP_MODE(42,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1))),
+ MPP_MODE(43,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1))),
+ MPP_MODE(44,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1))),
+ MPP_MODE(45,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1))),
+ MPP_MODE(46,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1))),
+ MPP_MODE(47,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))),
+ MPP_MODE(48,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1))),
+ MPP_MODE(49,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0)),
+ MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1)),
+ MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0)),
+ MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1)),
+ MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1))),
+};
+
+static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
+ MPP_REG_CTRL(0, 29),
+};
+
+static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 30),
+};
+
+static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
+ MPP_REG_CTRL(0, 35),
+};
+
+static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 4),
+};
+
+static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
+ MPP_REG_CTRL(0, 49),
+};
+
+static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 18),
+};
+
+static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
+ { .compatible = "marvell,88f6180-pinctrl",
+ .data = (void *)VARIANT_MV88F6180 },
+ { .compatible = "marvell,88f6190-pinctrl",
+ .data = (void *)VARIANT_MV88F6190 },
+ { .compatible = "marvell,88f6192-pinctrl",
+ .data = (void *)VARIANT_MV88F6192 },
+ { .compatible = "marvell,88f6281-pinctrl",
+ .data = (void *)VARIANT_MV88F6281 },
+ { .compatible = "marvell,88f6282-pinctrl",
+ .data = (void *)VARIANT_MV88F6282 },
+ { }
+};
+
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
+ const struct of_device_id *match =
+ of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+
+ if (match) {
+ soc->variant = (unsigned)match->data & 0xff;
+ switch (soc->variant) {
+ case VARIANT_MV88F6180:
+ soc->controls = mv88f6180_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f6180_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
+ break;
+ case VARIANT_MV88F6190:
+ case VARIANT_MV88F6192:
+ soc->controls = mv88f619x_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f619x_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
+ break;
+ case VARIANT_MV88F6281:
+ case VARIANT_MV88F6282:
+ soc->controls = mv88f628x_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f628x_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
+ break;
+ }
+ pdev->dev.platform_data = soc;
+ }
+ return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit kirkwood_pinctrl_remove(struct platform_device *pdev)
+{
+ return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver kirkwood_pinctrl_driver = {
+ .driver = {
+ .name = "kirkwood-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(kirkwood_pinctrl_of_match),
+ },
+ .probe = kirkwood_pinctrl_probe,
+ .remove = __devexit_p(kirkwood_pinctrl_remove),
+};
+
+module_platform_driver(kirkwood_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <[email protected]>");
+MODULE_DESCRIPTION("Marvell Kirkwood pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
The Armada XP evaluation board is based on the MV78460 Armava XP
SoC. Now that we have separate .dtsi files for the three different
SoCs of the Armada XP family, use the appropriate one as include for
the Armada XP evaluation board .dts file.
Signed-off-by: Thomas Petazzoni <[email protected]>
Acked-by: Linus Walleij <[email protected]>
---
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/armada-xp-db.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d..b1fc728 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
*/
/dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Evaluation Board";
- compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+ compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada 370 SoC.
Signed-off-by: Thomas Petazzoni <[email protected]>
Acked-by: Linus Walleij <[email protected]>
---
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/armada-370.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..875fcd8 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -31,5 +31,9 @@
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x100>;
};
+
+ pinctrl@d0018000 {
+ compatible = "marvell,mv88f6710-pinctrl";
+ };
};
};
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada XP SoCs.
Until now, the device tree representation considered the Armada XP as
a single SoC. But in fact, there are three different SoCs in the
Armada XP families, with different number of CPU cores, different
number of Ethernet interfaces... and different number of muxable pins
or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
the three SoCs of the Armada XP family. The current armada-xp-db.dts
evaluation board uses the MV78460 variant of the SoC.
Signed-off-by: Thomas Petazzoni <[email protected]>
Acked-by: Linus Walleij <[email protected]>
---
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 27 +++++++++++++++++++++++++++
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 27 +++++++++++++++++++++++++++
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 27 +++++++++++++++++++++++++++
3 files changed, 81 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 0000000..69ad287
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP family SoC";
+ compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ soc {
+ pinctrl@d0018000 {
+ compatible = "marvell,mv78230-pinctrl";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 0000000..0f38fa9
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP family SoC";
+ compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ soc {
+ pinctrl@d0018000 {
+ compatible = "marvell,mv78260-pinctrl";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 0000000..9e61836
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+ model = "Marvell Armada XP family SoC";
+ compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ soc {
+ pinctrl@d0018000 {
+ compatible = "marvell,mv78460-pinctrl";
+ };
+ };
+ };
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
The Armada 370 and XP SoCs have configurable muxing for a certain
number of their pins, controlled through a pinctrl driver.
The 'compatible' property is defined in the SoC-specific .dtsi files,
since the compatible string identifies the number of pins and other
SoC-specific properties.
Signed-off-by: Thomas Petazzoni <[email protected]>
Acked-by: Linus Walleij <[email protected]>
---
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/armada-370-xp.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 16cc82c..54a944a 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -68,6 +68,13 @@
compatible = "marvell,armada-addr-decoding-controller";
reg = <0xd0020000 0x258>;
};
+
+ pinctrl@d0018000 {
+ reg = <0xd0018000 0x38>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
};
};
--
1.7.10.4
From: Thomas Petazzoni <[email protected]>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
v2: replaced variant with enum and used bitops.h
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 100 +++++
drivers/pinctrl/Kconfig | 4 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-armada-xp.c | 468 ++++++++++++++++++++
4 files changed, 573 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
new file mode 100644
index 0000000..bfa0a2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+ "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name pins functions
+================================================================================
+mpp0 0 gpio, ge0(txclko), lcd(d0)
+mpp1 1 gpio, ge0(txd0), lcd(d1)
+mpp2 2 gpio, ge0(txd1), lcd(d2)
+mpp3 3 gpio, ge0(txd2), lcd(d3)
+mpp4 4 gpio, ge0(txd3), lcd(d4)
+mpp5 5 gpio, ge0(txctl), lcd(d5)
+mpp6 6 gpio, ge0(rxd0), lcd(d6)
+mpp7 7 gpio, ge0(rxd1), lcd(d7)
+mpp8 8 gpio, ge0(rxd2), lcd(d8)
+mpp9 9 gpio, ge0(rxd3), lcd(d9)
+mpp10 10 gpio, ge0(rxctl), lcd(d10)
+mpp11 11 gpio, ge0(rxclk), lcd(d11)
+mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30 30 gpio, tdm(int1), sd0(clk)
+mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36 36 gpio, spi(mosi)
+mpp37 37 gpio, spi(miso)
+mpp38 38 gpio, spi(sck)
+mpp39 39 gpio, spi(cs0)
+mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+ pcie(clkreq0)
+mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+ pcie(clkreq1)
+mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+ vdd(cpu0-pd)
+mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+ vdd(cpu2-3-pd){1}
+mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+ mem(bat)
+mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+ ref(clkout)
+mpp48 48 gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name pins functions
+================================================================================
+mpp49 49 gpio, dev(we3)
+mpp50 50 gpio, dev(we2)
+mpp51 51 gpio, dev(ad16)
+mpp52 52 gpio, dev(ad17)
+mpp53 53 gpio, dev(ad18)
+mpp54 54 gpio, dev(ad19)
+mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
+mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
+mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58 58 gpio, dev(ad23)
+mpp59 59 gpio, dev(ad24)
+mpp60 60 gpio, dev(ad25)
+mpp61 61 gpio, dev(ad26)
+mpp62 62 gpio, dev(ad27)
+mpp63 63 gpio, dev(ad28)
+mpp64 64 gpio, dev(ad29)
+mpp65 65 gpio, dev(ad30)
+mpp66 66 gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e16b8b0..a754144 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -163,6 +163,10 @@ config PINCTRL_ARMADA_370
bool
select PINCTRL_MVEBU
+config PINCTRL_ARMADA_XP
+ bool
+ select PINCTRL_MVEBU
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e6d6667..f2ea050 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-armada-xp.c b/drivers/pinctrl/pinctrl-armada-xp.c
new file mode 100644
index 0000000..40bd52a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-xp.c
@@ -0,0 +1,468 @@
+/*
+ * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file supports the three variants of Armada XP SoCs that are
+ * available: mv78230, mv78260 and mv78460. From a pin muxing
+ * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
+ * both have 67 MPP pins (more GPIOs and address lines for the memory
+ * bus mainly). The only difference between the mv78260 and the
+ * mv78460 in terms of pin muxing is the addition of two functions on
+ * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
+ * cores, mv78460 has four cores).
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/bitops.h>
+
+#include "pinctrl-mvebu.h"
+
+enum armada_xp_variant {
+ V_MV78230 = BIT(0),
+ V_MV78260 = BIT(1),
+ V_MV78460 = BIT(2),
+ V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460),
+ V_MV78260_PLUS = (V_MV78260 | V_MV78460),
+};
+
+static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txclko", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
+ MPP_MODE(1,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
+ MPP_MODE(2,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)),
+ MPP_MODE(3,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)),
+ MPP_MODE(4,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)),
+ MPP_MODE(5,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txctl", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)),
+ MPP_MODE(6,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)),
+ MPP_MODE(7,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)),
+ MPP_MODE(8,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)),
+ MPP_MODE(9,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)),
+ MPP_MODE(10,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxctl", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d10", V_MV78230_PLUS)),
+ MPP_MODE(11,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxclk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d11", V_MV78230_PLUS)),
+ MPP_MODE(12,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "clkout", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)),
+ MPP_MODE(13,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)),
+ MPP_MODE(14,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)),
+ MPP_MODE(15,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txd7", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txd2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d15", V_MV78230_PLUS)),
+ MPP_MODE(16,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)),
+ MPP_MODE(17,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)),
+ MPP_MODE(18,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxerr", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxd0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "ptp", "trig", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d18", V_MV78230_PLUS)),
+ MPP_MODE(19,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "crs", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxd1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "ptp", "evreq", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d19", V_MV78230_PLUS)),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd4", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxd2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "ptp", "clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d20", V_MV78230_PLUS)),
+ MPP_MODE(21,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "mem", "bat", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)),
+ MPP_MODE(22,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd6", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxctl", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "sata0", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d22", V_MV78230_PLUS)),
+ MPP_MODE(23,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ge0", "rxd7", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "d23", V_MV78230_PLUS)),
+ MPP_MODE(24,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)),
+ MPP_MODE(25,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)),
+ MPP_MODE(26,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
+ MPP_MODE(27,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "dtx", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "e", V_MV78230_PLUS)),
+ MPP_MODE(28,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ptp", "evreq", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "drx", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "pwm", V_MV78230_PLUS)),
+ MPP_MODE(29,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
+ MPP_MODE(30,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int1", V_MV78230_PLUS)),
+ MPP_MODE(31,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
+ MPP_MODE(32,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
+ MPP_MODE(33,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS)),
+ MPP_MODE(34,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS)),
+ MPP_MODE(35,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sata1", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)),
+ MPP_MODE(36,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "mosi", V_MV78230_PLUS)),
+ MPP_MODE(37,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "miso", V_MV78230_PLUS)),
+ MPP_MODE(38,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "sck", V_MV78230_PLUS)),
+ MPP_MODE(39,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "cs0", V_MV78230_PLUS)),
+ MPP_MODE(40,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)),
+ MPP_MODE(41,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)),
+ MPP_MODE(42,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
+ MPP_MODE(43,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)),
+ MPP_MODE(44,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)),
+ MPP_MODE(45,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs5", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)),
+ MPP_MODE(46,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs6", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)),
+ MPP_MODE(47,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x3, "spi", "cs7", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)),
+ MPP_MODE(48,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS),
+ MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)),
+ MPP_MODE(49,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)),
+ MPP_MODE(50,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "we2", V_MV78260_PLUS)),
+ MPP_MODE(51,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad16", V_MV78260_PLUS)),
+ MPP_MODE(52,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad17", V_MV78260_PLUS)),
+ MPP_MODE(53,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad18", V_MV78260_PLUS)),
+ MPP_MODE(54,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),
+ MPP_MODE(55,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)),
+ MPP_MODE(56,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)),
+ MPP_MODE(57,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)),
+ MPP_MODE(58,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),
+ MPP_MODE(59,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad24", V_MV78260_PLUS)),
+ MPP_MODE(60,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad25", V_MV78260_PLUS)),
+ MPP_MODE(61,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad26", V_MV78260_PLUS)),
+ MPP_MODE(62,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad27", V_MV78260_PLUS)),
+ MPP_MODE(63,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad28", V_MV78260_PLUS)),
+ MPP_MODE(64,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad29", V_MV78260_PLUS)),
+ MPP_MODE(65,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad30", V_MV78260_PLUS)),
+ MPP_MODE(66,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)),
+};
+
+static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
+
+static struct of_device_id armada_xp_pinctrl_of_match[] __devinitdata = {
+ {
+ .compatible = "marvell,mv78230-pinctrl",
+ .data = (void *) V_MV78230,
+ },
+ {
+ .compatible = "marvell,mv78260-pinctrl",
+ .data = (void *) V_MV78260,
+ },
+ {
+ .compatible = "marvell,mv78460-pinctrl",
+ .data = (void *) V_MV78460,
+ },
+ { },
+};
+
+static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
+ MPP_REG_CTRL(0, 48),
+};
+
+static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 17),
+};
+
+static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
+ MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 32),
+ MPP_GPIO_RANGE(2, 64, 64, 3),
+};
+
+static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
+ MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 32),
+ MPP_GPIO_RANGE(2, 64, 64, 3),
+};
+
+static int __devinit armada_xp_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
+ const struct of_device_id *match =
+ of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
+
+ if (!match)
+ return -ENODEV;
+
+ soc->variant = (unsigned) match->data & 0xff;
+
+ switch (soc->variant) {
+ case V_MV78230:
+ soc->controls = mv78230_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
+ soc->modes = armada_xp_mpp_modes;
+ /* We don't necessarily want the full list of the
+ * armada_xp_mpp_modes, but only the first 'n' ones
+ * that are available on this SoC */
+ soc->nmodes = mv78230_mpp_controls[0].npins;
+ soc->gpioranges = mv78230_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
+ break;
+ case V_MV78260:
+ soc->controls = mv78260_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
+ soc->modes = armada_xp_mpp_modes;
+ /* We don't necessarily want the full list of the
+ * armada_xp_mpp_modes, but only the first 'n' ones
+ * that are available on this SoC */
+ soc->nmodes = mv78260_mpp_controls[0].npins;
+ soc->gpioranges = mv78260_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
+ break;
+ case V_MV78460:
+ soc->controls = mv78460_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
+ soc->modes = armada_xp_mpp_modes;
+ /* We don't necessarily want the full list of the
+ * armada_xp_mpp_modes, but only the first 'n' ones
+ * that are available on this SoC */
+ soc->nmodes = mv78460_mpp_controls[0].npins;
+ soc->gpioranges = mv78460_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
+ break;
+ }
+
+ pdev->dev.platform_data = soc;
+
+ return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_xp_pinctrl_remove(struct platform_device *pdev)
+{
+ return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_xp_pinctrl_driver = {
+ .driver = {
+ .name = "armada-xp-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(armada_xp_pinctrl_of_match),
+ },
+ .probe = armada_xp_pinctrl_probe,
+ .remove = __devexit_p(armada_xp_pinctrl_remove),
+};
+
+module_platform_driver(armada_xp_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <[email protected]>");
+MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.10.4
This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Thomas Petazzoni <[email protected]>
---
v2:
- restructured Kconfig to have a common PINCTRL_MVEBU that are selected by
SoC specific drivers.
- cleaned pinctrl-mvebu and replaced 'magic numbers' by defines
- make use of of_iomap instead of get_resource/ioremap
- extended include documentation and checked with scripts/kernel-doc
- cleaned devicetree binding documentation
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pinctrl/marvell,mvebu-pinctrl.txt | 45 ++
arch/arm/Kconfig | 1 +
drivers/pinctrl/Kconfig | 6 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-mvebu.c | 761 ++++++++++++++++++++
drivers/pinctrl/pinctrl-mvebu.h | 192 +++++
6 files changed, 1006 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
create mode 100644 drivers/pinctrl/pinctrl-mvebu.h
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
new file mode 100644
index 0000000..dc419e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -0,0 +1,45 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+ Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing a function to mux to for all
+ marvell,pins given in this pin configuration node. The function has to be
+ common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+ valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial@12100 {
+ compatible = "ns16550a";
+ reg = <0x12100 0x100>;
+ reg-shift = <2>;
+ interrupts = <7>;
+
+ pinctrl-0 = <&pmx_uart1_sw>;
+};
+
+pinctrl: pinctrl@d0200 {
+ compatible = "marvell,dove-pinctrl";
+ reg = <0xd0200 0x20>;
+
+ pmx_uart1_sw: pmx-uart1-sw {
+ marvell,pins = "mpp_uart1";
+ marvell,function = "uart1";
+ };
+};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a2b6f74..2eb3f6b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -574,6 +574,7 @@ config ARCH_MVEBU
select IRQ_DOMAIN
select COMMON_CLK
select PLAT_ORION
+ select PINCTRL
help
Support for the Marvell SoC Family with device tree support
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..20bfdc3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -145,6 +145,12 @@ config PINCTRL_COH901
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
ports of 8 GPIO pins each.
+config PINCTRL_MVEBU
+ bool
+ depends on ARCH_MVEBU
+ select PINMUX
+ select PINCONF
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..007ed32 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-mvebu.c b/drivers/pinctrl/pinctrl-mvebu.c
new file mode 100644
index 0000000..5397765
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.c
@@ -0,0 +1,761 @@
+/*
+ * Marvell MVEBU pinctrl core driver
+ *
+ * Authors: Sebastian Hesselbarth <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinctrl-mvebu.h"
+
+#define MPPS_PER_REG 8
+#define MPP_BITS 4
+#define MPP_MASK 0xf
+
+struct mvebu_pinctrl_function {
+ unsigned fid;
+ const char *name;
+ const char *setting;
+ const char **groups;
+ unsigned num_groups;
+};
+
+struct mvebu_pinctrl_group {
+ const char *name;
+ struct mvebu_mpp_ctrl *ctrl;
+ struct mvebu_mpp_ctrl_setting *settings;
+ unsigned num_settings;
+ unsigned gid;
+ unsigned *pins;
+ unsigned npins;
+};
+
+struct mvebu_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_desc desc;
+ void __iomem *base;
+ struct mvebu_pinctrl_group *groups;
+ unsigned num_groups;
+ struct mvebu_pinctrl_function *functions;
+ unsigned num_functions;
+ u8 variant;
+};
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
+ struct mvebu_pinctrl *pctl, unsigned pid)
+{
+ unsigned n;
+ for (n = 0; n < pctl->num_groups; n++) {
+ if (pid >= pctl->groups[n].pins[0] &&
+ pid < pctl->groups[n].pins[0] +
+ pctl->groups[n].npins)
+ return &pctl->groups[n];
+ }
+ return NULL;
+}
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
+ struct mvebu_pinctrl *pctl, const char *name)
+{
+ unsigned n;
+ for (n = 0; n < pctl->num_groups; n++) {
+ if (strcmp(name, pctl->groups[n].name) == 0)
+ return &pctl->groups[n];
+ }
+ return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
+ struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+ unsigned long config)
+{
+ unsigned n;
+ for (n = 0; n < grp->num_settings; n++) {
+ if (config == grp->settings[n].val) {
+ if (!pctl->variant || (pctl->variant &
+ grp->settings[n].variant))
+ return &grp->settings[n];
+ }
+ }
+ return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
+ struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+ const char *name)
+{
+ unsigned n;
+ for (n = 0; n < grp->num_settings; n++) {
+ if (strcmp(name, grp->settings[n].name) == 0) {
+ if (!pctl->variant || (pctl->variant &
+ grp->settings[n].variant))
+ return &grp->settings[n];
+ }
+ }
+ return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
+ struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
+{
+ unsigned n;
+ for (n = 0; n < grp->num_settings; n++) {
+ if (grp->settings[n].flags &
+ (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+ if (!pctl->variant || (pctl->variant &
+ grp->settings[n].variant))
+ return &grp->settings[n];
+ }
+ }
+ return NULL;
+}
+
+struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
+ struct mvebu_pinctrl *pctl, const char *name)
+{
+ unsigned n;
+ for (n = 0; n < pctl->num_functions; n++) {
+ if (strcmp(name, pctl->functions[n].name) == 0)
+ return &pctl->functions[n];
+ }
+ return NULL;
+}
+
+/*
+ * Common mpp pin configuration registers on MVEBU are
+ * registers of eight 4-bit values for each mpp setting.
+ * Register offset and bit mask are calculated accordingly below.
+ */
+static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
+ struct mvebu_pinctrl_group *grp,
+ unsigned long *config)
+{
+ unsigned pin = grp->gid;
+ unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
+ unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
+
+ *config = readl(pctl->base + off);
+ *config >>= shift;
+ *config &= MPP_MASK;
+
+ return 0;
+}
+
+static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
+ struct mvebu_pinctrl_group *grp,
+ unsigned long config)
+{
+ unsigned pin = grp->gid;
+ unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
+ unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
+ unsigned long reg;
+
+ reg = readl(pctl->base + off);
+ reg &= ~(MPP_MASK << shift);
+ reg |= (config << shift);
+ writel(reg, pctl->base + off);
+
+ return 0;
+}
+
+static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned gid, unsigned long *config)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+ if (!grp->ctrl)
+ return -EINVAL;
+
+ if (grp->ctrl->mpp_get)
+ return grp->ctrl->mpp_get(grp->ctrl, config);
+
+ return mvebu_common_mpp_get(pctl, grp, config);
+}
+
+static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned gid, unsigned long config)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+ if (!grp->ctrl)
+ return -EINVAL;
+
+ if (grp->ctrl->mpp_set)
+ return grp->ctrl->mpp_set(grp->ctrl, config);
+
+ return mvebu_common_mpp_set(pctl, grp, config);
+}
+
+static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned gid)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+ struct mvebu_mpp_ctrl_setting *curr;
+ unsigned long config;
+ unsigned n;
+
+ if (mvebu_pinconf_group_get(pctldev, gid, &config))
+ return;
+
+ curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
+
+ if (curr) {
+ seq_printf(s, "current: %s", curr->name);
+ if (curr->subname)
+ seq_printf(s, "(%s)", curr->subname);
+ if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+ seq_printf(s, "(");
+ if (curr->flags & MVEBU_SETTING_GPI)
+ seq_printf(s, "i");
+ if (curr->flags & MVEBU_SETTING_GPO)
+ seq_printf(s, "o");
+ seq_printf(s, ")");
+ }
+ } else
+ seq_printf(s, "current: UNKNOWN");
+
+ if (grp->num_settings > 1) {
+ seq_printf(s, ", available = [");
+ for (n = 0; n < grp->num_settings; n++) {
+ if (curr == &grp->settings[n])
+ continue;
+
+ /* skip unsupported settings for this variant */
+ if (pctl->variant &&
+ !(pctl->variant & grp->settings[n].variant))
+ continue;
+
+ seq_printf(s, " %s", grp->settings[n].name);
+ if (grp->settings[n].subname)
+ seq_printf(s, "(%s)", grp->settings[n].subname);
+ if (grp->settings[n].flags &
+ (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+ seq_printf(s, "(");
+ if (grp->settings[n].flags & MVEBU_SETTING_GPI)
+ seq_printf(s, "i");
+ if (grp->settings[n].flags & MVEBU_SETTING_GPO)
+ seq_printf(s, "o");
+ seq_printf(s, ")");
+ }
+ }
+ seq_printf(s, " ]");
+ }
+ return;
+}
+
+struct pinconf_ops mvebu_pinconf_ops = {
+ .pin_config_group_get = mvebu_pinconf_group_get,
+ .pin_config_group_set = mvebu_pinconf_group_set,
+ .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
+};
+
+static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->num_functions;
+}
+
+static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned fid)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->functions[fid].name;
+}
+
+static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctl->functions[fid].groups;
+ *num_groups = pctl->functions[fid].num_groups;
+ return 0;
+}
+
+static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
+ unsigned gid)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_function *func = &pctl->functions[fid];
+ struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+ struct mvebu_mpp_ctrl_setting *setting;
+ int ret;
+
+ setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
+ func->setting);
+ if (!setting) {
+ dev_err(pctl->dev,
+ "unable to find setting %s in group %s\n",
+ func->setting, func->groups[gid]);
+ return -EINVAL;
+ }
+
+ ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+ if (ret) {
+ dev_err(pctl->dev, "cannot set group %s to %s\n",
+ func->groups[gid], func->setting);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp;
+ struct mvebu_mpp_ctrl_setting *setting;
+
+ grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+ if (!grp)
+ return -EINVAL;
+
+ if (grp->ctrl->mpp_gpio_req)
+ return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
+
+ setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+ if (!setting)
+ return -ENOTSUPP;
+
+ return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+}
+
+static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mvebu_pinctrl_group *grp;
+ struct mvebu_mpp_ctrl_setting *setting;
+
+ grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+ if (!grp)
+ return -EINVAL;
+
+ if (grp->ctrl->mpp_gpio_dir)
+ return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
+
+ setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+ if (!setting)
+ return -ENOTSUPP;
+
+ if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
+ (!input && (setting->flags & MVEBU_SETTING_GPO)))
+ return 0;
+
+ return -ENOTSUPP;
+}
+
+static struct pinmux_ops mvebu_pinmux_ops = {
+ .get_functions_count = mvebu_pinmux_get_funcs_count,
+ .get_function_name = mvebu_pinmux_get_func_name,
+ .get_function_groups = mvebu_pinmux_get_groups,
+ .gpio_request_enable = mvebu_pinmux_gpio_request_enable,
+ .gpio_set_direction = mvebu_pinmux_gpio_set_direction,
+ .enable = mvebu_pinmux_enable,
+};
+
+static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ return pctl->num_groups;
+}
+
+static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned gid)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ return pctl->groups[gid].name;
+}
+
+static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned gid, const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ *pins = pctl->groups[gid].pins;
+ *num_pins = pctl->groups[gid].npins;
+ return 0;
+}
+
+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned *num_maps)
+{
+ struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct property *prop;
+ const char *function;
+ const char *group;
+ int ret, nmaps, n;
+
+ *map = NULL;
+ *num_maps = 0;
+
+ ret = of_property_read_string(np, "marvell,function", &function);
+ if (ret) {
+ dev_err(pctl->dev,
+ "missing marvell,function in node %s\n", np->name);
+ return 0;
+ }
+
+ nmaps = of_property_count_strings(np, "marvell,pins");
+ if (nmaps < 0) {
+ dev_err(pctl->dev,
+ "missing marvell,pins in node %s\n", np->name);
+ return 0;
+ }
+
+ *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
+ if (map == NULL) {
+ dev_err(pctl->dev,
+ "cannot allocate pinctrl_map memory for %s\n",
+ np->name);
+ return -ENOMEM;
+ }
+
+ n = 0;
+ of_property_for_each_string(np, "marvell,pins", prop, group) {
+ struct mvebu_pinctrl_group *grp =
+ mvebu_pinctrl_find_group_by_name(pctl, group);
+
+ if (!grp) {
+ dev_err(pctl->dev, "unknown pin %s", group);
+ continue;
+ }
+
+ if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+ dev_err(pctl->dev, "unsupported function %s on pin %s",
+ function, group);
+ continue;
+ }
+
+ (*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)[n].data.mux.group = group;
+ (*map)[n].data.mux.function = np->name;
+ n++;
+ }
+
+ *num_maps = nmaps;
+
+ return 0;
+}
+
+static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ kfree(map);
+}
+
+static struct pinctrl_ops mvebu_pinctrl_ops = {
+ .get_groups_count = mvebu_pinctrl_get_groups_count,
+ .get_group_name = mvebu_pinctrl_get_group_name,
+ .get_group_pins = mvebu_pinctrl_get_group_pins,
+ .dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
+ .dt_free_map = mvebu_pinctrl_dt_free_map,
+};
+
+static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,
+ struct device_node *np, unsigned idx)
+{
+ struct mvebu_pinctrl_function *func = &pctl->functions[idx];
+ struct property *prop;
+ const char *setting;
+ const char *group;
+ unsigned n = 0;
+ int ret, num_groups;
+
+ ret = of_property_read_string(np, "marvell,function", &setting);
+ if (ret) {
+ dev_err(pctl->dev,
+ "missing marvell,function in node %s\n", np->name);
+ return -EINVAL;
+ }
+
+ num_groups = of_property_count_strings(np, "marvell,pins");
+ if (num_groups <= 0) {
+ dev_err(pctl->dev,
+ "missing marvell,pins in node %s\n", np->name);
+ return -EINVAL;
+ }
+
+ func->fid = idx;
+ func->name = np->name;
+ func->setting = setting;
+ func->num_groups = num_groups;
+ func->groups = devm_kzalloc(pctl->dev, num_groups * sizeof(char *),
+ GFP_KERNEL);
+ if (!func->groups) {
+ dev_err(pctl->dev,
+ "unable to alloc function groups\n");
+ return -ENOMEM;
+ }
+
+ of_property_for_each_string(np, "marvell,pins", prop, group) {
+ struct mvebu_pinctrl_group *grp =
+ mvebu_pinctrl_find_group_by_name(pctl, group);
+
+ if (!grp) {
+ dev_err(pctl->dev, "unknown pin %s", group);
+ return -EINVAL;
+ }
+
+ if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, setting)) {
+ dev_err(pctl->dev, "unsupported function %s on pin %s",
+ setting, group);
+ return -EINVAL;
+ }
+
+ func->groups[n++] = group;
+ }
+ return 0;
+}
+
+static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
+ struct mvebu_pinctrl *pctl)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct device_node *np;
+ unsigned nfuncs = 0, n = 0;
+ int ret;
+
+ if (!node)
+ return -ENODEV;
+
+ nfuncs = of_get_child_count(node);
+ if (nfuncs <= 0) {
+ dev_warn(pctl->dev, "no function defined in device node\n");
+ return 0;
+ }
+
+ pctl->num_functions = nfuncs;
+ pctl->functions = devm_kzalloc(&pdev->dev, nfuncs *
+ sizeof(struct mvebu_pinctrl_function),
+ GFP_KERNEL);
+ if (!pctl->functions) {
+ dev_err(pctl->dev, "unable to alloc functions\n");
+ return -ENOMEM;
+ }
+
+ for_each_child_of_node(node, np) {
+ ret = mvebu_pinctrl_dt_parse_function(pctl, np, n++);
+ if (ret) {
+ dev_warn(pctl->dev, "failed to parse function %s\n",
+ np->name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+int __devinit mvebu_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
+ struct device_node *np = pdev->dev.of_node;
+ struct mvebu_pinctrl *pctl;
+ void __iomem *base;
+ struct pinctrl_pin_desc *pdesc;
+ unsigned gid, n, k;
+ int ret;
+
+ if (!soc || !soc->controls || !soc->modes) {
+ dev_err(&pdev->dev, "wrong pinctrl soc info\n");
+ return -EINVAL;
+ }
+
+ base = of_iomap(np, 0);
+ if (!base) {
+ dev_err(&pdev->dev, "unable to get base address\n");
+ return -ENODEV;
+ }
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
+ GFP_KERNEL);
+ if (!pctl) {
+ dev_err(&pdev->dev, "unable to alloc driver\n");
+ return -ENOMEM;
+ }
+
+ pctl->desc.name = dev_name(&pdev->dev);
+ pctl->desc.owner = THIS_MODULE;
+ pctl->desc.pctlops = &mvebu_pinctrl_ops;
+ pctl->desc.pmxops = &mvebu_pinmux_ops;
+ pctl->desc.confops = &mvebu_pinconf_ops;
+ pctl->variant = soc->variant;
+ pctl->base = base;
+ pctl->dev = &pdev->dev;
+ platform_set_drvdata(pdev, pctl);
+
+ /* count controls and create names for mvebu generic
+ register controls; also does sanity checks */
+ pctl->num_groups = 0;
+ pctl->desc.npins = 0;
+ for (n = 0; n < soc->ncontrols; n++) {
+ struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+ char *names;
+
+ pctl->desc.npins += ctrl->npins;
+ /* initial control pins */
+ for (k = 0; k < ctrl->npins; k++)
+ ctrl->pins[k] = ctrl->pid + k;
+
+ /* special soc specific control */
+ if (ctrl->mpp_get || ctrl->mpp_set) {
+ if (!ctrl->name || !ctrl->mpp_set || !ctrl->mpp_set) {
+ dev_err(&pdev->dev, "wrong soc control info\n");
+ return -EINVAL;
+ }
+ pctl->num_groups += 1;
+ continue;
+ }
+
+ /* generic mvebu register control */
+ names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
+ if (!names) {
+ dev_err(&pdev->dev, "failed to alloc mpp names\n");
+ return -ENOMEM;
+ }
+ for (k = 0; k < ctrl->npins; k++)
+ sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
+ ctrl->name = names;
+ pctl->num_groups += ctrl->npins;
+ }
+
+ pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
+ sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
+ if (!pdesc) {
+ dev_err(&pdev->dev, "failed to alloc pinctrl pins\n");
+ return -ENOMEM;
+ }
+
+ for (n = 0; n < pctl->desc.npins; n++)
+ pdesc[n].number = n;
+ pctl->desc.pins = pdesc;
+
+ pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
+ sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
+ if (!pctl->groups) {
+ dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
+ return -ENOMEM;
+ }
+
+ /* assign mpp controls to groups */
+ gid = 0;
+ for (n = 0; n < soc->ncontrols; n++) {
+ struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+ pctl->groups[gid].gid = gid;
+ pctl->groups[gid].ctrl = ctrl;
+ pctl->groups[gid].name = ctrl->name;
+ pctl->groups[gid].pins = ctrl->pins;
+ pctl->groups[gid].npins = ctrl->npins;
+
+ /* generic mvebu register control maps to a number of groups */
+ if (!ctrl->mpp_get && !ctrl->mpp_set) {
+ pctl->groups[gid].npins = 1;
+
+ for (k = 1; k < ctrl->npins; k++) {
+ gid++;
+ pctl->groups[gid].gid = gid;
+ pctl->groups[gid].ctrl = ctrl;
+ pctl->groups[gid].name = &ctrl->name[8*k];
+ pctl->groups[gid].pins = &ctrl->pins[k];
+ pctl->groups[gid].npins = 1;
+ }
+ }
+ gid++;
+ }
+
+ /* assign mpp modes to groups */
+ for (n = 0; n < soc->nmodes; n++) {
+ struct mvebu_mpp_mode *mode = &soc->modes[n];
+ struct mvebu_pinctrl_group *grp =
+ mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
+ unsigned num_settings;
+
+ if (!grp) {
+ dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
+ mode->pid);
+ continue;
+ }
+
+ for (num_settings = 0; ;) {
+ struct mvebu_mpp_ctrl_setting *set =
+ &mode->settings[num_settings];
+
+ if (!set->name)
+ break;
+ num_settings++;
+
+ /* skip unsupported settings for this variant */
+ if (pctl->variant && !(pctl->variant & set->variant))
+ continue;
+
+ /* find gpio/gpo/gpi settings */
+ if (strcmp(set->name, "gpio") == 0)
+ set->flags = MVEBU_SETTING_GPI |
+ MVEBU_SETTING_GPO;
+ else if (strcmp(set->name, "gpo") == 0)
+ set->flags = MVEBU_SETTING_GPO;
+ else if (strcmp(set->name, "gpi") == 0)
+ set->flags = MVEBU_SETTING_GPI;
+ }
+
+ grp->settings = mode->settings;
+ grp->num_settings = num_settings;
+ }
+
+ ret = mvebu_pinctrl_dt_parse(pdev, pctl);
+ if (ret) {
+ /* look for pinmux functions in platform_device data */
+ dev_err(&pdev->dev, "unable to parse device tree\n");
+ return ret;
+ }
+
+ pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
+ if (!pctl->pctldev) {
+ dev_err(&pdev->dev, "unable to register pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ dev_info(&pdev->dev, "registered pinctrl driver\n");
+
+ /* register gpio ranges */
+ for (n = 0; n < soc->ngpioranges; n++)
+ pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
+
+ return 0;
+}
+
+int __devexit mvebu_pinctrl_remove(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl *pctl = platform_get_drvdata(pdev);
+ pinctrl_unregister(pctl->pctldev);
+ return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-mvebu.h b/drivers/pinctrl/pinctrl-mvebu.h
new file mode 100644
index 0000000..90bd3be
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.h
@@ -0,0 +1,192 @@
+/*
+ * Marvell MVEBU pinctrl driver
+ *
+ * Authors: Sebastian Hesselbarth <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_MVEBU_H__
+#define __PINCTRL_MVEBU_H__
+
+/**
+ * struct mvebu_mpp_ctrl - describe a mpp control
+ * @name: name of the control group
+ * @pid: first pin id handled by this control
+ * @npins: number of pins controlled by this control
+ * @mpp_get: (optional) special function to get mpp setting
+ * @mpp_set: (optional) special function to set mpp setting
+ * @mpp_gpio_req: (optional) special function to request gpio
+ * @mpp_gpio_dir: (optional) special function to set gpio direction
+ *
+ * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
+ * internal function, inside the SoC. Each muxable unit can be switched
+ * between two or more different settings, e.g. assign mpp pin 13 to
+ * uart1 or sata.
+ *
+ * If optional mpp_get/_set functions are set these are used to get/set
+ * a specific mode. Otherwise it is assumed that the mpp control is based
+ * on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir
+ * functions can be used to allow pin settings with varying gpio pins.
+ */
+struct mvebu_mpp_ctrl {
+ const char *name;
+ u8 pid;
+ u8 npins;
+ unsigned *pins;
+ int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
+ int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
+ int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
+ int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
+};
+
+/**
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
+ * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
+ * @subname: (optional) additional ctrl setting name, e.g. rts, cts
+ * @variant: (optional) variant identifier mask
+ * @flags: (private) flags to store gpi/gpo/gpio capabilities
+ *
+ * A ctrl_setting describes a specific internal mux function that a mpp pin
+ * can be switched to. The value (val) will be written in the corresponding
+ * register for common mpp pin configuration registers on MVEBU. SoC specific
+ * mpp_get/_set function may use val to distinguish between different settings.
+ *
+ * The name will be used to switch to this setting in DT description, e.g.
+ * marvell,function = "uart2". subname is only for debugging purposes.
+ *
+ * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
+ * parsed during initialization and stored in flags.
+ *
+ * The variant can be used to combine different revisions of one SoC to a
+ * common pinctrl driver. It is matched (AND) with variant of soc_info to
+ * determine if a setting is available on the current SoC revision.
+ */
+struct mvebu_mpp_ctrl_setting {
+ u8 val;
+ const char *name;
+ const char *subname;
+ u8 variant;
+ u8 flags;
+#define MVEBU_SETTING_GPO (1 << 0)
+#define MVEBU_SETTING_GPI (1 << 1)
+};
+
+/**
+ * struct mvebu_mpp_mode - link ctrl and settings
+ * @pid: first pin id handled by this mode
+ * @settings: list of settings available for this mode
+ *
+ * A mode connects all available settings with the corresponding mpp_ctrl
+ * given by pid.
+ */
+struct mvebu_mpp_mode {
+ u8 pid;
+ struct mvebu_mpp_ctrl_setting *settings;
+};
+
+/**
+ * struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu
+ * @variant: variant mask of soc_info
+ * @controls: list of available mvebu_mpp_ctrls
+ * @ncontrols: number of available mvebu_mpp_ctrls
+ * @modes: list of available mvebu_mpp_modes
+ * @nmodes: number of available mvebu_mpp_modes
+ * @gpioranges: list of pinctrl_gpio_ranges
+ * @ngpioranges: number of available pinctrl_gpio_ranges
+ *
+ * This struct describes all pinctrl related information for a specific SoC.
+ * If variant is unequal 0 it will be matched (AND) with variant of each
+ * setting and allows to distinguish between different revisions of one SoC.
+ */
+struct mvebu_pinctrl_soc_info {
+ u8 variant;
+ struct mvebu_mpp_ctrl *controls;
+ int ncontrols;
+ struct mvebu_mpp_mode *modes;
+ int nmodes;
+ struct pinctrl_gpio_range *gpioranges;
+ int ngpioranges;
+};
+
+#define MPP_REG_CTRL(_idl, _idh) \
+ { \
+ .name = NULL, \
+ .pid = _idl, \
+ .npins = _idh - _idl + 1, \
+ .pins = (unsigned[_idh - _idl + 1]) { }, \
+ .mpp_get = NULL, \
+ .mpp_set = NULL, \
+ .mpp_gpio_req = NULL, \
+ .mpp_gpio_dir = NULL, \
+ }
+
+#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \
+ { \
+ .name = _name, \
+ .pid = _idl, \
+ .npins = _idh - _idl + 1, \
+ .pins = (unsigned[_idh - _idl + 1]) { }, \
+ .mpp_get = _func ## _get, \
+ .mpp_set = _func ## _set, \
+ .mpp_gpio_req = NULL, \
+ .mpp_gpio_dir = NULL, \
+ }
+
+#define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \
+ { \
+ .name = _name, \
+ .pid = _idl, \
+ .npins = _idh - _idl + 1, \
+ .pins = (unsigned[_idh - _idl + 1]) { }, \
+ .mpp_get = _func ## _get, \
+ .mpp_set = _func ## _set, \
+ .mpp_gpio_req = _func ## _gpio_req, \
+ .mpp_gpio_dir = _func ## _gpio_dir, \
+ }
+
+#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
+ { \
+ .val = _val, \
+ .name = _name, \
+ .subname = _subname, \
+ .variant = _mask, \
+ .flags = 0, \
+ }
+
+#if defined(CONFIG_DEBUG_FS)
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
+ _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
+#else
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
+ _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
+#endif
+
+#define MPP_FUNCTION(_val, _name, _subname) \
+ MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
+
+#define MPP_MODE(_id, ...) \
+ { \
+ .pid = _id, \
+ .settings = (struct mvebu_mpp_ctrl_setting[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
+ { \
+ .name = "mvebu-gpio", \
+ .id = _id, \
+ .pin_base = _pinbase, \
+ .base = _gpiobase, \
+ .npins = _npins, \
+ }
+
+int mvebu_pinctrl_probe(struct platform_device *pdev);
+int mvebu_pinctrl_remove(struct platform_device *pdev);
+
+#endif
--
1.7.10.4
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be
always selected by arch/arm/mach-mvebu/Kconfig
- cleaned pinctrl-dove and replaced 'magic numbers' by defines
- use devm_clk_get for (now optional) pdma clock and add to required
properties in devicetree binding documentation
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pinctrl/marvell,dove-pinctrl.txt | 72 +++
drivers/pinctrl/Kconfig | 4 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-dove.c | 622 ++++++++++++++++++++
4 files changed, 699 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
create mode 100644 drivers/pinctrl/pinctrl-dove.c
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
new file mode 100644
index 0000000..a648aaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -0,0 +1,72 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+- clocks: (optional) phandle of pdma clock
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name pins functions
+================================================================================
+mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+ uart1(rts)
+mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+ uart1(cts), lcd-spi(cs1)
+mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8 8 gpio, pmu, watchdog(rstout)
+mpp9 9 gpio, pmu, pex1(clkreq)
+mpp10 10 gpio, pmu, ssp(sclk)
+mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+ sdio1(ledctrl), pex0(clkreq)
+mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+ ssp(extclk)
+mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+ ac97-1(sysclko)
+mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+ ac97(sysclko)
+mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+ uart1(cts), ssp(sfrm)
+mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+ lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+ lcd-spi(sck), ssp(sclk)
+mpp_camera 24-39 gpio, camera
+mpp_sdio0 40-45 gpio, sdio0
+mpp_sdio1 46-51 gpio, sdio1
+mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+ ssp/twsi
+mpp_spi0 58-61 gpio, spi0
+mpp_uart1 62-63 gpio, uart1
+mpp_nand 64-71 gpo, nand
+audio0 - i2s, ac97
+twsi - none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+ - gpio : gpio on pins 52-57
+ - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+ - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
+ - spdifo : spdifo on pin 57, gpio on pins 52-55
+ - twsi : twsi on pins 56,57, gpio on pins 52-55
+ - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
+ - ssp : ssp on pins 52-55, gpio on pins 56,57
+ - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+ audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 20bfdc3..f15eba4 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -151,6 +151,10 @@ config PINCTRL_MVEBU
select PINMUX
select PINCONF
+config PINCTRL_DOVE
+ bool
+ select PINCTRL_MVEBU
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 007ed32..d1327df 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c
new file mode 100644
index 0000000..cb31b63
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-dove.c
@@ -0,0 +1,622 @@
+/*
+ * Marvell Dove pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
+#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
+#define DOVE_AU0_AC97_SEL BIT(16)
+#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define DOVE_TWSI_ENABLE_OPTION1 BIT(7)
+#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define DOVE_TWSI_ENABLE_OPTION2 BIT(20)
+#define DOVE_TWSI_ENABLE_OPTION3 BIT(21)
+#define DOVE_TWSI_OPTION3_GPIO BIT(22)
+#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define DOVE_SSP_ON_AU1 BIT(0)
+#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1)
+#define DOVE_NAND_GPIO_EN BIT(0)
+#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
+#define DOVE_SPI_GPIO_SEL BIT(5)
+#define DOVE_UART1_GPIO_SEL BIT(4)
+#define DOVE_AU1_GPIO_SEL BIT(3)
+#define DOVE_CAM_GPIO_SEL BIT(2)
+#define DOVE_SD1_GPIO_SEL BIT(1)
+#define DOVE_SD0_GPIO_SEL BIT(0)
+
+#define MPPS_PER_REG 8
+#define MPP_BITS 4
+#define MPP_MASK 0xf
+
+#define CONFIG_PMU BIT(4)
+
+static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
+ unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
+ unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+ unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+ if (pmu & (1 << ctrl->pid))
+ *config = CONFIG_PMU;
+ else
+ *config = (mpp >> shift) & MPP_MASK;
+ return 0;
+}
+
+static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
+ unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
+ unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+ unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+ if (config == CONFIG_PMU)
+ writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+ else {
+ writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+ mpp &= ~(MPP_MASK << shift);
+ mpp |= config << shift;
+ writel(mpp, DOVE_MPP_VIRT_BASE + off);
+ }
+ return 0;
+}
+
+static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ unsigned long mask;
+
+ switch (ctrl->pid) {
+ case 24: /* mpp_camera */
+ mask = DOVE_CAM_GPIO_SEL;
+ break;
+ case 40: /* mpp_sdio0 */
+ mask = DOVE_SD0_GPIO_SEL;
+ break;
+ case 46: /* mpp_sdio1 */
+ mask = DOVE_SD1_GPIO_SEL;
+ break;
+ case 58: /* mpp_spi0 */
+ mask = DOVE_SPI_GPIO_SEL;
+ break;
+ case 62: /* mpp_uart1 */
+ mask = DOVE_UART1_GPIO_SEL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *config = ((mpp4 & mask) != 0);
+
+ return 0;
+}
+
+static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ unsigned long mask;
+
+ switch (ctrl->pid) {
+ case 24: /* mpp_camera */
+ mask = DOVE_CAM_GPIO_SEL;
+ break;
+ case 40: /* mpp_sdio0 */
+ mask = DOVE_SD0_GPIO_SEL;
+ break;
+ case 46: /* mpp_sdio1 */
+ mask = DOVE_SD1_GPIO_SEL;
+ break;
+ case 58: /* mpp_spi0 */
+ mask = DOVE_SPI_GPIO_SEL;
+ break;
+ case 62: /* mpp_uart1 */
+ mask = DOVE_UART1_GPIO_SEL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mpp4 &= ~mask;
+ if (config)
+ mpp4 |= mask;
+
+ writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+
+ return 0;
+}
+
+static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+ *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
+
+ return 0;
+}
+
+static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+ gmpp &= ~DOVE_NAND_GPIO_EN;
+ if (config)
+ gmpp |= DOVE_NAND_GPIO_EN;
+
+ writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+
+ return 0;
+}
+
+static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+ *config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
+
+ return 0;
+}
+
+static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+ pmu &= ~DOVE_AU0_AC97_SEL;
+ if (config)
+ pmu |= DOVE_AU0_AC97_SEL;
+ writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
+
+ return 0;
+}
+
+static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+ unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+ unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+ *config = 0;
+ if (mpp4 & DOVE_AU1_GPIO_SEL)
+ *config |= BIT(3);
+ if (sspc1 & DOVE_SSP_ON_AU1)
+ *config |= BIT(2);
+ if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
+ *config |= BIT(1);
+ if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
+ *config |= BIT(0);
+
+ /* SSP/TWSI only if I2S1 not set*/
+ if ((*config & BIT(3)) == 0)
+ *config &= ~(BIT(2) | BIT(0));
+ /* TWSI only if SPDIFO not set*/
+ if ((*config & BIT(1)) == 0)
+ *config &= ~BIT(0);
+ return 0;
+}
+
+static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+ unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+ unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+ if (config & BIT(0))
+ gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+ if (config & BIT(1))
+ gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
+ if (config & BIT(2))
+ sspc1 |= DOVE_SSP_ON_AU1;
+ if (config & BIT(3))
+ mpp4 |= DOVE_AU1_GPIO_SEL;
+
+ writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+ writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
+ writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+ writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+ return 0;
+}
+
+/* mpp[52:57] gpio pins depend heavily on current config;
+ * gpio_req does not try to mux in gpio capabilities to not
+ * break other functions. If you require all mpps as gpio
+ * enforce gpio setting by pinctrl mapping.
+ */
+static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
+{
+ unsigned long config;
+
+ dove_audio1_ctrl_get(ctrl, &config);
+
+ switch (config) {
+ case 0x02: /* i2s1 : gpio[56:57] */
+ case 0x0e: /* ssp : gpio[56:57] */
+ if (pid >= 56)
+ return 0;
+ return -ENOTSUPP;
+ case 0x08: /* spdifo : gpio[52:55] */
+ case 0x0b: /* twsi : gpio[52:55] */
+ if (pid <= 55)
+ return 0;
+ return -ENOTSUPP;
+ case 0x0a: /* all gpio */
+ return 0;
+ /* 0x00 : i2s1/spdifo : no gpio */
+ /* 0x0c : ssp/spdifo : no gpio */
+ /* 0x0f : ssp/twsi : no gpio */
+ }
+ return -ENOTSUPP;
+}
+
+/* mpp[52:57] has gpio pins capable of in and out */
+static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
+ bool input)
+{
+ if (pid < 52 || pid > 57)
+ return -ENOTSUPP;
+ return 0;
+}
+
+static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long *config)
+{
+ unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+ unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+ *config = 0;
+ if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
+ *config = 1;
+ else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
+ *config = 2;
+ else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
+ *config = 3;
+
+ return 0;
+}
+
+static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+ unsigned long config)
+{
+ unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+ unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+ gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
+ gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+
+ switch (config) {
+ case 1:
+ gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+ break;
+ case 2:
+ gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+ break;
+ case 3:
+ gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+ break;
+ }
+
+ writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
+ writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+ return 0;
+}
+
+static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
+ MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
+ MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
+ MPP_REG_CTRL(16, 23),
+ MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
+ MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
+ MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
+ MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
+ MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
+ MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
+ MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
+ MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
+ MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
+};
+
+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "rts"),
+ MPP_FUNCTION(0x03, "sdio0", "cd"),
+ MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(1,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "cts"),
+ MPP_FUNCTION(0x03, "sdio0", "wp"),
+ MPP_FUNCTION(0x0f, "lcd1", "pwm"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(2,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "sata", "prsnt"),
+ MPP_FUNCTION(0x02, "uart2", "txd"),
+ MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+ MPP_FUNCTION(0x04, "uart1", "rts"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(3,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "sata", "act"),
+ MPP_FUNCTION(0x02, "uart2", "rxd"),
+ MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+ MPP_FUNCTION(0x04, "uart1", "cts"),
+ MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(4,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "rts"),
+ MPP_FUNCTION(0x03, "sdio1", "cd"),
+ MPP_FUNCTION(0x04, "spi1", "miso"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(5,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "cts"),
+ MPP_FUNCTION(0x03, "sdio1", "wp"),
+ MPP_FUNCTION(0x04, "spi1", "cs"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(6,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "txd"),
+ MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+ MPP_FUNCTION(0x04, "spi1", "mosi"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(7,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "rxd"),
+ MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+ MPP_FUNCTION(0x04, "spi1", "sck"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(8,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "watchdog", "rstout"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(9,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x05, "pex1", "clkreq"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(10,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x05, "ssp", "sclk"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(11,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "sata", "prsnt"),
+ MPP_FUNCTION(0x02, "sata-1", "act"),
+ MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+ MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+ MPP_FUNCTION(0x05, "pex0", "clkreq"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(12,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "sata", "act"),
+ MPP_FUNCTION(0x02, "uart2", "rts"),
+ MPP_FUNCTION(0x03, "audio0", "extclk"),
+ MPP_FUNCTION(0x04, "sdio1", "cd"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(13,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "cts"),
+ MPP_FUNCTION(0x03, "audio1", "extclk"),
+ MPP_FUNCTION(0x04, "sdio1", "wp"),
+ MPP_FUNCTION(0x05, "ssp", "extclk"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(14,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "txd"),
+ MPP_FUNCTION(0x04, "sdio1", "buspwr"),
+ MPP_FUNCTION(0x05, "ssp", "rxd"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(15,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "rxd"),
+ MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+ MPP_FUNCTION(0x05, "ssp", "sfrm"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),
+ MPP_MODE(16,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "rts"),
+ MPP_FUNCTION(0x03, "sdio0", "cd"),
+ MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
+ MPP_FUNCTION(0x05, "ac97", "sdi1")),
+ MPP_MODE(17,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
+ MPP_FUNCTION(0x02, "uart3", "cts"),
+ MPP_FUNCTION(0x03, "sdio0", "wp"),
+ MPP_FUNCTION(0x04, "twsi", "sda"),
+ MPP_FUNCTION(0x05, "ac97", "sdi2")),
+ MPP_MODE(18,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "txd"),
+ MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+ MPP_FUNCTION(0x04, "lcd0", "pwm"),
+ MPP_FUNCTION(0x05, "ac97", "sdi3")),
+ MPP_MODE(19,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart3", "rxd"),
+ MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+ MPP_FUNCTION(0x04, "twsi", "sck")),
+ MPP_MODE(20,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "ac97", "sysclko"),
+ MPP_FUNCTION(0x02, "lcd-spi", "miso"),
+ MPP_FUNCTION(0x03, "sdio1", "cd"),
+ MPP_FUNCTION(0x05, "sdio0", "cd"),
+ MPP_FUNCTION(0x06, "spi1", "miso")),
+ MPP_MODE(21,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "uart1", "rts"),
+ MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
+ MPP_FUNCTION(0x03, "sdio1", "wp"),
+ MPP_FUNCTION(0x04, "ssp", "sfrm"),
+ MPP_FUNCTION(0x05, "sdio0", "wp"),
+ MPP_FUNCTION(0x06, "spi1", "cs")),
+ MPP_MODE(22,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x01, "uart1", "cts"),
+ MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
+ MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+ MPP_FUNCTION(0x04, "ssp", "txd"),
+ MPP_FUNCTION(0x05, "sdio0", "buspwr"),
+ MPP_FUNCTION(0x06, "spi1", "mosi")),
+ MPP_MODE(23,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "lcd-spi", "sck"),
+ MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+ MPP_FUNCTION(0x04, "ssp", "sclk"),
+ MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
+ MPP_FUNCTION(0x06, "spi1", "sck")),
+ MPP_MODE(24,
+ MPP_FUNCTION(0x00, "camera", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(40,
+ MPP_FUNCTION(0x00, "sdio0", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(46,
+ MPP_FUNCTION(0x00, "sdio1", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(52,
+ MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
+ MPP_FUNCTION(0x02, "i2s1", NULL),
+ MPP_FUNCTION(0x08, "spdifo", NULL),
+ MPP_FUNCTION(0x0a, "gpio", NULL),
+ MPP_FUNCTION(0x0b, "twsi", NULL),
+ MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
+ MPP_FUNCTION(0x0e, "ssp", NULL),
+ MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
+ MPP_MODE(58,
+ MPP_FUNCTION(0x00, "spi0", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(62,
+ MPP_FUNCTION(0x00, "uart1", NULL),
+ MPP_FUNCTION(0x01, "gpio", NULL)),
+ MPP_MODE(64,
+ MPP_FUNCTION(0x00, "nand", NULL),
+ MPP_FUNCTION(0x01, "gpo", NULL)),
+ MPP_MODE(72,
+ MPP_FUNCTION(0x00, "i2s", NULL),
+ MPP_FUNCTION(0x01, "ac97", NULL)),
+ MPP_MODE(73,
+ MPP_FUNCTION(0x00, "none", NULL),
+ MPP_FUNCTION(0x01, "opt1", NULL),
+ MPP_FUNCTION(0x02, "opt2", NULL),
+ MPP_FUNCTION(0x03, "opt3", NULL)),
+};
+
+static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+ MPP_GPIO_RANGE(1, 32, 32, 32),
+ MPP_GPIO_RANGE(2, 64, 64, 8),
+};
+
+static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
+ .controls = dove_mpp_controls,
+ .ncontrols = ARRAY_SIZE(dove_mpp_controls),
+ .modes = dove_mpp_modes,
+ .nmodes = ARRAY_SIZE(dove_mpp_modes),
+ .gpioranges = dove_mpp_gpio_ranges,
+ .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
+ .variant = 0,
+};
+
+static struct clk *clk;
+
+static struct of_device_id dove_pinctrl_of_match[] __devinitdata = {
+ { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
+ { }
+};
+
+static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match =
+ of_match_device(dove_pinctrl_of_match, &pdev->dev);
+
+ if (match)
+ pdev->dev.platform_data = match->data;
+
+ /*
+ * General MPP Configuration Register is part of pdma registers.
+ * grab clk to make sure it is ticking.
+ */
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (!IS_ERR(clk))
+ clk_prepare_enable(clk);
+
+ return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = mvebu_pinctrl_remove(pdev);
+ if (!IS_ERR(clk))
+ clk_disable_unprepare(clk);
+ return ret;
+}
+
+static struct platform_driver dove_pinctrl_driver = {
+ .driver = {
+ .name = "dove-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(dove_pinctrl_of_match),
+ },
+ .probe = dove_pinctrl_probe,
+ .remove = __devexit_p(dove_pinctrl_remove),
+};
+
+module_platform_driver(dove_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <[email protected]>");
+MODULE_DESCRIPTION("Marvell Dove pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
1.7.10.4
On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
> This patch adds a pinctrl driver core for Marvell SoCs plus DT
> binding documentation. This core driver will be used by SoC family
> specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
This, and all the other binding documents in this series, all look sane
to me.
> +++ b/drivers/pinctrl/pinctrl-mvebu.c
> +static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
> + of_property_for_each_string(np, "marvell,pins", prop, group) {
> + struct mvebu_pinctrl_group *grp =
> + mvebu_pinctrl_find_group_by_name(pctl, group);
> +
> + if (!grp) {
> + dev_err(pctl->dev, "unknown pin %s", group);
> + continue;
> + }
> +
> + if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
> + dev_err(pctl->dev, "unsupported function %s on pin %s",
> + function, group);
> + continue;
> + }
The error-checking here isn't strictly necessary; the pinctrl core will
error-check all the names if/when the map entries are used. So, you
could probably get away with just assigning the pin/function names
directly into (*map) and hence remove some code here. Still, it's not a
big deal either way.
> +static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,
> +static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
> + struct mvebu_pinctrl *pctl)
I don't understand what those two functions do, or a good chunk of
probe(). It seems like they're setting up the ability to get/set pin
configrations in addition to pin muxing, although if that's so, it seems
odd that none of the binding documents specify any way of controlling
pin configuration from device tree. Are you expecting drivers to call
APIs such as pin_config_set() directly, rather than controlling pin
config through DT?
On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
> This commits adds the necessary device tree information to define the
> compatible property for the pinctrl driver instance of Armada XP SoCs.
>
> Until now, the device tree representation considered the Armada XP as
> a single SoC. But in fact, there are three different SoCs in the
> Armada XP families, with different number of CPU cores, different
> number of Ethernet interfaces... and different number of muxable pins
> or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
> the three SoCs of the Armada XP family. The current armada-xp-db.dts
> evaluation board uses the MV78460 variant of the SoC.
> diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
> +/include/ "armada-xp.dtsi"
> +
> +/ {
> + model = "Marvell Armada XP family SoC";
> + compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
Since each of these files is specifically for a different SoC, I'd
expect them all to say something different in the model property?
> diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
> + model = "Marvell Armada XP family SoC";
> + compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
> diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
> + model = "Marvell Armada XP family SoC";
> + compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
> This commits adds the necessary device tree information to define the
> compatible property for the pinctrl driver instance of Armada 370 SoC.
> diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
> +
> + pinctrl@d0018000 {
> + compatible = "marvell,mv88f6710-pinctrl";
> + };
The indentation here is a mix of spaces and TABs.
On 8/22/12, Stephen Warren <[email protected]> wrote:
> On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
>> +++ b/drivers/pinctrl/pinctrl-mvebu.c
>
>> +static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
>
>> + of_property_for_each_string(np, "marvell,pins", prop, group) {
>> + struct mvebu_pinctrl_group *grp =
>> + mvebu_pinctrl_find_group_by_name(pctl, group);
>> +
>> + if (!grp) {
>> + dev_err(pctl->dev, "unknown pin %s", group);
>> + continue;
>> + }
>> +
>> + if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
>> + dev_err(pctl->dev, "unsupported function %s on pin %s",
>> + function, group);
>> + continue;
>> + }
>
> The error-checking here isn't strictly necessary; the pinctrl core will
> error-check all the names if/when the map entries are used. So, you
> could probably get away with just assigning the pin/function names
> directly into (*map) and hence remove some code here. Still, it's not a
> big deal either way.
Hi Stephen,
as these error checks are only performed once, I'd like to have them there
as they give hints when someone uses wrong marvell,pins/function names
in DT.
>> +static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl
>> *pctl,
>
>> +static int __devinit mvebu_pinctrl_dt_parse(struct platform_device
>> *pdev,
>> + struct mvebu_pinctrl *pctl)
>
> I don't understand what those two functions do, or a good chunk of
> probe(). It seems like they're setting up the ability to get/set pin
> configrations in addition to pin muxing, although if that's so, it seems
> odd that none of the binding documents specify any way of controlling
> pin configuration from device tree. Are you expecting drivers to call
> APIs such as pin_config_set() directly, rather than controlling pin
> config through DT?
probe() receives some structs from the SoC specific driver stubs that
describe, e.g. how many muxable pins are available, which pingroup they
belong to (marvell,pins), what valid register values are and how they are
named (marvell,function). Although, all mvebu SoC share a good part of
pinmux register layout, there are especially for dove some very different
ways to mux pins. As mvebu pinctrl is a true mux-only driver, i.e. no
pin drive strength or pin direction configuration, we decided not to have
single pins controlable but only pingroups even if they comprise only a
single pin.
dt_parse() and dt_parse_function() build up structs that get used later on
in mvebu_pinmux_ops that require indexed functions. I can join them with
dt_node_to_map() but that would require incremental kzalloc for the
corresponding array. Or I could (functionally) leave dt_parse() to allocate
the array and only join dt_parse_function() with dt_node_to_map().
There is an example of how to use pinctrl in marvell.mvebu-pinctrl.txt:
uart1: serial@12100 {
compatible = "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <7>;
pinctrl-0 = <&pmx_uart1_sw>;
};
pinctrl: pinctrl@d0200 {
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x20>;
pmx_uart1_sw: pmx-uart1-sw {
marvell,pins = "mpp_uart1";
marvell,function = "uart1";
};
};
In my understanding this will allow uart1 to switch the pingroup "mpp_uart1"
to the function "uart1". The pinctrl core driver is taking care of
translating mpp_uart1
to the corresponding pingroup and mvebu core driver of translating
uart1 into the required
register values to set the requested function. Is it so odd, that we
use names instead
of direct register values in DT? I agree, that maybe picking an example for dove
that is a little bit different in pingroup naming isn't the best
choice but it still gives
you an idea how to use it.
Consider this (virtual) example:
Muxing some SATA functions to pins 24 and 37 would require to set
register values
to 0x3 on pin 24 and 0x6 on pin 37. The proposed driver still allows
us to have a DT
description of
pmx_sata_example: pmx-sata-example {
marvell,pins = "mpp24", "mpp37";
marvell,function = "sata";
};
because the SoC specific driver passes function "sata" on pins 24 and
37 with the
corresponding register values. These are fed by the mvebu core driver
that builds
up all required pins, pingroups, and pinmux functions.
Sebastian
On 08/23/2012 03:45 AM, Sebastian Hesselbarth wrote:
> On 8/22/12, Stephen Warren <[email protected]> wrote:
>> On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
>>> +++ b/drivers/pinctrl/pinctrl-mvebu.c
>>
>>> +static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
>>
>>> + of_property_for_each_string(np, "marvell,pins", prop, group) {
>>> + struct mvebu_pinctrl_group *grp =
>>> + mvebu_pinctrl_find_group_by_name(pctl, group);
>>> +
>>> + if (!grp) {
>>> + dev_err(pctl->dev, "unknown pin %s", group);
>>> + continue;
>>> + }
>>> +
>>> + if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
>>> + dev_err(pctl->dev, "unsupported function %s on pin %s",
>>> + function, group);
>>> + continue;
>>> + }
>>
>> The error-checking here isn't strictly necessary; the pinctrl core will
>> error-check all the names if/when the map entries are used. So, you
>> could probably get away with just assigning the pin/function names
>> directly into (*map) and hence remove some code here. Still, it's not a
>> big deal either way.
>
> Hi Stephen,
>
> as these error checks are only performed once, I'd like to have them there
> as they give hints when someone uses wrong marvell,pins/function names
> in DT.
>
>>> +static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl
>>> *pctl,
>>
>>> +static int __devinit mvebu_pinctrl_dt_parse(struct platform_device
>>> *pdev,
>>> + struct mvebu_pinctrl *pctl)
>>
>> I don't understand what those two functions do, or a good chunk of
>> probe(). It seems like they're setting up the ability to get/set pin
>> configrations in addition to pin muxing, although if that's so, it seems
>> odd that none of the binding documents specify any way of controlling
>> pin configuration from device tree. Are you expecting drivers to call
>> APIs such as pin_config_set() directly, rather than controlling pin
>> config through DT?
>
> probe() receives some structs from the SoC specific driver stubs that
> describe, e.g. how many muxable pins are available, which pingroup they
> belong to (marvell,pins), what valid register values are and how they are
> named (marvell,function). Although, all mvebu SoC share a good part of
> pinmux register layout, there are especially for dove some very different
> ways to mux pins. As mvebu pinctrl is a true mux-only driver, i.e. no
> pin drive strength or pin direction configuration, we decided not to have
> single pins controlable but only pingroups even if they comprise only a
> single pin.
>
> dt_parse() and dt_parse_function() build up structs that get used later on
> in mvebu_pinmux_ops that require indexed functions. I can join them with
> dt_node_to_map() but that would require incremental kzalloc for the
> corresponding array. Or I could (functionally) leave dt_parse() to allocate
> the array and only join dt_parse_function() with dt_node_to_map().
So everything you said makes sense, in that the core driver is
parameterizable and receives data from a SoC-variant-specific driver
indicating which pins/groups/functions are available. I'm still not sure
though why the translation of the pin/group/function structures passed
to probe into other data structures requires accessing the DT at all;
the set of available pins/groups/functions isn't configured through DT,
and doesn't need to be limited to only those options actually used in
DT, so can't you just process all the data that's passed to probe
without interaction with the DT?
On 08/23/2012 07:54 PM, Stephen Warren wrote:
>> dt_parse() and dt_parse_function() build up structs that get used later on
>> in mvebu_pinmux_ops that require indexed functions. I can join them with
>> dt_node_to_map() but that would require incremental kzalloc for the
>> corresponding array. Or I could (functionally) leave dt_parse() to allocate
>> the array and only join dt_parse_function() with dt_node_to_map().
>
> So everything you said makes sense, in that the core driver is
> parameterizable and receives data from a SoC-variant-specific driver
> indicating which pins/groups/functions are available. I'm still not sure
> though why the translation of the pin/group/function structures passed
> to probe into other data structures requires accessing the DT at all;
> the set of available pins/groups/functions isn't configured through DT,
> and doesn't need to be limited to only those options actually used in
> DT, so can't you just process all the data that's passed to probe
> without interaction with the DT?
Hmm, maybe I still don't quite understand the terminology of pinctrl/pinmux
core completely. What exactly should mvebu_pinmux_get_funcs_count return
if not the number of DT node children?
I thought that a "function" in the terminology of pinctrl/pinmux core is
a list of pingroups and corresponding values to actually set it to e.g. uart1.
In pinctrl-mvebu this would be one marvell,function assigned to one or more
marvell,pins.
If the above is correct, I still need to access DT in probe() at least to count
the number of children passed to allocate an array for mvebu_pinmux_ops callbacks
that get indexed by "fid" (pctl->functions).
Sebastian
On 08/23/2012 02:31 PM, Sebastian Hesselbarth wrote:
> On 08/23/2012 07:54 PM, Stephen Warren wrote:
>>> dt_parse() and dt_parse_function() build up structs that get used
>>> later on
>>> in mvebu_pinmux_ops that require indexed functions. I can join them with
>>> dt_node_to_map() but that would require incremental kzalloc for the
>>> corresponding array. Or I could (functionally) leave dt_parse() to
>>> allocate
>>> the array and only join dt_parse_function() with dt_node_to_map().
>>
>> So everything you said makes sense, in that the core driver is
>> parameterizable and receives data from a SoC-variant-specific driver
>> indicating which pins/groups/functions are available. I'm still not sure
>> though why the translation of the pin/group/function structures passed
>> to probe into other data structures requires accessing the DT at all;
>> the set of available pins/groups/functions isn't configured through DT,
>> and doesn't need to be limited to only those options actually used in
>> DT, so can't you just process all the data that's passed to probe
>> without interaction with the DT?
>
> Hmm, maybe I still don't quite understand the terminology of pinctrl/pinmux
> core completely. What exactly should mvebu_pinmux_get_funcs_count return
> if not the number of DT node children?
In HW, you have:
* A number of pins
* In some cases, multiple pins are controlled by a single register
field, so there are groups of pins, whose pins all get mux'd at once.
* In some cases, SW chooses to control multiple pins at once even if the
HW allows otherwise, and these are also represented as groups.
* A (mux) function represents what options (signals, modules, ...) are
available to be mux'd onto any given pin or group of pins.
If all of your pins/groups can support 4 different mux choices 0..3
(even though the interpretation of values 0..3 may differ per pin/group)
you may simply have functions 0, 1, 2, 3 exposed by your driver.
Alternatively, you may define a function for each logical HW module
(e.g. UART1, UART2, SPI1, SPI2, MMC1...) that exists in your SoC, or
even per each separate subset of signals (e.g. UART1 RX/TX, UART 1
RTS/CTS, UART 2 RX/TX/RTS/CTS, ...).
In a driver where the set of pins, groups, and functions known to the
driver is defined as static data in the driver itself (which I believe
covers your driver; IIRC I saw all those tables in the patch), then
you'd simply count up all the defined function names/IDs available, and
return that from pinmux_ops.get_functions_count(). In this case, the
number of functions is entirely static, being defined by the SoC HW
design, and hence DT content has absolutely no impact on it. For
reference, this is how the Tegra pinctrl drivers work.
In a driver where the set of pins, groups, and functions known to the
driver is not hard-coded into the driver itself, but instead derived
from DT content (which is useful for a driver that works for say 10
different similar SoCs, each with slightly different sets of actual
pins/groups/functions, but where you don't want to hard-code all the
tables into the driver), then you may need to parse DT to extract the
definitions of those pins/groups/functions. Then, there's the question
of how to represent the set of known pins/groups/function in DT; do you
have explicit tables for this, or reverse engineer the tables based on
whichever pins/groups/function just happen to be used by the board
you're running on, in which cases the reverse-engineered lists will
probably not include all options the HW could support, given one
particular DT file. Anyway, as I said, I don't think this approach
applies to your driver anyway since IIRC I did see all the data tables
in the patch.
As you may have guessed, I strongly prefer the hard-coded static table
based approach, or at least separating the definition of known
pins/groups/functions from the configuration nodes that define which
particular mux settings to actually use.
Puting this all a little more simply, the pinctrl core wants to generate
a list of all known functions. It is a single global/unified list. It
first calls pinmux_ops.get_functions_count() to find out how many
functions there are in the list, then pinmux_ops.get_function_name() for
each one to find its name, then pinmux_ops.get_function_groups() to find
out which groups allow that function to be mux'd onto them.
On 08/23/2012 11:26 PM, Stephen Warren wrote:
> As you may have guessed, I strongly prefer the hard-coded static table
> based approach, or at least separating the definition of known
> pins/groups/functions from the configuration nodes that define which
> particular mux settings to actually use.
>
> Puting this all a little more simply, the pinctrl core wants to generate
> a list of all known functions. It is a single global/unified list. It
> first calls pinmux_ops.get_functions_count() to find out how many
> functions there are in the list, then pinmux_ops.get_function_name() for
> each one to find its name, then pinmux_ops.get_function_groups() to find
> out which groups allow that function to be mux'd onto them.
Ok, now this becomes a little bit more clear to me.
Consider uart1 on dove is muxable to:
mpp2 uart1(rts), mpp3 uart1(cts), mpp21 uart1(rts), mpp22 uart1(cts),
and finally mpp_uart1(rx and tx).
So possible, valid combinations for uart1 would be:
(a) mpp_uart1;
(b) mpp_uart1, mpp2, mpp3;
(c) mpp_uart1, mpp21, mpp22;
(d) mpp_uart1, mpp2, mpp22;
(e) mpp_uart1, mpp21, mpp3;
Now what we currently do is, use DT to setup all known functions with e.g.
marvell,pins = "mpp_uart1", "mpp2", "mpp22" and marvell,function = "uart1".
This requires to count all pinctrl DT node children to count the known
functions that can ever be muxed to. It will never allow to mux uart1 to sw
flow control during run-time when there was no DT child node for it.
But you are proposing to scan the list passed from SoC specific driver for all
possible marvell,function ("uart1", "uart2", "sdio0", ...) and build up lists
of pingroups that can be used with this specific marvell,function; or even build
up lists of pingroups that allow uart1(rts), and another one for uart1(cts), ...?
Sebastian
On 08/23/2012 05:01 PM, Sebastian Hesselbarth wrote:
> On 08/23/2012 11:26 PM, Stephen Warren wrote:
>> As you may have guessed, I strongly prefer the hard-coded static table
>> based approach, or at least separating the definition of known
>> pins/groups/functions from the configuration nodes that define which
>> particular mux settings to actually use.
>>
>> Puting this all a little more simply, the pinctrl core wants to generate
>> a list of all known functions. It is a single global/unified list. It
>> first calls pinmux_ops.get_functions_count() to find out how many
>> functions there are in the list, then pinmux_ops.get_function_name() for
>> each one to find its name, then pinmux_ops.get_function_groups() to find
>> out which groups allow that function to be mux'd onto them.
>
> Ok, now this becomes a little bit more clear to me.
>
> Consider uart1 on dove is muxable to:
> mpp2 uart1(rts), mpp3 uart1(cts), mpp21 uart1(rts), mpp22 uart1(cts),
> and finally mpp_uart1(rx and tx).
>
> So possible, valid combinations for uart1 would be:
> (a) mpp_uart1;
> (b) mpp_uart1, mpp2, mpp3;
> (c) mpp_uart1, mpp21, mpp22;
> (d) mpp_uart1, mpp2, mpp22;
> (e) mpp_uart1, mpp21, mpp3;
>
> Now what we currently do is, use DT to setup all known functions with e.g.
> marvell,pins = "mpp_uart1", "mpp2", "mpp22" and marvell,function = "uart1".
> This requires to count all pinctrl DT node children to count the known
> functions that can ever be muxed to. It will never allow to mux uart1 to sw
> flow control during run-time when there was no DT child node for it.
In the example above, there is a single function named "uart1". If this
was all the HW supported, I'd expect the driver's
pinmux_ops.get_functions_count() to return 1,
pinmux_ops.get_function_name(0) to return "uart1", and
pinmux_ops.get_function_name(n>0) to return an error.
In practice, I assume there are many other options that can be muxed
onto mpp2/3/21/22/uart1, so they'd be included in the list as well.
> But you are proposing to scan the list passed from SoC specific driver
> for all
> possible marvell,function ("uart1", "uart2", "sdio0", ...) and build up
> lists
> of pingroups that can be used with this specific marvell,function; or
> even build
> up lists of pingroups that allow uart1(rts), and another one for
> uart1(cts), ...?
I don't expect any scanning, no. I'd expect that tables provided by the
SoC-specific drivers to be:
* A table of pins
* A table of groups
* A table of functions
No scanning involved.
On Mon, Aug 20, 2012 at 11:09:51AM +0200, Linus Walleij wrote:
> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> <[email protected]> wrote:
>
> > This patch adds a pinctrl driver core for Marvell SoCs plus DT
> > binding documentation. This core driver will be used by SoC family
> > specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
>
> Thanks for dealing with this, much appreaciated!
>
> Are you taking this patch series through some Marvell tree or do you want
> me to carry it in the pinctrl tree?
Hi Linus
We can carry it thought the Marvell tree.
Andrew
On 08/24/2012 05:34 AM, Stephen Warren wrote:
> On 08/23/2012 05:01 PM, Sebastian Hesselbarth wrote:
>> So possible, valid combinations for uart1 would be:
>> (a) mpp_uart1;
>> (b) mpp_uart1, mpp2, mpp3;
>> (c) mpp_uart1, mpp21, mpp22;
>> (d) mpp_uart1, mpp2, mpp22;
>> (e) mpp_uart1, mpp21, mpp3;
>> [...]
> In the example above, there is a single function named "uart1". If this
> was all the HW supported, I'd expect the driver's
> pinmux_ops.get_functions_count() to return 1,
> pinmux_ops.get_function_name(0) to return "uart1", and
> pinmux_ops.get_function_name(n>0) to return an error.
>
> In practice, I assume there are many other options that can be muxed
> onto mpp2/3/21/22/uart1, so they'd be included in the list as well.
>
> I don't expect any scanning, no. I'd expect that tables provided by the
> SoC-specific drivers to be:
>
> * A table of pins
> * A table of groups
> * A table of functions
>
> No scanning involved.
Stephen,
now I do understand but in the current driver we pass pingroups associated
with the available functions, i.e. "mpp2" with "uart1", "uart2", "sdio0", aso.
IMHO for the above three functions it would be better to have functions associated
with the corresponding groups, i.e. "uart1" with "mpp_uart1", "mpp2", "mpp3", aso.
That would require some larger rework of the driver and therefore I just
wanted to make sure, that I hit your expectations/explanations.
Sebastian
On 08/25/2012 08:53 AM, Sebastian Hesselbarth wrote:
> On 08/24/2012 05:34 AM, Stephen Warren wrote:
>> On 08/23/2012 05:01 PM, Sebastian Hesselbarth wrote:
>>> So possible, valid combinations for uart1 would be:
>>> (a) mpp_uart1;
>>> (b) mpp_uart1, mpp2, mpp3;
>>> (c) mpp_uart1, mpp21, mpp22;
>>> (d) mpp_uart1, mpp2, mpp22;
>>> (e) mpp_uart1, mpp21, mpp3;
>>> [...]
>> In the example above, there is a single function named "uart1". If this
>> was all the HW supported, I'd expect the driver's
>> pinmux_ops.get_functions_count() to return 1,
>> pinmux_ops.get_function_name(0) to return "uart1", and
>> pinmux_ops.get_function_name(n>0) to return an error.
>>
>> In practice, I assume there are many other options that can be muxed
>> onto mpp2/3/21/22/uart1, so they'd be included in the list as well.
>>
>> I don't expect any scanning, no. I'd expect that tables provided by the
>> SoC-specific drivers to be:
>>
>> * A table of pins
>> * A table of groups
>> * A table of functions
>>
>> No scanning involved.
>
> Stephen,
>
> now I do understand but in the current driver we pass pingroups associated
> with the available functions, i.e. "mpp2" with "uart1", "uart2",
> "sdio0", aso.
> IMHO for the above three functions it would be better to have functions
> associated
> with the corresponding groups, i.e. "uart1" with "mpp_uart1", "mpp2",
> "mpp3", aso.
The pinctrl subsystem does expect a list of functions, and for each
function, a list of the groups where it can be selected. I admit that
when I think about this, it's slightly backward, since HW typically has
a list of pins/groups, and for each, a certain set of functions can be
selected. Oh well...
On 20/08/2012 06:49, Linus Walleij wrote:
> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> <[email protected]> wrote:
>
>> This patch adds a SoC specific pinctrl driver for Marvell Kirkwood
>> SoCs
>> plus DT binding documentation. This driver will use the mvebu
>> pinctrl
>> driver core.
>
> Thanks for working on Kirkwood. Love this platform.
>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index cd3d827..361f513 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
>> select GENERIC_CLOCKEVENTS
>> select NEED_MACH_IO_H
>> select PLAT_ORION
>> + select PINCTRL
>
> select PINCTRL_KIRKWOOD too I think.
> Then it's just automatic.
>
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> index e2427eb..1f84090 100644
>> --- a/drivers/pinctrl/Kconfig
>> +++ b/drivers/pinctrl/Kconfig
>> @@ -147,7 +147,7 @@ config PINCTRL_COH901
>>
>> config PINCTRL_MVEBU
>> bool "Marvell SoC pin controller drivers"
>> - depends on ARCH_MVEBU || ARCH_DOVE
>> + depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
>
> As stated elsewhere I think this should be
> depends on PLAT_ORION
>
>> +config PINCTRL_KIRKWOOD
>> + bool "Support for Marvell Kirkwood SoCs"
>> + depends on PINCTRL_MVEBU
>
> depends on ARCH_KIRKWOOD
> select PINCTRL_MVEBU
>
> (...)
>> diff --git a/drivers/pinctrl/pinctrl-kirkwood.c
>> b/drivers/pinctrl/pinctrl-kirkwood.c
>> +static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
>> +
>> +static struct of_device_id kirkwood_pinctrl_of_match[]
>> __devinitdata = {
>> + { .compatible = "marvell,88f6180-pinctrl",
>> + .data = (void
>> *)VARIANT_MV88F6180 },
>> + { .compatible = "marvell,88f6190-pinctrl",
>> + .data = (void
>> *)VARIANT_MV88F6190 },
>> + { .compatible = "marvell,88f6192-pinctrl",
>> + .data = (void
>> *)VARIANT_MV88F6192 },
>> + { .compatible = "marvell,88f6281-pinctrl",
>> + .data = (void
>> *)VARIANT_MV88F6281 },
>> + { .compatible = "marvell,88f6282-pinctrl",
>> + .data = (void
>> *)VARIANT_MV88F6282 },
>> + { }
>> +};
>
> I'm thinking this variant should maybe be an enum... unless it is
> strongly established somewhere in Orion/Marvell stuff.
>
>> +static int __devinit kirkwood_pinctrl_probe(struct platform_device
>> *pdev)
>> +{
>> + struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
>> + const struct of_device_id *match =
>> + of_match_device(kirkwood_pinctrl_of_match,
>> &pdev->dev);
>> +
>> + if (match) {
>> + soc->variant = (unsigned)match->data & 0xff;
>> + switch (soc->variant) {
>> + case VARIANT_MV88F6180:
>> + soc->controls = mv88f6180_mpp_controls;
>> + soc->ncontrols =
>> ARRAY_SIZE(mv88f6180_mpp_controls);
>> + soc->modes = mv88f6xxx_mpp_modes;
>> + soc->nmodes =
>> ARRAY_SIZE(mv88f6xxx_mpp_modes);
>> + soc->gpioranges = mv88f6180_gpio_ranges;
>> + soc->ngpioranges =
>> ARRAY_SIZE(mv88f6180_gpio_ranges);
>> + break;
>> + case VARIANT_MV88F6190:
>> + case VARIANT_MV88F6192:
>> + soc->controls = mv88f619x_mpp_controls;
>> + soc->ncontrols =
>> ARRAY_SIZE(mv88f619x_mpp_controls);
>> + soc->modes = mv88f6xxx_mpp_modes;
>> + soc->nmodes =
>> ARRAY_SIZE(mv88f6xxx_mpp_modes);
>> + soc->gpioranges = mv88f619x_gpio_ranges;
>> + soc->ngpioranges =
>> ARRAY_SIZE(mv88f619x_gpio_ranges);
>> + break;
>> + case VARIANT_MV88F6281:
>> + case VARIANT_MV88F6282:
>> + soc->controls = mv88f628x_mpp_controls;
>> + soc->ncontrols =
>> ARRAY_SIZE(mv88f628x_mpp_controls);
>> + soc->modes = mv88f6xxx_mpp_modes;
>> + soc->nmodes =
>> ARRAY_SIZE(mv88f6xxx_mpp_modes);
>> + soc->gpioranges = mv88f628x_gpio_ranges;
>> + soc->ngpioranges =
>> ARRAY_SIZE(mv88f628x_gpio_ranges);
>> + break;
>> + }
>> + pdev->dev.platform_data = soc;
>> + }
>> + return mvebu_pinctrl_probe(pdev);
>> +}
Why not have structures defining the soc-> parameters and use that in
the
of_match list?
--
Ben
On 08/27/2012 03:43 PM, Ben Dooks wrote:
> On 20/08/2012 06:49, Linus Walleij wrote:
>> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
>> <[email protected]> wrote:
>> (...)
>>> diff --git a/drivers/pinctrl/pinctrl-kirkwood.c
>>> b/drivers/pinctrl/pinctrl-kirkwood.c
>>> +static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
>>> +
>>> +static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata
>>> = {
>>> + { .compatible = "marvell,88f6180-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6180 },
>>> + { .compatible = "marvell,88f6190-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6190 },
>>> + { .compatible = "marvell,88f6192-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6192 },
>>> + { .compatible = "marvell,88f6281-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6281 },
>>> + { .compatible = "marvell,88f6282-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6282 },
>>> + { }
>>> +};
>>
>> I'm thinking this variant should maybe be an enum... unless it is
>> strongly established somewhere in Orion/Marvell stuff.
>>
>>> +static int __devinit kirkwood_pinctrl_probe(struct platform_device
>>> *pdev)
>>> +{
>>> + struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
>>> + const struct of_device_id *match =
>>> + of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
>>> +
>>> + if (match) {
>>> + soc->variant = (unsigned)match->data & 0xff;
>>> + switch (soc->variant) {
>>> + case VARIANT_MV88F6180:
>>> + soc->controls = mv88f6180_mpp_controls;
>>> + soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
>>> + soc->modes = mv88f6xxx_mpp_modes;
>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>> + soc->gpioranges = mv88f6180_gpio_ranges;
>>> + soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
>>> + break;
>>> + case VARIANT_MV88F6190:
>>> + case VARIANT_MV88F6192:
>>> + soc->controls = mv88f619x_mpp_controls;
>>> + soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
>>> + soc->modes = mv88f6xxx_mpp_modes;
>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>> + soc->gpioranges = mv88f619x_gpio_ranges;
>>> + soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
>>> + break;
>>> + case VARIANT_MV88F6281:
>>> + case VARIANT_MV88F6282:
>>> + soc->controls = mv88f628x_mpp_controls;
>>> + soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
>>> + soc->modes = mv88f6xxx_mpp_modes;
>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>> + soc->gpioranges = mv88f628x_gpio_ranges;
>>> + soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
>>> + break;
>>> + }
>>> + pdev->dev.platform_data = soc;
>>> + }
>>> + return mvebu_pinctrl_probe(pdev);
>>> +}
>
> Why not have structures defining the soc-> parameters and use that in the
> of_match list?
Ben,
functionally it is equivalent and IMHO using soc structs doesn't improve
readability here. I there any other good reason to have structs for each
soc?
Sebastian
On 08/27/2012 12:19 PM, Sebastian Hesselbarth wrote:
> On 08/27/2012 03:43 PM, Ben Dooks wrote:
>> On 20/08/2012 06:49, Linus Walleij wrote:
>>> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
>>> <[email protected]> wrote:
>>> (...)
>>>> diff --git a/drivers/pinctrl/pinctrl-kirkwood.c
>>>> b/drivers/pinctrl/pinctrl-kirkwood.c
>>>> +static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
>>>> +
>>>> +static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata
>>>> = {
>>>> + { .compatible = "marvell,88f6180-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6180 },
>>>> + { .compatible = "marvell,88f6190-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6190 },
>>>> + { .compatible = "marvell,88f6192-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6192 },
>>>> + { .compatible = "marvell,88f6281-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6281 },
>>>> + { .compatible = "marvell,88f6282-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6282 },
>>>> + { }
>>>> +};
>>>
>>> I'm thinking this variant should maybe be an enum... unless it is
>>> strongly established somewhere in Orion/Marvell stuff.
>>>
>>>> +static int __devinit kirkwood_pinctrl_probe(struct platform_device
>>>> *pdev)
>>>> +{
>>>> + struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
>>>> + const struct of_device_id *match =
>>>> + of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
>>>> +
>>>> + if (match) {
>>>> + soc->variant = (unsigned)match->data & 0xff;
>>>> + switch (soc->variant) {
>>>> + case VARIANT_MV88F6180:
>>>> + soc->controls = mv88f6180_mpp_controls;
>>>> + soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
>>>> + soc->modes = mv88f6xxx_mpp_modes;
>>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>>> + soc->gpioranges = mv88f6180_gpio_ranges;
>>>> + soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
>>>> + break;
>>>> + case VARIANT_MV88F6190:
>>>> + case VARIANT_MV88F6192:
>>>> + soc->controls = mv88f619x_mpp_controls;
>>>> + soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
>>>> + soc->modes = mv88f6xxx_mpp_modes;
>>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>>> + soc->gpioranges = mv88f619x_gpio_ranges;
>>>> + soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
>>>> + break;
>>>> + case VARIANT_MV88F6281:
>>>> + case VARIANT_MV88F6282:
>>>> + soc->controls = mv88f628x_mpp_controls;
>>>> + soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
>>>> + soc->modes = mv88f6xxx_mpp_modes;
>>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>>> + soc->gpioranges = mv88f628x_gpio_ranges;
>>>> + soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
>>>> + break;
>>>> + }
>>>> + pdev->dev.platform_data = soc;
>>>> + }
>>>> + return mvebu_pinctrl_probe(pdev);
>>>> +}
>>
>> Why not have structures defining the soc-> parameters and use that in the
>> of_match list?
>
> Ben,
>
> functionally it is equivalent and IMHO using soc structs doesn't improve
> readability here. I there any other good reason to have structs for each
> soc?
Well, it does change from 6 assignments down to one, and remove the need
for a switch statement - i.e. all of the code quoted above becomes just
roughly:
*soc = *match->data;