From: Sean Wang <[email protected]>
add dts nodes to MT7622 SoC and related rfb1 board
Ryder Lee (2):
arm64: dts: mt7622: add PCIe device nodes
arm64: dts: mt7622: add SATA device nodes
Sean Wang (10):
dt-bindings: clock: mediatek: add missing required #reset-cells
arm64: dts: mt7622: add clock controller device nodes
arm64: dts: mt7622: add power domain controller device nodes
arm64: dts: mt7622: add pinctrl related device nodes
arm64: dts: mt7622: add PMIC MT6380 related nodes
arm64: dts: mt7622: add cpufreq related device nodes
arm64: dts: mt7622: turn uart0 clock to real ones
arm64: dts: mt7622: add SoC and peripheral related device nodes
arm64: dts: mt7622: add flash related device nodes
arm64: dts: mt7622: add ethernet device nodes
.../bindings/arm/mediatek/mediatek,ethsys.txt | 2 +
.../bindings/arm/mediatek/mediatek,pciesys.txt | 2 +
.../bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 +
arch/arm64/boot/dts/mediatek/mt6380.dtsi | 91 ++++
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 337 +++++++++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 533 ++++++++++++++++++++-
6 files changed, 962 insertions(+), 5 deletions(-)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
--
2.7.4
From: Sean Wang <[email protected]>
All ethsys, pciesys and ssusbsys internally include reset controller, so
explicitly add back these missing cell definitions to related bindings
and examples.
Signed-off-by: Sean Wang <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Stephen Boyd <[email protected]>
---
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 2 ++
Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++
Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
3 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 7aa3fa1..8f5335b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -20,4 +21,5 @@ ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
index d5d5f12..7fe5dc6 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-pciesys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
index 00760019..b8184da 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-ssusbsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
--
2.7.4
From: Sean Wang <[email protected]>
add power domain controller nodes
Signed-off-by: Sean Wang <[email protected]>
Cc: Matthias Brugger <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 9730f0e..6fdc449 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h>
+#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/reset/mt7622-reset.h>
/ {
@@ -109,6 +110,20 @@
#reset-cells = <1>;
};
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt7622-scpsys",
+ "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_HIF_SEL>;
+ clock-names = "hif_sel";
+ };
+
sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt7622-sysirq",
"mediatek,mt6577-sysirq";
--
2.7.4
From: Ryder Lee <[email protected]>
This patch adds SATA support fot MT7622.
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Sean Wang <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 40 ++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 53d4efd..cafb860 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -325,6 +325,14 @@
status = "okay";
};
+&sata {
+ status = "okay";
+};
+
+&sata_phy {
+ status = "okay";
+};
+
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spic0_pins>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 2801b7d..f875f10 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/reset/mt7622-reset.h>
@@ -545,6 +546,45 @@
};
};
+ sata: sata@1a200000 {
+ compatible = "mediatek,mt7622-ahci",
+ "mediatek,mtk-ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&sata_port PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ status = "disabled";
+ };
+
+ sata_phy: sata-phy@1a243000 {
+ compatible = "mediatek,generic-tphy-v1";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ sata_port: sata-phy@1a243000 {
+ reg = <0 0x1a243000 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_ETH_500M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7622-ethsys",
"syscon";
--
2.7.4
From: Ryder Lee <[email protected]>
This patch adds PCIe support fot MT7622.
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Sean Wang <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 10 ++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 76 ++++++++++++++++++++++++++++
2 files changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index d4609a1..53d4efd 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -54,6 +54,16 @@
};
};
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+
+ pcie@0,0 {
+ status = "okay";
+ };
+};
+
&pio {
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 04a047e..2801b7d 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -469,6 +469,82 @@
#reset-cells = <1>;
};
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>,
+ <0 0x1a143000 0 0x1000>,
+ <0 0x1a145000 0 0x1000>;
+ reg-names = "subsys", "port0", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+ <&pciesys CLK_PCIE_P1_MAC_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AUX_EN>,
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P0_AXI_EN>,
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
+ <&pciesys CLK_PCIE_P0_PIPE_EN>,
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+ "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+ "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+ status = "disabled";
+
+ pcie0: pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7622-ethsys",
"syscon";
--
2.7.4
From: Sean Wang <[email protected]>
add nodes for NOR flash, parallel Nand flash with error correction code
support.
Signed-off-by: Sean Wang <[email protected]>
Cc: RogerCC Lin <[email protected]>
Cc: Guochun Mao <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 23 +++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 34 ++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 3b2eacc..20b1160 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -235,6 +235,10 @@
};
};
+&bch {
+ status = "disabled";
+};
+
&btif {
status = "okay";
};
@@ -257,6 +261,25 @@
status = "okay";
};
+&nandc {
+ pinctrl-names = "default";
+ pinctrl-0 = <¶llel_nand_pins>;
+ status = "disabled";
+};
+
+&nor_flash {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_nor_pins>;
+ status = "disabled";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 681c87a..540d2fe 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -395,6 +395,40 @@
status = "disabled";
};
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt7622-nfc";
+ reg = <0 0x1100D000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ bch: ecc@1100e000 {
+ compatible = "mediatek,mt7622-ecc";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+
+ nor_flash: spi@11014000 {
+ compatible = "mediatek,mt7622-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x11014000 0 0xe0>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
spi1: spi@11016000 {
compatible = "mediatek,mt7622-spi";
reg = <0 0x11016000 0 0x100>;
--
2.7.4
From: Sean Wang <[email protected]>
Add clock controller nodes for MT7622 and include header for topckgen,
infracfg, pericfg, apmixedsys, ethsys, sgmiisys, pciesys and ssusbsys
for those devices nodes to be added afterwards.
In addition, provides an oscillator node for the source of PLLs and dummy
clock for PWARP to complement missing support of clock gate for the
wrapper circuit in the driver.
Signed-off-by: Sean Wang <[email protected]>
Cc: Stephen Boyd <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 76 ++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index b111fec..9730f0e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+#include <dt-bindings/reset/mt7622-reset.h>
/ {
compatible = "mediatek,mt7622";
@@ -48,6 +50,19 @@
clock-frequency = <280000000>;
};
+ pwrap_clk: dummy40m {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ };
+
+ clk25m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "clkxtal";
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
@@ -78,6 +93,22 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ infracfg: infracfg@10000000 {
+ compatible = "mediatek,mt7622-infracfg",
+ "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: pericfg@10002000 {
+ compatible = "mediatek,mt7622-pericfg",
+ "syscon";
+ reg = <0 0x10002000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt7622-sysirq",
"mediatek,mt6577-sysirq";
@@ -87,6 +118,20 @@
reg = <0 0x10200620 0 0x20>;
};
+ apmixedsys: apmixedsys@10209000 {
+ compatible = "mediatek,mt7622-apmixedsys",
+ "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: topckgen@10210000 {
+ compatible = "mediatek,mt7622-topckgen",
+ "syscon";
+ reg = <0 0x10210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
gic: interrupt-controller@10300000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -107,4 +152,35 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+ ssusbsys: ssusbsys@1a000000 {
+ compatible = "mediatek,mt7622-ssusbsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pciesys: pciesys@1a100800 {
+ compatible = "mediatek,mt7622-pciesys",
+ "syscon";
+ reg = <0 0x1a100800 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ ethsys: syscon@1b000000 {
+ compatible = "mediatek,mt7622-ethsys",
+ "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sgmiisys: sgmiisys@1b128000 {
+ compatible = "mediatek,mt7622-sgmiisys",
+ "syscon";
+ reg = <0 0x1b128000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
--
2.7.4
From: Sean Wang <[email protected]>
Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
regulator nodes in an alone file to allow similar boards using MT6380
able to resue the configuration.
Signed-off-by: Sean Wang <[email protected]>
Cc: Mark Brown <[email protected]>
Cc: Matthias Brugger <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6380.dtsi | 91 ++++++++++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++
3 files changed, 111 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
new file mode 100644
index 0000000..7eb7dc2
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Chenglin Xu <[email protected]>
+ * Sean Wang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&pwrap {
+ regulators {
+ compatible = "mediatek,mt6380-regulator";
+
+ mt6380_vcpu_reg: buck-vcore1 {
+ regulator-name = "vcore1";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1393750>;
+ regulator-ramp-delay = <6250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vcore_reg: buck-vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1393750>;
+ regulator-ramp-delay = <6250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vrf_reg: buck-vrf {
+ regulator-name = "vrf";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1575000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vm_reg: ldo-vm {
+ regulator-name = "vm";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_va_reg: ldo-va {
+ regulator-name = "va";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vphy_reg: ldo-vphy {
+ regulator-name = "vphy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vddr_reg: ldo-vddr {
+ regulator-name = "vddr";
+ regulator-min-microvolt = <1240000>;
+ regulator-max-microvolt = <1840000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6380_vt_reg: ldo-vt {
+ regulator-name = "vt";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index c77e77a..f72f1f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -10,6 +10,7 @@
#include <dt-bindings/input/input.h>
#include "mt7622.dtsi"
+#include "mt6380.dtsi"
/ {
model = "MediaTek MT7622 RFB1 board";
@@ -222,6 +223,13 @@
};
};
+&pwrap {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_bus_pins>;
+
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index a531278..5b7f0a3 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -102,6 +102,18 @@
#reset-cells = <1>;
};
+ pwrap: pwrap@10001000 {
+ compatible = "mediatek,mt7622-pwrap";
+ reg = <0 0x10001000 0 0x250>;
+ reg-names = "pwrap";
+ clocks = <&infracfg CLK_INFRA_PMIC_PD>,<&pwrap_clk>;
+ clock-names = "spi","wrap";
+ resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
+ reset-names = "pwrap";
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
pericfg: pericfg@10002000 {
compatible = "mediatek,mt7622-pericfg",
"syscon";
--
2.7.4
From: Sean Wang <[email protected]>
add ethernet device nodes which enable GMAC1 with SGMII interface
Signed-off-by: Sean Wang <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 31 ++++++++++++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 20b1160..d4609a1 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -249,6 +249,28 @@
status = "okay";
};
+ð {
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_pins>;
+ status = "okay";
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-handle = <&phy5>;
+ };
+
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ phy-mode = "sgmii";
+ };
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 540d2fe..04a047e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -477,6 +477,37 @@
#reset-cells = <1>;
};
+ eth: ethernet@1b100000 {
+ compatible = "mediatek,mt7622-eth",
+ "mediatek,mt2701-eth",
+ "syscon";
+ reg = <0 0x1b100000 0 0x20000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
+ <ðsys CLK_ETH_ESW_EN>,
+ <ðsys CLK_ETH_GP0_EN>,
+ <ðsys CLK_ETH_GP1_EN>,
+ <ðsys CLK_ETH_GP2_EN>,
+ <&sgmiisys CLK_SGMII_TX250M_EN>,
+ <&sgmiisys CLK_SGMII_RX250M_EN>,
+ <&sgmiisys CLK_SGMII_CDR_REF>,
+ <&sgmiisys CLK_SGMII_CDR_FB>,
+ <&topckgen CLK_TOP_SGMIIPLL>,
+ <&apmixedsys CLK_APMIXED_ETH2PLL>;
+ clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
+ "sgmii_tx250m", "sgmii_rx250m",
+ "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
+ "eth2pll";
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
+ mediatek,ethsys = <ðsys>;
+ mediatek,sgmiisys = <&sgmiisys>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sgmiisys: sgmiisys@1b128000 {
compatible = "mediatek,mt7622-sgmiisys",
"syscon";
--
2.7.4
From: Sean Wang <[email protected]>
This patch also cleans up two oscillators that provide clocks for MT7623.
Switch the uart clocks to the real ones while at it.
Signed-off-by: Sean Wang <[email protected]>
Cc: Matthias Brugger <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 90b2761..3b6f082 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -88,18 +88,6 @@
};
};
- uart_clk: dummy25m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- bus_clk: dummy280m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <280000000>;
- };
-
pwrap_clk: dummy40m {
compatible = "fixed-clock";
clock-frequency = <40000000>;
@@ -231,7 +219,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>, <&bus_clk>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART1_PD>;
clock-names = "baud", "bus";
status = "disabled";
};
--
2.7.4
From: Sean Wang <[email protected]>
add pinctrl device nodes and rfb1 board, additionally include all pin
groups possible being used on rfb1 board.
Signed-off-by: Sean Wang <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 200 +++++++++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +
2 files changed, 207 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index c08309d..c77e77a 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -7,6 +7,8 @@
*/
/dts-v1/;
+#include <dt-bindings/input/input.h>
+
#include "mt7622.dtsi"
/ {
@@ -17,11 +19,209 @@
bootargs = "console=ttyS0,115200n1";
};
+ gpio_keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ factory {
+ label = "factory";
+ linux,code = <BTN_0>;
+ gpios = <&pio 0 0>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 102 0>;
+ };
+ };
+
memory {
reg = <0 0x40000000 0 0x3F000000>;
};
};
+&pio {
+ /* eMMC is shared pin with parallel NAND */
+ emmc_pins_default: emmc-pins-default {
+ mux {
+ function = "emmc", "emmc_rst";
+ groups = "emmc";
+ };
+ };
+
+ emmc_pins_uhs: emmc-pins-uhs {
+ mux {
+ function = "emmc";
+ groups = "emmc";
+ };
+ };
+
+ eth_pins: eth-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio", "rgmii_via_gmac2";
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_0";
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c2_0";
+ };
+ };
+
+ i2s1_pins: i2s1-pins {
+ mux {
+ function = "i2s";
+ groups = "i2s_out_bclk_ws_mclk",
+ "i2s1_in_data",
+ "i2s1_out_data";
+ };
+ };
+
+ irrx_pins: irrx-pins {
+ mux {
+ function = "ir";
+ groups = "ir_1_rx";
+ };
+ };
+
+ irtx_pins: irtx-pins {
+ mux {
+ function = "ir";
+ groups = "ir_1_tx";
+ };
+ };
+
+ /* Parallel nand is shared pin with eMMC */
+ parallel_nand_pins: parallel-nand-pins {
+ mux {
+ function = "flash";
+ groups = "par_nand";
+ };
+ };
+
+ pcie0_pins: pcie0-pins {
+ mux {
+ groups = "pcie0_pad_perst",
+ "pcie0_1_waken",
+ "pcie0_1_clkreq";
+ function = "pcie";
+ };
+ };
+
+ pcie1_pins: pcie1-pins {
+ mux {
+ groups = "pcie1_pad_perst",
+ "pcie1_0_waken",
+ "pcie1_0_clkreq";
+ function = "pcie";
+ };
+ };
+
+ pmic_bus_pins: pmic-bus-pins {
+ mux {
+ groups = "pmic_bus";
+ function = "pmic";
+ };
+ };
+
+ pwm7_pins: pwm1-2-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm_ch7_2";
+ };
+ };
+
+ wled_pins: wled-pins {
+ mux {
+ function = "led";
+ groups = "wled";
+ };
+ };
+
+ sd0_pins_default: sd0-pins-default {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+ };
+
+ sd0_pins_uhs: sd0-pins-uhs {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+ };
+
+ /* Serial NAND is shared pin with SPI-NOR */
+ serial_nand_pins: serial-nand-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ spic0_pins: spic0-pins {
+ mux {
+ function = "spi";
+ groups = "spic0_0";
+ };
+ };
+
+ spic1_pins: spic1-pins {
+ mux {
+ function = "spi";
+ groups = "spic1_0";
+ };
+ };
+
+ /* SPI-NOR is shared pin with serial NAND */
+ spi_nor_pins: spi-nor-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ /* serial NAND is shared pin with SPI-NOR */
+ serial_nand_pins: serial-nand-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx" ;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_1_tx_rx" ;
+ };
+ };
+
+ watchdog_pins: watchdog-pins {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 6fdc449..a531278 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -147,6 +147,13 @@
#clock-cells = <1>;
};
+ pio: pinctrl@10211000 {
+ compatible = "mediatek,mt7622-pinctrl";
+ reg = <0 0x10211000 0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
gic: interrupt-controller@10300000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.7.4
From: Sean Wang <[email protected]>
Add clocks, regulators and opp information into cpu nodes.
In addition, the power supply for cpu nodes is deployed on
mt7622-rfb1 board.
Signed-off-by: Sean Wang <[email protected]>
Cc: Viresh Kumar <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 12 +++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 49 ++++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index f72f1f5..4762168 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -20,6 +20,18 @@
bootargs = "console=ttyS0,115200n1";
};
+ cpus {
+ cpu@0 {
+ proc-supply = <&mt6380_vcpu_reg>;
+ sram-supply = <&mt6380_vm_reg>;
+ };
+
+ cpu@1 {
+ proc-supply = <&mt6380_vcpu_reg>;
+ sram-supply = <&mt6380_vm_reg>;
+ };
+ };
+
gpio_keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 5b7f0a3..90b2761 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -18,6 +18,50 @@
#address-cells = <2>;
#size-cells = <2>;
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-300000000 {
+ opp-hz = /bits/ 64 <30000000>;
+ opp-microvolt = <950000>;
+ };
+
+ opp-437500000 {
+ opp-hz = /bits/ 64 <437500000>;
+ opp-microvolt = <1000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-812500000 {
+ opp-hz = /bits/ 64 <812500000>;
+ opp-microvolt = <1100000>;
+ };
+
+ opp-1025000000 {
+ opp-hz = /bits/ 64 <1025000000>;
+ opp-microvolt = <1150000>;
+ };
+
+ opp-1137500000 {
+ opp-hz = /bits/ 64 <1137500000>;
+ opp-microvolt = <1200000>;
+ };
+
+ opp-1262500000 {
+ opp-hz = /bits/ 64 <1262500000>;
+ opp-microvolt = <1250000>;
+ };
+
+ opp-1350000000 {
+ opp-hz = /bits/ 64 <1350000000>;
+ opp-microvolt = <1310000>;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -26,6 +70,10 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
+ clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
+ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <1300000000>;
};
@@ -34,6 +82,7 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <1300000000>;
};
--
2.7.4
From: Sean Wang <[email protected]>
Add watchdog, rtc, auxadc, cir, efuse, rng, uart[1-4], pwm, i2c[0-2],
spi[0-1] and btif nodes
Signed-off-by: Sean Wang <[email protected]>
Cc: Andrew-CT Chen <[email protected]>
Cc: Zhiyong Tao <[email protected]>
Cc: Zhi Mao <[email protected]>
Cc: Jun Gao <[email protected]>
Cc: Leilk Liu <[email protected]>
Cc: Matthias Brugger <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 54 ++++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 194 +++++++++++++++++++++++++++
2 files changed, 248 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 4762168..3b2eacc 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -235,6 +235,34 @@
};
};
+&btif {
+ status = "okay";
+};
+
+&cir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&irrx_pins>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm7_pins>;
+ status = "okay";
+};
+
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
@@ -242,6 +270,32 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic0_pins>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic1_pins>;
+ status = "okay";
+};
+
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&watchdog {
+ pinctrl-names = "default";
+ pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 3b6f082..681c87a 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -173,6 +173,16 @@
clock-names = "hif_sel";
};
+ cir: cir@10009000 {
+ compatible = "mediatek,mt7622-cir";
+ reg = <0 0x10009000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_IRRX_PD>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "clk", "bus";
+ status = "disabled";
+ };
+
sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt7622-sysirq",
"mediatek,mt6577-sysirq";
@@ -182,6 +192,18 @@
reg = <0 0x10200620 0 0x20>;
};
+ efuse: efuse@10206000 {
+ compatible = "mediatek,mt7622-efuse",
+ "mediatek,efuse";
+ reg = <0 0x10206000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ thermal_calibration: calib@198 {
+ reg = <0x198 0x8>;
+ };
+ };
+
apmixedsys: apmixedsys@10209000 {
compatible = "mediatek,mt7622-apmixedsys",
"syscon";
@@ -196,6 +218,14 @@
#clock-cells = <1>;
};
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt7622-rng",
+ "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_TRNG>;
+ clock-names = "rng";
+ };
+
pio: pinctrl@10211000 {
compatible = "mediatek,mt7622-pinctrl";
reg = <0 0x10211000 0 0x1000>;
@@ -203,6 +233,21 @@
#gpio-cells = <2>;
};
+ watchdog: watchdog@10212000 {
+ compatible = "mediatek,mt7622-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10212000 0 0x800>;
+ };
+
+ rtc: rtc@10212800 {
+ compatible = "mediatek,mt7622-rtc",
+ "mediatek,soc-rtc";
+ reg = <0 0x10212800 0 0x200>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_RTC>;
+ clock-names = "rtc";
+ };
+
gic: interrupt-controller@10300000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -214,6 +259,14 @@
<0 0x10360000 0 0x2000>;
};
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt7622-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&pericfg CLK_PERI_AUXADC_PD>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7622-uart",
"mediatek,mt6577-uart";
@@ -225,6 +278,147 @@
status = "disabled";
};
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART1_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART2_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11005000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART3_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt7622-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&pericfg CLK_PERI_PWM_PD>,
+ <&pericfg CLK_PERI_PWM1_PD>,
+ <&pericfg CLK_PERI_PWM2_PD>,
+ <&pericfg CLK_PERI_PWM3_PD>,
+ <&pericfg CLK_PERI_PWM4_PD>,
+ <&pericfg CLK_PERI_PWM5_PD>,
+ <&pericfg CLK_PERI_PWM6_PD>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
+ "pwm5", "pwm6";
+ status = "disabled";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt7622-i2c";
+ reg = <0 0x11007000 0 0x90>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0_PD>,
+ <&pericfg CLK_PERI_AP_DMA_PD>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt7622-i2c";
+ reg = <0 0x11008000 0 0x90>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1_PD>,
+ <&pericfg CLK_PERI_AP_DMA_PD>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt7622-i2c";
+ reg = <0 0x11009000 0 0x90>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2_PD>,
+ <&pericfg CLK_PERI_AP_DMA_PD>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt7622-spi";
+ reg = <0 0x1100a000 0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI0_SEL>,
+ <&pericfg CLK_PERI_SPI0_PD>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ btif: serial@1100c000 {
+ compatible = "mediatek,mt7622-btif",
+ "mediatek,mtk-btif";
+ reg = <0 0x1100c000 0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_BTIF_PD>;
+ clock-names = "main";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi1: spi@11016000 {
+ compatible = "mediatek,mt7622-spi";
+ reg = <0 0x11016000 0 0x100>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI1_SEL>,
+ <&pericfg CLK_PERI_SPI1_PD>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart4: serial@11019000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11019000 0 0x400>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART4_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys",
"syscon";
--
2.7.4
On 04-01-18, 17:40, [email protected] wrote:
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index 5b7f0a3..90b2761 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -18,6 +18,50 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + cpu_opp_table: opp_table {
Rob recently asked me to do name the nodes with "-" instead of "_". So
this becomes "cpu_opp_table: opp-table {" then.
--
viresh
On Thu, 2018-01-04 at 15:15 +0530, Viresh Kumar wrote:
> On 04-01-18, 17:40, [email protected] wrote:
> > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> > index 5b7f0a3..90b2761 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> > @@ -18,6 +18,50 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + cpu_opp_table: opp_table {
>
> Rob recently asked me to do name the nodes with "-" instead of "_". So
> this becomes "cpu_opp_table: opp-table {" then.
>
okay, I will do it in the next version.
Sean,
On Thu, Jan 4, 2018 at 10:40 AM, <[email protected]> wrote:
> From: Sean Wang <[email protected]>
>
> Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
> regulator nodes in an alone file to allow similar boards using MT6380
> able to resue the configuration.
>
> Signed-off-by: Sean Wang <[email protected]>
> Cc: Mark Brown <[email protected]>
> Cc: Matthias Brugger <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt6380.dtsi | 91 ++++++++++++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++
> 3 files changed, 111 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> new file mode 100644
> index 0000000..7eb7dc2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> @@ -0,0 +1,91 @@
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Chenglin Xu <[email protected]>
> + * Sean Wang <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
Would you mind using SPDX tags instead of this fine but long legalese?
This is documented in Thomas patches [1].
Also if you could spread the word in your team, this would earn you
good karma points.
Thank you!
[1] https://lkml.org/lkml/2017/12/28/323
--
Cordially
Philippe Ombredanne
On Thu, 2018-01-04 at 11:27 +0100, Philippe Ombredanne wrote:
> Sean,
>
> On Thu, Jan 4, 2018 at 10:40 AM, <[email protected]> wrote:
> > From: Sean Wang <[email protected]>
> >
> > Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
> > regulator nodes in an alone file to allow similar boards using MT6380
> > able to resue the configuration.
> >
> > Signed-off-by: Sean Wang <[email protected]>
> > Cc: Mark Brown <[email protected]>
> > Cc: Matthias Brugger <[email protected]>
> > ---
> > arch/arm64/boot/dts/mediatek/mt6380.dtsi | 91 ++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++
> > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++
> > 3 files changed, 111 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> > new file mode 100644
> > index 0000000..7eb7dc2
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> > @@ -0,0 +1,91 @@
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + * Author: Chenglin Xu <[email protected]>
> > + * Sean Wang <[email protected]>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
>
> Would you mind using SPDX tags instead of this fine but long legalese?
> This is documented in Thomas patches [1].
> Also if you could spread the word in your team, this would earn you
> good karma points.
> Thank you!
>
> [1] https://lkml.org/lkml/2017/12/28/323
Hi, Philippe
thanks for your suggestion
Certainly, this can be replaced with
SPDX-License-Identifier: GPL-2.0
most drivers from MediaTek use the similar disclaimer, it should be fine
to use SPDX tags instead.
Sean
Sean,
On Fri, Jan 5, 2018 at 4:42 AM, Sean Wang <[email protected]> wrote:
> On Thu, 2018-01-04 at 11:27 +0100, Philippe Ombredanne wrote:
>> Sean,
>>
>> On Thu, Jan 4, 2018 at 10:40 AM, <[email protected]> wrote:
>> > From: Sean Wang <[email protected]>
>> >
>> > Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
>> > regulator nodes in an alone file to allow similar boards using MT6380
>> > able to resue the configuration.
>> >
>> > Signed-off-by: Sean Wang <[email protected]>
>> > Cc: Mark Brown <[email protected]>
>> > Cc: Matthias Brugger <[email protected]>
>> > ---
>> > arch/arm64/boot/dts/mediatek/mt6380.dtsi | 91 ++++++++++++++++++++++++++++
>> > arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++
>> > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++
>> > 3 files changed, 111 insertions(+)
>> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
>> >
>> > diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
>> > new file mode 100644
>> > index 0000000..7eb7dc2
>> > --- /dev/null
>> > +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
>> > @@ -0,0 +1,91 @@
>> > +/*
>> > + * Copyright (c) 2018 MediaTek Inc.
>> > + * Author: Chenglin Xu <[email protected]>
>> > + * Sean Wang <[email protected]>
>> > + *
>> > + * This program is free software; you can redistribute it and/or modify
>> > + * it under the terms of the GNU General Public License version 2 as
>> > + * published by the Free Software Foundation.
>> > + *
>> > + * This program is distributed in the hope that it will be useful,
>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> > + * GNU General Public License for more details.
>> > + */
>>
>> Would you mind using SPDX tags instead of this fine but long legalese?
>> This is documented in Thomas patches [1].
>
>> Also if you could spread the word in your team, this would earn you
>> good karma points.
>> Thank you!
>>
>> [1] https://lkml.org/lkml/2017/12/28/323
>
>
> Hi, Philippe
>
> thanks for your suggestion
>
> Certainly, this can be replaced with
>
> SPDX-License-Identifier: GPL-2.0
>
> most drivers from MediaTek use the similar disclaimer, it should be fine
> to use SPDX tags instead.
>
> Sean
>
Thank you! that's great.
--
Cordially
Philippe Ombredanne
On Thu, Jan 04, 2018 at 05:40:51PM +0800, [email protected] wrote:
> From: Sean Wang <[email protected]>
>
> All ethsys, pciesys and ssusbsys internally include reset controller, so
> explicitly add back these missing cell definitions to related bindings
> and examples.
>
> Signed-off-by: Sean Wang <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 2 ++
> Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++
> Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
> 3 files changed, 6 insertions(+)
Reviewed-by: Rob Herring <[email protected]>
Hi, Philippe
Currently, I'm really confused about what usage STYLE of SPDX license
identifier I should use for each type of file.
could you point me where I can find the related document describing SPDX
usage style for those files expected by the community in the future?
I found more than one way STYLE of SPDX present at current code, for
example as below. If there's no absolute definition for them, and then
which way that is better?
1)
for *.dts, applied with "// " at head or within " /* */ " not at head
such as
arch/arm/boot/dts/bcm953012hr.dts:2: * SPDX-License-Identifier:
BSD-3-Clause
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts:4: *
SPDX-License-Identifier: (GPL-2.0+ OR MIT)
arch/arm/boot/dts/uniphier-ld6b-ref.dts:7: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts:4: *
SPDX-License-Identifier: (GPL-2.0+ OR MIT)
arch/arm/boot/dts/keystone-k2g-ice.dts:6: * SPDX-License-Identifier:
GPL-2.0
arch/arm/boot/dts/uniphier-pro4-sanji.dts:7: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm/boot/dts/owl-s500-cubieboard6.dts:6: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm/boot/dts/uniphier-pro4-ace.dts:7: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm/boot/dts/uniphier-sld8-ref.dts:7: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm/boot/dts/uniphier-pro4-ref.dts:7: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm/boot/dts/uniphier-pxs2-gentil.dts:7: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm/boot/dts/uniphier-pxs2-vodka.dts:7: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm/boot/dts/uniphier-ld4-ref.dts:7: * SPDX-License-Identifier:
(GPL-2.0+ OR MIT)
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts:1://
SPDX-License-Identifier: GPL-2.0
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts:1://
SPDX-License-Identifier: GPL-2.0
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts:1://
SPDX-License-Identifier: GPL-2.0
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts:1://
SPDX-License-Identifier: GPL-2.0
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts:1:// SPDX-License-Identifier:
GPL-2.0
arch/arm64/boot/dts/arm/foundation-v8.dts:1:// SPDX-License-Identifier:
GPL-2.0
arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts:1://
SPDX-License-Identifier: GPL-2.0
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts:1://
SPDX-License-Identifier: GPL-2.0
2)
for *.c, applied with "// " at head or within " /* */ " not at head
such as
drivers/base/memory.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/base/devtmpfs.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/base/node.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/base/dma-coherent.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/cpuidle/cpuidle-pseries.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/cpuidle/cpuidle-powernv.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/mtd/maps/tsunami_flash.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/mtd/maps/physmap_of_gemini.c:1:// SPDX-License-Identifier:
GPL-2.0
drivers/mtd/tests/mtd_test.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/mtd/onenand/onenand_bbt.c:1:// SPDX-License-Identifier: GPL-2.0
drivers/media/common/b2c2/flexcop-i2c.c:1:// SPDX-License-Identifier:
GPL-2.0
drivers/soc/xilinx/zynqmp/pm.c:10: * SPDX-License-Identifier: GPL-2.0+
drivers/soc/amlogic/meson-gx-pwrc-vpu.c:5: * SPDX-License-Identifier:
GPL-2.0+
drivers/soc/amlogic/meson-gx-socinfo.c:5: * SPDX-License-Identifier:
GPL-2.0+
drivers/soc/amlogic/meson-mx-socinfo.c:4: * SPDX-License-Identifier:
GPL-2.0+
drivers/i2c/busses/i2c-sprd.c:4: * SPDX-License-Identifier: (GPL-2.0+ OR
MIT)
drivers/spi/spi-meson-spicc.c:7: * SPDX-License-Identifier: GPL-2.0+
drivers/spi/spi-sprd-adi.c:4: * SPDX-License-Identifier: GPL-2.0
drivers/dma/sprd-dma.c:4: * SPDX-License-Identifier: GPL-2.0
3)
for *.h, applied with "// " at head or within " /* */ " at head
such as
drivers/usb/dwc3/gadget.h:1:// SPDX-License-Identifier: GPL-2.0
drivers/usb/dwc3/io.h:1:// SPDX-License-Identifier: GPL-2.0
drivers/usb/dwc3/debug.h:1:// SPDX-License-Identifier: GPL-2.0
drivers/usb/dwc3/core.h:1:// SPDX-License-Identifier: GPL-2.0
drivers/usb/atm/usbatm.h:1:// SPDX-License-Identifier: GPL-2.0+
drivers/usb/misc/rio500_usb.h:1:// SPDX-License-Identifier: GPL-2.0+
drivers/usb/misc/sisusbvga/sisusb.h:1:// SPDX-License-Identifier:
(GPL-2.0 OR BSD-3-Clause)
drivers/usb/misc/sisusbvga/sisusb_init.h:1:// SPDX-License-Identifier:
(GPL-2.0+ OR BSD-3-Clause)
drivers/usb/misc/sisusbvga/sisusb_struct.h:1:// SPDX-License-Identifier:
(GPL-2.0+ OR BSD-3-Clause)
drivers/usb/misc/usb_u132.h:1:// SPDX-License-Identifier: GPL-2.0
drivers/tty/serial/dz.h:1:/* SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/apbuart.h:1:/* SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/sunzilog.h:1:/* SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/zs.h:1:/* SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/sh-sci.h:1:/* SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/cpm_uart/cpm_uart_cpm1.h:1:/*
SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/cpm_uart/cpm_uart_cpm2.h:1:/*
SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/sunsab.h:1:/* SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/amba-pl011.h:1:/* SPDX-License-Identifier: GPL-2.0 */
drivers/tty/serial/crisv10.h:1:/* SPDX-License-Identifier: GPL-2.0 */
4)
no issue, Makefile, or Kconfig, definitely applied with "# " at head
Sean
On Fri, 2018-01-05 at 09:21 +0100, Philippe Ombredanne wrote:
> Sean,
>
> On Fri, Jan 5, 2018 at 4:42 AM, Sean Wang <[email protected]> wrote:
> > On Thu, 2018-01-04 at 11:27 +0100, Philippe Ombredanne wrote:
> >> Sean,
> >>
> >> On Thu, Jan 4, 2018 at 10:40 AM, <[email protected]> wrote:
> >> > From: Sean Wang <[email protected]>
> >> >
> >> > Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
> >> > regulator nodes in an alone file to allow similar boards using MT6380
> >> > able to resue the configuration.
> >> >
> >> > Signed-off-by: Sean Wang <[email protected]>
> >> > Cc: Mark Brown <[email protected]>
> >> > Cc: Matthias Brugger <[email protected]>
> >> > ---
> >> > arch/arm64/boot/dts/mediatek/mt6380.dtsi | 91 ++++++++++++++++++++++++++++
> >> > arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++
> >> > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++
> >> > 3 files changed, 111 insertions(+)
> >> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
> >> >
> >> > diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> >> > new file mode 100644
> >> > index 0000000..7eb7dc2
> >> > --- /dev/null
> >> > +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> >> > @@ -0,0 +1,91 @@
> >> > +/*
> >> > + * Copyright (c) 2018 MediaTek Inc.
> >> > + * Author: Chenglin Xu <[email protected]>
> >> > + * Sean Wang <[email protected]>
> >> > + *
> >> > + * This program is free software; you can redistribute it and/or modify
> >> > + * it under the terms of the GNU General Public License version 2 as
> >> > + * published by the Free Software Foundation.
> >> > + *
> >> > + * This program is distributed in the hope that it will be useful,
> >> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> > + * GNU General Public License for more details.
> >> > + */
> >>
> >> Would you mind using SPDX tags instead of this fine but long legalese?
> >> This is documented in Thomas patches [1].
> >
> >> Also if you could spread the word in your team, this would earn you
> >> good karma points.
> >> Thank you!
> >>
> >> [1] https://lkml.org/lkml/2017/12/28/323
> >
> >
> > Hi, Philippe
> >
> > thanks for your suggestion
> >
> > Certainly, this can be replaced with
> >
> > SPDX-License-Identifier: GPL-2.0
> >
> > most drivers from MediaTek use the similar disclaimer, it should be fine
> > to use SPDX tags instead.
> >
> > Sean
> >
>
> Thank you! that's great.
>
Sean,
sorry for the late reply and thanks you for this research.
On Fri, Jan 12, 2018 at 4:33 AM, Sean Wang <[email protected]> wrote:
> Currently, I'm really confused about what usage STYLE of SPDX license
> identifier I should use for each type of file.
>
> could you point me where I can find the related document describing SPDX
> usage style for those files expected by the community in the future?
The doc is in this patchset [1]
[1] https://lkml.org/lkml/2017/12/28/326
> I found more than one way STYLE of SPDX present at current code, for
> example as below. If there's no absolute definition for them, and then
> which way that is better?
> 1)
> for *.dts, applied with "// " at head or within " /* */ " not at head
> such as
>
> arch/arm/boot/dts/bcm953012hr.dts:2: * SPDX-License-Identifier:
> BSD-3-Clause
This is a "style bug". The comment style for .dts should be //
> 2)
> for *.c, applied with "// " at head or within " /* */ " not at head
> such as
> drivers/soc/xilinx/zynqmp/pm.c:10: * SPDX-License-Identifier: GPL-2.0+
This is a "style bug". The comment style for .c should be //
> 3)
> for *.h, applied with "// " at head or within " /* */ " at head
> such as
> drivers/usb/dwc3/gadget.h:1:// SPDX-License-Identifier: GPL-2.0
This is a "style bug". The comment style for .h should be /**/
> 4)
> no issue, Makefile, or Kconfig, definitely applied with "# " at head
That's the correct way.
So the net-net is that these "style bugs" should be fixed.
--
Cordially
Philippe Ombredanne
Hi, Philippe
Really appreciate your info and detailed explanation. it's clear how
correct way to add GPDX license identifier. I will have a follow-up.
Sean
On Tue, 2018-01-23 at 11:46 +0100, Philippe Ombredanne wrote:
> Sean,
> sorry for the late reply and thanks you for this research.
>
> On Fri, Jan 12, 2018 at 4:33 AM, Sean Wang <[email protected]> wrote:
> > Currently, I'm really confused about what usage STYLE of SPDX license
> > identifier I should use for each type of file.
> >
> > could you point me where I can find the related document describing SPDX
> > usage style for those files expected by the community in the future?
>
> The doc is in this patchset [1]
>
> [1] https://lkml.org/lkml/2017/12/28/326
>
>
> > I found more than one way STYLE of SPDX present at current code, for
> > example as below. If there's no absolute definition for them, and then
> > which way that is better?
> > 1)
> > for *.dts, applied with "// " at head or within " /* */ " not at head
> > such as
> >
> > arch/arm/boot/dts/bcm953012hr.dts:2: * SPDX-License-Identifier:
> > BSD-3-Clause
>
> This is a "style bug". The comment style for .dts should be //
>
> > 2)
> > for *.c, applied with "// " at head or within " /* */ " not at head
> > such as
> > drivers/soc/xilinx/zynqmp/pm.c:10: * SPDX-License-Identifier: GPL-2.0+
>
> This is a "style bug". The comment style for .c should be //
>
> > 3)
> > for *.h, applied with "// " at head or within " /* */ " at head
> > such as
> > drivers/usb/dwc3/gadget.h:1:// SPDX-License-Identifier: GPL-2.0
>
> This is a "style bug". The comment style for .h should be /**/
>
> > 4)
> > no issue, Makefile, or Kconfig, definitely applied with "# " at head
>
> That's the correct way.
>
> So the net-net is that these "style bugs" should be fixed.
>