This patch series add RDMA memory mode support for mediatek SOC MT2712.
MT2712 has three display data path, including three HW engine,
two OVL and one RDMA.
The RDMA used in third ddp and it need to be set memory mode,
then RDMA could read data from memory and output to panel.
Stu Hsieh (15):
drm/mediatek: add connection from RDMA0 to DPI1
drm/mediatek: add connection from RDMA0 to DSI1
drm/mediatek: add connection from RDMA1 to DSI0
drm/mediatek: add connection from RDMA2 to DSI0
drm/mediatek: add RDMA memory mode for crtc created
drm/mediatek: add memory mode for RDMA
drm/mediatek: add layer config to set RDMA for plane setting
drm/mediatek: add RGB color format support for RDMA
drm/mediatek: add YUYV/UYVY color format support for RDMA
drm/mediatek: add drm_device in RDMA for mamory mode to reaquest
buffer
drm/mediatek: add dummy buffer for RDMA memory mode
drm/mediatek: add layer number condition for RDMA to control plane
drm/mediatek: Update some variable name from ovl to comp
drm/mediatek: fixed the error value for add DSI1 in mutex
drm/mediatek: fixed connection from RDMA2 to DSI1
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 122 +++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 59 +++++++++-----
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 20 ++++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
5 files changed, 181 insertions(+), 26 deletions(-)
--
2.12.5
This patch add connection from RDMA0 to DPI1
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 87e4191c250e..03e3628b5b0d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -106,6 +106,7 @@
#define OVL1_MOUT_EN_COLOR1 0x1
#define GAMMA_MOUT_EN_RDMA1 0x1
#define RDMA0_SOUT_DPI0 0x2
+#define RDMA0_SOUT_DPI1 0x3
#define RDMA0_SOUT_DSI2 0x4
#define RDMA0_SOUT_DSI3 0x5
#define RDMA1_SOUT_DPI0 0x2
@@ -224,6 +225,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
--
2.12.5
This patch add RGB color format support for RDMA,
including RGB565, RGB888, RGBA8888 and ARGB8888.
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 41 ++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 4ad0715c8341..5b7dadc21016 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -36,6 +36,8 @@
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
+#define DISP_RDMA_MEM_CON 0x0024
+#define MEM_MODE_INPUT_SWAP BIT(8)
#define DISP_RDMA_MEM_SRC_PITCH 0x002c
#define DISP_RDMA_MEM_GMC_SETTING_0 0x0030
#define DISP_REG_RDMA_FIFO_CON 0x0040
@@ -48,6 +50,11 @@
#define MATRIX_INT_MTX_SEL_DEFAULT 0xb00000
#define RDMA_MEM_GMC 0x40402020
+#define MEM_MODE_INPUT_FORMAT_RGB565 0x0
+#define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
+#define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4)
+#define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4)
+
struct mtk_disp_rdma_data {
unsigned int fifo_size;
};
@@ -156,16 +163,50 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
}
+static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
+ unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return MEM_MODE_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return MEM_MODE_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return MEM_MODE_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return MEM_MODE_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
+ }
+}
+
static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
struct mtk_plane_state *state)
{
+ struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
struct mtk_plane_pending_state *pending = &state->pending;
unsigned int addr = pending->addr;
unsigned int pitch = pending->pitch & 0xffff;
+ unsigned int fmt = pending->format;
+ unsigned int con;
if (pending->height == 0u || pending->width == 0u)
return;
+ con = rdma_fmt_convert(rdma, fmt);
+ writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
+
writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
--
2.12.5
This patch fixed connection from RDMA2 to DSI1
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index ac047fdb1a2b..66a27b6a7583 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -314,7 +314,7 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
--
2.12.5
This patch add YUYV/UYVY color format support for RDMA
and transform matrix for YUYV/UYVY.
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 5b7dadc21016..49edbae50167 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -34,6 +34,8 @@
#define RDMA_SOFT_RESET BIT(4)
#define RDMA_MODE_MEMORY BIT(1)
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
+#define RDMA_MATRIX_ENABLE BIT(17)
+#define RDMA_MATRIX_INT_MTX_SEL (7UL << 20)
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
#define DISP_RDMA_MEM_CON 0x0024
@@ -54,6 +56,8 @@
#define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
#define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4)
#define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4)
+#define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
+#define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
struct mtk_disp_rdma_data {
unsigned int fifo_size;
@@ -188,6 +192,10 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_UYVY:
+ return MEM_MODE_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return MEM_MODE_INPUT_FORMAT_YUYV;
}
}
@@ -206,6 +214,12 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
con = rdma_fmt_convert(rdma, fmt);
writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
+ if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV)
+ rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+ RDMA_MATRIX_ENABLE | RDMA_MATRIX_INT_MTX_SEL);
+ else
+ rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+ MATRIX_INT_MTX_SEL_DEFAULT);
writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
--
2.12.5
This patch add connection from RDMA0 to DSI1
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 03e3628b5b0d..310d8482d5a0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -107,6 +107,7 @@
#define GAMMA_MOUT_EN_RDMA1 0x1
#define RDMA0_SOUT_DPI0 0x2
#define RDMA0_SOUT_DPI1 0x3
+#define RDMA0_SOUT_DSI1 0x1
#define RDMA0_SOUT_DSI2 0x4
#define RDMA0_SOUT_DSI3 0x5
#define RDMA1_SOUT_DPI0 0x2
@@ -228,6 +229,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
--
2.12.5
This patch add RDMA memory mode for crtc created
For mt2712, the third ddp use RDMA engine to read data from dram.
Therefore, when crtc created, crtc need to decide using OVL or RDMA
by ddp to read data from dram.
If this ddp use RDMA, the crtc should set this RDMA which in the crtc
using memory mode.
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 5 ++++-
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8 ++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 585943c81e1f..60851bb2dd63 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -150,6 +150,7 @@ static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
void *data)
{
struct mtk_disp_rdma *priv = dev_get_drvdata(dev);
+ struct mtk_ddp_comp *comp = &priv->ddp_comp;
struct drm_device *drm_dev = data;
int ret;
@@ -160,8 +161,10 @@ static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
return ret;
}
- return 0;
+ comp->comp_mode = &priv->rdma_memory_mode;
+
+ return 0;
}
static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 2d6aa150a9ff..4bf636e466f2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -578,6 +578,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
enum mtk_ddp_comp_id comp_id = path[i];
struct mtk_ddp_comp *comp;
struct device_node *node;
+ bool *rdma_memory_mode;
node = priv->comp_node[comp_id];
comp = priv->ddp_comp[comp_id];
@@ -595,6 +596,13 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
goto unprepare;
}
+ if (i == 0 && (comp_id == DDP_COMPONENT_RDMA0 ||
+ comp_id == DDP_COMPONENT_RDMA1 ||
+ comp_id == DDP_COMPONENT_RDMA2)) {
+ rdma_memory_mode = comp->comp_mode;
+ *rdma_memory_mode = true;
+ }
+
mtk_crtc->ddp_comp[i] = comp;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 7413ffeb3c9d..a1988ce15141 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -93,6 +93,7 @@ struct mtk_ddp_comp {
struct device *larb_dev;
enum mtk_ddp_comp_id id;
const struct mtk_ddp_comp_funcs *funcs;
+ void *comp_mode;
};
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
--
2.12.5
This patch add layer config to set RDMA for plane setting
Layer config set the data address and pitch to RDMA from plane setting.
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 78a1a0057aff..4ad0715c8341 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -36,13 +36,17 @@
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
+#define DISP_RDMA_MEM_SRC_PITCH 0x002c
+#define DISP_RDMA_MEM_GMC_SETTING_0 0x0030
#define DISP_REG_RDMA_FIFO_CON 0x0040
#define RDMA_FIFO_UNDERFLOW_EN BIT(31)
#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
+#define DISP_RDMA_MEM_START_ADDR 0x0f00
#define MATRIX_INT_MTX_SEL_DEFAULT 0xb00000
+#define RDMA_MEM_GMC 0x40402020
struct mtk_disp_rdma_data {
unsigned int fifo_size;
@@ -152,12 +156,28 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
}
+static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
+ struct mtk_plane_state *state)
+{
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int addr = pending->addr;
+ unsigned int pitch = pending->pitch & 0xffff;
+
+ if (pending->height == 0u || pending->width == 0u)
+ return;
+
+ writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
+ writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
+ writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
+}
+
static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
.config = mtk_rdma_config,
.start = mtk_rdma_start,
.stop = mtk_rdma_stop,
.enable_vblank = mtk_rdma_enable_vblank,
.disable_vblank = mtk_rdma_disable_vblank,
+ .layer_config = mtk_rdma_layer_config,
};
static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
--
2.12.5
This patch add dummy buffer for RDMA memory mode
When display power on, the drm frame work would modeset and
set up the display HW.
In this time, the RDMA would start wroking and read the data from memory.
But, user space not send the data to drm yet.
For this case, if user space not send data to display hw(RDMA) yet,
RDMA would read the wrong address to show garbage.
Therefore, we create dummy buffer for RDMA reading memory
when userspace not send the data yet.
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 23 +++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 8d41f5cd485b..e28f368728cd 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -20,6 +20,7 @@
#include "mtk_drm_crtc.h"
#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_gem.h"
#define DISP_REG_RDMA_INT_ENABLE 0x0000
#define DISP_REG_RDMA_INT_STATUS 0x0004
@@ -59,6 +60,9 @@
#define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
#define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
+#define RDMA_DUMMY_BUFFER_SIZE(h, v) ((h) * (v) * 4)
+#define RDMA_DUMMY_BUFFER_PITCH(h) ((h) * 4)
+
struct mtk_disp_rdma_data {
unsigned int fifo_size;
};
@@ -74,6 +78,7 @@ struct mtk_disp_rdma {
const struct mtk_disp_rdma_data *data;
struct drm_device *drm_dev;
bool rdma_memory_mode;
+ unsigned int dummy_size;
};
static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
@@ -126,14 +131,29 @@ static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
static void mtk_rdma_start(struct mtk_ddp_comp *comp)
{
+ struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+ bool *rdma_memory_mode = comp->comp_mode;
+
+ if (*rdma_memory_mode == true) {
+ comp->mtk_gem = mtk_drm_gem_create(rdma->drm_dev,
+ rdma->dummy_size, false);
+ writel(comp->mtk_gem->dma_addr & 0xFFFFFFFF,
+ comp->regs + DISP_RDMA_MEM_START_ADDR);
+ }
+
rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
RDMA_ENGINE_EN);
}
static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
{
+ bool *rdma_memory_mode = comp->comp_mode;
+
writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
+
+ if (*rdma_memory_mode == true)
+ mtk_drm_gem_free_object(&comp->mtk_gem->base);
}
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
@@ -149,8 +169,11 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
if (*rdma_memory_mode == true) {
+ rdma->dummy_size = RDMA_DUMMY_BUFFER_SIZE(width, height);
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
MATRIX_INT_MTX_SEL_DEFAULT);
+ writel(RDMA_DUMMY_BUFFER_PITCH(width),
+ comp->regs + DISP_RDMA_MEM_SRC_PITCH);
rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index a1988ce15141..6dbb83144a74 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -92,6 +92,7 @@ struct mtk_ddp_comp {
int irq;
struct device *larb_dev;
enum mtk_ddp_comp_id id;
+ struct mtk_drm_gem_obj *mtk_gem;
const struct mtk_ddp_comp_funcs *funcs;
void *comp_mode;
};
--
2.12.5
This patch fixed the error value for add DSI1 in mutex
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 3239f22785fd..ac047fdb1a2b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -437,7 +437,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
reg = MUTEX_SOF_DSI0;
break;
case DDP_COMPONENT_DSI1:
- reg = MUTEX_SOF_DSI0;
+ reg = MUTEX_SOF_DSI1;
break;
case DDP_COMPONENT_DSI2:
reg = MUTEX_SOF_DSI2;
--
2.12.5
If RDMA want to request gem buffer, it need to save the drm device.
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 49edbae50167..8d41f5cd485b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -72,6 +72,7 @@ struct mtk_disp_rdma {
struct mtk_ddp_comp ddp_comp;
struct drm_crtc *crtc;
const struct mtk_disp_rdma_data *data;
+ struct drm_device *drm_dev;
bool rdma_memory_mode;
};
@@ -240,6 +241,7 @@ static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
{
struct mtk_disp_rdma *priv = dev_get_drvdata(dev);
struct mtk_ddp_comp *comp = &priv->ddp_comp;
+ struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
struct drm_device *drm_dev = data;
int ret;
@@ -250,6 +252,7 @@ static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
return ret;
}
+ rdma->drm_dev = drm_dev;
comp->comp_mode = &priv->rdma_memory_mode;
--
2.12.5
This patch add connection from RDMA1 to DSI0
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 310d8482d5a0..31189fad8d4e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -124,6 +124,7 @@
#define DPI0_SEL_IN_RDMA2 0x3
#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1 0x1
#define DSI1_SEL_IN_RDMA1 0x1
#define DSI1_SEL_IN_RDMA2 0x4
#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
@@ -290,6 +291,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
value = DSI1_SEL_IN_RDMA1;
--
2.12.5
This patch Update some variable name from ovl to comp
Because RDMA would be first HW in ddp, the naming ovl
should be change to comp.
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 26 +++++++++++++-------------
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 +-
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 8ad90c62caa6..2509ed3e0278 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -172,9 +172,9 @@ static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
- mtk_ddp_comp_enable_vblank(ovl, &mtk_crtc->base);
+ mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base);
return 0;
}
@@ -182,9 +182,9 @@ static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
- mtk_ddp_comp_disable_vblank(ovl);
+ mtk_ddp_comp_disable_vblank(comp);
}
static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
@@ -335,7 +335,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
unsigned int i;
/*
@@ -344,7 +344,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
* queue update module registers on vblank.
*/
if (state->pending_config) {
- mtk_ddp_comp_config(ovl, state->pending_width,
+ mtk_ddp_comp_config(comp, state->pending_width,
state->pending_height,
state->pending_vrefresh, 0);
@@ -359,7 +359,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
plane_state = to_mtk_plane_state(plane->state);
if (plane_state->pending.config) {
- mtk_ddp_comp_layer_config(ovl, i, plane_state);
+ mtk_ddp_comp_layer_config(comp, i, plane_state);
plane_state->pending.config = false;
}
}
@@ -371,12 +371,12 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
int ret;
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
- ret = mtk_smi_larb_get(ovl->larb_dev);
+ ret = mtk_smi_larb_get(comp->larb_dev);
if (ret) {
DRM_ERROR("Failed to get larb: %d\n", ret);
return;
@@ -384,7 +384,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
ret = mtk_crtc_ddp_hw_init(mtk_crtc);
if (ret) {
- mtk_smi_larb_put(ovl->larb_dev);
+ mtk_smi_larb_put(comp->larb_dev);
return;
}
@@ -396,7 +396,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
int i;
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
@@ -419,7 +419,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
drm_crtc_vblank_off(crtc);
mtk_crtc_ddp_hw_fini(mtk_crtc);
- mtk_smi_larb_put(ovl->larb_dev);
+ mtk_smi_larb_put(comp->larb_dev);
mtk_crtc->enabled = false;
}
@@ -517,7 +517,7 @@ static int mtk_drm_crtc_init(struct drm_device *drm,
return ret;
}
-void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
+void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_drm_private *priv = crtc->dev->dev_private;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index b44fefadf14a..0de77f60c806 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -26,7 +26,7 @@
#define MTK_MIN_BPC 3
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
-void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl);
+void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
unsigned int path_len);
--
2.12.5
This patch add memory mode for RDMA
If use RDMA to read data from memory, it should set memory mode to RDMA
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 60851bb2dd63..78a1a0057aff 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -31,6 +31,8 @@
#define RDMA_REG_UPDATE_INT BIT(0)
#define DISP_REG_RDMA_GLOBAL_CON 0x0010
#define RDMA_ENGINE_EN BIT(0)
+#define RDMA_SOFT_RESET BIT(4)
+#define RDMA_MODE_MEMORY BIT(1)
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
@@ -40,6 +42,8 @@
#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
+#define MATRIX_INT_MTX_SEL_DEFAULT 0xb00000
+
struct mtk_disp_rdma_data {
unsigned int fifo_size;
};
@@ -53,6 +57,7 @@ struct mtk_disp_rdma {
struct mtk_ddp_comp ddp_comp;
struct drm_crtc *crtc;
const struct mtk_disp_rdma_data *data;
+ bool rdma_memory_mode;
};
static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
@@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
{
- rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
+ writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
+ writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
}
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
@@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
unsigned int threshold;
unsigned int reg;
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+ bool *rdma_memory_mode = comp->comp_mode;
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
+ if (*rdma_memory_mode == true) {
+ rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
+ MATRIX_INT_MTX_SEL_DEFAULT);
+ rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
+ RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
+ }
+
/*
* Enable FIFO underflow since DSI and DPI can't be blocked.
* Keep the FIFO pseudo size reset default of 8 KiB. Set the
--
2.12.5
This patch add layer number condition for RDMA to control plane
When plane init in crtc create,
it use the number of OVL layer to init plane.
That's OVL can read 4 memory address.
For mt2712 third ddp, it use RDMA to read memory.
RDMA can read 1 memory address, so it just init one plane.
For compatibility, this patch use two define OVL_LAYER_NR and
RDMA_LAYER_NR to distingush two difference HW engine.
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +++++++++++++++++--------
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 ++
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 4bf636e466f2..8ad90c62caa6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -45,7 +45,8 @@ struct mtk_drm_crtc {
bool pending_needs_vblank;
struct drm_pending_vblank_event *event;
- struct drm_plane planes[OVL_LAYER_NR];
+ struct drm_plane planes[MAX_LAYER_NR];
+ unsigned int layer_nr;
bool pending_planes;
void __iomem *config_regs;
@@ -286,7 +287,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
}
/* Initially configure all planes */
- for (i = 0; i < OVL_LAYER_NR; i++) {
+ for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i];
struct mtk_plane_state *plane_state;
@@ -351,7 +352,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
}
if (mtk_crtc->pending_planes) {
- for (i = 0; i < OVL_LAYER_NR; i++) {
+ for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i];
struct mtk_plane_state *plane_state;
@@ -403,7 +404,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
return;
/* Set all pending plane state to disabled */
- for (i = 0; i < OVL_LAYER_NR; i++) {
+ for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i];
struct mtk_plane_state *plane_state;
@@ -450,7 +451,7 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
if (mtk_crtc->event)
mtk_crtc->pending_needs_vblank = true;
- for (i = 0; i < OVL_LAYER_NR; i++) {
+ for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i];
struct mtk_plane_state *plane_state;
@@ -559,6 +560,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!mtk_crtc)
return -ENOMEM;
+ mtk_crtc->layer_nr = OVL_LAYER_NR;
mtk_crtc->config_regs = priv->config_regs;
mtk_crtc->ddp_comp_nr = path_len;
mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
@@ -601,12 +603,13 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
comp_id == DDP_COMPONENT_RDMA2)) {
rdma_memory_mode = comp->comp_mode;
*rdma_memory_mode = true;
+ mtk_crtc->layer_nr = RDMA_LAYER_NR;
}
mtk_crtc->ddp_comp[i] = comp;
}
- for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) {
+ for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) {
type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
(zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
DRM_PLANE_TYPE_OVERLAY;
@@ -616,8 +619,14 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
goto unprepare;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
- &mtk_crtc->planes[1], pipe);
+ if (mtk_crtc->layer_nr == 1) {
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
+ NULL, pipe);
+ } else {
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
+ &mtk_crtc->planes[1], pipe);
+ }
+
if (ret < 0)
goto unprepare;
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 9d9410c67ae9..b44fefadf14a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -18,7 +18,9 @@
#include "mtk_drm_ddp_comp.h"
#include "mtk_drm_plane.h"
+#define MAX_LAYER_NR 4
#define OVL_LAYER_NR 4
+#define RDMA_LAYER_NR 1
#define MTK_LUT_SIZE 512
#define MTK_MAX_BPC 10
#define MTK_MIN_BPC 3
--
2.12.5
This patch add connection from RDMA2 to DSI0
Signed-off-by: Stu Hsieh <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 31189fad8d4e..3239f22785fd 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -125,6 +125,7 @@
#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
#define DSI0_SEL_IN_RDMA1 0x1
+#define DSI0_SEL_IN_RDMA2 0x4
#define DSI1_SEL_IN_RDMA1 0x1
#define DSI1_SEL_IN_RDMA2 0x4
#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
@@ -309,6 +310,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
*addr = DISP_REG_CONFIG_DPI_SEL_IN;
value = DPI1_SEL_IN_RDMA2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+ value = DSI0_SEL_IN_RDMA2;
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
value = DSI1_SEL_IN_RDMA2;
--
2.12.5
Hi, Stu:
It looks like the series is a bug fix of [1]. In [1], you create third
crtc but it does not work unless apply this series. So for all the
patches in this series, you should refer to [2] to add 'Fixes:' and
'Cc:' in commit message.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=e6ab087a224fd7bcf712db698fbade673cc9addd
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=83ba62bc700bab710b22be3a1bf6cf973f754273
Regards,
CK
On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> This patch series add RDMA memory mode support for mediatek SOC MT2712.
> MT2712 has three display data path, including three HW engine,
> two OVL and one RDMA.
>
> The RDMA used in third ddp and it need to be set memory mode,
> then RDMA could read data from memory and output to panel.
>
> Stu Hsieh (15):
> drm/mediatek: add connection from RDMA0 to DPI1
> drm/mediatek: add connection from RDMA0 to DSI1
> drm/mediatek: add connection from RDMA1 to DSI0
> drm/mediatek: add connection from RDMA2 to DSI0
> drm/mediatek: add RDMA memory mode for crtc created
> drm/mediatek: add memory mode for RDMA
> drm/mediatek: add layer config to set RDMA for plane setting
> drm/mediatek: add RGB color format support for RDMA
> drm/mediatek: add YUYV/UYVY color format support for RDMA
> drm/mediatek: add drm_device in RDMA for mamory mode to reaquest
> buffer
> drm/mediatek: add dummy buffer for RDMA memory mode
> drm/mediatek: add layer number condition for RDMA to control plane
> drm/mediatek: Update some variable name from ovl to comp
> drm/mediatek: fixed the error value for add DSI1 in mutex
> drm/mediatek: fixed connection from RDMA2 to DSI1
>
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 122 +++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 59 +++++++++-----
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 20 ++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
> 5 files changed, 181 insertions(+), 26 deletions(-)
>
Hi, Stu:
On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> This patch add memory mode for RDMA
>
> If use RDMA to read data from memory, it should set memory mode to RDMA
>
> Signed-off-by: Stu Hsieh <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
[...]
> static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> @@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
>
> static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
> {
> - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
> + writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> + writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
Without reset, what happen to dram mode? Why direct link mode need not
this reset?
> }
>
> static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> @@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> unsigned int threshold;
> unsigned int reg;
> struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> + bool *rdma_memory_mode = comp->comp_mode;
>
> rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
>
> + if (*rdma_memory_mode == true) {
> + rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> + MATRIX_INT_MTX_SEL_DEFAULT);
> + rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> + RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> + }
> +
I would like this to be a kind of 'layer' config. In some SoC, one layer
of OVL could switch to direct link input or dram input. So I think it's
better to move this setting into some layer interface.
Regards,
CK
> /*
> * Enable FIFO underflow since DSI and DPI can't be blocked.
> * Keep the FIFO pseudo size reset default of 8 KiB. Set the
Hi, Stu:
On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> This patch add layer number condition for RDMA to control plane
>
> When plane init in crtc create,
> it use the number of OVL layer to init plane.
> That's OVL can read 4 memory address.
>
> For mt2712 third ddp, it use RDMA to read memory.
> RDMA can read 1 memory address, so it just init one plane.
>
> For compatibility, this patch use two define OVL_LAYER_NR and
> RDMA_LAYER_NR to distingush two difference HW engine.
>
> Signed-off-by: Stu Hsieh <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +++++++++++++++++--------
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 ++
> 2 files changed, 19 insertions(+), 8 deletions(-)
>
[...]
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 9d9410c67ae9..b44fefadf14a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -18,7 +18,9 @@
> #include "mtk_drm_ddp_comp.h"
> #include "mtk_drm_plane.h"
>
> +#define MAX_LAYER_NR 4
> #define OVL_LAYER_NR 4
> +#define RDMA_LAYER_NR 1
> #define MTK_LUT_SIZE 512
> #define MTK_MAX_BPC 10
> #define MTK_MIN_BPC 3
If the layer number is not fixed in '4', I would like to get this value
from component because in some SoC, OVL may have 6 layer. So add an
interface to get the max layer number and OVL, RDMA driver would return
the number for this SoC.
Regards,
CK
Hi, Stu:
On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> This patch fixed the error value for add DSI1 in mutex
>
English is not my mother language, but should it be 'fix' rather than
'fixed'?
Regards,
CK
> Signed-off-by: Stu Hsieh <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 3239f22785fd..ac047fdb1a2b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -437,7 +437,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> reg = MUTEX_SOF_DSI0;
> break;
> case DDP_COMPONENT_DSI1:
> - reg = MUTEX_SOF_DSI0;
> + reg = MUTEX_SOF_DSI1;
> break;
> case DDP_COMPONENT_DSI2:
> reg = MUTEX_SOF_DSI2;
Hi, Stu:
On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> This patch add dummy buffer for RDMA memory mode
>
> When display power on, the drm frame work would modeset and
> set up the display HW.
>
> In this time, the RDMA would start wroking and read the data from memory.
> But, user space not send the data to drm yet.
>
> For this case, if user space not send data to display hw(RDMA) yet,
> RDMA would read the wrong address to show garbage.
>
> Therefore, we create dummy buffer for RDMA reading memory
> when userspace not send the data yet.
>
Is this the only solution? If panel resolution is 1920x1080, the buffer
size is 8294400 bytes. How large it is. If we have another solution,
I'll not accept this one. As far as I know, DSI or DPI could output
single color even though there is no input data. If this is true, when
encoder is enabled, it output the single color. When crtc enable, config
all setting except 'start'. When receive the buffer, 'start' the
pipeline which include encoder. When encoder 'start', it disable the
single color function and output the data from input.
Regards,
CK
> Signed-off-by: Stu Hsieh <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 23 +++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 8d41f5cd485b..e28f368728cd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -20,6 +20,7 @@
>
> #include "mtk_drm_crtc.h"
> #include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_gem.h"
>
> #define DISP_REG_RDMA_INT_ENABLE 0x0000
> #define DISP_REG_RDMA_INT_STATUS 0x0004
> @@ -59,6 +60,9 @@
> #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
> #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
>
> +#define RDMA_DUMMY_BUFFER_SIZE(h, v) ((h) * (v) * 4)
> +#define RDMA_DUMMY_BUFFER_PITCH(h) ((h) * 4)
> +
> struct mtk_disp_rdma_data {
> unsigned int fifo_size;
> };
> @@ -74,6 +78,7 @@ struct mtk_disp_rdma {
> const struct mtk_disp_rdma_data *data;
> struct drm_device *drm_dev;
> bool rdma_memory_mode;
> + unsigned int dummy_size;
> };
>
> static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> @@ -126,14 +131,29 @@ static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
>
> static void mtk_rdma_start(struct mtk_ddp_comp *comp)
> {
> + struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> + bool *rdma_memory_mode = comp->comp_mode;
> +
> + if (*rdma_memory_mode == true) {
> + comp->mtk_gem = mtk_drm_gem_create(rdma->drm_dev,
> + rdma->dummy_size, false);
> + writel(comp->mtk_gem->dma_addr & 0xFFFFFFFF,
> + comp->regs + DISP_RDMA_MEM_START_ADDR);
> + }
> +
> rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
> RDMA_ENGINE_EN);
> }
>
> static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
> {
> + bool *rdma_memory_mode = comp->comp_mode;
> +
> writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> +
> + if (*rdma_memory_mode == true)
> + mtk_drm_gem_free_object(&comp->mtk_gem->base);
> }
>
> static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> @@ -149,8 +169,11 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
>
> if (*rdma_memory_mode == true) {
> + rdma->dummy_size = RDMA_DUMMY_BUFFER_SIZE(width, height);
> rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> MATRIX_INT_MTX_SEL_DEFAULT);
> + writel(RDMA_DUMMY_BUFFER_PITCH(width),
> + comp->regs + DISP_RDMA_MEM_SRC_PITCH);
> rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> }
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index a1988ce15141..6dbb83144a74 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -92,6 +92,7 @@ struct mtk_ddp_comp {
> int irq;
> struct device *larb_dev;
> enum mtk_ddp_comp_id id;
> + struct mtk_drm_gem_obj *mtk_gem;
> const struct mtk_ddp_comp_funcs *funcs;
> void *comp_mode;
> };
Hi, CK:
On Wed, 2018-07-25 at 09:39 +0800, CK Hu wrote:
> Hi, Stu:
>
> It looks like the series is a bug fix of [1]. In [1], you create third
> crtc but it does not work unless apply this series. So for all the
> patches in this series, you should refer to [2] to add 'Fixes:' and
> 'Cc:' in commit message.
>
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=e6ab087a224fd7bcf712db698fbade673cc9addd
> [2]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=83ba62bc700bab710b22be3a1bf6cf973f754273
>
> Regards,
> CK
>
OK
Regards,
Stu
> On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> > This patch series add RDMA memory mode support for mediatek SOC MT2712.
> > MT2712 has three display data path, including three HW engine,
> > two OVL and one RDMA.
> >
> > The RDMA used in third ddp and it need to be set memory mode,
> > then RDMA could read data from memory and output to panel.
> >
> > Stu Hsieh (15):
> > drm/mediatek: add connection from RDMA0 to DPI1
> > drm/mediatek: add connection from RDMA0 to DSI1
> > drm/mediatek: add connection from RDMA1 to DSI0
> > drm/mediatek: add connection from RDMA2 to DSI0
> > drm/mediatek: add RDMA memory mode for crtc created
> > drm/mediatek: add memory mode for RDMA
> > drm/mediatek: add layer config to set RDMA for plane setting
> > drm/mediatek: add RGB color format support for RDMA
> > drm/mediatek: add YUYV/UYVY color format support for RDMA
> > drm/mediatek: add drm_device in RDMA for mamory mode to reaquest
> > buffer
> > drm/mediatek: add dummy buffer for RDMA memory mode
> > drm/mediatek: add layer number condition for RDMA to control plane
> > drm/mediatek: Update some variable name from ovl to comp
> > drm/mediatek: fixed the error value for add DSI1 in mutex
> > drm/mediatek: fixed connection from RDMA2 to DSI1
> >
> > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 122 +++++++++++++++++++++++++++-
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 59 +++++++++-----
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 4 +-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 20 ++++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
> > 5 files changed, 181 insertions(+), 26 deletions(-)
> >
>
>
Hi, CK:
On Wed, 2018-07-25 at 10:40 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> > This patch add memory mode for RDMA
> >
> > If use RDMA to read data from memory, it should set memory mode to RDMA
> >
> > Signed-off-by: Stu Hsieh <[email protected]>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
> > 1 file changed, 15 insertions(+), 1 deletion(-)
> >
>
> [...]
>
> > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> > @@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
> >
> > static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
> > {
> > - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
> > + writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> > + writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
>
> Without reset, what happen to dram mode? Why direct link mode need not
> this reset?
>
There is nothing to happen, I would remove it.
> > }
> >
> > static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > @@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > unsigned int threshold;
> > unsigned int reg;
> > struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> > + bool *rdma_memory_mode = comp->comp_mode;
> >
> > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
> >
> > + if (*rdma_memory_mode == true) {
> > + rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> > + MATRIX_INT_MTX_SEL_DEFAULT);
> > + rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> > + RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> > + }
> > +
>
> I would like this to be a kind of 'layer' config. In some SoC, one layer
> of OVL could switch to direct link input or dram input. So I think it's
> better to move this setting into some layer interface.
>
> Regards,
> CK
>
If move it to layer_config, RDMA would not trigger interrupt.
In the future, when cmdq patch upstream and accepted, this part can move
to layer_config.
Regard,
Stu
> > /*
> > * Enable FIFO underflow since DSI and DPI can't be blocked.
> > * Keep the FIFO pseudo size reset default of 8 KiB. Set the
>
>
Hi, CK:
On Wed, 2018-07-25 at 11:02 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> > This patch add layer number condition for RDMA to control plane
> >
> > When plane init in crtc create,
> > it use the number of OVL layer to init plane.
> > That's OVL can read 4 memory address.
> >
> > For mt2712 third ddp, it use RDMA to read memory.
> > RDMA can read 1 memory address, so it just init one plane.
> >
> > For compatibility, this patch use two define OVL_LAYER_NR and
> > RDMA_LAYER_NR to distingush two difference HW engine.
> >
> > Signed-off-by: Stu Hsieh <[email protected]>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +++++++++++++++++--------
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 ++
> > 2 files changed, 19 insertions(+), 8 deletions(-)
> >
>
> [...]
>
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > index 9d9410c67ae9..b44fefadf14a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > @@ -18,7 +18,9 @@
> > #include "mtk_drm_ddp_comp.h"
> > #include "mtk_drm_plane.h"
> >
> > +#define MAX_LAYER_NR 4
> > #define OVL_LAYER_NR 4
> > +#define RDMA_LAYER_NR 1
> > #define MTK_LUT_SIZE 512
> > #define MTK_MAX_BPC 10
> > #define MTK_MIN_BPC 3
>
> If the layer number is not fixed in '4', I would like to get this value
> from component because in some SoC, OVL may have 6 layer. So add an
> interface to get the max layer number and OVL, RDMA driver would return
> the number for this SoC.
>
> Regards,
> CK
>
OK
Regards,
Stu
>
Hi, CK:
On Wed, 2018-07-25 at 13:10 +0800, CK Hu wrote:
> Hi, Stu:
>
>
> On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> > This patch fixed the error value for add DSI1 in mutex
> >
>
> English is not my mother language, but should it be 'fix' rather than
> 'fixed'?
>
> Regards,
> CK
>
OK
Regards,
Stu
> > Signed-off-by: Stu Hsieh <[email protected]>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 3239f22785fd..ac047fdb1a2b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -437,7 +437,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> > reg = MUTEX_SOF_DSI0;
> > break;
> > case DDP_COMPONENT_DSI1:
> > - reg = MUTEX_SOF_DSI0;
> > + reg = MUTEX_SOF_DSI1;
> > break;
> > case DDP_COMPONENT_DSI2:
> > reg = MUTEX_SOF_DSI2;
>
>
Hi, CK:
On Wed, 2018-07-25 at 13:42 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> > This patch add dummy buffer for RDMA memory mode
> >
> > When display power on, the drm frame work would modeset and
> > set up the display HW.
> >
> > In this time, the RDMA would start wroking and read the data from memory.
> > But, user space not send the data to drm yet.
> >
> > For this case, if user space not send data to display hw(RDMA) yet,
> > RDMA would read the wrong address to show garbage.
> >
> > Therefore, we create dummy buffer for RDMA reading memory
> > when userspace not send the data yet.
> >
>
> Is this the only solution? If panel resolution is 1920x1080, the buffer
> size is 8294400 bytes. How large it is. If we have another solution,
> I'll not accept this one. As far as I know, DSI or DPI could output
> single color even though there is no input data. If this is true, when
> encoder is enabled, it output the single color. When crtc enable, config
> all setting except 'start'. When receive the buffer, 'start' the
> pipeline which include encoder. When encoder 'start', it disable the
> single color function and output the data from input.
>
> Regards,
> CK
>
I would remove dummy_buffer patch.
Your idea "use encoder black pattern before the first buffer coming" can
work.
But it need also move "rdma memory mode setting" to layer_config.
Therefore, when cmdq patch accepted, I will commit another patch set to
fix the garbage output to panel.
>
> > Signed-off-by: Stu Hsieh <[email protected]>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 23 +++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > 2 files changed, 24 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > index 8d41f5cd485b..e28f368728cd 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > @@ -20,6 +20,7 @@
> >
> > #include "mtk_drm_crtc.h"
> > #include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_gem.h"
> >
> > #define DISP_REG_RDMA_INT_ENABLE 0x0000
> > #define DISP_REG_RDMA_INT_STATUS 0x0004
> > @@ -59,6 +60,9 @@
> > #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
> > #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
> >
> > +#define RDMA_DUMMY_BUFFER_SIZE(h, v) ((h) * (v) * 4)
> > +#define RDMA_DUMMY_BUFFER_PITCH(h) ((h) * 4)
> > +
> > struct mtk_disp_rdma_data {
> > unsigned int fifo_size;
> > };
> > @@ -74,6 +78,7 @@ struct mtk_disp_rdma {
> > const struct mtk_disp_rdma_data *data;
> > struct drm_device *drm_dev;
> > bool rdma_memory_mode;
> > + unsigned int dummy_size;
> > };
> >
> > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> > @@ -126,14 +131,29 @@ static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
> >
> > static void mtk_rdma_start(struct mtk_ddp_comp *comp)
> > {
> > + struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> > + bool *rdma_memory_mode = comp->comp_mode;
> > +
> > + if (*rdma_memory_mode == true) {
> > + comp->mtk_gem = mtk_drm_gem_create(rdma->drm_dev,
> > + rdma->dummy_size, false);
> > + writel(comp->mtk_gem->dma_addr & 0xFFFFFFFF,
> > + comp->regs + DISP_RDMA_MEM_START_ADDR);
> > + }
> > +
> > rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
> > RDMA_ENGINE_EN);
> > }
> >
> > static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
> > {
> > + bool *rdma_memory_mode = comp->comp_mode;
> > +
> > writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> > writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> > +
> > + if (*rdma_memory_mode == true)
> > + mtk_drm_gem_free_object(&comp->mtk_gem->base);
> > }
> >
> > static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > @@ -149,8 +169,11 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
> >
> > if (*rdma_memory_mode == true) {
> > + rdma->dummy_size = RDMA_DUMMY_BUFFER_SIZE(width, height);
> > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> > MATRIX_INT_MTX_SEL_DEFAULT);
> > + writel(RDMA_DUMMY_BUFFER_PITCH(width),
> > + comp->regs + DISP_RDMA_MEM_SRC_PITCH);
> > rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> > RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> > }
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index a1988ce15141..6dbb83144a74 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -92,6 +92,7 @@ struct mtk_ddp_comp {
> > int irq;
> > struct device *larb_dev;
> > enum mtk_ddp_comp_id id;
> > + struct mtk_drm_gem_obj *mtk_gem;
> > const struct mtk_ddp_comp_funcs *funcs;
> > void *comp_mode;
> > };
>
>
Hi, Stu:
On Thu, 2018-08-02 at 19:36 +0800, Stu Hsieh wrote:
> Hi, CK:
>
> On Wed, 2018-07-25 at 10:40 +0800, CK Hu wrote:
> > Hi, Stu:
> >
> > On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote:
> > > This patch add memory mode for RDMA
> > >
> > > If use RDMA to read data from memory, it should set memory mode to RDMA
> > >
> > > Signed-off-by: Stu Hsieh <[email protected]>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++-
> > > 1 file changed, 15 insertions(+), 1 deletion(-)
> > >
> >
> > [...]
> >
> > > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> > > @@ -111,7 +116,8 @@ static void mtk_rdma_start(struct mtk_ddp_comp *comp)
> > >
> > > static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
> > > {
> > > - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
> > > + writel(RDMA_SOFT_RESET, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> > > + writel(0, comp->regs + DISP_REG_RDMA_GLOBAL_CON);
> >
> > Without reset, what happen to dram mode? Why direct link mode need not
> > this reset?
> >
>
> There is nothing to happen, I would remove it.
>
> > > }
> > >
> > > static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > > @@ -121,10 +127,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> > > unsigned int threshold;
> > > unsigned int reg;
> > > struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> > > + bool *rdma_memory_mode = comp->comp_mode;
> > >
> > > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> > > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
> > >
> > > + if (*rdma_memory_mode == true) {
> > > + rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xff0000,
> > > + MATRIX_INT_MTX_SEL_DEFAULT);
> > > + rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> > > + RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> > > + }
> > > +
> >
> > I would like this to be a kind of 'layer' config. In some SoC, one layer
> > of OVL could switch to direct link input or dram input. So I think it's
> > better to move this setting into some layer interface.
> >
> > Regards,
> > CK
> >
>
> If move it to layer_config, RDMA would not trigger interrupt.
> In the future, when cmdq patch upstream and accepted, this part can move
> to layer_config.
I don't know why interrupt would be influenced by moving this to layer
config? In mtk_crtc_ddp_hw_init(), call mtk_ddp_comp_config() first and
then call mtk_ddp_comp_layer_config() later. It's in almost the same
place.
Regards,
CK
>
> Regard,
> Stu
>
> > > /*
> > > * Enable FIFO underflow since DSI and DPI can't be blocked.
> > > * Keep the FIFO pseudo size reset default of 8 KiB. Set the
> >
> >
>
>