From: Philipp Rossak <[email protected]>
This Patchseries enables the IR controller and the dwmac-sun8i
on the Friendlyarm Nanopi M1 and Friendlyarm Nanopi M1 Plus boards.
On the Nanopi M1 Plus additionally the BT/Wifi module is activated.
Philipp Rossak (7):
ARM: dts: sun8i: h3: nanopi-m1: Enable IR controller
ARM: dts: sun8i: h3: nanopi-m1-plus: Enable IR controller
ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Nanopi M1 Plus
ARM: dts: sun8i: h3: Enable AP6212 WiFi on mmc1 on Nanopi M1 Plus
ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Nanopi M1
ARM: dts: sun8i: h3: Adding UART3 RTS and CTS Pins
ARM: dts: sun8i: h3: Enable AP6212 BT on uart3 on Nanopi M1 Plus
arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 80 +++++++++++++++++++++++++++
arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 17 ++++++
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 ++
3 files changed, 102 insertions(+)
--
2.7.4
From: Philipp Rossak <[email protected]>
The Nanopi M1 Plus has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Signed-off-by: Philipp Rossak <[email protected]>
---
arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 8ddd1b2..ece275b 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -55,6 +55,12 @@
status = "okay";
};
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.7.4
From: Philipp Rossak <[email protected]>
The dwmac-sun8i hardware is present on the Nanopi M1.
It uses the internal PHY.
Signed-off-by: Philipp Rossak <[email protected]>
---
arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
index 3a2ccdb..c77fbca 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -45,6 +45,10 @@
/ {
model = "FriendlyArm NanoPi M1";
compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3";
+
+ aliases {
+ ethernet0 = &emac;
+ };
};
&ehci1 {
@@ -55,6 +59,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
--
2.7.4
From: Philipp Rossak <[email protected]>
The BT side of the AP6212 WiFi/BT combo module is connected to
uart3.
Enable BT on this board by enabling uart3 with using additionally
the cts and rts pins.
Signed-off-by: Philipp Rossak <[email protected]>
---
arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 3054308..8c12419 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -49,6 +49,7 @@
aliases {
ethernet0 = &emac;
ethernet1 = &ap6212;
+ serial1 = &uart3;
};
reg_gmac_3v3: gmac-3v3 {
@@ -135,3 +136,9 @@
function = "gpio_out";
};
};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
+ status = "okay";
+};
--
2.7.4
From: Philipp Rossak <[email protected]>
This node adds the definition for the UART3 RTS and CTS Pins
That makes it able to use UART3 with RTS and CTS.
Signed-off-by: Philipp Rossak <[email protected]>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d38282b..7f750ef 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -381,6 +381,11 @@
pins = "PA13", "PA14";
function = "uart3";
};
+
+ uart3_rts_cts_pins: uart3_rts_cts {
+ pins = "PA15", "PA16";
+ function = "uart3";
+ };
};
timer@01c20c00 {
--
2.7.4
From: Philipp Rossak <[email protected]>
The WiFi side of the AP6212 WiFi/BT combo module is connected to
mmc1. There are also GPIOs for enable and interrupts.
Enable WiFi on this board by enabling mmc1 and adding the power
sequencing clocks and GPIO, as well as the chip's interrupt line.
Signed-off-by: Philipp Rossak <[email protected]>
---
arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 35 +++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index b9c6c27..3054308 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -48,6 +48,7 @@
aliases {
ethernet0 = &emac;
+ ethernet1 = &ap6212;
};
reg_gmac_3v3: gmac-3v3 {
@@ -59,6 +60,14 @@
enable-active-high;
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_en_npi_m1p>;
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ };
+
};
&ehci1 {
@@ -93,6 +102,25 @@
};
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ ap6212: sdio_wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
+};
+
&ohci1 {
status = "okay";
};
@@ -100,3 +128,10 @@
&ohci2 {
status = "okay";
};
+
+&r_pio {
+ wifi_en_npi_m1p: wifi_en_pin {
+ pins = "PL7";
+ function = "gpio_out";
+ };
+};
--
2.7.4
From: Philipp Rossak <[email protected]>
The Nanopi M1 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Signed-off-by: Philipp Rossak <[email protected]>
---
arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
index ec63d10..3a2ccdb 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -55,6 +55,12 @@
status = "okay";
};
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.7.4
From: Philipp Rossak <[email protected]>
The dwmac-sun8i hardware is present on the Nanopi M1 Plus.
It uses an external PHY.
Signed-off-by: Philipp Rossak <[email protected]>
---
arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 32 +++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index ece275b..b9c6c27 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -45,6 +45,20 @@
/ {
model = "FriendlyArm NanoPi M1 Plus";
compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
+
+ aliases {
+ ethernet0 = &emac;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
};
&ehci1 {
@@ -55,12 +69,30 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&ohci1 {
status = "okay";
};
--
2.7.4
On Wed, Aug 30, 2017 at 11:01 AM, Philipp Rossak <[email protected]> wrote:
> From: Philipp Rossak <[email protected]>
>
> The dwmac-sun8i hardware is present on the Nanopi M1 Plus.
Support for this has been reverted. Please send this once it has
been added again.
ChenYu
> It uses an external PHY.
>
> Signed-off-by: Philipp Rossak <[email protected]>
On Wed, Aug 30, 2017 at 05:01:04AM +0200, Philipp Rossak wrote:
> From: Philipp Rossak <[email protected]>
>
> The Nanopi M1 has an onboard IR receiver.
> This enables the onboard IR receiver subnode.
>
> Signed-off-by: Philipp Rossak <[email protected]>
Queued for 4.15, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
On Wed, Aug 30, 2017 at 05:01:05AM +0200, Philipp Rossak wrote:
> From: Philipp Rossak <[email protected]>
>
> The Nanopi M1 Plus has an onboard IR receiver.
> This enables the onboard IR receiver subnode.
>
> Signed-off-by: Philipp Rossak <[email protected]>
Queued for 4.15, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Hi,
On Wed, Aug 30, 2017 at 05:01:07AM +0200, Philipp Rossak wrote:
> From: Philipp Rossak <[email protected]>
>
> The WiFi side of the AP6212 WiFi/BT combo module is connected to
> mmc1. There are also GPIOs for enable and interrupts.
>
> Enable WiFi on this board by enabling mmc1 and adding the power
> sequencing clocks and GPIO, as well as the chip's interrupt line.
>
> Signed-off-by: Philipp Rossak <[email protected]>
> ---
> arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 35 +++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> index b9c6c27..3054308 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> @@ -48,6 +48,7 @@
>
> aliases {
> ethernet0 = &emac;
> + ethernet1 = &ap6212;
> };
>
> reg_gmac_3v3: gmac-3v3 {
> @@ -59,6 +60,14 @@
> enable-active-high;
> gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
> };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_en_npi_m1p>;
There's no need for pinctrl nodes when the pin is set to a GPIO.
> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
> + };
> +
> };
>
> &ehci1 {
> @@ -93,6 +102,25 @@
> };
> };
>
> +&mmc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc1_pins_a>;
> + vmmc-supply = <®_vcc3v3>;
> + vqmmc-supply = <®_vcc3v3>;
You don't need vqmmc in this case.
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +
> + ap6212: sdio_wifi@1 {
You're sure you need a label here?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Hi,
thanks for the feedback I will rework the patch.
Should I also update the sun8i-h3-bananapi-m2-plus.dts? It uses also the
AP6212 and it is done in the same way like in this patch.
Am 30.08.2017 um 16:52 schrieb Maxime Ripard:
> Hi,
>
> On Wed, Aug 30, 2017 at 05:01:07AM +0200, Philipp Rossak wrote:
>> From: Philipp Rossak <[email protected]>
>>
>> The WiFi side of the AP6212 WiFi/BT combo module is connected to
>> mmc1. There are also GPIOs for enable and interrupts.
>>
>> Enable WiFi on this board by enabling mmc1 and adding the power
>> sequencing clocks and GPIO, as well as the chip's interrupt line.
>>
>> Signed-off-by: Philipp Rossak <[email protected]>
>> ---
>> arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 35 +++++++++++++++++++++++++++
>> 1 file changed, 35 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
>> index b9c6c27..3054308 100644
>> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
>> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
>> @@ -48,6 +48,7 @@
>>
>> aliases {
>> ethernet0 = &emac;
>> + ethernet1 = &ap6212;
>> };
>>
>> reg_gmac_3v3: gmac-3v3 {
>> @@ -59,6 +60,14 @@
>> enable-active-high;
>> gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
>> };
>> +
>> + wifi_pwrseq: wifi_pwrseq {
>> + compatible = "mmc-pwrseq-simple";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&wifi_en_npi_m1p>;
>
> There's no need for pinctrl nodes when the pin is set to a GPIO.
>
>> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
>> + };
>> +
>> };
>>
>> &ehci1 {
>> @@ -93,6 +102,25 @@
>> };
>> };
>>
>> +&mmc1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mmc1_pins_a>;
>> + vmmc-supply = <®_vcc3v3>;
>> + vqmmc-supply = <®_vcc3v3>;
>
> You don't need vqmmc in this case.
>
>> + mmc-pwrseq = <&wifi_pwrseq>;
>> + bus-width = <4>;
>> + non-removable;
>> + status = "okay";
>> +
>> + ap6212: sdio_wifi@1 {
>
> You're sure you need a label here?
>
> Thanks!
> Maxime
>
On Wed, Aug 30, 2017 at 05:01:09AM +0200, Philipp Rossak wrote:
> From: Philipp Rossak <[email protected]>
>
> This node adds the definition for the UART3 RTS and CTS Pins
>
> That makes it able to use UART3 with RTS and CTS.
>
> Signed-off-by: Philipp Rossak <[email protected]>
Queued for 4.15, thanks
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
On Wed, Aug 30, 2017 at 05:01:10AM +0200, Philipp Rossak wrote:
> From: Philipp Rossak <[email protected]>
>
> The BT side of the AP6212 WiFi/BT combo module is connected to
> uart3.
>
> Enable BT on this board by enabling uart3 with using additionally
> the cts and rts pins.
>
> Signed-off-by: Philipp Rossak <[email protected]>
I've queued this patch for 4.15, but...
> ---
> arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> index 3054308..8c12419 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> @@ -49,6 +49,7 @@
> aliases {
> ethernet0 = &emac;
> ethernet1 = &ap6212;
> + serial1 = &uart3;
You'll also need an alias for serial 0 here. Can you send a follow up
patch to do so?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
On Wed, Aug 30, 2017 at 11:51:37PM +0200, Philipp Rossak wrote:
> Hi,
> thanks for the feedback I will rework the patch.
> Should I also update the sun8i-h3-bananapi-m2-plus.dts? It uses also the
> AP6212 and it is done in the same way like in this patch.
Yes, please.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com