Hi,
This patch series adds initial support for the Microsemi MIPS SoCs. It
is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514).
It also adds support for the reset controller.
This produces a kernel that can boot to the console.
This is a single series for reference but the reset driver can be taken
separately.
Changes in v3:
- removed the pinctrl driver as it has already been taken
- removed the irqchip driver as the bindings have been acked and will not
change
- changed the reset controller bindings following Rob's review
Changes in v2:
- removed the wildcard in MAINAINERS
- corrected the Cc list
- added proper documentation for both syscons
- removed the mscc,cpucontrol property
- updated the ranges property in the ocelot dtsi
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: Sebastian Reichel <[email protected]>
Cc: [email protected]
Alexandre Belloni (8):
dt-bindings: mips: Add bindings for Microsemi SoCs
dt-bindings: power: reset: Document ocelot-reset binding
power: reset: Add a driver for the Microsemi Ocelot reset
MIPS: mscc: Add initial support for Microsemi MIPS SoCs
MIPS: mscc: add ocelot dtsi
MIPS: mscc: add ocelot PCB123 device tree
MIPS: defconfigs: add a defconfig for Microsemi SoCs
MAINTAINERS: Add entry for Microsemi MIPS SoCs
Documentation/devicetree/bindings/mips/mscc.txt | 44 +++++++++
.../bindings/power/reset/ocelot-reset.txt | 14 +++
MAINTAINERS | 7 ++
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 24 +++++
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/mscc/Makefile | 6 ++
arch/mips/boot/dts/mscc/ocelot.dtsi | 110 +++++++++++++++++++++
arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 27 +++++
arch/mips/configs/mscc_defconfig | 84 ++++++++++++++++
arch/mips/mscc/Makefile | 11 +++
arch/mips/mscc/Platform | 12 +++
arch/mips/mscc/setup.c | 106 ++++++++++++++++++++
drivers/power/reset/Kconfig | 7 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/ocelot-reset.c | 88 +++++++++++++++++
16 files changed, 543 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
create mode 100644 arch/mips/boot/dts/mscc/Makefile
create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi
create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts
create mode 100644 arch/mips/configs/mscc_defconfig
create mode 100644 arch/mips/mscc/Makefile
create mode 100644 arch/mips/mscc/Platform
create mode 100644 arch/mips/mscc/setup.c
create mode 100644 drivers/power/reset/ocelot-reset.c
--
2.15.1
Add myself as a maintainer for the Microsemi MIPS SoCs.
Signed-off-by: Alexandre Belloni <[email protected]>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52fd76..a71fa0ac0abb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9062,6 +9062,13 @@ S: Maintained
F: drivers/usb/misc/usb251xb.c
F: Documentation/devicetree/bindings/usb/usb251xb.txt
+MICROSEMI MIPS SOCS
+M: Alexandre Belloni <[email protected]>
+L: [email protected]
+S: Maintained
+F: arch/mips/mscc/
+F: arch/mips/boot/dts/mscc/
+
MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi)
M: Don Brace <[email protected]>
L: [email protected]
--
2.15.1
Add a device tree include file for the Microsemi Ocelot SoC.
Signed-off-by: Alexandre Belloni <[email protected]>
---
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/mscc/Makefile | 4 ++
arch/mips/boot/dts/mscc/ocelot.dtsi | 110 ++++++++++++++++++++++++++++++++++++
3 files changed, 115 insertions(+)
create mode 100644 arch/mips/boot/dts/mscc/Makefile
create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index e2c6f131c8eb..1e79cab8e269 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
+subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
subdir-y += ni
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
new file mode 100644
index 000000000000..f0a155a74e02
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -0,0 +1,4 @@
+obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+
+# Force kbuild to make empty built-in.o if necessary
+obj- += dummy.o
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
new file mode 100644
index 000000000000..b2f936e1fbb9
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,ocelot";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mips-hpt-frequency = <250000000>;
+
+ cpu@0 {
+ compatible = "mscc,ocelot";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x70000000 0x2000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ reset@1070008 {
+ compatible = "mscc,ocelot-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
+ gpio: pinctrl@1070034 {
+ compatible = "mscc,ocelot-pinctrl";
+ reg = <0x1070034 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_6", "GPIO_7";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_12", "GPIO_13";
+ function = "uart2";
+ };
+ };
+ };
+};
--
2.15.1
Add a defconfg that reaches userspace for Microsemi Ocelot.
Signed-off-by: Alexandre Belloni <[email protected]>
---
arch/mips/configs/mscc_defconfig | 84 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 arch/mips/configs/mscc_defconfig
diff --git a/arch/mips/configs/mscc_defconfig b/arch/mips/configs/mscc_defconfig
new file mode 100644
index 000000000000..58cf09b1ae82
--- /dev/null
+++ b/arch/mips/configs/mscc_defconfig
@@ -0,0 +1,84 @@
+CONFIG_MSCC_OCELOT=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_MIPS_ELF_APPENDED_DTB=y
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_SWAP is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_SHMEM is not set
+CONFIG_EMBEDDED=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_MICROSEMI_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_N_GSM=y
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_OCELOT_RESET=y
+CONFIG_SENSORS_TMP401=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_OVERLAY_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_CRYPTO_HW is not set
--
2.15.1
The Microsemi Ocelot SoC has a register allowing to reset the MIPS core.
Unfortunately, the syscon-reboot driver can't be used directly (but almost)
as the reset control may be disabled using another register.
Cc: Sebastian Reichel <[email protected]>
Cc: [email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/ocelot-reset.c | 88 ++++++++++++++++++++++++++++++++++++++
3 files changed, 96 insertions(+)
create mode 100644 drivers/power/reset/ocelot-reset.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index ca0de1a78e85..2372f8e1040d 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -113,6 +113,13 @@ config POWER_RESET_MSM
help
Power off and restart support for Qualcomm boards.
+config POWER_RESET_OCELOT_RESET
+ bool "Microsemi Ocelot reset driver"
+ depends on MSCC_OCELOT || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This driver supports restart for Microsemi Ocelot SoC.
+
config POWER_RESET_PIIX4_POWEROFF
tristate "Intel PIIX4 power-off driver"
depends on PCI
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index aeb65edb17b7..df9d92291c67 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
+obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
new file mode 100644
index 000000000000..5a13a5cc8188
--- /dev/null
+++ b/drivers/power/reset/ocelot-reset.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi MIPS SoC reset driver
+ *
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/notifier.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+
+struct ocelot_reset_context {
+ void __iomem *base;
+ struct regmap *cpu_ctrl;
+ struct notifier_block restart_handler;
+};
+
+#define ICPU_CFG_CPU_SYSTEM_CTRL_RESET 0x20
+#define CORE_RST_PROTECT BIT(2)
+
+#define SOFT_CHIP_RST BIT(0)
+
+static int ocelot_restart_handle(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+ struct ocelot_reset_context *ctx = container_of(this, struct
+ ocelot_reset_context,
+ restart_handler);
+
+ /* Make sure the core is not protected from reset */
+ regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_RESET,
+ CORE_RST_PROTECT, 0);
+
+ writel(SOFT_CHIP_RST, ctx->base);
+
+ pr_emerg("Unable to restart system\n");
+ return NOTIFY_DONE;
+}
+
+static int ocelot_reset_probe(struct platform_device *pdev)
+{
+ struct ocelot_reset_context *ctx;
+ struct resource *res;
+
+ struct device *dev = &pdev->dev;
+ int err;
+
+ ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ctx->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(ctx->base))
+ return PTR_ERR(ctx->base);
+
+ ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible("mscc,ocelot-cpu-syscon");
+ if (IS_ERR(ctx->cpu_ctrl))
+ return PTR_ERR(ctx->cpu_ctrl);
+
+ ctx->restart_handler.notifier_call = ocelot_restart_handle;
+ ctx->restart_handler.priority = 192;
+ err = register_restart_handler(&ctx->restart_handler);
+ if (err)
+ dev_err(dev, "can't register restart notifier (err=%d)\n", err);
+
+ return err;
+}
+
+static const struct of_device_id ocelot_reset_of_match[] = {
+ { .compatible = "mscc,ocelot-chip-reset" },
+ {}
+};
+
+static struct platform_driver ocelot_reset_driver = {
+ .probe = ocelot_reset_probe,
+ .driver = {
+ .name = "ocelot-chip-reset",
+ .of_match_table = ocelot_reset_of_match,
+ },
+};
+builtin_platform_driver(ocelot_reset_driver);
--
2.15.1
Introduce support for the MIPS based Microsemi Ocelot SoCs.
As the plan is to have all SoCs supported only using device tree, the
mach directory is simply called mscc.
Signed-off-by: Alexandre Belloni <[email protected]>
---
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 24 ++++++++++
arch/mips/mscc/Makefile | 11 +++++
arch/mips/mscc/Platform | 12 +++++
arch/mips/mscc/setup.c | 106 +++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 154 insertions(+)
create mode 100644 arch/mips/mscc/Makefile
create mode 100644 arch/mips/mscc/Platform
create mode 100644 arch/mips/mscc/setup.c
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index ac7ad54f984f..b3b2f8dc91db 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -18,6 +18,7 @@ platforms += lantiq
platforms += lasat
platforms += loongson32
platforms += loongson64
+platforms += mscc
platforms += mti-malta
platforms += netlogic
platforms += paravirt
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 350a990fc719..a9db028a0338 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -527,6 +527,30 @@ config MIPS_MALTA
This enables support for the MIPS Technologies Malta evaluation
board.
+config MSCC_OCELOT
+ bool "Microsemi Ocelot architecture"
+ select BOOT_RAW
+ select CEVT_R4K
+ select CSRC_R4K
+ select IRQ_MIPS_CPU
+ select DMA_NONCOHERENT
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_HAS_EARLY_PRINTK
+ select USE_GENERIC_EARLY_PRINTK_8250
+ select MSCC_OCELOT_IRQ
+ select PINCTRL
+ select GPIOLIB
+ select COMMON_CLK
+ select USE_OF
+ select BUILTIN_DTB
+ select LIBFDT
+ help
+ This enables support for the Microsemi Ocelot architecture.
+ It builds a generic DT-based kernel image.
+
config MACH_PIC32
bool "Microchip PIC32 Family"
help
diff --git a/arch/mips/mscc/Makefile b/arch/mips/mscc/Makefile
new file mode 100644
index 000000000000..c96b13546730
--- /dev/null
+++ b/arch/mips/mscc/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: (GPL-2.0 OR MIT)
+#
+# Microsemi MIPS SoC support
+#
+# License: Dual MIT/GPL
+# Copyright (c) 2017 Microsemi Corporation
+
+#
+# Makefile for the Microsemi MIPS SoCs
+#
+obj-y := setup.o
diff --git a/arch/mips/mscc/Platform b/arch/mips/mscc/Platform
new file mode 100644
index 000000000000..9ae874c8f136
--- /dev/null
+++ b/arch/mips/mscc/Platform
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: (GPL-2.0 OR MIT)
+#
+# Microsemi MIPS SoC support
+#
+# License: Dual MIT/GPL
+# Copyright (c) 2017 Microsemi Corporation
+
+#
+# Microsemi Ocelot board(s)
+#
+platform-$(CONFIG_MSCC_OCELOT) += mscc/
+load-$(CONFIG_MSCC_OCELOT) += 0x80100000
diff --git a/arch/mips/mscc/setup.c b/arch/mips/mscc/setup.c
new file mode 100644
index 000000000000..77803edd7bfd
--- /dev/null
+++ b/arch/mips/mscc/setup.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi MIPS SoC support
+ *
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <linux/reboot.h>
+
+#include <asm/time.h>
+#include <asm/idle.h>
+#include <asm/prom.h>
+#include <asm/reboot.h>
+
+static void __init ocelot_earlyprintk_init(void)
+{
+ void __iomem *uart_base;
+
+ uart_base = ioremap_nocache(0x70100000, 0x0f);
+ setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
+}
+
+void __init prom_init(void)
+{
+ /* Sanity check for defunct bootloader */
+ if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
+ unsigned int prom_argc = fw_arg0;
+ const char **prom_argv = (const char **)fw_arg1;
+
+ if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
+ /* ignore all built-in args if any f/w args given */
+ strcpy(arcs_cmdline, prom_argv[1]);
+ }
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+unsigned int get_c0_compare_int(void)
+{
+ return CP0_LEGACY_COMPARE_IRQ;
+}
+
+void __init plat_time_init(void)
+{
+ struct device_node *np;
+ u32 freq;
+
+ np = of_find_node_by_name(NULL, "cpus");
+ if (!np)
+ panic("missing 'cpus' DT node");
+ if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
+ panic("missing 'mips-hpt-frequency' property");
+ of_node_put(np);
+
+ mips_hpt_frequency = freq;
+}
+
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
+
+const char *get_system_type(void)
+{
+ return "Microsemi Ocelot";
+}
+
+static void __init ocelot_late_init(void)
+{
+ ocelot_earlyprintk_init();
+}
+
+extern void (*late_time_init)(void);
+
+void __init plat_mem_setup(void)
+{
+ /* This has to be done so late because ioremap needs to work */
+ late_time_init = ocelot_late_init;
+
+ __dt_setup_arch(__dtb_start);
+}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
+}
+
+static int __init populate_machine(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ return 0;
+}
+arch_initcall(populate_machine);
--
2.15.1
Add a device tree for the Microsemi Ocelot PCB123 evaluation board.
Signed-off-by: Alexandre Belloni <[email protected]>
---
arch/mips/boot/dts/mscc/Makefile | 2 ++
arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 27 +++++++++++++++++++++++++++
2 files changed, 29 insertions(+)
create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
index f0a155a74e02..09a1c4b97de2 100644
--- a/arch/mips/boot/dts/mscc/Makefile
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -1,3 +1,5 @@
+dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb
+
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
# Force kbuild to make empty built-in.o if necessary
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
new file mode 100644
index 000000000000..42bd404471f6
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/dts-v1/;
+
+#include "ocelot.dtsi"
+
+/ {
+ compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0e000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.15.1
Add bindings for Microsemi SoCs. Currently only Ocelot is supported.
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
---
Documentation/devicetree/bindings/mips/mscc.txt | 44 +++++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
new file mode 100644
index 000000000000..f531d195efc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -0,0 +1,44 @@
+* Microsemi MIPS CPUs
+
+Boards with a SoC of the Microsemi MIPS family shall have the following
+properties:
+
+Required properties:
+- compatible: "mscc,ocelot"
+- mips-hpt-frequency: CPU counter frequency.
+
+
+* Other peripherals:
+
+o CPU chip regs:
+
+The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
+functionalities: chip ID, general purpose register for software use, reset
+controller, hardware status and configuration, efuses.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+ };
+
+
+o CPU system control:
+
+The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
+the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
+endianess, CPU bus control, CPU status.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
--
2.15.1
Add binding documentation for the Microsemi Ocelot reset block.
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: Sebastian Reichel <[email protected]>
Cc: [email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
new file mode 100644
index 000000000000..1b4213eb3473
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -0,0 +1,14 @@
+Microsemi Ocelot reset controller
+
+The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
+SoC MIPS core.
+
+Required Properties:
+ - compatible: "mscc,ocelot-chip-reset"
+
+Example:
+ reset@1070008 {
+ compatible = "mscc,ocelot-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
--
2.15.1
On Tue, Jan 16, 2018 at 11:12:33AM +0100, Alexandre Belloni wrote:
> Add bindings for Microsemi SoCs. Currently only Ocelot is supported.
>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> Signed-off-by: Alexandre Belloni <[email protected]>
> ---
> Documentation/devicetree/bindings/mips/mscc.txt | 44 +++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
You missed my R-by on v2.
Rob
On Tue, Jan 16, 2018 at 11:12:34AM +0100, Alexandre Belloni wrote:
> Add binding documentation for the Microsemi Ocelot reset block.
>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> Cc: Sebastian Reichel <[email protected]>
> Cc: [email protected]
> Signed-off-by: Alexandre Belloni <[email protected]>
> ---
> .../devicetree/bindings/power/reset/ocelot-reset.txt | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
Reviewed-by: Rob Herring <[email protected]>
Hi,
On Tue, Jan 16, 2018 at 11:12:34AM +0100, Alexandre Belloni wrote:
> Add binding documentation for the Microsemi Ocelot reset block.
>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> Cc: Sebastian Reichel <[email protected]>
> Cc: [email protected]
> Signed-off-by: Alexandre Belloni <[email protected]>
> ---
Thanks, queued. My public for-next branch is waiting for 4.16-rc1
tag, though.
-- Sebastian
> .../devicetree/bindings/power/reset/ocelot-reset.txt | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
>
> diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> new file mode 100644
> index 000000000000..1b4213eb3473
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> @@ -0,0 +1,14 @@
> +Microsemi Ocelot reset controller
> +
> +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
> +SoC MIPS core.
> +
> +Required Properties:
> + - compatible: "mscc,ocelot-chip-reset"
> +
> +Example:
> + reset@1070008 {
> + compatible = "mscc,ocelot-chip-reset";
> + reg = <0x1070008 0x4>;
> + };
> +
> --
> 2.15.1
>
Hi,
On Tue, Jan 16, 2018 at 11:12:35AM +0100, Alexandre Belloni wrote:
> The Microsemi Ocelot SoC has a register allowing to reset the MIPS core.
> Unfortunately, the syscon-reboot driver can't be used directly (but almost)
> as the reset control may be disabled using another register.
>
> Cc: Sebastian Reichel <[email protected]>
> Cc: [email protected]
> Signed-off-by: Alexandre Belloni <[email protected]>
> ---
Thanks, queued. My for-next branch is waiting for 4.16-rc1 tag, though.
-- Sebastian
> drivers/power/reset/Kconfig | 7 +++
> drivers/power/reset/Makefile | 1 +
> drivers/power/reset/ocelot-reset.c | 88 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 96 insertions(+)
> create mode 100644 drivers/power/reset/ocelot-reset.c
>
> diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
> index ca0de1a78e85..2372f8e1040d 100644
> --- a/drivers/power/reset/Kconfig
> +++ b/drivers/power/reset/Kconfig
> @@ -113,6 +113,13 @@ config POWER_RESET_MSM
> help
> Power off and restart support for Qualcomm boards.
>
> +config POWER_RESET_OCELOT_RESET
> + bool "Microsemi Ocelot reset driver"
> + depends on MSCC_OCELOT || COMPILE_TEST
> + select MFD_SYSCON
> + help
> + This driver supports restart for Microsemi Ocelot SoC.
> +
> config POWER_RESET_PIIX4_POWEROFF
> tristate "Intel PIIX4 power-off driver"
> depends on PCI
> diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
> index aeb65edb17b7..df9d92291c67 100644
> --- a/drivers/power/reset/Makefile
> +++ b/drivers/power/reset/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
> obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
> obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o
> obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
> +obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
> obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
> obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
> obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
> diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
> new file mode 100644
> index 000000000000..5a13a5cc8188
> --- /dev/null
> +++ b/drivers/power/reset/ocelot-reset.c
> @@ -0,0 +1,88 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Microsemi MIPS SoC reset driver
> + *
> + * License: Dual MIT/GPL
> + * Copyright (c) 2017 Microsemi Corporation
> + */
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/notifier.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/reboot.h>
> +#include <linux/regmap.h>
> +
> +struct ocelot_reset_context {
> + void __iomem *base;
> + struct regmap *cpu_ctrl;
> + struct notifier_block restart_handler;
> +};
> +
> +#define ICPU_CFG_CPU_SYSTEM_CTRL_RESET 0x20
> +#define CORE_RST_PROTECT BIT(2)
> +
> +#define SOFT_CHIP_RST BIT(0)
> +
> +static int ocelot_restart_handle(struct notifier_block *this,
> + unsigned long mode, void *cmd)
> +{
> + struct ocelot_reset_context *ctx = container_of(this, struct
> + ocelot_reset_context,
> + restart_handler);
> +
> + /* Make sure the core is not protected from reset */
> + regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_RESET,
> + CORE_RST_PROTECT, 0);
> +
> + writel(SOFT_CHIP_RST, ctx->base);
> +
> + pr_emerg("Unable to restart system\n");
> + return NOTIFY_DONE;
> +}
> +
> +static int ocelot_reset_probe(struct platform_device *pdev)
> +{
> + struct ocelot_reset_context *ctx;
> + struct resource *res;
> +
> + struct device *dev = &pdev->dev;
> + int err;
> +
> + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
> + if (!ctx)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + ctx->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(ctx->base))
> + return PTR_ERR(ctx->base);
> +
> + ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible("mscc,ocelot-cpu-syscon");
> + if (IS_ERR(ctx->cpu_ctrl))
> + return PTR_ERR(ctx->cpu_ctrl);
> +
> + ctx->restart_handler.notifier_call = ocelot_restart_handle;
> + ctx->restart_handler.priority = 192;
> + err = register_restart_handler(&ctx->restart_handler);
> + if (err)
> + dev_err(dev, "can't register restart notifier (err=%d)\n", err);
> +
> + return err;
> +}
> +
> +static const struct of_device_id ocelot_reset_of_match[] = {
> + { .compatible = "mscc,ocelot-chip-reset" },
> + {}
> +};
> +
> +static struct platform_driver ocelot_reset_driver = {
> + .probe = ocelot_reset_probe,
> + .driver = {
> + .name = "ocelot-chip-reset",
> + .of_match_table = ocelot_reset_of_match,
> + },
> +};
> +builtin_platform_driver(ocelot_reset_driver);
> --
> 2.15.1
>
On Tue, Jan 16, 2018 at 11:12:37AM +0100, Alexandre Belloni wrote:
> Add a device tree include file for the Microsemi Ocelot SoC.
>
> Signed-off-by: Alexandre Belloni <[email protected]>
May I suggest Cc'ing the DT folk on this patch.
> diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
> new file mode 100644
> index 000000000000..f0a155a74e02
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/Makefile
> @@ -0,0 +1,4 @@
> +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
> +
> +# Force kbuild to make empty built-in.o if necessary
> +obj- += dummy.o
I don't think you need this since f7adc3124da0 ("kbuild: create
built-in.o automatically if parent directory wants it"). It was removed
from other places in bf070bb0e6c6 ("kbuild: remove all dummy assignments
to obj-").
Cheers
James
On Tue, Jan 16, 2018 at 11:12:33AM +0100, Alexandre Belloni wrote:
> +o CPU system control:
> +
> +The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
> +the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
> +endianess, CPU bus control, CPU status.
nit: checkpatch suggests endianess should be spelt endianness
Cheers
James
On Tue, Jan 16, 2018 at 11:12:36AM +0100, Alexandre Belloni wrote:
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 350a990fc719..a9db028a0338 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -527,6 +527,30 @@ config MIPS_MALTA
> This enables support for the MIPS Technologies Malta evaluation
> board.
>
> +config MSCC_OCELOT
> + bool "Microsemi Ocelot architecture"
> + select BOOT_RAW
> + select CEVT_R4K
> + select CSRC_R4K
> + select IRQ_MIPS_CPU
> + select DMA_NONCOHERENT
> + select SYS_HAS_CPU_MIPS32_R2
> + select SYS_SUPPORTS_32BIT_KERNEL
> + select SYS_SUPPORTS_BIG_ENDIAN
> + select SYS_SUPPORTS_LITTLE_ENDIAN
> + select SYS_HAS_EARLY_PRINTK
> + select USE_GENERIC_EARLY_PRINTK_8250
> + select MSCC_OCELOT_IRQ
> + select PINCTRL
> + select GPIOLIB
> + select COMMON_CLK
> + select USE_OF
> + select BUILTIN_DTB
> + select LIBFDT
Please sort alphanumerically.
> + help
> + This enables support for the Microsemi Ocelot architecture.
> + It builds a generic DT-based kernel image.
> +
> config MACH_PIC32
> bool "Microchip PIC32 Family"
> help
...
> diff --git a/arch/mips/mscc/Platform b/arch/mips/mscc/Platform
> new file mode 100644
> index 000000000000..9ae874c8f136
> --- /dev/null
> +++ b/arch/mips/mscc/Platform
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +#
> +# Microsemi MIPS SoC support
> +#
> +# License: Dual MIT/GPL
> +# Copyright (c) 2017 Microsemi Corporation
> +
> +#
> +# Microsemi Ocelot board(s)
> +#
> +platform-$(CONFIG_MSCC_OCELOT) += mscc/
Please use tabs to align
> +load-$(CONFIG_MSCC_OCELOT) += 0x80100000
Please drop the space after the tab.
> diff --git a/arch/mips/mscc/setup.c b/arch/mips/mscc/setup.c
> new file mode 100644
> index 000000000000..77803edd7bfd
> --- /dev/null
> +++ b/arch/mips/mscc/setup.c
> @@ -0,0 +1,106 @@
...
> +
> +#include <asm/time.h>
> +#include <asm/idle.h>
> +#include <asm/prom.h>
> +#include <asm/reboot.h>
Please sort these includes alphanumerically if possible.
> +
> +static void __init ocelot_earlyprintk_init(void)
> +{
> + void __iomem *uart_base;
> +
> + uart_base = ioremap_nocache(0x70100000, 0x0f);
Maybe these hex literals (the address at least) can use #defines.
0xf is an odd size when the 2 below indicates 32-bit registers.
> + setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
> +}
...
> +extern void (*late_time_init)(void);
This is already declared in linux/init.h which you include, so I think
you can drop it.
> +void __init device_tree_init(void)
> +{
> + if (!initial_boot_params)
> + return;
I think flatten_and_copy_device_tree() already checks this (with a
warning), so this could be dropped.
Cheers
James
On Tue, Jan 16, 2018 at 11:12:38AM +0100, Alexandre Belloni wrote:
> Add a device tree for the Microsemi Ocelot PCB123 evaluation board.
>
> Signed-off-by: Alexandre Belloni <[email protected]>
Please Cc DT folk.
> diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> new file mode 100644
> index 000000000000..42bd404471f6
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/* Copyright (c) 2017 Microsemi Corporation */
> +
> +/dts-v1/;
> +
> +#include "ocelot.dtsi"
> +
> +/ {
> + compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
Should mscc,ocelot-pcb123 be added to the mscc DT binding documentation
in the other patch?
Cheers
James
On Tue, Jan 16, 2018 at 11:12:39AM +0100, Alexandre Belloni wrote:
> +# CONFIG_EARLY_PRINTK is not set
Only Loongson1b/1c explicitly disable early printk. Do you disable it
for a particular reason?
Cheers
James
On Tue, Jan 16, 2018 at 11:12:40AM +0100, Alexandre Belloni wrote:
> +MICROSEMI MIPS SOCS
> +M: Alexandre Belloni <[email protected]>
> +L: [email protected]
> +S: Maintained
> +F: arch/mips/mscc/
> +F: arch/mips/boot/dts/mscc/
You should probably include
Documentation/devicetree/bindings/mips/mscc.txt here.
Cheers
James
Alexandre,
On Wed, Feb 14, 2018 at 5:51 PM, James Hogan <[email protected]> wrote:
> On Tue, Jan 16, 2018 at 11:12:36AM +0100, Alexandre Belloni wrote:
...
>> diff --git a/arch/mips/mscc/Platform b/arch/mips/mscc/Platform
>> new file mode 100644
>> index 000000000000..9ae874c8f136
>> --- /dev/null
>> +++ b/arch/mips/mscc/Platform
>> @@ -0,0 +1,12 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +#
>> +# Microsemi MIPS SoC support
>> +#
>> +# License: Dual MIT/GPL
IMHO you should remove this line as it exactly repeats the
SPDX-License-Identifier: (GPL-2.0 OR MIT) line in a less clear and
precise way.
The whole purpose of the SPDX things is to make licensing eventually
as clear ass possible
Thanks!
--
Cordially
Philippe Ombredanne
On 14/02/2018 at 17:03:43 +0000, James Hogan wrote:
> On Tue, Jan 16, 2018 at 11:12:39AM +0100, Alexandre Belloni wrote:
> > +# CONFIG_EARLY_PRINTK is not set
>
> Only Loongson1b/1c explicitly disable early printk. Do you disable it
> for a particular reason?
>
Well, it is so late that it is not really useful and I don't find that
particularly interesting to have it on by default.
But I don't have a strong opinion, I certainly can let it enabled.
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Feb 27, 2018 at 05:15:50PM +0100, Alexandre Belloni wrote:
> On 14/02/2018 at 17:03:43 +0000, James Hogan wrote:
> > On Tue, Jan 16, 2018 at 11:12:39AM +0100, Alexandre Belloni wrote:
> > > +# CONFIG_EARLY_PRINTK is not set
> >
> > Only Loongson1b/1c explicitly disable early printk. Do you disable it
> > for a particular reason?
> >
>
> Well, it is so late that it is not really useful and I don't find that
> particularly interesting to have it on by default.
>
> But I don't have a strong opinion, I certainly can let it enabled.
No problem. I leave it up to you.
Cheers
James
On 14/02/2018 at 16:57:43 +0000, James Hogan wrote:
> On Tue, Jan 16, 2018 at 11:12:37AM +0100, Alexandre Belloni wrote:
> > Add a device tree include file for the Microsemi Ocelot SoC.
> >
> > Signed-off-by: Alexandre Belloni <[email protected]>
>
> May I suggest Cc'ing the DT folk on this patch.
>
I can do that but I think that while they care about the bindings
themselves, they usually don't review the device trees.
So I wouldn't expect any review from Rob on such a patch, especially
since he reviewed the bndings.
> > diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
> > new file mode 100644
> > index 000000000000..f0a155a74e02
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/mscc/Makefile
> > @@ -0,0 +1,4 @@
> > +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
> > +
> > +# Force kbuild to make empty built-in.o if necessary
> > +obj- += dummy.o
>
> I don't think you need this since f7adc3124da0 ("kbuild: create
> built-in.o automatically if parent directory wants it"). It was removed
> from other places in bf070bb0e6c6 ("kbuild: remove all dummy assignments
> to obj-").
>
> Cheers
> James
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
On 14/02/2018 at 17:00:42 +0000, James Hogan wrote:
> On Tue, Jan 16, 2018 at 11:12:38AM +0100, Alexandre Belloni wrote:
> > Add a device tree for the Microsemi Ocelot PCB123 evaluation board.
> >
> > Signed-off-by: Alexandre Belloni <[email protected]>
>
> Please Cc DT folk.
>
I can do but again, I don't think they care.
> > diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> > new file mode 100644
> > index 000000000000..42bd404471f6
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> > @@ -0,0 +1,27 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> > +/* Copyright (c) 2017 Microsemi Corporation */
> > +
> > +/dts-v1/;
> > +
> > +#include "ocelot.dtsi"
> > +
> > +/ {
> > + compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
>
> Should mscc,ocelot-pcb123 be added to the mscc DT binding documentation
> in the other patch?
>
On ARM at least, we don't document the board compatibles because this
will be a huge list without much benefit as they are mostly unused.
Still, it is nice to have in case something specific needs to be done
for a particular board (and hopefully this never happens).
also, I don't think any other MIPS boards are documented bu if you
insist, I can either add it in
Documentation/devicetree/bindings/mips/mscc.txt or create a new file to
list all the mips board compatibles.
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Feb 27, 2018 at 04:54:44PM +0100, Alexandre Belloni wrote:
> On 14/02/2018 at 17:00:42 +0000, James Hogan wrote:
> > On Tue, Jan 16, 2018 at 11:12:38AM +0100, Alexandre Belloni wrote:
> > > Add a device tree for the Microsemi Ocelot PCB123 evaluation board.
> > >
> > > Signed-off-by: Alexandre Belloni <[email protected]>
> >
> > Please Cc DT folk.
> >
>
> I can do but again, I don't think they care.
>
> > > diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> > > new file mode 100644
> > > index 000000000000..42bd404471f6
> > > --- /dev/null
> > > +++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> > > @@ -0,0 +1,27 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> > > +/* Copyright (c) 2017 Microsemi Corporation */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "ocelot.dtsi"
> > > +
> > > +/ {
> > > + compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
> >
> > Should mscc,ocelot-pcb123 be added to the mscc DT binding documentation
> > in the other patch?
> >
>
> On ARM at least, we don't document the board compatibles because this
> will be a huge list without much benefit as they are mostly unused.
> Still, it is nice to have in case something specific needs to be done
> for a particular board (and hopefully this never happens).
>
> also, I don't think any other MIPS boards are documented bu if you
> insist, I can either add it in
> Documentation/devicetree/bindings/mips/mscc.txt or create a new file to
> list all the mips board compatibles.
I don't insist. It was a genuine question :-)
Thanks
James
On 16 January 2018 at 11:12, Alexandre Belloni
<[email protected]> wrote:
> Add a device tree include file for the Microsemi Ocelot SoC.
>
> Signed-off-by: Alexandre Belloni <[email protected]>
> ---
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/mscc/Makefile | 4 ++
> arch/mips/boot/dts/mscc/ocelot.dtsi | 110 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 115 insertions(+)
> create mode 100644 arch/mips/boot/dts/mscc/Makefile
> create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi
>
> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> index e2c6f131c8eb..1e79cab8e269 100644
> --- a/arch/mips/boot/dts/Makefile
> +++ b/arch/mips/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += cavium-octeon
> subdir-y += img
> subdir-y += ingenic
> subdir-y += lantiq
> +subdir-y += mscc
> subdir-y += mti
> subdir-y += netlogic
> subdir-y += ni
> diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
> new file mode 100644
> index 000000000000..f0a155a74e02
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/Makefile
> @@ -0,0 +1,4 @@
> +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
> +
> +# Force kbuild to make empty built-in.o if necessary
> +obj- += dummy.o
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> new file mode 100644
> index 000000000000..b2f936e1fbb9
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -0,0 +1,110 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/* Copyright (c) 2017 Microsemi Corporation */
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "mscc,ocelot";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mips-hpt-frequency = <250000000>;
> +
> + cpu@0 {
> + compatible = "mscc,ocelot";
You are using the same compatible string for the whole chip as well as
the cpu core of it, this doesn't seem right.
Also is this really a custom cpu core? Your product brief suggests
this is a "normal" 24KEc MIPS CPU, at least for ocelot-10 (VSC7514).
So something like "mips,mips24KEc" might be more appropriate here.
Regards
Jonas
On 27/02/2018 at 22:01:37 +0100, Jonas Gorski wrote:
> On 16 January 2018 at 11:12, Alexandre Belloni
> <[email protected]> wrote:
> > Add a device tree include file for the Microsemi Ocelot SoC.
> >
> > Signed-off-by: Alexandre Belloni <[email protected]>
> > ---
> > arch/mips/boot/dts/Makefile | 1 +
> > arch/mips/boot/dts/mscc/Makefile | 4 ++
> > arch/mips/boot/dts/mscc/ocelot.dtsi | 110 ++++++++++++++++++++++++++++++++++++
> > 3 files changed, 115 insertions(+)
> > create mode 100644 arch/mips/boot/dts/mscc/Makefile
> > create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi
> >
> > diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> > index e2c6f131c8eb..1e79cab8e269 100644
> > --- a/arch/mips/boot/dts/Makefile
> > +++ b/arch/mips/boot/dts/Makefile
> > @@ -4,6 +4,7 @@ subdir-y += cavium-octeon
> > subdir-y += img
> > subdir-y += ingenic
> > subdir-y += lantiq
> > +subdir-y += mscc
> > subdir-y += mti
> > subdir-y += netlogic
> > subdir-y += ni
> > diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
> > new file mode 100644
> > index 000000000000..f0a155a74e02
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/mscc/Makefile
> > @@ -0,0 +1,4 @@
> > +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
> > +
> > +# Force kbuild to make empty built-in.o if necessary
> > +obj- += dummy.o
> > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> > new file mode 100644
> > index 000000000000..b2f936e1fbb9
> > --- /dev/null
> > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> > @@ -0,0 +1,110 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> > +/* Copyright (c) 2017 Microsemi Corporation */
> > +
> > +/ {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "mscc,ocelot";
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + mips-hpt-frequency = <250000000>;
> > +
> > + cpu@0 {
> > + compatible = "mscc,ocelot";
>
> You are using the same compatible string for the whole chip as well as
> the cpu core of it, this doesn't seem right.
>
> Also is this really a custom cpu core? Your product brief suggests
> this is a "normal" 24KEc MIPS CPU, at least for ocelot-10 (VSC7514).
> So something like "mips,mips24KEc" might be more appropriate here.
>
Indeed, that is something I forgot to change before sending.
>
> Regards
> Jonas
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com