There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
transfer to be send twice in DMA mode. Please get more information from:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
new sdma ram script which works in XCH mode as PIO inside sdma instead
of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
exist on all legacy i.mx6/7 soc family before i.mx6ul.
NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
or not.
The first two reverted patches should be the same issue, though, it
seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
have the chance to test this patch set if could fix their issues.
Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
on i.mx8mm because the event id is zero.
PS:
Please get sdma firmware from below linux-firmware and copy it to your
local rootfs /lib/firmware/imx/sdma.
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/imx/sdma
v2:
1.Add commit log for reverted patches.
2.Add comment for 'ecspi_fixed' in sdma driver.
3.Add 'fsl,imx6sll-ecspi' compatible instead of 'fsl,imx6ul-ecspi'
rather than remove.
v3:
1.Confirm with design team make sure ERR009165 fixed on i.mx6ul/i.mx6ull
/i.mx6sll, not fixed on i.mx8m/8mm and other i.mx6/7 legacy chips.
Correct dts related dts patch in v2.
2.Clean eratta information in binding doc and new 'tx_glitch_fixed' flag
in spi-imx driver to state ERR009165 fixed or not.
3.Enlarge burst size to fifo size for tx since tx_wml set to 0 in the
errata workaroud, thus improve performance as possible.
v4:
1.Add Ack tag from Mark and Vinod
2.Remove checking 'event_id1' zero as 'event_id0'.
v5:
1.Add the last patch for compatible with the current uart driver which
using rom script, so both uart ram script and rom script supported
in latest firmware, by default uart rom script used. UART driver
will be broken without this patch.
v6:
1.Resend after rebase the latest next branch.
2.Remove below No.13~No.15 patches of v5 because they were mergered.
ARM: dts: imx6ul: add dma support on ecspi
ARM: dts: imx6sll: correct sdma compatible
arm64: defconfig: Enable SDMA on i.mx8mq/8mm
3.Revert "dmaengine: imx-sdma: fix context cache" since
'context_loaded' removed.
v7:
1.Put the last patch 13/13 'Revert "dmaengine: imx-sdma: fix context
cache"' to the ahead of 03/13 'Revert "dmaengine: imx-sdma: refine
to load context only once" so that no building waring during comes out
during bisect.
2.Address Sascha's comments, including eliminating any i.mx6sx in this
series, adding new 'is_imx6ul_ecspi()' instead imx in imx51 and taking
care SMC bit for PIO.
3.Add back missing 'Reviewed-by' tag on 08/15(v5):09/13(v7)
'spi: imx: add new i.mx6ul compatible name in binding doc'
Robin Gong (13):
Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core"
Revert "ARM: dts: imx6: Use correct SDMA script for SPI cores"
Revert "dmaengine: imx-sdma: fix context cache"
Revert "dmaengine: imx-sdma: refine to load context only once"
dmaengine: imx-sdma: remove dupilicated sdma_load_context
dmaengine: imx-sdma: add mcu_2_ecspi script
spi: imx: fix ERR009165
spi: imx: remove ERR009165 workaround on i.mx6ul
spi: imx: add new i.mx6ul compatible name in binding doc
dmaengine: imx-sdma: remove ERR009165 on i.mx6ul
dma: imx-sdma: add i.mx6ul compatible name
dmaengine: imx-sdma: fix ecspi1 rx dma not work on i.mx8mm
dmaengine: imx-sdma: add uart rom script
.../devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
.../devicetree/bindings/spi/fsl-imx-cspi.txt | 1 +
arch/arm/boot/dts/imx6q.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl.dtsi | 8 +--
drivers/dma/imx-sdma.c | 67 ++++++++++++++--------
drivers/spi/spi-imx.c | 61 +++++++++++++++++---
include/linux/platform_data/dma-imx-sdma.h | 8 ++-
7 files changed, 108 insertions(+), 40 deletions(-)
--
2.7.4
There are two ways for SDMA accessing SPBA devices: one is SDMA->AIPS
->SPBA(masterA port), another is SDMA->SPBA(masterC port). Please refer
to the 'Figure 58-1. i.MX 6Dual/6Quad SPBA connectivity' of i.mx6DQ
Reference Manual. SDMA provide the corresponding app_2_mcu/mcu_2_app and
shp_2_mcu/mcu_2_shp script for such two options. So both AIPS and SPBA
scripts should keep the same behaviour, the issue only caught in AIPS
script sounds not solide.
The issue is more likely as the ecspi errata
ERR009165(http://www.nxp.com/docs/en/errata/IMX6DQCE.pdf):
eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to
be sent twice
So revert commit 'df07101e1c4a' firstly.
Signed-off-by: Robin Gong <[email protected]>
---
arch/arm/boot/dts/imx6q.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 78a4d64..afdd9eb 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -177,7 +177,7 @@
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
- dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
+ dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
--
2.7.4
There are two ways for SDMA accessing SPBA devices: one is SDMA->AIPS
->SPBA(masterA port), another is SDMA->SPBA(masterC port). Please refer
to the 'Figure 58-1. i.MX 6Dual/6Quad SPBA connectivity' of i.mx6DQ
Reference Manual. SDMA provide the corresponding app_2_mcu/mcu_2_app and
shp_2_mcu/mcu_2_shp script for such two options. So both AIPS and SPBA
scripts should keep the same behaviour, the issue only caught in AIPS
script sounds not solide.
The issue is more likely as the ecspi errata
ERR009165(http://www.nxp.com/docs/en/errata/IMX6DQCE.pdf):
eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to
be sent twice
So revert commit 'dd4b487b32a3' firstly.
Signed-off-by: Robin Gong <[email protected]>
---
arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 98da446..4a50331 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -337,7 +337,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
<&clks IMX6QDL_CLK_ECSPI1>;
clock-names = "ipg", "per";
- dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
+ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -351,7 +351,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI2>,
<&clks IMX6QDL_CLK_ECSPI2>;
clock-names = "ipg", "per";
- dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
+ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -365,7 +365,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI3>,
<&clks IMX6QDL_CLK_ECSPI3>;
clock-names = "ipg", "per";
- dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
+ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -379,7 +379,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI4>,
<&clks IMX6QDL_CLK_ECSPI4>;
clock-names = "ipg", "per";
- dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
+ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
--
2.7.4
This reverts commit d288bddd8374e0a043ac9dde64a1ae6a09411d74, since
'context_loaded' finally removed.
Signed-off-by: Robin Gong <[email protected]>
---
drivers/dma/imx-sdma.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 4d4477d..3d4aac9 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1338,7 +1338,6 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
sdmac->event_id0 = 0;
sdmac->event_id1 = 0;
- sdmac->context_loaded = false;
sdma_set_channel_priority(sdmac, 0);
--
2.7.4
This reverts commit ad0d92d7ba6aecbe2705907c38ff8d8be4da1e9c, because
in spi-imx case, burst length may be changed dynamically.
Signed-off-by: Robin Gong <[email protected]>
---
drivers/dma/imx-sdma.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 3d4aac9..397f11d 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -377,7 +377,6 @@ struct sdma_channel {
unsigned long watermark_level;
u32 shp_addr, per_addr;
enum dma_status status;
- bool context_loaded;
struct imx_dma_data data;
struct work_struct terminate_worker;
};
@@ -984,9 +983,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
int ret;
unsigned long flags;
- if (sdmac->context_loaded)
- return 0;
-
if (sdmac->direction == DMA_DEV_TO_MEM)
load_address = sdmac->pc_from_device;
else if (sdmac->direction == DMA_DEV_TO_DEV)
@@ -1029,8 +1025,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
- sdmac->context_loaded = true;
-
return ret;
}
@@ -1069,7 +1063,6 @@ static void sdma_channel_terminate_work(struct work_struct *work)
vchan_get_all_descriptors(&sdmac->vc, &head);
spin_unlock_irqrestore(&sdmac->vc.lock, flags);
vchan_dma_desc_free_list(&sdmac->vc, &head);
- sdmac->context_loaded = false;
}
static int sdma_terminate_all(struct dma_chan *chan)
--
2.7.4
Change to XCH mode even in dma mode, please refer to the below
errata:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Mark Brown <[email protected]>
---
drivers/spi/spi-imx.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index f4f28a4..70df8e6 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -585,8 +585,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
- if (spi_imx->usedma)
- ctrl |= MX51_ECSPI_CTRL_SMC;
+ /* ERR009165: work in XHC mode as PIO */
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -617,7 +617,7 @@ static void mx51_setup_wml(struct spi_imx_data *spi_imx)
* and enable DMA request.
*/
writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
- MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
+ MX51_ECSPI_DMA_TX_WML(0) |
MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
@@ -1171,7 +1171,11 @@ static int spi_imx_dma_configure(struct spi_master *master)
tx.direction = DMA_MEM_TO_DEV;
tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
tx.dst_addr_width = buswidth;
- tx.dst_maxburst = spi_imx->wml;
+ /*
+ * For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
+ * to speed up fifo filling as possible.
+ */
+ tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
ret = dmaengine_slave_config(master->dma_tx, &tx);
if (ret) {
dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
@@ -1265,10 +1269,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
{
int ret;
- /* use pio mode for i.mx6dl chip TKT238285 */
- if (of_machine_is_compatible("fsl,imx6dl"))
- return 0;
-
spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
/* Prepare for TX DMA: */
--
2.7.4
ERR009165 fixed on i.mx6ul/6ull/6sll. All other i.mx6/7 and
i.mx8m/8mm still need this errata. Please refer to nxp official
errata document from https://www.nxp.com/ .
For removing workaround on those chips. Add new i.mx6ul type.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Mark Brown <[email protected]>
---
drivers/spi/spi-imx.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 50 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 70df8e6..a57edcb 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -57,6 +57,7 @@ enum spi_imx_devtype {
IMX35_CSPI, /* CSPI on all i.mx except above */
IMX51_ECSPI, /* ECSPI on i.mx51 */
IMX53_ECSPI, /* ECSPI on i.mx53 and later */
+ IMX6UL_ECSPI, /* ERR009165 fix from i.mx6ul */
};
struct spi_imx_data;
@@ -75,6 +76,11 @@ struct spi_imx_devtype_data {
bool has_slavemode;
unsigned int fifo_size;
bool dynamic_burst;
+ /*
+ * ERR009165 fixed or not:
+ * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+ */
+ bool tx_glitch_fixed;
enum spi_imx_devtype devtype;
};
@@ -131,6 +137,11 @@ static inline int is_imx51_ecspi(struct spi_imx_data *d)
return d->devtype_data->devtype == IMX51_ECSPI;
}
+static inline int is_imx6ul_ecspi(struct spi_imx_data *d)
+{
+ return d->devtype_data->devtype == IMX6UL_ECSPI;
+}
+
static inline int is_imx53_ecspi(struct spi_imx_data *d)
{
return d->devtype_data->devtype == IMX53_ECSPI;
@@ -585,8 +596,14 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
- /* ERR009165: work in XHC mode as PIO */
- ctrl &= ~MX51_ECSPI_CTRL_SMC;
+ /*
+ * ERR009165: work in XHC mode instead of SMC as PIO on the chips
+ * before i.mx6ul.
+ */
+ if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
+ ctrl |= MX51_ECSPI_CTRL_SMC;
+ else
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -612,12 +629,16 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
static void mx51_setup_wml(struct spi_imx_data *spi_imx)
{
+ u32 tx_wml = 0;
+
+ if (spi_imx->devtype_data->tx_glitch_fixed)
+ tx_wml = spi_imx->wml;
/*
* Configure the DMA register: setup the watermark
* and enable DMA request.
*/
writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
- MX51_ECSPI_DMA_TX_WML(0) |
+ MX51_ECSPI_DMA_TX_WML(tx_wml) |
MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
@@ -1009,6 +1030,23 @@ static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
.devtype = IMX53_ECSPI,
};
+static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
+ .intctrl = mx51_ecspi_intctrl,
+ .prepare_message = mx51_ecspi_prepare_message,
+ .prepare_transfer = mx51_ecspi_prepare_transfer,
+ .trigger = mx51_ecspi_trigger,
+ .rx_available = mx51_ecspi_rx_available,
+ .reset = mx51_ecspi_reset,
+ .setup_wml = mx51_setup_wml,
+ .fifo_size = 64,
+ .has_dmamode = true,
+ .dynamic_burst = true,
+ .has_slavemode = true,
+ .tx_glitch_fixed = true,
+ .disable = mx51_ecspi_disable,
+ .devtype = IMX6UL_ECSPI,
+};
+
static const struct platform_device_id spi_imx_devtype[] = {
{
.name = "imx1-cspi",
@@ -1032,6 +1070,9 @@ static const struct platform_device_id spi_imx_devtype[] = {
.name = "imx53-ecspi",
.driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
}, {
+ .name = "imx6ul-ecspi",
+ .driver_data = (kernel_ulong_t) &imx6ul_ecspi_devtype_data,
+ }, {
/* sentinel */
}
};
@@ -1044,6 +1085,7 @@ static const struct of_device_id spi_imx_dt_ids[] = {
{ .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
{ .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
{ .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
+ { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
@@ -1175,7 +1217,10 @@ static int spi_imx_dma_configure(struct spi_master *master)
* For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
* to speed up fifo filling as possible.
*/
- tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
+ if (spi_imx->devtype_data->tx_glitch_fixed)
+ tx.dst_maxburst = spi_imx->wml;
+ else
+ tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
ret = dmaengine_slave_config(master->dma_tx, &tx);
if (ret) {
dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
@@ -1659,7 +1704,7 @@ static int spi_imx_probe(struct platform_device *pdev)
spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
| SPI_NO_CS;
if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
- is_imx53_ecspi(spi_imx))
+ is_imx53_ecspi(spi_imx) || is_imx6ul_ecspi(spi_imx))
spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
spi_imx->spi_drctl = spi_drctl;
--
2.7.4
Add i.mx6ul compatible name in binding doc.
Signed-off-by: Robin Gong <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index c9e9740..12c316f 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -9,6 +9,7 @@ Required properties:
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
"fsl,imx7d-sdma"
+ "fsl,imx6ul-sdma"
"fsl,imx8mq-sdma"
"fsl,imx8mm-sdma"
"fsl,imx8mn-sdma"
--
2.7.4
Because the number of ecspi1 rx event on i.mx8mm is 0, the condition
check ignore such special case without dma channel enabled, which caused
ecspi1 rx works failed. Actually, no need to check event_id0/event_id1
and replace checking 'event_id1' with 'DMA_DEV_TO_DEV', so that configure
event_id1 only in case DEV_TO_DEV.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 22f9f20..9d49aaf 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1183,7 +1183,7 @@ static int sdma_config_channel(struct dma_chan *chan)
if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
/* Handle multiple event channels differently */
- if (sdmac->event_id1) {
+ if (sdmac->direction == DMA_DEV_TO_DEV) {
if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac);
@@ -1351,9 +1351,9 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
sdma_channel_synchronize(chan);
- if (sdmac->event_id0 >= 0)
- sdma_event_disable(sdmac, sdmac->event_id0);
- if (sdmac->event_id1)
+ sdma_event_disable(sdmac, sdmac->event_id0);
+
+ if (sdmac->direction == DMA_DEV_TO_DEV)
sdma_event_disable(sdmac, sdmac->event_id1);
sdmac->event_id0 = 0;
@@ -1651,13 +1651,11 @@ static int sdma_config(struct dma_chan *chan,
memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
/* Set ENBLn earlier to make sure dma request triggered after that */
- if (sdmac->event_id0 >= 0) {
- if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
- return -EINVAL;
- sdma_event_enable(sdmac, sdmac->event_id0);
- }
+ if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
+ return -EINVAL;
+ sdma_event_enable(sdmac, sdmac->event_id0);
- if (sdmac->event_id1) {
+ if (sdmac->direction == DMA_DEV_TO_DEV) {
if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
return -EINVAL;
sdma_event_enable(sdmac, sdmac->event_id1);
--
2.7.4
For the compatibility of NXP internal legacy kernel before 4.19 which
is based on uart ram script and upstreaming kernel based on uart rom
script, add both uart ram/rom script in latest sdma firmware. By default
uart rom script used.
Besides, add two multi-fifo scripts for SAI/PDM on i.mx8m/8mm and add
back qspi script miss for v4(i.mx7d/8m/8mm family, but v3 is for i.mx6).
rom script:
uart_2_mcu_addr
uartsh_2_mcu_addr /* through spba bus */
am script:
uart_2_mcu_ram_addr
uartsh_2_mcu_ram_addr /* through spba bus */
Please get latest sdma firmware from the below and put them into the path
(/lib/firmware/imx/sdma/):
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
/tree/imx/sdma
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 4 ++--
include/linux/platform_data/dma-imx-sdma.h | 8 ++++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 9d49aaf..01422e7 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1718,8 +1718,8 @@ static void sdma_issue_pending(struct dma_chan *chan)
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
-#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
-#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45
+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46
static void sdma_add_scripts(struct sdma_engine *sdma,
const struct sdma_script_start_addrs *addr)
diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h
index 30e676b..e12d2e8 100644
--- a/include/linux/platform_data/dma-imx-sdma.h
+++ b/include/linux/platform_data/dma-imx-sdma.h
@@ -20,12 +20,12 @@ struct sdma_script_start_addrs {
s32 per_2_firi_addr;
s32 mcu_2_firi_addr;
s32 uart_2_per_addr;
- s32 uart_2_mcu_addr;
+ s32 uart_2_mcu_ram_addr;
s32 per_2_app_addr;
s32 mcu_2_app_addr;
s32 per_2_per_addr;
s32 uartsh_2_per_addr;
- s32 uartsh_2_mcu_addr;
+ s32 uartsh_2_mcu_ram_addr;
s32 per_2_shp_addr;
s32 mcu_2_shp_addr;
s32 ata_2_mcu_addr;
@@ -52,6 +52,10 @@ struct sdma_script_start_addrs {
s32 zcanfd_2_mcu_addr;
s32 zqspi_2_mcu_addr;
s32 mcu_2_ecspi_addr;
+ s32 mcu_2_sai_addr;
+ s32 sai_2_mcu_addr;
+ s32 uart_2_mcu_addr;
+ s32 uartsh_2_mcu_addr;
/* End of v3 array */
s32 mcu_2_zqspi_addr;
/* End of v4 array */
--
2.7.4
ERR009165 fixed from i.mx6ul, add its compatible name in binding doc.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Mark Brown <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
index 33bc58f..0a529ba 100644
--- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
+++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
@@ -10,6 +10,7 @@ Required properties:
- "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
- "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
- "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
+ - "fsl,imx6ul-ecspi" for SPI compatible with the one integrated on i.MX6UL and later Soc
- "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8MQ
- "fsl,imx8mm-ecspi" for SPI compatible with the one integrated on i.MX8MM
- "fsl,imx8mn-ecspi" for SPI compatible with the one integrated on i.MX8MN
--
2.7.4
Since sdma_transfer_init() will do sdma_load_context before any
sdma transfer, no need once more in sdma_config_channel().
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 397f11d..69ea44d 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1137,7 +1137,6 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
static int sdma_config_channel(struct dma_chan *chan)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
- int ret;
sdma_disable_channel(chan);
@@ -1177,9 +1176,7 @@ static int sdma_config_channel(struct dma_chan *chan)
sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
}
- ret = sdma_load_context(sdmac);
-
- return ret;
+ return 0;
}
static int sdma_set_channel_priority(struct sdma_channel *sdmac,
--
2.7.4
Add mcu_2_ecspi script to fix ecspi errata ERR009165.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 69ea44d..e034375 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -920,6 +920,9 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
break;
case IMX_DMATYPE_CSPI:
+ per_2_emi = sdma->script_addrs->app_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
+ break;
case IMX_DMATYPE_EXT:
case IMX_DMATYPE_SSI:
case IMX_DMATYPE_SAI:
--
2.7.4
ECSPI issue fixed from i.mx6ul at hardware level, no need
ERR009165 anymore on those chips such as i.mx8mq.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index e034375..22f9f20 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -419,6 +419,13 @@ struct sdma_driver_data {
int num_events;
struct sdma_script_start_addrs *script_addrs;
bool check_ratio;
+ /*
+ * ecspi ERR009165 fixed should be done in sdma script
+ * and it has been fixed in soc from i.mx6ul.
+ * please get more information from the below link:
+ * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+ */
+ bool ecspi_fixed;
};
struct sdma_engine {
@@ -539,6 +546,13 @@ static struct sdma_driver_data sdma_imx6q = {
.script_addrs = &sdma_script_imx6q,
};
+static struct sdma_driver_data sdma_imx6ul = {
+ .chnenbl0 = SDMA_CHNENBL0_IMX35,
+ .num_events = 48,
+ .script_addrs = &sdma_script_imx6q,
+ .ecspi_fixed = true,
+};
+
static struct sdma_script_start_addrs sdma_script_imx7d = {
.ap_2_ap_addr = 644,
.uart_2_mcu_addr = 819,
@@ -587,6 +601,9 @@ static const struct platform_device_id sdma_devtypes[] = {
.name = "imx7d-sdma",
.driver_data = (unsigned long)&sdma_imx7d,
}, {
+ .name = "imx6ul-sdma",
+ .driver_data = (unsigned long)&sdma_imx6ul,
+ }, {
.name = "imx8mq-sdma",
.driver_data = (unsigned long)&sdma_imx8mq,
}, {
@@ -603,6 +620,7 @@ static const struct of_device_id sdma_dt_ids[] = {
{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
{ .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
+ { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
{ .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
{ /* sentinel */ }
};
@@ -1169,8 +1187,17 @@ static int sdma_config_channel(struct dma_chan *chan)
if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac);
- } else
+ } else {
+ /*
+ * ERR009165 fixed from i.mx6ul, no errata need,
+ * set bit31 to let sdma script skip the errata.
+ */
+ if (sdmac->peripheral_type == IMX_DMATYPE_CSPI &&
+ sdmac->direction == DMA_MEM_TO_DEV &&
+ sdmac->sdma->drvdata->ecspi_fixed)
+ __set_bit(31, &sdmac->watermark_level);
__set_bit(sdmac->event_id0, sdmac->event_mask);
+ }
/* Address */
sdmac->shp_addr = sdmac->per_address;
--
2.7.4
In the subject: s/dupilicated/duplicated/
Sascha
On Tue, May 12, 2020 at 01:32:28AM +0800, Robin Gong wrote:
> Since sdma_transfer_init() will do sdma_load_context before any
> sdma transfer, no need once more in sdma_config_channel().
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Vinod Koul <[email protected]>
> ---
> drivers/dma/imx-sdma.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 397f11d..69ea44d 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -1137,7 +1137,6 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
> static int sdma_config_channel(struct dma_chan *chan)
> {
> struct sdma_channel *sdmac = to_sdma_chan(chan);
> - int ret;
>
> sdma_disable_channel(chan);
>
> @@ -1177,9 +1176,7 @@ static int sdma_config_channel(struct dma_chan *chan)
> sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
> }
>
> - ret = sdma_load_context(sdmac);
> -
> - return ret;
> + return 0;
> }
>
> static int sdma_set_channel_priority(struct sdma_channel *sdmac,
> --
> 2.7.4
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Wed, 13 May 2020 at 08:07, Sascha Hauer <[email protected]> wrote:
>
> On Tue, May 12, 2020 at 01:32:26AM +0800, Robin Gong wrote:
> > This reverts commit d288bddd8374e0a043ac9dde64a1ae6a09411d74, since
> > 'context_loaded' finally removed.
> >
> > Signed-off-by: Robin Gong <[email protected]>
> > ---
>
> I think this can safely be folded into the next patch which makes it
> more clear what is happening.
>
Agreed,
not only that but having 2 separate patches also means that the bug
that was fixed by the commit being reverted could reappear during
bisection.
More generally I think reverts should be reserved for commits that
later turn out to be wrong or unneeded (ie should never really have
been applied).
If they were OK at the time but later become unnecessary due to other
code changes I think all the related modifications should be done in a
single normal non revert patch.
Martin
On Tue, May 12, 2020 at 01:32:30AM +0800, Robin Gong wrote:
> Change to XCH mode even in dma mode, please refer to the below
> errata:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
This patch is the one bisecting will end up with when somebody uses an
older SDMA firmware or the ROM scripts. It should have a better
description what happens and what should be done about it.
Sascha
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Mark Brown <[email protected]>
> ---
> drivers/spi/spi-imx.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> index f4f28a4..70df8e6 100644
> --- a/drivers/spi/spi-imx.c
> +++ b/drivers/spi/spi-imx.c
> @@ -585,8 +585,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
> ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> spi_imx->spi_bus_clk = clk;
>
> - if (spi_imx->usedma)
> - ctrl |= MX51_ECSPI_CTRL_SMC;
> + /* ERR009165: work in XHC mode as PIO */
> + ctrl &= ~MX51_ECSPI_CTRL_SMC;
>
> writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
>
> @@ -617,7 +617,7 @@ static void mx51_setup_wml(struct spi_imx_data *spi_imx)
> * and enable DMA request.
> */
> writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> - MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
> + MX51_ECSPI_DMA_TX_WML(0) |
> MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> @@ -1171,7 +1171,11 @@ static int spi_imx_dma_configure(struct spi_master *master)
> tx.direction = DMA_MEM_TO_DEV;
> tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
> tx.dst_addr_width = buswidth;
> - tx.dst_maxburst = spi_imx->wml;
> + /*
> + * For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
> + * to speed up fifo filling as possible.
> + */
> + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
> ret = dmaengine_slave_config(master->dma_tx, &tx);
> if (ret) {
> dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
> @@ -1265,10 +1269,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
> {
> int ret;
>
> - /* use pio mode for i.mx6dl chip TKT238285 */
> - if (of_machine_is_compatible("fsl,imx6dl"))
> - return 0;
> -
> spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
>
> /* Prepare for TX DMA: */
> --
> 2.7.4
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Tue, May 12, 2020 at 01:32:30AM +0800, Robin Gong wrote:
> Change to XCH mode even in dma mode, please refer to the below
> errata:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Mark Brown <[email protected]>
> ---
> drivers/spi/spi-imx.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> index f4f28a4..70df8e6 100644
> --- a/drivers/spi/spi-imx.c
> +++ b/drivers/spi/spi-imx.c
> @@ -585,8 +585,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
> ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> spi_imx->spi_bus_clk = clk;
>
> - if (spi_imx->usedma)
> - ctrl |= MX51_ECSPI_CTRL_SMC;
> + /* ERR009165: work in XHC mode as PIO */
> + ctrl &= ~MX51_ECSPI_CTRL_SMC;
>
> writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
>
> @@ -617,7 +617,7 @@ static void mx51_setup_wml(struct spi_imx_data *spi_imx)
> * and enable DMA request.
> */
> writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> - MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
> + MX51_ECSPI_DMA_TX_WML(0) |
> MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> @@ -1171,7 +1171,11 @@ static int spi_imx_dma_configure(struct spi_master *master)
> tx.direction = DMA_MEM_TO_DEV;
> tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
> tx.dst_addr_width = buswidth;
> - tx.dst_maxburst = spi_imx->wml;
> + /*
> + * For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
> + * to speed up fifo filling as possible.
> + */
> + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
In the next patch this is changed again to:
+ if (spi_imx->devtype_data->tx_glitch_fixed)
+ tx.dst_maxburst = spi_imx->wml;
+ else
+ tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
So with tx_glitch_fixed we end up with tx.dst_maxburst being the same
as two patches before which is rather confusing. Better introduce
tx_glitch_fixed in this patch, or maybe even merge this patch and the
next one.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Tue, May 12, 2020 at 01:32:23AM +0800, Robin Gong wrote:
> There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> transfer to be send twice in DMA mode. Please get more information from:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
> new sdma ram script which works in XCH mode as PIO inside sdma instead
> of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
> exist on all legacy i.mx6/7 soc family before i.mx6ul.
> NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
> 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
> still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
> for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
> or not.
> The first two reverted patches should be the same issue, though, it
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the event id is zero.
It's not nice to break SPI support when the new firmware is not present
and I think we can do better. Wouldn't it be possible to fall back to PIO
in this case?
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On 2020/05/13 14:06 Sascha Hauer <[email protected]> wrote:
> Subject: Re: [PATCH v7 RESEND 05/13] dmaengine: imx-sdma: remove
> dupilicated sdma_load_context
>
> In the subject: s/dupilicated/duplicated/
Will fix typo in v8.
On 2020/05/13 Fuzzey, Martin <[email protected]> wrote:
> On Wed, 13 May 2020 at 08:07, Sascha Hauer <[email protected]>
> wrote:
> >
> > On Tue, May 12, 2020 at 01:32:26AM +0800, Robin Gong wrote:
> > > This reverts commit d288bddd8374e0a043ac9dde64a1ae6a09411d74, since
> > > 'context_loaded' finally removed.
> > >
> > > Signed-off-by: Robin Gong <[email protected]>
> > > ---
> >
> > I think this can safely be folded into the next patch which makes it
> > more clear what is happening.
> >
>
> Agreed,
> not only that but having 2 separate patches also means that the bug that was
> fixed by the commit being reverted could reappear during bisection.
>
> More generally I think reverts should be reserved for commits that later turn
> out to be wrong or unneeded (ie should never really have been applied).
> If they were OK at the time but later become unnecessary due to other code
> changes I think all the related modifications should be done in a single normal
> non revert patch.
Okay, will remove it in v8.
On 2020/05/13 Sascha Hauer <[email protected]> wrote:
> On Tue, May 12, 2020 at 01:32:23AM +0800, Robin Gong wrote:
> > There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> > transfer to be send twice in DMA mode. Please get more information from:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
> >
> nxp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=02%7C01%7C
> yibin.g
> >
> ong%40nxp.com%7C4276d42955334886056508d7f70e18af%7C686ea1d3bc2b4
> c6fa92
> >
> cd99c5c301635%7C0%7C1%7C637249512224944620&sdata=vh0e3BER01
> 02648t9HRe14h%2BaE9m%2BAlJ5Smd6v%2B9AhM%3D&reserved=0. The
> workaround is adding new sdma ram script which works in XCH mode as PIO
> inside sdma instead of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0.
> The issue should be exist on all legacy i.mx6/7 soc family before i.mx6ul.
> > NXP fix this design issue from i.mx6ul, so newer chips including
> > i.mx6ul/ 6ull/6sll do not need this workaroud anymore. All other
> > i.mx6/7/8 chips still need this workaroud. This patch set add new
> 'fsl,imx6ul-ecspi'
> > for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need
> > errata or not.
> > The first two reverted patches should be the same issue, though, it
> > seems 'fixed' by changing to other shp script. Hope Sean or Sascha
> > could have the chance to test this patch set if could fix their issues.
> > Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> > on i.mx8mm because the event id is zero.
>
> It's not nice to break SPI support when the new firmware is not present and I
> think we can do better. Wouldn't it be possible to fall back to PIO in this case?
I'm afraid that's not easy since spi driver don't know which firmware used. Could I add some comments in commit log?
On Wed, May 13, 2020 at 08:38:26AM +0000, Robin Gong wrote:
> On 2020/05/13 Sascha Hauer <[email protected]> wrote:
> > This patch is the one bisecting will end up with when somebody uses an older
> > SDMA firmware or the ROM scripts. It should have a better description what
> > happens and what should be done about it.
> Emm..That's true. Timeout will be caught in such case, hence, maybe we can fall back it to pio always.
With my patch applied sdma_load_context() will fail. I don't know how
exactly this hits into the SPI driver, but it won't be a timeout.
Sascha
> > >
> > > Signed-off-by: Robin Gong <[email protected]>
> > > Acked-by: Mark Brown <[email protected]>
> > > ---
> > > drivers/spi/spi-imx.c | 16 ++++++++--------
> > > 1 file changed, 8 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > > f4f28a4..70df8e6 100644
> > > --- a/drivers/spi/spi-imx.c
> > > +++ b/drivers/spi/spi-imx.c
> > > @@ -585,8 +585,8 @@ static int mx51_ecspi_prepare_transfer(struct
> > spi_imx_data *spi_imx,
> > > ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> > > spi_imx->spi_bus_clk = clk;
> > >
> > > - if (spi_imx->usedma)
> > > - ctrl |= MX51_ECSPI_CTRL_SMC;
> > > + /* ERR009165: work in XHC mode as PIO */
> > > + ctrl &= ~MX51_ECSPI_CTRL_SMC;
> > >
> > > writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
> > >
> > > @@ -617,7 +617,7 @@ static void mx51_setup_wml(struct spi_imx_data
> > *spi_imx)
> > > * and enable DMA request.
> > > */
> > > writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> > > - MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
> > > + MX51_ECSPI_DMA_TX_WML(0) |
> > > MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> > > MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> > > MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> > @@ -1171,7
> > > +1171,11 @@ static int spi_imx_dma_configure(struct spi_master *master)
> > > tx.direction = DMA_MEM_TO_DEV;
> > > tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
> > > tx.dst_addr_width = buswidth;
> > > - tx.dst_maxburst = spi_imx->wml;
> > > + /*
> > > + * For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
> > > + * to speed up fifo filling as possible.
> > > + */
> > > + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
> > > ret = dmaengine_slave_config(master->dma_tx, &tx);
> > > if (ret) {
> > > dev_err(spi_imx->dev, "TX dma configuration failed with %d\n",
> > > ret); @@ -1265,10 +1269,6 @@ static int spi_imx_sdma_init(struct
> > > device *dev, struct spi_imx_data *spi_imx, {
> > > int ret;
> > >
> > > - /* use pio mode for i.mx6dl chip TKT238285 */
> > > - if (of_machine_is_compatible("fsl,imx6dl"))
> > > - return 0;
> > > -
> > > spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
> > >
> > > /* Prepare for TX DMA: */
> > > --
> > > 2.7.4
> > >
> > >
> >
> > --
> > Pengutronix e.K. |
> > |
> > Steuerwalder Str. 21 |
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pe
> > ngutronix.de%2F&data=02%7C01%7Cyibin.gong%40nxp.com%7C2f49309
> > 819cc4c45418108d7f70e46fb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> > 7C1%7C637249513003506970&sdata=RoLVnDaCfG20i88OmmlpbMH6lZu
> > qqW2CJv4VSSDkPcM%3D&reserved=0 |
> > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0
> > |
> > Amtsgericht Hildesheim, HRA 2686 | Fax:
> > +49-5121-206917-5555 |
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On 2020/05/13 16:48 Sascha Hauer <[email protected]> wrote:
> On Wed, May 13, 2020 at 08:38:26AM +0000, Robin Gong wrote:
> > On 2020/05/13 Sascha Hauer <[email protected]> wrote:
> > > This patch is the one bisecting will end up with when somebody uses
> > > an older SDMA firmware or the ROM scripts. It should have a better
> > > description what happens and what should be done about it.
> > Emm..That's true. Timeout will be caught in such case, hence, maybe we can
> fall back it to pio always.
>
> With my patch applied sdma_load_context() will fail. I don't know how exactly
> this hits into the SPI driver, but it won't be a timeout.
Thanks for your quick test, assume you use ROM firmware, right?
On 2020/05/13 Sascha Hauer <[email protected]> wrote:d
> > drivers/spi/spi-imx.c | 16 ++++++++--------
> > 1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > f4f28a4..70df8e6 100644
> > --- a/drivers/spi/spi-imx.c
> > +++ b/drivers/spi/spi-imx.c
> > @@ -585,8 +585,8 @@ static int mx51_ecspi_prepare_transfer(struct
> spi_imx_data *spi_imx,
> > ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> > spi_imx->spi_bus_clk = clk;
> >
> > - if (spi_imx->usedma)
> > - ctrl |= MX51_ECSPI_CTRL_SMC;
> > + /* ERR009165: work in XHC mode as PIO */
> > + ctrl &= ~MX51_ECSPI_CTRL_SMC;
> >
> > writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
> >
> > @@ -617,7 +617,7 @@ static void mx51_setup_wml(struct spi_imx_data
> *spi_imx)
> > * and enable DMA request.
> > */
> > writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> > - MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
> > + MX51_ECSPI_DMA_TX_WML(0) |
> > MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> > MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> > MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> @@ -1171,7
> > +1171,11 @@ static int spi_imx_dma_configure(struct spi_master *master)
> > tx.direction = DMA_MEM_TO_DEV;
> > tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
> > tx.dst_addr_width = buswidth;
> > - tx.dst_maxburst = spi_imx->wml;
> > + /*
> > + * For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
> > + * to speed up fifo filling as possible.
> > + */
> > + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
>
> In the next patch this is changed again to:
>
> + if (spi_imx->devtype_data->tx_glitch_fixed)
> + tx.dst_maxburst = spi_imx->wml;
> + else
> + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
>
> So with tx_glitch_fixed we end up with tx.dst_maxburst being the same as two
> patches before which is rather confusing. Better introduce tx_glitch_fixed in
> this patch, or maybe even merge this patch and the next one.
Sorry confused you, I should repleace 'tx_wml=0' in the above comments with ' TX_THRESHOLD=0', which means tx transfer dma have to wait all the tx data in tx fifo transferred with ERR009165 rather than generically 'tx_wml' (for example --half fifo size used as TX_THRESHOLD). Obviously TX_THRESHOLD=0 would down performance, so enlarge dst_maxburst to fifo size as PIO with ERR009165. After ERR009165 fixed at HW level. TX_THRESHOLD could be used as common 'spi_imx->wml' so change it back. Will add more detail information in v8.
On Wed, May 13, 2020 at 09:05:33AM +0000, Robin Gong wrote:
> On 2020/05/13 Sascha Hauer <[email protected]> wrote:d
> > > drivers/spi/spi-imx.c | 16 ++++++++--------
> > > 1 file changed, 8 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > > f4f28a4..70df8e6 100644
> > > --- a/drivers/spi/spi-imx.c
> > > +++ b/drivers/spi/spi-imx.c
> > > @@ -585,8 +585,8 @@ static int mx51_ecspi_prepare_transfer(struct
> > spi_imx_data *spi_imx,
> > > ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> > > spi_imx->spi_bus_clk = clk;
> > >
> > > - if (spi_imx->usedma)
> > > - ctrl |= MX51_ECSPI_CTRL_SMC;
> > > + /* ERR009165: work in XHC mode as PIO */
> > > + ctrl &= ~MX51_ECSPI_CTRL_SMC;
> > >
> > > writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
> > >
> > > @@ -617,7 +617,7 @@ static void mx51_setup_wml(struct spi_imx_data
> > *spi_imx)
> > > * and enable DMA request.
> > > */
> > > writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> > > - MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
> > > + MX51_ECSPI_DMA_TX_WML(0) |
> > > MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> > > MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> > > MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> > @@ -1171,7
> > > +1171,11 @@ static int spi_imx_dma_configure(struct spi_master *master)
> > > tx.direction = DMA_MEM_TO_DEV;
> > > tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
> > > tx.dst_addr_width = buswidth;
> > > - tx.dst_maxburst = spi_imx->wml;
> > > + /*
> > > + * For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
> > > + * to speed up fifo filling as possible.
> > > + */
> > > + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
> >
> > In the next patch this is changed again to:
> >
> > + if (spi_imx->devtype_data->tx_glitch_fixed)
> > + tx.dst_maxburst = spi_imx->wml;
> > + else
> > + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
> >
> > So with tx_glitch_fixed we end up with tx.dst_maxburst being the same as two
> > patches before which is rather confusing. Better introduce tx_glitch_fixed in
> > this patch, or maybe even merge this patch and the next one.
> Sorry confused you, I should repleace 'tx_wml=0' in the above comments
> with ' TX_THRESHOLD=0', which means tx transfer dma have to wait all
> the tx data in tx fifo transferred with ERR009165 rather than
> generically 'tx_wml' (for example --half fifo size used as
> TX_THRESHOLD). Obviously TX_THRESHOLD=0 would down performance, so
> enlarge dst_maxburst to fifo size as PIO with ERR009165. After
> ERR009165 fixed at HW level. TX_THRESHOLD could be used as common
> 'spi_imx->wml' so change it back. Will add more detail information in
> v8.
I am not confused, I meant the patches are confusing. What you are doing
is:
No patch:
tx.dst_maxburst = a;
1st patch
tx.dst_maxburst = b;
2nd patch:
if (foo)
tx.dst_maxburst = a;
else
tx.dst_maxburst = b;
It would be better readable and understandable if you did that in one
patch, because that would directly say "Under certain conditions we have
to choose a, otherwise b". That's much better than changing "a" to "b" and
then to "a or b"
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Wed, May 13, 2020 at 08:52:39AM +0000, Robin Gong wrote:
> On 2020/05/13 16:48 Sascha Hauer <[email protected]> wrote:
> > On Wed, May 13, 2020 at 08:38:26AM +0000, Robin Gong wrote:
> > > On 2020/05/13 Sascha Hauer <[email protected]> wrote:
> > > > This patch is the one bisecting will end up with when somebody uses
> > > > an older SDMA firmware or the ROM scripts. It should have a better
> > > > description what happens and what should be done about it.
> > > Emm..That's true. Timeout will be caught in such case, hence, maybe we can
> > fall back it to pio always.
> >
> > With my patch applied sdma_load_context() will fail. I don't know how exactly
> > this hits into the SPI driver, but it won't be a timeout.
> Thanks for your quick test, assume you use ROM firmware, right?
Yes.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Tue, May 12, 2020 at 01:32:26AM +0800, Robin Gong wrote:
> This reverts commit d288bddd8374e0a043ac9dde64a1ae6a09411d74, since
> 'context_loaded' finally removed.
>
> Signed-off-by: Robin Gong <[email protected]>
> ---
> drivers/dma/imx-sdma.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 4d4477d..3d4aac9 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -1338,7 +1338,6 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
>
> sdmac->event_id0 = 0;
> sdmac->event_id1 = 0;
> - sdmac->context_loaded = false;
>
> sdma_set_channel_priority(sdmac, 0);
I think this can safely be folded into the next patch which makes it
more clear what is happening.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On 2020/05/13 Sascha Hauer <[email protected]> wrote:
> On Wed, May 13, 2020 at 08:52:39AM +0000, Robin Gong wrote:
> > On 2020/05/13 16:48 Sascha Hauer <[email protected]> wrote:
> > > On Wed, May 13, 2020 at 08:38:26AM +0000, Robin Gong wrote:
> > > > On 2020/05/13 Sascha Hauer <[email protected]> wrote:
> > > > > This patch is the one bisecting will end up with when somebody
> > > > > uses an older SDMA firmware or the ROM scripts. It should have a
> > > > > better description what happens and what should be done about it.
> > > > Emm..That's true. Timeout will be caught in such case, hence,
> > > > maybe we can
> > > fall back it to pio always.
> > >
> > > With my patch applied sdma_load_context() will fail. I don't know
> > > how exactly this hits into the SPI driver, but it won't be a timeout.
> > Thanks for your quick test, assume you use ROM firmware, right?
>
> Yes.
Would you please have a try with the attached patch which is based this patch set?
On 2020/05/13 Sascha Hauer <[email protected]> wrote:
> This patch is the one bisecting will end up with when somebody uses an older
> SDMA firmware or the ROM scripts. It should have a better description what
> happens and what should be done about it.
Emm..That's true. Timeout will be caught in such case, hence, maybe we can fall back it to pio always.
> >
> > Signed-off-by: Robin Gong <[email protected]>
> > Acked-by: Mark Brown <[email protected]>
> > ---
> > drivers/spi/spi-imx.c | 16 ++++++++--------
> > 1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > f4f28a4..70df8e6 100644
> > --- a/drivers/spi/spi-imx.c
> > +++ b/drivers/spi/spi-imx.c
> > @@ -585,8 +585,8 @@ static int mx51_ecspi_prepare_transfer(struct
> spi_imx_data *spi_imx,
> > ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> > spi_imx->spi_bus_clk = clk;
> >
> > - if (spi_imx->usedma)
> > - ctrl |= MX51_ECSPI_CTRL_SMC;
> > + /* ERR009165: work in XHC mode as PIO */
> > + ctrl &= ~MX51_ECSPI_CTRL_SMC;
> >
> > writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
> >
> > @@ -617,7 +617,7 @@ static void mx51_setup_wml(struct spi_imx_data
> *spi_imx)
> > * and enable DMA request.
> > */
> > writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> > - MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
> > + MX51_ECSPI_DMA_TX_WML(0) |
> > MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> > MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> > MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> @@ -1171,7
> > +1171,11 @@ static int spi_imx_dma_configure(struct spi_master *master)
> > tx.direction = DMA_MEM_TO_DEV;
> > tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
> > tx.dst_addr_width = buswidth;
> > - tx.dst_maxburst = spi_imx->wml;
> > + /*
> > + * For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
> > + * to speed up fifo filling as possible.
> > + */
> > + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
> > ret = dmaengine_slave_config(master->dma_tx, &tx);
> > if (ret) {
> > dev_err(spi_imx->dev, "TX dma configuration failed with %d\n",
> > ret); @@ -1265,10 +1269,6 @@ static int spi_imx_sdma_init(struct
> > device *dev, struct spi_imx_data *spi_imx, {
> > int ret;
> >
> > - /* use pio mode for i.mx6dl chip TKT238285 */
> > - if (of_machine_is_compatible("fsl,imx6dl"))
> > - return 0;
> > -
> > spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
> >
> > /* Prepare for TX DMA: */
> > --
> > 2.7.4
> >
> >
>
> --
> Pengutronix e.K. |
> |
> Steuerwalder Str. 21 |
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pe
> ngutronix.de%2F&data=02%7C01%7Cyibin.gong%40nxp.com%7C2f49309
> 819cc4c45418108d7f70e46fb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> 7C1%7C637249513003506970&sdata=RoLVnDaCfG20i88OmmlpbMH6lZu
> qqW2CJv4VSSDkPcM%3D&reserved=0 |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0
> |
> Amtsgericht Hildesheim, HRA 2686 | Fax:
> +49-5121-206917-5555 |
On 2020/05/13 Sascha Hauer <[email protected]> wrote:
> On Wed, May 13, 2020 at 09:05:33AM +0000, Robin Gong wrote:
> > On 2020/05/13 Sascha Hauer <[email protected]> wrote:d
> > > > drivers/spi/spi-imx.c | 16 ++++++++--------
> > > > 1 file changed, 8 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > > > f4f28a4..70df8e6 100644
> > > > --- a/drivers/spi/spi-imx.c
> > > > +++ b/drivers/spi/spi-imx.c
> > > > @@ -585,8 +585,8 @@ static int mx51_ecspi_prepare_transfer(struct
> > > spi_imx_data *spi_imx,
> > > > ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> > > > spi_imx->spi_bus_clk = clk;
> > > >
> > > > - if (spi_imx->usedma)
> > > > - ctrl |= MX51_ECSPI_CTRL_SMC;
> > > > + /* ERR009165: work in XHC mode as PIO */
> > > > + ctrl &= ~MX51_ECSPI_CTRL_SMC;
> > > >
> > > > writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
> > > >
> > > > @@ -617,7 +617,7 @@ static void mx51_setup_wml(struct spi_imx_data
> > > *spi_imx)
> > > > * and enable DMA request.
> > > > */
> > > > writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> > > > - MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
> > > > + MX51_ECSPI_DMA_TX_WML(0) |
> > > > MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> > > > MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> > > > MX51_ECSPI_DMA_RXTDEN, spi_imx->base +
> MX51_ECSPI_DMA);
> > > @@ -1171,7
> > > > +1171,11 @@ static int spi_imx_dma_configure(struct spi_master
> > > > +*master)
> > > > tx.direction = DMA_MEM_TO_DEV;
> > > > tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
> > > > tx.dst_addr_width = buswidth;
> > > > - tx.dst_maxburst = spi_imx->wml;
> > > > + /*
> > > > + * For ERR009165 with tx_wml = 0 could enlarge burst size to fifo size
> > > > + * to speed up fifo filling as possible.
> > > > + */
> > > > + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
> > >
> > > In the next patch this is changed again to:
> > >
> > > + if (spi_imx->devtype_data->tx_glitch_fixed)
> > > + tx.dst_maxburst = spi_imx->wml;
> > > + else
> > > + tx.dst_maxburst = spi_imx->devtype_data->fifo_size;
> > >
> > > So with tx_glitch_fixed we end up with tx.dst_maxburst being the
> > > same as two patches before which is rather confusing. Better
> > > introduce tx_glitch_fixed in this patch, or maybe even merge this patch and
> the next one.
> > Sorry confused you, I should repleace 'tx_wml=0' in the above comments
> > with ' TX_THRESHOLD=0', which means tx transfer dma have to wait all
> > the tx data in tx fifo transferred with ERR009165 rather than
> > generically 'tx_wml' (for example --half fifo size used as
> > TX_THRESHOLD). Obviously TX_THRESHOLD=0 would down performance, so
> > enlarge dst_maxburst to fifo size as PIO with ERR009165. After
> > ERR009165 fixed at HW level. TX_THRESHOLD could be used as common
> > 'spi_imx->wml' so change it back. Will add more detail information in
> > v8.
>
> I am not confused, I meant the patches are confusing. What you are doing
> is:
>
> No patch:
> tx.dst_maxburst = a;
>
> 1st patch
> tx.dst_maxburst = b;
>
> 2nd patch:
>
> if (foo)
> tx.dst_maxburst = a;
> else
> tx.dst_maxburst = b;
>
> It would be better readable and understandable if you did that in one patch,
> because that would directly say "Under certain conditions we have to choose a,
> otherwise b". That's much better than changing "a" to "b" and then to "a or b"
>
Okay, I'll merge those 2 changes into the next 08/13.
Hi Robin,
On Mon, May 11, 2020 at 6:33 AM Robin Gong <[email protected]> wrote:
> Please get latest sdma firmware from the below and put them into the path
> (/lib/firmware/imx/sdma/):
> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
> /tree/imx/sdma
"latest sdma firmware" is too vague. Better specify the commit ID of
the firmware where this is valid.
On 2020/05/14 5:07 Fabio Estevam <[email protected]> wrote:
> Hi Robin,
>
> On Mon, May 11, 2020 at 6:33 AM Robin Gong <[email protected]> wrote:
>
> > Please get latest sdma firmware from the below and put them into the
> > path
> > (/lib/firmware/imx/sdma/):
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.
> >
> kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ffirmware%2Flinux-firm
> w
> >
> are.git&data=02%7C01%7Cyibin.gong%40nxp.com%7Cc38e0fc1fdc44557a
> f8e
> >
> 08d7f7815cac%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637250
> 007291
> >
> 672980&sdata=CnABtiTICTIf4ZQQ%2F8x9qP6HD9lDbRE%2BwXqcRhmKcd
> 0%3D&am
> > p;reserved=0
> > /tree/imx/sdma
>
> "latest sdma firmware" is too vague. Better specify the commit ID of the
> firmware where this is valid.
Okay, will add it in v8.