This series has two fixes of tegra210_mc_clients, and three
changes to add missing swgroups, according to Tegra X1 TRM.
Nicolin Chen (5):
memory: tegra: Correct la.reg address of seswr
memory: tegra: Correct tegra210_mc_clients def values
memory: tegra: Sort tegra210_swgroups by reg address
dt-bindings: memory: tegra: Add missing swgroups
memory: tegra: Complete tegra210_swgroups
drivers/memory/tegra/tegra210.c | 60 ++++++++++++++----------
include/dt-bindings/memory/tegra210-mc.h | 10 ++++
2 files changed, 45 insertions(+), 25 deletions(-)
--
2.17.1
According to Tegra X1 TRM, there are missing swgroups in the
tegra210_swgroups list. So this patch adds them to the list.
Note that the TEGRA_SWGROUP_GPU (in list) should be actually
TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
TEGRA_SWGROUP_GPU (in list) as it is.
Signed-off-by: Nicolin Chen <[email protected]>
---
drivers/memory/tegra/tegra210.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index b400802c9f14..b3bbc5a05ba1 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
{ .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
+ { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
+ { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
@@ -1036,19 +1038,27 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
+ { .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 },
+ { .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 },
{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
{ .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
{ .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
+ { .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 },
{ .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
{ .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
{ .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
{ .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
+ { .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 },
+ { .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 },
{ .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
{ .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
{ .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
+ { .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 },
+ { .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc },
+ { .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 },
};
static const unsigned int tegra210_group_display[] = {
--
2.17.1
According to Tegra X1 TRM, there are missing swgroups in the
tegra210_swgroups list. So this patch adds them in bindings.
Note that the TEGRA_SWGROUP_GPU (in list) should be actually
TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
TEGRA_SWGROUP_GPU (in list) as it is.
Signed-off-by: Nicolin Chen <[email protected]>
---
include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
index c226cba9e077..f9fcb18a6d9b 100644
--- a/include/dt-bindings/memory/tegra210-mc.h
+++ b/include/dt-bindings/memory/tegra210-mc.h
@@ -33,6 +33,16 @@
#define TEGRA_SWGROUP_AXIAP 28
#define TEGRA_SWGROUP_ETR 29
#define TEGRA_SWGROUP_TSECB 30
+#define TEGRA_SWGROUP_NV 31
+#define TEGRA_SWGROUP_NV2 32
+#define TEGRA_SWGROUP_PPCS1 33
+#define TEGRA_SWGROUP_DC1 34
+#define TEGRA_SWGROUP_PPCS2 35
+#define TEGRA_SWGROUP_HC1 36
+#define TEGRA_SWGROUP_SE1 37
+#define TEGRA_SWGROUP_TSEC1 38
+#define TEGRA_SWGROUP_TSECB1 39
+#define TEGRA_SWGROUP_NVDEC1 40
#define TEGRA210_MC_RESET_AFI 0
#define TEGRA210_MC_RESET_AVPC 1
--
2.17.1
On Thu, 8 Oct 2020 at 02:44, Nicolin Chen <[email protected]> wrote:
>
> This series has two fixes of tegra210_mc_clients, and three
> changes to add missing swgroups, according to Tegra X1 TRM.
>
> Nicolin Chen (5):
> memory: tegra: Correct la.reg address of seswr
> memory: tegra: Correct tegra210_mc_clients def values
> memory: tegra: Sort tegra210_swgroups by reg address
> dt-bindings: memory: tegra: Add missing swgroups
> memory: tegra: Complete tegra210_swgroups
Hi,
It's too late in the cycle for another pull request so this will wait
for merge window to finish.
Best regards,
Krzysztof
Hi Krzysztof,
On Thu, Oct 08, 2020 at 12:29:06PM +0200, Krzysztof Kozlowski wrote:
> On Thu, 8 Oct 2020 at 02:44, Nicolin Chen <[email protected]> wrote:
> >
> > This series has two fixes of tegra210_mc_clients, and three
> > changes to add missing swgroups, according to Tegra X1 TRM.
> >
> > Nicolin Chen (5):
> > memory: tegra: Correct la.reg address of seswr
> > memory: tegra: Correct tegra210_mc_clients def values
> > memory: tegra: Sort tegra210_swgroups by reg address
> > dt-bindings: memory: tegra: Add missing swgroups
> > memory: tegra: Complete tegra210_swgroups
>
> Hi,
>
> It's too late in the cycle for another pull request so this will wait
> for merge window to finish.
I see. Thanks for telling me this!
On Fri, Oct 09, 2020 at 02:21:10PM +0200, Thierry Reding wrote:
> On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> > According to Tegra X1 TRM, there are missing swgroups in the
> > tegra210_swgroups list. So this patch adds them in bindings.
> >
> > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > TEGRA_SWGROUP_GPU (in list) as it is.
> >
> > Signed-off-by: Nicolin Chen <[email protected]>
> > ---
> > include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> > index c226cba9e077..f9fcb18a6d9b 100644
> > --- a/include/dt-bindings/memory/tegra210-mc.h
> > +++ b/include/dt-bindings/memory/tegra210-mc.h
> > @@ -33,6 +33,16 @@
> > #define TEGRA_SWGROUP_AXIAP 28
> > #define TEGRA_SWGROUP_ETR 29
> > #define TEGRA_SWGROUP_TSECB 30
> > +#define TEGRA_SWGROUP_NV 31
> > +#define TEGRA_SWGROUP_NV2 32
> > +#define TEGRA_SWGROUP_PPCS1 33
> > +#define TEGRA_SWGROUP_DC1 34
> > +#define TEGRA_SWGROUP_PPCS2 35
> > +#define TEGRA_SWGROUP_HC1 36
> > +#define TEGRA_SWGROUP_SE1 37
> > +#define TEGRA_SWGROUP_TSEC1 38
> > +#define TEGRA_SWGROUP_TSECB1 39
> > +#define TEGRA_SWGROUP_NVDEC1 40
>
> I'm not sure this is right. The existing list is based on "Table 4:
> Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
> none of these new swgroups seem to be present in that table.
I went through all the MC_SMMU_XX_ASID_0 registers. All of
them have their own ASID registers that I added in PATCH-5.
On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them in bindings.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <[email protected]>
> ---
> include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> index c226cba9e077..f9fcb18a6d9b 100644
> --- a/include/dt-bindings/memory/tegra210-mc.h
> +++ b/include/dt-bindings/memory/tegra210-mc.h
> @@ -33,6 +33,16 @@
> #define TEGRA_SWGROUP_AXIAP 28
> #define TEGRA_SWGROUP_ETR 29
> #define TEGRA_SWGROUP_TSECB 30
> +#define TEGRA_SWGROUP_NV 31
> +#define TEGRA_SWGROUP_NV2 32
> +#define TEGRA_SWGROUP_PPCS1 33
> +#define TEGRA_SWGROUP_DC1 34
> +#define TEGRA_SWGROUP_PPCS2 35
> +#define TEGRA_SWGROUP_HC1 36
> +#define TEGRA_SWGROUP_SE1 37
> +#define TEGRA_SWGROUP_TSEC1 38
> +#define TEGRA_SWGROUP_TSECB1 39
> +#define TEGRA_SWGROUP_NVDEC1 40
I'm not sure this is right. The existing list is based on "Table 4:
Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
none of these new swgroups seem to be present in that table.
Where exactly did you get those from?
Thierry
On Fri, Oct 09, 2020 at 08:52:18AM -0700, Nicolin Chen wrote:
> On Fri, Oct 09, 2020 at 02:21:10PM +0200, Thierry Reding wrote:
> > On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> > > According to Tegra X1 TRM, there are missing swgroups in the
> > > tegra210_swgroups list. So this patch adds them in bindings.
> > >
> > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > > TEGRA_SWGROUP_GPU (in list) as it is.
> > >
> > > Signed-off-by: Nicolin Chen <[email protected]>
> > > ---
> > > include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> > > index c226cba9e077..f9fcb18a6d9b 100644
> > > --- a/include/dt-bindings/memory/tegra210-mc.h
> > > +++ b/include/dt-bindings/memory/tegra210-mc.h
> > > @@ -33,6 +33,16 @@
> > > #define TEGRA_SWGROUP_AXIAP 28
> > > #define TEGRA_SWGROUP_ETR 29
> > > #define TEGRA_SWGROUP_TSECB 30
> > > +#define TEGRA_SWGROUP_NV 31
> > > +#define TEGRA_SWGROUP_NV2 32
> > > +#define TEGRA_SWGROUP_PPCS1 33
> > > +#define TEGRA_SWGROUP_DC1 34
> > > +#define TEGRA_SWGROUP_PPCS2 35
> > > +#define TEGRA_SWGROUP_HC1 36
> > > +#define TEGRA_SWGROUP_SE1 37
> > > +#define TEGRA_SWGROUP_TSEC1 38
> > > +#define TEGRA_SWGROUP_TSECB1 39
> > > +#define TEGRA_SWGROUP_NVDEC1 40
> >
> > I'm not sure this is right. The existing list is based on "Table 4:
> > Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
> > none of these new swgroups seem to be present in that table.
>
> I went through all the MC_SMMU_XX_ASID_0 registers. All of
> them have their own ASID registers that I added in PATCH-5.
Thierry,
Any follow ups on this topic? Does it require a fix or looks correct?
Best regards,
Krzysztof
On Mon, Oct 26, 2020 at 09:17:58PM +0100, Krzysztof Kozlowski wrote:
> On Fri, Oct 09, 2020 at 08:52:18AM -0700, Nicolin Chen wrote:
> > On Fri, Oct 09, 2020 at 02:21:10PM +0200, Thierry Reding wrote:
> > > On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> > > > According to Tegra X1 TRM, there are missing swgroups in the
> > > > tegra210_swgroups list. So this patch adds them in bindings.
> > > >
> > > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > > > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > > > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > > > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > > > TEGRA_SWGROUP_GPU (in list) as it is.
> > > >
> > > > Signed-off-by: Nicolin Chen <[email protected]>
> > > > ---
> > > > include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> > > > 1 file changed, 10 insertions(+)
> > > >
> > > > diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> > > > index c226cba9e077..f9fcb18a6d9b 100644
> > > > --- a/include/dt-bindings/memory/tegra210-mc.h
> > > > +++ b/include/dt-bindings/memory/tegra210-mc.h
> > > > @@ -33,6 +33,16 @@
> > > > #define TEGRA_SWGROUP_AXIAP 28
> > > > #define TEGRA_SWGROUP_ETR 29
> > > > #define TEGRA_SWGROUP_TSECB 30
> > > > +#define TEGRA_SWGROUP_NV 31
> > > > +#define TEGRA_SWGROUP_NV2 32
> > > > +#define TEGRA_SWGROUP_PPCS1 33
> > > > +#define TEGRA_SWGROUP_DC1 34
> > > > +#define TEGRA_SWGROUP_PPCS2 35
> > > > +#define TEGRA_SWGROUP_HC1 36
> > > > +#define TEGRA_SWGROUP_SE1 37
> > > > +#define TEGRA_SWGROUP_TSEC1 38
> > > > +#define TEGRA_SWGROUP_TSECB1 39
> > > > +#define TEGRA_SWGROUP_NVDEC1 40
> > >
> > > I'm not sure this is right. The existing list is based on "Table 4:
> > > Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
> > > none of these new swgroups seem to be present in that table.
> >
> > I went through all the MC_SMMU_XX_ASID_0 registers. All of
> > them have their own ASID registers that I added in PATCH-5.
>
> Thierry,
>
> Any follow ups on this topic? Does it require a fix or looks correct?
This does indeed look correct, based on what registers exist for these.
It'd be good to know how Nicolin expects these to be used, since these
are currently not listed in device tree. There's certainly some like
TSEC or NVDEC that we don't support (yet) upstream, but things like DC1
and HC1 already have equivalents that we use, so I'm not sure how we'll
integrate these new ones.
I suppose it doesn't really matter if any of these end up being unused,
so:
Acked-by: Thierry Reding <[email protected]>
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them to the list.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <[email protected]>
> ---
> drivers/memory/tegra/tegra210.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> index b400802c9f14..b3bbc5a05ba1 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> + { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
> + { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
Oddly enough I can see these in the TRM, but they are not in the
internal reference manuals that are supposed to be the canonical
reference for the TRM. Perhaps the TRM is out of date?
Thierry
On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them in bindings.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <[email protected]>
> ---
> include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
Thanks, applied.
Best regards,
Krzysztof
On Tue, Oct 27, 2020 at 01:55:06PM +0100, Thierry Reding wrote:
> This does indeed look correct, based on what registers exist for these.
> It'd be good to know how Nicolin expects these to be used, since these
> are currently not listed in device tree. There's certainly some like
Judging from our downstream code, I don't actually expect all of
them will be used, except some being used yet not got upstream.
> TSEC or NVDEC that we don't support (yet) upstream, but things like DC1
> and HC1 already have equivalents that we use, so I'm not sure how we'll
> integrate these new ones.
Downstream code groups those equivalents swgroups, so I think we
can do similarly using tegra_smmu_group_soc like the existing one
for display, if any of them gets upstream someday.
On Tue, Oct 27, 2020 at 02:01:11PM +0100, Thierry Reding wrote:
> On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote:
> > According to Tegra X1 TRM, there are missing swgroups in the
> > tegra210_swgroups list. So this patch adds them to the list.
> >
> > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > TEGRA_SWGROUP_GPU (in list) as it is.
> >
> > Signed-off-by: Nicolin Chen <[email protected]>
> > ---
> > drivers/memory/tegra/tegra210.c | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
> > index b400802c9f14..b3bbc5a05ba1 100644
> > --- a/drivers/memory/tegra/tegra210.c
> > +++ b/drivers/memory/tegra/tegra210.c
> > @@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
> > { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
> > { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
> > { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
> > + { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
> > + { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
>
> Oddly enough I can see these in the TRM, but they are not in the
> internal reference manuals that are supposed to be the canonical
> reference for the TRM. Perhaps the TRM is out of date?
Hmm..I actually have been using the TRM from official site all
the time. These two aren't being used downstream either; I put
them in the patch merely because they exist in the TRM. So we
may drop them if you feel that's better.
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them to the list.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <[email protected]>
> ---
> drivers/memory/tegra/tegra210.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Acked-by: Thierry Reding <[email protected]>
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, there are missing swgroups in the
> tegra210_swgroups list. So this patch adds them to the list.
>
> Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> TEGRA_SWGROUP_GPU (in list) as it is.
>
> Signed-off-by: Nicolin Chen <[email protected]>
> ---
> drivers/memory/tegra/tegra210.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Thanks, applied.
Best regards,
Krzysztof