LinuxLists.cc - [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port

2022-02-08 06:46:45

Subject: [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port

2022-02-08 08:06:11

Subject: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver

Xilinx Versal Premium series has CPM5 block which supports Root port
functioning at Gen5 speed.
Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit
to enable and handle legacy interrupts.

Signed-off-by: Bharat Kumar Gogada <[email protected]>
---
drivers/pci/controller/pcie-xilinx-cpm.c | 33 +++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index c7cd44ed4dfc..eb69f494571a 100644
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -35,6 +35,10 @@
#define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348
#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1)

+#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0
+#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8
+#define XILINX_CPM_PCIE_IR_LOCAL BIT(0)
+
/* Interrupt registers definitions */
#define XILINX_CPM_PCIE_INTR_LINK_DOWN 0
#define XILINX_CPM_PCIE_INTR_HOT_RESET 3
@@ -109,6 +113,7 @@
* @intx_irq: legacy interrupt number
* @irq: Error interrupt number
* @lock: lock protecting shared register access
+ * @is_cpm5: value to check cpm version
*/
struct xilinx_cpm_pcie {
struct device *dev;
@@ -120,6 +125,7 @@ struct xilinx_cpm_pcie {
int intx_irq;
int irq;
raw_spinlock_t lock;
+ bool is_cpm5;
};

static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
@@ -285,6 +291,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
generic_handle_domain_irq(port->cpm_domain, i);
pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);

+ if (port->is_cpm5) {
+ val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
+ if (val)
+ writel_relaxed(val,
+ port->cpm_base +
+ XILINX_CPM_PCIE_IR_STATUS);
+ }
+
/*
* XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
* CPM SLCR block.
@@ -484,6 +498,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
*/
writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
+
+ if (port->is_cpm5) {
+ writel(XILINX_CPM_PCIE_IR_LOCAL,
+ port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
+ }
+
/* Enable the Bridge enable bit */
pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
XILINX_CPM_PCIE_REG_RPSC_BEN,
@@ -504,6 +524,9 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
struct platform_device *pdev = to_platform_device(dev);
struct resource *res;

+ if (of_device_is_compatible(dev->of_node, "xlnx,versal-cpm5-host-1.00"))
+ port->is_cpm5 = true;
+
port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
"cpm_slcr");
if (IS_ERR(port->cpm_base))
@@ -518,7 +541,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
if (IS_ERR(port->cfg))
return PTR_ERR(port->cfg);

- port->reg_base = port->cfg->win;
+ if (!port->is_cpm5) {
+ port->reg_base = port->cfg->win;
+ } else {
+ port->reg_base = devm_platform_ioremap_resource_byname(pdev,
+ "cpm_csr");
+ if (IS_ERR(port->reg_base))
+ return PTR_ERR(port->reg_base);
+ }

return 0;
}
@@ -593,6 +623,7 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)

static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
{ .compatible = "xlnx,versal-cpm-host-1.00", },
+ { .compatible = "xlnx,versal-cpm5-host-1.00", },
{}
};

--
2.17.1

2022-02-08 15:43:17

by Bharat Kumar Gogada

[permalink] [raw]

Subject: RE: [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port

Hi All,

Sorry for resending, my mailbox didn't show one patch, resent this assuming patch was missing.

Regards,
Bharat

> -----Original Message-----
> From: Bharat Kumar Gogada <[email protected]>
> Sent: Monday, February 7, 2022 9:43 AM
> To: [email protected]; [email protected]
> Cc: [email protected]; [email protected]; Michal Simek
> <[email protected]>; Bharat Kumar Gogada <[email protected]>
> Subject: [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port
>
> Xilinx Versal Premium series has CPM5 block which supports Root port
> functioning at Gen5 speed.
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additonal register bit
> to enable and handle legacy interrupts.
>
> Bharat Kumar Gogada (2):
> PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port
> PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver
>
> .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++---
> drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++-
> 2 files changed, 72 insertions(+), 8 deletions(-)
>
> --
> 2.17.1

2022-02-08 22:26:58

by Bharat Kumar Gogada

[permalink] [raw]

Subject: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port

Xilinx Versal Premium series has CPM5 block which supports Root port
functioning at Gen5 speed.
Add support for YAML schemas documentation for Versal CPM5 Root Port driver.

Signed-off-by: Bharat Kumar Gogada <[email protected]>
---
.../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++---
1 file changed, 40 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index 32f4641085bc..97c7229d7f91 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -14,17 +14,21 @@ allOf:

properties:
compatible:
- const: xlnx,versal-cpm-host-1.00
+ contains:
+ enum:
+ - xlnx,versal-cpm-host-1.00
+ - xlnx,versal-cpm5-host-1.00

reg:
- items:
- - description: Configuration space region and bridge registers.
- - description: CPM system level control and status registers.
+ description: |
+ Should contain cpm_slcr, cfg registers location and length.
+ For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr.
+ minItems: 2
+ maxItems: 3

reg-names:
- items:
- - const: cfg
- - const: cpm_slcr
+ minItems: 2
+ maxItems: 3

interrupts:
maxItems: 1
@@ -95,4 +99,33 @@ examples:
interrupt-controller;
};
};
+
+ cpm5_pcie: pcie@fcdd0000 {
+ compatible = "xlnx,versal-cpm5-host-1.00";
+ device_type = "pci";
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupts = <0 72 4>;
+ interrupt-parent = <&gic>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
+ <0 0 0 2 &pcie_intc_1 1>,
+ <0 0 0 3 &pcie_intc_1 2>,
+ <0 0 0 4 &pcie_intc_1 3>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
+ <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
+ msi-map = <0x0 &its_gic 0x0 0x10000>;
+ reg = <0x00 0xfcdd0000 0x00 0x1000>,
+ <0x06 0x00000000 0x00 0x1000000>,
+ <0x00 0xfce20000 0x00 0x1000000>;
+ reg-names = "cpm_slcr", "cfg", "cpm_csr";
+
+ pcie_intc_1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
};
--
2.17.1

2022-02-08 23:36:46

by Bjorn Helgaas

[permalink] [raw]

Subject: Re: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port

It looks like the subject line convention here would be something
like:

dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port

(From "git log --oneline Documentation/devicetree/bindings/pci/")

On Mon, Feb 07, 2022 at 09:42:48AM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root port
> functioning at Gen5 speed.
> Add support for YAML schemas documentation for Versal CPM5 Root Port driver.

s/Root port/Root Port/ to be consistent.
Add blank line between paragraphs.

Bjorn

2022-02-09 06:17:29

by Bjorn Helgaas

[permalink] [raw]

Subject: Re: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver

In subject, possibly:

PCI: xilinx-cpm: Add Versal CPM5 Root Port support

since you're adding support for a *device*, not for a *driver*.

On Mon, Feb 07, 2022 at 09:42:50AM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root port
> functioning at Gen5 speed.
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additional register bit
> to enable and handle legacy interrupts.

s/Root port/Root Port/ to be consistent.
Add blank line between paragraphs.

Bjorn

2022-02-09 07:36:07

by Bharat Kumar Gogada

[permalink] [raw]

Subject: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port

2022-02-09 10:54:13

by Bharat Kumar Gogada

[permalink] [raw]

Subject: RE: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port

> Subject: Re: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal
> CPM5 Root Port
>
> It looks like the subject line convention here would be something
> like:
>
> dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
>
> (From "git log --oneline Documentation/devicetree/bindings/pci/")
>
> On Mon, Feb 07, 2022 at 09:42:48AM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root port
> > functioning at Gen5 speed.
> > Add support for YAML schemas documentation for Versal CPM5 Root Port
> driver.
>
> s/Root port/Root Port/ to be consistent.
> Add blank line between paragraphs.
>
Thanks Bjorn, will do the changes in next patch.

Regards,
Bharat

2022-02-09 11:05:04

by Bharat Kumar Gogada

[permalink] [raw]

Subject: RE: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver

> Subject: Re: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root
> Port driver
>
> In subject, possibly:
>
> PCI: xilinx-cpm: Add Versal CPM5 Root Port support
>
> since you're adding support for a *device*, not for a *driver*.
>
> On Mon, Feb 07, 2022 at 09:42:50AM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root port
> > functioning at Gen5 speed.
> > Xilinx Versal CPM5 has few changes with existing CPM block.
> > - CPM5 has dedicated register space for control and status registers.
> > - CPM5 legacy interrupt handling needs additional register bit
> > to enable and handle legacy interrupts.
>
> s/Root port/Root Port/ to be consistent.
> Add blank line between paragraphs.
>
Thanks Bjorn, will do the changes in next patch.

Regards,
Bharat