Add preliminary support for boards based on the JZ4755 SoC from
Ingenic.
It is a low-power SoC with a MIPS32r1 core running at ~432 MHz,
and has no FPU.
The JZ4755 SoC is supposed to be newer than the JZ4725B SoC, but its
internals are very close to each other. Also the Ingenic's kernel
source tree calls JZ4755 as JZ4750D and JZ4725B as JZ4750L, this might
mean that JZ4725B is a pin to pin compatible replacement for older
JZ4725 (both are LQFP128) but belongs to newer generation JZ475x. Who
knows?
I guess Ingenic released their SoCs in the following order:
JZ4720 (MXU ?)
JZ4725 (MXU ?)
JZ4730 (MXU ?)
JZ4740 (MXU1 r1)
JZ4750 (MXU1 r2)
JZ4755 (MXU1 r2)
JZ4725b (MXU1 r2)
JZ4760 ...
So JZ4755 DT is reusing many JZ4725B drivers because their support
in mainline kernel appears earlier.
Siarhei Volkau (8):
dt-bindings: ingenic: Add support for the JZ4755 SoC
MIPS: ingenic: add new machine type MACH_JZ4755
dt-bindings: clock: Add Ingenic JZ4755 CGU header
clk: Add Ingenic JZ4755 CGU driver
pinctrl: ingenic: JZ4755 minor bug fixes
dmaengine: JZ4780: Add support for the JZ4755.
serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs
MIPS: ingenic: Add support for the JZ4755 SoC
.../bindings/clock/ingenic,cgu.yaml | 2 +
.../devicetree/bindings/dma/ingenic,dma.yaml | 1 +
.../bindings/serial/ingenic,uart.yaml | 4 +
arch/mips/boot/dts/ingenic/jz4755.dtsi | 439 ++++++++++++++++++
arch/mips/ingenic/Kconfig | 5 +
drivers/clk/ingenic/Kconfig | 10 +
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/jz4755-cgu.c | 350 ++++++++++++++
drivers/dma/dma-jz4780.c | 8 +
drivers/pinctrl/pinctrl-ingenic.c | 4 +-
drivers/tty/serial/8250/8250_ingenic.c | 39 +-
.../dt-bindings/clock/ingenic,jz4755-cgu.h | 49 ++
12 files changed, 905 insertions(+), 7 deletions(-)
create mode 100644 arch/mips/boot/dts/ingenic/jz4755.dtsi
create mode 100644 drivers/clk/ingenic/jz4755-cgu.c
create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h
--
2.36.1
Add preliminary support for boards based on the JZ4755 SoC from
Ingenic.
It is a low-power SoC with a MIPS32r1 SoC running at ~432 MHz, and no
FPU.
The JZ4755 SoC is supposed to be newer than the JZ4725B SoC, but its
internals are very close to each other. So JZ4755 DT is reusing many
JZ4725b drivers because JZ4725b support in the kernel appears earlier.
Signed-off-by: Siarhei Volkau <[email protected]>
---
arch/mips/boot/dts/ingenic/jz4755.dtsi | 439 +++++++++++++++++++++++++
1 file changed, 439 insertions(+)
create mode 100644 arch/mips/boot/dts/ingenic/jz4755.dtsi
diff --git a/arch/mips/boot/dts/ingenic/jz4755.dtsi b/arch/mips/boot/dts/ingenic/jz4755.dtsi
new file mode 100644
index 000000000..e1630e0fe
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/jz4755.dtsi
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/ingenic,jz4755-cgu.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ingenic,jz4755";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst-mxu1.1";
+ reg = <0>;
+
+ clocks = <&cgu JZ4755_CLK_CCLK>;
+ clock-names = "cpu";
+ };
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ intc: interrupt-controller@10001000 {
+ compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
+ reg = <0x10001000 0x14>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ ext: ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ osc32k: osc32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ cgu: clock-controller@10000000 {
+ compatible = "ingenic,jz4755-cgu";
+ reg = <0x10000000 0x100>;
+
+ clocks = <&ext>, <&osc32k>;
+ clock-names = "ext", "osc32k";
+
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@10030000 {
+ compatible = "ingenic,jz4755-uart", "ingenic,jz4750-uart";
+ reg = <0x10030000 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <9>;
+
+ clocks = <&cgu JZ4755_CLK_EXT_HALF>, <&cgu JZ4755_CLK_UART0>;
+ clock-names = "baud", "module";
+
+ status = "disabled";
+ };
+
+ uart1: serial@10031000 {
+ compatible = "ingenic,jz4755-uart", "ingenic,jz4750-uart";
+ reg = <0x10031000 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+
+ clocks = <&cgu JZ4755_CLK_EXT_HALF>, <&cgu JZ4755_CLK_UART1>;
+ clock-names = "baud", "module";
+
+ status = "disabled";
+ };
+
+ uart2: serial@10032000 {
+ compatible = "ingenic,jz4755-uart", "ingenic,jz4750-uart";
+ reg = <0x10032000 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <7>;
+
+ clocks = <&cgu JZ4755_CLK_EXT_HALF>, <&cgu JZ4755_CLK_UART2>;
+ clock-names = "baud", "module";
+
+ status = "disabled";
+ };
+
+ rtc_dev: rtc@10003000 {
+ compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc";
+ reg = <0x10003000 0x40>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <6>;
+
+ clocks = <&cgu JZ4755_CLK_RTC>;
+ clock-names = "rtc";
+ };
+
+ pinctrl: pinctrl@10010000 {
+ compatible = "ingenic,jz4755-pinctrl";
+ reg = <0x10010000 0x600>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,jz4755-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+ };
+
+ gpb: gpio@1 {
+ compatible = "ingenic,jz4755-gpio";
+ reg = <1>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <15>;
+ };
+
+ gpc: gpio@2 {
+ compatible = "ingenic,jz4755-gpio";
+ reg = <2>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <14>;
+ };
+
+ gpd: gpio@3 {
+ compatible = "ingenic,jz4755-gpio";
+ reg = <3>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <13>;
+ };
+
+ gpe: gpio@4 {
+ compatible = "ingenic,jz4755-gpio";
+ reg = <4>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+ };
+
+ gpf: gpio@5 {
+ compatible = "ingenic,jz4755-gpio";
+ reg = <5>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 160 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <11>;
+ };
+ };
+
+ mmc0: mmc@10021000 {
+ compatible = "ingenic,jz4725b-mmc";
+ reg = <0x10021000 0x1000>;
+
+ clocks = <&cgu JZ4755_CLK_MMC0>;
+ clock-names = "mmc";
+
+ interrupt-parent = <&intc>;
+ interrupts = <25>;
+
+ dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cap-sdio-irq;
+ };
+
+ mmc1: mmc@10022000 {
+ compatible = "ingenic,jz4725b-mmc";
+ reg = <0x10022000 0x1000>;
+
+ clocks = <&cgu JZ4755_CLK_MMC1>;
+ clock-names = "mmc";
+
+ interrupt-parent = <&intc>;
+ interrupts = <24>;
+
+ dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cap-sdio-irq;
+ };
+
+ dmac0: dma-controller@13020000 {
+ compatible = "ingenic,jz4755-dma";
+ reg = <0x13020000 0xd0>, <0x13020300 0x14>;
+
+ #dma-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <29>;
+
+ clocks = <&cgu JZ4755_CLK_DMA>;
+ };
+
+ dmac1: dma-controller@13020100 {
+ compatible = "ingenic,jz4755-dma";
+ reg = <0x13020100 0xd0>, <0x13020400 0x14>;
+
+ #dma-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+
+ clocks = <&cgu JZ4755_CLK_DMA>;
+ };
+
+ tcu: timer@10002000 {
+ compatible = "ingenic,jz4725b-tcu", "simple-mfd";
+ reg = <0x10002000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10002000 0x1000>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu JZ4755_CLK_RTC>,
+ <&cgu JZ4755_CLK_EXT>,
+ <&cgu JZ4755_CLK_PCLK>,
+ <&cgu JZ4755_CLK_TCU>;
+ clock-names = "rtc", "ext", "pclk", "tcu";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <23>, <22>, <21>;
+
+ watchdog: watchdog@0 {
+ compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog";
+ reg = <0x0 0xc>;
+
+ clocks = <&tcu TCU_CLK_WDT>;
+ clock-names = "wdt";
+ };
+
+ pwm: pwm@60 {
+ compatible = "ingenic,jz4725b-pwm";
+ reg = <0x60 0x40>;
+
+ #pwm-cells = <3>;
+
+ clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
+ <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>;
+ clock-names = "timer0", "timer1", "timer2",
+ "timer3", "timer4", "timer5";
+ };
+
+ ost: timer@e0 {
+ compatible = "ingenic,jz4725b-ost";
+ reg = <0xe0 0x20>;
+
+ clocks = <&tcu TCU_CLK_OST>;
+ clock-names = "ost";
+
+ interrupts = <15>;
+ };
+ };
+
+ aic: audio-controller@10020000 {
+ compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s";
+ reg = <0x10020000 0x38>;
+
+ #sound-dai-cells = <0>;
+
+ clocks = <&cgu JZ4755_CLK_AIC>,
+ <&cgu JZ4755_CLK_I2S>,
+ <&cgu JZ4755_CLK_EXT>,
+ <&cgu JZ4755_CLK_PLL_HALF>;
+ clock-names = "aic", "i2s", "ext", "pll half";
+
+ interrupt-parent = <&intc>;
+ interrupts = <10>;
+
+ dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>;
+ dma-names = "rx", "tx";
+ };
+
+ codec: audio-codec@100200a4 {
+ compatible = "ingenic,jz4725b-codec";
+ reg = <0x100200a4 0x8>;
+
+ #sound-dai-cells = <0>;
+
+ clocks = <&cgu JZ4755_CLK_AIC>;
+ clock-names = "aic";
+ };
+
+ adc: adc@10070000 {
+ compatible = "ingenic,jz4725b-adc";
+ #io-channel-cells = <1>;
+
+ reg = <0x10070000 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10070000 0x30>;
+
+ clocks = <&cgu JZ4755_CLK_ADC>;
+ clock-names = "adc";
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+ };
+
+ nemc: memory-controller@13010000 {
+ compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc";
+ reg = <0x13010000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>,
+ <3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>;
+
+ clocks = <&cgu JZ4755_CLK_MCLK>;
+ };
+
+ udc: usb@13040000 {
+ compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb";
+ reg = <0x13040000 0x10000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+ interrupt-names = "mc";
+
+ clocks = <&cgu JZ4755_CLK_UDC>;
+ clock-names = "udc";
+ };
+
+ lcd: lcd-controller@13050000 {
+ compatible = "ingenic,jz4725b-lcd";
+ reg = <0x13050000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <31>;
+
+ clocks = <&cgu JZ4755_CLK_LCD>;
+ clock-names = "lcd_pclk";
+
+ lcd_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@8 {
+ reg = <8>;
+
+ ipu_output: endpoint {
+ remote-endpoint = <&ipu_input>;
+ };
+ };
+ };
+ };
+
+ ipu: ipu@13080000 {
+ compatible = "ingenic,jz4725b-ipu";
+ reg = <0x13080000 0x64>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+
+ clocks = <&cgu JZ4755_CLK_IPU>;
+ clock-names = "ipu";
+
+ port {
+ ipu_input: endpoint {
+ remote-endpoint = <&ipu_output>;
+ };
+ };
+ };
+
+ bch: ecc-controller@130d0000 {
+ compatible = "ingenic,jz4725b-bch";
+ reg = <0x130d0000 0x44>;
+
+ clocks = <&cgu JZ4755_CLK_BCH>;
+ };
+};
--
2.36.1
Fixes UART1 function bits and mmc groups typo.
For pins 0x97,0x99 function 0 is designated to PWM3/PWM5
respectively, function is 1 designated to the UART1.
Tested-by: Siarhei Volkau <[email protected]>
Signed-off-by: Siarhei Volkau <[email protected]>
---
drivers/pinctrl/pinctrl-ingenic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 3a9ee9c8a..2991fe0bb 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -667,7 +667,7 @@ static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
static const struct group_desc jz4755_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
- INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),
+ INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
@@ -721,7 +721,7 @@ static const char *jz4755_ssi_groups[] = {
"ssi-ce1-b", "ssi-ce1-f",
};
static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
-static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
+static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
static const char *jz4755_i2c_groups[] = { "i2c-data", };
static const char *jz4755_cim_groups[] = { "cim-data", };
static const char *jz4755_lcd_groups[] = {
--
2.36.1
JZ4755 is a low-power SoC similar to JZ4725B which is already here.
The patch adds compatibles for parts which aren't implemented yet and
they are subject of this patch serie.
Signed-off-by: Siarhei Volkau <[email protected]>
---
Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++
Documentation/devicetree/bindings/dma/ingenic,dma.yaml | 1 +
Documentation/devicetree/bindings/serial/ingenic,uart.yaml | 4 ++++
3 files changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
index aa1df03ef..df256ebcd 100644
--- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
@@ -22,6 +22,7 @@ select:
enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
+ - ingenic,jz4755-cgu
- ingenic,jz4760-cgu
- ingenic,jz4760b-cgu
- ingenic,jz4770-cgu
@@ -51,6 +52,7 @@ properties:
- enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
+ - ingenic,jz4755-cgu
- ingenic,jz4760-cgu
- ingenic,jz4760b-cgu
- ingenic,jz4770-cgu
diff --git a/Documentation/devicetree/bindings/dma/ingenic,dma.yaml b/Documentation/devicetree/bindings/dma/ingenic,dma.yaml
index 3b0b3b919..e42b8ce94 100644
--- a/Documentation/devicetree/bindings/dma/ingenic,dma.yaml
+++ b/Documentation/devicetree/bindings/dma/ingenic,dma.yaml
@@ -18,6 +18,7 @@ properties:
- enum:
- ingenic,jz4740-dma
- ingenic,jz4725b-dma
+ - ingenic,jz4755-dma
- ingenic,jz4760-dma
- ingenic,jz4760-bdma
- ingenic,jz4760-mdma
diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml
index 9ca7a18ec..315ceb722 100644
--- a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml
@@ -20,6 +20,7 @@ properties:
oneOf:
- enum:
- ingenic,jz4740-uart
+ - ingenic,jz4750-uart
- ingenic,jz4760-uart
- ingenic,jz4780-uart
- ingenic,x1000-uart
@@ -31,6 +32,9 @@ properties:
- items:
- const: ingenic,jz4725b-uart
- const: ingenic,jz4740-uart
+ - items:
+ - const: ingenic,jz4755-uart
+ - const: ingenic,jz4750-uart
reg:
maxItems: 1
--
2.36.1
This will be used from the devicetree bindings to specify the clocks
that should be obtained from the jz4755-cgu driver.
Signed-off-by: Siarhei Volkau <[email protected]>
---
.../dt-bindings/clock/ingenic,jz4755-cgu.h | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h
diff --git a/include/dt-bindings/clock/ingenic,jz4755-cgu.h b/include/dt-bindings/clock/ingenic,jz4755-cgu.h
new file mode 100644
index 000000000..32307f68c
--- /dev/null
+++ b/include/dt-bindings/clock/ingenic,jz4755-cgu.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4755-cgu DT binding.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__
+
+#define JZ4755_CLK_EXT 0
+#define JZ4755_CLK_OSC32K 1
+#define JZ4755_CLK_PLL 2
+#define JZ4755_CLK_PLL_HALF 3
+#define JZ4755_CLK_EXT_HALF 4
+#define JZ4755_CLK_CCLK 5
+#define JZ4755_CLK_H0CLK 6
+#define JZ4755_CLK_PCLK 7
+#define JZ4755_CLK_MCLK 8
+#define JZ4755_CLK_H1CLK 9
+#define JZ4755_CLK_UDC 10
+#define JZ4755_CLK_LCD 11
+#define JZ4755_CLK_UART0 12
+#define JZ4755_CLK_UART1 13
+#define JZ4755_CLK_UART2 14
+#define JZ4755_CLK_DMA 15
+#define JZ4755_CLK_MMC 16
+#define JZ4755_CLK_MMC0 17
+#define JZ4755_CLK_MMC1 18
+#define JZ4755_CLK_EXT512 19
+#define JZ4755_CLK_RTC 20
+#define JZ4755_CLK_UDC_PHY 21
+#define JZ4755_CLK_I2S 22
+#define JZ4755_CLK_SPI 23
+#define JZ4755_CLK_AIC 24
+#define JZ4755_CLK_ADC 25
+#define JZ4755_CLK_TCU 26
+#define JZ4755_CLK_BCH 27
+#define JZ4755_CLK_I2C 28
+#define JZ4755_CLK_TVE 29
+#define JZ4755_CLK_CIM 30
+#define JZ4755_CLK_AUX_CPU 31
+#define JZ4755_CLK_AHB1 32
+#define JZ4755_CLK_IDCT 33
+#define JZ4755_CLK_DB 34
+#define JZ4755_CLK_ME 35
+#define JZ4755_CLK_MC 36
+#define JZ4755_CLK_TSSI 37
+#define JZ4755_CLK_IPU 38
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */
--
2.36.1
The JZ4755 has 4 DMA channels per DMA unit, two idential DMA units.
The JZ4755 has the similar DMA engine to JZ4725b, so I assume it has the
same bug as JZ4725b, see commit a40c94be2336.
Signed-off-by: Siarhei Volkau <[email protected]>
---
drivers/dma/dma-jz4780.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
index 2a483802d..9c1a6e9a9 100644
--- a/drivers/dma/dma-jz4780.c
+++ b/drivers/dma/dma-jz4780.c
@@ -1038,6 +1038,13 @@ static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = {
JZ_SOC_DATA_BREAK_LINKS,
};
+static const struct jz4780_dma_soc_data jz4755_dma_soc_data = {
+ .nb_channels = 4,
+ .transfer_ord_max = 5,
+ .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC |
+ JZ_SOC_DATA_BREAK_LINKS,
+};
+
static const struct jz4780_dma_soc_data jz4760_dma_soc_data = {
.nb_channels = 5,
.transfer_ord_max = 6,
@@ -1101,6 +1108,7 @@ static const struct jz4780_dma_soc_data x1830_dma_soc_data = {
static const struct of_device_id jz4780_dma_dt_match[] = {
{ .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data },
{ .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data },
+ { .compatible = "ingenic,jz4755-dma", .data = &jz4755_dma_soc_data },
{ .compatible = "ingenic,jz4760-dma", .data = &jz4760_dma_soc_data },
{ .compatible = "ingenic,jz4760-mdma", .data = &jz4760_mdma_soc_data },
{ .compatible = "ingenic,jz4760-bdma", .data = &jz4760_bdma_soc_data },
--
2.36.1
These SoCs are close to others but they have a clock divisor /2 for low
clock peripherals, thus to set up a proper baud rate we need to take
this into account.
The divisor bit is located in CGU area, unfortunately the clk framework
can't be used at early boot steps, so it's checked by direct readl()
call.
Signed-off-by: Siarhei Volkau <[email protected]>
---
drivers/tty/serial/8250/8250_ingenic.c | 39 ++++++++++++++++++++++----
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c
index 2b2f5d8d2..f2662720d 100644
--- a/drivers/tty/serial/8250/8250_ingenic.c
+++ b/drivers/tty/serial/8250/8250_ingenic.c
@@ -70,7 +70,8 @@ static void ingenic_early_console_write(struct console *console,
ingenic_early_console_putc);
}
-static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
+static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev,
+ int clkdiv)
{
void *fdt = initial_boot_params;
const __be32 *prop;
@@ -84,11 +85,11 @@ static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev
if (!prop)
return;
- dev->port.uartclk = be32_to_cpup(prop);
+ dev->port.uartclk = be32_to_cpup(prop) / clkdiv;
}
-static int __init ingenic_early_console_setup(struct earlycon_device *dev,
- const char *opt)
+static int __init ingenic_earlycon_setup_common(struct earlycon_device *dev,
+ const char *opt, int clkdiv)
{
struct uart_port *port = &dev->port;
unsigned int divisor;
@@ -103,7 +104,7 @@ static int __init ingenic_early_console_setup(struct earlycon_device *dev,
uart_parse_options(opt, &baud, &parity, &bits, &flow);
}
- ingenic_early_console_setup_clock(dev);
+ ingenic_early_console_setup_clock(dev, clkdiv);
if (dev->baud)
baud = dev->baud;
@@ -129,9 +130,31 @@ static int __init ingenic_early_console_setup(struct earlycon_device *dev,
return 0;
}
+static int __init ingenic_early_console_setup(struct earlycon_device *dev,
+ const char *opt)
+{
+ return ingenic_earlycon_setup_common(dev, opt, 1);
+}
+
+static int __init jz4750_early_console_setup(struct earlycon_device *dev,
+ const char *opt)
+{
+#define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
+#define CPCCR_ECS BIT(30)
+ u32 cpccr = readl(CGU_REG_CPCCR);
+ int clk_div = (cpccr & CPCCR_ECS) ? 2 : 1;
+#undef CGU_REG_CPCCR
+#undef CPCCR_ECS
+
+ return ingenic_earlycon_setup_common(dev, opt, clk_div);
+}
+
OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
ingenic_early_console_setup);
+OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
+ jz4750_early_console_setup);
+
OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
ingenic_early_console_setup);
@@ -311,6 +334,11 @@ static const struct ingenic_uart_config jz4740_uart_config = {
.fifosize = 16,
};
+static const struct ingenic_uart_config jz4750_uart_config = {
+ .tx_loadsz = 16,
+ .fifosize = 32,
+};
+
static const struct ingenic_uart_config jz4760_uart_config = {
.tx_loadsz = 16,
.fifosize = 32,
@@ -328,6 +356,7 @@ static const struct ingenic_uart_config x1000_uart_config = {
static const struct of_device_id of_match[] = {
{ .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
+ { .compatible = "ingenic,jz4750-uart", .data = &jz4750_uart_config },
{ .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
--
2.36.1
which is close to jz4725b because it is actually a low price
successor of the jz4755.
It has the same MIPS32r1 core with Xburst(R) extension
MXU version 1 release 2.
Signed-off-by: Siarhei Volkau <[email protected]>
---
arch/mips/ingenic/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig
index f595b339a..edd84cf13 100644
--- a/arch/mips/ingenic/Kconfig
+++ b/arch/mips/ingenic/Kconfig
@@ -4,6 +4,7 @@ config MACH_INGENIC_GENERIC
bool
select MACH_INGENIC
select MACH_JZ4740
+ select MACH_JZ4755
select MACH_JZ4725B
select MACH_JZ4770
select MACH_JZ4780
@@ -53,6 +54,10 @@ config MACH_JZ4740
bool
select SYS_HAS_CPU_MIPS32_R1
+config MACH_JZ4755
+ bool
+ select SYS_HAS_CPU_MIPS32_R1
+
config MACH_JZ4770
bool
select MIPS_CPU_SCACHE
--
2.36.1
Add support for the clocks provided by the CGU in the Ingenic JZ4755
SoC.
Signed-off-by: Siarhei Volkau <[email protected]>
---
drivers/clk/ingenic/Kconfig | 10 +
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/jz4755-cgu.c | 350 +++++++++++++++++++++++++++++++
3 files changed, 361 insertions(+)
create mode 100644 drivers/clk/ingenic/jz4755-cgu.c
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index 898f1bc47..f80ac4f29 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -15,6 +15,16 @@ config INGENIC_CGU_JZ4740
If building for a JZ4740 SoC, you want to say Y here.
+config INGENIC_CGU_JZ4755
+ bool "Ingenic JZ4755 CGU driver"
+ default MACH_JZ4755
+ select INGENIC_CGU_COMMON
+ help
+ Support the clocks provided by the CGU hardware on Ingenic JZ4755
+ and compatible SoCs.
+
+ If building for a JZ4755 SoC, you want to say Y here.
+
config INGENIC_CGU_JZ4725B
bool "Ingenic JZ4725B CGU driver"
default MACH_JZ4725B
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 9edfaf461..81d8e23c2 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
+obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c
new file mode 100644
index 000000000..98887f20b
--- /dev/null
+++ b/drivers/clk/ingenic/jz4755-cgu.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Ingenic JZ4755 SoC CGU driver
+ * Heavily based on JZ4725b CGU driver
+ *
+ * Copyright (C) 2022 Siarhei Volkau
+ * Author: Siarhei Volkau <[email protected]>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+
+#include <dt-bindings/clock/ingenic,jz4755-cgu.h>
+
+#include "cgu.h"
+#include "pm.h"
+
+/* CGU register offsets */
+#define CGU_REG_CPCCR 0x00
+#define CGU_REG_LCR 0x04
+#define CGU_REG_CPPCR 0x10
+#define CGU_REG_CLKGR 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LPCDR 0x64
+#define CGU_REG_MSCCDR 0x68
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7C
+
+/* bits within the LCR register */
+#define LCR_SLEEP BIT(0)
+
+static struct ingenic_cgu *cgu;
+
+static const s8 pll_od_encoding[4] = {
+ 0x0, 0x1, -1, 0x3,
+};
+
+static const u8 jz4755_cgu_cpccr_div_table[] = {
+ 1, 2, 3, 4, 6, 8,
+};
+
+static const u8 jz4755_cgu_pll_half_div_table[] = {
+ 2, 1,
+};
+
+static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = {
+
+ /* External clocks */
+
+ [JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT },
+ [JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
+
+ [JZ4755_CLK_PLL] = {
+ "pll", CGU_CLK_PLL,
+ .parents = { JZ4755_CLK_EXT, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_CPPCR,
+ .rate_multiplier = 1,
+ .m_shift = 23,
+ .m_bits = 9,
+ .m_offset = 2,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 2,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 4,
+ .od_encoding = pll_od_encoding,
+ .stable_bit = 10,
+ .bypass_reg = CGU_REG_CPPCR,
+ .bypass_bit = 9,
+ .enable_bit = 8,
+ },
+ },
+
+ /* Muxes & dividers */
+
+ [JZ4755_CLK_PLL_HALF] = {
+ "pll half", CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+ .div = {
+ CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
+ jz4755_cgu_pll_half_div_table,
+ },
+ },
+
+ [JZ4755_CLK_EXT_HALF] = {
+ "ext half", CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_EXT, -1, -1, -1 },
+ .div = {
+ CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0,
+ 0,
+ },
+ },
+
+ [JZ4755_CLK_CCLK] = {
+ "cclk", CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+ .div = {
+ CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
+ jz4755_cgu_cpccr_div_table,
+ },
+ },
+
+ [JZ4755_CLK_H0CLK] = {
+ "hclk", CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+ .div = {
+ CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
+ jz4755_cgu_cpccr_div_table,
+ },
+ },
+
+ [JZ4755_CLK_PCLK] = {
+ "pclk", CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+ .div = {
+ CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
+ jz4755_cgu_cpccr_div_table,
+ },
+ },
+
+ [JZ4755_CLK_MCLK] = {
+ "mclk", CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+ .div = {
+ CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
+ jz4755_cgu_cpccr_div_table,
+ },
+ },
+
+ [JZ4755_CLK_H1CLK] = {
+ "h1clk", CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+ .div = {
+ CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
+ jz4755_cgu_cpccr_div_table,
+ },
+ },
+
+ [JZ4755_CLK_UDC] = {
+ "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 },
+ .mux = { CGU_REG_CPCCR, 29, 1 },
+ .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 10 },
+ },
+
+ [JZ4755_CLK_LCD] = {
+ "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
+ .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 9 },
+ },
+
+ [JZ4755_CLK_MMC] = {
+ "mmc", CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
+ .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
+ },
+
+ [JZ4755_CLK_I2S] = {
+ "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 },
+ .mux = { CGU_REG_CPCCR, 31, 1 },
+ .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
+ },
+
+ [JZ4755_CLK_SPI] = {
+ "spi", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
+ .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 4 },
+ },
+
+ [JZ4755_CLK_TVE] = {
+ "tve", CGU_CLK_MUX | CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, -1, -1 },
+ .mux = { CGU_REG_LPCDR, 31, 1 },
+ .gate = { CGU_REG_CLKGR, 18 },
+ },
+
+ [JZ4755_CLK_RTC] = {
+ "rtc", CGU_CLK_MUX | CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, -1, -1 },
+ .mux = { CGU_REG_OPCR, 2, 1},
+ .gate = { CGU_REG_CLKGR, 2 },
+ },
+
+ [JZ4755_CLK_CIM] = {
+ "cim", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
+ .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 8 },
+ },
+
+ /* Gate-only clocks */
+
+ [JZ4755_CLK_UART0] = {
+ "uart0", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 0 },
+ },
+
+ [JZ4755_CLK_UART1] = {
+ "uart1", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 14 },
+ },
+
+ [JZ4755_CLK_UART2] = {
+ "uart2", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 15 },
+ },
+
+ [JZ4755_CLK_ADC] = {
+ "adc", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 7 },
+ },
+
+ [JZ4755_CLK_AIC] = {
+ "aic", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_I2S, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 5 },
+ },
+
+ [JZ4755_CLK_I2C] = {
+ "i2c", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 3 },
+ },
+
+ [JZ4755_CLK_BCH] = {
+ "bch", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_MCLK/* not sure */, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 11 },
+ },
+
+ [JZ4755_CLK_TCU] = {
+ "tcu", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 1 },
+ },
+
+ [JZ4755_CLK_DMA] = {
+ "dma", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_PCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 12 },
+ },
+
+ [JZ4755_CLK_MMC0] = {
+ "mmc0", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_MMC, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 6 },
+ },
+
+ [JZ4755_CLK_MMC1] = {
+ "mmc1", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_MMC, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 16 },
+ },
+
+ [JZ4755_CLK_AUX_CPU] = {
+ "aux_cpu", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 24 },
+ },
+
+ [JZ4755_CLK_AHB1] = {
+ "ahb1", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 23 },
+ },
+
+ [JZ4755_CLK_IDCT] = {
+ "idct", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 22 },
+ },
+
+ [JZ4755_CLK_DB] = {
+ "db", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 21 },
+ },
+
+ [JZ4755_CLK_ME] = {
+ "me", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 20 },
+ },
+
+ [JZ4755_CLK_MC] = {
+ "mc", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 19 },
+ },
+
+ [JZ4755_CLK_TSSI] = {
+ "tssi", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT_HALF/* not sure */, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 17 },
+ },
+
+ [JZ4755_CLK_IPU] = {
+ "ipu", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_PLL_HALF/* not sure */, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 13 },
+ },
+
+ [JZ4755_CLK_EXT512] = {
+ "ext/512", CGU_CLK_FIXDIV,
+ .parents = { JZ4755_CLK_EXT },
+
+ /* JZ4725b doc calls it EXT512, but it seems to be /256...
+ * Not sure if it applied to JZ4755 too, and which actual
+ * source is used EXT or EXT_HALF
+ */
+ .fixdiv = { 256 },
+ },
+
+ [JZ4755_CLK_UDC_PHY] = {
+ "udc_phy", CGU_CLK_GATE,
+ .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+ .gate = { CGU_REG_OPCR, 6, true },
+ },
+};
+
+static void __init jz4755_cgu_init(struct device_node *np)
+{
+ int retval;
+
+ cgu = ingenic_cgu_new(jz4755_cgu_clocks,
+ ARRAY_SIZE(jz4755_cgu_clocks), np);
+ if (!cgu) {
+ pr_err("%s: failed to initialise CGU\n", __func__);
+ return;
+ }
+
+ retval = ingenic_cgu_register_clocks(cgu);
+ if (retval)
+ pr_err("%s: failed to register CGU Clocks\n", __func__);
+
+ ingenic_cgu_register_syscore_ops(cgu);
+}
+CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init);
--
2.36.1
Hi Siarhei,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next vkoul-dmaengine/next linus/master v6.0 next-20221007]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: ia64-allyesconfig
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/d0252164e0fa9fdb0493eead109a4b24bd873a03
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
git checkout d0252164e0fa9fdb0493eead109a4b24bd873a03
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/tty/serial/8250/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
drivers/tty/serial/8250/8250_ingenic.c: In function 'jz4750_early_console_setup':
drivers/tty/serial/8250/8250_ingenic.c:142:34: error: implicit declaration of function 'CKSEG1ADDR' [-Werror=implicit-function-declaration]
142 | #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
| ^~~~~~~~~~
drivers/tty/serial/8250/8250_ingenic.c:144:27: note: in expansion of macro 'CGU_REG_CPCCR'
144 | u32 cpccr = readl(CGU_REG_CPCCR);
| ^~~~~~~~~~~~~
>> drivers/tty/serial/8250/8250_ingenic.c:142:26: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
142 | #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
| ^
drivers/tty/serial/8250/8250_ingenic.c:144:27: note: in expansion of macro 'CGU_REG_CPCCR'
144 | u32 cpccr = readl(CGU_REG_CPCCR);
| ^~~~~~~~~~~~~
{standard input}: Assembler messages:
{standard input}:790: Error: Register number out of range 0..4
{standard input}:791: Error: Register number out of range 0..4
{standard input}:791: Warning: Use of 'mov' violates WAW dependency 'GR%, % in 1 - 127' (impliedf), specific resource number is 42
{standard input}:791: Warning: Only the first path encountering the conflict is reported
{standard input}:790: Warning: This is the location of the conflicting usage
{standard input}:795: Error: Register number out of range 0..4
cc1: some warnings being treated as errors
vim +142 drivers/tty/serial/8250/8250_ingenic.c
138
139 static int __init jz4750_early_console_setup(struct earlycon_device *dev,
140 const char *opt)
141 {
> 142 #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
143 #define CPCCR_ECS BIT(30)
144 u32 cpccr = readl(CGU_REG_CPCCR);
145 int clk_div = (cpccr & CPCCR_ECS) ? 2 : 1;
146 #undef CGU_REG_CPCCR
147 #undef CPCCR_ECS
148
149 return ingenic_earlycon_setup_common(dev, opt, clk_div);
150 }
151
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On Sun, Oct 09, 2022 at 09:13:32PM +0300, Siarhei Volkau wrote:
> This will be used from the devicetree bindings to specify the clocks
> that should be obtained from the jz4755-cgu driver.
>
> Signed-off-by: Siarhei Volkau <[email protected]>
> ---
> .../dt-bindings/clock/ingenic,jz4755-cgu.h | 49 +++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h
>
> diff --git a/include/dt-bindings/clock/ingenic,jz4755-cgu.h b/include/dt-bindings/clock/ingenic,jz4755-cgu.h
> new file mode 100644
> index 000000000..32307f68c
> --- /dev/null
> +++ b/include/dt-bindings/clock/ingenic,jz4755-cgu.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
Dual license please.
> +/*
> + * This header provides clock numbers for the ingenic,jz4755-cgu DT binding.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__
> +#define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__
> +
> +#define JZ4755_CLK_EXT 0
> +#define JZ4755_CLK_OSC32K 1
> +#define JZ4755_CLK_PLL 2
> +#define JZ4755_CLK_PLL_HALF 3
> +#define JZ4755_CLK_EXT_HALF 4
> +#define JZ4755_CLK_CCLK 5
> +#define JZ4755_CLK_H0CLK 6
> +#define JZ4755_CLK_PCLK 7
> +#define JZ4755_CLK_MCLK 8
> +#define JZ4755_CLK_H1CLK 9
> +#define JZ4755_CLK_UDC 10
> +#define JZ4755_CLK_LCD 11
> +#define JZ4755_CLK_UART0 12
> +#define JZ4755_CLK_UART1 13
> +#define JZ4755_CLK_UART2 14
> +#define JZ4755_CLK_DMA 15
> +#define JZ4755_CLK_MMC 16
> +#define JZ4755_CLK_MMC0 17
> +#define JZ4755_CLK_MMC1 18
> +#define JZ4755_CLK_EXT512 19
> +#define JZ4755_CLK_RTC 20
> +#define JZ4755_CLK_UDC_PHY 21
> +#define JZ4755_CLK_I2S 22
> +#define JZ4755_CLK_SPI 23
> +#define JZ4755_CLK_AIC 24
> +#define JZ4755_CLK_ADC 25
> +#define JZ4755_CLK_TCU 26
> +#define JZ4755_CLK_BCH 27
> +#define JZ4755_CLK_I2C 28
> +#define JZ4755_CLK_TVE 29
> +#define JZ4755_CLK_CIM 30
> +#define JZ4755_CLK_AUX_CPU 31
> +#define JZ4755_CLK_AHB1 32
> +#define JZ4755_CLK_IDCT 33
> +#define JZ4755_CLK_DB 34
> +#define JZ4755_CLK_ME 35
> +#define JZ4755_CLK_MC 36
> +#define JZ4755_CLK_TSSI 37
> +#define JZ4755_CLK_IPU 38
> +
> +#endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */
> --
> 2.36.1
>
>
On 09/10/2022 14:13, Siarhei Volkau wrote:
> Add preliminary support for boards based on the JZ4755 SoC from
> Ingenic.
>
> It is a low-power SoC with a MIPS32r1 SoC running at ~432 MHz, and no
> FPU.
>
> The JZ4755 SoC is supposed to be newer than the JZ4725B SoC, but its
> internals are very close to each other. So JZ4755 DT is reusing many
> JZ4725b drivers because JZ4725b support in the kernel appears earlier.
>
> Signed-off-by: Siarhei Volkau <[email protected]>
> ---
> arch/mips/boot/dts/ingenic/jz4755.dtsi | 439 +++++++++++++++++++++++++
How do you build it? How do you test it? It's basically non-compillable,
dead code. You need a board.
Best regards,
Krzysztof
On 09/10/2022 14:13, Siarhei Volkau wrote:
> JZ4755 is a low-power SoC similar to JZ4725B which is already here.
>
> The patch adds compatibles for parts which aren't implemented yet and
> they are subject of this patch serie.
>
> Signed-off-by: Siarhei Volkau <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++
> Documentation/devicetree/bindings/dma/ingenic,dma.yaml | 1 +
> Documentation/devicetree/bindings/serial/ingenic,uart.yaml | 4 ++++
How do you plan to merge it? Usually these go via subsystem trees...
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Hi Siarhei,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on robh/for-next vkoul-dmaengine/next linus/master v6.0 next-20221010]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm64-randconfig-r035-20221010
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/d0252164e0fa9fdb0493eead109a4b24bd873a03
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
git checkout d0252164e0fa9fdb0493eead109a4b24bd873a03
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/tty/serial/8250/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All error/warnings (new ones prefixed by >>):
>> drivers/tty/serial/8250/8250_ingenic.c:144:20: error: call to undeclared function 'CKSEG1ADDR'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
u32 cpccr = readl(CGU_REG_CPCCR);
^
drivers/tty/serial/8250/8250_ingenic.c:142:32: note: expanded from macro 'CGU_REG_CPCCR'
#define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
^
>> drivers/tty/serial/8250/8250_ingenic.c:144:20: warning: cast to 'void *' from smaller integer type 'int' [-Wint-to-void-pointer-cast]
u32 cpccr = readl(CGU_REG_CPCCR);
^~~~~~~~~~~~~
drivers/tty/serial/8250/8250_ingenic.c:142:24: note: expanded from macro 'CGU_REG_CPCCR'
#define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning and 1 error generated.
vim +/CKSEG1ADDR +144 drivers/tty/serial/8250/8250_ingenic.c
138
139 static int __init jz4750_early_console_setup(struct earlycon_device *dev,
140 const char *opt)
141 {
142 #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
143 #define CPCCR_ECS BIT(30)
> 144 u32 cpccr = readl(CGU_REG_CPCCR);
145 int clk_div = (cpccr & CPCCR_ECS) ? 2 : 1;
146 #undef CGU_REG_CPCCR
147 #undef CPCCR_ECS
148
149 return ingenic_earlycon_setup_common(dev, opt, clk_div);
150 }
151
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Hi Siarhei,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next vkoul-dmaengine/next linus/master v6.0 next-20221010]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: mips-randconfig-s042-20221010
compiler: mips64el-linux-gcc (GCC) 12.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-39-gce1a6720-dirty
# https://github.com/intel-lab-lkp/linux/commit/6d24b5a35a40bad51094228d64da242aa0516d83
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
git checkout 6d24b5a35a40bad51094228d64da242aa0516d83
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=mips SHELL=/bin/bash drivers/clk/ingenic/ drivers/tty/serial/8250/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
sparse warnings: (new ones prefixed by >>)
>> drivers/clk/ingenic/jz4755-cgu.c:94:25: sparse: sparse: Using plain integer as NULL pointer
vim +94 drivers/clk/ingenic/jz4755-cgu.c
49
50 /* External clocks */
51
52 [JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT },
53 [JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
54
55 [JZ4755_CLK_PLL] = {
56 "pll", CGU_CLK_PLL,
57 .parents = { JZ4755_CLK_EXT, -1, -1, -1 },
58 .pll = {
59 .reg = CGU_REG_CPPCR,
60 .rate_multiplier = 1,
61 .m_shift = 23,
62 .m_bits = 9,
63 .m_offset = 2,
64 .n_shift = 18,
65 .n_bits = 5,
66 .n_offset = 2,
67 .od_shift = 16,
68 .od_bits = 2,
69 .od_max = 4,
70 .od_encoding = pll_od_encoding,
71 .stable_bit = 10,
72 .bypass_reg = CGU_REG_CPPCR,
73 .bypass_bit = 9,
74 .enable_bit = 8,
75 },
76 },
77
78 /* Muxes & dividers */
79
80 [JZ4755_CLK_PLL_HALF] = {
81 "pll half", CGU_CLK_DIV,
82 .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
83 .div = {
84 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
85 jz4755_cgu_pll_half_div_table,
86 },
87 },
88
89 [JZ4755_CLK_EXT_HALF] = {
90 "ext half", CGU_CLK_DIV,
91 .parents = { JZ4755_CLK_EXT, -1, -1, -1 },
92 .div = {
93 CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0,
> 94 0,
95 },
96 },
97
98 [JZ4755_CLK_CCLK] = {
99 "cclk", CGU_CLK_DIV,
100 .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
101 .div = {
102 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
103 jz4755_cgu_cpccr_div_table,
104 },
105 },
106
107 [JZ4755_CLK_H0CLK] = {
108 "hclk", CGU_CLK_DIV,
109 .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
110 .div = {
111 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
112 jz4755_cgu_cpccr_div_table,
113 },
114 },
115
116 [JZ4755_CLK_PCLK] = {
117 "pclk", CGU_CLK_DIV,
118 .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
119 .div = {
120 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
121 jz4755_cgu_cpccr_div_table,
122 },
123 },
124
125 [JZ4755_CLK_MCLK] = {
126 "mclk", CGU_CLK_DIV,
127 .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
128 .div = {
129 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
130 jz4755_cgu_cpccr_div_table,
131 },
132 },
133
134 [JZ4755_CLK_H1CLK] = {
135 "h1clk", CGU_CLK_DIV,
136 .parents = { JZ4755_CLK_PLL, -1, -1, -1 },
137 .div = {
138 CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
139 jz4755_cgu_cpccr_div_table,
140 },
141 },
142
143 [JZ4755_CLK_UDC] = {
144 "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
145 .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 },
146 .mux = { CGU_REG_CPCCR, 29, 1 },
147 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
148 .gate = { CGU_REG_CLKGR, 10 },
149 },
150
151 [JZ4755_CLK_LCD] = {
152 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
153 .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
154 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
155 .gate = { CGU_REG_CLKGR, 9 },
156 },
157
158 [JZ4755_CLK_MMC] = {
159 "mmc", CGU_CLK_DIV,
160 .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
161 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
162 },
163
164 [JZ4755_CLK_I2S] = {
165 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
166 .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 },
167 .mux = { CGU_REG_CPCCR, 31, 1 },
168 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
169 },
170
171 [JZ4755_CLK_SPI] = {
172 "spi", CGU_CLK_DIV | CGU_CLK_GATE,
173 .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
174 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
175 .gate = { CGU_REG_CLKGR, 4 },
176 },
177
178 [JZ4755_CLK_TVE] = {
179 "tve", CGU_CLK_MUX | CGU_CLK_GATE,
180 .parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, -1, -1 },
181 .mux = { CGU_REG_LPCDR, 31, 1 },
182 .gate = { CGU_REG_CLKGR, 18 },
183 },
184
185 [JZ4755_CLK_RTC] = {
186 "rtc", CGU_CLK_MUX | CGU_CLK_GATE,
187 .parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, -1, -1 },
188 .mux = { CGU_REG_OPCR, 2, 1},
189 .gate = { CGU_REG_CLKGR, 2 },
190 },
191
192 [JZ4755_CLK_CIM] = {
193 "cim", CGU_CLK_DIV | CGU_CLK_GATE,
194 .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
195 .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
196 .gate = { CGU_REG_CLKGR, 8 },
197 },
198
199 /* Gate-only clocks */
200
201 [JZ4755_CLK_UART0] = {
202 "uart0", CGU_CLK_GATE,
203 .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
204 .gate = { CGU_REG_CLKGR, 0 },
205 },
206
207 [JZ4755_CLK_UART1] = {
208 "uart1", CGU_CLK_GATE,
209 .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
210 .gate = { CGU_REG_CLKGR, 14 },
211 },
212
213 [JZ4755_CLK_UART2] = {
214 "uart2", CGU_CLK_GATE,
215 .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
216 .gate = { CGU_REG_CLKGR, 15 },
217 },
218
219 [JZ4755_CLK_ADC] = {
220 "adc", CGU_CLK_GATE,
221 .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
222 .gate = { CGU_REG_CLKGR, 7 },
223 },
224
225 [JZ4755_CLK_AIC] = {
226 "aic", CGU_CLK_GATE,
227 .parents = { JZ4755_CLK_I2S, -1, -1, -1 },
228 .gate = { CGU_REG_CLKGR, 5 },
229 },
230
231 [JZ4755_CLK_I2C] = {
232 "i2c", CGU_CLK_GATE,
233 .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
234 .gate = { CGU_REG_CLKGR, 3 },
235 },
236
237 [JZ4755_CLK_BCH] = {
238 "bch", CGU_CLK_GATE,
239 .parents = { JZ4755_CLK_MCLK/* not sure */, -1, -1, -1 },
240 .gate = { CGU_REG_CLKGR, 11 },
241 },
242
243 [JZ4755_CLK_TCU] = {
244 "tcu", CGU_CLK_GATE,
245 .parents = { JZ4755_CLK_EXT, -1, -1, -1 },
246 .gate = { CGU_REG_CLKGR, 1 },
247 },
248
249 [JZ4755_CLK_DMA] = {
250 "dma", CGU_CLK_GATE,
251 .parents = { JZ4755_CLK_PCLK, -1, -1, -1 },
252 .gate = { CGU_REG_CLKGR, 12 },
253 },
254
255 [JZ4755_CLK_MMC0] = {
256 "mmc0", CGU_CLK_GATE,
257 .parents = { JZ4755_CLK_MMC, -1, -1, -1 },
258 .gate = { CGU_REG_CLKGR, 6 },
259 },
260
261 [JZ4755_CLK_MMC1] = {
262 "mmc1", CGU_CLK_GATE,
263 .parents = { JZ4755_CLK_MMC, -1, -1, -1 },
264 .gate = { CGU_REG_CLKGR, 16 },
265 },
266
267 [JZ4755_CLK_AUX_CPU] = {
268 "aux_cpu", CGU_CLK_GATE,
269 .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
270 .gate = { CGU_REG_CLKGR, 24 },
271 },
272
273 [JZ4755_CLK_AHB1] = {
274 "ahb1", CGU_CLK_GATE,
275 .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
276 .gate = { CGU_REG_CLKGR, 23 },
277 },
278
279 [JZ4755_CLK_IDCT] = {
280 "idct", CGU_CLK_GATE,
281 .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
282 .gate = { CGU_REG_CLKGR, 22 },
283 },
284
285 [JZ4755_CLK_DB] = {
286 "db", CGU_CLK_GATE,
287 .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
288 .gate = { CGU_REG_CLKGR, 21 },
289 },
290
291 [JZ4755_CLK_ME] = {
292 "me", CGU_CLK_GATE,
293 .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
294 .gate = { CGU_REG_CLKGR, 20 },
295 },
296
297 [JZ4755_CLK_MC] = {
298 "mc", CGU_CLK_GATE,
299 .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
300 .gate = { CGU_REG_CLKGR, 19 },
301 },
302
303 [JZ4755_CLK_TSSI] = {
304 "tssi", CGU_CLK_GATE,
305 .parents = { JZ4755_CLK_EXT_HALF/* not sure */, -1, -1, -1 },
306 .gate = { CGU_REG_CLKGR, 17 },
307 },
308
309 [JZ4755_CLK_IPU] = {
310 "ipu", CGU_CLK_GATE,
311 .parents = { JZ4755_CLK_PLL_HALF/* not sure */, -1, -1, -1 },
312 .gate = { CGU_REG_CLKGR, 13 },
313 },
314
315 [JZ4755_CLK_EXT512] = {
316 "ext/512", CGU_CLK_FIXDIV,
317 .parents = { JZ4755_CLK_EXT },
318
319 /* JZ4725b doc calls it EXT512, but it seems to be /256...
320 * Not sure if it applied to JZ4755 too, and which actual
321 * source is used EXT or EXT_HALF
322 */
323 .fixdiv = { 256 },
324 },
325
326 [JZ4755_CLK_UDC_PHY] = {
327 "udc_phy", CGU_CLK_GATE,
328 .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
329 .gate = { CGU_REG_OPCR, 6, true },
330 },
331 };
332
--
0-DAY CI Kernel Test Service
https://01.org/lkp
> How do you build it? How do you test it? It's basically non-compillable,
> dead code. You need a board.
I tested it on a Ritmix RZX-50 handheld, although this patchset doesn't
include it as it requires many other changes to be fully functional.
I decided to do this in two steps: add platform first (this patchset) then
specific drivers and quirks, in the next patchset, when this one passes.
Of course I can add machine's dts with working parts. What's the usual way?
On Sun, Oct 09, 2022 at 09:13:36PM +0300, Siarhei Volkau wrote:
> These SoCs are close to others but they have a clock divisor /2 for low
> clock peripherals, thus to set up a proper baud rate we need to take
> this into account.
>
> The divisor bit is located in CGU area, unfortunately the clk framework
> can't be used at early boot steps, so it's checked by direct readl()
> call.
>
> Signed-off-by: Siarhei Volkau <[email protected]>
> ---
> drivers/tty/serial/8250/8250_ingenic.c | 39 ++++++++++++++++++++++----
> 1 file changed, 34 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c
> index 2b2f5d8d2..f2662720d 100644
> --- a/drivers/tty/serial/8250/8250_ingenic.c
> +++ b/drivers/tty/serial/8250/8250_ingenic.c
> @@ -70,7 +70,8 @@ static void ingenic_early_console_write(struct console *console,
> ingenic_early_console_putc);
> }
>
> -static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
> +static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev,
> + int clkdiv)
What does "clkdiv" mean here?
And this function is rough, adding a random integer to a function
requires you to look it up every time you see this call.
If you only have 1 or 2 as an option, just have 2 functions instead
please.
thanks,
greg k-h
пн, 10 окт. 2022 г. в 17:55, Krzysztof Kozlowski
<[email protected]>:
> How do you plan to merge it? Usually these go via subsystem trees...
It's a new case for me, could you explain the problem a bit more?
What things should I bother with in the next patchset version?
Thanks in advance.
Hi Siarhei,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next vkoul-dmaengine/next linus/master v6.0 next-20221010]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: mips-randconfig-s042-20221010
compiler: mips64el-linux-gcc (GCC) 12.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-39-gce1a6720-dirty
# https://github.com/intel-lab-lkp/linux/commit/d0252164e0fa9fdb0493eead109a4b24bd873a03
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
git checkout d0252164e0fa9fdb0493eead109a4b24bd873a03
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=mips SHELL=/bin/bash drivers/tty/serial/8250/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
sparse warnings: (new ones prefixed by >>)
>> drivers/tty/serial/8250/8250_ingenic.c:144:27: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got void * @@
drivers/tty/serial/8250/8250_ingenic.c:144:27: sparse: expected void const volatile [noderef] __iomem *mem
drivers/tty/serial/8250/8250_ingenic.c:144:27: sparse: got void *
vim +144 drivers/tty/serial/8250/8250_ingenic.c
138
139 static int __init jz4750_early_console_setup(struct earlycon_device *dev,
140 const char *opt)
141 {
142 #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
143 #define CPCCR_ECS BIT(30)
> 144 u32 cpccr = readl(CGU_REG_CPCCR);
145 int clk_div = (cpccr & CPCCR_ECS) ? 2 : 1;
146 #undef CGU_REG_CPCCR
147 #undef CPCCR_ECS
148
149 return ingenic_earlycon_setup_common(dev, opt, clk_div);
150 }
151
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On 10/10/2022 16:18, Siarhei Volkau wrote:
> пн, 10 окт. 2022 г. в 17:55, Krzysztof Kozlowski
> <[email protected]>:
>
>> How do you plan to merge it? Usually these go via subsystem trees...
>
> It's a new case for me, could you explain the problem a bit more?
> What things should I bother with in the next patchset version?
> Thanks in advance.
Each binding goes via subsystem maintainer, not via DT bindings tree, so
keeping all in one patch messes with that.
Best regards,
Krzysztof
On 10/10/2022 16:00, Siarhei Volkau wrote:
>> How do you build it? How do you test it? It's basically non-compillable,
>> dead code. You need a board.
>
> I tested it on a Ritmix RZX-50 handheld,
You cannot, there is no such DTS.
> although this patchset doesn't
> include it as it requires many other changes to be fully functional.
Exactly.
> I decided to do this in two steps: add platform first (this patchset) then
> specific drivers and quirks, in the next patchset, when this one passes.
>
> Of course I can add machine's dts with working parts. What's the usual way?
Don't add dead code to the kernel, so DTSI comes with DTS.
Best regards,
Krzysztof
пн, 10 окт. 2022 г. в 23:20, Greg Kroah-Hartman <[email protected]>:
> What does "clkdiv" mean here?
That means a clock divisor between the input oscillator and UART
peripheral clock source. Most Ingenic SoCs don't have that divisor,
so 1 is always in effect for them.
However, the JZ4750 and JZ4755 have switchable /2 clock divisor.
> If you only have 1 or 2 as an option
Yes, it is.
> just have 2 functions instead please.
Got it, will do that.
Thank you.
пн, 10 окт. 2022 г. в 01:29, kernel test robot <[email protected]>:
> config: ia64-allyesconfig
> config: arm64-randconfig-r035-20221010
> > 142 #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
> 0-DAY CI Kernel Test Service
I know CKSEG1ADDR is MIPS specific, might be it needed to disable COMPILE_TEST
on the driver?
Since early syscon isn't mainlined yet I don't see any other way at the moment.
Any suggestions on that, folks?
On Thu, Oct 13, 2022, at 8:37 AM, Siarhei Volkau wrote:
> пн, 10 окт. 2022 г. в 01:29, kernel test robot <[email protected]>:
>> config: ia64-allyesconfig
>> config: arm64-randconfig-r035-20221010
>
>> > 142 #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
>
>> 0-DAY CI Kernel Test Service
>
> I know CKSEG1ADDR is MIPS specific, might be it needed to disable COMPILE_TEST
> on the driver?
> Since early syscon isn't mainlined yet I don't see any other way at the moment.
>
> Any suggestions on that, folks?
This looks like some setup that belongs into the bootloader. If you are
handing over the console from bootloader to kernel, the hardware should
already be in a working state, with no need to touch it during early
boot.
If you are dealing with broken bootloaders that are not under your control,
having this code in the architecture specific early boot as a fixup
would be better than putting it into the driver.
Arnd
Hi Siarhei,
Le lun., oct. 10 2022 at 23:18:05 +0300, Siarhei Volkau
<[email protected]> a écrit :
> пн, 10 окт. 2022 г. в 17:55, Krzysztof Kozlowski
> <[email protected]>:
>
>> How do you plan to merge it? Usually these go via subsystem trees...
>
> It's a new case for me, could you explain the problem a bit more?
> What things should I bother with in the next patchset version?
> Thanks in advance.
Just split the patchset, most of your patches (e.g. DMA patch, CGU,
pinctrl, UART) should be sent separately.
Otherwise it makes things much more complicated for merging.
Cheers,
-Paul
Hi,
Le jeu., oct. 13 2022 at 08:46:39 +0200, Arnd Bergmann <[email protected]>
a écrit :
> On Thu, Oct 13, 2022, at 8:37 AM, Siarhei Volkau wrote:
>> пн, 10 окт. 2022 г. в 01:29, kernel test robot
>> <[email protected]>:
>>> config: ia64-allyesconfig
>>> config: arm64-randconfig-r035-20221010
>>
>>> > 142 #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
>>
>>> 0-DAY CI Kernel Test Service
>>
>> I know CKSEG1ADDR is MIPS specific, might be it needed to disable
>> COMPILE_TEST
>> on the driver?
>> Since early syscon isn't mainlined yet I don't see any other way at
>> the moment.
>>
>> Any suggestions on that, folks?
>
> This looks like some setup that belongs into the bootloader. If you
> are
> handing over the console from bootloader to kernel, the hardware
> should
> already be in a working state, with no need to touch it during early
> boot.
>
> If you are dealing with broken bootloaders that are not under your
> control,
> having this code in the architecture specific early boot as a fixup
> would be better than putting it into the driver.
Agreed. I am not fond of having a driver poking into an unrelated
subsystem's memory area.
Just disable the divider in ingenic_fixup_fdt() in
arch/mips/generic/board-ingenic.c.
Cheers,
-Paul
чт, 13 окт. 2022 г. в 12:17, Paul Cercueil <[email protected]>:
>
> Just disable the divider in ingenic_fixup_fdt() in
> arch/mips/generic/board-ingenic.c.
>
> Cheers,
> -Paul
>
Looks reasonable, I hope the bootloader initialized peripherals can handle
doubled frequency, till re-initialization completes. I'll check that.
Thank you all, guys.
чт, 13 окт. 2022 г. в 21:56, Siarhei Volkau <[email protected]>:
> > Just disable the divider in ingenic_fixup_fdt() in
> I'll check that.
I checked that approach: serial seems to be working as expected,
but not all the time: there's a time period when the CGU driver
started but serial console driver is still early one.
In my case UART produces garbage at that period since CGU
needs to enable clock divider back: ext is 24MHz but 12MHz
required for audio codec and USB to function properly.
So I think Arnd's approach:
> the hardware should already be in a working state,
> with no need to touch it during early boot.
shall resolve the problem, although I can't check it on all supported
hardware.
BR,
Siarhei
Hi Siarhei,
Le dim., oct. 16 2022 at 21:39:48 +0300, Siarhei Volkau
<[email protected]> a écrit :
> чт, 13 окт. 2022 г. в 21:56, Siarhei Volkau
> <[email protected]>:
>
>> > Just disable the divider in ingenic_fixup_fdt() in
>
>> I'll check that.
>
> I checked that approach: serial seems to be working as expected,
> but not all the time: there's a time period when the CGU driver
> started but serial console driver is still early one.
> In my case UART produces garbage at that period since CGU
> needs to enable clock divider back: ext is 24MHz but 12MHz
> required for audio codec and USB to function properly.
What I'd do, is just force-enable it to 12 MHz in ingenic_fixup_fdt(),
since the programming manual basically says that 24 MHz does not work
properly.
Then in the earlycon setup code hardcode the /2 divider with a big fat
comment about why it's there.
Cheers,
-Paul
> So I think Arnd's approach:
>
>> the hardware should already be in a working state,
>> with no need to touch it during early boot.
>
> shall resolve the problem, although I can't check it on all supported
> hardware.
>
> BR,
> Siarhei
On Sun, Oct 9, 2022 at 8:14 PM Siarhei Volkau <[email protected]> wrote:
> Fixes UART1 function bits and mmc groups typo.
>
> For pins 0x97,0x99 function 0 is designated to PWM3/PWM5
> respectively, function is 1 designated to the UART1.
>
> Tested-by: Siarhei Volkau <[email protected]>
> Signed-off-by: Siarhei Volkau <[email protected]>
This patch applied for fixes.
Yours,
Linus Walleij
пн, 17 окт. 2022 г. в 12:32, Paul Cercueil <[email protected]>:
> > I checked that approach: serial seems to be working as expected,
> > but not all the time: there's a time period when the CGU driver
> > started but serial console driver is still early one.
> > In my case UART produces garbage at that period since CGU
> > needs to enable clock divider back: ext is 24MHz but 12MHz
> > required for audio codec and USB to function properly.
>
> What I'd do, is just force-enable it to 12 MHz in ingenic_fixup_fdt(),
> since the programming manual basically says that 24 MHz does not work
> properly.
>
> Then in the earlycon setup code hardcode the /2 divider with a big fat
> comment about why it's there.
Agree, the vendor's kernel does that as well.
Also I found that:
1. Many other drivers compile the early console only when
CONFIG_SERIAL_8250_CONSOLE is set.
2. All the early ingenic_ functions can be labeled as __init.
Shall I fix that while I'm already here?