2023-05-01 14:36:56

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 0/9] Add multiport support for DWC3 controllers

Currently the DWC3 driver supports only single port controller which
requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
DWC3 controller with multiple ports that can operate in host mode.
Some of the port supports both SS+HS and other port supports only HS
mode.

This change primarily refactors the Phy logic in core driver to allow
multiport support with Generic Phy's.

Chananges have been tested on QCOM SoC SA8295P which has 4 ports (2
are HS+SS capable and 2 are HS only capable).

Changes in v7:
Added power event irq's for Multiport controller.
Udpated commit text for patch-9 (adding DT changes for enabling first
port of multiport controller on sa8540-ride).
Fixed check-patch warnings for driver code.
Fixed DT binding errors for changes in snps,dwc3.yaml
Reabsed code on top of usb-next

Changes in v6:
Updated comments in code after.
Updated variables names appropriately as per review comments.
Updated commit text in patch-2 and added additional info as per review
comments.
The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected
it in this version.

Changes in v5:
Added DT support for first port of Teritiary USB controller on SA8540-Ride
Added support for reading port info from XHCI Extended Params registers.

Changes in RFC v4:
Added DT support for SA8295p.

Changes in RFC v3:
Incase any PHY init fails, then clear/exit the PHYs that
are already initialized.

Changes in RFC v2:
Changed dwc3_count_phys to return the number of PHY Phandles in the node.
This will be used now in dwc3_extract_num_phys to increment num_usb2_phy
and num_usb3_phy.

Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its
structure such that the first half is for HS-PHY and second half is for
SS-PHY.

In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is
present, pass proper SS_IDX else pass -1.

Link to v6: https://lore.kernel.org/all/[email protected]/
Link to v5: https://lore.kernel.org/all/[email protected]/
Link to RFC v4: https://lore.kernel.org/all/[email protected]/
Link to RFC v3: https://lore.kernel.org/all/[email protected]/#r
Link to RFC v2: https://lore.kernel.org/all/[email protected]/#r

Test results:

Bus 3/4 represent multiport controller having 4 HS ports and 2 SS ports.

/ # dmesg |grep hub
[ 0.029029] usbcore: registered new interface driver hub
[ 1.372812] hub 1-0:1.0: USB hub found
[ 1.389142] hub 1-0:1.0: 1 port detected
[ 1.414721] hub 2-0:1.0: USB hub found
[ 1.427669] hub 2-0:1.0: 1 port detected
[ 2.931465] hub 3-0:1.0: USB hub found
[ 2.935340] hub 3-0:1.0: 4 ports detected
[ 2.948721] hub 4-0:1.0: USB hub found
[ 2.952604] hub 4-0:1.0: 2 ports detected
/ #
/ # lsusb
Bus 003 Device 001: ID 1d6b:0002
Bus 001 Device 001: ID 1d6b:0002
Bus 003 Device 005: ID 0b0e:0300
Bus 003 Device 002: ID 046d:c077
Bus 004 Device 001: ID 1d6b:0003
Bus 002 Device 001: ID 1d6b:0003
Bus 003 Device 004: ID 03f0:0024
Bus 003 Device 003: ID 046d:c016


Krishna Kurapati (9):
dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport
dt-bindings: usb: Add bindings for multiport properties on DWC3
controller
usb: dwc3: core: Access XHCI address space temporarily to read port
info
usb: dwc3: core: Skip setting event buffers for host only controllers
usb: dwc3: core: Refactor PHY logic to support Multiport Controller
usb: dwc3: qcom: Add multiport controller support for qcom wrapper
arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
ports
arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
controller

.../devicetree/bindings/usb/qcom,dwc3.yaml | 21 ++
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++
drivers/usb/dwc3/core.c | 352 ++++++++++++++----
drivers/usb/dwc3/core.h | 68 +++-
drivers/usb/dwc3/drd.c | 13 +-
drivers/usb/dwc3/dwc3-qcom.c | 28 +-
9 files changed, 533 insertions(+), 95 deletions(-)

--
2.40.0


2023-05-01 14:36:59

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 4/9] usb: dwc3: core: Skip setting event buffers for host only controllers

On some SoC's like SA8295P where the tertiary controller is host-only
capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible.
Trying to setup them up during core_init leads to a crash.

For DRD/Peripheral supported controllers, event buffer setup is done
again in gadget_pullup. Skip setup or cleanup of event buffers if
controller is host-only capable.

Signed-off-by: Krishna Kurapati <[email protected]>
---
drivers/usb/dwc3/core.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index b8ac7bcee391..8625fc5c7ab4 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -835,7 +835,12 @@ static void dwc3_clk_disable(struct dwc3 *dwc)

static void dwc3_core_exit(struct dwc3 *dwc)
{
- dwc3_event_buffers_cleanup(dwc);
+ unsigned int hw_mode;
+
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST)
+ dwc3_event_buffers_cleanup(dwc);
+
dwc3_phy_power_off(dwc);
dwc3_phy_exit(dwc);
dwc3_clk_disable(dwc);
@@ -1141,10 +1146,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (ret)
goto err_exit_phy;

- ret = dwc3_event_buffers_setup(dwc);
- if (ret) {
- dev_err(dwc->dev, "failed to setup event buffers\n");
- goto err_power_off_phy;
+ if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) {
+ ret = dwc3_event_buffers_setup(dwc);
+ if (ret) {
+ dev_err(dwc->dev, "failed to setup event buffers\n");
+ goto err_power_off_phy;
+ }
}

/*
@@ -1958,7 +1965,10 @@ static int dwc3_probe(struct platform_device *pdev)

err_exit_debugfs:
dwc3_debugfs_exit(dwc);
- dwc3_event_buffers_cleanup(dwc);
+
+ if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST)
+ dwc3_event_buffers_cleanup(dwc);
+
dwc3_phy_power_off(dwc);
dwc3_phy_exit(dwc);
dwc3_ulpi_exit(dwc);
--
2.40.0

2023-05-01 14:37:02

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

Currently the DWC3 driver supports only single port controller
which requires at most one HS and one SS PHY.

But the DWC3 USB controller can be connected to multiple ports and
each port can have their own PHYs. Each port of the multiport
controller can either be HS+SS capable or HS only capable
Proper quantification of them is required to modify GUSB2PHYCFG
and GUSB3PIPECTL registers appropriately.

Add support for detecting, obtaining and configuring phy's supported
by a multiport controller and limit the max number of ports
supported to 4.

Signed-off-by: Harsh Agarwal <[email protected]>
Signed-off-by: Krishna Kurapati <[email protected]>
---
drivers/usb/dwc3/core.c | 262 +++++++++++++++++++++++++++++-----------
drivers/usb/dwc3/core.h | 12 +-
drivers/usb/dwc3/drd.c | 13 +-
3 files changed, 209 insertions(+), 78 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 8625fc5c7ab4..b91c3f965abc 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -121,6 +121,7 @@ static void __dwc3_set_mode(struct work_struct *work)
struct dwc3 *dwc = work_to_dwc(work);
unsigned long flags;
int ret;
+ int i;
u32 reg;
u32 desired_dr_role;

@@ -200,8 +201,10 @@ static void __dwc3_set_mode(struct work_struct *work)
} else {
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+ phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+ }
if (dwc->dis_split_quirk) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
reg |= DWC3_GUCTL3_SPLITDISABLE;
@@ -216,8 +219,8 @@ static void __dwc3_set_mode(struct work_struct *work)

if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);

ret = dwc3_gadget_init(dwc);
if (ret)
@@ -575,22 +578,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
return ret;
}

-/**
- * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
- * @dwc: Pointer to our controller context structure
- *
- * Returns 0 on success. The USB PHY interfaces are configured but not
- * initialized. The PHY interfaces and the PHYs get initialized together with
- * the core in dwc3_core_init.
- */
-static int dwc3_phy_setup(struct dwc3 *dwc)
+static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
{
unsigned int hw_mode;
u32 reg;

hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);

- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));

/*
* Make sure UX_EXIT_PX is cleared as that causes issues with some
@@ -645,9 +640,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->dis_del_phy_power_chg_quirk)
reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;

- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);

- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ return 0;
+}
+
+static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
+{
+ unsigned int hw_mode;
+ u32 reg;
+
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));

/* Select the HS PHY interface */
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
@@ -659,7 +664,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
} else if (dwc->hsphy_interface &&
!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
} else {
/* Relying on default value. */
if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
@@ -726,7 +731,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->ulpi_ext_vbus_drv)
reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;

- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
+
+ return 0;
+}
+
+/**
+ * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ *
+ * Returns 0 on success. The USB PHY interfaces are configured but not
+ * initialized. The PHY interfaces and the PHYs get initialized together with
+ * the core in dwc3_core_init.
+ */
+static int dwc3_phy_setup(struct dwc3 *dwc)
+{
+ int i;
+ int ret;
+
+ for (i = 0; i < dwc->num_usb3_ports; i++) {
+ ret = dwc3_ss_phy_setup(dwc, i);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = dwc3_hs_phy_setup(dwc, i);
+ if (ret)
+ return ret;
+ }

return 0;
}
@@ -734,22 +767,36 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
static int dwc3_phy_init(struct dwc3 *dwc)
{
int ret;
+ int i, j;

usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);

- ret = phy_init(dwc->usb2_generic_phy);
- if (ret < 0)
- goto err_shutdown_usb3_phy;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_init(dwc->usb2_generic_phy[i]);
+ if (ret < 0) {
+ /* clean up prior initialized HS PHYs */
+ for (j = 0; j < i; j++)
+ phy_exit(dwc->usb2_generic_phy[j]);
+ goto err_shutdown_usb3_phy;
+ }
+ }

- ret = phy_init(dwc->usb3_generic_phy);
- if (ret < 0)
- goto err_exit_usb2_phy;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_init(dwc->usb3_generic_phy[i]);
+ if (ret < 0) {
+ /* clean up prior initialized SS PHYs */
+ for (j = 0; j < i; j++)
+ phy_exit(dwc->usb3_generic_phy[j]);
+ goto err_exit_usb2_phy;
+ }
+ }

return 0;

err_exit_usb2_phy:
- phy_exit(dwc->usb2_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++)
+ phy_exit(dwc->usb2_generic_phy[i]);
err_shutdown_usb3_phy:
usb_phy_shutdown(dwc->usb3_phy);
usb_phy_shutdown(dwc->usb2_phy);
@@ -759,8 +806,12 @@ static int dwc3_phy_init(struct dwc3 *dwc)

static void dwc3_phy_exit(struct dwc3 *dwc)
{
- phy_exit(dwc->usb3_generic_phy);
- phy_exit(dwc->usb2_generic_phy);
+ int i;
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_exit(dwc->usb3_generic_phy[i]);
+ phy_exit(dwc->usb2_generic_phy[i]);
+ }

usb_phy_shutdown(dwc->usb3_phy);
usb_phy_shutdown(dwc->usb2_phy);
@@ -769,22 +820,36 @@ static void dwc3_phy_exit(struct dwc3 *dwc)
static int dwc3_phy_power_on(struct dwc3 *dwc)
{
int ret;
+ int i, j;

usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0);

- ret = phy_power_on(dwc->usb2_generic_phy);
- if (ret < 0)
- goto err_suspend_usb3_phy;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_power_on(dwc->usb2_generic_phy[i]);
+ if (ret < 0) {
+ /* Turn off prior ON'ed HS Phy's */
+ for (j = 0; j < i; j++)
+ phy_power_off(dwc->usb2_generic_phy[j]);
+ goto err_suspend_usb3_phy;
+ }
+ }

- ret = phy_power_on(dwc->usb3_generic_phy);
- if (ret < 0)
- goto err_power_off_usb2_phy;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_power_on(dwc->usb3_generic_phy[i]);
+ if (ret < 0) {
+ /* Turn of prior ON'ed SS Phy's */
+ for (j = 0; j < i; j++)
+ phy_power_off(dwc->usb3_generic_phy[j]);
+ goto err_power_off_usb2_phy;
+ }
+ }

return 0;

err_power_off_usb2_phy:
- phy_power_off(dwc->usb2_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++)
+ phy_power_off(dwc->usb2_generic_phy[i]);
err_suspend_usb3_phy:
usb_phy_set_suspend(dwc->usb3_phy, 1);
usb_phy_set_suspend(dwc->usb2_phy, 1);
@@ -794,8 +859,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc)

static void dwc3_phy_power_off(struct dwc3 *dwc)
{
- phy_power_off(dwc->usb3_generic_phy);
- phy_power_off(dwc->usb2_generic_phy);
+ int i;
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_power_off(dwc->usb3_generic_phy[i]);
+ phy_power_off(dwc->usb2_generic_phy[i]);
+ }

usb_phy_set_suspend(dwc->usb3_phy, 1);
usb_phy_set_suspend(dwc->usb2_phy, 1);
@@ -1073,6 +1142,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
unsigned int hw_mode;
u32 reg;
int ret;
+ int i;

hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);

@@ -1116,15 +1186,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
if (!dwc->dis_u3_susphy_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
- reg |= DWC3_GUSB3PIPECTL_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ for (i = 0; i < dwc->num_usb3_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
+ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
+ }
}

if (!dwc->dis_u2_susphy_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ reg |= DWC3_GUSB2PHYCFG_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }
}
}

@@ -1281,6 +1355,42 @@ static int dwc3_core_init(struct dwc3 *dwc)
return ret;
}

+static int dwc3_get_multiport_phys(struct dwc3 *dwc)
+{
+ int ret;
+ struct device *dev = dwc->dev;
+ int i;
+ char phy_name[11];
+
+ /*
+ * Each port is at least HS capable. So loop over num_usb2_ports
+ * to get available phy's.
+ */
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ sprintf(phy_name, "usb2-port%d", i);
+ dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
+ if (IS_ERR(dwc->usb2_generic_phy[i])) {
+ ret = PTR_ERR(dwc->usb2_generic_phy[i]);
+ if (ret == -ENOSYS || ret == -ENODEV)
+ dwc->usb2_generic_phy[i] = NULL;
+ else
+ return dev_err_probe(dev, ret, "usb2 phy: %s not configured\n", phy_name);
+ }
+
+ sprintf(phy_name, "usb3-port%d", i);
+ dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
+ if (IS_ERR(dwc->usb3_generic_phy[i])) {
+ ret = PTR_ERR(dwc->usb3_generic_phy[i]);
+ if (ret == -ENOSYS || ret == -ENODEV)
+ dwc->usb3_generic_phy[i] = NULL;
+ else
+ return dev_err_probe(dev, ret, "usb3 phy: %s not configured\n", phy_name);
+ }
+ }
+
+ return 0;
+}
+
static int dwc3_core_get_phy(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
@@ -1311,20 +1421,23 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
return dev_err_probe(dev, ret, "no usb3 phy configured\n");
}

- dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(dwc->usb2_generic_phy)) {
- ret = PTR_ERR(dwc->usb2_generic_phy);
+ if (dwc->num_usb2_ports > 1)
+ return dwc3_get_multiport_phys(dwc);
+
+ dwc->usb2_generic_phy[0] = devm_phy_get(dev, "usb2-phy");
+ if (IS_ERR(dwc->usb2_generic_phy[0])) {
+ ret = PTR_ERR(dwc->usb2_generic_phy[0]);
if (ret == -ENOSYS || ret == -ENODEV)
- dwc->usb2_generic_phy = NULL;
+ dwc->usb2_generic_phy[0] = NULL;
else
return dev_err_probe(dev, ret, "no usb2 phy configured\n");
}

- dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
- if (IS_ERR(dwc->usb3_generic_phy)) {
- ret = PTR_ERR(dwc->usb3_generic_phy);
+ dwc->usb3_generic_phy[0] = devm_phy_get(dev, "usb3-phy");
+ if (IS_ERR(dwc->usb3_generic_phy[0])) {
+ ret = PTR_ERR(dwc->usb3_generic_phy[0]);
if (ret == -ENOSYS || ret == -ENODEV)
- dwc->usb3_generic_phy = NULL;
+ dwc->usb3_generic_phy[0] = NULL;
else
return dev_err_probe(dev, ret, "no usb3 phy configured\n");
}
@@ -1336,6 +1449,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
int ret;
+ int i;

switch (dwc->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
@@ -1343,8 +1457,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)

if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);

ret = dwc3_gadget_init(dwc);
if (ret)
@@ -1355,8 +1469,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)

if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+ phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+ }

ret = dwc3_host_init(dwc);
if (ret)
@@ -2046,6 +2162,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc)

static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
{
+ int i;
unsigned long flags;
u32 reg;

@@ -2066,17 +2183,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
/* Let controller to suspend HSPHY before PHY driver suspends */
if (dwc->dis_u2_susphy_quirk ||
dwc->dis_enblslpm_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
- DWC3_GUSB2PHYCFG_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
+ DWC3_GUSB2PHYCFG_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }

/* Give some time for USB2 PHY to suspend */
usleep_range(5000, 6000);
}

- phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
- phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
+ phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
+ }
break;
case DWC3_GCTL_PRTCAP_OTG:
/* do nothing during runtime_suspend */
@@ -2105,6 +2226,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
{
unsigned long flags;
int ret;
+ int i;
u32 reg;

switch (dwc->current_dr_role) {
@@ -2125,17 +2247,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
break;
}
/* Restore GUSB2PHYCFG bits that were modified in suspend */
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- if (dwc->dis_u2_susphy_quirk)
- reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ if (dwc->dis_u2_susphy_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;

- if (dwc->dis_enblslpm_quirk)
- reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+ if (dwc->dis_enblslpm_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }

- phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
- phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
+ phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
+ }
break;
case DWC3_GCTL_PRTCAP_OTG:
/* nothing to do on runtime_resume */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 21312703e053..0bba074b44e4 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -35,6 +35,9 @@

#define DWC3_MSG_MAX 500

+/* Number of ports supported by a multiport controller */
+#define MAX_PORTS_SUPPORTED 4
+
/* Define XHCI Extcap register offsets for getting multiport info */
#define XHCI_HCC_PARAMS_OFFSET 0x10
#define DWC3_XHCI_HCSPARAMS1 0x04
@@ -1038,8 +1041,8 @@ struct dwc3_scratchpad_array {
* @usb3_phy: pointer to USB3 PHY
* @num_usb2_ports: number of usb2 ports.
* @num_usb3_ports: number of usb3 ports.
- * @usb2_generic_phy: pointer to USB2 PHY
- * @usb3_generic_phy: pointer to USB3 PHY
+ * @usb2_generic_phy: pointer to array of USB2 PHY
+ * @usb3_generic_phy: pointer to array of USB3 PHY
* @phys_ready: flag to indicate that PHYs are ready
* @ulpi: pointer to ulpi interface
* @ulpi_ready: flag to indicate that ULPI is initialized
@@ -1177,9 +1180,8 @@ struct dwc3 {

u32 num_usb2_ports;
u32 num_usb3_ports;
-
- struct phy *usb2_generic_phy;
- struct phy *usb3_generic_phy;
+ struct phy *usb2_generic_phy[MAX_PORTS_SUPPORTED];
+ struct phy *usb3_generic_phy[MAX_PORTS_SUPPORTED];

bool phys_ready;

diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index 039bf241769a..0377295717ab 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -328,6 +328,7 @@ static void dwc3_otg_device_exit(struct dwc3 *dwc)
void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
{
int ret;
+ int i;
u32 reg;
int id;
unsigned long flags;
@@ -386,9 +387,11 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
} else {
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- if (dwc->usb2_generic_phy)
- phy_set_mode(dwc->usb2_generic_phy,
- PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ if (dwc->usb2_generic_phy[i])
+ phy_set_mode(dwc->usb2_generic_phy[i],
+ PHY_MODE_USB_HOST);
+ }
}
break;
case DWC3_OTG_ROLE_DEVICE:
@@ -400,8 +403,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)

if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- if (dwc->usb2_generic_phy)
- phy_set_mode(dwc->usb2_generic_phy,
+ if (dwc->usb2_generic_phy[0])
+ phy_set_mode(dwc->usb2_generic_phy[0],
PHY_MODE_USB_DEVICE);
ret = dwc3_gadget_init(dwc);
if (ret)
--
2.40.0

2023-05-01 14:37:31

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 1/9] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport

Add the compatible string for SC8280 Multiport USB controller from
Qualcomm.

There are 4 power event irq interrupts supported by this controller
(one for each port of multiport). Added all the 4 as non-optional
interrupts for SC8280XP-MP

Signed-off-by: Krishna Kurapati <[email protected]>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index d84281926f10..2c96da1ce5b8 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,sc7180-dwc3
- qcom,sc7280-dwc3
- qcom,sc8280xp-dwc3
+ - qcom,sc8280xp-dwc3-mp
- qcom,sdm660-dwc3
- qcom,sdm670-dwc3
- qcom,sdm845-dwc3
@@ -455,6 +456,26 @@ allOf:
- const: dm_hs_phy_irq
- const: ss_phy_irq

+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8280xp-dwc3-mp
+ then:
+ properties:
+ interrupts:
+ maxItems: 7
+ interrupt-names:
+ items:
+ - const: pwr_event_1
+ - const: pwr_event_2
+ - const: pwr_event_3
+ - const: pwr_event_4
+ - const: dp_hs_phy_irq
+ - const: dm_hs_phy_irq
+ - const: ss_phy_irq
+
additionalProperties: false

examples:
--
2.40.0

2023-05-01 14:37:53

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 3/9] usb: dwc3: core: Access XHCI address space temporarily to read port info

Currently host-only capable DWC3 controllers support Multiport.
Temporarily map XHCI address space for host-only controllers and parse
XHCI Extended Capabilities registers to read number of usb2 ports and
usb3 ports present on multiport controller. Each USB Port is at least HS
capable.

The port info for usb2 and usb3 phy are identified as num_usb2_ports
and num_usb3_ports. The intention is as follows:

Wherever we need to perform phy operations like:

LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
{
phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
}

If number of usb2 ports is 3, loop can go from index 0-2 for
usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
if the first 2 ports are SS capable or some other ports like (2 and 3)
are SS capable. So instead, num_usb2_ports is used to loop around all
phy's (both hs and ss) for performing phy operations. If any
usb3_generic_phy turns out to be NULL, phy operation just bails out.

num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
phy's as we need to know how many SS capable ports are there for this.

Signed-off-by: Krishna Kurapati <[email protected]>
---
drivers/usb/dwc3/core.c | 68 +++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 58 +++++++++++++++++++++++++++++++++++
2 files changed, 126 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 0beaab932e7d..b8ac7bcee391 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1767,6 +1767,59 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
return 0;
}

+static int dwc3_read_port_info(struct dwc3 *dwc)
+{
+ void __iomem *regs;
+ u32 offset;
+ u32 temp;
+ u8 major_revision;
+ int ret = 0;
+
+ /*
+ * Remap xHCI address space to access XHCI ext cap regs,
+ * since it is needed to get port info.
+ */
+ regs = ioremap(dwc->xhci_resources[0].start,
+ resource_size(&dwc->xhci_resources[0]));
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ offset = dwc3_xhci_find_next_ext_cap(regs, 0,
+ XHCI_EXT_CAPS_PROTOCOL);
+ while (offset) {
+ temp = readl(regs + offset);
+ major_revision = XHCI_EXT_PORT_MAJOR(temp);
+
+ temp = readl(regs + offset + 0x08);
+ if (major_revision == 0x03) {
+ dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp);
+ } else if (major_revision <= 0x02) {
+ dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp);
+ } else {
+ dev_err(dwc->dev, "port revision seems wrong\n");
+ ret = -EINVAL;
+ goto unmap_reg;
+ }
+
+ offset = dwc3_xhci_find_next_ext_cap(regs, offset,
+ XHCI_EXT_CAPS_PROTOCOL);
+ }
+
+ temp = readl(regs + DWC3_XHCI_HCSPARAMS1);
+ if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) {
+ dev_err(dwc->dev, "inconsistency in port info\n");
+ ret = -EINVAL;
+ goto unmap_reg;
+ }
+
+ dev_dbg(dwc->dev,
+ "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports);
+
+unmap_reg:
+ iounmap(regs);
+ return ret;
+}
+
static int dwc3_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1774,6 +1827,7 @@ static int dwc3_probe(struct platform_device *pdev)
void __iomem *regs;
struct dwc3 *dwc;
int ret;
+ unsigned int hw_mode;

dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
if (!dwc)
@@ -1843,6 +1897,20 @@ static int dwc3_probe(struct platform_device *pdev)
goto err_disable_clks;
}

+ /*
+ * Currently DWC3 controllers that are host-only capable
+ * support Multiport
+ */
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+ ret = dwc3_read_port_info(dwc);
+ if (ret)
+ goto err_disable_clks;
+ } else {
+ dwc->num_usb2_ports = 1;
+ dwc->num_usb3_ports = 1;
+ }
+
spin_lock_init(&dwc->lock);
mutex_init(&dwc->mutex);

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index d56457c02996..21312703e053 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -35,6 +35,17 @@

#define DWC3_MSG_MAX 500

+/* Define XHCI Extcap register offsets for getting multiport info */
+#define XHCI_HCC_PARAMS_OFFSET 0x10
+#define DWC3_XHCI_HCSPARAMS1 0x04
+#define XHCI_EXT_CAPS_PROTOCOL 2
+#define XHCI_HCC_EXT_CAPS(x) (((x) >> 16) & 0xffff)
+#define XHCI_EXT_CAPS_ID(x) (((x) >> 0) & 0xff)
+#define XHCI_EXT_CAPS_NEXT(x) (((x) >> 8) & 0xff)
+#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
+#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
+#define HCS_MAX_PORTS(x) (((x) >> 24) & 0x7f)
+
/* Global constants */
#define DWC3_PULL_UP_TIMEOUT 500 /* ms */
#define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
@@ -1025,6 +1036,8 @@ struct dwc3_scratchpad_array {
* @usb_psy: pointer to power supply interface.
* @usb2_phy: pointer to USB2 PHY
* @usb3_phy: pointer to USB3 PHY
+ * @num_usb2_ports: number of usb2 ports.
+ * @num_usb3_ports: number of usb3 ports.
* @usb2_generic_phy: pointer to USB2 PHY
* @usb3_generic_phy: pointer to USB3 PHY
* @phys_ready: flag to indicate that PHYs are ready
@@ -1162,6 +1175,9 @@ struct dwc3 {
struct usb_phy *usb2_phy;
struct usb_phy *usb3_phy;

+ u32 num_usb2_ports;
+ u32 num_usb3_ports;
+
struct phy *usb2_generic_phy;
struct phy *usb3_generic_phy;

@@ -1650,4 +1666,46 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
{ }
#endif

+/**
+ * dwc3_xhci_find_next_ext_cap - Find the offset of the extended capabilities
+ * with capability ID id.
+ *
+ * @base PCI MMIO registers base address.
+ * @start address at which to start looking, (0 or HCC_PARAMS to start at
+ * beginning of list)
+ * @id Extended capability ID to search for, or 0 for the next
+ * capability
+ *
+ * Returns the offset of the next matching extended capability structure.
+ * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
+ * and this provides a way to find them all.
+ */
+static inline int dwc3_xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
+{
+ u32 val;
+ u32 next;
+ u32 offset;
+
+ offset = start;
+ if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
+ val = readl(base + XHCI_HCC_PARAMS_OFFSET);
+ if (val == ~0)
+ return 0;
+ offset = XHCI_HCC_EXT_CAPS(val) << 2;
+ if (!offset)
+ return 0;
+ }
+ do {
+ val = readl(base + offset);
+ if (val == ~0)
+ return 0;
+ if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
+ return offset;
+
+ next = XHCI_EXT_CAPS_NEXT(val);
+ offset += next << 2;
+ } while (next);
+
+ return 0;
+}
#endif /* __DRIVERS_USB_DWC3_CORE_H */
--
2.40.0

2023-05-01 14:38:13

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 7/9] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280

Add USB and DWC3 node for tertiary port of SC8280 along with multiport
IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
platforms.

Signed-off-by: Krishna Kurapati <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++
1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 8fa9fbfe5d00..0e4fb286956b 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint {
};
};

+ usb_2: usb@a4f8800 {
+ compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
+ reg = <0 0x0a4f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_SLEEP_CLK>,
+ <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
+ "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 126 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
+ "ss_phy_irq", "pwr_event_1",
+ "pwr_event_2", "pwr_event_3",
+ "pwr_event_4";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ resets = <&gcc GCC_USB30_MP_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ required-opps = <&rpmhpd_opp_nom>;
+
+ status = "disabled";
+
+ usb_2_dwc3: usb@a400000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a400000 0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x800 0x0>;
+ phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
+ <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
+ <&usb_2_hsphy2>,
+ <&usb_2_hsphy3>;
+ phy-names = "usb2-port0", "usb3-port0",
+ "usb2-port1", "usb3-port1",
+ "usb2-port2",
+ "usb2-port3";
+ };
+ };
+
mdss0: display-subsystem@ae00000 {
compatible = "qcom,sc8280xp-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.40.0

2023-05-01 14:38:34

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 6/9] usb: dwc3: qcom: Add multiport controller support for qcom wrapper

QCOM SoC SA8295P's tertiary quad port controller supports 2 HS+SS
ports and 2 HS only ports. Add support for configuring PWR_EVENT_IRQ's
for all the ports during suspend/resume.

Signed-off-by: Krishna Kurapati <[email protected]>
---
drivers/usb/dwc3/dwc3-qcom.c | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 959fc925ca7c..7a9bce66295d 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -37,7 +37,10 @@
#define PIPE3_PHYSTATUS_SW BIT(3)
#define PIPE_UTMI_CLK_DIS BIT(8)

-#define PWR_EVNT_IRQ_STAT_REG 0x58
+#define PWR_EVNT_IRQ1_STAT_REG 0x58
+#define PWR_EVNT_IRQ2_STAT_REG 0x1dc
+#define PWR_EVNT_IRQ3_STAT_REG 0x228
+#define PWR_EVNT_IRQ4_STAT_REG 0x238
#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)

@@ -93,6 +96,13 @@ struct dwc3_qcom {
struct icc_path *icc_path_apps;
};

+static u32 pwr_evnt_irq_stat_reg_offset[4] = {
+ PWR_EVNT_IRQ1_STAT_REG,
+ PWR_EVNT_IRQ2_STAT_REG,
+ PWR_EVNT_IRQ3_STAT_REG,
+ PWR_EVNT_IRQ4_STAT_REG,
+};
+
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
{
u32 reg;
@@ -413,13 +423,16 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
{
u32 val;
int i, ret;
+ struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);

if (qcom->is_suspended)
return 0;

- val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
- if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
- dev_err(qcom->dev, "HS-PHY not in L2\n");
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]);
+ if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
+ dev_err(qcom->dev, "HS-PHY%d not in L2\n", i);
+ }

for (i = qcom->num_clocks - 1; i >= 0; i--)
clk_disable_unprepare(qcom->clks[i]);
@@ -446,6 +459,7 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
{
int ret;
int i;
+ struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);

if (!qcom->is_suspended)
return 0;
@@ -467,8 +481,10 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);

/* Clear existing events from PHY related to L2 in/out */
- dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
- PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
+ for (i = 0; i < dwc->num_usb2_ports; i++)
+ dwc3_qcom_setbits(qcom->qscratch_base,
+ pwr_evnt_irq_stat_reg_offset[i],
+ PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);

qcom->is_suspended = false;

--
2.40.0

2023-05-01 14:39:46

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 9/9] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller

There is now support for the multiport USB controller this uses so
enable it.

The board only has a single port hooked up (despite it being wired up to
the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
which by default on boot is selected to mux properly. Grab the gpio
controlling that and ensure it stays in the right position so USB 2.0
continues to be routed from the external port to the SoC.

Signed-off-by: Andrew Halaney <[email protected]>
Signed-off-by: Krishna Kurapati <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 24fa449d48a6..53d47593306e 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -309,6 +309,19 @@ &usb_2_qmpphy0 {
status = "okay";
};

+&usb_2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_en_state>;
+
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+ phy-names = "usb2-port0", "usb3-port0";
+ phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
+};
+
&xo_board_clk {
clock-frequency = <38400000>;
};
@@ -401,4 +414,13 @@ wake-pins {
bias-pull-up;
};
};
+
+ usb2_en_state: usb2-en-state {
+ /* TS3USB221A USB2.0 mux select */
+ pins = "gpio24";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
};
--
2.40.0

2023-05-01 14:41:23

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: [PATCH v7 8/9] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports

Enable tertiary controller for SA8295P (based on SC8280XP).
Add pinctrl support for usb ports to provide VBUS to connected peripherals.

Signed-off-by: Krishna Kurapati <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 ++++++++++++++++++++++++
1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index fd253942e5e5..7e6061c43835 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -584,6 +584,19 @@ &usb_1_qmpphy {
status = "okay";
};

+&usb_2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_en_state>,
+ <&usb3_en_state>,
+ <&usb4_en_state>,
+ <&usb5_en_state>;
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+};
+
&usb_2_hsphy0 {
vdda-pll-supply = <&vreg_l5a>;
vdda18-supply = <&vreg_l7g>;
@@ -729,3 +742,37 @@ wake-n-pins {
};
};
};
+
+&pmm8540c_gpios {
+ usb2_en_state: usb2-en-state {
+ pins = "gpio9";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8540e_gpios {
+ usb3_en_state: usb3-en-state {
+ pins = "gpio5";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8540g_gpios {
+ usb4_en_state: usb4-en-state {
+ pins = "gpio5";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+
+ usb5_en_state: usb5-en-state {
+ pins = "gpio9";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+};
--
2.40.0

2023-05-02 08:00:49

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH v7 7/9] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280

On 01/05/2023 16:34, Krishna Kurapati wrote:
> Add USB and DWC3 node for tertiary port of SC8280 along with multiport
> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
> platforms.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 8fa9fbfe5d00..0e4fb286956b 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint {
> };
> };
>
> + usb_2: usb@a4f8800 {

Nodes are ordered by unit address, more or less.

> + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
> + reg = <0 0x0a4f8800 0 0x400>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
> + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
> + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
> +
> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;

Does not look aligned.

> +
> + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
> + "ss_phy_irq", "pwr_event_1",

Does not look aligned.

> + "pwr_event_2", "pwr_event_3",
> + "pwr_event_4";
> +
> + power-domains = <&gcc USB30_MP_GDSC>;
> +
> + resets = <&gcc GCC_USB30_MP_BCR>;
> +
> + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
> + interconnect-names = "usb-ddr", "apps-usb";
> +
> + required-opps = <&rpmhpd_opp_nom>;
> +

Please open the DTSI and look how this is organized there. I don't think
doing this differently - with different order - helps to review.
required-opps is next to power-domains.

> + status = "disabled";
> +
> + usb_2_dwc3: usb@a400000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a400000 0 0xcd00>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x800 0x0>;
> + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
> + <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
> + <&usb_2_hsphy2>,
> + <&usb_2_hsphy3>;
> + phy-names = "usb2-port0", "usb3-port0",
> + "usb2-port1", "usb3-port1",
> + "usb2-port2",
> + "usb2-port3";
> + };
> + };
> +
> mdss0: display-subsystem@ae00000 {
> compatible = "qcom,sc8280xp-mdss";
> reg = <0 0x0ae00000 0 0x1000>;

Best regards,
Krzysztof

2023-05-02 08:01:10

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH v7 1/9] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport

On 01/05/2023 16:34, Krishna Kurapati wrote:
> Add the compatible string for SC8280 Multiport USB controller from
> Qualcomm.
>
> There are 4 power event irq interrupts supported by this controller
> (one for each port of multiport). Added all the 4 as non-optional
> interrupts for SC8280XP-MP
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> .../devicetree/bindings/usb/qcom,dwc3.yaml | 21 +++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> index d84281926f10..2c96da1ce5b8 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -26,6 +26,7 @@ properties:
> - qcom,sc7180-dwc3
> - qcom,sc7280-dwc3
> - qcom,sc8280xp-dwc3
> + - qcom,sc8280xp-dwc3-mp

SC8280xp comes with two USB controllers: one single-port and one multi-port?
> - qcom,sdm660-dwc3
> - qcom,sdm670-dwc3
> - qcom,sdm845-dwc3
> @@ -455,6 +456,26 @@ allOf:
> - const: dm_hs_phy_irq
> - const: ss_phy_irq
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8280xp-dwc3-mp

You miss entries for all other constraints.


Best regards,
Krzysztof

2023-05-02 08:38:30

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 1/9] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport



On 5/2/2023 1:18 PM, Krzysztof Kozlowski wrote:
> On 01/05/2023 16:34, Krishna Kurapati wrote:
>> Add the compatible string for SC8280 Multiport USB controller from
>> Qualcomm.
>>
>> There are 4 power event irq interrupts supported by this controller
>> (one for each port of multiport). Added all the 4 as non-optional
>> interrupts for SC8280XP-MP
>>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
>> .../devicetree/bindings/usb/qcom,dwc3.yaml | 21 +++++++++++++++++++
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>> index d84281926f10..2c96da1ce5b8 100644
>> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>> @@ -26,6 +26,7 @@ properties:
>> - qcom,sc7180-dwc3
>> - qcom,sc7280-dwc3
>> - qcom,sc8280xp-dwc3
>> + - qcom,sc8280xp-dwc3-mp
>
> SC8280xp comes with two USB controllers: one single-port and one multi-port?

Hi Krzysztof,

SC8280XP comes with 3 controllers. The first two are single port
controller and the third one is a multiport controller. In DTSI:
usb_0 / usb1: have compatible set to : "qcom,sc8280xp-dwc3"

And multiport controller has it set to "qcom,sc8280xp-dwc3-mp"


>> - qcom,sdm660-dwc3
>> - qcom,sdm670-dwc3
>> - qcom,sdm845-dwc3
>> @@ -455,6 +456,26 @@ allOf:
>> - const: dm_hs_phy_irq
>> - const: ss_phy_irq
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,sc8280xp-dwc3-mp
>
> You miss entries for all other constraints.
>
Let me add the clock properties as well.

Regards,
Krishna,

2023-05-02 08:39:01

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 7/9] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280



On 5/2/2023 1:17 PM, Krzysztof Kozlowski wrote:
> On 01/05/2023 16:34, Krishna Kurapati wrote:
>> Add USB and DWC3 node for tertiary port of SC8280 along with multiport
>> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
>> platforms.
>>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++
>> 1 file changed, 64 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index 8fa9fbfe5d00..0e4fb286956b 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint {
>> };
>> };
>>
>> + usb_2: usb@a4f8800 {
>
> Nodes are ordered by unit address, more or less >
>> + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
>> + reg = <0 0x0a4f8800 0 0x400>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
>> + <&gcc GCC_USB30_MP_MASTER_CLK>,
>> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
>> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
>> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
>> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
>> + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
>> + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
>> +
>> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
>> + <&gcc GCC_USB30_MP_MASTER_CLK>;
>> + assigned-clock-rates = <19200000>, <200000000>;
>> +
>> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
>> + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
>> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
>
> Does not look aligned. >
>> +
>> + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
>> + "ss_phy_irq", "pwr_event_1",
>
> Does not look aligned.
>
Sure, will fix up the indentation issues.
>> + "pwr_event_2", "pwr_event_3",
>> + "pwr_event_4";
>> +
>> + power-domains = <&gcc USB30_MP_GDSC>;
>> +
>> + resets = <&gcc GCC_USB30_MP_BCR>;
>> +
>> + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
>> + interconnect-names = "usb-ddr", "apps-usb";
>> +
>> + required-opps = <&rpmhpd_opp_nom>;
>> +
>
> Please open the DTSI and look how this is organized there. I don't think
> doing this differently - with different order - helps to review.
> required-opps is next to power-domains.
Sure. Will fix it up.
>
>> + status = "disabled";
>> +
>> + usb_2_dwc3: usb@a400000 {
>> + compatible = "snps,dwc3";
>> + reg = <0 0x0a400000 0 0xcd00>;
>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + iommus = <&apps_smmu 0x800 0x0>;
>> + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
>> + <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
>> + <&usb_2_hsphy2>,
>> + <&usb_2_hsphy3>;
>> + phy-names = "usb2-port0", "usb3-port0",
>> + "usb2-port1", "usb3-port1",
>> + "usb2-port2",
>> + "usb2-port3";
>> + };
>> + };
>> +
>> mdss0: display-subsystem@ae00000 {
>> compatible = "qcom,sc8280xp-mdss";
>> reg = <0 0x0ae00000 0 0x1000>;
>

Thanks,
Krishna,

2023-05-02 08:51:00

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH v7 1/9] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport

On 02/05/2023 10:35, Krishna Kurapati PSSNV wrote:
>
>
> On 5/2/2023 1:18 PM, Krzysztof Kozlowski wrote:
>> On 01/05/2023 16:34, Krishna Kurapati wrote:
>>> Add the compatible string for SC8280 Multiport USB controller from
>>> Qualcomm.
>>>
>>> There are 4 power event irq interrupts supported by this controller
>>> (one for each port of multiport). Added all the 4 as non-optional
>>> interrupts for SC8280XP-MP
>>>
>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>> ---
>>> .../devicetree/bindings/usb/qcom,dwc3.yaml | 21 +++++++++++++++++++
>>> 1 file changed, 21 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>>> index d84281926f10..2c96da1ce5b8 100644
>>> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>>> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>>> @@ -26,6 +26,7 @@ properties:
>>> - qcom,sc7180-dwc3
>>> - qcom,sc7280-dwc3
>>> - qcom,sc8280xp-dwc3
>>> + - qcom,sc8280xp-dwc3-mp
>>
>> SC8280xp comes with two USB controllers: one single-port and one multi-port?
>
> Hi Krzysztof,
>
> SC8280XP comes with 3 controllers. The first two are single port
> controller and the third one is a multiport controller. In DTSI:
> usb_0 / usb1: have compatible set to : "qcom,sc8280xp-dwc3"
>
> And multiport controller has it set to "qcom,sc8280xp-dwc3-mp"

OK, then this looks fine.

Please add the compatible to existing allOf:if:then to constrain clocks
and other pieces. If none of existing if:then: matches your case, add
new one.

Best regards,
Krzysztof

2023-05-02 09:12:34

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 1/9] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport



On 5/2/2023 2:17 PM, Krzysztof Kozlowski wrote:
> On 02/05/2023 10:35, Krishna Kurapati PSSNV wrote:
>>
>>
>> On 5/2/2023 1:18 PM, Krzysztof Kozlowski wrote:
>>> On 01/05/2023 16:34, Krishna Kurapati wrote:
>>>> Add the compatible string for SC8280 Multiport USB controller from
>>>> Qualcomm.
>>>>
>>>> There are 4 power event irq interrupts supported by this controller
>>>> (one for each port of multiport). Added all the 4 as non-optional
>>>> interrupts for SC8280XP-MP
>>>>
>>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>>> ---
>>>> .../devicetree/bindings/usb/qcom,dwc3.yaml | 21 +++++++++++++++++++
>>>> 1 file changed, 21 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>>>> index d84281926f10..2c96da1ce5b8 100644
>>>> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>>>> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>>>> @@ -26,6 +26,7 @@ properties:
>>>> - qcom,sc7180-dwc3
>>>> - qcom,sc7280-dwc3
>>>> - qcom,sc8280xp-dwc3
>>>> + - qcom,sc8280xp-dwc3-mp
>>>
>>> SC8280xp comes with two USB controllers: one single-port and one multi-port?
>>
>> Hi Krzysztof,
>>
>> SC8280XP comes with 3 controllers. The first two are single port
>> controller and the third one is a multiport controller. In DTSI:
>> usb_0 / usb1: have compatible set to : "qcom,sc8280xp-dwc3"
>>
>> And multiport controller has it set to "qcom,sc8280xp-dwc3-mp"
>
> OK, then this looks fine.
>
> Please add the compatible to existing allOf:if:then to constrain clocks
> and other pieces. If none of existing if:then: matches your case, add
> new one.
>
> Best regards,
> Krzysztof
>

Thanks Krzysztof. One query:

Clocks are same for both single/multiport controllers. Would the
following be fine ?

diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index 2c96da1ce5b8..c0f4745febf0 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -263,6 +263,7 @@ allOf:
contains:
enum:
- qcom,sc8280xp-dwc3
+ - qcom,sc8280xp-dwc3-mp
then:
properties:
clocks:

Regards,
Krishna,

2023-05-02 10:19:05

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH v7 1/9] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport

On 02/05/2023 10:52, Krishna Kurapati PSSNV wrote:
>> Best regards,
>> Krzysztof
>>
>
> Thanks Krzysztof. One query:
>
> Clocks are same for both single/multiport controllers. Would the
> following be fine ?
>

Yes, thanks.

Best regards,
Krzysztof

2023-05-02 11:15:29

by Konrad Dybcio

[permalink] [raw]
Subject: Re: [PATCH v7 8/9] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports



On 1.05.2023 16:34, Krishna Kurapati wrote:
> Enable tertiary controller for SA8295P (based on SC8280XP).
> Add pinctrl support for usb ports to provide VBUS to connected peripherals.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 ++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> index fd253942e5e5..7e6061c43835 100644
> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> @@ -584,6 +584,19 @@ &usb_1_qmpphy {
> status = "okay";
> };
>
> +&usb_2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb2_en_state>,
> + <&usb3_en_state>,
> + <&usb4_en_state>,
> + <&usb5_en_state>;
This is misaligned. Also, please do property-n before property-names.

> + status = "okay";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "host";
> +};
> +
> &usb_2_hsphy0 {
> vdda-pll-supply = <&vreg_l5a>;
> vdda18-supply = <&vreg_l7g>;
> @@ -729,3 +742,37 @@ wake-n-pins {
> };
> };
> };
> +
> +&pmm8540c_gpios {
> + usb2_en_state: usb2-en-state {
> + pins = "gpio9";
> + function = "normal";
> + output-high;
> + power-source = <0>;
No drive-strength values?

Konrad
> + };
> +};
> +
> +&pmm8540e_gpios {
> + usb3_en_state: usb3-en-state {
> + pins = "gpio5";
> + function = "normal";
> + output-high;
> + power-source = <0>;
> + };
> +};
> +
> +&pmm8540g_gpios {
> + usb4_en_state: usb4-en-state {
> + pins = "gpio5";
> + function = "normal";
> + output-high;
> + power-source = <0>;
> + };
> +
> + usb5_en_state: usb5-en-state {
> + pins = "gpio9";
> + function = "normal";
> + output-high;
> + power-source = <0>;
> + };
> +};

2023-05-02 11:15:47

by Konrad Dybcio

[permalink] [raw]
Subject: Re: [PATCH v7 9/9] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller



On 1.05.2023 16:34, Krishna Kurapati wrote:
> There is now support for the multiport USB controller this uses so
> enable it.
>
> The board only has a single port hooked up (despite it being wired up to
> the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
> which by default on boot is selected to mux properly. Grab the gpio
> controlling that and ensure it stays in the right position so USB 2.0
> continues to be routed from the external port to the SoC.
>
> Signed-off-by: Andrew Halaney <[email protected]>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
same comments as patch 8

Konrad
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> index 24fa449d48a6..53d47593306e 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -309,6 +309,19 @@ &usb_2_qmpphy0 {
> status = "okay";
> };
>
> +&usb_2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb2_en_state>;
> +
> + status = "okay";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "host";
> + phy-names = "usb2-port0", "usb3-port0";
> + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
> +};
> +
> &xo_board_clk {
> clock-frequency = <38400000>;
> };
> @@ -401,4 +414,13 @@ wake-pins {
> bias-pull-up;
> };
> };
> +
> + usb2_en_state: usb2-en-state {
> + /* TS3USB221A USB2.0 mux select */
> + pins = "gpio24";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> };

2023-05-02 12:45:04

by kernel test robot

[permalink] [raw]
Subject: Re: [PATCH v7 3/9] usb: dwc3: core: Access XHCI address space temporarily to read port info

Hi Krishna,

kernel test robot noticed the following build warnings:

[auto build test WARNING on usb/usb-testing]
[also build test WARNING on usb/usb-next usb/usb-linus linus/master next-20230428]
[cannot apply to robh/for-next v6.3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Krishna-Kurapati/dt-bindings-usb-qcom-dwc3-Add-bindings-for-SC8280-Multiport/20230501-224209
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-testing
patch link: https://lore.kernel.org/r/20230501143445.3851-4-quic_kriskura%40quicinc.com
patch subject: [PATCH v7 3/9] usb: dwc3: core: Access XHCI address space temporarily to read port info
reproduce:
# https://github.com/intel-lab-lkp/linux/commit/840e9a485800cf72e5fbf4dca1aaf92085aad584
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Krishna-Kurapati/dt-bindings-usb-qcom-dwc3-Add-bindings-for-SC8280-Multiport/20230501-224209
git checkout 840e9a485800cf72e5fbf4dca1aaf92085aad584
make menuconfig
# enable CONFIG_COMPILE_TEST, CONFIG_WARN_MISSING_DOCUMENTS, CONFIG_WARN_ABI_ERRORS
make htmldocs

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

>> Documentation/driver-api/usb/dwc3:687: ./drivers/usb/dwc3/core.h:1674: WARNING: Unexpected indentation.
>> Documentation/driver-api/usb/dwc3:687: ./drivers/usb/dwc3/core.h:1675: WARNING: Block quote ends without a blank line; unexpected unindent.

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests

2023-05-02 21:45:47

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v7 3/9] usb: dwc3: core: Access XHCI address space temporarily to read port info

Hi,

On Mon, May 01, 2023, Krishna Kurapati wrote:
> Currently host-only capable DWC3 controllers support Multiport.
> Temporarily map XHCI address space for host-only controllers and parse
> XHCI Extended Capabilities registers to read number of usb2 ports and
> usb3 ports present on multiport controller. Each USB Port is at least HS
> capable.
>
> The port info for usb2 and usb3 phy are identified as num_usb2_ports
> and num_usb3_ports. The intention is as follows:
>
> Wherever we need to perform phy operations like:
>
> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> {
> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> }
>
> If number of usb2 ports is 3, loop can go from index 0-2 for
> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> if the first 2 ports are SS capable or some other ports like (2 and 3)
> are SS capable. So instead, num_usb2_ports is used to loop around all
> phy's (both hs and ss) for performing phy operations. If any
> usb3_generic_phy turns out to be NULL, phy operation just bails out.
>
> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> phy's as we need to know how many SS capable ports are there for this.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 68 +++++++++++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 58 +++++++++++++++++++++++++++++++++++
> 2 files changed, 126 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 0beaab932e7d..b8ac7bcee391 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -1767,6 +1767,59 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> return 0;
> }
>
> +static int dwc3_read_port_info(struct dwc3 *dwc)
> +{
> + void __iomem *regs;
> + u32 offset;
> + u32 temp;
> + u8 major_revision;
> + int ret = 0;
> +
> + /*
> + * Remap xHCI address space to access XHCI ext cap regs,
> + * since it is needed to get port info.
> + */
> + regs = ioremap(dwc->xhci_resources[0].start,
> + resource_size(&dwc->xhci_resources[0]));
> + if (IS_ERR(regs))
> + return PTR_ERR(regs);
> +
> + offset = dwc3_xhci_find_next_ext_cap(regs, 0,
> + XHCI_EXT_CAPS_PROTOCOL);
> + while (offset) {
> + temp = readl(regs + offset);
> + major_revision = XHCI_EXT_PORT_MAJOR(temp);
> +
> + temp = readl(regs + offset + 0x08);
> + if (major_revision == 0x03) {
> + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp);
> + } else if (major_revision <= 0x02) {
> + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp);
> + } else {
> + dev_err(dwc->dev, "port revision seems wrong\n");

Can we print this instead:
dev_err(dwc->dev, "Unrecognized port major revision %d\n", major_revision);

> + ret = -EINVAL;
> + goto unmap_reg;
> + }
> +
> + offset = dwc3_xhci_find_next_ext_cap(regs, offset,
> + XHCI_EXT_CAPS_PROTOCOL);
> + }
> +
> + temp = readl(regs + DWC3_XHCI_HCSPARAMS1);
> + if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) {
> + dev_err(dwc->dev, "inconsistency in port info\n");

Can we print this instead:
dev_err(dwc->dev, "Mismatched reported MAXPORTS (%d)\n", HCS_MAX_PORTS(temp));

> + ret = -EINVAL;
> + goto unmap_reg;
> + }
> +
> + dev_dbg(dwc->dev,
> + "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports);
> +
> +unmap_reg:
> + iounmap(regs);
> + return ret;
> +}
> +
> static int dwc3_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -1774,6 +1827,7 @@ static int dwc3_probe(struct platform_device *pdev)
> void __iomem *regs;
> struct dwc3 *dwc;
> int ret;
> + unsigned int hw_mode;
>
> dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
> if (!dwc)
> @@ -1843,6 +1897,20 @@ static int dwc3_probe(struct platform_device *pdev)
> goto err_disable_clks;
> }
>
> + /*
> + * Currently DWC3 controllers that are host-only capable
> + * support Multiport
> + */
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
> + ret = dwc3_read_port_info(dwc);
> + if (ret)
> + goto err_disable_clks;
> + } else {
> + dwc->num_usb2_ports = 1;
> + dwc->num_usb3_ports = 1;
> + }
> +
> spin_lock_init(&dwc->lock);
> mutex_init(&dwc->mutex);
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index d56457c02996..21312703e053 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -35,6 +35,17 @@
>
> #define DWC3_MSG_MAX 500
>
> +/* Define XHCI Extcap register offsets for getting multiport info */
> +#define XHCI_HCC_PARAMS_OFFSET 0x10
> +#define DWC3_XHCI_HCSPARAMS1 0x04
> +#define XHCI_EXT_CAPS_PROTOCOL 2
> +#define XHCI_HCC_EXT_CAPS(x) (((x) >> 16) & 0xffff)
> +#define XHCI_EXT_CAPS_ID(x) (((x) >> 0) & 0xff)
> +#define XHCI_EXT_CAPS_NEXT(x) (((x) >> 8) & 0xff)
> +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
> +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
> +#define HCS_MAX_PORTS(x) (((x) >> 24) & 0x7f)
> +
> /* Global constants */
> #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
> #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
> @@ -1025,6 +1036,8 @@ struct dwc3_scratchpad_array {
> * @usb_psy: pointer to power supply interface.
> * @usb2_phy: pointer to USB2 PHY
> * @usb3_phy: pointer to USB3 PHY
> + * @num_usb2_ports: number of usb2 ports.
> + * @num_usb3_ports: number of usb3 ports.
> * @usb2_generic_phy: pointer to USB2 PHY
> * @usb3_generic_phy: pointer to USB3 PHY
> * @phys_ready: flag to indicate that PHYs are ready
> @@ -1162,6 +1175,9 @@ struct dwc3 {
> struct usb_phy *usb2_phy;
> struct usb_phy *usb3_phy;
>
> + u32 num_usb2_ports;
> + u32 num_usb3_ports;

can we use u8?

> +
> struct phy *usb2_generic_phy;
> struct phy *usb3_generic_phy;
>
> @@ -1650,4 +1666,46 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
> { }
> #endif
>
> +/**
> + * dwc3_xhci_find_next_ext_cap - Find the offset of the extended capabilities
> + * with capability ID id.
> + *
> + * @base PCI MMIO registers base address.
> + * @start address at which to start looking, (0 or HCC_PARAMS to start at
> + * beginning of list)
> + * @id Extended capability ID to search for, or 0 for the next
> + * capability

I know that this is a duplicate from the xhci driver, but can we fix the
kerneldoc style as in other places if we're going to keep it?

> + *
> + * Returns the offset of the next matching extended capability structure.
> + * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
> + * and this provides a way to find them all.
> + */
> +static inline int dwc3_xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)

This is a bit much for an inline function, can we just keep it in core.c
as a static function?

> +{
> + u32 val;
> + u32 next;
> + u32 offset;
> +
> + offset = start;
> + if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
> + val = readl(base + XHCI_HCC_PARAMS_OFFSET);
> + if (val == ~0)
> + return 0;
> + offset = XHCI_HCC_EXT_CAPS(val) << 2;
> + if (!offset)
> + return 0;
> + }
> + do {
> + val = readl(base + offset);
> + if (val == ~0)
> + return 0;
> + if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
> + return offset;
> +
> + next = XHCI_EXT_CAPS_NEXT(val);
> + offset += next << 2;
> + } while (next);
> +
> + return 0;
> +}
> #endif /* __DRIVERS_USB_DWC3_CORE_H */
> --
> 2.40.0

Thanks!
Thinh

2023-05-02 21:46:09

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v7 4/9] usb: dwc3: core: Skip setting event buffers for host only controllers

On Mon, May 01, 2023, Krishna Kurapati wrote:
> On some SoC's like SA8295P where the tertiary controller is host-only
> capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible.
> Trying to setup them up during core_init leads to a crash.
>
> For DRD/Peripheral supported controllers, event buffer setup is done
> again in gadget_pullup. Skip setup or cleanup of event buffers if
> controller is host-only capable.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 22 ++++++++++++++++------
> 1 file changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index b8ac7bcee391..8625fc5c7ab4 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -835,7 +835,12 @@ static void dwc3_clk_disable(struct dwc3 *dwc)
>
> static void dwc3_core_exit(struct dwc3 *dwc)
> {
> - dwc3_event_buffers_cleanup(dwc);
> + unsigned int hw_mode;
> +
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST)
> + dwc3_event_buffers_cleanup(dwc);

I think it's cleaner to do these checks in dwc3_event_buffers_cleanup
and dwc3_event_buffers_setup.

Thanks,
Thinh

> +
> dwc3_phy_power_off(dwc);
> dwc3_phy_exit(dwc);
> dwc3_clk_disable(dwc);
> @@ -1141,10 +1146,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
> if (ret)
> goto err_exit_phy;
>
> - ret = dwc3_event_buffers_setup(dwc);
> - if (ret) {
> - dev_err(dwc->dev, "failed to setup event buffers\n");
> - goto err_power_off_phy;
> + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) {
> + ret = dwc3_event_buffers_setup(dwc);
> + if (ret) {
> + dev_err(dwc->dev, "failed to setup event buffers\n");
> + goto err_power_off_phy;
> + }
> }
>
> /*
> @@ -1958,7 +1965,10 @@ static int dwc3_probe(struct platform_device *pdev)
>
> err_exit_debugfs:
> dwc3_debugfs_exit(dwc);
> - dwc3_event_buffers_cleanup(dwc);
> +
> + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST)
> + dwc3_event_buffers_cleanup(dwc);
> +
> dwc3_phy_power_off(dwc);
> dwc3_phy_exit(dwc);
> dwc3_ulpi_exit(dwc);
> --
> 2.40.0
>

2023-05-02 22:16:05

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

On Mon, May 01, 2023, Krishna Kurapati wrote:
> Currently the DWC3 driver supports only single port controller
> which requires at most one HS and one SS PHY.
>
> But the DWC3 USB controller can be connected to multiple ports and
> each port can have their own PHYs. Each port of the multiport
> controller can either be HS+SS capable or HS only capable
> Proper quantification of them is required to modify GUSB2PHYCFG
> and GUSB3PIPECTL registers appropriately.
>
> Add support for detecting, obtaining and configuring phy's supported
> by a multiport controller and limit the max number of ports
> supported to 4.
>
> Signed-off-by: Harsh Agarwal <[email protected]>
> Signed-off-by: Krishna Kurapati <[email protected]>

Are you a co-author or only Harsh is the main author of this patch?

> ---
> drivers/usb/dwc3/core.c | 262 +++++++++++++++++++++++++++++-----------
> drivers/usb/dwc3/core.h | 12 +-
> drivers/usb/dwc3/drd.c | 13 +-
> 3 files changed, 209 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 8625fc5c7ab4..b91c3f965abc 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -121,6 +121,7 @@ static void __dwc3_set_mode(struct work_struct *work)
> struct dwc3 *dwc = work_to_dwc(work);
> unsigned long flags;
> int ret;
> + int i;
> u32 reg;
> u32 desired_dr_role;
>
> @@ -200,8 +201,10 @@ static void __dwc3_set_mode(struct work_struct *work)
> } else {
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> + }
> if (dwc->dis_split_quirk) {
> reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
> reg |= DWC3_GUCTL3_SPLITDISABLE;
> @@ -216,8 +219,8 @@ static void __dwc3_set_mode(struct work_struct *work)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>
> ret = dwc3_gadget_init(dwc);
> if (ret)
> @@ -575,22 +578,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
> return ret;
> }
>
> -/**
> - * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
> - * @dwc: Pointer to our controller context structure
> - *
> - * Returns 0 on success. The USB PHY interfaces are configured but not
> - * initialized. The PHY interfaces and the PHYs get initialized together with
> - * the core in dwc3_core_init.
> - */
> -static int dwc3_phy_setup(struct dwc3 *dwc)
> +static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
> {
> unsigned int hw_mode;
> u32 reg;
>
> hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
>
> /*
> * Make sure UX_EXIT_PX is cleared as that causes issues with some
> @@ -645,9 +640,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> if (dwc->dis_del_phy_power_chg_quirk)
> reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
>
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> + return 0;
> +}
> +
> +static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
> +{
> + unsigned int hw_mode;
> + u32 reg;
> +
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> +
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
>
> /* Select the HS PHY interface */
> switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
> @@ -659,7 +664,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> } else if (dwc->hsphy_interface &&
> !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
> reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
> } else {
> /* Relying on default value. */
> if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
> @@ -726,7 +731,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> if (dwc->ulpi_ext_vbus_drv)
> reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
> +
> + return 0;
> +}
> +
> +/**
> + * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
> + * @dwc: Pointer to our controller context structure
> + *
> + * Returns 0 on success. The USB PHY interfaces are configured but not
> + * initialized. The PHY interfaces and the PHYs get initialized together with
> + * the core in dwc3_core_init.
> + */
> +static int dwc3_phy_setup(struct dwc3 *dwc)
> +{
> + int i;
> + int ret;
> +
> + for (i = 0; i < dwc->num_usb3_ports; i++) {
> + ret = dwc3_ss_phy_setup(dwc, i);
> + if (ret)
> + return ret;
> + }
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = dwc3_hs_phy_setup(dwc, i);
> + if (ret)
> + return ret;
> + }
>
> return 0;
> }
> @@ -734,22 +767,36 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
> static int dwc3_phy_init(struct dwc3 *dwc)
> {
> int ret;
> + int i, j;

Minor style nit, can we declare in separate lines?

>
> usb_phy_init(dwc->usb2_phy);
> usb_phy_init(dwc->usb3_phy);
>
> - ret = phy_init(dwc->usb2_generic_phy);
> - if (ret < 0)
> - goto err_shutdown_usb3_phy;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = phy_init(dwc->usb2_generic_phy[i]);
> + if (ret < 0) {
> + /* clean up prior initialized HS PHYs */
> + for (j = 0; j < i; j++)
> + phy_exit(dwc->usb2_generic_phy[j]);
> + goto err_shutdown_usb3_phy;
> + }
> + }
>
> - ret = phy_init(dwc->usb3_generic_phy);
> - if (ret < 0)
> - goto err_exit_usb2_phy;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = phy_init(dwc->usb3_generic_phy[i]);
> + if (ret < 0) {
> + /* clean up prior initialized SS PHYs */
> + for (j = 0; j < i; j++)
> + phy_exit(dwc->usb3_generic_phy[j]);
> + goto err_exit_usb2_phy;
> + }
> + }
>
> return 0;
>
> err_exit_usb2_phy:
> - phy_exit(dwc->usb2_generic_phy);
> + for (i = 0; i < dwc->num_usb2_ports; i++)
> + phy_exit(dwc->usb2_generic_phy[i]);
> err_shutdown_usb3_phy:
> usb_phy_shutdown(dwc->usb3_phy);
> usb_phy_shutdown(dwc->usb2_phy);
> @@ -759,8 +806,12 @@ static int dwc3_phy_init(struct dwc3 *dwc)
>
> static void dwc3_phy_exit(struct dwc3 *dwc)
> {
> - phy_exit(dwc->usb3_generic_phy);
> - phy_exit(dwc->usb2_generic_phy);
> + int i;
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_exit(dwc->usb3_generic_phy[i]);
> + phy_exit(dwc->usb2_generic_phy[i]);
> + }
>
> usb_phy_shutdown(dwc->usb3_phy);
> usb_phy_shutdown(dwc->usb2_phy);
> @@ -769,22 +820,36 @@ static void dwc3_phy_exit(struct dwc3 *dwc)
> static int dwc3_phy_power_on(struct dwc3 *dwc)
> {
> int ret;
> + int i, j;
>
> usb_phy_set_suspend(dwc->usb2_phy, 0);
> usb_phy_set_suspend(dwc->usb3_phy, 0);
>
> - ret = phy_power_on(dwc->usb2_generic_phy);
> - if (ret < 0)
> - goto err_suspend_usb3_phy;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = phy_power_on(dwc->usb2_generic_phy[i]);
> + if (ret < 0) {
> + /* Turn off prior ON'ed HS Phy's */
> + for (j = 0; j < i; j++)
> + phy_power_off(dwc->usb2_generic_phy[j]);
> + goto err_suspend_usb3_phy;
> + }
> + }
>
> - ret = phy_power_on(dwc->usb3_generic_phy);
> - if (ret < 0)
> - goto err_power_off_usb2_phy;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + ret = phy_power_on(dwc->usb3_generic_phy[i]);
> + if (ret < 0) {
> + /* Turn of prior ON'ed SS Phy's */
> + for (j = 0; j < i; j++)
> + phy_power_off(dwc->usb3_generic_phy[j]);
> + goto err_power_off_usb2_phy;
> + }
> + }
>
> return 0;
>
> err_power_off_usb2_phy:
> - phy_power_off(dwc->usb2_generic_phy);
> + for (i = 0; i < dwc->num_usb2_ports; i++)
> + phy_power_off(dwc->usb2_generic_phy[i]);
> err_suspend_usb3_phy:
> usb_phy_set_suspend(dwc->usb3_phy, 1);
> usb_phy_set_suspend(dwc->usb2_phy, 1);
> @@ -794,8 +859,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc)
>
> static void dwc3_phy_power_off(struct dwc3 *dwc)
> {
> - phy_power_off(dwc->usb3_generic_phy);
> - phy_power_off(dwc->usb2_generic_phy);
> + int i;
> +
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_power_off(dwc->usb3_generic_phy[i]);
> + phy_power_off(dwc->usb2_generic_phy[i]);
> + }
>
> usb_phy_set_suspend(dwc->usb3_phy, 1);
> usb_phy_set_suspend(dwc->usb2_phy, 1);
> @@ -1073,6 +1142,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
> unsigned int hw_mode;
> u32 reg;
> int ret;
> + int i;
>
> hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>
> @@ -1116,15 +1186,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
> if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
> !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
> if (!dwc->dis_u3_susphy_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> - reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
> + for (i = 0; i < dwc->num_usb3_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
> + reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
> + }
> }
>
> if (!dwc->dis_u2_susphy_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - reg |= DWC3_GUSB2PHYCFG_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + reg |= DWC3_GUSB2PHYCFG_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
> }
> }
>
> @@ -1281,6 +1355,42 @@ static int dwc3_core_init(struct dwc3 *dwc)
> return ret;
> }
>
> +static int dwc3_get_multiport_phys(struct dwc3 *dwc)
> +{
> + int ret;
> + struct device *dev = dwc->dev;
> + int i;
> + char phy_name[11];

Minor minor nit. Can we reorder this as follow:
struct device *dev = dwc->dev;
char phy_name[11];
int ret;
int i;


> +
> + /*
> + * Each port is at least HS capable. So loop over num_usb2_ports
> + * to get available phy's.
> + */
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + sprintf(phy_name, "usb2-port%d", i);
> + dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
> + if (IS_ERR(dwc->usb2_generic_phy[i])) {
> + ret = PTR_ERR(dwc->usb2_generic_phy[i]);
> + if (ret == -ENOSYS || ret == -ENODEV)
> + dwc->usb2_generic_phy[i] = NULL;
> + else
> + return dev_err_probe(dev, ret, "usb2 phy: %s not configured\n", phy_name);
> + }
> +
> + sprintf(phy_name, "usb3-port%d", i);
> + dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
> + if (IS_ERR(dwc->usb3_generic_phy[i])) {
> + ret = PTR_ERR(dwc->usb3_generic_phy[i]);
> + if (ret == -ENOSYS || ret == -ENODEV)
> + dwc->usb3_generic_phy[i] = NULL;
> + else
> + return dev_err_probe(dev, ret, "usb3 phy: %s not configured\n", phy_name);
> + }
> + }
> +
> + return 0;
> +}
> +
> static int dwc3_core_get_phy(struct dwc3 *dwc)
> {
> struct device *dev = dwc->dev;
> @@ -1311,20 +1421,23 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
> return dev_err_probe(dev, ret, "no usb3 phy configured\n");
> }
>
> - dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
> - if (IS_ERR(dwc->usb2_generic_phy)) {
> - ret = PTR_ERR(dwc->usb2_generic_phy);
> + if (dwc->num_usb2_ports > 1)
> + return dwc3_get_multiport_phys(dwc);
> +
> + dwc->usb2_generic_phy[0] = devm_phy_get(dev, "usb2-phy");
> + if (IS_ERR(dwc->usb2_generic_phy[0])) {
> + ret = PTR_ERR(dwc->usb2_generic_phy[0]);
> if (ret == -ENOSYS || ret == -ENODEV)
> - dwc->usb2_generic_phy = NULL;
> + dwc->usb2_generic_phy[0] = NULL;
> else
> return dev_err_probe(dev, ret, "no usb2 phy configured\n");
> }
>
> - dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
> - if (IS_ERR(dwc->usb3_generic_phy)) {
> - ret = PTR_ERR(dwc->usb3_generic_phy);
> + dwc->usb3_generic_phy[0] = devm_phy_get(dev, "usb3-phy");
> + if (IS_ERR(dwc->usb3_generic_phy[0])) {
> + ret = PTR_ERR(dwc->usb3_generic_phy[0]);
> if (ret == -ENOSYS || ret == -ENODEV)
> - dwc->usb3_generic_phy = NULL;
> + dwc->usb3_generic_phy[0] = NULL;
> else
> return dev_err_probe(dev, ret, "no usb3 phy configured\n");
> }
> @@ -1336,6 +1449,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
> {
> struct device *dev = dwc->dev;
> int ret;
> + int i;
>
> switch (dwc->dr_mode) {
> case USB_DR_MODE_PERIPHERAL:
> @@ -1343,8 +1457,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>
> ret = dwc3_gadget_init(dwc);
> if (ret)
> @@ -1355,8 +1469,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> + }
>
> ret = dwc3_host_init(dwc);
> if (ret)
> @@ -2046,6 +2162,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc)
>
> static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
> {
> + int i;
> unsigned long flags;
> u32 reg;
>
> @@ -2066,17 +2183,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
> /* Let controller to suspend HSPHY before PHY driver suspends */
> if (dwc->dis_u2_susphy_quirk ||
> dwc->dis_enblslpm_quirk) {
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
> - DWC3_GUSB2PHYCFG_SUSPHY;
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
> + DWC3_GUSB2PHYCFG_SUSPHY;
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
>
> /* Give some time for USB2 PHY to suspend */
> usleep_range(5000, 6000);
> }
>
> - phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
> - phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
> + phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
> + }
> break;
> case DWC3_GCTL_PRTCAP_OTG:
> /* do nothing during runtime_suspend */
> @@ -2105,6 +2226,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
> {
> unsigned long flags;
> int ret;
> + int i;
> u32 reg;
>
> switch (dwc->current_dr_role) {
> @@ -2125,17 +2247,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
> break;
> }
> /* Restore GUSB2PHYCFG bits that were modified in suspend */
> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
> - if (dwc->dis_u2_susphy_quirk)
> - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
> + if (dwc->dis_u2_susphy_quirk)
> + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
>
> - if (dwc->dis_enblslpm_quirk)
> - reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
> + if (dwc->dis_enblslpm_quirk)
> + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
>
> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
> + }
>
> - phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
> - phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
> + phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
> + }
> break;
> case DWC3_GCTL_PRTCAP_OTG:
> /* nothing to do on runtime_resume */
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 21312703e053..0bba074b44e4 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -35,6 +35,9 @@
>
> #define DWC3_MSG_MAX 500
>
> +/* Number of ports supported by a multiport controller */
> +#define MAX_PORTS_SUPPORTED 4
> +
> /* Define XHCI Extcap register offsets for getting multiport info */
> #define XHCI_HCC_PARAMS_OFFSET 0x10
> #define DWC3_XHCI_HCSPARAMS1 0x04
> @@ -1038,8 +1041,8 @@ struct dwc3_scratchpad_array {
> * @usb3_phy: pointer to USB3 PHY
> * @num_usb2_ports: number of usb2 ports.
> * @num_usb3_ports: number of usb3 ports.
> - * @usb2_generic_phy: pointer to USB2 PHY
> - * @usb3_generic_phy: pointer to USB3 PHY
> + * @usb2_generic_phy: pointer to array of USB2 PHY
> + * @usb3_generic_phy: pointer to array of USB3 PHY
> * @phys_ready: flag to indicate that PHYs are ready
> * @ulpi: pointer to ulpi interface
> * @ulpi_ready: flag to indicate that ULPI is initialized
> @@ -1177,9 +1180,8 @@ struct dwc3 {
>
> u32 num_usb2_ports;
> u32 num_usb3_ports;
> -
> - struct phy *usb2_generic_phy;
> - struct phy *usb3_generic_phy;
> + struct phy *usb2_generic_phy[MAX_PORTS_SUPPORTED];
> + struct phy *usb3_generic_phy[MAX_PORTS_SUPPORTED];
>
> bool phys_ready;
>
> diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
> index 039bf241769a..0377295717ab 100644
> --- a/drivers/usb/dwc3/drd.c
> +++ b/drivers/usb/dwc3/drd.c
> @@ -328,6 +328,7 @@ static void dwc3_otg_device_exit(struct dwc3 *dwc)
> void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
> {
> int ret;
> + int i;
> u32 reg;
> int id;
> unsigned long flags;
> @@ -386,9 +387,11 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
> } else {
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, true);
> - if (dwc->usb2_generic_phy)
> - phy_set_mode(dwc->usb2_generic_phy,
> - PHY_MODE_USB_HOST);
> + for (i = 0; i < dwc->num_usb2_ports; i++) {
> + if (dwc->usb2_generic_phy[i])
> + phy_set_mode(dwc->usb2_generic_phy[i],
> + PHY_MODE_USB_HOST);
> + }
> }
> break;
> case DWC3_OTG_ROLE_DEVICE:
> @@ -400,8 +403,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
>
> if (dwc->usb2_phy)
> otg_set_vbus(dwc->usb2_phy->otg, false);
> - if (dwc->usb2_generic_phy)
> - phy_set_mode(dwc->usb2_generic_phy,
> + if (dwc->usb2_generic_phy[0])
> + phy_set_mode(dwc->usb2_generic_phy[0],
> PHY_MODE_USB_DEVICE);
> ret = dwc3_gadget_init(dwc);
> if (ret)
> --
> 2.40.0
>

Thanks,
Thinh

2023-05-03 03:51:18

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 4/9] usb: dwc3: core: Skip setting event buffers for host only controllers



On 5/3/2023 3:14 AM, Thinh Nguyen wrote:
> On Mon, May 01, 2023, Krishna Kurapati wrote:
>> On some SoC's like SA8295P where the tertiary controller is host-only
>> capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible.
>> Trying to setup them up during core_init leads to a crash.
>>
>> For DRD/Peripheral supported controllers, event buffer setup is done
>> again in gadget_pullup. Skip setup or cleanup of event buffers if
>> controller is host-only capable.
>>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
>> drivers/usb/dwc3/core.c | 22 ++++++++++++++++------
>> 1 file changed, 16 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index b8ac7bcee391..8625fc5c7ab4 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -835,7 +835,12 @@ static void dwc3_clk_disable(struct dwc3 *dwc)
>>
>> static void dwc3_core_exit(struct dwc3 *dwc)
>> {
>> - dwc3_event_buffers_cleanup(dwc);
>> + unsigned int hw_mode;
>> +
>> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>> + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST)
>> + dwc3_event_buffers_cleanup(dwc);
>
> I think it's cleaner to do these checks in dwc3_event_buffers_cleanup
> and dwc3_event_buffers_setup.
>
> Thanks,
> Thinh
>

Hi Thinh,

Good point. Will move these checks to respective functions in next
version. Thanks for pointing it out.

Regards,
Krishna,
>> +
>> dwc3_phy_power_off(dwc);
>> dwc3_phy_exit(dwc);
>> dwc3_clk_disable(dwc);
>> @@ -1141,10 +1146,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
>> if (ret)
>> goto err_exit_phy;
>>
>> - ret = dwc3_event_buffers_setup(dwc);
>> - if (ret) {
>> - dev_err(dwc->dev, "failed to setup event buffers\n");
>> - goto err_power_off_phy;
>> + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) {
>> + ret = dwc3_event_buffers_setup(dwc);
>> + if (ret) {
>> + dev_err(dwc->dev, "failed to setup event buffers\n");
>> + goto err_power_off_phy;
>> + }
>> }
>>
>> /*
>> @@ -1958,7 +1965,10 @@ static int dwc3_probe(struct platform_device *pdev)
>>
>> err_exit_debugfs:
>> dwc3_debugfs_exit(dwc);
>> - dwc3_event_buffers_cleanup(dwc);
>> +
>> + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST)
>> + dwc3_event_buffers_cleanup(dwc);
>> +
>> dwc3_phy_power_off(dwc);
>> dwc3_phy_exit(dwc);
>> dwc3_ulpi_exit(dwc);
>> --
>> 2.40.0

2023-05-03 03:51:25

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 3/9] usb: dwc3: core: Access XHCI address space temporarily to read port info



On 5/3/2023 3:11 AM, Thinh Nguyen wrote:
> Hi,
>
> On Mon, May 01, 2023, Krishna Kurapati wrote:
>> Currently host-only capable DWC3 controllers support Multiport.
>> Temporarily map XHCI address space for host-only controllers and parse
>> XHCI Extended Capabilities registers to read number of usb2 ports and
>> usb3 ports present on multiport controller. Each USB Port is at least HS
>> capable.
>>
>> The port info for usb2 and usb3 phy are identified as num_usb2_ports
>> and num_usb3_ports. The intention is as follows:
>>
>> Wherever we need to perform phy operations like:
>>
>> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
>> {
>> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
>> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
>> }
>>
>> If number of usb2 ports is 3, loop can go from index 0-2 for
>> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
>> if the first 2 ports are SS capable or some other ports like (2 and 3)
>> are SS capable. So instead, num_usb2_ports is used to loop around all
>> phy's (both hs and ss) for performing phy operations. If any
>> usb3_generic_phy turns out to be NULL, phy operation just bails out.
>>
>> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
>> phy's as we need to know how many SS capable ports are there for this.
>>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
>> drivers/usb/dwc3/core.c | 68 +++++++++++++++++++++++++++++++++++++++++
>> drivers/usb/dwc3/core.h | 58 +++++++++++++++++++++++++++++++++++
>> 2 files changed, 126 insertions(+)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index 0beaab932e7d..b8ac7bcee391 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -1767,6 +1767,59 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
>> return 0;
>> }
>>
>> +static int dwc3_read_port_info(struct dwc3 *dwc)
>> +{
>> + void __iomem *regs;
>> + u32 offset;
>> + u32 temp;
>> + u8 major_revision;
>> + int ret = 0;
>> +
>> + /*
>> + * Remap xHCI address space to access XHCI ext cap regs,
>> + * since it is needed to get port info.
>> + */
>> + regs = ioremap(dwc->xhci_resources[0].start,
>> + resource_size(&dwc->xhci_resources[0]));
>> + if (IS_ERR(regs))
>> + return PTR_ERR(regs);
>> +
>> + offset = dwc3_xhci_find_next_ext_cap(regs, 0,
>> + XHCI_EXT_CAPS_PROTOCOL);
>> + while (offset) {
>> + temp = readl(regs + offset);
>> + major_revision = XHCI_EXT_PORT_MAJOR(temp);
>> +
>> + temp = readl(regs + offset + 0x08);
>> + if (major_revision == 0x03) {
>> + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp);
>> + } else if (major_revision <= 0x02) {
>> + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp);
>> + } else {
>> + dev_err(dwc->dev, "port revision seems wrong\n");
>
> Can we print this instead:
> dev_err(dwc->dev, "Unrecognized port major revision %d\n", major_revision);
>
>> + ret = -EINVAL;
>> + goto unmap_reg;
>> + }
>> +
>> + offset = dwc3_xhci_find_next_ext_cap(regs, offset,
>> + XHCI_EXT_CAPS_PROTOCOL);
>> + }
>> +
>> + temp = readl(regs + DWC3_XHCI_HCSPARAMS1);
>> + if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) {
>> + dev_err(dwc->dev, "inconsistency in port info\n");
>
> Can we print this instead:
> dev_err(dwc->dev, "Mismatched reported MAXPORTS (%d)\n", HCS_MAX_PORTS(temp));
>
>> + ret = -EINVAL;
>> + goto unmap_reg;
>> + }
>> +
>> + dev_dbg(dwc->dev,
>> + "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports);
>> +
>> +unmap_reg:
>> + iounmap(regs);
>> + return ret;
>> +}
>> +
>> static int dwc3_probe(struct platform_device *pdev)
>> {
>> struct device *dev = &pdev->dev;
>> @@ -1774,6 +1827,7 @@ static int dwc3_probe(struct platform_device *pdev)
>> void __iomem *regs;
>> struct dwc3 *dwc;
>> int ret;
>> + unsigned int hw_mode;
>>
>> dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
>> if (!dwc)
>> @@ -1843,6 +1897,20 @@ static int dwc3_probe(struct platform_device *pdev)
>> goto err_disable_clks;
>> }
>>
>> + /*
>> + * Currently DWC3 controllers that are host-only capable
>> + * support Multiport
>> + */
>> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>> + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
>> + ret = dwc3_read_port_info(dwc);
>> + if (ret)
>> + goto err_disable_clks;
>> + } else {
>> + dwc->num_usb2_ports = 1;
>> + dwc->num_usb3_ports = 1;
>> + }
>> +
>> spin_lock_init(&dwc->lock);
>> mutex_init(&dwc->mutex);
>>
>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>> index d56457c02996..21312703e053 100644
>> --- a/drivers/usb/dwc3/core.h
>> +++ b/drivers/usb/dwc3/core.h
>> @@ -35,6 +35,17 @@
>>
>> #define DWC3_MSG_MAX 500
>>
>> +/* Define XHCI Extcap register offsets for getting multiport info */
>> +#define XHCI_HCC_PARAMS_OFFSET 0x10
>> +#define DWC3_XHCI_HCSPARAMS1 0x04
>> +#define XHCI_EXT_CAPS_PROTOCOL 2
>> +#define XHCI_HCC_EXT_CAPS(x) (((x) >> 16) & 0xffff)
>> +#define XHCI_EXT_CAPS_ID(x) (((x) >> 0) & 0xff)
>> +#define XHCI_EXT_CAPS_NEXT(x) (((x) >> 8) & 0xff)
>> +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
>> +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
>> +#define HCS_MAX_PORTS(x) (((x) >> 24) & 0x7f)
>> +
>> /* Global constants */
>> #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
>> #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
>> @@ -1025,6 +1036,8 @@ struct dwc3_scratchpad_array {
>> * @usb_psy: pointer to power supply interface.
>> * @usb2_phy: pointer to USB2 PHY
>> * @usb3_phy: pointer to USB3 PHY
>> + * @num_usb2_ports: number of usb2 ports.
>> + * @num_usb3_ports: number of usb3 ports.
>> * @usb2_generic_phy: pointer to USB2 PHY
>> * @usb3_generic_phy: pointer to USB3 PHY
>> * @phys_ready: flag to indicate that PHYs are ready
>> @@ -1162,6 +1175,9 @@ struct dwc3 {
>> struct usb_phy *usb2_phy;
>> struct usb_phy *usb3_phy;
>>
>> + u32 num_usb2_ports;
>> + u32 num_usb3_ports;
>
> can we use u8?
>
>> +
>> struct phy *usb2_generic_phy;
>> struct phy *usb3_generic_phy;
>>
>> @@ -1650,4 +1666,46 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
>> { }
>> #endif
>>
>> +/**
>> + * dwc3_xhci_find_next_ext_cap - Find the offset of the extended capabilities
>> + * with capability ID id.
>> + *
>> + * @base PCI MMIO registers base address.
>> + * @start address at which to start looking, (0 or HCC_PARAMS to start at
>> + * beginning of list)
>> + * @id Extended capability ID to search for, or 0 for the next
>> + * capability
>
> I know that this is a duplicate from the xhci driver, but can we fix the
> kerneldoc style as in other places if we're going to keep it?
>

Hi Thinh,

Isn't this same as other functions ?

/**
* <function name> - description
* @params
*
*/

I missed the function name in comments last time, but added it in this
version.

Checkpatch too didn't give any errors/warnings other than alignment. Can
you help point out any other mistake in this function doc/comments so
that I can fix it in next version.

>> + *
>> + * Returns the offset of the next matching extended capability structure.
>> + * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
>> + * and this provides a way to find them all.
>> + */
>> +static inline int dwc3_xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
>
> This is a bit much for an inline function, can we just keep it in core.c
> as a static function >
Sure, will move this to core.c

Regards,
Krishna,

2023-05-03 04:04:17

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 8/9] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports



On 5/2/2023 4:36 PM, Konrad Dybcio wrote:
>
>
> On 1.05.2023 16:34, Krishna Kurapati wrote:
>> Enable tertiary controller for SA8295P (based on SC8280XP).
>> Add pinctrl support for usb ports to provide VBUS to connected peripherals.
>>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 ++++++++++++++++++++++++
>> 1 file changed, 47 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> index fd253942e5e5..7e6061c43835 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>> @@ -584,6 +584,19 @@ &usb_1_qmpphy {
>> status = "okay";
>> };
>>
>> +&usb_2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&usb2_en_state>,
>> + <&usb3_en_state>,
>> + <&usb4_en_state>,
>> + <&usb5_en_state>;
> This is misaligned. Also, please do property-n before property-names.
>
>> + status = "okay";
>> +};
>> +
>> +&usb_2_dwc3 {
>> + dr_mode = "host";
>> +};
>> +
>> &usb_2_hsphy0 {
>> vdda-pll-supply = <&vreg_l5a>;
>> vdda18-supply = <&vreg_l7g>;
>> @@ -729,3 +742,37 @@ wake-n-pins {
>> };
>> };
>> };
>> +
>> +&pmm8540c_gpios {
>> + usb2_en_state: usb2-en-state {
>> + pins = "gpio9";
>> + function = "normal";
>> + output-high;
>> + power-source = <0>;
> No drive-strength values?
>
> Konrad

Hi Konrad,

TBH, I didn't add the drive strength values as things worked out of
the box with the current changes (may be the default value of drive
strength is sufficient for us).

Let me know if it is mandatory, I will add it up in the next version.

Regards,
Krishna,

>> + };
>> +};
>> +
>> +&pmm8540e_gpios {
>> + usb3_en_state: usb3-en-state {
>> + pins = "gpio5";
>> + function = "normal";
>> + output-high;
>> + power-source = <0>;
>> + };
>> +};
>> +
>> +&pmm8540g_gpios {
>> + usb4_en_state: usb4-en-state {
>> + pins = "gpio5";
>> + function = "normal";
>> + output-high;
>> + power-source = <0>;
>> + };
>> +
>> + usb5_en_state: usb5-en-state {
>> + pins = "gpio9";
>> + function = "normal";
>> + output-high;
>> + power-source = <0>;
>> + };
>> +};

2023-05-03 04:17:05

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller



On 5/3/2023 3:41 AM, Thinh Nguyen wrote:
> On Mon, May 01, 2023, Krishna Kurapati wrote:
>> Currently the DWC3 driver supports only single port controller
>> which requires at most one HS and one SS PHY.
>>
>> But the DWC3 USB controller can be connected to multiple ports and
>> each port can have their own PHYs. Each port of the multiport
>> controller can either be HS+SS capable or HS only capable
>> Proper quantification of them is required to modify GUSB2PHYCFG
>> and GUSB3PIPECTL registers appropriately.
>>
>> Add support for detecting, obtaining and configuring phy's supported
>> by a multiport controller and limit the max number of ports
>> supported to 4.
>>
>> Signed-off-by: Harsh Agarwal <[email protected]>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>
> Are you a co-author or only Harsh is the main author of this patch?
>
Harsh began developing this series and pushed the first 3 RFC versions
(supporting both usb-phy / generic phy frameworks) until maintainers
pointed out that we only support generic phy changes.

From then on I took it up and started pushing next versions. I would
say both of us are primary authors for this patch. But if there has to
be only one, I would say its Harsh.

Regards,
Krishna,

>> ---
>> drivers/usb/dwc3/core.c | 262 +++++++++++++++++++++++++++++-----------
>> drivers/usb/dwc3/core.h | 12 +-
>> drivers/usb/dwc3/drd.c | 13 +-
>> 3 files changed, 209 insertions(+), 78 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index 8625fc5c7ab4..b91c3f965abc 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -121,6 +121,7 @@ static void __dwc3_set_mode(struct work_struct *work)
>> struct dwc3 *dwc = work_to_dwc(work);
>> unsigned long flags;
>> int ret;
>> + int i;
>> u32 reg;
>> u32 desired_dr_role;
>>
>> @@ -200,8 +201,10 @@ static void __dwc3_set_mode(struct work_struct *work)
>> } else {
>> if (dwc->usb2_phy)
>> otg_set_vbus(dwc->usb2_phy->otg, true);
>> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
>> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
>> + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
>> + }
>> if (dwc->dis_split_quirk) {
>> reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
>> reg |= DWC3_GUCTL3_SPLITDISABLE;
>> @@ -216,8 +219,8 @@ static void __dwc3_set_mode(struct work_struct *work)
>>
>> if (dwc->usb2_phy)
>> otg_set_vbus(dwc->usb2_phy->otg, false);
>> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
>> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
>> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
>> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>>
>> ret = dwc3_gadget_init(dwc);
>> if (ret)
>> @@ -575,22 +578,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
>> return ret;
>> }
>>
>> -/**
>> - * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
>> - * @dwc: Pointer to our controller context structure
>> - *
>> - * Returns 0 on success. The USB PHY interfaces are configured but not
>> - * initialized. The PHY interfaces and the PHYs get initialized together with
>> - * the core in dwc3_core_init.
>> - */
>> -static int dwc3_phy_setup(struct dwc3 *dwc)
>> +static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
>> {
>> unsigned int hw_mode;
>> u32 reg;
>>
>> hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>>
>> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
>> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
>>
>> /*
>> * Make sure UX_EXIT_PX is cleared as that causes issues with some
>> @@ -645,9 +640,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
>> if (dwc->dis_del_phy_power_chg_quirk)
>> reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
>>
>> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
>> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
>>
>> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
>> + return 0;
>> +}
>> +
>> +static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
>> +{
>> + unsigned int hw_mode;
>> + u32 reg;
>> +
>> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>> +
>> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
>>
>> /* Select the HS PHY interface */
>> switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
>> @@ -659,7 +664,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
>> } else if (dwc->hsphy_interface &&
>> !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
>> reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
>> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
>> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
>> } else {
>> /* Relying on default value. */
>> if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
>> @@ -726,7 +731,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
>> if (dwc->ulpi_ext_vbus_drv)
>> reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
>>
>> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
>> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
>> + * @dwc: Pointer to our controller context structure
>> + *
>> + * Returns 0 on success. The USB PHY interfaces are configured but not
>> + * initialized. The PHY interfaces and the PHYs get initialized together with
>> + * the core in dwc3_core_init.
>> + */
>> +static int dwc3_phy_setup(struct dwc3 *dwc)
>> +{
>> + int i;
>> + int ret;
>> +
>> + for (i = 0; i < dwc->num_usb3_ports; i++) {
>> + ret = dwc3_ss_phy_setup(dwc, i);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + ret = dwc3_hs_phy_setup(dwc, i);
>> + if (ret)
>> + return ret;
>> + }
>>
>> return 0;
>> }
>> @@ -734,22 +767,36 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
>> static int dwc3_phy_init(struct dwc3 *dwc)
>> {
>> int ret;
>> + int i, j;
>
> Minor style nit, can we declare in separate lines?
>
>>
>> usb_phy_init(dwc->usb2_phy);
>> usb_phy_init(dwc->usb3_phy);
>>
>> - ret = phy_init(dwc->usb2_generic_phy);
>> - if (ret < 0)
>> - goto err_shutdown_usb3_phy;
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + ret = phy_init(dwc->usb2_generic_phy[i]);
>> + if (ret < 0) {
>> + /* clean up prior initialized HS PHYs */
>> + for (j = 0; j < i; j++)
>> + phy_exit(dwc->usb2_generic_phy[j]);
>> + goto err_shutdown_usb3_phy;
>> + }
>> + }
>>
>> - ret = phy_init(dwc->usb3_generic_phy);
>> - if (ret < 0)
>> - goto err_exit_usb2_phy;
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + ret = phy_init(dwc->usb3_generic_phy[i]);
>> + if (ret < 0) {
>> + /* clean up prior initialized SS PHYs */
>> + for (j = 0; j < i; j++)
>> + phy_exit(dwc->usb3_generic_phy[j]);
>> + goto err_exit_usb2_phy;
>> + }
>> + }
>>
>> return 0;
>>
>> err_exit_usb2_phy:
>> - phy_exit(dwc->usb2_generic_phy);
>> + for (i = 0; i < dwc->num_usb2_ports; i++)
>> + phy_exit(dwc->usb2_generic_phy[i]);
>> err_shutdown_usb3_phy:
>> usb_phy_shutdown(dwc->usb3_phy);
>> usb_phy_shutdown(dwc->usb2_phy);
>> @@ -759,8 +806,12 @@ static int dwc3_phy_init(struct dwc3 *dwc)
>>
>> static void dwc3_phy_exit(struct dwc3 *dwc)
>> {
>> - phy_exit(dwc->usb3_generic_phy);
>> - phy_exit(dwc->usb2_generic_phy);
>> + int i;
>> +
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + phy_exit(dwc->usb3_generic_phy[i]);
>> + phy_exit(dwc->usb2_generic_phy[i]);
>> + }
>>
>> usb_phy_shutdown(dwc->usb3_phy);
>> usb_phy_shutdown(dwc->usb2_phy);
>> @@ -769,22 +820,36 @@ static void dwc3_phy_exit(struct dwc3 *dwc)
>> static int dwc3_phy_power_on(struct dwc3 *dwc)
>> {
>> int ret;
>> + int i, j;
>>
>> usb_phy_set_suspend(dwc->usb2_phy, 0);
>> usb_phy_set_suspend(dwc->usb3_phy, 0);
>>
>> - ret = phy_power_on(dwc->usb2_generic_phy);
>> - if (ret < 0)
>> - goto err_suspend_usb3_phy;
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + ret = phy_power_on(dwc->usb2_generic_phy[i]);
>> + if (ret < 0) {
>> + /* Turn off prior ON'ed HS Phy's */
>> + for (j = 0; j < i; j++)
>> + phy_power_off(dwc->usb2_generic_phy[j]);
>> + goto err_suspend_usb3_phy;
>> + }
>> + }
>>
>> - ret = phy_power_on(dwc->usb3_generic_phy);
>> - if (ret < 0)
>> - goto err_power_off_usb2_phy;
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + ret = phy_power_on(dwc->usb3_generic_phy[i]);
>> + if (ret < 0) {
>> + /* Turn of prior ON'ed SS Phy's */
>> + for (j = 0; j < i; j++)
>> + phy_power_off(dwc->usb3_generic_phy[j]);
>> + goto err_power_off_usb2_phy;
>> + }
>> + }
>>
>> return 0;
>>
>> err_power_off_usb2_phy:
>> - phy_power_off(dwc->usb2_generic_phy);
>> + for (i = 0; i < dwc->num_usb2_ports; i++)
>> + phy_power_off(dwc->usb2_generic_phy[i]);
>> err_suspend_usb3_phy:
>> usb_phy_set_suspend(dwc->usb3_phy, 1);
>> usb_phy_set_suspend(dwc->usb2_phy, 1);
>> @@ -794,8 +859,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc)
>>
>> static void dwc3_phy_power_off(struct dwc3 *dwc)
>> {
>> - phy_power_off(dwc->usb3_generic_phy);
>> - phy_power_off(dwc->usb2_generic_phy);
>> + int i;
>> +
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + phy_power_off(dwc->usb3_generic_phy[i]);
>> + phy_power_off(dwc->usb2_generic_phy[i]);
>> + }
>>
>> usb_phy_set_suspend(dwc->usb3_phy, 1);
>> usb_phy_set_suspend(dwc->usb2_phy, 1);
>> @@ -1073,6 +1142,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
>> unsigned int hw_mode;
>> u32 reg;
>> int ret;
>> + int i;
>>
>> hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>>
>> @@ -1116,15 +1186,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
>> if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
>> !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
>> if (!dwc->dis_u3_susphy_quirk) {
>> - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
>> - reg |= DWC3_GUSB3PIPECTL_SUSPHY;
>> - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
>> + for (i = 0; i < dwc->num_usb3_ports; i++) {
>> + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
>> + reg |= DWC3_GUSB3PIPECTL_SUSPHY;
>> + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
>> + }
>> }
>>
>> if (!dwc->dis_u2_susphy_quirk) {
>> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
>> - reg |= DWC3_GUSB2PHYCFG_SUSPHY;
>> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
>> + reg |= DWC3_GUSB2PHYCFG_SUSPHY;
>> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
>> + }
>> }
>> }
>>
>> @@ -1281,6 +1355,42 @@ static int dwc3_core_init(struct dwc3 *dwc)
>> return ret;
>> }
>>
>> +static int dwc3_get_multiport_phys(struct dwc3 *dwc)
>> +{
>> + int ret;
>> + struct device *dev = dwc->dev;
>> + int i;
>> + char phy_name[11];
>
> Minor minor nit. Can we reorder this as follow:
> struct device *dev = dwc->dev;
> char phy_name[11];
> int ret;
> int i;
>
>
>> +
>> + /*
>> + * Each port is at least HS capable. So loop over num_usb2_ports
>> + * to get available phy's.
>> + */
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + sprintf(phy_name, "usb2-port%d", i);
>> + dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
>> + if (IS_ERR(dwc->usb2_generic_phy[i])) {
>> + ret = PTR_ERR(dwc->usb2_generic_phy[i]);
>> + if (ret == -ENOSYS || ret == -ENODEV)
>> + dwc->usb2_generic_phy[i] = NULL;
>> + else
>> + return dev_err_probe(dev, ret, "usb2 phy: %s not configured\n", phy_name);
>> + }
>> +
>> + sprintf(phy_name, "usb3-port%d", i);
>> + dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
>> + if (IS_ERR(dwc->usb3_generic_phy[i])) {
>> + ret = PTR_ERR(dwc->usb3_generic_phy[i]);
>> + if (ret == -ENOSYS || ret == -ENODEV)
>> + dwc->usb3_generic_phy[i] = NULL;
>> + else
>> + return dev_err_probe(dev, ret, "usb3 phy: %s not configured\n", phy_name);
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> static int dwc3_core_get_phy(struct dwc3 *dwc)
>> {
>> struct device *dev = dwc->dev;
>> @@ -1311,20 +1421,23 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
>> return dev_err_probe(dev, ret, "no usb3 phy configured\n");
>> }
>>
>> - dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
>> - if (IS_ERR(dwc->usb2_generic_phy)) {
>> - ret = PTR_ERR(dwc->usb2_generic_phy);
>> + if (dwc->num_usb2_ports > 1)
>> + return dwc3_get_multiport_phys(dwc);
>> +
>> + dwc->usb2_generic_phy[0] = devm_phy_get(dev, "usb2-phy");
>> + if (IS_ERR(dwc->usb2_generic_phy[0])) {
>> + ret = PTR_ERR(dwc->usb2_generic_phy[0]);
>> if (ret == -ENOSYS || ret == -ENODEV)
>> - dwc->usb2_generic_phy = NULL;
>> + dwc->usb2_generic_phy[0] = NULL;
>> else
>> return dev_err_probe(dev, ret, "no usb2 phy configured\n");
>> }
>>
>> - dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
>> - if (IS_ERR(dwc->usb3_generic_phy)) {
>> - ret = PTR_ERR(dwc->usb3_generic_phy);
>> + dwc->usb3_generic_phy[0] = devm_phy_get(dev, "usb3-phy");
>> + if (IS_ERR(dwc->usb3_generic_phy[0])) {
>> + ret = PTR_ERR(dwc->usb3_generic_phy[0]);
>> if (ret == -ENOSYS || ret == -ENODEV)
>> - dwc->usb3_generic_phy = NULL;
>> + dwc->usb3_generic_phy[0] = NULL;
>> else
>> return dev_err_probe(dev, ret, "no usb3 phy configured\n");
>> }
>> @@ -1336,6 +1449,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>> {
>> struct device *dev = dwc->dev;
>> int ret;
>> + int i;
>>
>> switch (dwc->dr_mode) {
>> case USB_DR_MODE_PERIPHERAL:
>> @@ -1343,8 +1457,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>>
>> if (dwc->usb2_phy)
>> otg_set_vbus(dwc->usb2_phy->otg, false);
>> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
>> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
>> + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
>> + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
>>
>> ret = dwc3_gadget_init(dwc);
>> if (ret)
>> @@ -1355,8 +1469,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>>
>> if (dwc->usb2_phy)
>> otg_set_vbus(dwc->usb2_phy->otg, true);
>> - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
>> - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
>> + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
>> + }
>>
>> ret = dwc3_host_init(dwc);
>> if (ret)
>> @@ -2046,6 +2162,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc)
>>
>> static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
>> {
>> + int i;
>> unsigned long flags;
>> u32 reg;
>>
>> @@ -2066,17 +2183,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
>> /* Let controller to suspend HSPHY before PHY driver suspends */
>> if (dwc->dis_u2_susphy_quirk ||
>> dwc->dis_enblslpm_quirk) {
>> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
>> - reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
>> - DWC3_GUSB2PHYCFG_SUSPHY;
>> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
>> + reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
>> + DWC3_GUSB2PHYCFG_SUSPHY;
>> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
>> + }
>>
>> /* Give some time for USB2 PHY to suspend */
>> usleep_range(5000, 6000);
>> }
>>
>> - phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
>> - phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
>> + phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
>> + }
>> break;
>> case DWC3_GCTL_PRTCAP_OTG:
>> /* do nothing during runtime_suspend */
>> @@ -2105,6 +2226,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
>> {
>> unsigned long flags;
>> int ret;
>> + int i;
>> u32 reg;
>>
>> switch (dwc->current_dr_role) {
>> @@ -2125,17 +2247,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
>> break;
>> }
>> /* Restore GUSB2PHYCFG bits that were modified in suspend */
>> - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
>> - if (dwc->dis_u2_susphy_quirk)
>> - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
>> + if (dwc->dis_u2_susphy_quirk)
>> + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
>>
>> - if (dwc->dis_enblslpm_quirk)
>> - reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
>> + if (dwc->dis_enblslpm_quirk)
>> + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
>>
>> - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
>> + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
>> + }
>>
>> - phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
>> - phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
>> + phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
>> + }
>> break;
>> case DWC3_GCTL_PRTCAP_OTG:
>> /* nothing to do on runtime_resume */
>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>> index 21312703e053..0bba074b44e4 100644
>> --- a/drivers/usb/dwc3/core.h
>> +++ b/drivers/usb/dwc3/core.h
>> @@ -35,6 +35,9 @@
>>
>> #define DWC3_MSG_MAX 500
>>
>> +/* Number of ports supported by a multiport controller */
>> +#define MAX_PORTS_SUPPORTED 4
>> +
>> /* Define XHCI Extcap register offsets for getting multiport info */
>> #define XHCI_HCC_PARAMS_OFFSET 0x10
>> #define DWC3_XHCI_HCSPARAMS1 0x04
>> @@ -1038,8 +1041,8 @@ struct dwc3_scratchpad_array {
>> * @usb3_phy: pointer to USB3 PHY
>> * @num_usb2_ports: number of usb2 ports.
>> * @num_usb3_ports: number of usb3 ports.
>> - * @usb2_generic_phy: pointer to USB2 PHY
>> - * @usb3_generic_phy: pointer to USB3 PHY
>> + * @usb2_generic_phy: pointer to array of USB2 PHY
>> + * @usb3_generic_phy: pointer to array of USB3 PHY
>> * @phys_ready: flag to indicate that PHYs are ready
>> * @ulpi: pointer to ulpi interface
>> * @ulpi_ready: flag to indicate that ULPI is initialized
>> @@ -1177,9 +1180,8 @@ struct dwc3 {
>>
>> u32 num_usb2_ports;
>> u32 num_usb3_ports;
>> -
>> - struct phy *usb2_generic_phy;
>> - struct phy *usb3_generic_phy;
>> + struct phy *usb2_generic_phy[MAX_PORTS_SUPPORTED];
>> + struct phy *usb3_generic_phy[MAX_PORTS_SUPPORTED];
>>
>> bool phys_ready;
>>
>> diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
>> index 039bf241769a..0377295717ab 100644
>> --- a/drivers/usb/dwc3/drd.c
>> +++ b/drivers/usb/dwc3/drd.c
>> @@ -328,6 +328,7 @@ static void dwc3_otg_device_exit(struct dwc3 *dwc)
>> void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
>> {
>> int ret;
>> + int i;
>> u32 reg;
>> int id;
>> unsigned long flags;
>> @@ -386,9 +387,11 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
>> } else {
>> if (dwc->usb2_phy)
>> otg_set_vbus(dwc->usb2_phy->otg, true);
>> - if (dwc->usb2_generic_phy)
>> - phy_set_mode(dwc->usb2_generic_phy,
>> - PHY_MODE_USB_HOST);
>> + for (i = 0; i < dwc->num_usb2_ports; i++) {
>> + if (dwc->usb2_generic_phy[i])
>> + phy_set_mode(dwc->usb2_generic_phy[i],
>> + PHY_MODE_USB_HOST);
>> + }
>> }
>> break;
>> case DWC3_OTG_ROLE_DEVICE:
>> @@ -400,8 +403,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
>>
>> if (dwc->usb2_phy)
>> otg_set_vbus(dwc->usb2_phy->otg, false);
>> - if (dwc->usb2_generic_phy)
>> - phy_set_mode(dwc->usb2_generic_phy,
>> + if (dwc->usb2_generic_phy[0])
>> + phy_set_mode(dwc->usb2_generic_phy[0],
>> PHY_MODE_USB_DEVICE);
>> ret = dwc3_gadget_init(dwc);
>> if (ret)
>> --
>> 2.40.0
>>
>
> Thanks,
> Thinh

2023-05-03 11:35:27

by Johan Hovold

[permalink] [raw]
Subject: Re: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

On Mon, May 01, 2023 at 08:04:41PM +0530, Krishna Kurapati wrote:
> Currently the DWC3 driver supports only single port controller
> which requires at most one HS and one SS PHY.
>
> But the DWC3 USB controller can be connected to multiple ports and
> each port can have their own PHYs. Each port of the multiport
> controller can either be HS+SS capable or HS only capable
> Proper quantification of them is required to modify GUSB2PHYCFG
> and GUSB3PIPECTL registers appropriately.
>
> Add support for detecting, obtaining and configuring phy's supported
> by a multiport controller and limit the max number of ports
> supported to 4.
>
> Signed-off-by: Harsh Agarwal <[email protected]>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> drivers/usb/dwc3/core.c | 262 +++++++++++++++++++++++++++++-----------
> drivers/usb/dwc3/core.h | 12 +-
> drivers/usb/dwc3/drd.c | 13 +-
> 3 files changed, 209 insertions(+), 78 deletions(-)

Note that this patch no longer applies and you need to rebase the series
on mainline (e.g. including commit 1d72fab47656 ("USB: dwc3: refactor
phy handling").

Johan

2023-05-03 14:23:32

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller



On 5/3/2023 4:40 PM, Johan Hovold wrote:
> On Mon, May 01, 2023 at 08:04:41PM +0530, Krishna Kurapati wrote:
>> Currently the DWC3 driver supports only single port controller
>> which requires at most one HS and one SS PHY.
>>
>> But the DWC3 USB controller can be connected to multiple ports and
>> each port can have their own PHYs. Each port of the multiport
>> controller can either be HS+SS capable or HS only capable
>> Proper quantification of them is required to modify GUSB2PHYCFG
>> and GUSB3PIPECTL registers appropriately.
>>
>> Add support for detecting, obtaining and configuring phy's supported
>> by a multiport controller and limit the max number of ports
>> supported to 4.
>>
>> Signed-off-by: Harsh Agarwal <[email protected]>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
>> drivers/usb/dwc3/core.c | 262 +++++++++++++++++++++++++++++-----------
>> drivers/usb/dwc3/core.h | 12 +-
>> drivers/usb/dwc3/drd.c | 13 +-
>> 3 files changed, 209 insertions(+), 78 deletions(-)
>
> Note that this patch no longer applies and you need to rebase the series
> on mainline (e.g. including commit 1d72fab47656 ("USB: dwc3: refactor
> phy handling").
>
> Johan

Hi Johan,

This series is rebased on top of usb-next (on top of the above
mentioned patch). Probably that is why its not applying on top of
linux-next.

Regards,
Krishna,

2023-05-03 14:28:11

by Johan Hovold

[permalink] [raw]
Subject: Re: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

On Wed, May 03, 2023 at 07:50:57PM +0530, Krishna Kurapati PSSNV wrote:
> On 5/3/2023 4:40 PM, Johan Hovold wrote:
> > On Mon, May 01, 2023 at 08:04:41PM +0530, Krishna Kurapati wrote:
> >> Currently the DWC3 driver supports only single port controller
> >> which requires at most one HS and one SS PHY.
> >>
> >> But the DWC3 USB controller can be connected to multiple ports and
> >> each port can have their own PHYs. Each port of the multiport
> >> controller can either be HS+SS capable or HS only capable
> >> Proper quantification of them is required to modify GUSB2PHYCFG
> >> and GUSB3PIPECTL registers appropriately.
> >>
> >> Add support for detecting, obtaining and configuring phy's supported
> >> by a multiport controller and limit the max number of ports
> >> supported to 4.
> >>
> >> Signed-off-by: Harsh Agarwal <[email protected]>
> >> Signed-off-by: Krishna Kurapati <[email protected]>
> >> ---
> >> drivers/usb/dwc3/core.c | 262 +++++++++++++++++++++++++++++-----------
> >> drivers/usb/dwc3/core.h | 12 +-
> >> drivers/usb/dwc3/drd.c | 13 +-
> >> 3 files changed, 209 insertions(+), 78 deletions(-)
> >
> > Note that this patch no longer applies and you need to rebase the series
> > on mainline (e.g. including commit 1d72fab47656 ("USB: dwc3: refactor
> > phy handling").

> This series is rebased on top of usb-next (on top of the above
> mentioned patch). Probably that is why its not applying on top of
> linux-next.

Indeed it is. Sorry about the noise. Let me go double check why it did
not apply here. Perhaps I'm missing something else from usb-next.

Johan

2023-05-03 14:45:23

by Johan Hovold

[permalink] [raw]
Subject: Re: [PATCH v7 7/9] arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280

On Mon, May 01, 2023 at 08:04:43PM +0530, Krishna Kurapati wrote:
> Add USB and DWC3 node for tertiary port of SC8280 along with multiport
> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
> platforms.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 8fa9fbfe5d00..0e4fb286956b 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint {
> };
> };
>
> + usb_2: usb@a4f8800 {
> + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
> + reg = <0 0x0a4f8800 0 0x400>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
> + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
> + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
> +
> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;

This looks wrong. You're missing the &intc phandle for the last four
entries:

DTC arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dtb
/home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3372.4-3378.17: Warning (interrupts_extended_property): /soc@0/usb@a4f8800:interrupts-extended: cell 10 is not a phandle reference
/home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3349.22-3411.5: Warning (interrupts_extended_property): /soc@0/usb@a4f8800: Missing property '#interrupt-cells' in node /soc@0/display-subsystem@ae00000/displayport-controller@aea0000/opp-table or bad phandle (referred from interrupts-extended[10])
also defined at /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sa8540p-ride.dts:312.8-317.3
/home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3372.4-3378.17: Warning (interrupts_extended_property): /soc@0/usb@a4f8800:interrupts-extended: cell 10 is not a phandle reference
/home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3349.22-3411.5: Warning (interrupts_extended_property): /soc@0/usb@a4f8800: Missing property '#interrupt-cells' in node /soc@0/display-subsystem@ae00000/displayport-controller@ae9a000/ports/port@0/endpoint or bad phandle (referred from interrupts-extended[10])
also defined at /home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sa8295p-adp.dts:587.8-594.3
/home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3372.4-3378.17: Warning (interrupts_extended_property): /soc@0/usb@a4f8800:interrupts-extended: cell 10 is not a phandle reference
/home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3349.22-3411.5: Warning (interrupts_extended_property): /soc@0/usb@a4f8800: Missing property '#interrupt-cells' in node /interconnect-mmss-noc or bad phandle (referred from interrupts-extended[10])
/home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3372.4-3378.17: Warning (interrupts_extended_property): /soc@0/usb@a4f8800:interrupts-extended: cell 10 is not a phandle reference
/home/johan/work/linaro/src/linux/arch/arm64/boot/dts/qcom/sc8280xp.dtsi:3349.22-3411.5: Warning (interrupts_extended_property): /soc@0/usb@a4f8800: Missing property '#interrupt-cells' in node /soc@0/phy@88e7000 or bad phandle (referred from interrupts-extended[10])

> + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
> + "ss_phy_irq", "pwr_event_1",
> + "pwr_event_2", "pwr_event_3",
> + "pwr_event_4";

Also the order does not match the binding where you had the pwr_event
interrupts first.

Johan

2023-05-03 21:56:16

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v7 3/9] usb: dwc3: core: Access XHCI address space temporarily to read port info

On Wed, May 03, 2023, Krishna Kurapati PSSNV wrote:
>
>
> On 5/3/2023 3:11 AM, Thinh Nguyen wrote:
> > Hi,
> >
> > On Mon, May 01, 2023, Krishna Kurapati wrote:
> > > Currently host-only capable DWC3 controllers support Multiport.
> > > Temporarily map XHCI address space for host-only controllers and parse
> > > XHCI Extended Capabilities registers to read number of usb2 ports and
> > > usb3 ports present on multiport controller. Each USB Port is at least HS
> > > capable.
> > >
> > > The port info for usb2 and usb3 phy are identified as num_usb2_ports
> > > and num_usb3_ports. The intention is as follows:
> > >
> > > Wherever we need to perform phy operations like:
> > >
> > > LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> > > {
> > > phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> > > phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> > > }
> > >
> > > If number of usb2 ports is 3, loop can go from index 0-2 for
> > > usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> > > if the first 2 ports are SS capable or some other ports like (2 and 3)
> > > are SS capable. So instead, num_usb2_ports is used to loop around all
> > > phy's (both hs and ss) for performing phy operations. If any
> > > usb3_generic_phy turns out to be NULL, phy operation just bails out.
> > >
> > > num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> > > phy's as we need to know how many SS capable ports are there for this.
> > >
> > > Signed-off-by: Krishna Kurapati <[email protected]>
> > > ---
> > > drivers/usb/dwc3/core.c | 68 +++++++++++++++++++++++++++++++++++++++++
> > > drivers/usb/dwc3/core.h | 58 +++++++++++++++++++++++++++++++++++
> > > 2 files changed, 126 insertions(+)
> > >
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 0beaab932e7d..b8ac7bcee391 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -1767,6 +1767,59 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> > > return 0;
> > > }
> > > +static int dwc3_read_port_info(struct dwc3 *dwc)
> > > +{
> > > + void __iomem *regs;
> > > + u32 offset;
> > > + u32 temp;
> > > + u8 major_revision;
> > > + int ret = 0;
> > > +
> > > + /*
> > > + * Remap xHCI address space to access XHCI ext cap regs,
> > > + * since it is needed to get port info.
> > > + */
> > > + regs = ioremap(dwc->xhci_resources[0].start,
> > > + resource_size(&dwc->xhci_resources[0]));
> > > + if (IS_ERR(regs))
> > > + return PTR_ERR(regs);
> > > +
> > > + offset = dwc3_xhci_find_next_ext_cap(regs, 0,
> > > + XHCI_EXT_CAPS_PROTOCOL);
> > > + while (offset) {
> > > + temp = readl(regs + offset);
> > > + major_revision = XHCI_EXT_PORT_MAJOR(temp);
> > > +
> > > + temp = readl(regs + offset + 0x08);
> > > + if (major_revision == 0x03) {
> > > + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp);
> > > + } else if (major_revision <= 0x02) {
> > > + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp);
> > > + } else {
> > > + dev_err(dwc->dev, "port revision seems wrong\n");
> >
> > Can we print this instead:
> > dev_err(dwc->dev, "Unrecognized port major revision %d\n", major_revision);
> >
> > > + ret = -EINVAL;
> > > + goto unmap_reg;
> > > + }
> > > +
> > > + offset = dwc3_xhci_find_next_ext_cap(regs, offset,
> > > + XHCI_EXT_CAPS_PROTOCOL);
> > > + }
> > > +
> > > + temp = readl(regs + DWC3_XHCI_HCSPARAMS1);
> > > + if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) {
> > > + dev_err(dwc->dev, "inconsistency in port info\n");
> >
> > Can we print this instead:
> > dev_err(dwc->dev, "Mismatched reported MAXPORTS (%d)\n", HCS_MAX_PORTS(temp));
> >
> > > + ret = -EINVAL;
> > > + goto unmap_reg;
> > > + }
> > > +
> > > + dev_dbg(dwc->dev,
> > > + "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports);
> > > +
> > > +unmap_reg:
> > > + iounmap(regs);
> > > + return ret;
> > > +}
> > > +
> > > static int dwc3_probe(struct platform_device *pdev)
> > > {
> > > struct device *dev = &pdev->dev;
> > > @@ -1774,6 +1827,7 @@ static int dwc3_probe(struct platform_device *pdev)
> > > void __iomem *regs;
> > > struct dwc3 *dwc;
> > > int ret;
> > > + unsigned int hw_mode;
> > > dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
> > > if (!dwc)
> > > @@ -1843,6 +1897,20 @@ static int dwc3_probe(struct platform_device *pdev)
> > > goto err_disable_clks;
> > > }
> > > + /*
> > > + * Currently DWC3 controllers that are host-only capable
> > > + * support Multiport
> > > + */
> > > + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> > > + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
> > > + ret = dwc3_read_port_info(dwc);
> > > + if (ret)
> > > + goto err_disable_clks;
> > > + } else {
> > > + dwc->num_usb2_ports = 1;
> > > + dwc->num_usb3_ports = 1;
> > > + }
> > > +
> > > spin_lock_init(&dwc->lock);
> > > mutex_init(&dwc->mutex);
> > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > > index d56457c02996..21312703e053 100644
> > > --- a/drivers/usb/dwc3/core.h
> > > +++ b/drivers/usb/dwc3/core.h
> > > @@ -35,6 +35,17 @@
> > > #define DWC3_MSG_MAX 500
> > > +/* Define XHCI Extcap register offsets for getting multiport info */
> > > +#define XHCI_HCC_PARAMS_OFFSET 0x10
> > > +#define DWC3_XHCI_HCSPARAMS1 0x04
> > > +#define XHCI_EXT_CAPS_PROTOCOL 2
> > > +#define XHCI_HCC_EXT_CAPS(x) (((x) >> 16) & 0xffff)
> > > +#define XHCI_EXT_CAPS_ID(x) (((x) >> 0) & 0xff)
> > > +#define XHCI_EXT_CAPS_NEXT(x) (((x) >> 8) & 0xff)
> > > +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
> > > +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
> > > +#define HCS_MAX_PORTS(x) (((x) >> 24) & 0x7f)
> > > +
> > > /* Global constants */
> > > #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
> > > #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
> > > @@ -1025,6 +1036,8 @@ struct dwc3_scratchpad_array {
> > > * @usb_psy: pointer to power supply interface.
> > > * @usb2_phy: pointer to USB2 PHY
> > > * @usb3_phy: pointer to USB3 PHY
> > > + * @num_usb2_ports: number of usb2 ports.
> > > + * @num_usb3_ports: number of usb3 ports.
> > > * @usb2_generic_phy: pointer to USB2 PHY
> > > * @usb3_generic_phy: pointer to USB3 PHY
> > > * @phys_ready: flag to indicate that PHYs are ready
> > > @@ -1162,6 +1175,9 @@ struct dwc3 {
> > > struct usb_phy *usb2_phy;
> > > struct usb_phy *usb3_phy;
> > > + u32 num_usb2_ports;
> > > + u32 num_usb3_ports;
> >
> > can we use u8?
> >
> > > +
> > > struct phy *usb2_generic_phy;
> > > struct phy *usb3_generic_phy;
> > > @@ -1650,4 +1666,46 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
> > > { }
> > > #endif
> > > +/**
> > > + * dwc3_xhci_find_next_ext_cap - Find the offset of the extended capabilities
> > > + * with capability ID id.
> > > + *
> > > + * @base PCI MMIO registers base address.
> > > + * @start address at which to start looking, (0 or HCC_PARAMS to start at
> > > + * beginning of list)
> > > + * @id Extended capability ID to search for, or 0 for the next
> > > + * capability
> >
> > I know that this is a duplicate from the xhci driver, but can we fix the
> > kerneldoc style as in other places if we're going to keep it?
> >
>
> Hi Thinh,
>
> Isn't this same as other functions ?
>
> /**
> * <function name> - description
> * @params
> *
> */
>
> I missed the function name in comments last time, but added it in this
> version.
>
> Checkpatch too didn't give any errors/warnings other than alignment. Can you
> help point out any other mistake in this function doc/comments so that I can
> fix it in next version.
>

It's missing ":" after @params.

You can use the kernel-doc script to check for documentation's
errors/warnings.

Here's the output if you run the following command:
# <KERNEL_SRC>/scripts/kernel-doc -none -Werror -function dwc3_xhci_find_next_ext_cap drivers/usb/dwc3/core.h

drivers/usb/dwc3/core.h:1684: warning: Function parameter or member 'base' not described in 'dwc3_xhci_find_next_ext_cap'
drivers/usb/dwc3/core.h:1684: warning: Function parameter or member 'start' not described in 'dwc3_xhci_find_next_ext_cap'
drivers/usb/dwc3/core.h:1684: warning: Function parameter or member 'id' not described in 'dwc3_xhci_find_next_ext_cap'
3 warnings as Errors


This is a minor style issue. While I don't think it's strictly needed to
follow the kerneldoc style for a non-api function. But if we do follow
it, we should do it correctly.

Thanks,
Thinh

2023-05-03 22:02:16

by Thinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller

On Wed, May 03, 2023, Krishna Kurapati PSSNV wrote:
>
>
> On 5/3/2023 3:41 AM, Thinh Nguyen wrote:
> > On Mon, May 01, 2023, Krishna Kurapati wrote:
> > > Currently the DWC3 driver supports only single port controller
> > > which requires at most one HS and one SS PHY.
> > >
> > > But the DWC3 USB controller can be connected to multiple ports and
> > > each port can have their own PHYs. Each port of the multiport
> > > controller can either be HS+SS capable or HS only capable
> > > Proper quantification of them is required to modify GUSB2PHYCFG
> > > and GUSB3PIPECTL registers appropriately.
> > >
> > > Add support for detecting, obtaining and configuring phy's supported
> > > by a multiport controller and limit the max number of ports
> > > supported to 4.
> > >
> > > Signed-off-by: Harsh Agarwal <[email protected]>
> > > Signed-off-by: Krishna Kurapati <[email protected]>
> >
> > Are you a co-author or only Harsh is the main author of this patch?
> >
> Harsh began developing this series and pushed the first 3 RFC versions
> (supporting both usb-phy / generic phy frameworks) until maintainers pointed
> out that we only support generic phy changes.
>
> From then on I took it up and started pushing next versions. I would say
> both of us are primary authors for this patch. But if there has to be only
> one, I would say its Harsh.
>
> Regards,
> Krishna,
>

I just want to check to give you proper credit for the patch's
contribution. Since Harsh isn't the only one working on this you're not
simply transporting this change. Perhaps you should add Co-developed-by
tags.

Thanks,
Thinh

2023-05-04 04:20:10

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 3/9] usb: dwc3: core: Access XHCI address space temporarily to read port info



On 5/4/2023 3:19 AM, Thinh Nguyen wrote:
> On Wed, May 03, 2023, Krishna Kurapati PSSNV wrote:
>>
>>
>> On 5/3/2023 3:11 AM, Thinh Nguyen wrote:
>>> Hi,
>>>
>>> On Mon, May 01, 2023, Krishna Kurapati wrote:
>>>> Currently host-only capable DWC3 controllers support Multiport.
>>>> Temporarily map XHCI address space for host-only controllers and parse
>>>> XHCI Extended Capabilities registers to read number of usb2 ports and
>>>> usb3 ports present on multiport controller. Each USB Port is at least HS
>>>> capable.
>>>>
>>>> The port info for usb2 and usb3 phy are identified as num_usb2_ports
>>>> and num_usb3_ports. The intention is as follows:
>>>>
>>>> Wherever we need to perform phy operations like:
>>>>
>>>> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
>>>> {
>>>> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
>>>> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
>>>> }
>>>>
>>>> If number of usb2 ports is 3, loop can go from index 0-2 for
>>>> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
>>>> if the first 2 ports are SS capable or some other ports like (2 and 3)
>>>> are SS capable. So instead, num_usb2_ports is used to loop around all
>>>> phy's (both hs and ss) for performing phy operations. If any
>>>> usb3_generic_phy turns out to be NULL, phy operation just bails out.
>>>>
>>>> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
>>>> phy's as we need to know how many SS capable ports are there for this.
>>>>
>>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>>> ---
>>>> drivers/usb/dwc3/core.c | 68 +++++++++++++++++++++++++++++++++++++++++
>>>> drivers/usb/dwc3/core.h | 58 +++++++++++++++++++++++++++++++++++
>>>> 2 files changed, 126 insertions(+)
>>>>
>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>>>> index 0beaab932e7d..b8ac7bcee391 100644
>>>> --- a/drivers/usb/dwc3/core.c
>>>> +++ b/drivers/usb/dwc3/core.c
>>>> @@ -1767,6 +1767,59 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
>>>> return 0;
>>>> }
>>>> +static int dwc3_read_port_info(struct dwc3 *dwc)
>>>> +{
>>>> + void __iomem *regs;
>>>> + u32 offset;
>>>> + u32 temp;
>>>> + u8 major_revision;
>>>> + int ret = 0;
>>>> +
>>>> + /*
>>>> + * Remap xHCI address space to access XHCI ext cap regs,
>>>> + * since it is needed to get port info.
>>>> + */
>>>> + regs = ioremap(dwc->xhci_resources[0].start,
>>>> + resource_size(&dwc->xhci_resources[0]));
>>>> + if (IS_ERR(regs))
>>>> + return PTR_ERR(regs);
>>>> +
>>>> + offset = dwc3_xhci_find_next_ext_cap(regs, 0,
>>>> + XHCI_EXT_CAPS_PROTOCOL);
>>>> + while (offset) {
>>>> + temp = readl(regs + offset);
>>>> + major_revision = XHCI_EXT_PORT_MAJOR(temp);
>>>> +
>>>> + temp = readl(regs + offset + 0x08);
>>>> + if (major_revision == 0x03) {
>>>> + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp);
>>>> + } else if (major_revision <= 0x02) {
>>>> + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp);
>>>> + } else {
>>>> + dev_err(dwc->dev, "port revision seems wrong\n");
>>>
>>> Can we print this instead:
>>> dev_err(dwc->dev, "Unrecognized port major revision %d\n", major_revision);
>>>
>>>> + ret = -EINVAL;
>>>> + goto unmap_reg;
>>>> + }
>>>> +
>>>> + offset = dwc3_xhci_find_next_ext_cap(regs, offset,
>>>> + XHCI_EXT_CAPS_PROTOCOL);
>>>> + }
>>>> +
>>>> + temp = readl(regs + DWC3_XHCI_HCSPARAMS1);
>>>> + if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) {
>>>> + dev_err(dwc->dev, "inconsistency in port info\n");
>>>
>>> Can we print this instead:
>>> dev_err(dwc->dev, "Mismatched reported MAXPORTS (%d)\n", HCS_MAX_PORTS(temp));
>>>
>>>> + ret = -EINVAL;
>>>> + goto unmap_reg;
>>>> + }
>>>> +
>>>> + dev_dbg(dwc->dev,
>>>> + "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports);
>>>> +
>>>> +unmap_reg:
>>>> + iounmap(regs);
>>>> + return ret;
>>>> +}
>>>> +
>>>> static int dwc3_probe(struct platform_device *pdev)
>>>> {
>>>> struct device *dev = &pdev->dev;
>>>> @@ -1774,6 +1827,7 @@ static int dwc3_probe(struct platform_device *pdev)
>>>> void __iomem *regs;
>>>> struct dwc3 *dwc;
>>>> int ret;
>>>> + unsigned int hw_mode;
>>>> dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
>>>> if (!dwc)
>>>> @@ -1843,6 +1897,20 @@ static int dwc3_probe(struct platform_device *pdev)
>>>> goto err_disable_clks;
>>>> }
>>>> + /*
>>>> + * Currently DWC3 controllers that are host-only capable
>>>> + * support Multiport
>>>> + */
>>>> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
>>>> + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
>>>> + ret = dwc3_read_port_info(dwc);
>>>> + if (ret)
>>>> + goto err_disable_clks;
>>>> + } else {
>>>> + dwc->num_usb2_ports = 1;
>>>> + dwc->num_usb3_ports = 1;
>>>> + }
>>>> +
>>>> spin_lock_init(&dwc->lock);
>>>> mutex_init(&dwc->mutex);
>>>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>>>> index d56457c02996..21312703e053 100644
>>>> --- a/drivers/usb/dwc3/core.h
>>>> +++ b/drivers/usb/dwc3/core.h
>>>> @@ -35,6 +35,17 @@
>>>> #define DWC3_MSG_MAX 500
>>>> +/* Define XHCI Extcap register offsets for getting multiport info */
>>>> +#define XHCI_HCC_PARAMS_OFFSET 0x10
>>>> +#define DWC3_XHCI_HCSPARAMS1 0x04
>>>> +#define XHCI_EXT_CAPS_PROTOCOL 2
>>>> +#define XHCI_HCC_EXT_CAPS(x) (((x) >> 16) & 0xffff)
>>>> +#define XHCI_EXT_CAPS_ID(x) (((x) >> 0) & 0xff)
>>>> +#define XHCI_EXT_CAPS_NEXT(x) (((x) >> 8) & 0xff)
>>>> +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
>>>> +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
>>>> +#define HCS_MAX_PORTS(x) (((x) >> 24) & 0x7f)
>>>> +
>>>> /* Global constants */
>>>> #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
>>>> #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
>>>> @@ -1025,6 +1036,8 @@ struct dwc3_scratchpad_array {
>>>> * @usb_psy: pointer to power supply interface.
>>>> * @usb2_phy: pointer to USB2 PHY
>>>> * @usb3_phy: pointer to USB3 PHY
>>>> + * @num_usb2_ports: number of usb2 ports.
>>>> + * @num_usb3_ports: number of usb3 ports.
>>>> * @usb2_generic_phy: pointer to USB2 PHY
>>>> * @usb3_generic_phy: pointer to USB3 PHY
>>>> * @phys_ready: flag to indicate that PHYs are ready
>>>> @@ -1162,6 +1175,9 @@ struct dwc3 {
>>>> struct usb_phy *usb2_phy;
>>>> struct usb_phy *usb3_phy;
>>>> + u32 num_usb2_ports;
>>>> + u32 num_usb3_ports;
>>>
>>> can we use u8?
>>>
>>>> +
>>>> struct phy *usb2_generic_phy;
>>>> struct phy *usb3_generic_phy;
>>>> @@ -1650,4 +1666,46 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
>>>> { }
>>>> #endif
>>>> +/**
>>>> + * dwc3_xhci_find_next_ext_cap - Find the offset of the extended capabilities
>>>> + * with capability ID id.
>>>> + *
>>>> + * @base PCI MMIO registers base address.
>>>> + * @start address at which to start looking, (0 or HCC_PARAMS to start at
>>>> + * beginning of list)
>>>> + * @id Extended capability ID to search for, or 0 for the next
>>>> + * capability
>>>
>>> I know that this is a duplicate from the xhci driver, but can we fix the
>>> kerneldoc style as in other places if we're going to keep it?
>>>
>>
>> Hi Thinh,
>>
>> Isn't this same as other functions ?
>>
>> /**
>> * <function name> - description
>> * @params
>> *
>> */
>>
>> I missed the function name in comments last time, but added it in this
>> version.
>>
>> Checkpatch too didn't give any errors/warnings other than alignment. Can you
>> help point out any other mistake in this function doc/comments so that I can
>> fix it in next version.
>>
>
> It's missing ":" after @params.
>
> You can use the kernel-doc script to check for documentation's
> errors/warnings.
>
> Here's the output if you run the following command:
> # <KERNEL_SRC>/scripts/kernel-doc -none -Werror -function dwc3_xhci_find_next_ext_cap drivers/usb/dwc3/core.h
>
> drivers/usb/dwc3/core.h:1684: warning: Function parameter or member 'base' not described in 'dwc3_xhci_find_next_ext_cap'
> drivers/usb/dwc3/core.h:1684: warning: Function parameter or member 'start' not described in 'dwc3_xhci_find_next_ext_cap'
> drivers/usb/dwc3/core.h:1684: warning: Function parameter or member 'id' not described in 'dwc3_xhci_find_next_ext_cap'
> 3 warnings as Errors
>
>
> This is a minor style issue. While I don't think it's strictly needed to
> follow the kerneldoc style for a non-api function. But if we do follow
> it, we should do it correctly.
>
> Thanks,
> Thinh

Thanks Thinh for pointing it out. Will fix this in the next version.

Regards,
Krishna,

2023-05-04 04:51:54

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller



On 5/4/2023 3:25 AM, Thinh Nguyen wrote:
> On Wed, May 03, 2023, Krishna Kurapati PSSNV wrote:
>>
>>
>> On 5/3/2023 3:41 AM, Thinh Nguyen wrote:
>>> On Mon, May 01, 2023, Krishna Kurapati wrote:
>>>> Currently the DWC3 driver supports only single port controller
>>>> which requires at most one HS and one SS PHY.
>>>>
>>>> But the DWC3 USB controller can be connected to multiple ports and
>>>> each port can have their own PHYs. Each port of the multiport
>>>> controller can either be HS+SS capable or HS only capable
>>>> Proper quantification of them is required to modify GUSB2PHYCFG
>>>> and GUSB3PIPECTL registers appropriately.
>>>>
>>>> Add support for detecting, obtaining and configuring phy's supported
>>>> by a multiport controller and limit the max number of ports
>>>> supported to 4.
>>>>
>>>> Signed-off-by: Harsh Agarwal <[email protected]>
>>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>>
>>> Are you a co-author or only Harsh is the main author of this patch?
>>>
>> Harsh began developing this series and pushed the first 3 RFC versions
>> (supporting both usb-phy / generic phy frameworks) until maintainers pointed
>> out that we only support generic phy changes.
>>
>> From then on I took it up and started pushing next versions. I would say
>> both of us are primary authors for this patch. But if there has to be only
>> one, I would say its Harsh.
>>
>> Regards,
>> Krishna,
>>
>
> I just want to check to give you proper credit for the patch's
> contribution. Since Harsh isn't the only one working on this you're not
> simply transporting this change. Perhaps you should add Co-developed-by
> tags.
>
> Thanks,
> Thinh

Sure,

Let me put myself under Co-developed-by in the next version.

Regards,
Krishna,

2023-05-04 06:52:41

by Konrad Dybcio

[permalink] [raw]
Subject: Re: [PATCH v7 8/9] arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports



On 3.05.2023 05:55, Krishna Kurapati PSSNV wrote:
>
>
> On 5/2/2023 4:36 PM, Konrad Dybcio wrote:
>>
>>
>> On 1.05.2023 16:34, Krishna Kurapati wrote:
>>> Enable tertiary controller for SA8295P (based on SC8280XP).
>>> Add pinctrl support for usb ports to provide VBUS to connected peripherals.
>>>
>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 ++++++++++++++++++++++++
>>>   1 file changed, 47 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>>> index fd253942e5e5..7e6061c43835 100644
>>> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>>> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
>>> @@ -584,6 +584,19 @@ &usb_1_qmpphy {
>>>       status = "okay";
>>>   };
>>>   +&usb_2 {
>>> +    pinctrl-names = "default";
>>> +    pinctrl-0 = <&usb2_en_state>,
>>> +            <&usb3_en_state>,
>>> +            <&usb4_en_state>,
>>> +            <&usb5_en_state>;
>> This is misaligned. Also, please do property-n before property-names.
>>
>>> +    status = "okay";
>>> +};
>>> +
>>> +&usb_2_dwc3 {
>>> +    dr_mode = "host";
>>> +};
>>> +
>>>   &usb_2_hsphy0 {
>>>       vdda-pll-supply = <&vreg_l5a>;
>>>       vdda18-supply = <&vreg_l7g>;
>>> @@ -729,3 +742,37 @@ wake-n-pins {
>>>           };
>>>       };
>>>   };
>>> +
>>> +&pmm8540c_gpios {
>>> +    usb2_en_state: usb2-en-state {
>>> +        pins = "gpio9";
>>> +        function = "normal";
>>> +        output-high;
>>> +        power-source = <0>;
>> No drive-strength values?
>>
>> Konrad
>
> Hi Konrad,
>
>  TBH, I didn't add the drive strength values as things worked out of the box with the current changes (may be the default value of drive strength is sufficient for us).
>
> Let me know if it is mandatory, I will add it up in the next version.
It's not, but it helps eliminate one more potential inconsistency

Konrad
>
> Regards,
> Krishna,
>
>>> +    };
>>> +};
>>> +
>>> +&pmm8540e_gpios {
>>> +    usb3_en_state: usb3-en-state {
>>> +        pins = "gpio5";
>>> +        function = "normal";
>>> +        output-high;
>>> +        power-source = <0>;
>>> +    };
>>> +};
>>> +
>>> +&pmm8540g_gpios {
>>> +    usb4_en_state: usb4-en-state {
>>> +        pins = "gpio5";
>>> +        function = "normal";
>>> +        output-high;
>>> +        power-source = <0>;
>>> +    };
>>> +
>>> +    usb5_en_state: usb5-en-state {
>>> +        pins = "gpio9";
>>> +        function = "normal";
>>> +        output-high;
>>> +        power-source = <0>;
>>> +    };
>>> +};

2023-05-04 18:25:12

by Krishna Kurapati PSSNV

[permalink] [raw]
Subject: Re: [PATCH v7 9/9] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller



On 5/2/2023 4:37 PM, Konrad Dybcio wrote:
>
>
> On 1.05.2023 16:34, Krishna Kurapati wrote:
>> There is now support for the multiport USB controller this uses so
>> enable it.
>>
>> The board only has a single port hooked up (despite it being wired up to
>> the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
>> which by default on boot is selected to mux properly. Grab the gpio
>> controlling that and ensure it stays in the right position so USB 2.0
>> continues to be routed from the external port to the SoC.
>>
>> Signed-off-by: Andrew Halaney <[email protected]>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
> same comments as patch 8
>
> Konrad

Hi Konrad,

Sure, will add a default value for drive-strength for this pinctrl node.

Hi Andrew Halaney,

I currently don't have a Ride device with me to test this change. Can
you help test this patch on SA8540-Ride including (drive-strength =
<2>;) property (which I believe is the default value).

I can test the same on SA8295-ADP and can push the next version quickly.

Regards,
Krishna,

>> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
>> index 24fa449d48a6..53d47593306e 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
>> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
>> @@ -309,6 +309,19 @@ &usb_2_qmpphy0 {
>> status = "okay";
>> };
>>
>> +&usb_2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&usb2_en_state>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_2_dwc3 {
>> + dr_mode = "host";
>> + phy-names = "usb2-port0", "usb3-port0";
>> + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
>> +};
>> +
>> &xo_board_clk {
>> clock-frequency = <38400000>;
>> };
>> @@ -401,4 +414,13 @@ wake-pins {
>> bias-pull-up;
>> };
>> };
>> +
>> + usb2_en_state: usb2-en-state {
>> + /* TS3USB221A USB2.0 mux select */
>> + pins = "gpio24";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-disable;
>> + output-low;
>> + };
>> };

2023-05-04 21:22:35

by Andrew Halaney

[permalink] [raw]
Subject: Re: [PATCH v7 9/9] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller

nit I just noticed: s/sa8540-ride/sa8540p-ride/
please during the next spin!

On Thu, May 04, 2023 at 11:33:44PM +0530, Krishna Kurapati PSSNV wrote:
>
>
> On 5/2/2023 4:37 PM, Konrad Dybcio wrote:
> >
> >
> > On 1.05.2023 16:34, Krishna Kurapati wrote:
> > > There is now support for the multiport USB controller this uses so
> > > enable it.
> > >
> > > The board only has a single port hooked up (despite it being wired up to
> > > the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
> > > which by default on boot is selected to mux properly. Grab the gpio
> > > controlling that and ensure it stays in the right position so USB 2.0
> > > continues to be routed from the external port to the SoC.
> > >
> > > Signed-off-by: Andrew Halaney <[email protected]>
> > > Signed-off-by: Krishna Kurapati <[email protected]>
> > > ---
> > same comments as patch 8
> >
> > Konrad
>
> Hi Konrad,
>
> Sure, will add a default value for drive-strength for this pinctrl node.
>
> Hi Andrew Halaney,
>
> I currently don't have a Ride device with me to test this change. Can you
> help test this patch on SA8540-Ride including (drive-strength = <2>;)
> property (which I believe is the default value).
>
> I can test the same on SA8295-ADP and can push the next version quickly.
>

The patch here for sa8540p-ride already includes the drive strength. I
did pull this on top of usb-next and it is working well for me in a
quick sanity test. Konrad's pinctrl-names/pinctrl-0 swap is purely
cosmetic of course, but for what is worth that works fine too.

I'd add my Tested-by for this patch, but it seems silly since I authored
the original :)

Also, make CHECK_DTBS=y qcom/sa8540p-ride.dtb is still reporting issues,
but other reviewers have highlighted that I believe. Just for the record
though, make sure you get those silenced!

I look forward to the next revision.

Thanks,
Andrew

> Regards,
> Krishna,
>
> > > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++
> > > 1 file changed, 22 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> > > index 24fa449d48a6..53d47593306e 100644
> > > --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> > > +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> > > @@ -309,6 +309,19 @@ &usb_2_qmpphy0 {
> > > status = "okay";
> > > };
> > > +&usb_2 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&usb2_en_state>;
> > > +
> > > + status = "okay";
> > > +};
> > > +
> > > +&usb_2_dwc3 {
> > > + dr_mode = "host";
> > > + phy-names = "usb2-port0", "usb3-port0";
> > > + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
> > > +};
> > > +
> > > &xo_board_clk {
> > > clock-frequency = <38400000>;
> > > };
> > > @@ -401,4 +414,13 @@ wake-pins {
> > > bias-pull-up;
> > > };
> > > };
> > > +
> > > + usb2_en_state: usb2-en-state {
> > > + /* TS3USB221A USB2.0 mux select */
> > > + pins = "gpio24";
> > > + function = "gpio";
> > > + drive-strength = <2>;
> > > + bias-disable;
> > > + output-low;
> > > + };
> > > };
>