From: Guanjun <[email protected]>
This two patches fix the some issues for idxd driver.
Please help to review.
Thanks,
Guanjun
Guanjun (2):
dmaengine: idxd: Protect int_handle field in hw descriptor
dmaengine: idxd: Fix the incorrect descriptions
drivers/dma/idxd/registers.h | 13 ++++++++-----
drivers/dma/idxd/submit.c | 14 +++++++-------
2 files changed, 15 insertions(+), 12 deletions(-)
--
2.39.3
From: Guanjun <[email protected]>
Fix the incorrect descriptions for the GRPCFG register.
No functional changes
Signed-off-by: Guanjun <[email protected]>
---
drivers/dma/idxd/registers.h | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h
index 7b54a3939ea1..385a162a55f2 100644
--- a/drivers/dma/idxd/registers.h
+++ b/drivers/dma/idxd/registers.h
@@ -440,12 +440,15 @@ union wqcfg {
/*
* This macro calculates the offset into the GRPCFG register
* idxd - struct idxd *
- * n - wq id
- * ofs - the index of the 32b dword for the config register
+ * n - group id
+ * ofs - the index of the 64b qword for the config register
*
- * The WQCFG register block is divided into groups per each wq. The n index
- * allows us to move to the register group that's for that particular wq.
- * Each register is 32bits. The ofs gives us the number of register to access.
+ * The GRPCFG register block is divided into three different types, that
+ * includes GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group
+ * allows us to move to the register group that's for that particular wq,
+ * engine or group flag.
+ * Each register is 64bits. And the ofs in GRPWQCFG gives us the number
+ * of register to access.
*/
#define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
(n) * GRPCFG_SIZE + sizeof(u64) * (ofs))
--
2.39.3
From: Guanjun <[email protected]>
The int_handle field in hw descriptor should also be protected
by wmb() before possibly triggering a DMA read.
Signed-off-by: Guanjun <[email protected]>
---
drivers/dma/idxd/submit.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/idxd/submit.c b/drivers/dma/idxd/submit.c
index c01db23e3333..3f922518e3a5 100644
--- a/drivers/dma/idxd/submit.c
+++ b/drivers/dma/idxd/submit.c
@@ -182,13 +182,6 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
portal = idxd_wq_portal_addr(wq);
- /*
- * The wmb() flushes writes to coherent DMA data before
- * possibly triggering a DMA read. The wmb() is necessary
- * even on UP because the recipient is a device.
- */
- wmb();
-
/*
* Pending the descriptor to the lockless list for the irq_entry
* that we designated the descriptor to.
@@ -199,6 +192,13 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
llist_add(&desc->llnode, &ie->pending_llist);
}
+ /*
+ * The wmb() flushes writes to coherent DMA data before
+ * possibly triggering a DMA read. The wmb() is necessary
+ * even on UP because the recipient is a device.
+ */
+ wmb();
+
if (wq_dedicated(wq)) {
iosubmit_cmds512(portal, desc->hw, 1);
} else {
--
2.39.3
On 10/29/23 01:00, 'Guanjun' wrote:
> From: Guanjun <[email protected]>
>
> The int_handle field in hw descriptor should also be protected
> by wmb() before possibly triggering a DMA read.
>
> Signed-off-by: Guanjun <[email protected]>
Can you please provide a Fix tag? Otherwise
Reviewed-by: Dave Jiang <[email protected]>
> ---
> drivers/dma/idxd/submit.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/dma/idxd/submit.c b/drivers/dma/idxd/submit.c
> index c01db23e3333..3f922518e3a5 100644
> --- a/drivers/dma/idxd/submit.c
> +++ b/drivers/dma/idxd/submit.c
> @@ -182,13 +182,6 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
>
> portal = idxd_wq_portal_addr(wq);
>
> - /*
> - * The wmb() flushes writes to coherent DMA data before
> - * possibly triggering a DMA read. The wmb() is necessary
> - * even on UP because the recipient is a device.
> - */
> - wmb();
> -
> /*
> * Pending the descriptor to the lockless list for the irq_entry
> * that we designated the descriptor to.
> @@ -199,6 +192,13 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
> llist_add(&desc->llnode, &ie->pending_llist);
> }
>
> + /*
> + * The wmb() flushes writes to coherent DMA data before
> + * possibly triggering a DMA read. The wmb() is necessary
> + * even on UP because the recipient is a device.
> + */
> + wmb();
> +
> if (wq_dedicated(wq)) {
> iosubmit_cmds512(portal, desc->hw, 1);
> } else {
On 10/29/23 01:00, 'Guanjun' wrote:
> From: Guanjun <[email protected]>
>
> Fix the incorrect descriptions for the GRPCFG register.
> No functional changes
>
> Signed-off-by: Guanjun <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
Thanks!
> ---
> drivers/dma/idxd/registers.h | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h
> index 7b54a3939ea1..385a162a55f2 100644
> --- a/drivers/dma/idxd/registers.h
> +++ b/drivers/dma/idxd/registers.h
> @@ -440,12 +440,15 @@ union wqcfg {
> /*
> * This macro calculates the offset into the GRPCFG register
> * idxd - struct idxd *
> - * n - wq id
> - * ofs - the index of the 32b dword for the config register
> + * n - group id
> + * ofs - the index of the 64b qword for the config register
> *
> - * The WQCFG register block is divided into groups per each wq. The n index
> - * allows us to move to the register group that's for that particular wq.
> - * Each register is 32bits. The ofs gives us the number of register to access.
> + * The GRPCFG register block is divided into three different types, that
> + * includes GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group
> + * allows us to move to the register group that's for that particular wq,
> + * engine or group flag.
> + * Each register is 64bits. And the ofs in GRPWQCFG gives us the number
> + * of register to access.
> */
> #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
> (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))
On 10/29/23 01:00, 'Guanjun' wrote:
> From: Guanjun <[email protected]>
>
> The int_handle field in hw descriptor should also be protected
> by wmb() before possibly triggering a DMA read.
>
> Signed-off-by: Guanjun <[email protected]>
As Dave said, need to add fixes tag.
Reviewed-by: Fenghua Yu <[email protected]>
Thanks.
-Fenghua Yu
Hi, Guanjun,
On 10/29/23 01:00, 'Guanjun' wrote:
> From: Guanjun <[email protected]>
>
The subject may be changed to:
dmaengine: idxd: Fix incorrect descriptions for GRPWQCFG_OFFSET
> Fix the incorrect descriptions for the GRPCFG register.
> No functional changes
>
> Signed-off-by: Guanjun <[email protected]>
> ---
> drivers/dma/idxd/registers.h | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h
> index 7b54a3939ea1..385a162a55f2 100644
> --- a/drivers/dma/idxd/registers.h
> +++ b/drivers/dma/idxd/registers.h
> @@ -440,12 +440,15 @@ union wqcfg {
> /*
> * This macro calculates the offset into the GRPCFG register
> * idxd - struct idxd *
> - * n - wq id
> - * ofs - the index of the 32b dword for the config register
> + * n - group id
> + * ofs - the index of the 64b qword for the config register
> *
> - * The WQCFG register block is divided into groups per each wq. The n index
> - * allows us to move to the register group that's for that particular wq.
> - * Each register is 32bits. The ofs gives us the number of register to access.
> + * The GRPCFG register block is divided into three different types, that
s/different types/sub-registers/
> + * includes GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group
s/that includes/which are/
> + * allows us to move to the register group that's for that particular wq,
> + * engine or group flag.
s/that particular wq, engine or group flag./that contains the three
sub-registers/
> + * Each register is 64bits. And the ofs in GRPWQCFG gives us the number
> + * of register to access.
s/the number of register to access/the offset within the GRPCFG register
to access/
> */
> #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
> (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))
Thanks.
-Fenghua