Add three overlays to disable the eth phy, rtc, and spi nor. These
overlays will be used to disable device tree nodes for components
that are optionally not populated.
Nathan Morrisson (4):
arm64: dts: ti: k3-am64-phycore-som: Add serial_flash label
arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable eth phy
arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable rtc
arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disabl spi nor
arch/arm64/boot/dts/ti/Makefile | 5 +++++
.../boot/dts/ti/k3-am64-phycore-som.dtsi | 2 +-
.../ti/k3-am6xx-phycore-disable-eth-phy.dtso | 19 +++++++++++++++++++
.../dts/ti/k3-am6xx-phycore-disable-rtc.dtso | 15 +++++++++++++++
.../ti/k3-am6xx-phycore-disable-spi-nor.dtso | 15 +++++++++++++++
5 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso
create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso
--
2.25.1
Label the spi nor as serial_flash. This allows us to disable the
flash with an overlay common to all am6xx-phycore-som boards.
Signed-off-by: Nathan Morrisson <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index 125e507966fb..ca0bbf21f7fe 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -296,7 +296,7 @@ &ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
- flash@0 {
+ serial_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
--
2.25.1
Add an overlay to disable the eth phy for all am6xx-phycore-som
boards.
Signed-off-by: Nathan Morrisson <[email protected]>
---
arch/arm64/boot/dts/ti/Makefile | 3 +++
.../ti/k3-am6xx-phycore-disable-eth-phy.dtso | 19 +++++++++++++++++++
2 files changed, 22 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 9a722c2473fb..030c47b2d7de 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -53,6 +53,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
+# Common overlays for the phyCORE-AM6* family of boards
+dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo
+
# Boards with AM65x SoC
k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \
k3-am654-base-board-rocktech-rk101-panel.dtbo \
diff --git a/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
new file mode 100644
index 000000000000..356c82bbe143
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023 PHYTEC America, LLC
+ * Author: Garrett Giordano <[email protected]>
+ *
+ * Copyright (C) 2024 PHYTEC America, LLC
+ * Author: Nathan Morrisson <[email protected]>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&cpsw3g_phy1 {
+ status = "disabled";
+};
+
+&cpsw_port1 {
+ status = "disabled";
+};
--
2.25.1
Add an overlay to disable the rtc for all am6xx-phycore-som boards.
Signed-off-by: Nathan Morrisson <[email protected]>
---
arch/arm64/boot/dts/ti/Makefile | 1 +
.../boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso | 15 +++++++++++++++
2 files changed, 16 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 030c47b2d7de..83a108eb4a3d 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -55,6 +55,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
# Common overlays for the phyCORE-AM6* family of boards
dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-rtc.dtbo
# Boards with AM65x SoC
k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso
new file mode 100644
index 000000000000..8b24191f5948
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023 PHYTEC America, LLC
+ * Author: Garrett Giordano <[email protected]>
+ *
+ * Copyright (C) 2024 PHYTEC America, LLC
+ * Author: Nathan Morrisson <[email protected]>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&i2c_som_rtc {
+ status = "disabled";
+};
--
2.25.1
Add an overlay to disable the spi nor for all am6xx-phycore-som
boards.
Signed-off-by: Nathan Morrisson <[email protected]>
---
arch/arm64/boot/dts/ti/Makefile | 1 +
.../dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso | 15 +++++++++++++++
2 files changed, 16 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 83a108eb4a3d..01e5f3a83996 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
# Common overlays for the phyCORE-AM6* family of boards
dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-rtc.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-spi-nor.dtbo
# Boards with AM65x SoC
k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso
new file mode 100644
index 000000000000..cc0cf269b6e4
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023 PHYTEC America, LLC
+ * Author: Garrett Giordano <[email protected]>
+ *
+ * Copyright (C) 2024 PHYTEC America, LLC
+ * Author: Nathan Morrisson <[email protected]>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&serial_flash {
+ status = "disabled";
+};
--
2.25.1
Hi Nathan,
Am 03.05.24 um 01:08 schrieb Nathan Morrisson:
> Add an overlay to disable the eth phy for all am6xx-phycore-som
> boards.
>
> Signed-off-by: Nathan Morrisson <[email protected]>
> ---
> arch/arm64/boot/dts/ti/Makefile | 3 +++
> .../ti/k3-am6xx-phycore-disable-eth-phy.dtso | 19 +++++++++++++++++++
> 2 files changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 9a722c2473fb..030c47b2d7de 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -53,6 +53,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
>
> +# Common overlays for the phyCORE-AM6* family of boards
> +dtb-$(CONFIG_ARCH_K3) += k3-am6xx-phycore-disable-eth-phy.dtbo
> +
Don't you want to add the entries for build time tests/CONFIG_OF_ALL_DTBS?
Regards,
Wadim
> # Boards with AM65x SoC
> k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \
> k3-am654-base-board-rocktech-rk101-panel.dtbo \
> diff --git a/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
> new file mode 100644
> index 000000000000..356c82bbe143
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
> +/*
> + * Copyright (C) 2023 PHYTEC America, LLC
> + * Author: Garrett Giordano <[email protected]>
> + *
> + * Copyright (C) 2024 PHYTEC America, LLC
> + * Author: Nathan Morrisson <[email protected]>
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +&cpsw3g_phy1 {
> + status = "disabled";
> +};
> +
> +&cpsw_port1 {
> + status = "disabled";
> +};