This series adds basic support for the StarFive JH7110 RISC-V SoC to
boot up and get a serial console. This series includes basic clock,
reset, pinctrl and uart drivers, which are necessary for booting.
It's should be noted that the reset and clock driver codes of JH7110
are partly common with those of JH7100, so the common codes are
factored out and can be reused by drivers of JH7110 and other more
SoCs from StarFive.
The JH7110 is the upgraded version of JH7100 and also the first official
released version of JH71XX series SoCs from StarFive Technology Ltd.
The VisionFive 2 boards equipped with JH7110 SoCs are launched
recently [1]. More information and support can visit RVspace wiki [2].
This series is also available at
https://github.com/hal-feng/linux/commits/visionfive2-minimal
[1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
[2] https://wiki.rvspace.org/
Emil Renner Berthing (17):
dt-bindings: riscv: Add StarFive JH7110 bindings
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
soc: sifive: l2 cache: Convert to platform driver
soc: sifive: l2 cache: Add StarFive JH71x0 support
reset: starfive: jh7100: Use 32bit I/O on 32bit registers
dt-bindings: reset: Add StarFive JH7110 reset definitions
clk: starfive: Factor out common clock driver code
dt-bindings: clock: Add StarFive JH7110 system clock definitions
dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
clk: starfive: Add StarFive JH7110 system clock driver
dt-bindings: clock: Add StarFive JH7110 always-on definitions
dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
clk: starfive: Add StarFive JH7110 always-on clock driver
RISC-V: Add initial StarFive JH7110 device tree
RISC-V: Add StarFive JH7110 VisionFive2 board device tree
Hal Feng (8):
reset: starfive: jh7100: Use regmap APIs to operate registers
reset: starfive: jh7100: Move necessary properties to device tree
reset: starfive: Rename 'reset-starfive-jh7100.c' to
'reset-starfive.c'
dt-bindings: reset: Add starfive,jh7110-reset bindings
reset: starfive: Add StarFive JH7110 SoC support
clk: starfive: Use regmap APIs to operate registers
RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options
Jianlong Huang (5):
pinctrl: Create subdirectory for StarFive drivers
pinctrl: starfive: Rename "pinctrl-starfive" to
"pinctrl-starfive-jh7100"
dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings
pinctrl: starfive: Add StarFive JH7110 driver
.../clock/starfive,jh7110-clkgen-aon.yaml | 62 ++
.../clock/starfive,jh7110-clkgen-sys.yaml | 69 ++
.../sifive,plic-1.0.0.yaml | 1 +
.../pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
.../pinctrl/starfive,jh7110-pinctrl.yaml | 202 ++++
.../bindings/reset/starfive,jh7100-reset.yaml | 20 +
.../bindings/reset/starfive,jh7110-reset.yaml | 54 +
.../bindings/riscv/sifive-l2-cache.yaml | 4 +
.../devicetree/bindings/riscv/starfive.yaml | 3 +
.../bindings/timer/sifive,clint.yaml | 1 +
MAINTAINERS | 27 +-
arch/riscv/Kconfig.socs | 28 +-
arch/riscv/boot/dts/starfive/Makefile | 3 +-
.../dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
arch/riscv/boot/dts/starfive/jh7100.dtsi | 3 +
.../jh7110-starfive-visionfive-v2.dts | 91 ++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++
arch/riscv/configs/defconfig | 1 +
drivers/clk/starfive/Kconfig | 29 +-
drivers/clk/starfive/Makefile | 6 +-
.../clk/starfive/clk-starfive-jh7100-audio.c | 138 +--
drivers/clk/starfive/clk-starfive-jh7100.c | 836 +++++-----------
drivers/clk/starfive/clk-starfive-jh7100.h | 112 ---
.../clk/starfive/clk-starfive-jh7110-aon.c | 161 +++
.../clk/starfive/clk-starfive-jh7110-sys.c | 648 ++++++++++++
drivers/clk/starfive/clk-starfive.c | 349 +++++++
drivers/clk/starfive/clk-starfive.h | 112 +++
drivers/pinctrl/Kconfig | 18 +-
drivers/pinctrl/Makefile | 2 +-
drivers/pinctrl/starfive/Kconfig | 37 +
drivers/pinctrl/starfive/Makefile | 8 +
drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 718 ++++++++++++++
drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 925 +++++++++++++++++
.../pinctrl-starfive-jh7100.c} | 10 +-
drivers/pinctrl/starfive/pinctrl-starfive.c | 539 ++++++++++
drivers/pinctrl/starfive/pinctrl-starfive.h | 131 +++
drivers/reset/Kconfig | 7 +-
drivers/reset/Makefile | 2 +-
drivers/reset/reset-starfive-jh7100.c | 173 ----
drivers/reset/reset-starfive.c | 218 ++++
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
drivers/soc/sifive/sifive_l2_cache.c | 86 +-
.../dt-bindings/clock/starfive-jh7110-aon.h | 26 +
.../dt-bindings/clock/starfive-jh7110-sys.h | 215 ++++
...l-starfive.h => pinctrl-starfive-jh7100.h} | 6 +-
.../pinctrl/pinctrl-starfive-jh7110.h | 931 ++++++++++++++++++
include/dt-bindings/reset/starfive-jh7110.h | 154 +++
48 files changed, 6604 insertions(+), 1019 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
create mode 100644 drivers/clk/starfive/clk-starfive.c
create mode 100644 drivers/clk/starfive/clk-starfive.h
create mode 100644 drivers/pinctrl/starfive/Kconfig
create mode 100644 drivers/pinctrl/starfive/Makefile
create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
rename drivers/pinctrl/{pinctrl-starfive.c => starfive/pinctrl-starfive-jh7100.c} (99%)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h
delete mode 100644 drivers/reset/reset-starfive-jh7100.c
create mode 100644 drivers/reset/reset-starfive.c
create mode 100644 include/dt-bindings/clock/starfive-jh7110-aon.h
create mode 100644 include/dt-bindings/clock/starfive-jh7110-sys.h
rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
create mode 100644 include/dt-bindings/reset/starfive-jh7110.h
--
2.17.1
From: Emil Renner Berthing <[email protected]>
This cache controller is also used on the StarFive JH7100 and JH7110
SoCs.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index ca3b9be58058..ba29ecfd3a92 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -24,6 +24,8 @@ select:
enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
+ - starfive,jh7110-ccache
required:
- compatible
@@ -35,6 +37,8 @@ properties:
- enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
+ - starfive,jh7110-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add device tree bindings for the StarFive JH7110 RISC-V SoC and the
VisionFive2 board for it.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 5b36243fd674..543be573921d 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -21,6 +21,9 @@ properties:
- items:
- const: beagle,beaglev-starlight-jh7100-r0
- const: starfive,jh7100
+ - items:
+ - const: starfive,visionfive-v2
+ - const: starfive,jh7110
additionalProperties: true
--
2.17.1
On 29/09/2022 16:31, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> This cache controller is also used on the StarFive JH7100 and JH7110
> SoCs.
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
From: Emil Renner Berthing <[email protected]>
This converts the driver to use the builtin_platform_driver_probe macro
to initialize the driver. This macro ends up calling device_initcall as
was used previously, but also allocates a platform device which gives us
access to much nicer APIs such as platform_ioremap_resource,
platform_get_irq and dev_err_probe.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
1 file changed, 40 insertions(+), 39 deletions(-)
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 59640a1d0b28..010d612f7420 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -7,9 +7,9 @@
*/
#include <linux/debugfs.h>
#include <linux/interrupt.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
#include <asm/cacheinfo.h>
#include <soc/sifive/sifive_l2_cache.h>
@@ -96,12 +96,6 @@ static void l2_config_read(void)
pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
}
-static const struct of_device_id sifive_l2_ids[] = {
- { .compatible = "sifive,fu540-c000-ccache" },
- { .compatible = "sifive,fu740-c000-ccache" },
- { /* end of table */ },
-};
-
static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
int register_sifive_l2_error_notifier(struct notifier_block *nb)
@@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
return IRQ_HANDLED;
}
-static int __init sifive_l2_init(void)
+static int __init sifive_l2_probe(struct platform_device *pdev)
{
- struct device_node *np;
- struct resource res;
- int i, rc, intr_num;
-
- np = of_find_matching_node(NULL, sifive_l2_ids);
- if (!np)
- return -ENODEV;
-
- if (of_address_to_resource(np, 0, &res))
- return -ENODEV;
-
- l2_base = ioremap(res.start, resource_size(&res));
- if (!l2_base)
- return -ENOMEM;
-
- intr_num = of_property_count_u32_elems(np, "interrupts");
- if (!intr_num) {
- pr_err("L2CACHE: no interrupts property\n");
- return -ENODEV;
- }
-
- for (i = 0; i < intr_num; i++) {
- g_irq[i] = irq_of_parse_and_map(np, i);
- rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
- if (rc) {
- pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
- return rc;
- }
+ struct device *dev = &pdev->dev;
+ int nirqs;
+ int ret;
+ int i;
+
+ l2_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(l2_base))
+ return PTR_ERR(l2_base);
+
+ nirqs = platform_irq_count(pdev);
+ if (nirqs <= 0)
+ return dev_err_probe(dev, -ENODEV, "no interrupts\n");
+
+ for (i = 0; i < nirqs; i++) {
+ g_irq[i] = platform_get_irq(pdev, i);
+ if (g_irq[i] < 0)
+ return g_irq[i];
+
+ ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
+ if (ret)
+ return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
}
l2_config_read();
@@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
#endif
return 0;
}
-device_initcall(sifive_l2_init);
+
+static const struct of_device_id sifive_l2_match[] = {
+ { .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "sifive,fu740-c000-ccache" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver sifive_l2_driver = {
+ .driver = {
+ .name = "sifive_l2_cache",
+ .of_match_table = sifive_l2_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add compatible string for the StarFive JH7110 clint.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index e64f46339079..f85e4982ad05 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -26,6 +26,7 @@ properties:
- enum:
- sifive,fu540-c000-clint
- starfive,jh7100-clint
+ - starfive,jh7110-clint
- canaan,k210-clint
- const: sifive,clint0
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add compatible string for StarFive JH7110 plic.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 92e0f8c3eff2..cef0451c3a47 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -60,6 +60,7 @@ properties:
- enum:
- sifive,fu540-c000-plic
- starfive,jh7100-plic
+ - starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
--
2.17.1
On 29/09/2022 16:31, Hal Feng wrote:
> This series is also available at
> https://github.com/hal-feng/linux/commits/visionfive2-minimal
>
> [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> [2] https://wiki.rvspace.org/
>
> Emil Renner Berthing (17):
> dt-bindings: riscv: Add StarFive JH7110 bindings
> dt-bindings: timer: Add StarFive JH7110 clint
> dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
> soc: sifive: l2 cache: Convert to platform driver
> soc: sifive: l2 cache: Add StarFive JH71x0 support
> reset: starfive: jh7100: Use 32bit I/O on 32bit registers
> dt-bindings: reset: Add StarFive JH7110 reset definitions
> clk: starfive: Factor out common clock driver code
> dt-bindings: clock: Add StarFive JH7110 system clock definitions
> dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
> clk: starfive: Add StarFive JH7110 system clock driver
> dt-bindings: clock: Add StarFive JH7110 always-on definitions
> dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
> clk: starfive: Add StarFive JH7110 always-on clock driver
> RISC-V: Add initial StarFive JH7110 device tree
> RISC-V: Add StarFive JH7110 VisionFive2 board device tree
Where is the rest of patches? Lists got only 5 of them. Anyway this is a
bit too big patchset. Split per subsystem.
Best regards,
Krzysztof
On Thu, Sep 29, 2022 at 10:32:00PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> This converts the driver to use the builtin_platform_driver_probe macro
> to initialize the driver. This macro ends up calling device_initcall as
> was used previously, but also allocates a platform device which gives us
> access to much nicer APIs such as platform_ioremap_resource,
> platform_get_irq and dev_err_probe.
You should resend the series ignoring this comment, but for v2, I think
you should pay attention to following patchset:
https://lore.kernel.org/linux-riscv/[email protected]/
Hopefully by the time you get to a v2, that patchset will have been
applied as 6.1 material..
Thanks,
Conor.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
> 1 file changed, 40 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> index 59640a1d0b28..010d612f7420 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> @@ -7,9 +7,9 @@
> */
> #include <linux/debugfs.h>
> #include <linux/interrupt.h>
> -#include <linux/of_irq.h>
> -#include <linux/of_address.h>
> -#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> #include <asm/cacheinfo.h>
> #include <soc/sifive/sifive_l2_cache.h>
>
> @@ -96,12 +96,6 @@ static void l2_config_read(void)
> pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> }
>
> -static const struct of_device_id sifive_l2_ids[] = {
> - { .compatible = "sifive,fu540-c000-ccache" },
> - { .compatible = "sifive,fu740-c000-ccache" },
> - { /* end of table */ },
> -};
> -
> static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
>
> int register_sifive_l2_error_notifier(struct notifier_block *nb)
> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
> return IRQ_HANDLED;
> }
>
> -static int __init sifive_l2_init(void)
> +static int __init sifive_l2_probe(struct platform_device *pdev)
> {
> - struct device_node *np;
> - struct resource res;
> - int i, rc, intr_num;
> -
> - np = of_find_matching_node(NULL, sifive_l2_ids);
> - if (!np)
> - return -ENODEV;
> -
> - if (of_address_to_resource(np, 0, &res))
> - return -ENODEV;
> -
> - l2_base = ioremap(res.start, resource_size(&res));
> - if (!l2_base)
> - return -ENOMEM;
> -
> - intr_num = of_property_count_u32_elems(np, "interrupts");
> - if (!intr_num) {
> - pr_err("L2CACHE: no interrupts property\n");
> - return -ENODEV;
> - }
> -
> - for (i = 0; i < intr_num; i++) {
> - g_irq[i] = irq_of_parse_and_map(np, i);
> - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> - if (rc) {
> - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> - return rc;
> - }
> + struct device *dev = &pdev->dev;
> + int nirqs;
> + int ret;
> + int i;
> +
> + l2_base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(l2_base))
> + return PTR_ERR(l2_base);
> +
> + nirqs = platform_irq_count(pdev);
> + if (nirqs <= 0)
> + return dev_err_probe(dev, -ENODEV, "no interrupts\n");
> +
> + for (i = 0; i < nirqs; i++) {
> + g_irq[i] = platform_get_irq(pdev, i);
> + if (g_irq[i] < 0)
> + return g_irq[i];
> +
> + ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> + if (ret)
> + return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
> }
>
> l2_config_read();
> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
> #endif
> return 0;
> }
> -device_initcall(sifive_l2_init);
> +
> +static const struct of_device_id sifive_l2_match[] = {
> + { .compatible = "sifive,fu540-c000-ccache" },
> + { .compatible = "sifive,fu740-c000-ccache" },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver sifive_l2_driver = {
> + .driver = {
> + .name = "sifive_l2_cache",
> + .of_match_table = sifive_l2_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> This cache controller is also used on the StarFive JH7100 and JH7110
> SoCs.
Ditto this patch, hopefully [0] will have landed as 6.1 material
before you get around to an actual v2.
Thanks,
Conor
0 - https://lore.kernel.org/linux-riscv/[email protected]/
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> index ca3b9be58058..ba29ecfd3a92 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -24,6 +24,8 @@ select:
> enum:
> - sifive,fu540-c000-ccache
> - sifive,fu740-c000-ccache
> + - starfive,jh7100-ccache
> + - starfive,jh7110-ccache
>
> required:
> - compatible
> @@ -35,6 +37,8 @@ properties:
> - enum:
> - sifive,fu540-c000-ccache
> - sifive,fu740-c000-ccache
> + - starfive,jh7100-ccache
> + - starfive,jh7110-ccache
> - const: cache
> - items:
> - const: microchip,mpfs-ccache
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
From: Emil Renner Berthing <[email protected]>
This adds support for the StarFive JH7100 and JH7110 SoCs which also
feature this SiFive cache controller.
Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/Kconfig.socs | 1 +
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
drivers/soc/sifive/sifive_l2_cache.c | 7 +++++++
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..10f68a4359f9 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,7 @@ config SOC_STARFIVE
bool "StarFive SoCs"
select PINCTRL
select RESET_CONTROLLER
+ select SIFIVE_L2
select SIFIVE_PLIC
help
This enables support for StarFive SoC platform hardware.
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 69ba6508cf2c..534669840858 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -26,7 +26,7 @@ obj-y += qcom/
obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
-obj-$(CONFIG_SOC_SIFIVE) += sifive/
+obj-y += sifive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c40d08d..776b30723c04 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE
config SIFIVE_L2
bool "Sifive L2 Cache controller"
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 010d612f7420..d6637254977f 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -10,6 +10,7 @@
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <asm/cacheinfo.h>
#include <soc/sifive/sifive_l2_cache.h>
@@ -189,6 +190,7 @@ static irqreturn_t l2_int_handler(int irq, void *device)
static int __init sifive_l2_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ unsigned long quirks = (uintptr_t)device_get_match_data(dev);
int nirqs;
int ret;
int i;
@@ -206,6 +208,9 @@ static int __init sifive_l2_probe(struct platform_device *pdev)
if (g_irq[i] < 0)
return g_irq[i];
+ if (quirks & BIT(i))
+ continue;
+
ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
if (ret)
return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
@@ -225,6 +230,8 @@ static int __init sifive_l2_probe(struct platform_device *pdev)
static const struct of_device_id sifive_l2_match[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
+ { .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) },
+ { .compatible = "starfive,jh7110-ccache" },
{ /* sentinel */ }
};
--
2.17.1
Reset registers address region is shared with clock controller
on the new StarFive JH7110 SoC. Change to use regmap framework
to allow base address sharing and preparation for JH7110 reset
support.
Signed-off-by: Hal Feng <[email protected]>
---
drivers/reset/reset-starfive-jh7100.c | 61 +++++++++++++++------------
1 file changed, 34 insertions(+), 27 deletions(-)
diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c
index a6e0945071e9..8cba62348a16 100644
--- a/drivers/reset/reset-starfive-jh7100.c
+++ b/drivers/reset/reset-starfive-jh7100.c
@@ -3,15 +3,14 @@
* Reset driver for the StarFive JH7100 SoC
*
* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
+ * Copyright (C) 2021-2022 StarFive Technology Co., Ltd.
*/
-#include <linux/bitmap.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/mod_devicetable.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/reset-controller.h>
-#include <linux/spinlock.h>
#include <dt-bindings/reset/starfive-jh7100.h>
@@ -49,9 +48,7 @@ static const u32 jh7100_reset_asserted[4] = {
struct jh7100_reset {
struct reset_controller_dev rcdev;
- /* protect registers against concurrent read-modify-write */
- spinlock_t lock;
- void __iomem *base;
+ struct regmap *regmap;
};
static inline struct jh7100_reset *
@@ -64,31 +61,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct jh7100_reset *data = jh7100_reset_from(rcdev);
- unsigned long offset = id / 32;
+ u32 offset = id / 32;
u32 mask = BIT(id % 32);
- void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u32);
- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
+ u32 reg_assert = JH7100_RESET_ASSERT0 + offset * sizeof(u32);
+ u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32);
u32 done = jh7100_reset_asserted[offset] & mask;
u32 value;
- unsigned long flags;
int ret;
if (!assert)
done ^= mask;
- spin_lock_irqsave(&data->lock, flags);
-
- value = readl(reg_assert);
if (assert)
- value |= mask;
+ ret = regmap_update_bits(data->regmap, reg_assert, mask, mask);
else
- value &= ~mask;
- writel(value, reg_assert);
+ ret = regmap_update_bits(data->regmap, reg_assert, mask, 0);
+
+ if (ret)
+ return ret;
/* if the associated clock is gated, deasserting might otherwise hang forever */
- ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
+ ret = regmap_read_poll_timeout_atomic(data->regmap,
+ reg_status,
+ value, (value & mask) == done,
+ 0, 1000);
+ if (ret)
+ dev_warn(rcdev->dev, "id:%ld bank:%d, mask:%#x assert:%#x status:%#x ret:%d\n",
+ id, offset, mask, reg_assert, reg_status, ret);
- spin_unlock_irqrestore(&data->lock, flags);
return ret;
}
@@ -120,10 +120,15 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct jh7100_reset *data = jh7100_reset_from(rcdev);
- unsigned long offset = id / 32;
+ u32 offset = id / 32;
u32 mask = BIT(id % 32);
- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
- u32 value = readl(reg_status);
+ u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32);
+ u32 value;
+ int ret;
+
+ ret = regmap_read(data->regmap, reg_status, &value);
+ if (ret)
+ return ret;
return !((value ^ jh7100_reset_asserted[offset]) & mask);
}
@@ -143,16 +148,18 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
- data->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(data->base))
- return PTR_ERR(data->base);
+ data->regmap = device_node_to_regmap(pdev->dev.of_node);
+ if (IS_ERR(data->regmap)) {
+ dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
+ PTR_ERR(data->regmap));
+ return PTR_ERR(data->regmap);
+ }
data->rcdev.ops = &jh7100_reset_ops;
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = JH7100_RSTN_END;
data->rcdev.dev = &pdev->dev;
data->rcdev.of_node = pdev->dev.of_node;
- spin_lock_init(&data->lock);
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
}
--
2.17.1
Store the necessary properties in device tree instead of .c file,
in order to apply this reset driver to other StarFive SoCs.
Signed-off-by: Hal Feng <[email protected]>
---
.../bindings/reset/starfive,jh7100-reset.yaml | 20 ++++++++
arch/riscv/boot/dts/starfive/jh7100.dtsi | 3 ++
drivers/reset/reset-starfive-jh7100.c | 50 +++++++++++++------
3 files changed, 57 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
index 300359a5e14b..3eff3f72a1ed 100644
--- a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
@@ -20,19 +20,39 @@ properties:
"#reset-cells":
const: 1
+ starfive,assert-offset:
+ description: Offset of the first ASSERT register
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ starfive,status-offset:
+ description: Offset of the first STATUS register
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ starfive,nr-resets:
+ description: Number of reset signals
+ $ref: /schemas/types.yaml#/definitions/uint32
+
required:
- compatible
- reg
- "#reset-cells"
+ - starfive,assert-offset
+ - starfive,status-offset
+ - starfive,nr-resets
additionalProperties: false
examples:
- |
+ #include <dt-bindings/reset/starfive-jh7100.h>
+
reset-controller@11840000 {
compatible = "starfive,jh7100-reset";
reg = <0x11840000 0x10000>;
#reset-cells = <1>;
+ starfive,assert-offset = <0x0>;
+ starfive,status-offset= <0x10>;
+ starfive,nr-resets = <JH7100_RSTN_END>;
};
...
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 000447482aca..904a93411add 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -145,6 +145,9 @@
compatible = "starfive,jh7100-reset";
reg = <0x0 0x11840000 0x0 0x10000>;
#reset-cells = <1>;
+ starfive,assert-offset = <0x0>;
+ starfive,status-offset= <0x10>;
+ starfive,nr-resets = <JH7100_RSTN_END>;
};
i2c0: i2c@118b0000 {
diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c
index 8cba62348a16..d3656e99ae0e 100644
--- a/drivers/reset/reset-starfive-jh7100.c
+++ b/drivers/reset/reset-starfive-jh7100.c
@@ -14,16 +14,6 @@
#include <dt-bindings/reset/starfive-jh7100.h>
-/* register offsets */
-#define JH7100_RESET_ASSERT0 0x00
-#define JH7100_RESET_ASSERT1 0x04
-#define JH7100_RESET_ASSERT2 0x08
-#define JH7100_RESET_ASSERT3 0x0c
-#define JH7100_RESET_STATUS0 0x10
-#define JH7100_RESET_STATUS1 0x14
-#define JH7100_RESET_STATUS2 0x18
-#define JH7100_RESET_STATUS3 0x1c
-
/*
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
* line 32m + n, and writing a 0 deasserts the same line.
@@ -49,6 +39,10 @@ static const u32 jh7100_reset_asserted[4] = {
struct jh7100_reset {
struct reset_controller_dev rcdev;
struct regmap *regmap;
+ u32 assert_offset;
+ u32 status_offset;
+ u32 nr_resets;
+ const u32 *asserted;
};
static inline struct jh7100_reset *
@@ -63,9 +57,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
struct jh7100_reset *data = jh7100_reset_from(rcdev);
u32 offset = id / 32;
u32 mask = BIT(id % 32);
- u32 reg_assert = JH7100_RESET_ASSERT0 + offset * sizeof(u32);
- u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32);
- u32 done = jh7100_reset_asserted[offset] & mask;
+ u32 reg_assert = data->assert_offset + offset * sizeof(u32);
+ u32 reg_status = data->status_offset + offset * sizeof(u32);
+ u32 done = data->asserted ? data->asserted[offset] & mask : 0;
u32 value;
int ret;
@@ -122,7 +116,7 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
struct jh7100_reset *data = jh7100_reset_from(rcdev);
u32 offset = id / 32;
u32 mask = BIT(id % 32);
- u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32);
+ u32 reg_status = data->status_offset + offset * sizeof(u32);
u32 value;
int ret;
@@ -130,7 +124,7 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
if (ret)
return ret;
- return !((value ^ jh7100_reset_asserted[offset]) & mask);
+ return !((value ^ data->asserted[offset]) & mask);
}
static const struct reset_control_ops jh7100_reset_ops = {
@@ -143,6 +137,7 @@ static const struct reset_control_ops jh7100_reset_ops = {
static int __init jh7100_reset_probe(struct platform_device *pdev)
{
struct jh7100_reset *data;
+ int ret;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
@@ -155,12 +150,35 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
return PTR_ERR(data->regmap);
}
+ ret = of_property_read_u32(pdev->dev.of_node, "starfive,assert-offset",
+ &data->assert_offset);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to get starfive,assert-offset: %d\n", ret);
+ return ret;
+ }
+
+ ret = of_property_read_u32(pdev->dev.of_node, "starfive,status-offset",
+ &data->status_offset);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to get starfive,status-offset: %d\n", ret);
+ return ret;
+ }
+
+ ret = of_property_read_u32(pdev->dev.of_node, "starfive,nr-resets",
+ &data->nr_resets);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to get starfive,nr-resets: %d\n", ret);
+ return ret;
+ }
+
data->rcdev.ops = &jh7100_reset_ops;
data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = JH7100_RSTN_END;
+ data->rcdev.nr_resets = data->nr_resets;
data->rcdev.dev = &pdev->dev;
data->rcdev.of_node = pdev->dev.of_node;
+ data->asserted = jh7100_reset_asserted;
+
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
}
--
2.17.1
So this reset driver can be compatible with other StarFive SoCs.
No functional change.
Signed-off-by: Hal Feng <[email protected]>
---
MAINTAINERS | 9 +--
drivers/reset/Kconfig | 6 +-
drivers/reset/Makefile | 2 +-
...set-starfive-jh7100.c => reset-starfive.c} | 68 +++++++++----------
4 files changed, 43 insertions(+), 42 deletions(-)
rename drivers/reset/{reset-starfive-jh7100.c => reset-starfive.c} (70%)
diff --git a/MAINTAINERS b/MAINTAINERS
index f5ca4aefd184..f2319a3b708b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19411,12 +19411,13 @@ F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
F: drivers/pinctrl/pinctrl-starfive.c
F: include/dt-bindings/pinctrl/pinctrl-starfive.h
-STARFIVE JH7100 RESET CONTROLLER DRIVER
+STARFIVE RESET CONTROLLER DRIVER
M: Emil Renner Berthing <[email protected]>
+M: Hal Feng <[email protected]>
S: Maintained
-F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-F: drivers/reset/reset-starfive-jh7100.c
-F: include/dt-bindings/reset/starfive-jh7100.h
+F: Documentation/devicetree/bindings/reset/starfive*
+F: drivers/reset/reset-starfive.c
+F: include/dt-bindings/reset/starfive*
STATIC BRANCH/CALL
M: Peter Zijlstra <[email protected]>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 806773e88832..8121de5ecc3c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -225,12 +225,12 @@ config RESET_SOCFPGA
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
-config RESET_STARFIVE_JH7100
- bool "StarFive JH7100 Reset Driver"
+config RESET_STARFIVE
+ bool "StarFive SoC Reset Driver"
depends on SOC_STARFIVE || COMPILE_TEST
default SOC_STARFIVE
help
- This enables the reset controller driver for the StarFive JH7100 SoC.
+ This enables the reset controller driver for the StarFive SoCs.
config RESET_SUNPLUS
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index cd5cf8e7c6a7..269268a48f56 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
-obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
+obj-$(CONFIG_RESET_STARFIVE) += reset-starfive.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive.c
similarity index 70%
rename from drivers/reset/reset-starfive-jh7100.c
rename to drivers/reset/reset-starfive.c
index d3656e99ae0e..56d07bafadd7 100644
--- a/drivers/reset/reset-starfive-jh7100.c
+++ b/drivers/reset/reset-starfive.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Reset driver for the StarFive JH7100 SoC
+ * Reset driver for the StarFive SoC
*
* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
* Copyright (C) 2021-2022 StarFive Technology Co., Ltd.
@@ -36,7 +36,7 @@ static const u32 jh7100_reset_asserted[4] = {
0,
};
-struct jh7100_reset {
+struct starfive_reset {
struct reset_controller_dev rcdev;
struct regmap *regmap;
u32 assert_offset;
@@ -45,16 +45,16 @@ struct jh7100_reset {
const u32 *asserted;
};
-static inline struct jh7100_reset *
-jh7100_reset_from(struct reset_controller_dev *rcdev)
+static inline struct starfive_reset *
+starfive_reset_from(struct reset_controller_dev *rcdev)
{
- return container_of(rcdev, struct jh7100_reset, rcdev);
+ return container_of(rcdev, struct starfive_reset, rcdev);
}
-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
+static int starfive_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
{
- struct jh7100_reset *data = jh7100_reset_from(rcdev);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
u32 offset = id / 32;
u32 mask = BIT(id % 32);
u32 reg_assert = data->assert_offset + offset * sizeof(u32);
@@ -86,34 +86,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
return ret;
}
-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- return jh7100_reset_update(rcdev, id, true);
+ return starfive_reset_update(rcdev, id, true);
}
-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- return jh7100_reset_update(rcdev, id, false);
+ return starfive_reset_update(rcdev, id, false);
}
-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
int ret;
- ret = jh7100_reset_assert(rcdev, id);
+ ret = starfive_reset_assert(rcdev, id);
if (ret)
return ret;
- return jh7100_reset_deassert(rcdev, id);
+ return starfive_reset_deassert(rcdev, id);
}
-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- struct jh7100_reset *data = jh7100_reset_from(rcdev);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
u32 offset = id / 32;
u32 mask = BIT(id % 32);
u32 reg_status = data->status_offset + offset * sizeof(u32);
@@ -127,16 +127,16 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
return !((value ^ data->asserted[offset]) & mask);
}
-static const struct reset_control_ops jh7100_reset_ops = {
- .assert = jh7100_reset_assert,
- .deassert = jh7100_reset_deassert,
- .reset = jh7100_reset_reset,
- .status = jh7100_reset_status,
+static const struct reset_control_ops starfive_reset_ops = {
+ .assert = starfive_reset_assert,
+ .deassert = starfive_reset_deassert,
+ .reset = starfive_reset_reset,
+ .status = starfive_reset_status,
};
-static int __init jh7100_reset_probe(struct platform_device *pdev)
+static int __init starfive_reset_probe(struct platform_device *pdev)
{
- struct jh7100_reset *data;
+ struct starfive_reset *data;
int ret;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
@@ -171,7 +171,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
return ret;
}
- data->rcdev.ops = &jh7100_reset_ops;
+ data->rcdev.ops = &starfive_reset_ops;
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = data->nr_resets;
data->rcdev.dev = &pdev->dev;
@@ -182,16 +182,16 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
}
-static const struct of_device_id jh7100_reset_dt_ids[] = {
+static const struct of_device_id starfive_reset_dt_ids[] = {
{ .compatible = "starfive,jh7100-reset" },
{ /* sentinel */ }
};
-static struct platform_driver jh7100_reset_driver = {
+static struct platform_driver starfive_reset_driver = {
.driver = {
- .name = "jh7100-reset",
- .of_match_table = jh7100_reset_dt_ids,
+ .name = "starfive-reset",
+ .of_match_table = starfive_reset_dt_ids,
.suppress_bind_attrs = true,
},
};
-builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);
+builtin_platform_driver_probe(starfive_reset_driver, starfive_reset_probe);
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add resets for the StarFive JH7110 reset controller.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
include/dt-bindings/reset/starfive-jh7110.h | 154 ++++++++++++++++++++
1 file changed, 154 insertions(+)
create mode 100644 include/dt-bindings/reset/starfive-jh7110.h
diff --git a/include/dt-bindings/reset/starfive-jh7110.h b/include/dt-bindings/reset/starfive-jh7110.h
new file mode 100644
index 000000000000..512bd8834efb
--- /dev/null
+++ b/include/dt-bindings/reset/starfive-jh7110.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2021-2022 Emil Renner Berthing <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+
+/* syscrg_rst */
+#define JH7110_SYSRST_JTAG2APB 0
+#define JH7110_SYSRST_SYSCON 1
+#define JH7110_SYSRST_IOMUX 2
+#define JH7110_SYSRST_BUS 3
+#define JH7110_SYSRST_DEBUG 4
+#define JH7110_SYSRST_CORE0 5
+#define JH7110_SYSRST_CORE1 6
+#define JH7110_SYSRST_CORE2 7
+#define JH7110_SYSRST_CORE3 8
+#define JH7110_SYSRST_CORE4 9
+#define JH7110_SYSRST_CORE0_ST 10
+#define JH7110_SYSRST_CORE1_ST 11
+#define JH7110_SYSRST_CORE2_ST 12
+#define JH7110_SYSRST_CORE3_ST 13
+#define JH7110_SYSRST_CORE4_ST 14
+#define JH7110_SYSRST_TRACE0 15
+#define JH7110_SYSRST_TRACE1 16
+#define JH7110_SYSRST_TRACE2 17
+#define JH7110_SYSRST_TRACE3 18
+#define JH7110_SYSRST_TRACE4 19
+#define JH7110_SYSRST_TRACE_COM 20
+#define JH7110_SYSRST_GPU_APB 21
+#define JH7110_SYSRST_GPU_DOMA 22
+#define JH7110_SYSRST_NOC_BUS_APB_BUS 23
+#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
+#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
+#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
+#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
+#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
+#define JH7110_SYSRST_NOC_BUS_DDRC 29
+#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
+#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
+
+#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
+#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33
+#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36
+#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37
+#define JH7110_SYSRST_DDR_AXI 38
+#define JH7110_SYSRST_DDR_OSC 39
+#define JH7110_SYSRST_DDR_APB 40
+#define JH7110_SYSRST_DOM_ISP_TOP_N 41
+#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42
+#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43
+#define JH7110_SYSRST_CODAJ12_AXI 44
+#define JH7110_SYSRST_CODAJ12_CORE 45
+#define JH7110_SYSRST_CODAJ12_APB 46
+#define JH7110_SYSRST_WAVE511_AXI 47
+#define JH7110_SYSRST_WAVE511_BPU 48
+#define JH7110_SYSRST_WAVE511_VCE 49
+#define JH7110_SYSRST_WAVE511_APB 50
+#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51
+#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52
+#define JH7110_SYSRST_AXIMEM0_AXI 53
+#define JH7110_SYSRST_WAVE420L_AXI 54
+#define JH7110_SYSRST_WAVE420L_BPU 55
+#define JH7110_SYSRST_WAVE420L_VCE 56
+#define JH7110_SYSRST_WAVE420L_APB 57
+#define JH7110_SYSRST_AXIMEM1_AXI 58
+#define JH7110_SYSRST_AXIMEM2_AXI 59
+#define JH7110_SYSRST_INTMEM 60
+#define JH7110_SYSRST_QSPI_AHB 61
+#define JH7110_SYSRST_QSPI_APB 62
+#define JH7110_SYSRST_QSPI_REF 63
+
+#define JH7110_SYSRST_SDIO0_AHB 64
+#define JH7110_SYSRST_SDIO1_AHB 65
+#define JH7110_SYSRST_GMAC1_AXI 66
+#define JH7110_SYSRST_GMAC1_AHB 67
+#define JH7110_SYSRST_MAILBOX 68
+#define JH7110_SYSRST_SPI0_APB 69
+#define JH7110_SYSRST_SPI1_APB 70
+#define JH7110_SYSRST_SPI2_APB 71
+#define JH7110_SYSRST_SPI3_APB 72
+#define JH7110_SYSRST_SPI4_APB 73
+#define JH7110_SYSRST_SPI5_APB 74
+#define JH7110_SYSRST_SPI6_APB 75
+#define JH7110_SYSRST_I2C0_APB 76
+#define JH7110_SYSRST_I2C1_APB 77
+#define JH7110_SYSRST_I2C2_APB 78
+#define JH7110_SYSRST_I2C3_APB 79
+#define JH7110_SYSRST_I2C4_APB 80
+#define JH7110_SYSRST_I2C5_APB 81
+#define JH7110_SYSRST_I2C6_APB 82
+#define JH7110_SYSRST_UART0_APB 83
+#define JH7110_SYSRST_UART0_CORE 84
+#define JH7110_SYSRST_UART1_APB 85
+#define JH7110_SYSRST_UART1_CORE 86
+#define JH7110_SYSRST_UART2_APB 87
+#define JH7110_SYSRST_UART2_CORE 88
+#define JH7110_SYSRST_UART3_APB 89
+#define JH7110_SYSRST_UART3_CORE 90
+#define JH7110_SYSRST_UART4_APB 91
+#define JH7110_SYSRST_UART4_CORE 92
+#define JH7110_SYSRST_UART5_APB 93
+#define JH7110_SYSRST_UART5_CORE 94
+#define JH7110_SYSRST_SPDIF_APB 95
+
+#define JH7110_SYSRST_PWMDAC_APB 96
+#define JH7110_SYSRST_PDM_DMIC 97
+#define JH7110_SYSRST_PDM_APB 98
+#define JH7110_SYSRST_I2SRX_APB 99
+#define JH7110_SYSRST_I2SRX_BCLK 100
+#define JH7110_SYSRST_I2STX0_APB 101
+#define JH7110_SYSRST_I2STX0_BCLK 102
+#define JH7110_SYSRST_I2STX1_APB 103
+#define JH7110_SYSRST_I2STX1_BCLK 104
+#define JH7110_SYSRST_TDM_AHB 105
+#define JH7110_SYSRST_TDM_CORE 106
+#define JH7110_SYSRST_TDM_APB 107
+#define JH7110_SYSRST_PWM_APB 108
+#define JH7110_SYSRST_WDT_APB 109
+#define JH7110_SYSRST_WDT_CORE 110
+#define JH7110_SYSRST_CAN0_APB 111
+#define JH7110_SYSRST_CAN0_CORE 112
+#define JH7110_SYSRST_CAN0_TIMER 113
+#define JH7110_SYSRST_CAN1_APB 114
+#define JH7110_SYSRST_CAN1_CORE 115
+#define JH7110_SYSRST_CAN1_TIMER 116
+#define JH7110_SYSRST_TIMER_APB 117
+#define JH7110_SYSRST_TIMER0 118
+#define JH7110_SYSRST_TIMER1 119
+#define JH7110_SYSRST_TIMER2 120
+#define JH7110_SYSRST_TIMER3 121
+#define JH7110_SYSRST_INT_CTRL_APB 122
+#define JH7110_SYSRST_TEMP_APB 123
+#define JH7110_SYSRST_TEMP_CORE 124
+#define JH7110_SYSRST_JTAG_CERTIFICATION 125
+
+#define JH7110_SYSRST_END 126
+
+/* aoncrg_rst */
+#define JH7110_AONRST_GMAC0_AXI 0
+#define JH7110_AONRST_GMAC0_AHB 1
+#define JH7110_AONRST_AON_IOMUX 2
+#define JH7110_AONRST_PMU_APB 3
+#define JH7110_AONRST_PMU_WKUP 4
+#define JH7110_AONRST_RTC_APB 5
+#define JH7110_AONRST_RTC_CAL 6
+#define JH7110_AONRST_RTC_32K 7
+
+#define JH7110_AONRST_END 8
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
--
2.17.1
From: Emil Renner Berthing <[email protected]>
We currently use 64bit I/O on the 32bit registers. This works because
there are an even number of assert and status registers, so they're only
ever accessed in pairs on 64bit boundaries.
There are however other reset controllers for audio and video on the
JH7100 SoC with only one status register that isn't 64bit aligned so
64bit I/O results in an unaligned access exception.
Switch to 32bit I/O in preparation for supporting these resets too.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
drivers/reset/reset-starfive-jh7100.c | 41 +++++++++++++--------------
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c
index fc44b2fb3e03..a6e0945071e9 100644
--- a/drivers/reset/reset-starfive-jh7100.c
+++ b/drivers/reset/reset-starfive-jh7100.c
@@ -7,7 +7,6 @@
#include <linux/bitmap.h>
#include <linux/io.h>
-#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
@@ -34,16 +33,16 @@
* lines don't though, so store the expected value of the status registers when
* all lines are asserted.
*/
-static const u64 jh7100_reset_asserted[2] = {
+static const u32 jh7100_reset_asserted[4] = {
/* STATUS0 */
- BIT_ULL_MASK(JH7100_RST_U74) |
- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
+ BIT(JH7100_RST_U74 % 32) |
+ BIT(JH7100_RST_VP6_DRESET % 32) |
+ BIT(JH7100_RST_VP6_BRESET % 32),
/* STATUS1 */
- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
+ BIT(JH7100_RST_HIFI4_DRESET % 32) |
+ BIT(JH7100_RST_HIFI4_BRESET % 32),
/* STATUS2 */
- BIT_ULL_MASK(JH7100_RST_E24) |
+ BIT(JH7100_RST_E24 % 32),
/* STATUS3 */
0,
};
@@ -65,12 +64,12 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct jh7100_reset *data = jh7100_reset_from(rcdev);
- unsigned long offset = BIT_ULL_WORD(id);
- u64 mask = BIT_ULL_MASK(id);
- void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
- u64 done = jh7100_reset_asserted[offset] & mask;
- u64 value;
+ unsigned long offset = id / 32;
+ u32 mask = BIT(id % 32);
+ void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u32);
+ void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
+ u32 done = jh7100_reset_asserted[offset] & mask;
+ u32 value;
unsigned long flags;
int ret;
@@ -79,15 +78,15 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
spin_lock_irqsave(&data->lock, flags);
- value = readq(reg_assert);
+ value = readl(reg_assert);
if (assert)
value |= mask;
else
value &= ~mask;
- writeq(value, reg_assert);
+ writel(value, reg_assert);
/* if the associated clock is gated, deasserting might otherwise hang forever */
- ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
+ ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
spin_unlock_irqrestore(&data->lock, flags);
return ret;
@@ -121,10 +120,10 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct jh7100_reset *data = jh7100_reset_from(rcdev);
- unsigned long offset = BIT_ULL_WORD(id);
- u64 mask = BIT_ULL_MASK(id);
- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
- u64 value = readq(reg_status);
+ unsigned long offset = id / 32;
+ u32 mask = BIT(id % 32);
+ void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
+ u32 value = readl(reg_status);
return !((value ^ jh7100_reset_asserted[offset]) & mask);
}
--
2.17.1
Add bindings for the reset controller on the JH7110 RISC-V
SoC by StarFive Technology Ltd.
Signed-off-by: Hal Feng <[email protected]>
---
.../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
new file mode 100644
index 000000000000..bb0010c200f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
+
+maintainers:
+ - Emil Renner Berthing <[email protected]>
+ - Hal Feng <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - starfive,jh7110-reset
+
+ "#reset-cells":
+ const: 1
+
+ starfive,assert-offset:
+ description: Offset of the first ASSERT register
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ starfive,status-offset:
+ description: Offset of the first STATUS register
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ starfive,nr-resets:
+ description: Number of reset signals
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - "#reset-cells"
+ - starfive,assert-offset
+ - starfive,status-offset
+ - starfive,nr-resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/starfive-jh7110.h>
+
+ syscrg_rst: reset-controller@13020000 {
+ compatible = "starfive,jh7110-reset";
+ #reset-cells = <1>;
+ starfive,assert-offset = <0x2F8>;
+ starfive,status-offset= <0x308>;
+ starfive,nr-resets = <JH7110_SYSRST_END>;
+ };
+
+...
--
2.17.1
On 29/09/2022 15:32, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> This converts the driver to use the builtin_platform_driver_probe macro
> to initialize the driver. This macro ends up calling device_initcall as
> was used previously, but also allocates a platform device which gives us
> access to much nicer APIs such as platform_ioremap_resource,
> platform_get_irq and dev_err_probe.
This is useful, but also there are other changes currently being sorted
out by Zong Li (cc'd into this message) which have already been reviewed
and are hopefully queued for the next kernel release.
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
> 1 file changed, 40 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> index 59640a1d0b28..010d612f7420 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> @@ -7,9 +7,9 @@
> */
> #include <linux/debugfs.h>
> #include <linux/interrupt.h>
> -#include <linux/of_irq.h>
> -#include <linux/of_address.h>
> -#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> #include <asm/cacheinfo.h>
> #include <soc/sifive/sifive_l2_cache.h>
>
> @@ -96,12 +96,6 @@ static void l2_config_read(void)
> pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> }
>
> -static const struct of_device_id sifive_l2_ids[] = {
> - { .compatible = "sifive,fu540-c000-ccache" },
> - { .compatible = "sifive,fu740-c000-ccache" },
> - { /* end of table */ },
> -};
> -
> static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
>
> int register_sifive_l2_error_notifier(struct notifier_block *nb)
> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
> return IRQ_HANDLED;
> }
>
> -static int __init sifive_l2_init(void)
> +static int __init sifive_l2_probe(struct platform_device *pdev)
> {
> - struct device_node *np;
> - struct resource res;
> - int i, rc, intr_num;
> -
> - np = of_find_matching_node(NULL, sifive_l2_ids);
> - if (!np)
> - return -ENODEV;
> -
> - if (of_address_to_resource(np, 0, &res))
> - return -ENODEV;
> -
> - l2_base = ioremap(res.start, resource_size(&res));
> - if (!l2_base)
> - return -ENOMEM;
> -
> - intr_num = of_property_count_u32_elems(np, "interrupts");
> - if (!intr_num) {
> - pr_err("L2CACHE: no interrupts property\n");
> - return -ENODEV;
> - }
> -
> - for (i = 0; i < intr_num; i++) {
> - g_irq[i] = irq_of_parse_and_map(np, i);
> - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> - if (rc) {
> - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> - return rc;
> - }
> + struct device *dev = &pdev->dev;
> + int nirqs;
> + int ret;
> + int i;
> +
> + l2_base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(l2_base))
> + return PTR_ERR(l2_base);
> +
> + nirqs = platform_irq_count(pdev);
> + if (nirqs <= 0)
> + return dev_err_probe(dev, -ENODEV, "no interrupts\n");
I wonder if zero irqs is an actual issue here?
> + for (i = 0; i < nirqs; i++) {
> + g_irq[i] = platform_get_irq(pdev, i);
I wonder if we need to keep g_irq[] around now? Is it going to be useful
in the future?
> + if (g_irq[i] < 0)
> + return g_irq[i];
> +
> + ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> + if (ret)
> + return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
> }
>
> l2_config_read();
> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
> #endif
> return 0;
> }
> -device_initcall(sifive_l2_init);
> +
> +static const struct of_device_id sifive_l2_match[] = {
> + { .compatible = "sifive,fu540-c000-ccache" },
> + { .compatible = "sifive,fu740-c000-ccache" },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver sifive_l2_driver = {
> + .driver = {
> + .name = "sifive_l2_cache",
> + .of_match_table = sifive_l2_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
On Thu, Sep 29, 2022 at 04:45:26PM +0200, Krzysztof Kozlowski wrote:
> On 29/09/2022 16:31, Hal Feng wrote:
>
> > This series is also available at
> > https://github.com/hal-feng/linux/commits/visionfive2-minimal
> >
> > [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> > [2] https://wiki.rvspace.org/
> >
> > Emil Renner Berthing (17):
> > dt-bindings: riscv: Add StarFive JH7110 bindings
> > dt-bindings: timer: Add StarFive JH7110 clint
> > dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> > dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
> > soc: sifive: l2 cache: Convert to platform driver
> > soc: sifive: l2 cache: Add StarFive JH71x0 support
> > reset: starfive: jh7100: Use 32bit I/O on 32bit registers
> > dt-bindings: reset: Add StarFive JH7110 reset definitions
> > clk: starfive: Factor out common clock driver code
> > dt-bindings: clock: Add StarFive JH7110 system clock definitions
> > dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
> > clk: starfive: Add StarFive JH7110 system clock driver
> > dt-bindings: clock: Add StarFive JH7110 always-on definitions
> > dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
> > clk: starfive: Add StarFive JH7110 always-on clock driver
> > RISC-V: Add initial StarFive JH7110 device tree
> > RISC-V: Add StarFive JH7110 VisionFive2 board device tree
>
> Where is the rest of patches? Lists got only 5 of them. Anyway this is a
> bit too big patchset. Split per subsystem.
They seem to be coming in over time in dribs and drabs. I assume it is
not a mailing list problem given how many lists are CCed on the mail and
the fact that they have different providers.
For v2 (or multiple v2s) please fix up your process so that this gets
sent normally and not a couple of patches every hour.
Thanks,
Conor.
From: Emil Renner Berthing <[email protected]>
The clock control registers on the StarFive SoCs work identically,
so factor out the code then drivers for different SoCs can share
it without depending on each other. No functional change.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
MAINTAINERS | 9 +-
drivers/clk/starfive/Kconfig | 7 +-
drivers/clk/starfive/Makefile | 3 +-
.../clk/starfive/clk-starfive-jh7100-audio.c | 127 +--
drivers/clk/starfive/clk-starfive-jh7100.c | 825 ++++++------------
drivers/clk/starfive/clk-starfive-jh7100.h | 112 ---
drivers/clk/starfive/clk-starfive.c | 333 +++++++
drivers/clk/starfive/clk-starfive.h | 114 +++
8 files changed, 779 insertions(+), 751 deletions(-)
delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
create mode 100644 drivers/clk/starfive/clk-starfive.c
create mode 100644 drivers/clk/starfive/clk-starfive.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f2319a3b708b..70d64d2afb0c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19396,12 +19396,13 @@ M: Ion Badulescu <[email protected]>
S: Odd Fixes
F: drivers/net/ethernet/adaptec/starfire*
-STARFIVE JH7100 CLOCK DRIVERS
+STARFIVE CLOCK DRIVERS
M: Emil Renner Berthing <[email protected]>
+M: Xingyu Wu <[email protected]>
S: Maintained
-F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
-F: drivers/clk/starfive/clk-starfive-jh7100*
-F: include/dt-bindings/clock/starfive-jh7100*.h
+F: Documentation/devicetree/bindings/clock/starfive*
+F: drivers/clk/starfive/
+F: include/dt-bindings/clock/starfive*
STARFIVE JH7100 PINCTRL DRIVER
M: Emil Renner Berthing <[email protected]>
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 003bd2d56ce7..4ff61eb941c8 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -1,8 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
+config CLK_STARFIVE
+ bool
+
config CLK_STARFIVE_JH7100
bool "StarFive JH7100 clock support"
depends on SOC_STARFIVE || COMPILE_TEST
+ select CLK_STARFIVE
default SOC_STARFIVE
help
Say yes here to support the clock controller on the StarFive JH7100
@@ -10,7 +14,8 @@ config CLK_STARFIVE_JH7100
config CLK_STARFIVE_JH7100_AUDIO
tristate "StarFive JH7100 audio clock support"
- depends on CLK_STARFIVE_JH7100
+ depends on SOC_STARFIVE || COMPILE_TEST
+ select CLK_STARFIVE
default m if SOC_STARFIVE
help
Say Y or M here to support the audio clocks on the StarFive JH7100
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 0fa8ecb9ec1c..ddd04595516f 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-# StarFive Clock
+obj-$(CONFIG_CLK_STARFIVE) += clk-starfive.o
+
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 8473a65e219b..41389cacfe03 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -16,7 +16,7 @@
#include <dt-bindings/clock/starfive-jh7100-audio.h>
-#include "clk-starfive-jh7100.h"
+#include "clk-starfive.h"
/* external clocks */
#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
@@ -28,66 +28,68 @@
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
-static const struct jh7100_clk_data jh7100_audclk_data[] = {
- JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
- JH7100_AUDCLK_ADC_MCLK,
- JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
- JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
- JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
- JH7100_AUDCLK_I2SADC_BCLK_N,
- JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
- JH7100_AUDCLK_I2SADC_BCLK),
- JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
- JH7100_AUDCLK_DAC_MCLK,
- JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
- JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
- JH7100_AUDCLK_I2S1_MCLK,
- JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
- JH7100_AUDCLK_I2S1_MCLK,
- JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
- JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
- JH7100_AUDCLK_I2S1_BCLK_N,
- JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
- JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
- JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
- JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
- JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
- JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
- JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
- JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
- JH7100_AUDCLK_VAD_INTMEM,
- JH7100_AUDCLK_AUDIO_12288),
+static const struct starfive_clk_data jh7100_audclk_data[] = {
+ STARFIVE__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
+ JH7100_AUDCLK_ADC_MCLK,
+ JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
+ STARFIVE__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
+ JH7100_AUDCLK_I2SADC_BCLK_N,
+ JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
+ JH7100_AUDCLK_I2SADC_BCLK),
+ STARFIVE_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
+ JH7100_AUDCLK_DAC_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ STARFIVE__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
+ JH7100_AUDCLK_I2S1_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ STARFIVE_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
+ JH7100_AUDCLK_I2S1_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ STARFIVE__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
+ JH7100_AUDCLK_I2S1_BCLK_N,
+ JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
+ STARFIVE_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+ STARFIVE_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
+ STARFIVE_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
+ STARFIVE_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4,
+ JH7100_AUDCLK_USB_APB),
+ STARFIVE_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3,
+ JH7100_AUDCLK_USB_APB),
+ STARFIVE__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+ STARFIVE__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
+ JH7100_AUDCLK_VAD_INTMEM,
+ JH7100_AUDCLK_AUDIO_12288),
};
static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh7100_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7100_AUDCLK_END)
@@ -98,7 +100,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d
static int jh7100_audclk_probe(struct platform_device *pdev)
{
- struct jh7100_clk_priv *priv;
+ struct starfive_clk_priv *priv;
unsigned int idx;
int ret;
@@ -117,12 +119,13 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_audclk_data[idx].name,
- .ops = starfive_jh7100_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7100_audclk_data[idx].flags,
};
- struct jh7100_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
@@ -140,7 +143,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH7100_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 691aeebc7092..014e36f17595 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -7,20 +7,15 @@
* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
*/
-#include <linux/bits.h>
#include <linux/clk-provider.h>
-#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
-#include <linux/module.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/starfive-jh7100.h>
-#include "clk-starfive-jh7100.h"
+#include "clk-starfive.h"
/* external clocks */
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
@@ -28,570 +23,257 @@
#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
-static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
- JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT),
- JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
- JH7100_CLK_OSC_AUD,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL2_OUT),
- JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
- JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL1_OUT),
- JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
- JH7100_CLK_OSC_AUD,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL2_OUT),
- JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
- JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
- JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
- JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
- JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
- JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
- JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_OSC_AUD),
- JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
- JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
- JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
- JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
- JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
- JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
- JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
- JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
- JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
- JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
- JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
- JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
- JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
- JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
- JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
- JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
- JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
- JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
- JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
- JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
- JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
- JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
- JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
- JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
- JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
- JH7100_CLK_DDROSC_DIV2,
- JH7100_CLK_DDRPLL_DIV2,
- JH7100_CLK_DDRPLL_DIV4,
- JH7100_CLK_DDRPLL_DIV8),
- JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
- JH7100_CLK_DDROSC_DIV2,
- JH7100_CLK_DDRPLL_DIV2,
- JH7100_CLK_DDRPLL_DIV4,
- JH7100_CLK_DDRPLL_DIV8),
- JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
- JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
- JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
- JH7100_CLK_CPU_AXI,
- JH7100_CLK_NNEBUS_SRC1),
- JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
- JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
- JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
- JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
- JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
- JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
- JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
- JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
- JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
- JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
- JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
- JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
- JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
- JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
- JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
- JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
- JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
- JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_USBPHY_PLLDIV25M),
- JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
- JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
- JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
- JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
- JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
- JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
- JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
- JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
- JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
- JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
- JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
- JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
- JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
- JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
- JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
- JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
- JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
- JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
- JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
- JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
- JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
- JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
- JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
- JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
- JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
- JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
- JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
- JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
- JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
- JH7100_CLK_GMAC_GTX,
- JH7100_CLK_GMAC_TX_INV,
- JH7100_CLK_GMAC_RMII_TX),
- JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
- JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
- JH7100_CLK_GMAC_GR_MII_RX,
- JH7100_CLK_GMAC_RMII_RX),
- JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
- JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
- JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
- JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
- JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
- JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
- JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
- JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
- JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
+static const struct starfive_clk_data jh7100_clk_data[] __initconst = {
+ STARFIVE__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT),
+ STARFIVE__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
+ JH7100_CLK_OSC_AUD,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
+ STARFIVE__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL1_OUT),
+ STARFIVE__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
+ JH7100_CLK_OSC_AUD,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
+ STARFIVE__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
+ STARFIVE__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
+ STARFIVE__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
+ STARFIVE__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_OSC_AUD),
+ STARFIVE__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
+ STARFIVE__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
+ STARFIVE_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
+ STARFIVE_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
+ STARFIVE_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL,
+ JH7100_CLK_OSC_SYS),
+ STARFIVE_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
+ STARFIVE_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
+ STARFIVE_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
+ STARFIVE_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
+ STARFIVE_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
+ STARFIVE_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
+ STARFIVE__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
+ STARFIVE__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
+ STARFIVE_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
+ STARFIVE_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
+ STARFIVE_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
+ STARFIVE_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
+ STARFIVE_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
+ STARFIVE__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
+ STARFIVE_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
+ STARFIVE_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
+ STARFIVE_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2,
+ JH7100_CLK_PLL1_OUT),
+ STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
+ JH7100_CLK_DDRPLL_DIV2),
+ STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
+ JH7100_CLK_DDRPLL_DIV4),
+ STARFIVE_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2,
+ JH7100_CLK_OSC_SYS),
+ STARFIVE_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
+ JH7100_CLK_DDROSC_DIV2,
+ JH7100_CLK_DDRPLL_DIV2,
+ JH7100_CLK_DDRPLL_DIV4,
+ JH7100_CLK_DDRPLL_DIV8),
+ STARFIVE_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
+ JH7100_CLK_DDROSC_DIV2,
+ JH7100_CLK_DDRPLL_DIV2,
+ JH7100_CLK_DDRPLL_DIV4,
+ JH7100_CLK_DDRPLL_DIV8),
+ STARFIVE_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
+ STARFIVE_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
+ STARFIVE__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
+ JH7100_CLK_CPU_AXI,
+ JH7100_CLK_NNEBUS_SRC1),
+ STARFIVE_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
+ STARFIVE_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
+ STARFIVE_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
+ STARFIVE_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
+ STARFIVE__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
+ STARFIVE__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
+ STARFIVE_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
+ STARFIVE__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
+ STARFIVE_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
+ STARFIVE_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
+ STARFIVE__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+ STARFIVE_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+ STARFIVE_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8,
+ JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
+ STARFIVE_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
+ STARFIVE__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
+ STARFIVE_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
+ JH7100_CLK_USBPHY_ROOTDIV),
+ STARFIVE__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_USBPHY_PLLDIV25M),
+ STARFIVE_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
+ STARFIVE_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
+ STARFIVE_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
+ STARFIVE_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
+ STARFIVE__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
+ STARFIVE_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
+ STARFIVE_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
+ STARFIVE_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
+ STARFIVE__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
+ STARFIVE_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
+ STARFIVE_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
+ STARFIVE__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
+ STARFIVE_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
+ STARFIVE_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
+ STARFIVE_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
+ STARFIVE__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
+ STARFIVE__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
+ STARFIVE_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
+ STARFIVE_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
+ STARFIVE_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
+ STARFIVE__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
+ STARFIVE_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
+ STARFIVE__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
+ STARFIVE_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+ STARFIVE__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
+ JH7100_CLK_GMAC_GTX,
+ JH7100_CLK_GMAC_TX_INV,
+ JH7100_CLK_GMAC_RMII_TX),
+ STARFIVE__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
+ STARFIVE__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
+ JH7100_CLK_GMAC_GR_MII_RX,
+ JH7100_CLK_GMAC_RMII_RX),
+ STARFIVE__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
+ STARFIVE_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
+ STARFIVE_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
+ STARFIVE_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
+ STARFIVE_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
+ STARFIVE_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
+ STARFIVE_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
+ STARFIVE_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
};
-static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
-{
- return container_of(hw, struct jh7100_clk, hw);
-}
-
-static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
-{
- return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
-}
-
-static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
-{
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
- void __iomem *reg = priv->base + 4 * clk->idx;
-
- return readl_relaxed(reg);
-}
-
-static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
-{
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
- void __iomem *reg = priv->base + 4 * clk->idx;
- unsigned long flags;
-
- spin_lock_irqsave(&priv->rmw_lock, flags);
- value |= readl_relaxed(reg) & ~mask;
- writel_relaxed(value, reg);
- spin_unlock_irqrestore(&priv->rmw_lock, flags);
-}
-
-static int jh7100_clk_enable(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
- return 0;
-}
-
-static void jh7100_clk_disable(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
-}
-
-static int jh7100_clk_is_enabled(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
-
- return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
-}
-
-static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
-
- return div ? parent_rate / div : 0;
-}
-
-static int jh7100_clk_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- unsigned long parent = req->best_parent_rate;
- unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
- unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
- unsigned long result = parent / div;
-
- /*
- * we want the result clamped by min_rate and max_rate if possible:
- * case 1: div hits the max divider value, which means it's less than
- * parent / rate, so the result is greater than rate and min_rate in
- * particular. we can't do anything about result > max_rate because the
- * divider doesn't go any further.
- * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
- * always lower or equal to rate and max_rate. however the result may
- * turn out lower than min_rate, but then the next higher rate is fine:
- * div - 1 = ceil(parent / rate) - 1 < parent / rate
- * and thus
- * min_rate <= rate < parent / (div - 1)
- */
- if (result < req->min_rate && div > 1)
- result = parent / (div - 1);
-
- req->rate = result;
- return 0;
-}
-
-static int jh7100_clk_set_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long parent_rate)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
- 1UL, (unsigned long)clk->max_div);
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
- return 0;
-}
-
-static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 reg = jh7100_clk_reg_get(clk);
- unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
- ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
-
- return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
-}
-
-static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- unsigned long parent100 = 100 * req->best_parent_rate;
- unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
- unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
- unsigned long result = parent100 / div100;
-
- /* clamp the result as in jh7100_clk_determine_rate() above */
- if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
- result = parent100 / (div100 + 1);
- if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
- result = parent100 / (div100 - 1);
-
- req->rate = result;
- return 0;
-}
-
-static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long parent_rate)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
- u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
- return 0;
-}
-
-static u8 jh7100_clk_get_parent(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = jh7100_clk_reg_get(clk);
-
- return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
-}
-
-static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
- return 0;
-}
-
-static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- return clk_mux_determine_rate_flags(hw, req, 0);
-}
-
-static int jh7100_clk_get_phase(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = jh7100_clk_reg_get(clk);
-
- return (value & JH7100_CLK_INVERT) ? 180 : 0;
-}
-
-static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value;
-
- if (degrees == 0)
- value = 0;
- else if (degrees == 180)
- value = JH7100_CLK_INVERT;
- else
- return -EINVAL;
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
-{
- static const struct debugfs_reg32 jh7100_clk_reg = {
- .name = "CTRL",
- .offset = 0,
- };
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
- struct debugfs_regset32 *regset;
-
- regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
- if (!regset)
- return;
-
- regset->regs = &jh7100_clk_reg;
- regset->nregs = 1;
- regset->base = priv->base + 4 * clk->idx;
-
- debugfs_create_regset32("registers", 0400, dentry, regset);
-}
-#else
-#define jh7100_clk_debug_init NULL
-#endif
-
-static const struct clk_ops jh7100_clk_gate_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_div_ops = {
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_fdiv_ops = {
- .recalc_rate = jh7100_clk_frac_recalc_rate,
- .determine_rate = jh7100_clk_frac_determine_rate,
- .set_rate = jh7100_clk_frac_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gdiv_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_mux_ops = {
- .determine_rate = jh7100_clk_mux_determine_rate,
- .set_parent = jh7100_clk_set_parent,
- .get_parent = jh7100_clk_get_parent,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gmux_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .determine_rate = jh7100_clk_mux_determine_rate,
- .set_parent = jh7100_clk_set_parent,
- .get_parent = jh7100_clk_get_parent,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_mdiv_ops = {
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .get_parent = jh7100_clk_get_parent,
- .set_parent = jh7100_clk_set_parent,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gmd_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .get_parent = jh7100_clk_get_parent,
- .set_parent = jh7100_clk_set_parent,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_inv_ops = {
- .get_phase = jh7100_clk_get_phase,
- .set_phase = jh7100_clk_set_phase,
- .debug_init = jh7100_clk_debug_init,
-};
-
-const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
-{
- if (max & JH7100_CLK_DIV_MASK) {
- if (max & JH7100_CLK_MUX_MASK) {
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gmd_ops;
- return &jh7100_clk_mdiv_ops;
- }
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gdiv_ops;
- if (max == JH7100_CLK_FRAC_MAX)
- return &jh7100_clk_fdiv_ops;
- return &jh7100_clk_div_ops;
- }
-
- if (max & JH7100_CLK_MUX_MASK) {
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gmux_ops;
- return &jh7100_clk_mux_ops;
- }
-
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gate_ops;
-
- return &jh7100_clk_inv_ops;
-}
-EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
-
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh7100_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7100_CLK_PLL0_OUT)
@@ -605,7 +287,7 @@ static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data
static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
{
- struct jh7100_clk_priv *priv;
+ struct starfive_clk_priv *priv;
unsigned int idx;
int ret;
@@ -639,12 +321,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_clk_data[idx].name,
- .ops = starfive_jh7100_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7100_clk_data[idx].flags,
};
- struct jh7100_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
@@ -666,7 +349,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH7100_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h
deleted file mode 100644
index f116be5740a5..000000000000
--- a/drivers/clk/starfive/clk-starfive-jh7100.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CLK_STARFIVE_JH7100_H
-#define __CLK_STARFIVE_JH7100_H
-
-#include <linux/bits.h>
-#include <linux/clk-provider.h>
-
-/* register fields */
-#define JH7100_CLK_ENABLE BIT(31)
-#define JH7100_CLK_INVERT BIT(30)
-#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
-#define JH7100_CLK_MUX_SHIFT 24
-#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
-#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
-#define JH7100_CLK_FRAC_SHIFT 8
-#define JH7100_CLK_INT_MASK GENMASK(7, 0)
-
-/* fractional divider min/max */
-#define JH7100_CLK_FRAC_MIN 100UL
-#define JH7100_CLK_FRAC_MAX 25599UL
-
-/* clock data */
-struct jh7100_clk_data {
- const char *name;
- unsigned long flags;
- u32 max;
- u8 parents[4];
-};
-
-#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
- .name = _name, \
- .flags = CLK_SET_RATE_PARENT | (_flags), \
- .max = JH7100_CLK_ENABLE, \
- .parents = { [0] = _parent }, \
-}
-
-#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = _max, \
- .parents = { [0] = _parent }, \
-}
-
-#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
- .name = _name, \
- .flags = _flags, \
- .max = JH7100_CLK_ENABLE | (_max), \
- .parents = { [0] = _parent }, \
-}
-
-#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = JH7100_CLK_FRAC_MAX, \
- .parents = { [0] = _parent }, \
-}
-
-#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
- .parents = { __VA_ARGS__ }, \
-}
-
-#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = _flags, \
- .max = JH7100_CLK_ENABLE | \
- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
- .parents = { __VA_ARGS__ }, \
-}
-
-#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
- .parents = { __VA_ARGS__ }, \
-}
-
-#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = _flags, \
- .max = JH7100_CLK_ENABLE | \
- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
- .parents = { __VA_ARGS__ }, \
-}
-
-#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
- .name = _name, \
- .flags = CLK_SET_RATE_PARENT, \
- .max = JH7100_CLK_INVERT, \
- .parents = { [0] = _parent }, \
-}
-
-struct jh7100_clk {
- struct clk_hw hw;
- unsigned int idx;
- unsigned int max_div;
-};
-
-struct jh7100_clk_priv {
- /* protect clk enable and set rate/parent from happening at the same time */
- spinlock_t rmw_lock;
- struct device *dev;
- void __iomem *base;
- struct clk_hw *pll[3];
- struct jh7100_clk reg[];
-};
-
-const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
-
-#endif
diff --git a/drivers/clk/starfive/clk-starfive.c b/drivers/clk/starfive/clk-starfive.c
new file mode 100644
index 000000000000..76e3d45b5d86
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive Clock Generator Driver
+ *
+ * Copyright (C) 2021-2022 Emil Renner Berthing <[email protected]>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/io.h>
+
+#include "clk-starfive.h"
+
+static struct starfive_clk *starfive_clk_from(struct clk_hw *hw)
+{
+ return container_of(hw, struct starfive_clk, hw);
+}
+
+static struct starfive_clk_priv *starfive_priv_from(struct starfive_clk *clk)
+{
+ return container_of(clk, struct starfive_clk_priv, reg[clk->idx]);
+}
+
+static u32 starfive_clk_reg_get(struct starfive_clk *clk)
+{
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ void __iomem *reg = priv->base + 4 * clk->idx;
+
+ return readl_relaxed(reg);
+}
+
+static void starfive_clk_reg_rmw(struct starfive_clk *clk, u32 mask, u32 value)
+{
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ void __iomem *reg = priv->base + 4 * clk->idx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->rmw_lock, flags);
+ value |= readl_relaxed(reg) & ~mask;
+ writel_relaxed(value, reg);
+ spin_unlock_irqrestore(&priv->rmw_lock, flags);
+}
+
+static int starfive_clk_enable(struct clk_hw *hw)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE);
+ return 0;
+}
+
+static void starfive_clk_disable(struct clk_hw *hw)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, 0);
+}
+
+static int starfive_clk_is_enabled(struct clk_hw *hw)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+
+ return !!(starfive_clk_reg_get(clk) & STARFIVE_CLK_ENABLE);
+}
+
+static unsigned long starfive_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 div = starfive_clk_reg_get(clk) & STARFIVE_CLK_DIV_MASK;
+
+ return div ? parent_rate / div : 0;
+}
+
+static int starfive_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ unsigned long parent = req->best_parent_rate;
+ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+ unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
+ unsigned long result = parent / div;
+
+ /*
+ * we want the result clamped by min_rate and max_rate if possible:
+ * case 1: div hits the max divider value, which means it's less than
+ * parent / rate, so the result is greater than rate and min_rate in
+ * particular. we can't do anything about result > max_rate because the
+ * divider doesn't go any further.
+ * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
+ * always lower or equal to rate and max_rate. however the result may
+ * turn out lower than min_rate, but then the next higher rate is fine:
+ * div - 1 = ceil(parent / rate) - 1 < parent / rate
+ * and thus
+ * min_rate <= rate < parent / (div - 1)
+ */
+ if (result < req->min_rate && div > 1)
+ result = parent / (div - 1);
+
+ req->rate = result;
+ return 0;
+}
+
+static int starfive_clk_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
+ 1UL, (unsigned long)clk->max_div);
+
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, div);
+ return 0;
+}
+
+static unsigned long starfive_clk_frac_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 reg = starfive_clk_reg_get(clk);
+ unsigned long div100 = 100 * (reg & STARFIVE_CLK_INT_MASK) +
+ ((reg & STARFIVE_CLK_FRAC_MASK) >> STARFIVE_CLK_FRAC_SHIFT);
+
+ return (div100 >= STARFIVE_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
+}
+
+static int starfive_clk_frac_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ unsigned long parent100 = 100 * req->best_parent_rate;
+ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+ unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
+ STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
+ unsigned long result = parent100 / div100;
+
+ /* clamp the result as in starfive_clk_determine_rate() above */
+ if (result > req->max_rate && div100 < STARFIVE_CLK_FRAC_MAX)
+ result = parent100 / (div100 + 1);
+ if (result < req->min_rate && div100 > STARFIVE_CLK_FRAC_MIN)
+ result = parent100 / (div100 - 1);
+
+ req->rate = result;
+ return 0;
+}
+
+static int starfive_clk_frac_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
+ STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
+ u32 value = ((div100 % 100) << STARFIVE_CLK_FRAC_SHIFT) | (div100 / 100);
+
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, value);
+ return 0;
+}
+
+static u8 starfive_clk_get_parent(struct clk_hw *hw)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 value = starfive_clk_reg_get(clk);
+
+ return (value & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT;
+}
+
+static int starfive_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 value = (u32)index << STARFIVE_CLK_MUX_SHIFT;
+
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_MUX_MASK, value);
+ return 0;
+}
+
+static int starfive_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ return clk_mux_determine_rate_flags(hw, req, 0);
+}
+
+static int starfive_clk_get_phase(struct clk_hw *hw)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 value = starfive_clk_reg_get(clk);
+
+ return (value & STARFIVE_CLK_INVERT) ? 180 : 0;
+}
+
+static int starfive_clk_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 value;
+
+ if (degrees == 0)
+ value = 0;
+ else if (degrees == 180)
+ value = STARFIVE_CLK_INVERT;
+ else
+ return -EINVAL;
+
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_INVERT, value);
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ static const struct debugfs_reg32 starfive_clk_reg = {
+ .name = "CTRL",
+ .offset = 0,
+ };
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ struct debugfs_regset32 *regset;
+
+ regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
+ if (!regset)
+ return;
+
+ regset->regs = &starfive_clk_reg;
+ regset->nregs = 1;
+ regset->base = priv->base + 4 * clk->idx;
+
+ debugfs_create_regset32("registers", 0400, dentry, regset);
+}
+#else
+#define starfive_clk_debug_init NULL
+#endif
+
+static const struct clk_ops starfive_clk_gate_ops = {
+ .enable = starfive_clk_enable,
+ .disable = starfive_clk_disable,
+ .is_enabled = starfive_clk_is_enabled,
+ .debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_div_ops = {
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_fdiv_ops = {
+ .recalc_rate = starfive_clk_frac_recalc_rate,
+ .determine_rate = starfive_clk_frac_determine_rate,
+ .set_rate = starfive_clk_frac_set_rate,
+ .debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_gdiv_ops = {
+ .enable = starfive_clk_enable,
+ .disable = starfive_clk_disable,
+ .is_enabled = starfive_clk_is_enabled,
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_mux_ops = {
+ .determine_rate = starfive_clk_mux_determine_rate,
+ .set_parent = starfive_clk_set_parent,
+ .get_parent = starfive_clk_get_parent,
+ .debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_gmux_ops = {
+ .enable = starfive_clk_enable,
+ .disable = starfive_clk_disable,
+ .is_enabled = starfive_clk_is_enabled,
+ .determine_rate = starfive_clk_mux_determine_rate,
+ .set_parent = starfive_clk_set_parent,
+ .get_parent = starfive_clk_get_parent,
+ .debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_mdiv_ops = {
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .get_parent = starfive_clk_get_parent,
+ .set_parent = starfive_clk_set_parent,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_gmd_ops = {
+ .enable = starfive_clk_enable,
+ .disable = starfive_clk_disable,
+ .is_enabled = starfive_clk_is_enabled,
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .get_parent = starfive_clk_get_parent,
+ .set_parent = starfive_clk_set_parent,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_inv_ops = {
+ .get_phase = starfive_clk_get_phase,
+ .set_phase = starfive_clk_set_phase,
+ .debug_init = starfive_clk_debug_init,
+};
+
+const struct clk_ops *starfive_clk_ops(u32 max)
+{
+ if (max & STARFIVE_CLK_DIV_MASK) {
+ if (max & STARFIVE_CLK_MUX_MASK) {
+ if (max & STARFIVE_CLK_ENABLE)
+ return &starfive_clk_gmd_ops;
+ return &starfive_clk_mdiv_ops;
+ }
+ if (max & STARFIVE_CLK_ENABLE)
+ return &starfive_clk_gdiv_ops;
+ if (max == STARFIVE_CLK_FRAC_MAX)
+ return &starfive_clk_fdiv_ops;
+ return &starfive_clk_div_ops;
+ }
+
+ if (max & STARFIVE_CLK_MUX_MASK) {
+ if (max & STARFIVE_CLK_ENABLE)
+ return &starfive_clk_gmux_ops;
+ return &starfive_clk_mux_ops;
+ }
+
+ if (max & STARFIVE_CLK_ENABLE)
+ return &starfive_clk_gate_ops;
+
+ return &starfive_clk_inv_ops;
+}
+EXPORT_SYMBOL_GPL(starfive_clk_ops);
diff --git a/drivers/clk/starfive/clk-starfive.h b/drivers/clk/starfive/clk-starfive.h
new file mode 100644
index 000000000000..6b05cf1bfbb6
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CLK_STARFIVE_H
+#define __CLK_STARFIVE_H
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+
+/* register fields */
+#define STARFIVE_CLK_ENABLE BIT(31)
+#define STARFIVE_CLK_INVERT BIT(30)
+#define STARFIVE_CLK_MUX_MASK GENMASK(27, 24)
+#define STARFIVE_CLK_MUX_SHIFT 24
+#define STARFIVE_CLK_DIV_MASK GENMASK(23, 0)
+#define STARFIVE_CLK_FRAC_MASK GENMASK(15, 8)
+#define STARFIVE_CLK_FRAC_SHIFT 8
+#define STARFIVE_CLK_INT_MASK GENMASK(7, 0)
+
+/* fractional divider min/max */
+#define STARFIVE_CLK_FRAC_MIN 100UL
+#define STARFIVE_CLK_FRAC_MAX 25599UL
+
+/* clock data */
+struct starfive_clk_data {
+ const char *name;
+ unsigned long flags;
+ u32 max;
+ u8 parents[4];
+};
+
+#define STARFIVE_GATE(_idx, _name, _flags, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = CLK_SET_RATE_PARENT | (_flags), \
+ .max = STARFIVE_CLK_ENABLE, \
+ .parents = { [0] = _parent }, \
+}
+
+#define STARFIVE__DIV(_idx, _name, _max, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = _max, \
+ .parents = { [0] = _parent }, \
+}
+
+#define STARFIVE_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = STARFIVE_CLK_ENABLE | (_max), \
+ .parents = { [0] = _parent }, \
+}
+
+#define STARFIVE_FDIV(_idx, _name, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = STARFIVE_CLK_FRAC_MAX, \
+ .parents = { [0] = _parent }, \
+}
+
+#define STARFIVE__MUX(_idx, _name, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = ((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT, \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define STARFIVE_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = STARFIVE_CLK_ENABLE | \
+ (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define STARFIVE_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define STARFIVE__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = STARFIVE_CLK_ENABLE | \
+ (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define STARFIVE__INV(_idx, _name, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = CLK_SET_RATE_PARENT, \
+ .max = STARFIVE_CLK_INVERT, \
+ .parents = { [0] = _parent }, \
+}
+
+struct starfive_clk {
+ struct clk_hw hw;
+ unsigned int idx;
+ unsigned int max_div;
+};
+
+struct starfive_clk_priv {
+ /* protect clk enable and set rate/parent from happening at the same time */
+ spinlock_t rmw_lock;
+ struct device *dev;
+ void __iomem *base;
+ struct clk_hw *pll[3];
+ struct starfive_clk reg[];
+};
+
+const struct clk_ops *starfive_clk_ops(u32 max);
+
+#endif
--
2.17.1
Make the driver be compatible with StarFive JH7110 SoC.
Note that the register base address of clock controller is the
same with the reset controller one. So we store the property
'reg' in the parent node of node 'reset-controller' and use
syscon APIs to get regmap structure.
Signed-off-by: Hal Feng <[email protected]>
---
drivers/reset/reset-starfive.c | 35 +++++++++++++++++++++++++++-------
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/reset/reset-starfive.c b/drivers/reset/reset-starfive.c
index 56d07bafadd7..a953fed711fd 100644
--- a/drivers/reset/reset-starfive.c
+++ b/drivers/reset/reset-starfive.c
@@ -8,7 +8,7 @@
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/platform_device.h>
+#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -134,7 +134,7 @@ static const struct reset_control_ops starfive_reset_ops = {
.status = starfive_reset_status,
};
-static int __init starfive_reset_probe(struct platform_device *pdev)
+static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
{
struct starfive_reset *data;
int ret;
@@ -145,9 +145,12 @@ static int __init starfive_reset_probe(struct platform_device *pdev)
data->regmap = device_node_to_regmap(pdev->dev.of_node);
if (IS_ERR(data->regmap)) {
- dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
- PTR_ERR(data->regmap));
- return PTR_ERR(data->regmap);
+ data->regmap = syscon_node_to_regmap(pdev->dev.of_node->parent);
+ if (IS_ERR(data->regmap)) {
+ dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
+ PTR_ERR(data->regmap));
+ return PTR_ERR(data->regmap);
+ }
}
ret = of_property_read_u32(pdev->dev.of_node, "starfive,assert-offset",
@@ -177,16 +180,34 @@ static int __init starfive_reset_probe(struct platform_device *pdev)
data->rcdev.dev = &pdev->dev;
data->rcdev.of_node = pdev->dev.of_node;
- data->asserted = jh7100_reset_asserted;
+ data->asserted = asserted;
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
}
static const struct of_device_id starfive_reset_dt_ids[] = {
- { .compatible = "starfive,jh7100-reset" },
+ {
+ .compatible = "starfive,jh7100-reset",
+ .data = jh7100_reset_asserted,
+ },
+ {
+ .compatible = "starfive,jh7110-reset",
+ .data = NULL,
+ },
{ /* sentinel */ }
};
+static int __init starfive_reset_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+
+ match = of_match_device(starfive_reset_dt_ids, &pdev->dev);
+ if (!match)
+ return -EINVAL;
+
+ return reset_starfive_register(pdev, (u32 *)(match->data));
+}
+
static struct platform_driver starfive_reset_driver = {
.driver = {
.name = "starfive-reset",
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add all clock outputs for the StarFive JH7110 system clock generator.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../dt-bindings/clock/starfive-jh7110-sys.h | 215 ++++++++++++++++++
1 file changed, 215 insertions(+)
create mode 100644 include/dt-bindings/clock/starfive-jh7110-sys.h
diff --git a/include/dt-bindings/clock/starfive-jh7110-sys.h b/include/dt-bindings/clock/starfive-jh7110-sys.h
new file mode 100644
index 000000000000..d1186abd732b
--- /dev/null
+++ b/include/dt-bindings/clock/starfive-jh7110-sys.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright 2022 Emil Renner Berthing <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__
+
+#define JH7110_SYSCLK_CPU_ROOT 0
+#define JH7110_SYSCLK_CPU_CORE 1
+#define JH7110_SYSCLK_CPU_BUS 2
+#define JH7110_SYSCLK_GPU_ROOT 3
+#define JH7110_SYSCLK_PERH_ROOT 4
+#define JH7110_SYSCLK_BUS_ROOT 5
+#define JH7110_SYSCLK_NOCSTG_BUS 6
+#define JH7110_SYSCLK_AXI_CFG0 7
+#define JH7110_SYSCLK_STG_AXIAHB 8
+#define JH7110_SYSCLK_AHB0 9
+#define JH7110_SYSCLK_AHB1 10
+#define JH7110_SYSCLK_APB_BUS_FUNC 11
+#define JH7110_SYSCLK_APB0 12
+#define JH7110_SYSCLK_PLL0_DIV2 13
+#define JH7110_SYSCLK_PLL1_DIV2 14
+#define JH7110_SYSCLK_PLL2_DIV2 15
+#define JH7110_SYSCLK_AUDIO_ROOT 16
+#define JH7110_SYSCLK_MCLK_INNER 17
+#define JH7110_SYSCLK_MCLK 18
+#define JH7110_SYSCLK_MCLK_OUT 19
+#define JH7110_SYSCLK_ISP_2X 20
+#define JH7110_SYSCLK_ISP_AXI 21
+#define JH7110_SYSCLK_GCLK0 22
+#define JH7110_SYSCLK_GCLK1 23
+#define JH7110_SYSCLK_GCLK2 24
+#define JH7110_SYSCLK_CORE 25
+#define JH7110_SYSCLK_CORE1 26
+#define JH7110_SYSCLK_CORE2 27
+#define JH7110_SYSCLK_CORE3 28
+#define JH7110_SYSCLK_CORE4 29
+#define JH7110_SYSCLK_DEBUG 30
+#define JH7110_SYSCLK_RTC_TOGGLE 31
+#define JH7110_SYSCLK_TRACE0 32
+#define JH7110_SYSCLK_TRACE1 33
+#define JH7110_SYSCLK_TRACE2 34
+#define JH7110_SYSCLK_TRACE3 35
+#define JH7110_SYSCLK_TRACE4 36
+#define JH7110_SYSCLK_TRACE_COM 37
+#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
+#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
+#define JH7110_SYSCLK_OSC_DIV2 40
+#define JH7110_SYSCLK_PLL1_DIV4 41
+#define JH7110_SYSCLK_PLL1_DIV8 42
+#define JH7110_SYSCLK_DDR_BUS 43
+#define JH7110_SYSCLK_DDR_AXI 44
+#define JH7110_SYSCLK_GPU_CORE 45
+#define JH7110_SYSCLK_GPU_CORE_CLK 46
+#define JH7110_SYSCLK_GPU_SYS_CLK 47
+#define JH7110_SYSCLK_GPU_APB 48
+#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
+#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
+#define JH7110_SYSCLK_ISP_TOP_ISPCORE_2X 51
+#define JH7110_SYSCLK_ISP_TOP_ISP_AXI 52
+#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
+#define JH7110_SYSCLK_HIFI4_CORE 54
+#define JH7110_SYSCLK_HIFI4_AXI 55
+#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56
+#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57
+#define JH7110_SYSCLK_VOUT_SRC 58
+#define JH7110_SYSCLK_VOUT_AXI 59
+#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
+#define JH7110_SYSCLK_VOUT_TOP_VOUT_AHB 61
+#define JH7110_SYSCLK_VOUT_TOP_VOUT_AXI 62
+#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63
+#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64
+#define JH7110_SYSCLK_JPEGC_AXI 65
+#define JH7110_SYSCLK_CODAJ12_AXI 66
+#define JH7110_SYSCLK_CODAJ12_CORE 67
+#define JH7110_SYSCLK_CODAJ12_APB 68
+#define JH7110_SYSCLK_VDEC_AXI 69
+#define JH7110_SYSCLK_WAVE511_AXI 70
+#define JH7110_SYSCLK_WAVE511_BPU 71
+#define JH7110_SYSCLK_WAVE511_VCE 72
+#define JH7110_SYSCLK_WAVE511_APB 73
+#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74
+#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75
+#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
+#define JH7110_SYSCLK_VENC_AXI 77
+#define JH7110_SYSCLK_WAVE420L_AXI 78
+#define JH7110_SYSCLK_WAVE420L_BPU 79
+#define JH7110_SYSCLK_WAVE420L_VCE 80
+#define JH7110_SYSCLK_WAVE420L_APB 81
+#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84
+#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85
+#define JH7110_SYSCLK_AXIMEM2_128B_AXI 86
+#define JH7110_SYSCLK_QSPI_AHB 87
+#define JH7110_SYSCLK_QSPI_APB 88
+#define JH7110_SYSCLK_QSPI_REF_SRC 89
+#define JH7110_SYSCLK_QSPI_REF 90
+#define JH7110_SYSCLK_SDIO0_AHB 91
+#define JH7110_SYSCLK_SDIO1_AHB 92
+#define JH7110_SYSCLK_SDIO0_SDCARD 93
+#define JH7110_SYSCLK_SDIO1_SDCARD 94
+#define JH7110_SYSCLK_USB_125M 95
+#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
+#define JH7110_SYSCLK_GMAC1_AHB 97
+#define JH7110_SYSCLK_GMAC1_AXI 98
+#define JH7110_SYSCLK_GMAC_SRC 99
+#define JH7110_SYSCLK_GMAC1_GTXCLK 100
+#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
+#define JH7110_SYSCLK_GMAC1_PTP 102
+#define JH7110_SYSCLK_GMAC1_RX 103
+#define JH7110_SYSCLK_GMAC1_RX_INV 104
+#define JH7110_SYSCLK_GMAC1_TX 105
+#define JH7110_SYSCLK_GMAC1_TX_INV 106
+#define JH7110_SYSCLK_GMAC1_GTXC 107
+#define JH7110_SYSCLK_GMAC0_GTXCLK 108
+#define JH7110_SYSCLK_GMAC0_PTP 109
+#define JH7110_SYSCLK_GMAC_PHY 110
+#define JH7110_SYSCLK_GMAC0_GTXC 111
+#define JH7110_SYSCLK_IOMUX 112
+#define JH7110_SYSCLK_MAILBOX 113
+#define JH7110_SYSCLK_INT_CTRL_APB 114
+#define JH7110_SYSCLK_CAN0_APB 115
+#define JH7110_SYSCLK_CAN0_TIMER 116
+#define JH7110_SYSCLK_CAN0_CAN 117
+#define JH7110_SYSCLK_CAN1_APB 118
+#define JH7110_SYSCLK_CAN1_TIMER 119
+#define JH7110_SYSCLK_CAN1_CAN 120
+#define JH7110_SYSCLK_PWM_APB 121
+#define JH7110_SYSCLK_WDT_APB 122
+#define JH7110_SYSCLK_WDT_CORE 123
+#define JH7110_SYSCLK_TIMER_APB 124
+#define JH7110_SYSCLK_TIMER0 125
+#define JH7110_SYSCLK_TIMER1 126
+#define JH7110_SYSCLK_TIMER2 127
+#define JH7110_SYSCLK_TIMER3 128
+#define JH7110_SYSCLK_TEMP_APB 129
+#define JH7110_SYSCLK_TEMP_CORE 130
+#define JH7110_SYSCLK_SPI0_APB 131
+#define JH7110_SYSCLK_SPI1_APB 132
+#define JH7110_SYSCLK_SPI2_APB 133
+#define JH7110_SYSCLK_SPI3_APB 134
+#define JH7110_SYSCLK_SPI4_APB 135
+#define JH7110_SYSCLK_SPI5_APB 136
+#define JH7110_SYSCLK_SPI6_APB 137
+#define JH7110_SYSCLK_I2C0_APB 138
+#define JH7110_SYSCLK_I2C1_APB 139
+#define JH7110_SYSCLK_I2C2_APB 140
+#define JH7110_SYSCLK_I2C3_APB 141
+#define JH7110_SYSCLK_I2C4_APB 142
+#define JH7110_SYSCLK_I2C5_APB 143
+#define JH7110_SYSCLK_I2C6_APB 144
+#define JH7110_SYSCLK_UART0_APB 145
+#define JH7110_SYSCLK_UART0_CORE 146
+#define JH7110_SYSCLK_UART1_APB 147
+#define JH7110_SYSCLK_UART1_CORE 148
+#define JH7110_SYSCLK_UART2_APB 149
+#define JH7110_SYSCLK_UART2_CORE 150
+#define JH7110_SYSCLK_UART3_APB 151
+#define JH7110_SYSCLK_UART3_CORE 152
+#define JH7110_SYSCLK_UART4_APB 153
+#define JH7110_SYSCLK_UART4_CORE 154
+#define JH7110_SYSCLK_UART5_APB 155
+#define JH7110_SYSCLK_UART5_CORE 156
+#define JH7110_SYSCLK_PWMDAC_APB 157
+#define JH7110_SYSCLK_PWMDAC_CORE 158
+#define JH7110_SYSCLK_SPDIF_APB 159
+#define JH7110_SYSCLK_SPDIF_CORE 160
+#define JH7110_SYSCLK_I2STX0_APB 161
+#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
+#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
+#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
+#define JH7110_SYSCLK_I2STX0_BCLK 165
+#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
+#define JH7110_SYSCLK_I2STX0_LRCK 167
+#define JH7110_SYSCLK_I2STX1_APB 168
+#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
+#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
+#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
+#define JH7110_SYSCLK_I2STX1_BCLK 172
+#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
+#define JH7110_SYSCLK_I2STX1_LRCK 174
+#define JH7110_SYSCLK_I2SRX_APB 175
+#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
+#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
+#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
+#define JH7110_SYSCLK_I2SRX_BCLK 179
+#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
+#define JH7110_SYSCLK_I2SRX_LRCK 181
+#define JH7110_SYSCLK_PDM_DMIC 182
+#define JH7110_SYSCLK_PDM_APB 183
+#define JH7110_SYSCLK_TDM_AHB 184
+#define JH7110_SYSCLK_TDM_APB 185
+#define JH7110_SYSCLK_TDM_INTERNAL 186
+#define JH7110_SYSCLK_TDM_CLK_TDM 187
+#define JH7110_SYSCLK_TDM_CLK_TDM_N 188
+#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
+
+#define JH7110_SYSCLK_PLL0_OUT 190
+#define JH7110_SYSCLK_PLL1_OUT 191
+#define JH7110_SYSCLK_PLL2_OUT 192
+#define JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK 193
+#define JH7110_SYSCLK_U2_PCLK_MUX_PCLK 194
+#define JH7110_SYSCLK_APB_BUS 195
+#define JH7110_SYSCLK_AXI_CFG1 196
+#define JH7110_SYSCLK_APB12 197
+#define JH7110_SYSCLK_VOUT_ROOT 198
+#define JH7110_SYSCLK_VENC_ROOT 199
+#define JH7110_SYSCLK_VDEC_ROOT 200
+#define JH7110_SYSCLK_GMACUSB_ROOT 201
+
+#define JH7110_SYSCLK_END 202
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__ */
--
2.17.1
Clock registers address region is shared with reset controller
on the new StarFive JH7110 SoC. Change to use regmap framework
to allow base address sharing and preparation for JH7110 clock
support.
Signed-off-by: Hal Feng <[email protected]>
---
.../clk/starfive/clk-starfive-jh7100-audio.c | 11 ++--
drivers/clk/starfive/clk-starfive-jh7100.c | 11 ++--
drivers/clk/starfive/clk-starfive.c | 66 ++++++++++++-------
drivers/clk/starfive/clk-starfive.h | 4 +-
4 files changed, 56 insertions(+), 36 deletions(-)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 41389cacfe03..4168209d6600 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -9,6 +9,7 @@
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_device.h>
@@ -108,11 +109,13 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
- spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
- priv->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ priv->regmap = device_node_to_regmap(priv->dev->of_node);
+ if (IS_ERR(priv->regmap)) {
+ dev_err(priv->dev, "failed to get regmap (error %ld)\n",
+ PTR_ERR(priv->regmap));
+ return PTR_ERR(priv->regmap);
+ }
for (idx = 0; idx < JH7100_AUDCLK_END; idx++) {
u32 max = jh7100_audclk_data[idx].max;
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 014e36f17595..410aa6e06842 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -10,6 +10,7 @@
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
+#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
@@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
- spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
- priv->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ priv->regmap = device_node_to_regmap(priv->dev->of_node);
+ if (IS_ERR(priv->regmap)) {
+ dev_err(priv->dev, "failed to get regmap (error %ld)\n",
+ PTR_ERR(priv->regmap));
+ return PTR_ERR(priv->regmap);
+ }
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
"osc_sys", 0, 40, 1);
diff --git a/drivers/clk/starfive/clk-starfive.c b/drivers/clk/starfive/clk-starfive.c
index 76e3d45b5d86..e428476417c5 100644
--- a/drivers/clk/starfive/clk-starfive.c
+++ b/drivers/clk/starfive/clk-starfive.c
@@ -9,6 +9,9 @@
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
#include "clk-starfive.h"
@@ -25,36 +28,36 @@ static struct starfive_clk_priv *starfive_priv_from(struct starfive_clk *clk)
static u32 starfive_clk_reg_get(struct starfive_clk *clk)
{
struct starfive_clk_priv *priv = starfive_priv_from(clk);
- void __iomem *reg = priv->base + 4 * clk->idx;
+ unsigned int reg = sizeof(u32) * clk->idx;
+ unsigned int value;
+ int ret;
- return readl_relaxed(reg);
-}
-
-static void starfive_clk_reg_rmw(struct starfive_clk *clk, u32 mask, u32 value)
-{
- struct starfive_clk_priv *priv = starfive_priv_from(clk);
- void __iomem *reg = priv->base + 4 * clk->idx;
- unsigned long flags;
+ ret = regmap_read(priv->regmap, reg, &value);
+ if (ret) {
+ dev_warn(priv->dev, "Failed to read clock register: %d\n", ret);
+ value = 0;
+ }
- spin_lock_irqsave(&priv->rmw_lock, flags);
- value |= readl_relaxed(reg) & ~mask;
- writel_relaxed(value, reg);
- spin_unlock_irqrestore(&priv->rmw_lock, flags);
+ return value;
}
static int starfive_clk_enable(struct clk_hw *hw)
{
struct starfive_clk *clk = starfive_clk_from(hw);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ unsigned int reg = sizeof(u32) * clk->idx;
- starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE);
- return 0;
+ return regmap_update_bits(priv->regmap, reg,
+ STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE);
}
static void starfive_clk_disable(struct clk_hw *hw)
{
struct starfive_clk *clk = starfive_clk_from(hw);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ unsigned int reg = sizeof(u32) * clk->idx;
- starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, 0);
+ regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_ENABLE, 0);
}
static int starfive_clk_is_enabled(struct clk_hw *hw)
@@ -107,11 +110,12 @@ static int starfive_clk_set_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct starfive_clk *clk = starfive_clk_from(hw);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ unsigned int reg = sizeof(u32) * clk->idx;
unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
1UL, (unsigned long)clk->max_div);
- starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, div);
- return 0;
+ return regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_DIV_MASK, div);
}
static unsigned long starfive_clk_frac_recalc_rate(struct clk_hw *hw,
@@ -149,12 +153,13 @@ static int starfive_clk_frac_set_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct starfive_clk *clk = starfive_clk_from(hw);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ unsigned int reg = sizeof(u32) * clk->idx;
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
u32 value = ((div100 % 100) << STARFIVE_CLK_FRAC_SHIFT) | (div100 / 100);
- starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, value);
- return 0;
+ return regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_DIV_MASK, value);
}
static u8 starfive_clk_get_parent(struct clk_hw *hw)
@@ -168,10 +173,11 @@ static u8 starfive_clk_get_parent(struct clk_hw *hw)
static int starfive_clk_set_parent(struct clk_hw *hw, u8 index)
{
struct starfive_clk *clk = starfive_clk_from(hw);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ unsigned int reg = sizeof(u32) * clk->idx;
u32 value = (u32)index << STARFIVE_CLK_MUX_SHIFT;
- starfive_clk_reg_rmw(clk, STARFIVE_CLK_MUX_MASK, value);
- return 0;
+ return regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_MUX_MASK, value);
}
static int starfive_clk_mux_determine_rate(struct clk_hw *hw,
@@ -191,6 +197,8 @@ static int starfive_clk_get_phase(struct clk_hw *hw)
static int starfive_clk_set_phase(struct clk_hw *hw, int degrees)
{
struct starfive_clk *clk = starfive_clk_from(hw);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
+ unsigned int reg = sizeof(u32) * clk->idx;
u32 value;
if (degrees == 0)
@@ -200,8 +208,7 @@ static int starfive_clk_set_phase(struct clk_hw *hw, int degrees)
else
return -EINVAL;
- starfive_clk_reg_rmw(clk, STARFIVE_CLK_INVERT, value);
- return 0;
+ return regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_INVERT, value);
}
#ifdef CONFIG_DEBUG_FS
@@ -214,6 +221,7 @@ static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
struct starfive_clk *clk = starfive_clk_from(hw);
struct starfive_clk_priv *priv = starfive_priv_from(clk);
struct debugfs_regset32 *regset;
+ void __iomem *base;
regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
if (!regset)
@@ -221,7 +229,15 @@ static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
regset->regs = &starfive_clk_reg;
regset->nregs = 1;
- regset->base = priv->base + 4 * clk->idx;
+
+ base = of_iomap(priv->dev->of_node, 0);
+ if (!base) {
+ base = of_iomap(priv->dev->of_node->parent, 0);
+ if (!base)
+ return;
+ }
+
+ regset->base = base + sizeof(u32) * clk->idx;
debugfs_create_regset32("registers", 0400, dentry, regset);
}
diff --git a/drivers/clk/starfive/clk-starfive.h b/drivers/clk/starfive/clk-starfive.h
index 6b05cf1bfbb6..99cf74e8cbde 100644
--- a/drivers/clk/starfive/clk-starfive.h
+++ b/drivers/clk/starfive/clk-starfive.h
@@ -101,10 +101,8 @@ struct starfive_clk {
};
struct starfive_clk_priv {
- /* protect clk enable and set rate/parent from happening at the same time */
- spinlock_t rmw_lock;
struct device *dev;
- void __iomem *base;
+ struct regmap *regmap;
struct clk_hw *pll[3];
struct starfive_clk reg[];
};
--
2.17.1
On Thu, Sep 29, 2022 at 01:21:56PM -0500, Rob Herring wrote:
> On Fri, 30 Sep 2022 01:51:47 +0800, Hal Feng wrote:
> > Add bindings for the reset controller on the JH7110 RISC-V
> > SoC by StarFive Technology Ltd.
> >
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
> > 1 file changed, 54 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/reset/starfive,jh7110-reset.example.dts:18:18: fatal error: dt-bindings/reset/starfive-jh7110.h: No such file or directory
> 18 | #include <dt-bindings/reset/starfive-jh7110.h>
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> compilation terminated.
> make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/reset/starfive,jh7110-reset.example.dtb] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [Makefile:1420: dt_binding_check] Error 2
Looks to be because this series got moderated and came in waves. In any
case, patches 11 and 12 can be combined. Same for any other bindings and
binding headers.
Rob
On Fri, 30 Sep 2022 01:51:47 +0800, Hal Feng wrote:
> Add bindings for the reset controller on the JH7110 RISC-V
> SoC by StarFive Technology Ltd.
>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
> 1 file changed, 54 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/reset/starfive,jh7110-reset.example.dts:18:18: fatal error: dt-bindings/reset/starfive-jh7110.h: No such file or directory
18 | #include <dt-bindings/reset/starfive-jh7110.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/reset/starfive,jh7110-reset.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1420: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
> Add bindings for the reset controller on the JH7110 RISC-V
> SoC by StarFive Technology Ltd.
>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
> 1 file changed, 54 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>
> diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> new file mode 100644
> index 000000000000..bb0010c200f9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
> +
> +maintainers:
> + - Emil Renner Berthing <[email protected]>
> + - Hal Feng <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - starfive,jh7110-reset
'reg' needed? Is this a sub-block of something else?
> +
> + "#reset-cells":
> + const: 1
> +
> + starfive,assert-offset:
> + description: Offset of the first ASSERT register
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + starfive,status-offset:
> + description: Offset of the first STATUS register
> + $ref: /schemas/types.yaml#/definitions/uint32
These can't be implied from the compatible string?
> +
> + starfive,nr-resets:
> + description: Number of reset signals
> + $ref: /schemas/types.yaml#/definitions/uint32
Why do you need this? Most bindings don't. If just to validate 'resets'
args, then don't.
> +
> +required:
> + - compatible
> + - "#reset-cells"
> + - starfive,assert-offset
> + - starfive,status-offset
> + - starfive,nr-resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/reset/starfive-jh7110.h>
> +
> + syscrg_rst: reset-controller@13020000 {
> + compatible = "starfive,jh7110-reset";
> + #reset-cells = <1>;
> + starfive,assert-offset = <0x2F8>;
> + starfive,status-offset= <0x308>;
> + starfive,nr-resets = <JH7110_SYSRST_END>;
> + };
> +
> +...
> --
> 2.17.1
>
>
From: Emil Renner Berthing <[email protected]>
Add bindings for the system clock generator on the JH7110
RISC-V SoC by StarFive Technology Ltd.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../clock/starfive,jh7110-clkgen-sys.yaml | 69 +++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
new file mode 100644
index 000000000000..290b730145ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-sys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 System Clock Generator
+
+maintainers:
+ - Emil Renner Berthing <[email protected]>
+ - Xingyu Wu <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh7110-clkgen-sys
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: RMII reference clock
+ - description: RGMII RX clock
+ - description: I2S TX bit clock
+ - description: I2S TX left/right clock
+ - description: I2S RX bit clock
+ - description: I2S RX left/right clock
+ - description: TDM
+ - description: mclk
+
+ clock-names:
+ items:
+ - const: osc
+ - const: gmac1_rmii_refin
+ - const: gmac1_rgmii_rxin
+ - const: i2stx_bclk_ext
+ - const: i2stx_lrck_ext
+ - const: i2srx_bclk_ext
+ - const: i2srx_lrck_ext
+ - const: tdm_ext
+ - const: mclk_ext
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ syscrg_clk: clock-controller@13020000 {
+ compatible = "starfive,jh7110-clkgen-sys";
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ };
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add driver for the StarFive JH7110 system clock controller.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
drivers/clk/starfive/Kconfig | 9 +
drivers/clk/starfive/Makefile | 2 +
.../clk/starfive/clk-starfive-jh7110-sys.c | 648 ++++++++++++++++++
drivers/clk/starfive/clk-starfive.h | 2 +-
4 files changed, 660 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 4ff61eb941c8..c13096543a8b 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -20,3 +20,12 @@ config CLK_STARFIVE_JH7100_AUDIO
help
Say Y or M here to support the audio clocks on the StarFive JH7100
SoC.
+
+config CLK_STARFIVE_JH7110_SYS
+ bool "StarFive JH7110 system clock support"
+ depends on SOC_STARFIVE || COMPILE_TEST
+ select CLK_STARFIVE
+ default SOC_STARFIVE
+ help
+ Say yes here to support the system clock controller on the
+ StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index ddd04595516f..2bc126cc91f2 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_CLK_STARFIVE) += clk-starfive.o
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
+
+obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
new file mode 100644
index 000000000000..91ce17fae68c
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -0,0 +1,648 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 System Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive-jh7110-sys.h>
+
+#include "clk-starfive.h"
+
+/* external clocks */
+#define JH7110_SYSCLK_OSC (JH7110_SYSCLK_END + 0)
+#define JH7110_SYSCLK_GMAC1_RMII_REFIN (JH7110_SYSCLK_END + 1)
+#define JH7110_SYSCLK_GMAC1_RGMII_RXIN (JH7110_SYSCLK_END + 2)
+#define JH7110_SYSCLK_I2STX_BCLK_EXT (JH7110_SYSCLK_END + 3)
+#define JH7110_SYSCLK_I2STX_LRCK_EXT (JH7110_SYSCLK_END + 4)
+#define JH7110_SYSCLK_I2SRX_BCLK_EXT (JH7110_SYSCLK_END + 5)
+#define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6)
+#define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7)
+#define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8)
+
+static const struct starfive_clk_data jh7110_sysclk_data[] __initconst = {
+ /* root */
+ STARFIVE__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7,
+ JH7110_SYSCLK_CPU_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
+ JH7110_SYSCLK_PLL2_OUT,
+ JH7110_SYSCLK_PLL1_OUT),
+ STARFIVE_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
+ JH7110_SYSCLK_PLL0_OUT,
+ JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3,
+ JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3,
+ JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2,
+ JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_STG_AXIAHB),
+ STARFIVE__DIV(JH7110_SYSCLK_APB_BUS_FUNC, "apb_bus_func", 8,
+ JH7110_SYSCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB_BUS),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2,
+ JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2,
+ JH7110_SYSCLK_PLL1_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2,
+ JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8,
+ JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64,
+ JH7110_SYSCLK_AUDIO_ROOT),
+ STARFIVE__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
+ JH7110_SYSCLK_MCLK_INNER,
+ JH7110_SYSCLK_MCLK_EXT),
+ STARFIVE_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0,
+ JH7110_SYSCLK_MCLK_INNER),
+ STARFIVE_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
+ JH7110_SYSCLK_PLL2_OUT,
+ JH7110_SYSCLK_PLL1_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4,
+ JH7110_SYSCLK_ISP_2X),
+ STARFIVE_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62,
+ JH7110_SYSCLK_PLL0_DIV2),
+ STARFIVE_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62,
+ JH7110_SYSCLK_PLL1_DIV2),
+ STARFIVE_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62,
+ JH7110_SYSCLK_PLL2_DIV2),
+ /* cores */
+ STARFIVE_GATE(JH7110_SYSCLK_CORE, "core_clk", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE1, "core_clk1", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE2, "core_clk2", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE3, "core_clk3", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE4, "core_clk4", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_DEBUG, "debug_clk", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_BUS),
+ STARFIVE__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE0, "trace_clk0", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE1, "trace_clk1", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE2, "trace_clk2", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE3, "trace_clk3", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE4, "trace_clk4", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_CPU_BUS),
+ /* noc */
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi",
+ CLK_IS_CRITICAL,
+ JH7110_SYSCLK_CPU_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi",
+ CLK_IS_CRITICAL,
+ JH7110_SYSCLK_AXI_CFG0),
+ /* ddr */
+ STARFIVE__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2,
+ JH7110_SYSCLK_OSC),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2,
+ JH7110_SYSCLK_PLL1_DIV2),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2,
+ JH7110_SYSCLK_PLL1_DIV4),
+ STARFIVE__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
+ JH7110_SYSCLK_OSC_DIV2,
+ JH7110_SYSCLK_PLL1_DIV2,
+ JH7110_SYSCLK_PLL1_DIV4,
+ JH7110_SYSCLK_PLL1_DIV8),
+ STARFIVE_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_DDR_BUS),
+ /* gpu */
+ STARFIVE__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7,
+ JH7110_SYSCLK_GPU_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0,
+ JH7110_SYSCLK_GPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0,
+ JH7110_SYSCLK_AXI_CFG1),
+ STARFIVE_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0,
+ JH7110_SYSCLK_GPU_CORE),
+ /* isp */
+ STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_ISPCORE_2X,
+ "isp_top_ispcore_2x", 0,
+ JH7110_SYSCLK_ISP_2X),
+ STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_ISP_AXI, "isp_top_isp_axi", 0,
+ JH7110_SYSCLK_ISP_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_ISP_AXI),
+ /* hifi4 */
+ STARFIVE__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15,
+ JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2,
+ JH7110_SYSCLK_HIFI4_CORE),
+ /* axi_cfg1_dec */
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_DEC_MAIN, "axi_cfg1_dec_main",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AXI_CFG1),
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_DEC_AHB, "cfg1_dec_ahb",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AHB0),
+ /* vout */
+ STARFIVE_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0,
+ JH7110_SYSCLK_VOUT_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7,
+ JH7110_SYSCLK_VOUT_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0,
+ JH7110_SYSCLK_VOUT_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_VOUT_AHB, "vout_top_vout_ahb", 0,
+ JH7110_SYSCLK_AHB1),
+ STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_VOUT_AXI, "vout_top_vout_axi", 0,
+ JH7110_SYSCLK_VOUT_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK,
+ "vout_top_hdmitx0_mclk", 0,
+ JH7110_SYSCLK_MCLK),
+ STARFIVE__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF,
+ "vout_top_mipiphy_ref", 2,
+ JH7110_SYSCLK_OSC),
+ /* jpegc */
+ STARFIVE__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16,
+ JH7110_SYSCLK_VENC_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_AXI, "CODAJ12_axi", 0,
+ JH7110_SYSCLK_JPEGC_AXI),
+ STARFIVE_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "CODAJ12_core", 0, 16,
+ JH7110_SYSCLK_VENC_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_APB, "CODAJ12_apb", 0,
+ JH7110_SYSCLK_APB12),
+ /* vdec */
+ STARFIVE__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7,
+ JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_WAVE511_AXI, "WAVE511_axi", 0,
+ JH7110_SYSCLK_VDEC_AXI),
+ STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_BPU, "WAVE511_bpu", 0, 7,
+ JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_VCE, "WAVE511_vce", 0, 7,
+ JH7110_SYSCLK_VDEC_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_WAVE511_APB, "WAVE511_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_VDEC_JPG_ARB_JPG, "vdec_jpg_arb_jpg",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_JPEGC_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_VDEC_JPG_ARB_MAIN, "vdec_jpg_arb_main",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_VDEC_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0,
+ JH7110_SYSCLK_VDEC_AXI),
+ /* venc */
+ STARFIVE__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15,
+ JH7110_SYSCLK_VENC_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0,
+ JH7110_SYSCLK_VENC_AXI),
+ STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15,
+ JH7110_SYSCLK_VENC_ROOT),
+ STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15,
+ JH7110_SYSCLK_VENC_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0,
+ JH7110_SYSCLK_VENC_AXI),
+ /* intmem */
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV,
+ "axi_cfg0_dec_main_div", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AHB1),
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_DEC_MAIN, "axi_cfg0_dec_main",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4, "axi_cfg0_dec_hifi4",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_HIFI4_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_AXIMEM2_128B_AXI, "aximem2_128b_axi",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AXI_CFG0),
+ /* qspi */
+ STARFIVE_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AHB1),
+ STARFIVE_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB12),
+ STARFIVE__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16,
+ JH7110_SYSCLK_GMACUSB_ROOT),
+ STARFIVE_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", CLK_IGNORE_UNUSED, 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_QSPI_REF_SRC),
+ /* sdio */
+ STARFIVE_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AHB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AHB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard",
+ CLK_IGNORE_UNUSED, 15,
+ JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard",
+ CLK_IGNORE_UNUSED, 15,
+ JH7110_SYSCLK_AXI_CFG0),
+ /* stg */
+ STARFIVE__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15,
+ JH7110_SYSCLK_GMACUSB_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_NOCSTG_BUS),
+ /* gmac1 */
+ STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0,
+ JH7110_SYSCLK_AHB0),
+ STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0,
+ JH7110_SYSCLK_STG_AXIAHB),
+ STARFIVE__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7,
+ JH7110_SYSCLK_GMACUSB_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15,
+ JH7110_SYSCLK_GMACUSB_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
+ JH7110_SYSCLK_GMAC1_RMII_REFIN),
+ STARFIVE_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31,
+ JH7110_SYSCLK_GMAC_SRC),
+ STARFIVE__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
+ JH7110_SYSCLK_GMAC1_RGMII_RXIN,
+ JH7110_SYSCLK_GMAC1_RMII_RTX),
+ STARFIVE__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv",
+ JH7110_SYSCLK_GMAC1_RX),
+ STARFIVE_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", 0, 2,
+ JH7110_SYSCLK_GMAC1_GTXCLK,
+ JH7110_SYSCLK_GMAC1_RMII_RTX),
+ STARFIVE__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv",
+ JH7110_SYSCLK_GMAC1_TX),
+ STARFIVE_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0,
+ JH7110_SYSCLK_GMAC1_GTXCLK),
+ /* gmac0 */
+ STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15,
+ JH7110_SYSCLK_GMACUSB_ROOT),
+ STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31,
+ JH7110_SYSCLK_GMAC_SRC),
+ STARFIVE_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31,
+ JH7110_SYSCLK_GMAC_SRC),
+ STARFIVE__DIV(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 32,
+ JH7110_SYSCLK_GMAC0_GTXCLK),
+ /* sys misc */
+ STARFIVE_GATE(JH7110_SYSCLK_IOMUX, "iomux_pclk", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_MAILBOX, "mailbox_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB12),
+ /* can0 */
+ STARFIVE_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63,
+ JH7110_SYSCLK_PERH_ROOT),
+ /* can1 */
+ STARFIVE_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63,
+ JH7110_SYSCLK_PERH_ROOT),
+ /* pwm */
+ STARFIVE_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0,
+ JH7110_SYSCLK_APB12),
+ /* wdt */
+ STARFIVE_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_OSC),
+ /* timer */
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER0, "timer0_clk", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER1, "timer1_clk", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER2, "timer2_clk", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER3, "timer3_clk", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_OSC),
+ /* temp sensor */
+ STARFIVE_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24,
+ JH7110_SYSCLK_OSC),
+ /* spi */
+ STARFIVE_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0,
+ JH7110_SYSCLK_APB12),
+ /* i2c */
+ STARFIVE_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0,
+ JH7110_SYSCLK_APB12),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0,
+ JH7110_SYSCLK_APB12),
+ /* uart */
+ STARFIVE_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core",
+ CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0,
+ JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10,
+ JH7110_SYSCLK_PERH_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10,
+ JH7110_SYSCLK_PERH_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10,
+ JH7110_SYSCLK_PERH_ROOT),
+ /* pwmdac */
+ STARFIVE_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256,
+ JH7110_SYSCLK_AUDIO_ROOT),
+ /* spdif */
+ STARFIVE_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0,
+ JH7110_SYSCLK_MCLK),
+ /* i2stx0 */
+ STARFIVE_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32,
+ JH7110_SYSCLK_MCLK),
+ STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
+ JH7110_SYSCLK_I2STX0_BCLK_MST),
+ STARFIVE_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
+ JH7110_SYSCLK_I2STX0_BCLK_MST),
+ STARFIVE__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
+ JH7110_SYSCLK_I2STX0_BCLK_MST,
+ JH7110_SYSCLK_I2STX_BCLK_EXT),
+ STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv",
+ JH7110_SYSCLK_I2STX0_BCLK),
+ STARFIVE__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
+ JH7110_SYSCLK_I2STX0_LRCK_MST,
+ JH7110_SYSCLK_I2STX_LRCK_EXT),
+ /* i2stx1 */
+ STARFIVE_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32,
+ JH7110_SYSCLK_MCLK),
+ STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
+ JH7110_SYSCLK_I2STX1_BCLK_MST),
+ STARFIVE_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
+ JH7110_SYSCLK_I2STX1_BCLK_MST),
+ STARFIVE__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
+ JH7110_SYSCLK_I2STX1_BCLK_MST,
+ JH7110_SYSCLK_I2STX_BCLK_EXT),
+ STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv",
+ JH7110_SYSCLK_I2STX1_BCLK),
+ STARFIVE__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
+ JH7110_SYSCLK_I2STX1_LRCK_MST,
+ JH7110_SYSCLK_I2STX_LRCK_EXT),
+ /* i2srx */
+ STARFIVE_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32,
+ JH7110_SYSCLK_MCLK),
+ STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
+ JH7110_SYSCLK_I2SRX_BCLK_MST),
+ STARFIVE_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
+ JH7110_SYSCLK_I2SRX_BCLK_MST),
+ STARFIVE__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
+ JH7110_SYSCLK_I2SRX_BCLK_MST,
+ JH7110_SYSCLK_I2SRX_BCLK_EXT),
+ STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv",
+ JH7110_SYSCLK_I2SRX_BCLK),
+ STARFIVE__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
+ JH7110_SYSCLK_I2SRX_LRCK_MST,
+ JH7110_SYSCLK_I2SRX_LRCK_EXT),
+ /* pdm */
+ STARFIVE_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64,
+ JH7110_SYSCLK_MCLK),
+ STARFIVE_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0,
+ JH7110_SYSCLK_APB0),
+ /* tdm */
+ STARFIVE_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0,
+ JH7110_SYSCLK_AHB0),
+ STARFIVE_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0,
+ JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64,
+ JH7110_SYSCLK_MCLK),
+ STARFIVE__MUX(JH7110_SYSCLK_TDM_CLK_TDM, "tdm_clk_tdm", 2,
+ JH7110_SYSCLK_TDM_INTERNAL,
+ JH7110_SYSCLK_TDM_EXT),
+ STARFIVE__INV(JH7110_SYSCLK_TDM_CLK_TDM_N, "tdm_clk_tdm_n",
+ JH7110_SYSCLK_TDM_CLK_TDM),
+ /* jtag */
+ STARFIVE__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG,
+ "jtag_certification_trng", 4,
+ JH7110_SYSCLK_OSC),
+};
+
+static const struct {
+ const char *name;
+ const char *parent;
+ unsigned int mul;
+ unsigned int div;
+} jh7110_fixed_factor_clocks[JH7110_SYSCLK_END - JH7110_SYSCLK_PLL0_OUT] __initconst = {
+ [JH7110_SYSCLK_PLL0_OUT - JH7110_SYSCLK_PLL0_OUT] = {
+ "pll0_out", "osc", 625, 12 /* 24MHz -> 1250.0MHz */
+ },
+ [JH7110_SYSCLK_PLL1_OUT - JH7110_SYSCLK_PLL0_OUT] = {
+ "pll1_out", "osc", 533, 12 /* 24MHz -> 1066.0MHz */
+ },
+ [JH7110_SYSCLK_PLL2_OUT - JH7110_SYSCLK_PLL0_OUT] = {
+ "pll2_out", "osc", 256, 5 /* 24MHz -> 1228.8MHz */
+ },
+ [JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK - JH7110_SYSCLK_PLL0_OUT] = {
+ "u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1
+ },
+ [JH7110_SYSCLK_U2_PCLK_MUX_PCLK - JH7110_SYSCLK_PLL0_OUT] = {
+ "u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1
+ },
+ [JH7110_SYSCLK_APB_BUS - JH7110_SYSCLK_PLL0_OUT] = {
+ "apb_bus", "u2_pclk_mux_pclk", 1, 1
+ },
+ [JH7110_SYSCLK_AXI_CFG1 - JH7110_SYSCLK_PLL0_OUT] = {
+ "axi_cfg1", "isp_axi", 1, 1
+ },
+ [JH7110_SYSCLK_APB12 - JH7110_SYSCLK_PLL0_OUT] = {
+ "apb12", "apb_bus", 1, 1
+ },
+ [JH7110_SYSCLK_VOUT_ROOT - JH7110_SYSCLK_PLL0_OUT] = {
+ "vout_root", "pll2_out", 1, 1
+ },
+ [JH7110_SYSCLK_VENC_ROOT - JH7110_SYSCLK_PLL0_OUT] = {
+ "venc_root", "pll2_out", 1, 1
+ },
+ [JH7110_SYSCLK_VDEC_ROOT - JH7110_SYSCLK_PLL0_OUT] = {
+ "vdec_root", "pll0_out", 1, 1
+ },
+ [JH7110_SYSCLK_GMACUSB_ROOT - JH7110_SYSCLK_PLL0_OUT] = {
+ "gmacusb_root", "pll0_out", 1, 1
+ },
+};
+
+static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct starfive_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_SYSCLK_PLL0_OUT)
+ return &priv->reg[idx].hw;
+
+ if (idx < JH7110_SYSCLK_END)
+ return priv->pll[idx - JH7110_SYSCLK_PLL0_OUT];
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int __init jh7110_syscrg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int i, ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+
+ priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
+ if (IS_ERR(priv->regmap)) {
+ dev_err(priv->dev, "failed to get regmap (error %ld)\n",
+ PTR_ERR(priv->regmap));
+ return PTR_ERR(priv->regmap);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(jh7110_fixed_factor_clocks); i++) {
+ priv->pll[i] =
+ devm_clk_hw_register_fixed_factor(&pdev->dev,
+ jh7110_fixed_factor_clocks[i].name,
+ jh7110_fixed_factor_clocks[i].parent,
+ 0,
+ jh7110_fixed_factor_clocks[i].mul,
+ jh7110_fixed_factor_clocks[i].div);
+ if (IS_ERR(priv->pll[i]))
+ return PTR_ERR(priv->pll[i]);
+ }
+
+ for (idx = 0; idx < JH7110_SYSCLK_PLL0_OUT; idx++) {
+ u32 max = jh7110_sysclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_sysclk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_sysclk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_sysclk_data[idx].parents[i];
+
+ if (pidx < JH7110_SYSCLK_PLL0_OUT)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx < JH7110_SYSCLK_END)
+ parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
+ else if (pidx == JH7110_SYSCLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN)
+ parents[i].fw_name = "gmac1_rmii_refin";
+ else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN)
+ parents[i].fw_name = "gmac1_rgmii_rxin";
+ else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT)
+ parents[i].fw_name = "i2stx_bclk_ext";
+ else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT)
+ parents[i].fw_name = "i2stx_lrck_ext";
+ else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT)
+ parents[i].fw_name = "i2srx_bclk_ext";
+ else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT)
+ parents[i].fw_name = "i2srx_lrck_ext";
+ else if (pidx == JH7110_SYSCLK_TDM_EXT)
+ parents[i].fw_name = "tdm_ext";
+ else if (pidx == JH7110_SYSCLK_MCLK_EXT)
+ parents[i].fw_name = "mclk_ext";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);
+}
+
+static const struct of_device_id jh7110_syscrg_match[] = {
+ { .compatible = "starfive,jh7110-clkgen-sys" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jh7110_syscrg_driver = {
+ .driver = {
+ .name = "clk-starfive-jh7110-sys",
+ .of_match_table = jh7110_syscrg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe);
diff --git a/drivers/clk/starfive/clk-starfive.h b/drivers/clk/starfive/clk-starfive.h
index 99cf74e8cbde..b717bd033e26 100644
--- a/drivers/clk/starfive/clk-starfive.h
+++ b/drivers/clk/starfive/clk-starfive.h
@@ -103,7 +103,7 @@ struct starfive_clk {
struct starfive_clk_priv {
struct device *dev;
struct regmap *regmap;
- struct clk_hw *pll[3];
+ struct clk_hw *pll[12];
struct starfive_clk reg[];
};
--
2.17.1
On Fri, 30 Sep 2022 06:26:47 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add bindings for the system clock generator on the JH7110
> RISC-V SoC by StarFive Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../clock/starfive,jh7110-clkgen-sys.yaml | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.example.dts:18.47-31.11: Warning (unit_address_vs_reg): /example-0/clock-controller@13020000: node has a unit name, but no reg or ranges property
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
From: Emil Renner Berthing <[email protected]>
Add bindings for the always-on clock generator on the JH7110
RISC-V SoC by StarFive Technology Ltd.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../clock/starfive,jh7110-clkgen-aon.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
new file mode 100644
index 000000000000..029ff57b9e3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Always-On Clock Generator
+
+maintainers:
+ - Emil Renner Berthing <[email protected]>
+ - Xingyu Wu <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh7110-clkgen-aon
+
+ clocks:
+ items:
+ - description: Main Oscillator
+ - description: RTC clock
+ - description: RMII reference clock
+ - description: RGMII RX clock
+ - description: STG AXI/AHB clock
+ - description: APB Bus clock
+
+ clock-names:
+ items:
+ - const: osc
+ - const: clk_rtc
+ - const: gmac0_rmii_refin
+ - const: gmac0_rgmii_rxin
+ - const: stg_axiahb
+ - const: apb_bus_func
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive-jh7110-aon.h> for valid indices.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive-jh7110-sys.h>
+
+ aoncrg: clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ clocks = <&osc>, <&clk_rtc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>;
+ clock-names = "osc", "clk_rtc",
+ "gmac0_rmii_refin", "gmac0_rgmii_rxin",
+ "stg_axiahb", "apb_bus_func";
+ #clock-cells = <1>;
+ };
--
2.17.1
From: Jianlong Huang <[email protected]>
Move the StarFive JH7100 pinctrl driver to a new subdirectory
in preparation for adding more StarFive pinctrl drivers. No
functional change.
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
drivers/pinctrl/Kconfig | 18 +-----------------
drivers/pinctrl/Makefile | 2 +-
drivers/pinctrl/starfive/Kconfig | 19 +++++++++++++++++++
drivers/pinctrl/starfive/Makefile | 3 +++
.../pinctrl/{ => starfive}/pinctrl-starfive.c | 8 ++++----
5 files changed, 28 insertions(+), 22 deletions(-)
create mode 100644 drivers/pinctrl/starfive/Kconfig
create mode 100644 drivers/pinctrl/starfive/Makefile
rename drivers/pinctrl/{ => starfive}/pinctrl-starfive.c (99%)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1cf74b0c42e5..5abf1961f4d4 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -412,23 +412,6 @@ config PINCTRL_ST
select PINCONF
select GPIOLIB_IRQCHIP
-config PINCTRL_STARFIVE
- tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
- depends on SOC_STARFIVE || COMPILE_TEST
- depends on OF
- default SOC_STARFIVE
- select GENERIC_PINCTRL_GROUPS
- select GENERIC_PINMUX_FUNCTIONS
- select GENERIC_PINCONF
- select GPIOLIB
- select GPIOLIB_IRQCHIP
- select OF_GPIO
- help
- Say yes here to support pin control on the StarFive JH7100 SoC.
- This also provides an interface to the GPIO pins not used by other
- peripherals supporting inputs, outputs, configuring pull-up/pull-down
- and interrupts on input changes.
-
config PINCTRL_STMFX
tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
depends on I2C
@@ -526,6 +509,7 @@ source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
+source "drivers/pinctrl/starfive/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
source "drivers/pinctrl/sunplus/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e76f5cdc64b0..eccd4d568a3d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -43,7 +43,6 @@ obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
-obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
@@ -70,6 +69,7 @@ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
+obj-$(CONFIG_SOC_STARFIVE) += starfive/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
obj-y += sunplus/
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
new file mode 100644
index 000000000000..ed8c6a920886
--- /dev/null
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PINCTRL_STARFIVE
+ tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
+ depends on SOC_STARFIVE || COMPILE_TEST
+ depends on OF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select GPIOLIB_IRQCHIP
+ select OF_GPIO
+ default SOC_STARFIVE
+ help
+ Say yes here to support pin control on the StarFive JH7100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
new file mode 100644
index 000000000000..4c96e2f86292
--- /dev/null
+++ b/drivers/pinctrl/starfive/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
diff --git a/drivers/pinctrl/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c
similarity index 99%
rename from drivers/pinctrl/pinctrl-starfive.c
rename to drivers/pinctrl/starfive/pinctrl-starfive.c
index 3eb40e230d98..74a084740e8c 100644
--- a/drivers/pinctrl/pinctrl-starfive.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.c
@@ -22,10 +22,10 @@
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
-#include "core.h"
-#include "pinctrl-utils.h"
-#include "pinmux.h"
-#include "pinconf.h"
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "../pinmux.h"
+#include "../pinconf.h"
#define DRIVER_NAME "pinctrl-starfive"
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add all clock outputs for the StarFive JH7110 always-on clock generator.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../dt-bindings/clock/starfive-jh7110-aon.h | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 include/dt-bindings/clock/starfive-jh7110-aon.h
diff --git a/include/dt-bindings/clock/starfive-jh7110-aon.h b/include/dt-bindings/clock/starfive-jh7110-aon.h
new file mode 100644
index 000000000000..5f1f7f2f1533
--- /dev/null
+++ b/include/dt-bindings/clock/starfive-jh7110-aon.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright 2022 Emil Renner Berthing <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_AON_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_AON_H__
+
+#define JH7110_AONCLK_OSC_DIV4 0
+#define JH7110_AONCLK_APB_FUNC 1
+#define JH7110_AONCLK_GMAC0_AHB 2
+#define JH7110_AONCLK_GMAC0_AXI 3
+#define JH7110_AONCLK_GMAC0_RMII_RTX 4
+#define JH7110_AONCLK_GMAC0_TX 5
+#define JH7110_AONCLK_GMAC0_TX_INV 6
+#define JH7110_AONCLK_GMAC0_RX 7
+#define JH7110_AONCLK_GMAC0_RX_INV 8
+#define JH7110_AONCLK_OTPC_APB 9
+#define JH7110_AONCLK_RTC_APB 10
+#define JH7110_AONCLK_RTC_INTERNAL 11
+#define JH7110_AONCLK_RTC_32K 12
+#define JH7110_AONCLK_RTC_CAL 13
+
+#define JH7110_AONCLK_END 14
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add driver for the StarFive JH7110 always-on clock controller.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
drivers/clk/starfive/Kconfig | 9 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jh7110-aon.c | 161 ++++++++++++++++++
3 files changed, 171 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index c13096543a8b..42aad3b553cb 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -29,3 +29,12 @@ config CLK_STARFIVE_JH7110_SYS
help
Say yes here to support the system clock controller on the
StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_AON
+ tristate "StarFive JH7110 always-on clock support"
+ depends on SOC_STARFIVE || COMPILE_TEST
+ select CLK_STARFIVE
+ default m if SOC_STARFIVE
+ help
+ Say yes here to support the always-on clock controller on the
+ StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 2bc126cc91f2..b54d11340704 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
new file mode 100644
index 000000000000..4975e7ad67be
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Always-On Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive-jh7110-aon.h>
+
+#include "clk-starfive.h"
+
+/* external clocks */
+#define JH7110_AONCLK_OSC (JH7110_AONCLK_END + 0)
+#define JH7110_AONCLK_RTC (JH7110_AONCLK_END + 1)
+#define JH7110_AONCLK_GMAC0_RMII_REFIN (JH7110_AONCLK_END + 2)
+#define JH7110_AONCLK_GMAC0_RGMII_RXIN (JH7110_AONCLK_END + 3)
+#define JH7110_AONCLK_STG_AXIAHB (JH7110_AONCLK_END + 4)
+#define JH7110_AONCLK_APB_BUS_FUNC (JH7110_AONCLK_END + 5)
+#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 6)
+
+static const struct starfive_clk_data jh7110_aonclk_data[] = {
+ /* source */
+ STARFIVE__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4,
+ JH7110_AONCLK_OSC),
+ STARFIVE__MUX(JH7110_AONCLK_APB_FUNC, "aon_apb_func", 2,
+ JH7110_AONCLK_OSC_DIV4,
+ JH7110_AONCLK_OSC),
+ /* gmac0 */
+ STARFIVE_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0,
+ JH7110_AONCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0,
+ JH7110_AONCLK_STG_AXIAHB),
+ STARFIVE__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
+ JH7110_AONCLK_GMAC0_RMII_REFIN),
+ STARFIVE_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", 0, 2,
+ JH7110_AONCLK_GMAC0_GTXCLK,
+ JH7110_AONCLK_GMAC0_RMII_RTX),
+ STARFIVE__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv",
+ JH7110_AONCLK_GMAC0_TX),
+ STARFIVE__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
+ JH7110_AONCLK_GMAC0_RGMII_RXIN,
+ JH7110_AONCLK_GMAC0_RMII_RTX),
+ STARFIVE__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv",
+ JH7110_AONCLK_GMAC0_RX),
+ /* otpc */
+ STARFIVE_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", CLK_IGNORE_UNUSED,
+ JH7110_AONCLK_APB_BUS_FUNC),
+ /* rtc */
+ STARFIVE_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", CLK_IGNORE_UNUSED,
+ JH7110_AONCLK_APB_BUS_FUNC),
+ STARFIVE__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022,
+ JH7110_AONCLK_OSC),
+ STARFIVE__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
+ JH7110_AONCLK_RTC,
+ JH7110_AONCLK_RTC_INTERNAL),
+ STARFIVE_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0,
+ JH7110_AONCLK_OSC),
+};
+
+static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct starfive_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_AONCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_aoncrg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_AONCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+
+ priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
+ if (IS_ERR(priv->regmap)) {
+ dev_err(priv->dev, "failed to get regmap (error %ld)\n",
+ PTR_ERR(priv->regmap));
+ return PTR_ERR(priv->regmap);
+ }
+
+ for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
+ u32 max = jh7110_aonclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_aonclk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents = ((max & STARFIVE_CLK_MUX_MASK)
+ >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_aonclk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
+
+ if (pidx < JH7110_AONCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JH7110_AONCLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JH7110_AONCLK_RTC)
+ parents[i].fw_name = "clk_rtc";
+ else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
+ parents[i].fw_name = "gmac0_rmii_refin";
+ else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
+ parents[i].fw_name = "gmac0_rgmii_rxin";
+ else if (pidx == JH7110_AONCLK_STG_AXIAHB)
+ parents[i].fw_name = "stg_axiahb";
+ else if (pidx == JH7110_AONCLK_APB_BUS_FUNC)
+ parents[i].fw_name = "apb_bus_func";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
+}
+
+static const struct of_device_id jh7110_aoncrg_match[] = {
+ { .compatible = "starfive,jh7110-clkgen-aon" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match);
+
+static struct platform_driver jh7110_aoncrg_driver = {
+ .probe = jh7110_aoncrg_probe,
+ .driver = {
+ .name = "clk-starfive-jh7110-aon",
+ .of_match_table = jh7110_aoncrg_match,
+ },
+};
+module_platform_driver(jh7110_aoncrg_driver);
+
+MODULE_AUTHOR("Emil Renner Berthing");
+MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
+MODULE_LICENSE("GPL v2");
--
2.17.1
From: Jianlong Huang <[email protected]>
Add the SoC name to make it more clear. Also the next generation StarFive
SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
No functional change.
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../bindings/pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
drivers/pinctrl/starfive/Kconfig | 2 +-
drivers/pinctrl/starfive/Makefile | 2 +-
.../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} | 2 +-
.../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} | 6 +++---
6 files changed, 8 insertions(+), 8 deletions(-)
rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
index 92963604422f..a6140dddd39a 100644
--- a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
@@ -165,7 +165,7 @@ examples:
- |
#include <dt-bindings/clock/starfive-jh7100.h>
#include <dt-bindings/reset/starfive-jh7100.h>
- #include <dt-bindings/pinctrl/pinctrl-starfive.h>
+ #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
soc {
#address-cells = <2>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
index c9af67f7a0d2..f7a230110512 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
@@ -8,7 +8,7 @@
#include "jh7100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/pinctrl-starfive.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
/ {
model = "BeagleV Starlight Beta";
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index ed8c6a920886..5cedb546f93d 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-config PINCTRL_STARFIVE
+config PINCTRL_STARFIVE_JH7100
tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
depends on SOC_STARFIVE || COMPILE_TEST
depends on OF
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 4c96e2f86292..0293f26a0a99 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
similarity index 99%
rename from drivers/pinctrl/starfive/pinctrl-starfive.c
rename to drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
index 74a084740e8c..5b544fb7f3d8 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
@@ -20,7 +20,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
-#include <dt-bindings/pinctrl/pinctrl-starfive.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
#include "../core.h"
#include "../pinctrl-utils.h"
diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
similarity index 98%
rename from include/dt-bindings/pinctrl/pinctrl-starfive.h
rename to include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
index de4f75c2c9e8..a200f546d078 100644
--- a/include/dt-bindings/pinctrl/pinctrl-starfive.h
+++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
@@ -3,8 +3,8 @@
* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
*/
-#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_H__
-#define __DT_BINDINGS_PINCTRL_STARFIVE_H__
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__
#define PAD_GPIO_OFFSET 0
#define PAD_FUNC_SHARE_OFFSET 64
@@ -272,4 +272,4 @@
#define GPI_NONE 0xff
-#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_H__ */
+#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ */
--
2.17.1
From: Jianlong Huang <[email protected]>
Add pinctrl driver for StarFive JH7110 SoC.
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
MAINTAINERS | 9 +-
drivers/pinctrl/starfive/Kconfig | 20 +
drivers/pinctrl/starfive/Makefile | 5 +
drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 718 ++++++++++++++
drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 925 ++++++++++++++++++
drivers/pinctrl/starfive/pinctrl-starfive.c | 539 ++++++++++
drivers/pinctrl/starfive/pinctrl-starfive.h | 131 +++
7 files changed, 2343 insertions(+), 4 deletions(-)
create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 70d64d2afb0c..6847dee99603 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19404,13 +19404,14 @@ F: Documentation/devicetree/bindings/clock/starfive*
F: drivers/clk/starfive/
F: include/dt-bindings/clock/starfive*
-STARFIVE JH7100 PINCTRL DRIVER
+STARFIVE PINCTRL DRIVER
M: Emil Renner Berthing <[email protected]>
+M: Jianlong Huang <[email protected]>
L: [email protected]
S: Maintained
-F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
-F: drivers/pinctrl/pinctrl-starfive.c
-F: include/dt-bindings/pinctrl/pinctrl-starfive.h
+F: Documentation/devicetree/bindings/pinctrl/starfive*
+F: drivers/pinctrl/starfive/
+F: include/dt-bindings/pinctrl/pinctrl-starfive*
STARFIVE RESET CONTROLLER DRIVER
M: Emil Renner Berthing <[email protected]>
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 5cedb546f93d..fde39f4a7922 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -17,3 +17,23 @@ config PINCTRL_STARFIVE_JH7100
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE
+ bool
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select GPIOLIB_IRQCHIP
+ select OF_GPIO
+
+config PINCTRL_STARFIVE_JH7110
+ bool "Pinctrl and GPIO driver for the StarFive JH7110 SoC"
+ depends on SOC_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE
+ default SOC_STARFIVE
+ help
+ Say yes here to support pin control on the StarFive JH7110 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 0293f26a0a99..17cdd1b0e650 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -1,3 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
+
+# SoC Drivers
obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o
diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
new file mode 100644
index 000000000000..058acd3ff305
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
@@ -0,0 +1,718 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive.h"
+
+/* aon_iomux */
+#define AON_GPO_DOEN_CFG 0x0
+#define AON_GPO_DOEN_MASK GENMASK(2, 0)
+#define AON_GPO_DOUT_CFG 0x4
+#define AON_GPO_DOUT_MASK GENMASK(3, 0)
+#define AON_GPI_DIN_CFG 0x8
+#define AON_GPI_DIN_MASK GENMASK(3, 0)
+#define AON_GPIO_DIN_REG 0x2c
+
+/* aon_iomux GPIO CTRL */
+#define AON_GPIO_EN_REG 0xc
+#define AON_GPIO_IS_REG 0x10
+#define AON_GPIO_IC_REG 0x14
+#define AON_GPIO_IBE_REG 0x18
+#define AON_GPIO_IEV_REG 0x1c
+#define AON_GPIO_IE_REG 0x20
+#define AON_GPIO_MIS_REG 0x28
+
+/* aon_iomux PIN ioconfig reg */
+#define AON_GPO_PDA_0_5_CFG 0x30
+#define PADCFG_PAD_GMAC_SYSCON_SHIFT 0x0
+#define PADCFG_PAD_GMAC_SYSCON_MASK GENMASK(1, 0)
+#define A0N_GPO_PDA_CFG_OFFSET 0x4
+#define AON_GPIO_INPUT_ENABLE_REG 0x34
+
+#define AON_GPIO_NUM 4
+
+enum starfive_jh7110_aon_pads {
+ PAD_TESTEN = 0,
+ PAD_RGPIO0 = 1,
+ PAD_RGPIO1 = 2,
+ PAD_RGPIO2 = 3,
+ PAD_RGPIO3 = 4,
+ PAD_RSTN = 5,
+ PAD_GMAC0_MDC = 6,
+ PAD_GMAC0_MDIO = 7,
+ PAD_GMAC0_RXD0 = 8,
+ PAD_GMAC0_RXD1 = 9,
+ PAD_GMAC0_RXD2 = 10,
+ PAD_GMAC0_RXD3 = 11,
+ PAD_GMAC0_RXDV = 12,
+ PAD_GMAC0_RXC = 13,
+ PAD_GMAC0_TXD0 = 14,
+ PAD_GMAC0_TXD1 = 15,
+ PAD_GMAC0_TXD2 = 16,
+ PAD_GMAC0_TXD3 = 17,
+ PAD_GMAC0_TXEN = 18,
+ PAD_GMAC0_TXC = 19,
+};
+
+static const struct pinctrl_pin_desc starfive_jh7110_aon_pinctrl_pads[] = {
+ STARFIVE_PINCTRL_PIN(PAD_TESTEN),
+ STARFIVE_PINCTRL_PIN(PAD_RGPIO0),
+ STARFIVE_PINCTRL_PIN(PAD_RGPIO1),
+ STARFIVE_PINCTRL_PIN(PAD_RGPIO2),
+ STARFIVE_PINCTRL_PIN(PAD_RGPIO3),
+ STARFIVE_PINCTRL_PIN(PAD_RSTN),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_MDC),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_MDIO),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD0),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD1),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD2),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD3),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXDV),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXC),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD0),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD1),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD2),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD3),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXEN),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXC),
+};
+
+static int jh7110_aon_pmx_set_one_pin_mux(struct starfive_pinctrl *pctl,
+ struct starfive_pin *pin)
+{
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ struct starfive_pin_config *pin_config = &pin->pin_config;
+ const struct starfive_pin_reg *pin_reg;
+ unsigned int gpio, pin_id;
+ int i;
+ unsigned long flags;
+ int n, shift;
+
+ gpio = pin->pin_config.gpio_num;
+ pin_id = pin->pin;
+ pin_reg = &pctl->pin_regs[pin_id];
+
+ raw_spin_lock_irqsave(&pctl->lock, flags);
+ if (pin_reg->func_sel_reg != -1) {
+ pinctrl_set_reg(pctl->padctl_base + pin_reg->func_sel_reg,
+ pin_config->pinmux_func,
+ pin_reg->func_sel_shift,
+ pin_reg->func_sel_mask);
+ }
+
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ if (pin_reg->gpo_dout_reg != -1) {
+ pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
+ AON_GPO_DOUT_MASK << shift,
+ pin_config->gpio_dout << shift);
+ }
+
+ if (pin_reg->gpo_doen_reg != -1) {
+ pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
+ AON_GPO_DOEN_MASK << shift,
+ pin_config->gpio_doen << shift);
+ }
+
+ for (i = 0; i < pin_config->gpio_din_num; i++) {
+ n = pin_config->gpio_din_reg[i] >> 2;
+ shift = (pin_config->gpio_din_reg[i] & 3) << 3;
+ pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
+ AON_GPI_DIN_MASK << shift,
+ (gpio + 2) << shift);
+ }
+
+ if (pin_reg->syscon_reg != -1) {
+ pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
+ pin_config->syscon,
+ PADCFG_PAD_GMAC_SYSCON_SHIFT,
+ PADCFG_PAD_GMAC_SYSCON_MASK);
+ }
+
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+ return 0;
+}
+
+static void jh7110_aon_parse_pin_config(struct starfive_pinctrl *pctl,
+ unsigned int *pins_id,
+ struct starfive_pin *pin_data,
+ const __be32 *list_p,
+ struct device_node *np)
+{
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ struct starfive_pin_reg *pin_reg;
+ const __be32 *list = list_p;
+ const __be32 *list_din;
+ int size;
+ int size_din;
+ int pin_size;
+ u32 value;
+ int i;
+
+ pin_size = sizeof(u32);
+ *pins_id = be32_to_cpu(*list);
+ pin_reg = &pctl->pin_regs[*pins_id];
+ pin_data->pin = *pins_id;
+
+ if (pin_data->pin > PAD_GMAC0_TXC) {
+ dev_err(pctl->dev, "err pin num = %d\n", pin_data->pin);
+ return;
+ }
+
+ if (pin_data->pin < PAD_GMAC0_MDC) {
+ pin_reg->io_conf_reg = (pin_data->pin * A0N_GPO_PDA_CFG_OFFSET) +
+ AON_GPO_PDA_0_5_CFG;
+ }
+
+ if (!of_property_read_u32(np, "starfive,pin-ioconfig", &value))
+ pin_data->pin_config.io_config = value;
+
+ list = of_get_property(np, "starfive,pinmux", &size);
+ if (list) {
+ pin_reg->func_sel_reg = be32_to_cpu(*list++);
+ pin_reg->func_sel_shift = be32_to_cpu(*list++);
+ pin_reg->func_sel_mask = be32_to_cpu(*list++);
+ pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
+ }
+
+ list = of_get_property(np, "starfive,pin-syscon", &size);
+ if (list) {
+ pin_reg->syscon_reg = be32_to_cpu(*list++);
+ pin_data->pin_config.syscon = be32_to_cpu(*list++);
+ }
+
+ if (pin_data->pin >= PAD_RGPIO0 && pin_data->pin <= PAD_RGPIO3) {
+ pin_data->pin_config.gpio_num = pin_data->pin - 1;
+ pin_reg->gpo_dout_reg = info->dout_reg_base;
+ pin_reg->gpo_doen_reg = info->doen_reg_base;
+
+ if (!of_property_read_u32(np, "starfive,pin-gpio-dout", &value))
+ pin_data->pin_config.gpio_dout = value;
+
+ if (!of_property_read_u32(np, "starfive,pin-gpio-doen", &value))
+ pin_data->pin_config.gpio_doen = value;
+
+ list_din = of_get_property(np, "starfive,pin-gpio-din", &size_din);
+ if (list_din) {
+ if (!size_din || size_din % pin_size) {
+ dev_err(pctl->dev,
+ "Invalid starfive,pin-gpio-din property in node\n");
+ return;
+ }
+ pin_data->pin_config.gpio_din_num = size_din / pin_size;
+ pin_data->pin_config.gpio_din_reg =
+ devm_kcalloc(pctl->dev,
+ pin_data->pin_config.gpio_din_num,
+ sizeof(s32),
+ GFP_KERNEL);
+ for (i = 0; i < pin_data->pin_config.gpio_din_num; i++) {
+ value = be32_to_cpu(*list_din++);
+ pin_data->pin_config.gpio_din_reg[i] = value;
+ }
+ }
+ }
+}
+
+static int jh7110_aon_direction_input(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int shift;
+ void __iomem *reg_doen;
+ u32 mask;
+
+ if (gpio < 0 || gpio >= gc->ngpio)
+ return -EINVAL;
+
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ mask = AON_GPO_DOEN_MASK << shift;
+ reg_doen = chip->padctl_base + AON_GPO_DOEN_CFG;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ pinctrl_set_reg(reg_doen, 1, shift, mask);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int jh7110_aon_direction_output(struct gpio_chip *gc,
+ unsigned int gpio,
+ int value)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int shift;
+ void __iomem *reg_doen, *reg_dout;
+ u32 mask_doen, mask_dout;
+
+ if (gpio < 0 || gpio >= gc->ngpio)
+ return -EINVAL;
+
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ mask_doen = AON_GPO_DOEN_MASK << shift;
+ mask_dout = AON_GPO_DOUT_MASK << shift;
+ reg_doen = chip->padctl_base + AON_GPO_DOEN_CFG;
+ reg_dout = chip->padctl_base + AON_GPO_DOUT_CFG;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ pinctrl_set_reg(reg_doen, 0, shift, mask_doen);
+
+ pinctrl_set_reg(reg_dout, value, shift, mask_dout);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int jh7110_aon_get_direction(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int doen;
+ unsigned int shift;
+ void __iomem *reg_doen;
+ u32 mask;
+
+ if (gpio < 0 || gpio >= gc->ngpio)
+ return -EINVAL;
+
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ mask = AON_GPO_DOEN_MASK << shift;
+ reg_doen = chip->padctl_base + AON_GPO_DOEN_CFG;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ doen = readl_relaxed(reg_doen);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return !!(doen & mask);
+}
+
+static int jh7110_aon_get_value(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ int value;
+
+ if (gpio < 0 || gpio >= gc->ngpio)
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ value = readl_relaxed(chip->padctl_base + AON_GPIO_DIN_REG);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return (value >> gpio) & 0x1;
+}
+
+static void jh7110_aon_set_value(struct gpio_chip *gc,
+ unsigned int gpio, int value)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int shift;
+ void __iomem *reg_dout;
+ u32 mask;
+
+ if (gpio < 0 || gpio >= gc->ngpio)
+ return;
+
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ mask = AON_GPO_DOUT_MASK << shift;
+ reg_dout = chip->padctl_base + AON_GPO_DOUT_CFG;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ pinctrl_set_reg(reg_dout, value, shift, mask);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static void jh7110_aon_irq_handler(struct irq_desc *desc)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long mis;
+ unsigned int pin;
+
+ chained_irq_enter(chip, desc);
+
+ mis = readl_relaxed(sfp->padctl_base + AON_GPIO_MIS_REG);
+ for_each_set_bit(pin, &mis, AON_GPIO_NUM)
+ generic_handle_domain_irq(sfp->gc.irq.domain, pin);
+
+ chained_irq_exit(chip, desc);
+}
+
+static int jh7110_aon_init_hw(struct gpio_chip *gc)
+{
+ struct starfive_pinctrl *sfp = container_of(gc,
+ struct starfive_pinctrl, gc);
+
+ /* mask all GPIO interrupts */
+ writel_relaxed(0, sfp->padctl_base + AON_GPIO_IE_REG);
+ /* clear edge interrupt flags */
+ writel_relaxed(0, sfp->padctl_base + AON_GPIO_IC_REG);
+ writel_relaxed(0x0f, sfp->padctl_base + AON_GPIO_IC_REG);
+ /* enable GPIO interrupts */
+ writel_relaxed(1, sfp->padctl_base + AON_GPIO_EN_REG);
+ return 0;
+}
+
+static int jh7110_aon_irq_set_type(struct irq_data *d,
+ unsigned int trigger)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *base = sfp->padctl_base;
+ u32 mask = BIT(gpio);
+ u32 irq_type, edge_both, polarity;
+ unsigned long flags;
+
+ switch (trigger) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_type = 0; /* 0: level triggered */
+ edge_both = 0; /* 0: ignored */
+ polarity = 0; /* 0: high level */
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ irq_type = 0; /* 0: level triggered */
+ edge_both = 0; /* 0: ignored */
+ polarity = 1; /* 1: low level */
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = mask; /* 1: both edges */
+ polarity = 0; /* 0: ignored */
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = 0; /* 0: single edge */
+ polarity = mask; /* 1: rising edge */
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = 0; /* 0: single edge */
+ polarity = 0; /* 0: falling edge */
+ break;
+ }
+ if (trigger & IRQ_TYPE_EDGE_BOTH)
+ irq_set_handler_locked(d, handle_edge_irq);
+ else
+ irq_set_handler_locked(d, handle_level_irq);
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ irq_type |= readl_relaxed(base + AON_GPIO_IS_REG) & ~mask;
+ writel_relaxed(irq_type, base + AON_GPIO_IS_REG);
+
+ edge_both |= readl_relaxed(base + AON_GPIO_IBE_REG) & ~mask;
+ writel_relaxed(edge_both, base + AON_GPIO_IBE_REG);
+
+ polarity |= readl_relaxed(base + AON_GPIO_IEV_REG) & ~mask;
+ writel_relaxed(polarity, base + AON_GPIO_IEV_REG);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+ sfp->trigger[gpio] = trigger;
+ return 0;
+}
+
+static void jh7110_aon_irq_mask(struct irq_data *d)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
+ u32 mask = BIT(gpio);
+ unsigned long flags;
+ u32 value;
+
+ if (gpio < 0 || gpio >= sfp->gc.ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ie) & ~mask;
+ writel_relaxed(value, ie);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_aon_irq_unmask(struct irq_data *d)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
+ u32 mask = BIT(gpio);
+ unsigned long flags;
+ u32 value;
+
+ if (gpio < 0 || gpio >= sfp->gc.ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ie) | mask;
+ writel_relaxed(value, ie);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_aon_irq_ack(struct irq_data *d)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ic = sfp->padctl_base + AON_GPIO_IC_REG;
+ u32 mask = BIT(gpio);
+ unsigned long flags;
+ u32 value;
+
+ if (gpio < 0 || gpio >= sfp->gc.ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value, ic);
+ writel_relaxed(value | mask, ic);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_aon_irq_mask_ack(struct irq_data *d)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
+ void __iomem *ic = sfp->padctl_base + AON_GPIO_IC_REG;
+ u32 mask = BIT(gpio);
+ unsigned long flags;
+ u32 value;
+
+ if (gpio < 0 || gpio >= sfp->gc.ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ie) & ~mask;
+ writel_relaxed(value, ie);
+
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value, ic);
+ writel_relaxed(value | mask, ic);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static struct irq_chip jh7110_aon_irqchip = {
+ .name = "starfive-jh7110-aon-gpio",
+ .irq_ack = jh7110_aon_irq_ack,
+ .irq_mask_ack = jh7110_aon_irq_mask_ack,
+ .irq_set_type = jh7110_aon_irq_set_type,
+ .irq_mask = jh7110_aon_irq_mask,
+ .irq_unmask = jh7110_aon_irq_unmask,
+ .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static int jh7110_aon_add_pin_ranges(struct gpio_chip *gc)
+{
+ struct starfive_pinctrl *sfp = container_of(gc,
+ struct starfive_pinctrl, gc);
+
+ sfp->gpios.name = sfp->gc.label;
+ sfp->gpios.base = sfp->gc.base;
+ /*
+ * sfp->gpios.pin_base depends on the chosen signal group
+ * and is set in starfive_probe()
+ */
+ sfp->gpios.npins = AON_GPIO_NUM;
+ sfp->gpios.gc = &sfp->gc;
+ pinctrl_add_gpio_range(sfp->pctl_dev, &sfp->gpios);
+ return 0;
+}
+
+static int jh7110_aon_gpio_register(struct platform_device *pdev,
+ struct starfive_pinctrl *pctl)
+{
+ struct device *dev = &pdev->dev;
+ int ret, ngpio;
+ int loop;
+
+ ngpio = AON_GPIO_NUM;
+
+ pctl->gc.direction_input = jh7110_aon_direction_input;
+ pctl->gc.direction_output = jh7110_aon_direction_output;
+ pctl->gc.get_direction = jh7110_aon_get_direction;
+ pctl->gc.get = jh7110_aon_get_value;
+ pctl->gc.set = jh7110_aon_set_value;
+ pctl->gc.add_pin_ranges = jh7110_aon_add_pin_ranges;
+ pctl->gc.base = MAX_GPIO;
+ pctl->gc.ngpio = ngpio;
+ pctl->gc.label = dev_name(dev);
+ pctl->gc.parent = dev;
+ pctl->gc.owner = THIS_MODULE;
+
+ pctl->enabled = 0;
+
+ platform_set_drvdata(pdev, pctl);
+
+ jh7110_aon_irqchip.name = pctl->gc.label;
+
+ pctl->gc.irq.chip = &jh7110_aon_irqchip;
+ pctl->gc.irq.parent_handler = jh7110_aon_irq_handler;
+ pctl->gc.irq.num_parents = 1;
+ pctl->gc.irq.parents =
+ devm_kcalloc(dev, pctl->gc.irq.num_parents,
+ sizeof(*pctl->gc.irq.parents), GFP_KERNEL);
+ if (!pctl->gc.irq.parents)
+ return -ENOMEM;
+ pctl->gc.irq.default_type = IRQ_TYPE_NONE;
+ pctl->gc.irq.handler = handle_bad_irq;
+ pctl->gc.irq.init_hw = jh7110_aon_init_hw;
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0)
+ return ret;
+ pctl->gc.irq.parents[0] = ret;
+
+ ret = devm_gpiochip_add_data(dev, &pctl->gc, pctl);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not register gpiochip\n");
+
+ for (loop = 0; loop < ngpio; loop++) {
+ unsigned int v;
+ void __iomem *ie_reg = pctl->padctl_base +
+ AON_GPIO_INPUT_ENABLE_REG + (loop << 2);
+
+ v = readl_relaxed(ie_reg);
+ v |= 0x1;
+ writel_relaxed(v, ie_reg);
+ }
+
+ dev_info(dev, "StarFive AON GPIO chip registered %d GPIOs\n", ngpio);
+
+ return 0;
+}
+
+static int jh7110_aon_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin_id,
+ unsigned long *config)
+{
+ struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
+ unsigned long flags;
+ u32 value;
+
+ if (pin_reg->io_conf_reg == -1) {
+ dev_err(pctl->dev,
+ "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ raw_spin_lock_irqsave(&pctl->lock, flags);
+ value = readl_relaxed(pctl->padctl_base + pin_reg->io_conf_reg);
+ *config = value & 0xff;
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+ return 0;
+}
+
+static int jh7110_aon_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin_id,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
+ int i;
+ u32 value;
+ unsigned long flags;
+
+ if (pin_reg->io_conf_reg == -1) {
+ dev_err(pctl->dev,
+ "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ raw_spin_lock_irqsave(&pctl->lock, flags);
+ for (i = 0; i < num_configs; i++) {
+ value = readl_relaxed(pctl->padctl_base +
+ pin_reg->io_conf_reg);
+ value = value | (configs[i] & 0xFF);
+ writel_relaxed(value, pctl->padctl_base +
+ pin_reg->io_conf_reg);
+ }
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+ return 0;
+}
+
+static const struct starfive_pinctrl_soc_info jh7110_aon_pinctrl_info = {
+ .pins = starfive_jh7110_aon_pinctrl_pads,
+ .npins = ARRAY_SIZE(starfive_jh7110_aon_pinctrl_pads),
+ .flags = 1,
+ .dout_reg_base = AON_GPO_DOUT_CFG,
+ .doen_reg_base = AON_GPO_DOEN_CFG,
+ .din_reg_base = AON_GPI_DIN_CFG,
+ .starfive_pinconf_get = jh7110_aon_pinconf_get,
+ .starfive_pinconf_set = jh7110_aon_pinconf_set,
+ .starfive_pmx_set_one_pin_mux = jh7110_aon_pmx_set_one_pin_mux,
+ .starfive_gpio_register = jh7110_aon_gpio_register,
+ .starfive_pinctrl_parse_pin = jh7110_aon_parse_pin_config,
+};
+
+static const struct of_device_id jh7110_aon_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jh7110-aon-pinctrl",
+ .data = &jh7110_aon_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+
+static int jh7110_aon_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct starfive_pinctrl_soc_info *pinctrl_info;
+
+ pinctrl_info = of_device_get_match_data(&pdev->dev);
+ if (!pinctrl_info)
+ return -ENODEV;
+
+ return starfive_pinctrl_probe(pdev, pinctrl_info);
+}
+
+static struct platform_driver jh7110_aon_pinctrl_driver = {
+ .driver = {
+ .name = "starfive-jh7110-aon-pinctrl",
+ .of_match_table = of_match_ptr(jh7110_aon_pinctrl_of_match),
+ },
+ .probe = jh7110_aon_pinctrl_probe,
+};
+
+static int __init jh7110_aon_pinctrl_init(void)
+{
+ return platform_driver_register(&jh7110_aon_pinctrl_driver);
+}
+arch_initcall(jh7110_aon_pinctrl_init);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC aon controller");
+MODULE_AUTHOR("Jenny Zhang <[email protected]>");
+MODULE_AUTHOR("Jianlong Huang <[email protected]>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
new file mode 100644
index 000000000000..882d45c63497
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
@@ -0,0 +1,925 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive.h"
+
+#define SYS_GPO_DOEN_CFG 0x0
+#define SYS_GPO_DOEN_MASK GENMASK(5, 0)
+#define SYS_GPO_DOUT_CFG 0x40
+#define SYS_GPO_DOUT_MASK GENMASK(6, 0)
+#define SYS_GPI_DIN_CFG 0x80
+#define SYS_GPI_DIN_MASK GENMASK(6, 0)
+#define SYS_GPIO_INPUT_ENABLE_REG 0x120
+
+/* sys_iomux PIN 0-74 ioconfig reg */
+#define SYS_GPO_PDA_0_74_CFG 0x120
+/* sys_iomux PIN 89-94 ioconfig reg */
+#define SYS_GPO_PDA_89_94_CFG 0x284
+#define SYS_GPO_PDA_CFG_OFFSET 0x4
+
+/* sys_iomux GPIO CTRL */
+#define GPIO_EN 0xdc
+#define GPIO_IS_LOW 0xe0
+#define GPIO_IS_HIGH 0xe4
+#define GPIO_IC_LOW 0xe8
+#define GPIO_IC_HIGH 0xec
+#define GPIO_IBE_LOW 0xf0
+#define GPIO_IBE_HIGH 0xf4
+#define GPIO_IEV_LOW 0xf8
+#define GPIO_IEV_HIGH 0xfc
+#define GPIO_IE_LOW 0x100
+#define GPIO_IE_HIGH 0x104
+
+/* read only */
+#define GPIO_MIS_LOW 0x110
+#define GPIO_MIS_HIGH 0x114
+#define GPIO_DIN_LOW 0x118
+#define GPIO_DIN_HIGH 0x11c
+
+#define PADCFG_PAD_GMAC_SYSCON_SHIFT 0x0
+#define PADCFG_PAD_GMAC_SYSCON_MASK GENMASK(1, 0)
+
+/* one dword include 4 gpios */
+#define GPIO_NUM_SHIFT 2
+#define GPIO_NUM_PER_REG 32
+#define OFFSET_PER_REG 4
+#define SYS_GPIO_NUM 64
+
+enum starfive_jh7110_sys_pads {
+ PAD_GPIO0 = 0,
+ PAD_GPIO1 = 1,
+ PAD_GPIO2 = 2,
+ PAD_GPIO3 = 3,
+ PAD_GPIO4 = 4,
+ PAD_GPIO5 = 5,
+ PAD_GPIO6 = 6,
+ PAD_GPIO7 = 7,
+ PAD_GPIO8 = 8,
+ PAD_GPIO9 = 9,
+ PAD_GPIO10 = 10,
+ PAD_GPIO11 = 11,
+ PAD_GPIO12 = 12,
+ PAD_GPIO13 = 13,
+ PAD_GPIO14 = 14,
+ PAD_GPIO15 = 15,
+ PAD_GPIO16 = 16,
+ PAD_GPIO17 = 17,
+ PAD_GPIO18 = 18,
+ PAD_GPIO19 = 19,
+ PAD_GPIO20 = 20,
+ PAD_GPIO21 = 21,
+ PAD_GPIO22 = 22,
+ PAD_GPIO23 = 23,
+ PAD_GPIO24 = 24,
+ PAD_GPIO25 = 25,
+ PAD_GPIO26 = 26,
+ PAD_GPIO27 = 27,
+ PAD_GPIO28 = 28,
+ PAD_GPIO29 = 29,
+ PAD_GPIO30 = 30,
+ PAD_GPIO31 = 31,
+ PAD_GPIO32 = 32,
+ PAD_GPIO33 = 33,
+ PAD_GPIO34 = 34,
+ PAD_GPIO35 = 35,
+ PAD_GPIO36 = 36,
+ PAD_GPIO37 = 37,
+ PAD_GPIO38 = 38,
+ PAD_GPIO39 = 39,
+ PAD_GPIO40 = 40,
+ PAD_GPIO41 = 41,
+ PAD_GPIO42 = 42,
+ PAD_GPIO43 = 43,
+ PAD_GPIO44 = 44,
+ PAD_GPIO45 = 45,
+ PAD_GPIO46 = 46,
+ PAD_GPIO47 = 47,
+ PAD_GPIO48 = 48,
+ PAD_GPIO49 = 49,
+ PAD_GPIO50 = 50,
+ PAD_GPIO51 = 51,
+ PAD_GPIO52 = 52,
+ PAD_GPIO53 = 53,
+ PAD_GPIO54 = 54,
+ PAD_GPIO55 = 55,
+ PAD_GPIO56 = 56,
+ PAD_GPIO57 = 57,
+ PAD_GPIO58 = 58,
+ PAD_GPIO59 = 59,
+ PAD_GPIO60 = 60,
+ PAD_GPIO61 = 61,
+ PAD_GPIO62 = 62,
+ PAD_GPIO63 = 63,
+ PAD_SD0_CLK = 64,
+ PAD_SD0_CMD = 65,
+ PAD_SD0_DATA0 = 66,
+ PAD_SD0_DATA1 = 67,
+ PAD_SD0_DATA2 = 68,
+ PAD_SD0_DATA3 = 69,
+ PAD_SD0_DATA4 = 70,
+ PAD_SD0_DATA5 = 71,
+ PAD_SD0_DATA6 = 72,
+ PAD_SD0_DATA7 = 73,
+ PAD_SD0_STRB = 74,
+ PAD_GMAC1_MDC = 75,
+ PAD_GMAC1_MDIO = 76,
+ PAD_GMAC1_RXD0 = 77,
+ PAD_GMAC1_RXD1 = 78,
+ PAD_GMAC1_RXD2 = 79,
+ PAD_GMAC1_RXD3 = 80,
+ PAD_GMAC1_RXDV = 81,
+ PAD_GMAC1_RXC = 82,
+ PAD_GMAC1_TXD0 = 83,
+ PAD_GMAC1_TXD1 = 84,
+ PAD_GMAC1_TXD2 = 85,
+ PAD_GMAC1_TXD3 = 86,
+ PAD_GMAC1_TXEN = 87,
+ PAD_GMAC1_TXC = 88,
+ PAD_QSPI_SCLK = 89,
+ PAD_QSPI_CSn0 = 90,
+ PAD_QSPI_DATA0 = 91,
+ PAD_QSPI_DATA1 = 92,
+ PAD_QSPI_DATA2 = 93,
+ PAD_QSPI_DATA3 = 94,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc starfive_jh7110_sys_pinctrl_pads[] = {
+ STARFIVE_PINCTRL_PIN(PAD_GPIO0),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO1),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO2),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO3),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO4),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO5),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO6),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO7),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO8),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO9),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO10),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO11),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO12),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO13),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO14),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO15),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO16),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO17),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO18),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO19),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO20),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO21),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO22),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO23),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO24),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO25),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO26),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO27),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO28),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO29),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO30),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO31),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO32),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO33),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO34),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO35),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO36),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO37),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO38),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO39),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO40),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO41),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO42),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO43),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO44),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO45),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO46),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO47),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO48),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO49),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO50),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO51),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO52),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO53),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO54),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO55),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO56),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO57),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO58),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO59),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO60),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO61),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO62),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO63),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_CLK),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_CMD),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA0),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA1),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA2),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA3),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA4),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA5),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA6),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA7),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_STRB),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_MDC),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_MDIO),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD0),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD1),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD2),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD3),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXDV),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXC),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD0),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD1),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD2),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD3),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXEN),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXC),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_SCLK),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_CSn0),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA0),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA1),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA2),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA3),
+};
+
+static int jh7110_sys_direction_input(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int offset, shift;
+ void __iomem *reg_doen;
+ u32 mask;
+
+ if (gpio >= gc->ngpio)
+ return -EINVAL;
+
+ offset = GET_GPO_REG_OFFSET(gpio);
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ mask = SYS_GPO_DOEN_MASK << shift;
+ reg_doen = chip->padctl_base + SYS_GPO_DOEN_CFG + offset;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ pinctrl_set_reg(reg_doen, 1, shift, mask);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int jh7110_sys_direction_output(struct gpio_chip *gc,
+ unsigned int gpio,
+ int value)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int offset, shift;
+ void __iomem *reg_doen, *reg_dout;
+ u32 mask_doen, mask_dout;
+
+ if (gpio >= gc->ngpio)
+ return -EINVAL;
+
+ offset = GET_GPO_REG_OFFSET(gpio);
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ mask_doen = SYS_GPO_DOEN_MASK << shift;
+ mask_dout = SYS_GPO_DOUT_MASK << shift;
+ reg_doen = chip->padctl_base + SYS_GPO_DOEN_CFG + offset;
+ reg_dout = chip->padctl_base + SYS_GPO_DOUT_CFG + offset;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ pinctrl_set_reg(reg_doen, 0, shift, mask_doen);
+
+ pinctrl_set_reg(reg_dout, value, shift, mask_dout);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int jh7110_sys_get_direction(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int doen;
+ unsigned int offset, shift;
+ void __iomem *reg_doen;
+ u32 mask;
+
+ if (gpio >= gc->ngpio)
+ return -EINVAL;
+
+ offset = GET_GPO_REG_OFFSET(gpio);
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ mask = SYS_GPO_DOEN_MASK << shift;
+ reg_doen = chip->padctl_base + SYS_GPO_DOEN_CFG + offset;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ doen = readl_relaxed(reg_doen);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return !!(doen & mask);
+}
+
+static int jh7110_sys_get_value(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ int value;
+ int tmp;
+
+ if (gpio >= gc->ngpio)
+ return -EINVAL;
+
+ if (gpio < GPIO_NUM_PER_REG) {
+ value = readl_relaxed(chip->padctl_base + GPIO_DIN_LOW);
+ tmp = 0;
+ } else {
+ value = readl_relaxed(chip->padctl_base + GPIO_DIN_HIGH);
+ tmp = GPIO_NUM_PER_REG;
+ }
+ return (value >> (gpio - tmp)) & 0x1;
+}
+
+static void jh7110_sys_set_value(struct gpio_chip *gc,
+ unsigned int gpio,
+ int value)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int offset, shift;
+ void __iomem *reg_dout;
+ u32 mask;
+
+ if (gpio >= gc->ngpio)
+ return;
+
+ offset = GET_GPO_REG_OFFSET(gpio);
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ mask = SYS_GPO_DOUT_MASK << shift;
+ reg_dout = chip->padctl_base + SYS_GPO_DOUT_CFG + offset;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ pinctrl_set_reg(reg_dout, value, shift, mask);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static int jh7110_sys_irq_set_type(struct irq_data *d,
+ unsigned int trigger)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *base = sfp->padctl_base +
+ OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+ u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+ u32 irq_type, edge_both, polarity;
+ unsigned long flags;
+
+ switch (trigger) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_type = 0; /* 0: level triggered */
+ edge_both = 0; /* 0: ignored */
+ polarity = 0; /* 0: high level */
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ irq_type = 0; /* 0: level triggered */
+ edge_both = 0; /* 0: ignored */
+ polarity = 1; /* 1: low level */
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = mask; /* 1: both edges */
+ polarity = 0; /* 0: ignored */
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = 0; /* 0: single edge */
+ polarity = mask; /* 1: rising edge */
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = 0; /* 0: single edge */
+ polarity = 0; /* 0: falling edge */
+ break;
+ }
+ if (trigger & IRQ_TYPE_EDGE_BOTH)
+ irq_set_handler_locked(d, handle_edge_irq);
+ else
+ irq_set_handler_locked(d, handle_level_irq);
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ irq_type |= readl_relaxed(base + GPIO_IS_LOW) & ~mask;
+ writel_relaxed(irq_type, base + GPIO_IS_LOW);
+
+ edge_both |= readl_relaxed(base + GPIO_IBE_LOW) & ~mask;
+ writel_relaxed(edge_both, base + GPIO_IBE_LOW);
+
+ polarity |= readl_relaxed(base + GPIO_IEV_LOW) & ~mask;
+ writel_relaxed(polarity, base + GPIO_IEV_LOW);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+ sfp->trigger[gpio] = trigger;
+ return 0;
+}
+
+/* chained_irq_{enter,exit} already mask the parent */
+static void jh7110_sys_irq_mask(struct irq_data *d)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
+ OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+ u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+ unsigned long flags;
+ u32 value;
+
+ if (gpio < 0 || gpio >= sfp->gc.ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ie) & ~mask;
+ writel_relaxed(value, ie);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_sys_irq_unmask(struct irq_data *d)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
+ OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+ u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+ unsigned long flags;
+ u32 value;
+
+ if (gpio < 0 || gpio >= sfp->gc.ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ie) | mask;
+ writel_relaxed(value, ie);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_sys_irq_ack(struct irq_data *d)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ic = sfp->padctl_base + GPIO_IC_LOW +
+ OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+ u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+ unsigned long flags;
+ u32 value;
+
+ if (gpio < 0 || gpio >= sfp->gc.ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value, ic);
+ writel_relaxed(value | mask, ic);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_sys_irq_mask_ack(struct irq_data *d)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
+ OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+ void __iomem *ic = sfp->padctl_base + GPIO_IC_LOW +
+ OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+ u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+ unsigned long flags;
+ u32 value;
+
+ if (gpio < 0 || gpio >= sfp->gc.ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ie) & ~mask;
+ writel_relaxed(value, ie);
+
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value, ic);
+ writel_relaxed(value | mask, ic);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static struct irq_chip jh7110_sys_irqchip = {
+ .name = "starfive-jh7110-sys-gpio",
+ .irq_ack = jh7110_sys_irq_ack,
+ .irq_mask_ack = jh7110_sys_irq_mask_ack,
+ .irq_set_type = jh7110_sys_irq_set_type,
+ .irq_mask = jh7110_sys_irq_mask,
+ .irq_unmask = jh7110_sys_irq_unmask,
+ .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static void jh7110_sys_irq_handler(struct irq_desc *desc)
+{
+ struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long mis;
+ unsigned int pin;
+
+ chained_irq_enter(chip, desc);
+
+ mis = readl_relaxed(sfp->padctl_base + GPIO_MIS_LOW);
+ for_each_set_bit(pin, &mis, GPIO_NUM_PER_REG)
+ generic_handle_domain_irq(sfp->gc.irq.domain, pin);
+
+ mis = readl_relaxed(sfp->padctl_base + GPIO_MIS_HIGH);
+ for_each_set_bit(pin, &mis, GPIO_NUM_PER_REG)
+ generic_handle_domain_irq(sfp->gc.irq.domain,
+ pin + GPIO_NUM_PER_REG);
+
+ chained_irq_exit(chip, desc);
+}
+
+static int jh7110_sys_init_hw(struct gpio_chip *gc)
+{
+ struct starfive_pinctrl *sfp = container_of(gc,
+ struct starfive_pinctrl, gc);
+
+ /* mask all GPIO interrupts */
+ writel_relaxed(0, sfp->padctl_base + GPIO_IE_LOW);
+ writel_relaxed(0, sfp->padctl_base + GPIO_IE_HIGH);
+ /* clear edge interrupt flags */
+ writel_relaxed(0, sfp->padctl_base + GPIO_IC_LOW);
+ writel_relaxed(0, sfp->padctl_base + GPIO_IC_HIGH);
+ writel_relaxed(~0U, sfp->padctl_base + GPIO_IC_LOW);
+ writel_relaxed(~0U, sfp->padctl_base + GPIO_IC_HIGH);
+ /* enable GPIO interrupts */
+ writel_relaxed(1, sfp->padctl_base + GPIO_EN);
+ return 0;
+}
+
+static int jh7110_sys_add_pin_ranges(struct gpio_chip *gc)
+{
+ struct starfive_pinctrl *sfp = container_of(gc,
+ struct starfive_pinctrl, gc);
+
+ sfp->gpios.name = sfp->gc.label;
+ sfp->gpios.base = sfp->gc.base;
+ /*
+ * sfp->gpios.pin_base depends on the chosen signal group
+ * and is set in starfive_probe()
+ */
+ sfp->gpios.npins = SYS_GPIO_NUM;
+ sfp->gpios.gc = &sfp->gc;
+ pinctrl_add_gpio_range(sfp->pctl_dev, &sfp->gpios);
+ return 0;
+}
+
+static int jh7110_sys_gpio_register(struct platform_device *pdev,
+ struct starfive_pinctrl *pctl)
+{
+ struct device *dev = &pdev->dev;
+ int ret, ngpio;
+ int loop;
+
+ ngpio = SYS_GPIO_NUM;
+
+ pctl->gc.direction_input = jh7110_sys_direction_input;
+ pctl->gc.direction_output = jh7110_sys_direction_output;
+ pctl->gc.get_direction = jh7110_sys_get_direction;
+ pctl->gc.get = jh7110_sys_get_value;
+ pctl->gc.set = jh7110_sys_set_value;
+ pctl->gc.add_pin_ranges = jh7110_sys_add_pin_ranges;
+ pctl->gc.base = 0;
+ pctl->gc.ngpio = ngpio;
+ pctl->gc.label = dev_name(dev);
+ pctl->gc.parent = dev;
+ pctl->gc.owner = THIS_MODULE;
+ pctl->enabled = 0;
+
+ platform_set_drvdata(pdev, pctl);
+
+ jh7110_sys_irqchip.name = pctl->gc.label;
+
+ pctl->gc.irq.chip = &jh7110_sys_irqchip;
+ pctl->gc.irq.parent_handler = jh7110_sys_irq_handler;
+ pctl->gc.irq.num_parents = 1;
+ pctl->gc.irq.parents = devm_kcalloc(dev, pctl->gc.irq.num_parents,
+ sizeof(*pctl->gc.irq.parents),
+ GFP_KERNEL);
+ if (!pctl->gc.irq.parents)
+ return -ENOMEM;
+ pctl->gc.irq.default_type = IRQ_TYPE_NONE;
+ pctl->gc.irq.handler = handle_bad_irq;
+ pctl->gc.irq.init_hw = jh7110_sys_init_hw;
+
+ if (IS_ENABLED(CONFIG_PM))
+ pm_runtime_enable(dev);
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0)
+ return ret;
+ pctl->gc.irq.parents[0] = ret;
+
+ ret = devm_gpiochip_add_data(dev, &pctl->gc, pctl);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "could not register gpiochip\n");
+
+ for (loop = 0; loop < SYS_GPIO_NUM; loop++) {
+ unsigned int v;
+ void __iomem *reg_ie = pctl->padctl_base +
+ SYS_GPIO_INPUT_ENABLE_REG + (loop << 2);
+
+ v = readl_relaxed(reg_ie);
+ v |= 0x1;
+ writel_relaxed(v, reg_ie);
+ }
+
+ dev_info(dev, "StarFive SYS GPIO chip registered %d GPIOs\n", ngpio);
+
+ return 0;
+}
+
+static int jh7110_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin_id,
+ unsigned long *config)
+{
+ struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
+ u32 value;
+
+ if (pin_reg->io_conf_reg == -1) {
+ dev_err(pctl->dev,
+ "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ value = readl_relaxed(pctl->padctl_base + pin_reg->io_conf_reg);
+ *config = value & 0xff;
+ return 0;
+}
+
+static int jh7110_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin_id,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
+ int i;
+ u32 value;
+ unsigned long flags;
+
+ if (pin_reg->io_conf_reg == -1) {
+ dev_err(pctl->dev,
+ "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ raw_spin_lock_irqsave(&pctl->lock, flags);
+ for (i = 0; i < num_configs; i++) {
+ value = readl_relaxed(pctl->padctl_base +
+ pin_reg->io_conf_reg);
+ value = value | (configs[i] & 0xFF);
+ writel_relaxed(value, pctl->padctl_base +
+ pin_reg->io_conf_reg);
+ }
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+ return 0;
+}
+
+static int jh7110_sys_pmx_set_one_pin_mux(struct starfive_pinctrl *pctl,
+ struct starfive_pin *pin)
+{
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ struct starfive_pin_config *pin_config = &pin->pin_config;
+ const struct starfive_pin_reg *pin_reg;
+ unsigned int gpio, pin_id;
+ int i;
+ unsigned long flags;
+ int n, shift;
+
+ gpio = pin->pin_config.gpio_num;
+ pin_id = pin->pin;
+ pin_reg = &pctl->pin_regs[pin_id];
+
+ raw_spin_lock_irqsave(&pctl->lock, flags);
+ if (pin_reg->func_sel_reg != -1) {
+ pinctrl_set_reg(pctl->padctl_base + pin_reg->func_sel_reg,
+ pin_config->pinmux_func,
+ pin_reg->func_sel_shift,
+ pin_reg->func_sel_mask);
+ }
+
+ shift = GET_GPO_CFG_SHIFT(gpio);
+ if (pin_reg->gpo_dout_reg != -1) {
+ pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
+ SYS_GPO_DOUT_MASK << shift, pin_config->gpio_dout << shift);
+ }
+
+ if (pin_reg->gpo_doen_reg != -1) {
+ pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
+ SYS_GPO_DOEN_MASK << shift, pin_config->gpio_doen << shift);
+ }
+
+ for (i = 0; i < pin_config->gpio_din_num; i++) {
+ n = pin_config->gpio_din_reg[i] >> 2;
+ shift = (pin_config->gpio_din_reg[i] & 3) << 3;
+ pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
+ SYS_GPI_DIN_MASK << shift, (gpio + 2) << shift);
+ }
+
+ if (pin_reg->syscon_reg != -1) {
+ pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
+ pin_config->syscon, PADCFG_PAD_GMAC_SYSCON_SHIFT,
+ PADCFG_PAD_GMAC_SYSCON_MASK);
+ }
+
+ if (pin_reg->pad_sel_reg != -1) {
+ pinctrl_set_reg(pctl->padctl_base + pin_reg->pad_sel_reg,
+ pin_config->padmux_func,
+ pin_reg->pad_sel_shift,
+ pin_reg->pad_sel_mask);
+ }
+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+ return 0;
+}
+
+static void jh7110_sys_parse_pin_config(struct starfive_pinctrl *pctl,
+ unsigned int *pins_id,
+ struct starfive_pin *pin_data,
+ const __be32 *list_p,
+ struct device_node *np)
+{
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ struct starfive_pin_reg *pin_reg;
+ const __be32 *list = list_p;
+ const __be32 *list_din;
+ int size;
+ int size_din;
+ int pin_size;
+ u32 value;
+ int i;
+ int n;
+
+ pin_size = sizeof(u32);
+ *pins_id = be32_to_cpu(*list);
+ pin_reg = &pctl->pin_regs[*pins_id];
+ pin_data->pin = *pins_id;
+
+ if (pin_data->pin > PAD_QSPI_DATA3) {
+ dev_err(pctl->dev, "err pin num = %d\n", pin_data->pin);
+ return;
+ }
+
+ if (pin_data->pin < PAD_GMAC1_MDC) {
+ pin_reg->io_conf_reg = (pin_data->pin * SYS_GPO_PDA_CFG_OFFSET)
+ + SYS_GPO_PDA_0_74_CFG;
+ } else if (pin_data->pin > PAD_GMAC1_TXC) {
+ pin_reg->io_conf_reg = (pin_data->pin * SYS_GPO_PDA_CFG_OFFSET)
+ + SYS_GPO_PDA_89_94_CFG;
+ }
+
+ if (!of_property_read_u32(np, "starfive,pin-ioconfig", &value))
+ pin_data->pin_config.io_config = value;
+
+ list = of_get_property(np, "starfive,pinmux", &size);
+ if (list) {
+ pin_reg->func_sel_reg = be32_to_cpu(*list++);
+ pin_reg->func_sel_shift = be32_to_cpu(*list++);
+ pin_reg->func_sel_mask = be32_to_cpu(*list++);
+ pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
+ }
+
+ list = of_get_property(np, "starfive,padmux", &size);
+ if (list) {
+ pin_reg->pad_sel_reg = be32_to_cpu(*list++);
+ pin_reg->pad_sel_shift = be32_to_cpu(*list++);
+ pin_reg->pad_sel_mask = be32_to_cpu(*list++);
+ pin_data->pin_config.padmux_func = be32_to_cpu(*list++);
+ }
+
+ list = of_get_property(np, "starfive,pin-syscon", &size);
+ if (list) {
+ pin_reg->syscon_reg = be32_to_cpu(*list++);
+ pin_data->pin_config.syscon = be32_to_cpu(*list++);
+ }
+
+ if (pin_data->pin < PAD_SD0_CLK) {
+ pin_data->pin_config.gpio_num = pin_data->pin;
+ n = pin_data->pin_config.gpio_num >> GPIO_NUM_SHIFT;
+
+ if (!of_property_read_u32(np, "starfive,pin-gpio-dout", &value)) {
+ pin_data->pin_config.gpio_dout = value;
+ pin_reg->gpo_dout_reg = info->dout_reg_base + n * 4;
+ }
+
+ if (!of_property_read_u32(np, "starfive,pin-gpio-doen", &value)) {
+ pin_data->pin_config.gpio_doen = value;
+ pin_reg->gpo_doen_reg = info->doen_reg_base + n * 4;
+ }
+
+ list_din = of_get_property(np, "starfive,pin-gpio-din", &size_din);
+ if (list_din) {
+ if (!size_din || size_din % pin_size) {
+ dev_err(pctl->dev,
+ "Invalid starfive,pin-gpio-din property in node\n");
+ return;
+ }
+
+ pin_data->pin_config.gpio_din_num = size_din / pin_size;
+ pin_data->pin_config.gpio_din_reg =
+ devm_kcalloc(pctl->dev,
+ pin_data->pin_config.gpio_din_num,
+ sizeof(s32),
+ GFP_KERNEL);
+
+ for (i = 0; i < pin_data->pin_config.gpio_din_num; i++) {
+ value = be32_to_cpu(*list_din++);
+ pin_data->pin_config.gpio_din_reg[i] = value;
+ }
+ }
+ }
+}
+
+static const struct starfive_pinctrl_soc_info jh7110_sys_pinctrl_info = {
+ .pins = starfive_jh7110_sys_pinctrl_pads,
+ .npins = ARRAY_SIZE(starfive_jh7110_sys_pinctrl_pads),
+ .flags = 1,
+ .dout_reg_base = SYS_GPO_DOUT_CFG,
+ .doen_reg_base = SYS_GPO_DOEN_CFG,
+ .din_reg_base = SYS_GPI_DIN_CFG,
+ .starfive_pinconf_get = jh7110_pinconf_get,
+ .starfive_pinconf_set = jh7110_pinconf_set,
+ .starfive_pmx_set_one_pin_mux = jh7110_sys_pmx_set_one_pin_mux,
+ .starfive_gpio_register = jh7110_sys_gpio_register,
+ .starfive_pinctrl_parse_pin = jh7110_sys_parse_pin_config,
+};
+
+static const struct of_device_id jh7110_sys_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jh7110-sys-pinctrl",
+ .data = &jh7110_sys_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+
+static int jh7110_sys_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct starfive_pinctrl_soc_info *pinctrl_info;
+
+ pinctrl_info = of_device_get_match_data(&pdev->dev);
+ if (!pinctrl_info)
+ return -ENODEV;
+
+ return starfive_pinctrl_probe(pdev, pinctrl_info);
+}
+
+static struct platform_driver jh7110_sys_pinctrl_driver = {
+ .driver = {
+ .name = "starfive-jh7110-sys-pinctrl",
+ .of_match_table = of_match_ptr(jh7110_sys_pinctrl_of_match),
+ },
+ .probe = jh7110_sys_pinctrl_probe,
+};
+
+static int __init jh7110_sys_pinctrl_init(void)
+{
+ return platform_driver_register(&jh7110_sys_pinctrl_driver);
+}
+arch_initcall(jh7110_sys_pinctrl_init);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC sys controller");
+MODULE_AUTHOR("Jenny Zhang <[email protected]>");
+MODULE_AUTHOR("Jianlong Huang <[email protected]>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c
new file mode 100644
index 000000000000..80cf74ebc0e2
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.c
@@ -0,0 +1,539 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive.h"
+
+static inline const struct group_desc *
+starfive_pinctrl_find_group_by_name(struct pinctrl_dev *pctldev,
+ const char *name)
+{
+ const struct group_desc *grp = NULL;
+ int i;
+
+ for (i = 0; i < pctldev->num_groups; i++) {
+ grp = pinctrl_generic_get_group(pctldev, i);
+ if (grp && !strcmp(grp->name, name))
+ break;
+ }
+
+ return grp;
+}
+
+static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s,
+ unsigned int offset)
+{
+ seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **maps,
+ unsigned int *num_maps)
+{
+ struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = sfp->gc.parent;
+ const struct starfive_pinctrl_soc_info *info = sfp->info;
+ struct starfive_pin *pin_data;
+ struct device_node *child;
+ struct pinctrl_map *map;
+ struct group_desc *grp;
+ const char **pgnames;
+ const char *grpname;
+ int ngroups;
+ int nmaps;
+ int ret;
+ int *pins_id;
+ int psize, pin_size;
+ int size = 0;
+ int offset = 0;
+ const __be32 *list;
+ int i, child_num_pins;
+
+ nmaps = 0;
+ ngroups = 0;
+ pin_size = STARFIVE_PINS_SIZE;
+
+ for_each_child_of_node(np, child) {
+ list = of_get_property(child, "starfive,pins", &psize);
+ if (!list) {
+ dev_err(sfp->dev,
+ "no starfive,pins and pins property in node %pOF\n", np);
+ return -EINVAL;
+ }
+ size += psize;
+ }
+
+ if (!size || size % pin_size) {
+ dev_err(sfp->dev,
+ "Invalid starfive,pins or pins property in node %pOF\n", np);
+ return -EINVAL;
+ }
+
+ nmaps = size / pin_size * 2;
+ ngroups = size / pin_size;
+
+ pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
+ if (!pgnames)
+ return -ENOMEM;
+
+ map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
+ if (!map)
+ return -ENOMEM;
+
+ grp = devm_kzalloc(sfp->dev, sizeof(struct group_desc), GFP_KERNEL);
+ if (!grp) {
+ of_node_put(child);
+ return -ENOMEM;
+ }
+
+ grp->data = devm_kcalloc(sfp->dev,
+ ngroups, sizeof(struct starfive_pin),
+ GFP_KERNEL);
+ grp->pins = devm_kcalloc(sfp->dev,
+ ngroups, sizeof(int),
+ GFP_KERNEL);
+ if (!grp->pins || !grp->data)
+ return -ENOMEM;
+
+ nmaps = 0;
+ ngroups = 0;
+ mutex_lock(&sfp->mutex);
+
+ for_each_child_of_node(np, child) {
+ grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
+ if (!grpname) {
+ ret = -ENOMEM;
+ goto put_child;
+ }
+
+ pgnames[ngroups++] = grpname;
+ map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+ map[nmaps].data.mux.function = np->name;
+ map[nmaps].data.mux.group = grpname;
+ nmaps += 1;
+
+ list = of_get_property(child, "starfive,pins", &psize);
+ if (!list) {
+ dev_err(sfp->dev,
+ "no starfive,pins and pins property in node %pOF\n", np);
+ goto put_child;
+ }
+ child_num_pins = psize / pin_size;
+ grp->name = grpname;
+ grp->num_pins = child_num_pins;
+ for (i = 0; i < child_num_pins; i++) {
+ pin_data = &((struct starfive_pin *)(grp->data))[i + offset];
+ pins_id = &grp->pins[i + offset];
+
+ if (!info->starfive_pinctrl_parse_pin) {
+ dev_err(sfp->dev,
+ "pinmux ops lacks necessary functions\n");
+ goto put_child;
+ }
+
+ info->starfive_pinctrl_parse_pin(sfp,
+ pins_id, pin_data, list, child);
+ map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ map[nmaps].data.configs.group_or_pin =
+ pin_get_name(pctldev, pin_data->pin);
+ map[nmaps].data.configs.configs =
+ &pin_data->pin_config.io_config;
+ map[nmaps].data.configs.num_configs = 1;
+ nmaps += 1;
+
+ list++;
+ }
+ offset += i;
+
+ ret = pinctrl_generic_add_group(pctldev, grpname, pins_id,
+ child_num_pins, pin_data);
+ if (ret < 0) {
+ dev_err(dev, "error adding group %s: %d\n", grpname, ret);
+ goto put_child;
+ }
+ }
+
+ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
+ if (ret < 0) {
+ dev_err(dev, "error adding function %s: %d\n", np->name, ret);
+ goto free_map;
+ }
+
+ *maps = map;
+ *num_maps = nmaps;
+ mutex_unlock(&sfp->mutex);
+ return 0;
+
+put_child:
+ of_node_put(child);
+free_map:
+ pinctrl_utils_free_map(pctldev, map, nmaps);
+ mutex_unlock(&sfp->mutex);
+ return ret;
+}
+
+static void starfive_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map,
+ unsigned int num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops starfive_pctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .pin_dbg_show = starfive_pin_dbg_show,
+ .dt_node_to_map = starfive_dt_node_to_map,
+ .dt_free_map = starfive_dt_free_map,
+};
+
+static int starfive_pmx_set(struct pinctrl_dev *pctldev,
+ unsigned int selector, unsigned int group)
+{
+ struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+ struct function_desc *func;
+ struct group_desc *grp;
+ struct starfive_pin *pin;
+ unsigned int npins;
+ int i, err;
+
+ grp = pinctrl_generic_get_group(pctldev, group);
+ if (!grp)
+ return -EINVAL;
+
+ func = pinmux_generic_get_function(pctldev, selector);
+ if (!func)
+ return -EINVAL;
+
+ npins = grp->num_pins;
+
+ dev_dbg(pctl->dev, "enable function %s group %s\n",
+ func->name, grp->name);
+
+ for (i = 0; i < npins; i++) {
+ pin = &((struct starfive_pin *)(grp->data))[i];
+ if (info->starfive_pmx_set_one_pin_mux) {
+ err = info->starfive_pmx_set_one_pin_mux(pctl, pin);
+ if (err)
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+const struct pinmux_ops starfive_pmx_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = starfive_pmx_set,
+};
+
+static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin_id, unsigned long *config)
+{
+ struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+
+ if (info->starfive_pinconf_get)
+ return info->starfive_pinconf_get(pctldev, pin_id, config);
+
+ return 0;
+}
+
+static int starfive_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin_id, unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = pctl->info;
+
+ if (info->starfive_pinconf_set)
+ return info->starfive_pinconf_set(pctldev, pin_id,
+ configs, num_configs);
+ return 0;
+}
+
+static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int pin_id)
+{
+ struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pin_reg *pin_reg;
+ unsigned long config;
+ int ret;
+
+ pin_reg = &pctl->pin_regs[pin_id];
+ if (pin_reg->io_conf_reg == -1) {
+ seq_puts(s, "N/A");
+ return;
+ }
+
+ ret = starfive_pinconf_get(pctldev, pin_id, &config);
+ if (ret)
+ return;
+ seq_printf(s, "0x%lx", config);
+}
+
+static void starfive_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int group)
+{
+ struct group_desc *grp;
+ unsigned long config;
+ const char *name;
+ int i, ret;
+
+ if (group >= pctldev->num_groups)
+ return;
+
+ seq_puts(s, "\n");
+ grp = pinctrl_generic_get_group(pctldev, group);
+ if (!grp)
+ return;
+
+ for (i = 0; i < grp->num_pins; i++) {
+ struct starfive_pin *pin = &((struct starfive_pin *)(grp->data))[i];
+
+ name = pin_get_name(pctldev, pin->pin);
+ ret = starfive_pinconf_get(pctldev, pin->pin, &config);
+ if (ret)
+ return;
+ seq_printf(s, " %s: 0x%lx\n", name, config);
+ }
+}
+
+static const struct pinconf_ops starfive_pinconf_ops = {
+ .pin_config_get = starfive_pinconf_get,
+ .pin_config_set = starfive_pinconf_set,
+ .pin_config_dbg_show = starfive_pinconf_dbg_show,
+ .pin_config_group_dbg_show = starfive_pinconf_group_dbg_show,
+};
+
+static void starfive_disable_clock(void *data)
+{
+ clk_disable_unprepare(data);
+}
+
+void pinctrl_write_reg(void __iomem *addr, u32 mask, u32 val)
+{
+ u32 value;
+
+ value = readl_relaxed(addr);
+ value &= ~mask;
+ value |= (val & mask);
+ writel_relaxed(value, addr);
+}
+
+uint32_t pinctrl_get_reg(void __iomem *addr, u32 shift, u32 mask)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(addr);
+ tmp = (tmp & mask) >> shift;
+ return tmp;
+}
+
+void pinctrl_set_reg(void __iomem *addr, u32 data, u32 shift, u32 mask)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(addr);
+ tmp &= ~mask;
+ tmp |= (data << shift) & mask;
+ writel_relaxed(tmp, addr);
+}
+
+struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+
+ return container_of(gc, struct starfive_pinctrl, gc);
+}
+
+struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+
+ return container_of(gc, struct starfive_pinctrl, gc);
+}
+
+int starfive_pinctrl_probe(struct platform_device *pdev,
+ const struct starfive_pinctrl_soc_info *info)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl_desc *starfive_pinctrl_desc;
+ struct starfive_pinctrl *pctl;
+ struct resource *res;
+ struct reset_control *rst;
+ struct clk *clk;
+ int ret, i;
+ u32 value;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+ if (!pctl)
+ return -ENOMEM;
+
+ pctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
+ sizeof(*pctl->pin_regs),
+ GFP_KERNEL);
+ if (!pctl->pin_regs)
+ return -ENOMEM;
+
+ for (i = 0; i < info->npins; i++) {
+ pctl->pin_regs[i].io_conf_reg = -1;
+ pctl->pin_regs[i].gpo_dout_reg = -1;
+ pctl->pin_regs[i].gpo_doen_reg = -1;
+ pctl->pin_regs[i].func_sel_reg = -1;
+ pctl->pin_regs[i].syscon_reg = -1;
+ pctl->pin_regs[i].pad_sel_reg = -1;
+ }
+
+ pctl->padctl_base = devm_platform_ioremap_resource_byname(pdev, "control");
+ if (IS_ERR(pctl->padctl_base))
+ return PTR_ERR(pctl->padctl_base);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
+ if (res) {
+ pctl->gpio_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pctl->gpio_base))
+ return PTR_ERR(pctl->gpio_base);
+ }
+
+ clk = devm_clk_get_optional(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
+
+ rst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(rst))
+ return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
+
+ if (clk) {
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not enable clock\n");
+
+ ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * We don't want to assert reset and risk undoing pin muxing for the
+ * early boot serial console, but let's make sure the reset line is
+ * deasserted in case someone runs a really minimal bootloader.
+ */
+ ret = reset_control_deassert(rst);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not deassert reset\n");
+
+ if (info->starfive_iopad_sel_func) {
+ ret = info->starfive_iopad_sel_func(pdev, pctl, value);
+ if (ret)
+ return ret;
+ }
+
+ starfive_pinctrl_desc = devm_kzalloc(&pdev->dev,
+ sizeof(*starfive_pinctrl_desc),
+ GFP_KERNEL);
+ if (!starfive_pinctrl_desc)
+ return -ENOMEM;
+
+ raw_spin_lock_init(&pctl->lock);
+
+ starfive_pinctrl_desc->name = dev_name(&pdev->dev);
+ starfive_pinctrl_desc->pins = info->pins;
+ starfive_pinctrl_desc->npins = info->npins;
+ starfive_pinctrl_desc->pctlops = &starfive_pctrl_ops;
+ starfive_pinctrl_desc->pmxops = &starfive_pmx_ops;
+ starfive_pinctrl_desc->confops = &starfive_pinconf_ops;
+ starfive_pinctrl_desc->owner = THIS_MODULE;
+
+ mutex_init(&pctl->mutex);
+
+ pctl->info = info;
+ pctl->dev = &pdev->dev;
+ platform_set_drvdata(pdev, pctl);
+ pctl->gc.parent = dev;
+ ret = devm_pinctrl_register_and_init(&pdev->dev,
+ starfive_pinctrl_desc, pctl,
+ &pctl->pctl_dev);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "could not register starfive pinctrl driver\n");
+ return ret;
+ }
+
+ ret = pinctrl_enable(pctl->pctl_dev);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "pin controller failed to start\n");
+ return ret;
+ }
+
+ if (info->starfive_gpio_register) {
+ ret = info->starfive_gpio_register(pdev, pctl);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "starfive_gpio_register failed to register\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(starfive_pinctrl_probe);
+
+static int __maybe_unused starfive_pinctrl_suspend(struct device *dev)
+{
+ struct starfive_pinctrl *pctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(pctl->pctl_dev);
+}
+
+static int __maybe_unused starfive_pinctrl_resume(struct device *dev)
+{
+ struct starfive_pinctrl *pctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(pctl->pctl_dev);
+}
+
+const struct dev_pm_ops starfive_pinctrl_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(starfive_pinctrl_suspend,
+ starfive_pinctrl_resume)
+};
+EXPORT_SYMBOL_GPL(starfive_pinctrl_pm_ops);
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC");
+MODULE_AUTHOR("Jenny Zhang <[email protected]>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.h b/drivers/pinctrl/starfive/pinctrl-starfive.h
new file mode 100644
index 000000000000..8b956d07baae
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DRIVERS_PINCTRL_STARFIVE_H__
+#define __DRIVERS_PINCTRL_STARFIVE_H__
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+
+#define MAX_GPIO 64
+#define STARFIVE_PINS_SIZE 4
+
+/* 8 bits for each gpio */
+#define GPIO_BYTE_SHIFT 3
+#define GET_GPO_CFG_SHIFT(gpio) (((gpio) & 0x3) << GPIO_BYTE_SHIFT)
+#define GET_GPO_REG_OFFSET(gpio) ((gpio) & ~0x3)
+
+struct platform_device;
+
+extern const struct pinmux_ops starfive_pmx_ops;
+extern const struct dev_pm_ops starfive_pinctrl_pm_ops;
+
+struct starfive_pin_config {
+ unsigned long io_config;
+ u32 pinmux_func;
+ u32 gpio_num;
+ u32 gpio_dout;
+ u32 gpio_doen;
+ u32 gpio_din_num;
+ s32 *gpio_din_reg;
+ s32 syscon;
+ s32 padmux_func;
+};
+
+struct starfive_pin {
+ unsigned int pin;
+ struct starfive_pin_config pin_config;
+};
+
+struct starfive_pin_reg {
+ s32 io_conf_reg;
+ s32 gpo_dout_reg;
+ s32 gpo_doen_reg;
+ s32 func_sel_reg;
+ s32 func_sel_shift;
+ s32 func_sel_mask;
+ s32 syscon_reg;
+ s32 pad_sel_reg;
+ s32 pad_sel_shift;
+ s32 pad_sel_mask;
+};
+
+struct starfive_iopad_sel_func_inf {
+ unsigned int padctl_gpio_base;
+ unsigned int padctl_gpio0;
+};
+
+struct starfive_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl_dev;
+ void __iomem *padctl_base;
+ void __iomem *gpio_base;
+ unsigned int padctl_gpio_base;
+ unsigned int padctl_gpio0;
+ const struct starfive_pinctrl_soc_info *info;
+ struct starfive_pin_reg *pin_regs;
+ unsigned int group_index;
+
+ struct mutex mutex;
+ raw_spinlock_t lock;
+
+ struct gpio_chip gc;
+ struct pinctrl_gpio_range gpios;
+ unsigned long enabled;
+ unsigned int trigger[MAX_GPIO];
+};
+
+struct starfive_pinctrl_soc_info {
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ unsigned int flags;
+
+ /*gpio dout/doen/din register*/
+ unsigned int dout_reg_base;
+ unsigned int dout_reg_offset;
+ unsigned int doen_reg_base;
+ unsigned int doen_reg_offset;
+ unsigned int din_reg_base;
+ unsigned int din_reg_offset;
+
+ /* sel-function */
+ int (*starfive_iopad_sel_func)(struct platform_device *pdev,
+ struct starfive_pinctrl *ipctl,
+ unsigned int func_id);
+ /* generic pinconf */
+ int (*starfive_pinconf_get)(struct pinctrl_dev *pctldev,
+ unsigned int pin_id,
+ unsigned long *config);
+ int (*starfive_pinconf_set)(struct pinctrl_dev *pctldev,
+ unsigned int pin_id,
+ unsigned long *configs,
+ unsigned int num_configs);
+
+ /* generic pinmux */
+ int (*starfive_pmx_set_one_pin_mux)(struct starfive_pinctrl *ipctl,
+ struct starfive_pin *pin);
+ /* gpio chip */
+ int (*starfive_gpio_register)(struct platform_device *pdev,
+ struct starfive_pinctrl *ipctl);
+ void (*starfive_pinctrl_parse_pin)(struct starfive_pinctrl *ipctl,
+ unsigned int *pins_id,
+ struct starfive_pin *pin_data,
+ const __be32 *list_p,
+ struct device_node *np);
+};
+
+#define STARFIVE_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+int starfive_pinctrl_probe(struct platform_device *pdev,
+ const struct starfive_pinctrl_soc_info *info);
+void pinctrl_write_reg(void __iomem *addr, u32 mask, u32 val);
+uint32_t pinctrl_get_reg(void __iomem *addr, u32 shift, u32 mask);
+void pinctrl_set_reg(void __iomem *addr, u32 data, u32 shift, u32 mask);
+struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc);
+struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d);
+
+#endif /* __DRIVERS_PINCTRL_STARFIVE_H__ */
--
2.17.1
From: Jianlong Huang <[email protected]>
Add pinctrl bindings for StarFive JH7110 SoC.
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../pinctrl/starfive,jh7110-pinctrl.yaml | 202 ++++++++++++++++++
1 file changed, 202 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
new file mode 100644
index 000000000000..482012ad8a14
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
@@ -0,0 +1,202 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Pin Controller Device Tree Bindings
+
+description: |
+ Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
+
+maintainers:
+ - Jianlong Huang <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - starfive,jh7110-sys-pinctrl
+ - starfive,jh7110-aon-pinctrl
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: control
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ interrupts:
+ maxItems: 1
+ description: The GPIO parent interrupt.
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ ngpios:
+ enum:
+ - 64
+ - 4
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - "#gpio-cells"
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+
+patternProperties:
+ '-[0-9]+$':
+ type: object
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ muxer configuration, system signal configuration, pin groups for
+ vin/vout module, pin voltage, mux functions for output, mux functions
+ for output enable, mux functions for input.
+
+ properties:
+ starfive,pins:
+ description: |
+ The list of pin identifiers that properties in the node apply to.
+ This should be set using the PAD_GPIOX macros.
+ This has to be specified.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 63
+
+ starfive,pinmux:
+ description: |
+ The list of GPIOs and their mux functions that properties in the
+ node apply to. This should be set using the PAD_GPIOX_FUNC_SEL
+ macro with its value.
+ This is optional for some pins.
+ The value of PAD_GPIOX_FUNC_SEL macro can selects:
+ 0: GPIOX mux function 0,
+ 1: GPIOX mux function 1,
+ 2: GPIOX mux function 2.
+
+ starfive,pin-ioconfig:
+ description: |
+ This is used to configure the core settings of system signals.
+ The combination of GPIO_IE or GPIO_DS or GPIO_PU or GPIO_PD or
+ GPIO_SLEW or GPIO_SMT or GPIO_POS.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ starfive,padmux:
+ description: |
+ The padmux is for vin/vout module to select pin groups.
+ 0: vout will be set at pins from PAD_GPIO7 to PAD_GPIO34,
+ when PAD_GPIOX_FUNC_SEL is set as 1.
+ vin will be set at pins from PAD_GPIO6 to PAD_GPIO20.
+ when PAD_GPIOX_FUNC_SEL is set as 2.
+ 1: vout will be set at pins from PAD_GPIO36 to PAD_GPIO63,
+ when PAD_GPIOX_FUNC_SEL is set as 1.
+ vin will be set at pins from PAD_GPIO21 to PAD_GPIO35.
+ when PAD_GPIOX_FUNC_SEL is set as 2.
+ 2: vin will be set at pins from PAD_GPIO36 to PAD_GPIO50,
+ when PAD_GPIOX_FUNC_SEL is set as 2
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ starfive,pin-syscon:
+ description: |
+ This is used to set pin voltage,
+ 0: 3.3V, 1: 2.5V, 2: 1.8V.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ starfive,pin-gpio-dout:
+ description: |
+ This is used to set their mux functions for output.
+ This should be set using the GPO_XXX macro,
+ such as GPO_LOW, GPO_UART0_SOUT.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 107
+
+ starfive,pin-gpio-doen:
+ description: |
+ This is used to set their mux functions for output enable.
+ This should be set using the OEN_XXX macro,
+ such as OEN_LOW, OEN_I2C0_IC_CLK_OE.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 49
+
+ starfive,pin-gpio-din:
+ description: |
+ This is used to set their mux functions for input.
+ This should be set using the GPI_XXX macro,
+ such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 90
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive-jh7110-sys.h>
+ #include <dt-bindings/reset/starfive-jh7110.h>
+ #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+
+ gpio: gpio@13040000 {
+ compatible = "starfive,jh7110-sys-pinctrl";
+ reg = <0x0 0x13040000 0x0 0x10000>;
+ reg-names = "control";
+ clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
+ resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
+ interrupts = <86>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ ngpios = <64>;
+ status = "okay";
+
+ uart0_pins: uart0-pins {
+ uart0-pins-tx {
+ starfive,pins = <PAD_GPIO5>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ uart0-pins-rx {
+ starfive,pins = <PAD_GPIO6>;
+ starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_UART0_SIN>;
+ };
+ };
+ };
+
+ &uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+ };
+
+...
--
2.17.1
From: Jianlong Huang <[email protected]>
Add pinctrl definitions for StarFive JH7110 SoC.
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
.../pinctrl/pinctrl-starfive-jh7110.h | 931 ++++++++++++++++++
1 file changed, 931 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
new file mode 100644
index 000000000000..159cfcf6b915
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
@@ -0,0 +1,931 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+
+/* aon_iomux pin */
+#define PAD_TESTEN 0
+#define PAD_RGPIO0 1
+#define PAD_RGPIO1 2
+#define PAD_RGPIO2 3
+#define PAD_RGPIO3 4
+#define PAD_RSTN 5
+#define PAD_GMAC0_MDC 6
+#define PAD_GMAC0_MDIO 7
+#define PAD_GMAC0_RXD0 8
+#define PAD_GMAC0_RXD1 9
+#define PAD_GMAC0_RXD2 10
+#define PAD_GMAC0_RXD3 11
+#define PAD_GMAC0_RXDV 12
+#define PAD_GMAC0_RXC 13
+#define PAD_GMAC0_TXD0 14
+#define PAD_GMAC0_TXD1 15
+#define PAD_GMAC0_TXD2 16
+#define PAD_GMAC0_TXD3 17
+#define PAD_GMAC0_TXEN 18
+#define PAD_GMAC0_TXC 19
+
+/* aon_iomux dout */
+#define GPO_AON_CLK_32K_OUT 2
+#define GPO_AON_PTC0_PWM4 3
+#define GPO_AON_PTC0_PWM5 4
+#define GPO_AON_PTC0_PWM6 5
+#define GPO_AON_PTC0_PWM7 6
+#define GPO_AON_CLK_GCLK0 7
+#define GPO_AON_CLK_GCLK1 8
+#define GPO_AON_CLK_GCLK2 9
+
+/* aon_iomux doen */
+#define OEN_AON_PTC0_OE_N_4 2
+#define OEN_AON_PTC0_OE_N_5 3
+#define OEN_AON_PTC0_OE_N_6 4
+#define OEN_AON_PTC0_OE_N_7 5
+
+/* aon_iomux gin */
+#define GPI_AON_PMU_GPIO_WAKEUP_0 0
+#define GPI_AON_PMU_GPIO_WAKEUP_1 1
+#define GPI_AON_PMU_GPIO_WAKEUP_2 2
+#define GPI_AON_PMU_GPIO_WAKEUP_3 3
+
+/* aon_iomux gmac0 syscon */
+#define PADCFG_PAD_GMAC0_MDC_SYSCON 0x58
+#define PADCFG_PAD_GMAC0_MDIO_SYSCON 0x5c
+#define PADCFG_PAD_GMAC0_RXD0_SYSCON 0x60
+#define PADCFG_PAD_GMAC0_RXD1_SYSCON 0x64
+#define PADCFG_PAD_GMAC0_RXD2_SYSCON 0x68
+#define PADCFG_PAD_GMAC0_RXD3_SYSCON 0x6c
+#define PADCFG_PAD_GMAC0_RXDV_SYSCON 0x70
+#define PADCFG_PAD_GMAC0_RXC_SYSCON 0x74
+#define PADCFG_PAD_GMAC0_TXD0_SYSCON 0x78
+#define PADCFG_PAD_GMAC0_TXD1_SYSCON 0x7c
+#define PADCFG_PAD_GMAC0_TXD2_SYSCON 0x80
+#define PADCFG_PAD_GMAC0_TXD3_SYSCON 0x84
+#define PADCFG_PAD_GMAC0_TXEN_SYSCON 0x88
+#define PADCFG_PAD_GMAC0_TXC_SYSCON 0x8c
+
+/* aon_iomux func sel */
+#define AON_IOMUX_CFGSAIF_144_ADDR 0x90
+#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT 0x0
+#define PAD_GMAC0_RXC_FUNC_SEL_MASK 0x3
+
+#define PAD_GMAC0_RXC_FUNC_SEL \
+ AON_IOMUX_CFGSAIF_144_ADDR \
+ PAD_GMAC0_RXC_FUNC_SEL_SHIFT \
+ PAD_GMAC0_RXC_FUNC_SEL_MASK
+
+/* sys_iomux pin */
+#define PAD_GPIO0 0
+#define PAD_GPIO1 1
+#define PAD_GPIO2 2
+#define PAD_GPIO3 3
+#define PAD_GPIO4 4
+#define PAD_GPIO5 5
+#define PAD_GPIO6 6
+#define PAD_GPIO7 7
+#define PAD_GPIO8 8
+#define PAD_GPIO9 9
+#define PAD_GPIO10 10
+#define PAD_GPIO11 11
+#define PAD_GPIO12 12
+#define PAD_GPIO13 13
+#define PAD_GPIO14 14
+#define PAD_GPIO15 15
+#define PAD_GPIO16 16
+#define PAD_GPIO17 17
+#define PAD_GPIO18 18
+#define PAD_GPIO19 19
+#define PAD_GPIO20 20
+#define PAD_GPIO21 21
+#define PAD_GPIO22 22
+#define PAD_GPIO23 23
+#define PAD_GPIO24 24
+#define PAD_GPIO25 25
+#define PAD_GPIO26 26
+#define PAD_GPIO27 27
+#define PAD_GPIO28 28
+#define PAD_GPIO29 29
+#define PAD_GPIO30 30
+#define PAD_GPIO31 31
+#define PAD_GPIO32 32
+#define PAD_GPIO33 33
+#define PAD_GPIO34 34
+#define PAD_GPIO35 35
+#define PAD_GPIO36 36
+#define PAD_GPIO37 37
+#define PAD_GPIO38 38
+#define PAD_GPIO39 39
+#define PAD_GPIO40 40
+#define PAD_GPIO41 41
+#define PAD_GPIO42 42
+#define PAD_GPIO43 43
+#define PAD_GPIO44 44
+#define PAD_GPIO45 45
+#define PAD_GPIO46 46
+#define PAD_GPIO47 47
+#define PAD_GPIO48 48
+#define PAD_GPIO49 49
+#define PAD_GPIO50 50
+#define PAD_GPIO51 51
+#define PAD_GPIO52 52
+#define PAD_GPIO53 53
+#define PAD_GPIO54 54
+#define PAD_GPIO55 55
+#define PAD_GPIO56 56
+#define PAD_GPIO57 57
+#define PAD_GPIO58 58
+#define PAD_GPIO59 59
+#define PAD_GPIO60 60
+#define PAD_GPIO61 61
+#define PAD_GPIO62 62
+#define PAD_GPIO63 63
+#define PAD_SD0_CLK 64
+#define PAD_SD0_CMD 65
+#define PAD_SD0_DATA0 66
+#define PAD_SD0_DATA1 67
+#define PAD_SD0_DATA2 68
+#define PAD_SD0_DATA3 69
+#define PAD_SD0_DATA4 70
+#define PAD_SD0_DATA5 71
+#define PAD_SD0_DATA6 72
+#define PAD_SD0_DATA7 73
+#define PAD_SD0_STRB 74
+#define PAD_GMAC1_MDC 75
+#define PAD_GMAC1_MDIO 76
+#define PAD_GMAC1_RXD0 77
+#define PAD_GMAC1_RXD1 78
+#define PAD_GMAC1_RXD2 79
+#define PAD_GMAC1_RXD3 80
+#define PAD_GMAC1_RXDV 81
+#define PAD_GMAC1_RXC 82
+#define PAD_GMAC1_TXD0 83
+#define PAD_GMAC1_TXD1 84
+#define PAD_GMAC1_TXD2 85
+#define PAD_GMAC1_TXD3 86
+#define PAD_GMAC1_TXEN 87
+#define PAD_GMAC1_TXC 88
+#define PAD_QSPI_SCLK 89
+#define PAD_QSPI_CSn0 90
+#define PAD_QSPI_DATA0 91
+#define PAD_QSPI_DATA1 92
+#define PAD_QSPI_DATA2 93
+#define PAD_QSPI_DATA3 94
+
+#define GPO_LOW 0
+#define GPO_HIGH 1
+#define GPO_WAVE511_0_O_UART_TXSOUT 2
+#define GPO_CAN0_CTRL_STBY 3
+#define GPO_CAN0_CTRL_TST_NEXT_BIT 4
+#define GPO_CAN0_CTRL_TST_SAMPLE_POINT 5
+#define GPO_CAN0_CTRL_TXD 6
+#define GPO_USB0_DRIVE_VBUS_IO 7
+#define GPO_QSPI0_CSN1 8
+#define GPO_SPDIF0_SPDIFO 9
+#define GPO_HDMI0_CEC_SDA_OUT 10
+#define GPO_HDMI0_DDC_SCL_OUT 11
+#define GPO_HDMI0_DDC_SDA_OUT 12
+#define GPO_WDT0_WDOGRES 13
+#define GPO_I2C0_IC_CLK_OUT_A 14
+#define GPO_I2C0_IC_DATA_OUT_A 15
+#define GPO_SDIO0_BACK_END_POWER 16
+#define GPO_SDIO0_CARD_POWER_EN 17
+#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N 18
+#define GPO_SDIO0_RST_N 19
+#define GPO_UART0_SOUT 20
+#define GPO_JTAG_DSP_TDO 21
+#define GPO_JTAG_CPU_CERTIFICATION_TDO 22
+#define GPO_PDM_4MIC0_DMIC_MCLK 23
+#define GPO_PTC0_PWM_0 24
+#define GPO_PTC0_PWM_1 25
+#define GPO_PTC0_PWM_2 26
+#define GPO_PTC0_PWM_3 27
+#define GPO_PWMDAC0_LEFT_OUTPUT 28
+#define GPO_PWMDAC0_RIGHT_OUTPUT 29
+#define GPO_SPI0_SSPCLKOUT 30
+#define GPO_SPI0_SSPFSSOUT 31
+#define GPO_SPI0_SSPTXD 32
+#define GPO_GMAC0_CLK_PHY 33
+#define GPO_I2SRX0_BCLK_MST 34
+#define GPO_I2SRX0_LRCK_MST 35
+#define GPO_I2STX0_BCLK_MST 36
+#define GPO_I2STX0_LRCK_MST 37
+#define GPO_CRG0_MCLK_OUT 38
+#define GPO_TDM0_CLK_MST 39
+#define GPO_TDM0_PCM_SYNCOUT 40
+#define GPO_TDM0_PCM_TXD 41
+#define GPO_U7MC_TRACE0_TDATA_0 42
+#define GPO_U7MC_TRACE0_TDATA_1 43
+#define GPO_U7MC_TRACE0_TDATA_2 44
+#define GPO_U7MC_TRACE0_TDATA_3 45
+#define GPO_U7MC_TRACE0_TREF 46
+#define GPO_CAN1_CTRL_STBY 47
+#define GPO_CAN1_CTRL_TST_NEXT_BIT 48
+#define GPO_CAN1_CTRL_TST_SAMPLE_POINT 49
+#define GPO_CAN1_CTRL_TXD 50
+#define GPO_I2C1_IC_CLK_OUT_A 51
+#define GPO_I2C1_IC_DATA_OUT_A 52
+#define GPO_SDIO1_BACK_END_POWER 53
+#define GPO_SDIO1_CARD_POWER_EN 54
+#define GPO_SDIO1_CCLK_OUT 55
+#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N 56
+#define GPO_SDIO1_CCMD_OUT 57
+#define GPO_SDIO1_CDATA_OUT_0 58
+#define GPO_SDIO1_CDATA_OUT_1 59
+#define GPO_SDIO1_CDATA_OUT_2 60
+#define GPO_SDIO1_CDATA_OUT_3 61
+#define GPO_SDIO1_CDATA_OUT_4 62
+#define GPO_SDIO1_CDATA_OUT_5 63
+#define GPO_SDIO1_CDATA_OUT_6 64
+#define GPO_SDIO1_CDATA_OUT_7 65
+#define GPO_SDIO1_RST_N 66
+#define GPO_UART1_RTS_N 67
+#define GPO_UART1_SOUT 68
+#define GPO_I2STX_4CH1_SDO0 69
+#define GPO_I2STX_4CH1_SDO1 70
+#define GPO_I2STX_4CH1_SDO2 71
+#define GPO_I2STX_4CH1_SDO3 72
+#define GPO_SPI1_SSPCLKOUT 73
+#define GPO_SPI1_SSPFSSOUT 74
+#define GPO_SPI1_SSPTXD 75
+#define GPO_I2C2_IC_CLK_OUT_A 76
+#define GPO_I2C2_IC_DATA_OUT_A 77
+#define GPO_UART2_RTS_N 78
+#define GPO_UART2_SOUT 79
+#define GPO_SPI2_SSPCLKOUT 80
+#define GPO_SPI2_SSPFSSOUT 81
+#define GPO_SPI2_SSPTXD 82
+#define GPO_I2C3_IC_CLK_OUT_A 83
+#define GPO_I2C3_IC_DATA_OUT_A 84
+#define GPO_UART3_SOUT 85
+#define GPO_SPI3_SSPCLKOUT 86
+#define GPO_SPI3_SSPFSSOUT 87
+#define GPO_SPI3_SSPTXD 88
+#define GPO_I2C4_IC_CLK_OUT_A 89
+#define GPO_I2C4_IC_DATA_OUT_A 90
+#define GPO_UART4_RTS_N 91
+#define GPO_UART4_SOUT 92
+#define GPO_SPI4_SSPCLKOUT 93
+#define GPO_SPI4_SSPFSSOUT 94
+#define GPO_SPI4_SSPTXD 95
+#define GPO_I2C5_IC_CLK_OUT_A 96
+#define GPO_I2C5_IC_DATA_OUT_A 97
+#define GPO_UART5_RTS_N 98
+#define GPO_UART5_SOUT 99
+#define GPO_SPI5_SSPCLKOUT 100
+#define GPO_SPI5_SSPFSSOUT 101
+#define GPO_SPI5_SSPTXD 102
+#define GPO_I2C6_IC_CLK_OUT_A 103
+#define GPO_I2C6_IC_DATA_OUT_A 104
+#define GPO_SPI6_SSPCLKOUT 105
+#define GPO_SPI6_SSPFSSOUT 106
+#define GPO_SPI6_SSPTXD 107
+#define GPO_NONE 108
+
+#define OEN_LOW 0
+#define OEN_HIGH 1
+#define OEN_HDMI0_CEC_SDA_OEN 2
+#define OEN_HDMI0_DDC_SCL_OEN 3
+#define OEN_HDMI0_DDC_SDA_OEN 4
+#define OEN_I2C0_IC_CLK_OE 5
+#define OEN_I2C0_IC_DATA_OE 6
+#define OEN_JTAG_DSP_TDO_OEN 7
+#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE 8
+#define OEN_PTC0_PWM_0_OE_N 9
+#define OEN_PTC0_PWM_1_OE_N 10
+#define OEN_PTC0_PWM_2_OE_N 11
+#define OEN_PTC0_PWM_3_OE_N 12
+#define OEN_SPI0_NSSPCTLOE 13
+#define OEN_SPI0_NSSPOE 14
+#define OEN_TDM0_NPCM_SYNCOE 15
+#define OEN_TDM0_NPCM_TXDOE 16
+#define OEN_I2C1_IC_CLK_OE 17
+#define OEN_I2C1_IC_DATA_OE 18
+#define OEN_SDIO1_CCMD_OUT_EN 19
+#define OEN_SDIO1_CDATA_OUT_EN_0 20
+#define OEN_SDIO1_CDATA_OUT_EN_1 21
+#define OEN_SDIO1_CDATA_OUT_EN_2 22
+#define OEN_SDIO1_CDATA_OUT_EN_3 23
+#define OEN_SDIO1_CDATA_OUT_EN_4 24
+#define OEN_SDIO1_CDATA_OUT_EN_5 25
+#define OEN_SDIO1_CDATA_OUT_EN_6 26
+#define OEN_SDIO1_CDATA_OUT_EN_7 27
+#define OEN_SPI1_NSSPCTLOE 28
+#define OEN_SPI1_NSSPOE 29
+#define OEN_I2C2_IC_CLK_OE 30
+#define OEN_I2C2_IC_DATA_OE 31
+#define OEN_SPI2_NSSPCTLOE 32
+#define OEN_SPI2_NSSPOE 33
+#define OEN_I2C3_IC_CLK_OE 34
+#define OEN_I2C3_IC_DATA_OE 35
+#define OEN_SPI3_NSSPCTLOE 36
+#define OEN_SPI3_NSSPOE 37
+#define OEN_I2C4_IC_CLK_OE 38
+#define OEN_I2C4_IC_DATA_OE 39
+#define OEN_SPI4_NSSPCTLOE 40
+#define OEN_SPI4_NSSPOE 41
+#define OEN_I2C5_IC_CLK_OE 42
+#define OEN_I2C5_IC_DATA_OE 43
+#define OEN_SPI5_NSSPCTLOE 44
+#define OEN_SPI5_NSSPOE 45
+#define OEN_I2C6_IC_CLK_OE 46
+#define OEN_I2C6_IC_DATA_OE 47
+#define OEN_SPI6_NSSPCTLOE 48
+#define OEN_SPI6_NSSPOE 49
+#define OEN_NONE 50
+
+#define GPI_WAVE511_0_I_UART_RXSIN 0
+#define GPI_CAN0_CTRL_RXD 1
+#define GPI_USB0_OVERCURRENT_N_IO 2
+#define GPI_SPDIF0_SPDIFI 3
+#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN 4
+#define GPI_HDMI0_CEC_SDA_IN 5
+#define GPI_HDMI0_DDC_SCL_IN 6
+#define GPI_HDMI0_DDC_SDA_IN 7
+#define GPI_HDMI0_HPD 8
+#define GPI_I2C0_IC_CLK_IN_A 9
+#define GPI_I2C0_IC_DATA_IN_A 10
+#define GPI_SDIO0_CARD_DETECT_N 11
+#define GPI_SDIO0_CARD_INT_N 12
+#define GPI_SDIO0_CARD_WRITE_PRT 13
+#define GPI_UART0_SIN 14
+#define GPI_JTAG_DSP_TCK 15
+#define GPI_JTAG_DSP_TDI 16
+#define GPI_JTAG_DSP_TMS 17
+#define GPI_JTAG_DSP_TRST_N 18
+#define GPI_JTAG_CPU_CERTIFICATION_TDI 19
+#define GPI_JTAG_CPU_CERTIFICATION_TMS 20
+#define GPI_PDM_4MIC0_DMIC0_DIN 21
+#define GPI_PDM_4MIC0_DMIC1_DIN 22
+#define GPI_I2SRX0_EXT_SDIN0 23
+#define GPI_I2SRX0_EXT_SDIN1 24
+#define GPI_I2SRX0_EXT_SDIN2 25
+#define GPI_SPI0_SSPCLKIN 26
+#define GPI_SPI0_SSPFSSIN 27
+#define GPI_SPI0_SSPRXD 28
+#define GPI_JTAG_CPU_CERTIFICATION_TCK 29
+#define GPI_CRG0_EXT_MCLK 30
+#define GPI_I2SRX0_BCLK_SLV 31
+#define GPI_I2SRX0_LRCK_SLV 32
+#define GPI_I2STX0_BCLK_SLV 33
+#define GPI_I2STX0_LRCK_SLV 34
+#define GPI_TDM0_CLK_SLV 35
+#define GPI_TDM0_PCM_RXD 36
+#define GPI_TDM0_PCM_SYNCIN 37
+#define GPI_CAN1_CTRL_RXD 38
+#define GPI_I2C1_IC_CLK_IN_A 39
+#define GPI_I2C1_IC_DATA_IN_A 40
+#define GPI_SDIO1_CARD_DETECT_N 41
+#define GPI_SDIO1_CARD_INT_N 42
+#define GPI_SDIO1_CARD_WRITE_PRT 43
+#define GPI_SDIO1_CCMD_IN 44
+#define GPI_SDIO1_CDATA_IN_0 45
+#define GPI_SDIO1_CDATA_IN_1 46
+#define GPI_SDIO1_CDATA_IN_2 47
+#define GPI_SDIO1_CDATA_IN_3 48
+#define GPI_SDIO1_CDATA_IN_4 49
+#define GPI_SDIO1_CDATA_IN_5 50
+#define GPI_SDIO1_CDATA_IN_6 51
+#define GPI_SDIO1_CDATA_IN_7 52
+#define GPI_SDIO1_DATA_STROBE 53
+#define GPI_UART1_CTS_N 54
+#define GPI_UART1_SIN 55
+#define GPI_SPI1_SSPCLKIN 56
+#define GPI_SPI1_SSPFSSIN 57
+#define GPI_SPI1_SSPRXD 58
+#define GPI_I2C2_IC_CLK_IN_A 59
+#define GPI_I2C2_IC_DATA_IN_A 60
+#define GPI_UART2_CTS_N 61
+#define GPI_UART2_SIN 62
+#define GPI_SPI2_SSPCLKIN 63
+#define GPI_SPI2_SSPFSSIN 64
+#define GPI_SPI2_SSPRXD 65
+#define GPI_I2C3_IC_CLK_IN_A 66
+#define GPI_I2C3_IC_DATA_IN_A 67
+#define GPI_UART3_SIN 68
+#define GPI_SPI3_SSPCLKIN 69
+#define GPI_SPI3_SSPFSSIN 70
+#define GPI_SPI3_SSPRXD 71
+#define GPI_I2C4_IC_CLK_IN_A 72
+#define GPI_I2C4_IC_DATA_IN_A 73
+#define GPI_UART4_CTS_N 74
+#define GPI_UART4_SIN 75
+#define GPI_SPI4_SSPCLKIN 76
+#define GPI_SPI4_SSPFSSIN 77
+#define GPI_SPI4_SSPRXD 78
+#define GPI_I2C5_IC_CLK_IN_A 79
+#define GPI_I2C5_IC_DATA_IN_A 80
+#define GPI_UART5_CTS_N 81
+#define GPI_UART5_SIN 82
+#define GPI_SPI5_SSPCLKIN 83
+#define GPI_SPI5_SSPFSSIN 84
+#define GPI_SPI5_SSPRXD 85
+#define GPI_I2C6_IC_CLK_IN_A 86
+#define GPI_I2C6_IC_DATA_IN_A 87
+#define GPI_SPI6_SSPCLKIN 88
+#define GPI_SPI6_SSPFSSIN 89
+#define GPI_SPI6_SSPRXD 90
+#define GPI_NONE 91
+
+/* sys_iomux syscon */
+#define PADCFG_PAD_GMAC1_MDC_SYSCON 0x24c
+#define PADCFG_PAD_GMAC1_MDIO_SYSCON 0x250
+#define PADCFG_PAD_GMAC1_RXD0_SYSCON 0x254
+#define PADCFG_PAD_GMAC1_RXD1_SYSCON 0x258
+#define PADCFG_PAD_GMAC1_RXD2_SYSCON 0x25c
+#define PADCFG_PAD_GMAC1_RXD3_SYSCON 0x260
+#define PADCFG_PAD_GMAC1_RXDV_SYSCON 0x264
+#define PADCFG_PAD_GMAC1_RXC_SYSCON 0x268
+#define PADCFG_PAD_GMAC1_TXD0_SYSCON 0x26c
+#define PADCFG_PAD_GMAC1_TXD1_SYSCON 0x270
+#define PADCFG_PAD_GMAC1_TXD2_SYSCON 0x274
+#define PADCFG_PAD_GMAC1_TXD3_SYSCON 0x278
+#define PADCFG_PAD_GMAC1_TXEN_SYSCON 0x27c
+#define PADCFG_PAD_GMAC1_TXC_SYSCON 0x280
+
+/* sys_iomux func sel setting */
+#define SYS_IOMUX_CFGSAIF_668_ADDR 0x29c
+#define PAD_GMAC1_RXC_FUNC_SEL_SHIFT 0x0
+#define PAD_GMAC1_RXC_FUNC_SEL_MASK 0x3
+#define PAD_GPIO10_FUNC_SEL_SHIFT 0x2
+#define PAD_GPIO10_FUNC_SEL_MASK 0x1C
+#define PAD_GPIO11_FUNC_SEL_SHIFT 0x5
+#define PAD_GPIO11_FUNC_SEL_MASK 0xE0
+#define PAD_GPIO12_FUNC_SEL_SHIFT 0x8
+#define PAD_GPIO12_FUNC_SEL_MASK 0x700
+#define PAD_GPIO13_FUNC_SEL_SHIFT 0xB
+#define PAD_GPIO13_FUNC_SEL_MASK 0x3800
+#define PAD_GPIO14_FUNC_SEL_SHIFT 0xE
+#define PAD_GPIO14_FUNC_SEL_MASK 0x1C000
+#define PAD_GPIO15_FUNC_SEL_SHIFT 0x11
+#define PAD_GPIO15_FUNC_SEL_MASK 0xE0000
+#define PAD_GPIO16_FUNC_SEL_SHIFT 0x14
+#define PAD_GPIO16_FUNC_SEL_MASK 0x700000
+#define PAD_GPIO17_FUNC_SEL_SHIFT 0x17
+#define PAD_GPIO17_FUNC_SEL_MASK 0x3800000
+#define PAD_GPIO18_FUNC_SEL_SHIFT 0x1A
+#define PAD_GPIO18_FUNC_SEL_MASK 0x1C000000
+#define PAD_GPIO19_FUNC_SEL_SHIFT 0x1D
+#define PAD_GPIO19_FUNC_SEL_MASK 0xE0000000
+#define SYS_IOMUX_CFGSAIF_672_ADDR 0x2a0
+#define PAD_GPIO20_FUNC_SEL_SHIFT 0x0
+#define PAD_GPIO20_FUNC_SEL_MASK 0x7
+#define PAD_GPIO21_FUNC_SEL_SHIFT 0x3
+#define PAD_GPIO21_FUNC_SEL_MASK 0x38
+#define PAD_GPIO22_FUNC_SEL_SHIFT 0x6
+#define PAD_GPIO22_FUNC_SEL_MASK 0x1C0
+#define PAD_GPIO23_FUNC_SEL_SHIFT 0x9
+#define PAD_GPIO23_FUNC_SEL_MASK 0xE00
+#define PAD_GPIO24_FUNC_SEL_SHIFT 0xC
+#define PAD_GPIO24_FUNC_SEL_MASK 0x7000
+#define PAD_GPIO25_FUNC_SEL_SHIFT 0xF
+#define PAD_GPIO25_FUNC_SEL_MASK 0x38000
+#define PAD_GPIO26_FUNC_SEL_SHIFT 0x12
+#define PAD_GPIO26_FUNC_SEL_MASK 0x1C0000
+#define PAD_GPIO27_FUNC_SEL_SHIFT 0x15
+#define PAD_GPIO27_FUNC_SEL_MASK 0xE00000
+#define PAD_GPIO28_FUNC_SEL_SHIFT 0x18
+#define PAD_GPIO28_FUNC_SEL_MASK 0x7000000
+#define PAD_GPIO29_FUNC_SEL_SHIFT 0x1B
+#define PAD_GPIO29_FUNC_SEL_MASK 0x38000000
+#define SYS_IOMUX_CFGSAIF_676_ADDR 0x2a4
+#define PAD_GPIO30_FUNC_SEL_SHIFT 0x0
+#define PAD_GPIO30_FUNC_SEL_MASK 0x7
+#define PAD_GPIO31_FUNC_SEL_SHIFT 0x3
+#define PAD_GPIO31_FUNC_SEL_MASK 0x38
+#define PAD_GPIO32_FUNC_SEL_SHIFT 0x6
+#define PAD_GPIO32_FUNC_SEL_MASK 0x1C0
+#define PAD_GPIO33_FUNC_SEL_SHIFT 0x9
+#define PAD_GPIO33_FUNC_SEL_MASK 0xE00
+#define PAD_GPIO34_FUNC_SEL_SHIFT 0xC
+#define PAD_GPIO34_FUNC_SEL_MASK 0x7000
+#define PAD_GPIO35_FUNC_SEL_SHIFT 0xF
+#define PAD_GPIO35_FUNC_SEL_MASK 0x18000
+#define PAD_GPIO36_FUNC_SEL_SHIFT 0x11
+#define PAD_GPIO36_FUNC_SEL_MASK 0xE0000
+#define PAD_GPIO37_FUNC_SEL_SHIFT 0x14
+#define PAD_GPIO37_FUNC_SEL_MASK 0x700000
+#define PAD_GPIO38_FUNC_SEL_SHIFT 0x17
+#define PAD_GPIO38_FUNC_SEL_MASK 0x3800000
+#define PAD_GPIO39_FUNC_SEL_SHIFT 0x1A
+#define PAD_GPIO39_FUNC_SEL_MASK 0x1C000000
+#define PAD_GPIO40_FUNC_SEL_SHIFT 0x1D
+#define PAD_GPIO40_FUNC_SEL_MASK 0xE0000000
+#define SYS_IOMUX_CFGSAIF_680_ADDR 0x2a8
+#define PAD_GPIO41_FUNC_SEL_SHIFT 0x0
+#define PAD_GPIO41_FUNC_SEL_MASK 0x7
+#define PAD_GPIO42_FUNC_SEL_SHIFT 0x3
+#define PAD_GPIO42_FUNC_SEL_MASK 0x38
+#define PAD_GPIO43_FUNC_SEL_SHIFT 0x6
+#define PAD_GPIO43_FUNC_SEL_MASK 0x1C0
+#define PAD_GPIO44_FUNC_SEL_SHIFT 0x9
+#define PAD_GPIO44_FUNC_SEL_MASK 0xE00
+#define PAD_GPIO45_FUNC_SEL_SHIFT 0xC
+#define PAD_GPIO45_FUNC_SEL_MASK 0x7000
+#define PAD_GPIO46_FUNC_SEL_SHIFT 0xF
+#define PAD_GPIO46_FUNC_SEL_MASK 0x38000
+#define PAD_GPIO47_FUNC_SEL_SHIFT 0x12
+#define PAD_GPIO47_FUNC_SEL_MASK 0x1C0000
+#define PAD_GPIO48_FUNC_SEL_SHIFT 0x15
+#define PAD_GPIO48_FUNC_SEL_MASK 0xE00000
+#define PAD_GPIO49_FUNC_SEL_SHIFT 0x18
+#define PAD_GPIO49_FUNC_SEL_MASK 0x7000000
+#define PAD_GPIO50_FUNC_SEL_SHIFT 0x1B
+#define PAD_GPIO50_FUNC_SEL_MASK 0x38000000
+#define PAD_GPIO51_FUNC_SEL_SHIFT 0x1E
+#define PAD_GPIO51_FUNC_SEL_MASK 0xC0000000
+#define SYS_IOMUX_CFGSAIF_684_ADDR 0x2ac
+#define PAD_GPIO52_FUNC_SEL_SHIFT 0x0
+#define PAD_GPIO52_FUNC_SEL_MASK 0x3
+#define PAD_GPIO53_FUNC_SEL_SHIFT 0x2
+#define PAD_GPIO53_FUNC_SEL_MASK 0xC
+#define PAD_GPIO54_FUNC_SEL_SHIFT 0x4
+#define PAD_GPIO54_FUNC_SEL_MASK 0x30
+#define PAD_GPIO55_FUNC_SEL_SHIFT 0x6
+#define PAD_GPIO55_FUNC_SEL_MASK 0x1C0
+#define PAD_GPIO56_FUNC_SEL_SHIFT 0x9
+#define PAD_GPIO56_FUNC_SEL_MASK 0xE00
+#define PAD_GPIO57_FUNC_SEL_SHIFT 0xC
+#define PAD_GPIO57_FUNC_SEL_MASK 0x7000
+#define PAD_GPIO58_FUNC_SEL_SHIFT 0xF
+#define PAD_GPIO58_FUNC_SEL_MASK 0x38000
+#define PAD_GPIO59_FUNC_SEL_SHIFT 0x12
+#define PAD_GPIO59_FUNC_SEL_MASK 0x1C0000
+#define PAD_GPIO60_FUNC_SEL_SHIFT 0x15
+#define PAD_GPIO60_FUNC_SEL_MASK 0xE00000
+#define PAD_GPIO61_FUNC_SEL_SHIFT 0x18
+#define PAD_GPIO61_FUNC_SEL_MASK 0x7000000
+#define PAD_GPIO62_FUNC_SEL_SHIFT 0x1B
+#define PAD_GPIO62_FUNC_SEL_MASK 0x38000000
+#define PAD_GPIO63_FUNC_SEL_SHIFT 0x1E
+#define PAD_GPIO63_FUNC_SEL_MASK 0xC0000000
+#define SYS_IOMUX_CFGSAIF_688_ADDR 0x2b0
+#define PAD_GPIO6_FUNC_SEL_SHIFT 0x0
+#define PAD_GPIO6_FUNC_SEL_MASK 0x3
+#define PAD_GPIO7_FUNC_SEL_SHIFT 0x2
+#define PAD_GPIO7_FUNC_SEL_MASK 0x1C
+#define PAD_GPIO8_FUNC_SEL_SHIFT 0x5
+#define PAD_GPIO8_FUNC_SEL_MASK 0xE0
+#define PAD_GPIO9_FUNC_SEL_SHIFT 0x8
+#define PAD_GPIO9_FUNC_SEL_MASK 0x700
+#define ISP_VIN_DVP_DATA0_FUNC_SEL_SHIFT 0xB
+#define ISP_VIN_DVP_DATA0_FUNC_SEL_MASK 0x3800
+#define ISP_VIN_DVP_DATA10_FUNC_SEL_SHIFT 0xE
+#define ISP_VIN_DVP_DATA10_FUNC_SEL_MASK 0x1C000
+#define ISP_VIN_DVP_DATA11_FUNC_SEL_SHIFT 0x11
+#define ISP_VIN_DVP_DATA11_FUNC_SEL_MASK 0xE0000
+#define ISP_VIN_DVP_DATA1_FUNC_SEL_SHIFT 0x14
+#define ISP_VIN_DVP_DATA1_FUNC_SEL_MASK 0x700000
+#define ISP_VIN_DVP_DATA2_FUNC_SEL_SHIFT 0x17
+#define ISP_VIN_DVP_DATA2_FUNC_SEL_MASK 0x3800000
+#define ISP_VIN_DVP_DATA3_FUNC_SEL_SHIFT 0x1A
+#define ISP_VIN_DVP_DATA3_FUNC_SEL_MASK 0x1C000000
+#define ISP_VIN_DVP_DATA4_FUNC_SEL_SHIFT 0x1D
+#define ISP_VIN_DVP_DATA4_FUNC_SEL_MASK 0xE0000000
+#define SYS_IOMUX_CFGSAIF_692_ADDR 0x2b4
+#define ISP_VIN_DVP_DATA5_FUNC_SEL_SHIFT 0x0
+#define ISP_VIN_DVP_DATA5_FUNC_SEL_MASK 0x7
+#define ISP_VIN_DVP_DATA6_FUNC_SEL_SHIFT 0x3
+#define ISP_VIN_DVP_DATA6_FUNC_SEL_MASK 0x38
+#define ISP_VIN_DVP_DATA7_FUNC_SEL_SHIFT 0x6
+#define ISP_VIN_DVP_DATA7_FUNC_SEL_MASK 0x1C0
+#define ISP_VIN_DVP_DATA8_FUNC_SEL_SHIFT 0x9
+#define ISP_VIN_DVP_DATA8_FUNC_SEL_MASK 0xE00
+#define ISP_VIN_DVP_DATA9_FUNC_SEL_SHIFT 0xC
+#define ISP_VIN_DVP_DATA9_FUNC_SEL_MASK 0x7000
+#define ISP_VIN_DVP_HVALID_FUNC_SEL_SHIFT 0xF
+#define ISP_VIN_DVP_HVALID_FUNC_SEL_MASK 0x38000
+#define ISP_VIN_DVP_VVALID_FUNC_SEL_SHIFT 0x12
+#define ISP_VIN_DVP_VVALID_FUNC_SEL_MASK 0x1C0000
+#define DVP_CLK_FUNC_SEL_SHIFT 0x15
+#define DVP_CLK_FUNC_SEL_MASK 0xE00000
+
+#define PAD_GMAC1_RXC_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GMAC1_RXC_FUNC_SEL_SHIFT \
+ PAD_GMAC1_RXC_FUNC_SEL_MASK
+#define PAD_GPIO10_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO10_FUNC_SEL_SHIFT \
+ PAD_GPIO10_FUNC_SEL_MASK
+#define PAD_GPIO11_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO11_FUNC_SEL_SHIFT \
+ PAD_GPIO11_FUNC_SEL_MASK
+#define PAD_GPIO12_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO12_FUNC_SEL_SHIFT \
+ PAD_GPIO12_FUNC_SEL_MASK
+#define PAD_GPIO13_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO13_FUNC_SEL_SHIFT \
+ PAD_GPIO13_FUNC_SEL_MASK
+#define PAD_GPIO14_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO14_FUNC_SEL_SHIFT \
+ PAD_GPIO14_FUNC_SEL_MASK
+#define PAD_GPIO15_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO15_FUNC_SEL_SHIFT \
+ PAD_GPIO15_FUNC_SEL_MASK
+#define PAD_GPIO16_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO16_FUNC_SEL_SHIFT \
+ PAD_GPIO16_FUNC_SEL_MASK
+#define PAD_GPIO17_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO17_FUNC_SEL_SHIFT \
+ PAD_GPIO17_FUNC_SEL_MASK
+#define PAD_GPIO18_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO18_FUNC_SEL_SHIFT \
+ PAD_GPIO18_FUNC_SEL_MASK
+#define PAD_GPIO19_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_668_ADDR \
+ PAD_GPIO19_FUNC_SEL_SHIFT \
+ PAD_GPIO19_FUNC_SEL_MASK
+#define PAD_GPIO20_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO20_FUNC_SEL_SHIFT \
+ PAD_GPIO20_FUNC_SEL_MASK
+#define PAD_GPIO21_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO21_FUNC_SEL_SHIFT \
+ PAD_GPIO21_FUNC_SEL_MASK
+#define PAD_GPIO22_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO22_FUNC_SEL_SHIFT \
+ PAD_GPIO22_FUNC_SEL_MASK
+#define PAD_GPIO23_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO23_FUNC_SEL_SHIFT \
+ PAD_GPIO23_FUNC_SEL_MASK
+#define PAD_GPIO24_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO24_FUNC_SEL_SHIFT \
+ PAD_GPIO24_FUNC_SEL_MASK
+#define PAD_GPIO25_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO25_FUNC_SEL_SHIFT \
+ PAD_GPIO25_FUNC_SEL_MASK
+#define PAD_GPIO26_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO26_FUNC_SEL_SHIFT \
+ PAD_GPIO26_FUNC_SEL_MASK
+#define PAD_GPIO27_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO27_FUNC_SEL_SHIFT \
+ PAD_GPIO27_FUNC_SEL_MASK
+#define PAD_GPIO28_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO28_FUNC_SEL_SHIFT \
+ PAD_GPIO28_FUNC_SEL_MASK
+#define PAD_GPIO29_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_672_ADDR \
+ PAD_GPIO29_FUNC_SEL_SHIFT \
+ PAD_GPIO29_FUNC_SEL_MASK
+#define PAD_GPIO30_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO30_FUNC_SEL_SHIFT \
+ PAD_GPIO30_FUNC_SEL_MASK
+#define PAD_GPIO31_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO31_FUNC_SEL_SHIFT \
+ PAD_GPIO31_FUNC_SEL_MASK
+#define PAD_GPIO32_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO32_FUNC_SEL_SHIFT \
+ PAD_GPIO32_FUNC_SEL_MASK
+#define PAD_GPIO33_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO33_FUNC_SEL_SHIFT \
+ PAD_GPIO33_FUNC_SEL_MASK
+#define PAD_GPIO34_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO34_FUNC_SEL_SHIFT \
+ PAD_GPIO34_FUNC_SEL_MASK
+#define PAD_GPIO35_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO35_FUNC_SEL_SHIFT \
+ PAD_GPIO35_FUNC_SEL_MASK
+#define PAD_GPIO36_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO36_FUNC_SEL_SHIFT \
+ PAD_GPIO36_FUNC_SEL_MASK
+#define PAD_GPIO37_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO37_FUNC_SEL_SHIFT \
+ PAD_GPIO37_FUNC_SEL_MASK
+#define PAD_GPIO38_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO38_FUNC_SEL_SHIFT \
+ PAD_GPIO38_FUNC_SEL_MASK
+#define PAD_GPIO39_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO39_FUNC_SEL_SHIFT \
+ PAD_GPIO39_FUNC_SEL_MASK
+#define PAD_GPIO40_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_676_ADDR \
+ PAD_GPIO40_FUNC_SEL_SHIFT \
+ PAD_GPIO40_FUNC_SEL_MASK
+#define PAD_GPIO41_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO41_FUNC_SEL_SHIFT \
+ PAD_GPIO41_FUNC_SEL_MASK
+#define PAD_GPIO42_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO42_FUNC_SEL_SHIFT \
+ PAD_GPIO42_FUNC_SEL_MASK
+#define PAD_GPIO43_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO43_FUNC_SEL_SHIFT \
+ PAD_GPIO43_FUNC_SEL_MASK
+#define PAD_GPIO44_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO44_FUNC_SEL_SHIFT \
+ PAD_GPIO44_FUNC_SEL_MASK
+#define PAD_GPIO45_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO45_FUNC_SEL_SHIFT \
+ PAD_GPIO45_FUNC_SEL_MASK
+#define PAD_GPIO46_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO46_FUNC_SEL_SHIFT \
+ PAD_GPIO46_FUNC_SEL_MASK
+#define PAD_GPIO47_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO47_FUNC_SEL_SHIFT \
+ PAD_GPIO47_FUNC_SEL_MASK
+#define PAD_GPIO48_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO48_FUNC_SEL_SHIFT \
+ PAD_GPIO48_FUNC_SEL_MASK
+#define PAD_GPIO49_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO49_FUNC_SEL_SHIFT \
+ PAD_GPIO49_FUNC_SEL_MASK
+#define PAD_GPIO50_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO50_FUNC_SEL_SHIFT \
+ PAD_GPIO50_FUNC_SEL_MASK
+#define PAD_GPIO51_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_680_ADDR \
+ PAD_GPIO51_FUNC_SEL_SHIFT \
+ PAD_GPIO51_FUNC_SEL_MASK
+#define PAD_GPIO52_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO52_FUNC_SEL_SHIFT \
+ PAD_GPIO52_FUNC_SEL_MASK
+#define PAD_GPIO53_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO53_FUNC_SEL_SHIFT \
+ PAD_GPIO53_FUNC_SEL_MASK
+#define PAD_GPIO54_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO54_FUNC_SEL_SHIFT \
+ PAD_GPIO54_FUNC_SEL_MASK
+#define PAD_GPIO55_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO55_FUNC_SEL_SHIFT \
+ PAD_GPIO55_FUNC_SEL_MASK
+#define PAD_GPIO56_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO56_FUNC_SEL_SHIFT \
+ PAD_GPIO56_FUNC_SEL_MASK
+#define PAD_GPIO57_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO57_FUNC_SEL_SHIFT \
+ PAD_GPIO57_FUNC_SEL_MASK
+#define PAD_GPIO58_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO58_FUNC_SEL_SHIFT \
+ PAD_GPIO58_FUNC_SEL_MASK
+#define PAD_GPIO59_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO59_FUNC_SEL_SHIFT \
+ PAD_GPIO59_FUNC_SEL_MASK
+#define PAD_GPIO60_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO60_FUNC_SEL_SHIFT \
+ PAD_GPIO60_FUNC_SEL_MASK
+#define PAD_GPIO61_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO61_FUNC_SEL_SHIFT \
+ PAD_GPIO61_FUNC_SEL_MASK
+#define PAD_GPIO62_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO62_FUNC_SEL_SHIFT \
+ PAD_GPIO62_FUNC_SEL_MASK
+#define PAD_GPIO63_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_684_ADDR \
+ PAD_GPIO63_FUNC_SEL_SHIFT \
+ PAD_GPIO63_FUNC_SEL_MASK
+#define PAD_GPIO6_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ PAD_GPIO6_FUNC_SEL_SHIFT \
+ PAD_GPIO6_FUNC_SEL_MASK
+#define PAD_GPIO7_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ PAD_GPIO7_FUNC_SEL_SHIFT \
+ PAD_GPIO7_FUNC_SEL_MASK
+#define PAD_GPIO8_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ PAD_GPIO8_FUNC_SEL_SHIFT \
+ PAD_GPIO8_FUNC_SEL_MASK
+#define PAD_GPIO9_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ PAD_GPIO9_FUNC_SEL_SHIFT \
+ PAD_GPIO9_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA0_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ ISP_VIN_DVP_DATA0_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA0_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA10_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ ISP_VIN_DVP_DATA10_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA10_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA11_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ ISP_VIN_DVP_DATA11_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA11_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA1_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ ISP_VIN_DVP_DATA1_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA1_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA2_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ ISP_VIN_DVP_DATA2_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA2_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA3_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ ISP_VIN_DVP_DATA3_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA3_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA4_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_688_ADDR \
+ ISP_VIN_DVP_DATA4_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA4_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA5_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_692_ADDR \
+ ISP_VIN_DVP_DATA5_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA5_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA6_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_692_ADDR \
+ ISP_VIN_DVP_DATA6_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA6_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA7_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_692_ADDR \
+ ISP_VIN_DVP_DATA7_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA7_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA8_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_692_ADDR \
+ ISP_VIN_DVP_DATA8_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA8_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA9_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_692_ADDR \
+ ISP_VIN_DVP_DATA9_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_DATA9_FUNC_SEL_MASK
+#define ISP_VIN_DVP_HVALID_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_692_ADDR \
+ ISP_VIN_DVP_HVALID_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_HVALID_FUNC_SEL_MASK
+#define ISP_VIN_DVP_VVALID_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_692_ADDR \
+ ISP_VIN_DVP_VVALID_FUNC_SEL_SHIFT \
+ ISP_VIN_DVP_VVALID_FUNC_SEL_MASK
+#define DVP_CLK_FUNC_SEL \
+ SYS_IOMUX_CFGSAIF_692_ADDR \
+ DVP_CLK_FUNC_SEL_SHIFT \
+ DVP_CLK_FUNC_SEL_MASK
+
+/* POS[0] */
+#define TESTEN_POS(data) (((data) << 0x0) & 0x1)
+
+/* SMT[0] POS[1] */
+#define RSTN_SMT(data) (((data) << 0x0) & 0x1)
+#define RSTN_POS(data) (((data) << 0x1) & 0x2)
+
+/* DS[1:0] */
+#define OSC_DS(data) (((data) << 0x0) & 0x3)
+
+/* sys ioconfig */
+/* IE[0] DS[2:1] PU[3] PD[4] SLEW[5] SMT[6] POS[7] */
+#define GPIO_IE(data) (((data) << 0x0) & 0x1)
+#define GPIO_DS(data) (((data) << 0x1) & 0x6)
+#define GPIO_PU(data) (((data) << 0x3) & 0x8)
+#define GPIO_PD(data) (((data) << 0x4) & 0x7)
+#define GPIO_SLEW(data) (((data) << 0x5) & 0x20)
+#define GPIO_SMT(data) (((data) << 0x6) & 0x40)
+#define GPIO_POS(data) (((data) << 0x7) & 0x80)
+
+#define IO(config) ((config) & 0xFF)
+#define DOUT(dout) ((dout) & 0xFF)
+#define DOEN(doen) ((doen) & 0xFF)
+#define DIN(din_reg) ((din_reg) & 0xFF)
+
+/* syscon value */
+#define IO_3_3V 0 /* 00: 3.3v */
+#define IO_2_5V 1 /* 01: 2.5v */
+#define IO_1_8V 2 /* 10: 1.8v */
+
+#endif
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add a minimal device tree for StarFive JH7110 VisionFive2 board.
Support booting and basic clock/reset/pinctrl/uart drivers.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../jh7110-starfive-visionfive-v2.dts | 91 +++++++++++++++++++
2 files changed, 92 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 0ea1bc15ab30..e1237dbc6aac 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
new file mode 100644
index 000000000000..6b9fe32c7eac
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+
+/ {
+ model = "StarFive VisionFive V2";
+ compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ timebase-frequency = <4000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x20000000>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
+ linux,cma-default;
+ };
+
+ e24_mem: e24@c0000000 {
+ reg = <0x0 0xc0110000 0x0 0xf0000>;
+ no-map;
+ };
+
+ xrp_reserved: xrpbuffer@f0000000 {
+ reg = <0x0 0xf0000000 0x0 0x01ffffff>,
+ <0x0 0xf2000000 0x0 0x00001000>,
+ <0x0 0xf2001000 0x0 0x00fff000>,
+ <0x0 0xf3000000 0x0 0x00001000>;
+ };
+
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+};
+
+&gpio {
+ uart0_pins: uart0-pins {
+ uart0-pins-tx {
+ starfive,pins = <PAD_GPIO5>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+ starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
+ starfive,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ uart0-pins-rx {
+ starfive,pins = <PAD_GPIO6>;
+ starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
+ starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+ starfive,pin-gpio-doen = <OEN_HIGH>;
+ starfive,pin-gpio-din = <GPI_UART0_SIN>;
+ };
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
--
2.17.1
From: Emil Renner Berthing <[email protected]>
Add initial device tree for the JH7110 RISC-V SoC by
StarFive Technology Ltd.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
1 file changed, 449 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
new file mode 100644
index 000000000000..46f418d4198a
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive-jh7110-sys.h>
+#include <dt-bindings/clock/starfive-jh7110-aon.h>
+#include <dt-bindings/reset/starfive-jh7110.h>
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <8192>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imac";
+ tlb-split;
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu4: cpu@4 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <4>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+ };
+ };
+ };
+
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ clk_rtc: clk_rtc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rmii_refin: gmac0_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ gmac1_rmii_refin: gmac1_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ i2stx_bclk_ext: i2stx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ i2stx_lrck_ext: i2stx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <192000>;
+ };
+
+ i2srx_bclk_ext: i2srx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ i2srx_lrck_ext: i2srx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <192000>;
+ };
+
+ tdm_ext: tdm_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <49152000>;
+ };
+
+ mclk_ext: mclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <49152000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clint: clint@2000000 {
+ compatible = "starfive,jh7110-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
+ };
+
+ plic: plic@c000000 {
+ compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ riscv,ndev = <136>;
+ };
+
+ ccache: cache-controller@2010000 {
+ compatible = "starfive,jh7110-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x4000>;
+ interrupts = <1>, <3>, <4>, <2>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
+ syscrg: syscrg@13020000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x13020000 0x0 0x10000>;
+
+ syscrg_clk: clock-controller@13020000 {
+ compatible = "starfive,jh7110-clkgen-sys";
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ };
+
+ syscrg_rst: reset-controller@13020000 {
+ compatible = "starfive,jh7110-reset";
+ #reset-cells = <1>;
+ starfive,assert-offset = <0x2F8>;
+ starfive,status-offset= <0x308>;
+ starfive,nr-resets = <JH7110_SYSRST_END>;
+ };
+ };
+
+ aoncrg: aoncrg@17000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x17000000 0x0 0x10000>;
+
+ aoncrg_clk: clock-controller@17000000 {
+ compatible = "starfive,jh7110-clkgen-aon";
+ clocks = <&osc>, <&clk_rtc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg_clk JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg_clk JH7110_SYSCLK_APB_BUS_FUNC>;
+ clock-names = "osc", "clk_rtc",
+ "gmac0_rmii_refin", "gmac0_rgmii_rxin",
+ "stg_axiahb", "apb_bus_func";
+ #clock-cells = <1>;
+ };
+
+ aoncrg_rst: reset-controller@17000000 {
+ compatible = "starfive,jh7110-reset";
+ #reset-cells = <1>;
+ starfive,assert-offset = <0x38>;
+ starfive,status-offset= <0x3C>;
+ starfive,nr-resets = <JH7110_AONRST_END>;
+ };
+ };
+
+ gpio: gpio@13040000 {
+ compatible = "starfive,jh7110-sys-pinctrl";
+ reg = <0x0 0x13040000 0x0 0x10000>;
+ reg-names = "control";
+ clocks = <&syscrg_clk JH7110_SYSCLK_IOMUX>;
+ resets = <&syscrg_rst JH7110_SYSRST_IOMUX>;
+ interrupts = <86>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ ngpios = <64>;
+ };
+
+ gpioa: gpio@17020000 {
+ compatible = "starfive,jh7110-aon-pinctrl";
+ reg = <0x0 0x17020000 0x0 0x10000>;
+ reg-names = "control";
+ resets = <&aoncrg_rst JH7110_AONRST_AON_IOMUX>;
+ interrupts = <85>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ ngpios = <4>;
+ };
+
+ uart0: serial@10000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ clocks = <&syscrg_clk JH7110_SYSCLK_UART0_CORE>,
+ <&syscrg_clk JH7110_SYSCLK_UART0_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg_rst JH7110_SYSRST_UART0_APB>,
+ <&syscrg_rst JH7110_SYSRST_UART0_CORE>;
+ interrupts = <32>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@10010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ clocks = <&syscrg_clk JH7110_SYSCLK_UART1_CORE>,
+ <&syscrg_clk JH7110_SYSCLK_UART1_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg_rst JH7110_SYSRST_UART1_APB>,
+ <&syscrg_rst JH7110_SYSRST_UART1_CORE>;
+ interrupts = <33>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@10020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10020000 0x0 0x10000>;
+ clocks = <&syscrg_clk JH7110_SYSCLK_UART2_CORE>,
+ <&syscrg_clk JH7110_SYSCLK_UART2_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg_rst JH7110_SYSRST_UART2_APB>,
+ <&syscrg_rst JH7110_SYSRST_UART2_CORE>;
+ interrupts = <34>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@12000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12000000 0x0 0x10000>;
+ clocks = <&syscrg_clk JH7110_SYSCLK_UART3_CORE>,
+ <&syscrg_clk JH7110_SYSCLK_UART3_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg_rst JH7110_SYSRST_UART3_APB>,
+ <&syscrg_rst JH7110_SYSRST_UART3_CORE>;
+ interrupts = <45>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@12010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12010000 0x0 0x10000>;
+ clocks = <&syscrg_clk JH7110_SYSCLK_UART4_CORE>,
+ <&syscrg_clk JH7110_SYSCLK_UART4_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg_rst JH7110_SYSRST_UART4_APB>,
+ <&syscrg_rst JH7110_SYSRST_UART4_CORE>;
+ interrupts = <46>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@12020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12020000 0x0 0x10000>;
+ clocks = <&syscrg_clk JH7110_SYSCLK_UART5_CORE>,
+ <&syscrg_clk JH7110_SYSCLK_UART5_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg_rst JH7110_SYSRST_UART5_APB>,
+ <&syscrg_rst JH7110_SYSRST_UART5_CORE>;
+ interrupts = <47>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+};
--
2.17.1
Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
StarFive JH7110 and JH7100 SoCs to boot with serial ports.
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index aed332a9d4ea..0c44484cd3a4 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
--
2.17.1
On 30/09/2022 07:56, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add bindings for the always-on clock generator on the JH7110
> RISC-V SoC by StarFive Technology Ltd.
>
(...)
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive-jh7110-sys.h>
> +
> + aoncrg: clock-controller@17000000 {
Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Best regards,
Krzysztof
On 30/09/2022 09:33, Hal Feng wrote:
> From: Jianlong Huang <[email protected]>
>
> Add pinctrl definitions for StarFive JH7110 SoC.
>
> Signed-off-by: Jianlong Huang <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../pinctrl/pinctrl-starfive-jh7110.h | 931 ++++++++++++++++++
> 1 file changed, 931 insertions(+)
> create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
>
> diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
> new file mode 100644
> index 000000000000..159cfcf6b915
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
> @@ -0,0 +1,931 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
> +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
> +
> +/* aon_iomux pin */
> +#define PAD_TESTEN 0
> +#define PAD_RGPIO0 1
> +#define PAD_RGPIO1 2
> +#define PAD_RGPIO2 3
> +#define PAD_RGPIO3 4
> +#define PAD_RSTN 5
> +#define PAD_GMAC0_MDC 6
> +#define PAD_GMAC0_MDIO 7
> +#define PAD_GMAC0_RXD0 8
> +#define PAD_GMAC0_RXD1 9
> +#define PAD_GMAC0_RXD2 10
> +#define PAD_GMAC0_RXD3 11
> +#define PAD_GMAC0_RXDV 12
> +#define PAD_GMAC0_RXC 13
> +#define PAD_GMAC0_TXD0 14
> +#define PAD_GMAC0_TXD1 15
> +#define PAD_GMAC0_TXD2 16
> +#define PAD_GMAC0_TXD3 17
> +#define PAD_GMAC0_TXEN 18
> +#define PAD_GMAC0_TXC 19
> +
> +/* aon_iomux dout */
> +#define GPO_AON_CLK_32K_OUT 2
> +#define GPO_AON_PTC0_PWM4 3
> +#define GPO_AON_PTC0_PWM5 4
> +#define GPO_AON_PTC0_PWM6 5
> +#define GPO_AON_PTC0_PWM7 6
> +#define GPO_AON_CLK_GCLK0 7
> +#define GPO_AON_CLK_GCLK1 8
> +#define GPO_AON_CLK_GCLK2 9
> +
> +/* aon_iomux doen */
> +#define OEN_AON_PTC0_OE_N_4 2
> +#define OEN_AON_PTC0_OE_N_5 3
> +#define OEN_AON_PTC0_OE_N_6 4
> +#define OEN_AON_PTC0_OE_N_7 5
> +
> +/* aon_iomux gin */
> +#define GPI_AON_PMU_GPIO_WAKEUP_0 0
> +#define GPI_AON_PMU_GPIO_WAKEUP_1 1
> +#define GPI_AON_PMU_GPIO_WAKEUP_2 2
> +#define GPI_AON_PMU_GPIO_WAKEUP_3 3
> +
> +/* aon_iomux gmac0 syscon */
> +#define PADCFG_PAD_GMAC0_MDC_SYSCON 0x58
> +#define PADCFG_PAD_GMAC0_MDIO_SYSCON 0x5c
> +#define PADCFG_PAD_GMAC0_RXD0_SYSCON 0x60
> +#define PADCFG_PAD_GMAC0_RXD1_SYSCON 0x64
> +#define PADCFG_PAD_GMAC0_RXD2_SYSCON 0x68
> +#define PADCFG_PAD_GMAC0_RXD3_SYSCON 0x6c
> +#define PADCFG_PAD_GMAC0_RXDV_SYSCON 0x70
> +#define PADCFG_PAD_GMAC0_RXC_SYSCON 0x74
> +#define PADCFG_PAD_GMAC0_TXD0_SYSCON 0x78
> +#define PADCFG_PAD_GMAC0_TXD1_SYSCON 0x7c
> +#define PADCFG_PAD_GMAC0_TXD2_SYSCON 0x80
> +#define PADCFG_PAD_GMAC0_TXD3_SYSCON 0x84
> +#define PADCFG_PAD_GMAC0_TXEN_SYSCON 0x88
> +#define PADCFG_PAD_GMAC0_TXC_SYSCON 0x8c
Register values do not belong to bindings. D
> +
> +/* aon_iomux func sel */
> +#define AON_IOMUX_CFGSAIF_144_ADDR 0x90
> +#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT 0x0
> +#define PAD_GMAC0_RXC_FUNC_SEL_MASK 0x3
Register values do not belong to bindings. D
> +
> +#define PAD_GMAC0_RXC_FUNC_SEL \
> + AON_IOMUX_CFGSAIF_144_ADDR \
> + PAD_GMAC0_RXC_FUNC_SEL_SHIFT \
> + PAD_GMAC0_RXC_FUNC_SEL_MASK
> +
> +/* sys_iomux pin */
> +#define PAD_GPIO0 0
> +#define PAD_GPIO1 1
> +#define PAD_GPIO2 2
> +#define PAD_GPIO3 3
> +#define PAD_GPIO4 4
> +#define PAD_GPIO5 5
> +#define PAD_GPIO6 6
> +#define PAD_GPIO7 7
> +#define PAD_GPIO8 8
> +#define PAD_GPIO9 9
> +#define PAD_GPIO10 10
> +#define PAD_GPIO11 11
> +#define PAD_GPIO12 12
> +#define PAD_GPIO13 13
> +#define PAD_GPIO14 14
> +#define PAD_GPIO15 15
> +#define PAD_GPIO16 16
> +#define PAD_GPIO17 17
> +#define PAD_GPIO18 18
> +#define PAD_GPIO19 19
> +#define PAD_GPIO20 20
> +#define PAD_GPIO21 21
> +#define PAD_GPIO22 22
> +#define PAD_GPIO23 23
> +#define PAD_GPIO24 24
> +#define PAD_GPIO25 25
> +#define PAD_GPIO26 26
> +#define PAD_GPIO27 27
> +#define PAD_GPIO28 28
> +#define PAD_GPIO29 29
> +#define PAD_GPIO30 30
> +#define PAD_GPIO31 31
> +#define PAD_GPIO32 32
> +#define PAD_GPIO33 33
> +#define PAD_GPIO34 34
> +#define PAD_GPIO35 35
> +#define PAD_GPIO36 36
> +#define PAD_GPIO37 37
> +#define PAD_GPIO38 38
> +#define PAD_GPIO39 39
> +#define PAD_GPIO40 40
> +#define PAD_GPIO41 41
> +#define PAD_GPIO42 42
> +#define PAD_GPIO43 43
> +#define PAD_GPIO44 44
> +#define PAD_GPIO45 45
> +#define PAD_GPIO46 46
> +#define PAD_GPIO47 47
> +#define PAD_GPIO48 48
> +#define PAD_GPIO49 49
> +#define PAD_GPIO50 50
> +#define PAD_GPIO51 51
> +#define PAD_GPIO52 52
> +#define PAD_GPIO53 53
> +#define PAD_GPIO54 54
> +#define PAD_GPIO55 55
> +#define PAD_GPIO56 56
> +#define PAD_GPIO57 57
> +#define PAD_GPIO58 58
> +#define PAD_GPIO59 59
> +#define PAD_GPIO60 60
> +#define PAD_GPIO61 61
> +#define PAD_GPIO62 62
> +#define PAD_GPIO63 63
> +#define PAD_SD0_CLK 64
> +#define PAD_SD0_CMD 65
> +#define PAD_SD0_DATA0 66
> +#define PAD_SD0_DATA1 67
> +#define PAD_SD0_DATA2 68
> +#define PAD_SD0_DATA3 69
> +#define PAD_SD0_DATA4 70
> +#define PAD_SD0_DATA5 71
> +#define PAD_SD0_DATA6 72
> +#define PAD_SD0_DATA7 73
> +#define PAD_SD0_STRB 74
> +#define PAD_GMAC1_MDC 75
> +#define PAD_GMAC1_MDIO 76
> +#define PAD_GMAC1_RXD0 77
> +#define PAD_GMAC1_RXD1 78
> +#define PAD_GMAC1_RXD2 79
> +#define PAD_GMAC1_RXD3 80
> +#define PAD_GMAC1_RXDV 81
> +#define PAD_GMAC1_RXC 82
> +#define PAD_GMAC1_TXD0 83
> +#define PAD_GMAC1_TXD1 84
> +#define PAD_GMAC1_TXD2 85
> +#define PAD_GMAC1_TXD3 86
> +#define PAD_GMAC1_TXEN 87
> +#define PAD_GMAC1_TXC 88
> +#define PAD_QSPI_SCLK 89
> +#define PAD_QSPI_CSn0 90
> +#define PAD_QSPI_DATA0 91
> +#define PAD_QSPI_DATA1 92
> +#define PAD_QSPI_DATA2 93
> +#define PAD_QSPI_DATA3 94
> +
> +#define GPO_LOW 0
> +#define GPO_HIGH 1
> +#define GPO_WAVE511_0_O_UART_TXSOUT 2
> +#define GPO_CAN0_CTRL_STBY 3
> +#define GPO_CAN0_CTRL_TST_NEXT_BIT 4
> +#define GPO_CAN0_CTRL_TST_SAMPLE_POINT 5
> +#define GPO_CAN0_CTRL_TXD 6
> +#define GPO_USB0_DRIVE_VBUS_IO 7
> +#define GPO_QSPI0_CSN1 8
> +#define GPO_SPDIF0_SPDIFO 9
> +#define GPO_HDMI0_CEC_SDA_OUT 10
> +#define GPO_HDMI0_DDC_SCL_OUT 11
> +#define GPO_HDMI0_DDC_SDA_OUT 12
> +#define GPO_WDT0_WDOGRES 13
> +#define GPO_I2C0_IC_CLK_OUT_A 14
> +#define GPO_I2C0_IC_DATA_OUT_A 15
> +#define GPO_SDIO0_BACK_END_POWER 16
> +#define GPO_SDIO0_CARD_POWER_EN 17
> +#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N 18
> +#define GPO_SDIO0_RST_N 19
> +#define GPO_UART0_SOUT 20
> +#define GPO_JTAG_DSP_TDO 21
> +#define GPO_JTAG_CPU_CERTIFICATION_TDO 22
> +#define GPO_PDM_4MIC0_DMIC_MCLK 23
> +#define GPO_PTC0_PWM_0 24
> +#define GPO_PTC0_PWM_1 25
> +#define GPO_PTC0_PWM_2 26
> +#define GPO_PTC0_PWM_3 27
> +#define GPO_PWMDAC0_LEFT_OUTPUT 28
> +#define GPO_PWMDAC0_RIGHT_OUTPUT 29
> +#define GPO_SPI0_SSPCLKOUT 30
> +#define GPO_SPI0_SSPFSSOUT 31
> +#define GPO_SPI0_SSPTXD 32
> +#define GPO_GMAC0_CLK_PHY 33
> +#define GPO_I2SRX0_BCLK_MST 34
> +#define GPO_I2SRX0_LRCK_MST 35
> +#define GPO_I2STX0_BCLK_MST 36
> +#define GPO_I2STX0_LRCK_MST 37
> +#define GPO_CRG0_MCLK_OUT 38
> +#define GPO_TDM0_CLK_MST 39
> +#define GPO_TDM0_PCM_SYNCOUT 40
> +#define GPO_TDM0_PCM_TXD 41
> +#define GPO_U7MC_TRACE0_TDATA_0 42
> +#define GPO_U7MC_TRACE0_TDATA_1 43
> +#define GPO_U7MC_TRACE0_TDATA_2 44
> +#define GPO_U7MC_TRACE0_TDATA_3 45
> +#define GPO_U7MC_TRACE0_TREF 46
> +#define GPO_CAN1_CTRL_STBY 47
> +#define GPO_CAN1_CTRL_TST_NEXT_BIT 48
> +#define GPO_CAN1_CTRL_TST_SAMPLE_POINT 49
> +#define GPO_CAN1_CTRL_TXD 50
> +#define GPO_I2C1_IC_CLK_OUT_A 51
> +#define GPO_I2C1_IC_DATA_OUT_A 52
> +#define GPO_SDIO1_BACK_END_POWER 53
> +#define GPO_SDIO1_CARD_POWER_EN 54
> +#define GPO_SDIO1_CCLK_OUT 55
> +#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N 56
> +#define GPO_SDIO1_CCMD_OUT 57
> +#define GPO_SDIO1_CDATA_OUT_0 58
> +#define GPO_SDIO1_CDATA_OUT_1 59
> +#define GPO_SDIO1_CDATA_OUT_2 60
> +#define GPO_SDIO1_CDATA_OUT_3 61
> +#define GPO_SDIO1_CDATA_OUT_4 62
> +#define GPO_SDIO1_CDATA_OUT_5 63
> +#define GPO_SDIO1_CDATA_OUT_6 64
> +#define GPO_SDIO1_CDATA_OUT_7 65
> +#define GPO_SDIO1_RST_N 66
> +#define GPO_UART1_RTS_N 67
> +#define GPO_UART1_SOUT 68
> +#define GPO_I2STX_4CH1_SDO0 69
> +#define GPO_I2STX_4CH1_SDO1 70
> +#define GPO_I2STX_4CH1_SDO2 71
> +#define GPO_I2STX_4CH1_SDO3 72
> +#define GPO_SPI1_SSPCLKOUT 73
> +#define GPO_SPI1_SSPFSSOUT 74
> +#define GPO_SPI1_SSPTXD 75
> +#define GPO_I2C2_IC_CLK_OUT_A 76
> +#define GPO_I2C2_IC_DATA_OUT_A 77
> +#define GPO_UART2_RTS_N 78
> +#define GPO_UART2_SOUT 79
> +#define GPO_SPI2_SSPCLKOUT 80
> +#define GPO_SPI2_SSPFSSOUT 81
> +#define GPO_SPI2_SSPTXD 82
> +#define GPO_I2C3_IC_CLK_OUT_A 83
> +#define GPO_I2C3_IC_DATA_OUT_A 84
> +#define GPO_UART3_SOUT 85
> +#define GPO_SPI3_SSPCLKOUT 86
> +#define GPO_SPI3_SSPFSSOUT 87
> +#define GPO_SPI3_SSPTXD 88
> +#define GPO_I2C4_IC_CLK_OUT_A 89
> +#define GPO_I2C4_IC_DATA_OUT_A 90
> +#define GPO_UART4_RTS_N 91
> +#define GPO_UART4_SOUT 92
> +#define GPO_SPI4_SSPCLKOUT 93
> +#define GPO_SPI4_SSPFSSOUT 94
> +#define GPO_SPI4_SSPTXD 95
> +#define GPO_I2C5_IC_CLK_OUT_A 96
> +#define GPO_I2C5_IC_DATA_OUT_A 97
> +#define GPO_UART5_RTS_N 98
> +#define GPO_UART5_SOUT 99
> +#define GPO_SPI5_SSPCLKOUT 100
> +#define GPO_SPI5_SSPFSSOUT 101
> +#define GPO_SPI5_SSPTXD 102
> +#define GPO_I2C6_IC_CLK_OUT_A 103
> +#define GPO_I2C6_IC_DATA_OUT_A 104
> +#define GPO_SPI6_SSPCLKOUT 105
> +#define GPO_SPI6_SSPFSSOUT 106
> +#define GPO_SPI6_SSPTXD 107
> +#define GPO_NONE 108
> +
> +#define OEN_LOW 0
> +#define OEN_HIGH 1
> +#define OEN_HDMI0_CEC_SDA_OEN 2
> +#define OEN_HDMI0_DDC_SCL_OEN 3
> +#define OEN_HDMI0_DDC_SDA_OEN 4
> +#define OEN_I2C0_IC_CLK_OE 5
> +#define OEN_I2C0_IC_DATA_OE 6
> +#define OEN_JTAG_DSP_TDO_OEN 7
> +#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE 8
> +#define OEN_PTC0_PWM_0_OE_N 9
> +#define OEN_PTC0_PWM_1_OE_N 10
> +#define OEN_PTC0_PWM_2_OE_N 11
> +#define OEN_PTC0_PWM_3_OE_N 12
> +#define OEN_SPI0_NSSPCTLOE 13
> +#define OEN_SPI0_NSSPOE 14
> +#define OEN_TDM0_NPCM_SYNCOE 15
> +#define OEN_TDM0_NPCM_TXDOE 16
> +#define OEN_I2C1_IC_CLK_OE 17
> +#define OEN_I2C1_IC_DATA_OE 18
> +#define OEN_SDIO1_CCMD_OUT_EN 19
> +#define OEN_SDIO1_CDATA_OUT_EN_0 20
> +#define OEN_SDIO1_CDATA_OUT_EN_1 21
> +#define OEN_SDIO1_CDATA_OUT_EN_2 22
> +#define OEN_SDIO1_CDATA_OUT_EN_3 23
> +#define OEN_SDIO1_CDATA_OUT_EN_4 24
> +#define OEN_SDIO1_CDATA_OUT_EN_5 25
> +#define OEN_SDIO1_CDATA_OUT_EN_6 26
> +#define OEN_SDIO1_CDATA_OUT_EN_7 27
> +#define OEN_SPI1_NSSPCTLOE 28
> +#define OEN_SPI1_NSSPOE 29
> +#define OEN_I2C2_IC_CLK_OE 30
> +#define OEN_I2C2_IC_DATA_OE 31
> +#define OEN_SPI2_NSSPCTLOE 32
> +#define OEN_SPI2_NSSPOE 33
> +#define OEN_I2C3_IC_CLK_OE 34
> +#define OEN_I2C3_IC_DATA_OE 35
> +#define OEN_SPI3_NSSPCTLOE 36
> +#define OEN_SPI3_NSSPOE 37
> +#define OEN_I2C4_IC_CLK_OE 38
> +#define OEN_I2C4_IC_DATA_OE 39
> +#define OEN_SPI4_NSSPCTLOE 40
> +#define OEN_SPI4_NSSPOE 41
> +#define OEN_I2C5_IC_CLK_OE 42
> +#define OEN_I2C5_IC_DATA_OE 43
> +#define OEN_SPI5_NSSPCTLOE 44
> +#define OEN_SPI5_NSSPOE 45
> +#define OEN_I2C6_IC_CLK_OE 46
> +#define OEN_I2C6_IC_DATA_OE 47
> +#define OEN_SPI6_NSSPCTLOE 48
> +#define OEN_SPI6_NSSPOE 49
> +#define OEN_NONE 50
> +
> +#define GPI_WAVE511_0_I_UART_RXSIN 0
> +#define GPI_CAN0_CTRL_RXD 1
> +#define GPI_USB0_OVERCURRENT_N_IO 2
> +#define GPI_SPDIF0_SPDIFI 3
> +#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN 4
> +#define GPI_HDMI0_CEC_SDA_IN 5
> +#define GPI_HDMI0_DDC_SCL_IN 6
> +#define GPI_HDMI0_DDC_SDA_IN 7
> +#define GPI_HDMI0_HPD 8
> +#define GPI_I2C0_IC_CLK_IN_A 9
> +#define GPI_I2C0_IC_DATA_IN_A 10
> +#define GPI_SDIO0_CARD_DETECT_N 11
> +#define GPI_SDIO0_CARD_INT_N 12
> +#define GPI_SDIO0_CARD_WRITE_PRT 13
> +#define GPI_UART0_SIN 14
> +#define GPI_JTAG_DSP_TCK 15
> +#define GPI_JTAG_DSP_TDI 16
> +#define GPI_JTAG_DSP_TMS 17
> +#define GPI_JTAG_DSP_TRST_N 18
> +#define GPI_JTAG_CPU_CERTIFICATION_TDI 19
> +#define GPI_JTAG_CPU_CERTIFICATION_TMS 20
> +#define GPI_PDM_4MIC0_DMIC0_DIN 21
> +#define GPI_PDM_4MIC0_DMIC1_DIN 22
> +#define GPI_I2SRX0_EXT_SDIN0 23
> +#define GPI_I2SRX0_EXT_SDIN1 24
> +#define GPI_I2SRX0_EXT_SDIN2 25
> +#define GPI_SPI0_SSPCLKIN 26
> +#define GPI_SPI0_SSPFSSIN 27
> +#define GPI_SPI0_SSPRXD 28
> +#define GPI_JTAG_CPU_CERTIFICATION_TCK 29
> +#define GPI_CRG0_EXT_MCLK 30
> +#define GPI_I2SRX0_BCLK_SLV 31
> +#define GPI_I2SRX0_LRCK_SLV 32
> +#define GPI_I2STX0_BCLK_SLV 33
> +#define GPI_I2STX0_LRCK_SLV 34
> +#define GPI_TDM0_CLK_SLV 35
> +#define GPI_TDM0_PCM_RXD 36
> +#define GPI_TDM0_PCM_SYNCIN 37
> +#define GPI_CAN1_CTRL_RXD 38
> +#define GPI_I2C1_IC_CLK_IN_A 39
> +#define GPI_I2C1_IC_DATA_IN_A 40
> +#define GPI_SDIO1_CARD_DETECT_N 41
> +#define GPI_SDIO1_CARD_INT_N 42
> +#define GPI_SDIO1_CARD_WRITE_PRT 43
> +#define GPI_SDIO1_CCMD_IN 44
> +#define GPI_SDIO1_CDATA_IN_0 45
> +#define GPI_SDIO1_CDATA_IN_1 46
> +#define GPI_SDIO1_CDATA_IN_2 47
> +#define GPI_SDIO1_CDATA_IN_3 48
> +#define GPI_SDIO1_CDATA_IN_4 49
> +#define GPI_SDIO1_CDATA_IN_5 50
> +#define GPI_SDIO1_CDATA_IN_6 51
> +#define GPI_SDIO1_CDATA_IN_7 52
> +#define GPI_SDIO1_DATA_STROBE 53
> +#define GPI_UART1_CTS_N 54
> +#define GPI_UART1_SIN 55
> +#define GPI_SPI1_SSPCLKIN 56
> +#define GPI_SPI1_SSPFSSIN 57
> +#define GPI_SPI1_SSPRXD 58
> +#define GPI_I2C2_IC_CLK_IN_A 59
> +#define GPI_I2C2_IC_DATA_IN_A 60
> +#define GPI_UART2_CTS_N 61
> +#define GPI_UART2_SIN 62
> +#define GPI_SPI2_SSPCLKIN 63
> +#define GPI_SPI2_SSPFSSIN 64
> +#define GPI_SPI2_SSPRXD 65
> +#define GPI_I2C3_IC_CLK_IN_A 66
> +#define GPI_I2C3_IC_DATA_IN_A 67
> +#define GPI_UART3_SIN 68
> +#define GPI_SPI3_SSPCLKIN 69
> +#define GPI_SPI3_SSPFSSIN 70
> +#define GPI_SPI3_SSPRXD 71
> +#define GPI_I2C4_IC_CLK_IN_A 72
> +#define GPI_I2C4_IC_DATA_IN_A 73
> +#define GPI_UART4_CTS_N 74
> +#define GPI_UART4_SIN 75
> +#define GPI_SPI4_SSPCLKIN 76
> +#define GPI_SPI4_SSPFSSIN 77
> +#define GPI_SPI4_SSPRXD 78
> +#define GPI_I2C5_IC_CLK_IN_A 79
> +#define GPI_I2C5_IC_DATA_IN_A 80
> +#define GPI_UART5_CTS_N 81
> +#define GPI_UART5_SIN 82
> +#define GPI_SPI5_SSPCLKIN 83
> +#define GPI_SPI5_SSPFSSIN 84
> +#define GPI_SPI5_SSPRXD 85
> +#define GPI_I2C6_IC_CLK_IN_A 86
> +#define GPI_I2C6_IC_DATA_IN_A 87
> +#define GPI_SPI6_SSPCLKIN 88
> +#define GPI_SPI6_SSPFSSIN 89
> +#define GPI_SPI6_SSPRXD 90
> +#define GPI_NONE 91
> +
> +/* sys_iomux syscon */
> +#define PADCFG_PAD_GMAC1_MDC_SYSCON 0x24c
> +#define PADCFG_PAD_GMAC1_MDIO_SYSCON 0x250
> +#define PADCFG_PAD_GMAC1_RXD0_SYSCON 0x254
Register values do not belong to bindings. Drop everything also below.
> +#define PADCFG_PAD_GMAC1_RXD1_SYSCON 0x258
> +#define PADCFG_PAD_GMAC1_RXD2_SYSCON 0x25c
> +#define PADCFG_PAD_GMAC1_RXD3_SYSCON 0x260
> +#define PADCFG_PAD_GMAC1_RXDV_SYSCON 0x264
> +#define PADCFG_PAD_GMAC1_RXC_SYSCON 0x268
> +#define PADCFG_PAD_GMAC1_TXD0_SYSCON 0x26c
Best regards,
Krzysztof
On 30/09/2022 00:26, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add bindings for the system clock generator on the JH7110
> RISC-V SoC by StarFive Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
(...)
> + '#clock-cells':
> + const: 1
> + description:
> + See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices.
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + syscrg_clk: clock-controller@13020000 {
Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
> + compatible = "starfive,jh7110-clkgen-sys";
> + clocks = <&osc>, <&gmac1_rmii_refin>,
> + <&gmac1_rgmii_rxin>,
> + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> + <&tdm_ext>, <&mclk_ext>;
> + clock-names = "osc", "gmac1_rmii_refin",
> + "gmac1_rgmii_rxin",
> + "i2stx_bclk_ext", "i2stx_lrck_ext",
> + "i2srx_bclk_ext", "i2srx_lrck_ext",
> + "tdm_ext", "mclk_ext";
> + #clock-cells = <1>;
> + };
Best regards,
Krzysztof
On 30/09/2022 09:38, Hal Feng wrote:
> From: Jianlong Huang <[email protected]>
>
> Add pinctrl bindings for StarFive JH7110 SoC.
>
> Signed-off-by: Jianlong Huang <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../pinctrl/starfive,jh7110-pinctrl.yaml | 202 ++++++++++++++++++
> 1 file changed, 202 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
> new file mode 100644
> index 000000000000..482012ad8a14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Pin Controller Device Tree Bindings
> +
> +description: |
> + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
> +
> +maintainers:
> + - Jianlong Huang <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - starfive,jh7110-sys-pinctrl
> + - starfive,jh7110-aon-pinctrl
Wrong indentation.
Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
> +
> + reg:
> + minItems: 2
No need.
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: control
This does not match reg at all. Again - not tested.
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + "#gpio-cells":
> + const: 2
> +
> + interrupts:
> + maxItems: 1
> + description: The GPIO parent interrupt.
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 2
> +
> + ngpios:
> + enum:
> + - 64
> + - 4
Wrong indentation. Increasing order.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - "#gpio-cells"
> + - interrupts
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> +patternProperties:
This goes before required block
> + '-[0-9]+$':
Too loose pattern. Need some more specific pattern. What do you exactly
match here?
Missing description.
> + type: object
> + patternProperties:
> + '-pins$':
> + type: object
> + description: |
> + A pinctrl node should contain at least one subnode representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to
> + muxer configuration, system signal configuration, pin groups for
> + vin/vout module, pin voltage, mux functions for output, mux functions
> + for output enable, mux functions for input.
> +
> + properties:
> + starfive,pins:
No, use generic pinctrl bindings.
> + description: |
> + The list of pin identifiers that properties in the node apply to.
> + This should be set using the PAD_GPIOX macros.
> + This has to be specified.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 63
> +
> + starfive,pinmux:
No, use generic pinctrl bindings.
> + description: |
> + The list of GPIOs and their mux functions that properties in the
> + node apply to. This should be set using the PAD_GPIOX_FUNC_SEL
> + macro with its value.
> + This is optional for some pins.
> + The value of PAD_GPIOX_FUNC_SEL macro can selects:
> + 0: GPIOX mux function 0,
> + 1: GPIOX mux function 1,
> + 2: GPIOX mux function 2.
> +
> + starfive,pin-ioconfig:
> + description: |
> + This is used to configure the core settings of system signals.
> + The combination of GPIO_IE or GPIO_DS or GPIO_PU or GPIO_PD or
> + GPIO_SLEW or GPIO_SMT or GPIO_POS.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + starfive,padmux:
> + description: |
> + The padmux is for vin/vout module to select pin groups.
> + 0: vout will be set at pins from PAD_GPIO7 to PAD_GPIO34,
> + when PAD_GPIOX_FUNC_SEL is set as 1.
> + vin will be set at pins from PAD_GPIO6 to PAD_GPIO20.
> + when PAD_GPIOX_FUNC_SEL is set as 2.
> + 1: vout will be set at pins from PAD_GPIO36 to PAD_GPIO63,
> + when PAD_GPIOX_FUNC_SEL is set as 1.
> + vin will be set at pins from PAD_GPIO21 to PAD_GPIO35.
> + when PAD_GPIOX_FUNC_SEL is set as 2.
> + 2: vin will be set at pins from PAD_GPIO36 to PAD_GPIO50,
> + when PAD_GPIOX_FUNC_SEL is set as 2
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + starfive,pin-syscon:
> + description: |
> + This is used to set pin voltage,
> + 0: 3.3V, 1: 2.5V, 2: 1.8V.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + starfive,pin-gpio-dout:
No, use generic pinctrl bindings.
> + description: |
> + This is used to set their mux functions for output.
> + This should be set using the GPO_XXX macro,
> + such as GPO_LOW, GPO_UART0_SOUT.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 107
> +
> + starfive,pin-gpio-doen:
No, use generic pinctrl bindings.
> + description: |
> + This is used to set their mux functions for output enable.
> + This should be set using the OEN_XXX macro,
> + such as OEN_LOW, OEN_I2C0_IC_CLK_OE.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 49
> +
> + starfive,pin-gpio-din:
No, use generic pinctrl bindings.
> + description: |
> + This is used to set their mux functions for input.
> + This should be set using the GPI_XXX macro,
> + such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 90
> +
> + additionalProperties: false
> +
> + additionalProperties: false
> +
> +additionalProperties: false
Missing allof to generic pinctrl bindings.
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive-jh7110-sys.h>
> + #include <dt-bindings/reset/starfive-jh7110.h>
> + #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> + gpio: gpio@13040000 {
> + compatible = "starfive,jh7110-sys-pinctrl";
> + reg = <0x0 0x13040000 0x0 0x10000>;
> + reg-names = "control";
> + clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
> + resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
> + interrupts = <86>;
> + interrupt-controller;
> + #gpio-cells = <2>;
> + ngpios = <64>;
> + status = "okay";
> +
> + uart0_pins: uart0-pins {
Explain me please how it can possible match your pattern: '-[0-9]+$':
You really wrote something which was not tested and cannot work.
> + uart0-pins-tx {
> + starfive,pins = <PAD_GPIO5>;
> + starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
> + starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
> + starfive,pin-gpio-doen = <OEN_LOW>;
> + };
> +
> + uart0-pins-rx {
> + starfive,pins = <PAD_GPIO6>;
> + starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
> + starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
> + starfive,pin-gpio-doen = <OEN_HIGH>;
> + starfive,pin-gpio-din = <GPI_UART0_SIN>;
> + };
> + };
> + };
> +
> + &uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
Drop, obvious.
> + };
> +
> +...
Best regards,
Krzysztof
On Fri, 30 Sep 2022 15:38:45 +0800, Hal Feng wrote:
> From: Jianlong Huang <[email protected]>
>
> Add pinctrl bindings for StarFive JH7110 SoC.
>
> Signed-off-by: Jianlong Huang <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../pinctrl/starfive,jh7110-pinctrl.yaml | 202 ++++++++++++++++++
> 1 file changed, 202 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml:18:5: [warning] wrong indentation: expected 6 but found 4 (indentation)
./Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml:49:5: [warning] wrong indentation: expected 6 but found 4 (indentation)
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml: error checking schema file
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml: ignoring, error in schema: patternProperties: -[0-9]+$: patternProperties: -pins$: properties: starfive,pinmux
Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.example.dts:21:18: fatal error: dt-bindings/clock/starfive-jh7110-sys.h: No such file or directory
21 | #include <dt-bindings/clock/starfive-jh7110-sys.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1420: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Fri, Sep 30, 2022 at 01:56:32PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add bindings for the always-on clock generator on the JH7110
> RISC-V SoC by StarFive Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../clock/starfive,jh7110-clkgen-aon.yaml | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
> new file mode 100644
> index 000000000000..029ff57b9e3e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-aon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Always-On Clock Generator
> +
> +maintainers:
> + - Emil Renner Berthing <[email protected]>
> + - Xingyu Wu <[email protected]>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-clkgen-aon
> +
> + clocks:
> + items:
> + - description: Main Oscillator
> + - description: RTC clock
> + - description: RMII reference clock
> + - description: RGMII RX clock
> + - description: STG AXI/AHB clock
> + - description: APB Bus clock
> +
> + clock-names:
> + items:
> + - const: osc
> + - const: clk_rtc
> + - const: gmac0_rmii_refin
> + - const: gmac0_rgmii_rxin
> + - const: stg_axiahb
> + - const: apb_bus_func
> +
> + '#clock-cells':
> + const: 1
> + description:
> + See <dt-bindings/clock/starfive-jh7110-aon.h> for valid indices.
No 'reg'? How do you access this h/w then? If it is part of some block,
we need to see the full picture.
Rob
Add Kconfig options to select the specified StarFive SoC. Select
necessary Kconfig options required by the specified SoC for booting.
Signed-off-by: Hal Feng <[email protected]>
---
arch/riscv/Kconfig.socs | 27 ++++++++++++++++++++++++++-
arch/riscv/boot/dts/starfive/Makefile | 4 ++--
drivers/clk/starfive/Kconfig | 14 ++++++--------
drivers/pinctrl/starfive/Kconfig | 6 ++----
drivers/reset/Kconfig | 1 -
5 files changed, 36 insertions(+), 16 deletions(-)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 10f68a4359f9..321c448e7b6f 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,10 +22,35 @@ config SOC_STARFIVE
bool "StarFive SoCs"
select PINCTRL
select RESET_CONTROLLER
+ select RESET_STARFIVE
+ help
+ This enables support for StarFive SoC platform hardware.
+
+if SOC_STARFIVE
+
+config SOC_JH7100
+ bool "StarFive JH7100 SoC support"
+ depends on SOC_STARFIVE
select SIFIVE_L2
select SIFIVE_PLIC
+ select CLK_STARFIVE_JH7100
+ select PINCTRL_STARFIVE_JH7100
+ default SOC_STARFIVE
help
- This enables support for StarFive SoC platform hardware.
+ This enables support for StarFive JH7100 SoC.
+
+config SOC_JH7110
+ bool "StarFive JH7110 SoC support"
+ depends on SOC_STARFIVE
+ select SIFIVE_L2
+ select SIFIVE_PLIC
+ select CLK_STARFIVE_JH7110_SYS
+ select PINCTRL_STARFIVE_JH7110
+ default SOC_STARFIVE
+ help
+ This enables support for StarFive JH7110 SoC.
+
+endif
config SOC_VIRT
bool "QEMU Virt Machine"
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index e1237dbc6aac..a6ecd3c2ec7d 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
-dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
+dtb-$(CONFIG_SOC_JH7100) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_JH7110) += jh7110-starfive-visionfive-v2.dtb
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 42aad3b553cb..d0490e9f42db 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -5,36 +5,34 @@ config CLK_STARFIVE
config CLK_STARFIVE_JH7100
bool "StarFive JH7100 clock support"
- depends on SOC_STARFIVE || COMPILE_TEST
+ depends on SOC_JH7100 || COMPILE_TEST
select CLK_STARFIVE
- default SOC_STARFIVE
help
Say yes here to support the clock controller on the StarFive JH7100
SoC.
config CLK_STARFIVE_JH7100_AUDIO
tristate "StarFive JH7100 audio clock support"
- depends on SOC_STARFIVE || COMPILE_TEST
+ depends on SOC_JH7100 || COMPILE_TEST
select CLK_STARFIVE
- default m if SOC_STARFIVE
+ default m if SOC_JH7100
help
Say Y or M here to support the audio clocks on the StarFive JH7100
SoC.
config CLK_STARFIVE_JH7110_SYS
bool "StarFive JH7110 system clock support"
- depends on SOC_STARFIVE || COMPILE_TEST
+ depends on SOC_JH7110 || COMPILE_TEST
select CLK_STARFIVE
- default SOC_STARFIVE
help
Say yes here to support the system clock controller on the
StarFive JH7110 SoC.
config CLK_STARFIVE_JH7110_AON
tristate "StarFive JH7110 always-on clock support"
- depends on SOC_STARFIVE || COMPILE_TEST
+ depends on SOC_JH7110 || COMPILE_TEST
select CLK_STARFIVE
- default m if SOC_STARFIVE
+ default m if SOC_JH7110
help
Say yes here to support the always-on clock controller on the
StarFive JH7110 SoC.
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index fde39f4a7922..d09bdf6d3029 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -2,7 +2,7 @@
config PINCTRL_STARFIVE_JH7100
tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
- depends on SOC_STARFIVE || COMPILE_TEST
+ depends on SOC_JH7100 || COMPILE_TEST
depends on OF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
@@ -10,7 +10,6 @@ config PINCTRL_STARFIVE_JH7100
select GPIOLIB
select GPIOLIB_IRQCHIP
select OF_GPIO
- default SOC_STARFIVE
help
Say yes here to support pin control on the StarFive JH7100 SoC.
This also provides an interface to the GPIO pins not used by other
@@ -28,10 +27,9 @@ config PINCTRL_STARFIVE
config PINCTRL_STARFIVE_JH7110
bool "Pinctrl and GPIO driver for the StarFive JH7110 SoC"
- depends on SOC_STARFIVE || COMPILE_TEST
+ depends on SOC_JH7110 || COMPILE_TEST
depends on OF
select PINCTRL_STARFIVE
- default SOC_STARFIVE
help
Say yes here to support pin control on the StarFive JH7110 SoC.
This also provides an interface to the GPIO pins not used by other
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 8121de5ecc3c..c001879bd890 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -228,7 +228,6 @@ config RESET_SOCFPGA
config RESET_STARFIVE
bool "StarFive SoC Reset Driver"
depends on SOC_STARFIVE || COMPILE_TEST
- default SOC_STARFIVE
help
This enables the reset controller driver for the StarFive SoCs.
--
2.17.1
On Thu, Sep 29, 2022 at 10:32:04PM +0800, Hal Feng wrote:
> Store the necessary properties in device tree instead of .c file,
> in order to apply this reset driver to other StarFive SoCs.
>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../bindings/reset/starfive,jh7100-reset.yaml | 20 ++++++++
> arch/riscv/boot/dts/starfive/jh7100.dtsi | 3 ++
> drivers/reset/reset-starfive-jh7100.c | 50 +++++++++++++------
> 3 files changed, 57 insertions(+), 16 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> index 300359a5e14b..3eff3f72a1ed 100644
> --- a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> @@ -20,19 +20,39 @@ properties:
> "#reset-cells":
> const: 1
>
> + starfive,assert-offset:
> + description: Offset of the first ASSERT register
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + starfive,status-offset:
> + description: Offset of the first STATUS register
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + starfive,nr-resets:
> + description: Number of reset signals
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> required:
> - compatible
> - reg
> - "#reset-cells"
> + - starfive,assert-offset
> + - starfive,status-offset
> + - starfive,nr-resets
Adding required properties is a red flag. You can't add required
properties to an existing binding. That breaks the ABI unless the OS
deals with the properties being absent. If the OS has to do that, then
why add them in the first place? All this should be implied by the
compatible string.
Rob
On Fri, Sep 30, 2022 at 09:54:14PM +0100, Ben Dooks wrote:
> On 30/09/2022 10:06, Hal Feng wrote:
> > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
> >
> > Signed-off-by: Hal Feng <[email protected]>
>
> That might be useful for other users at some point an I don't
> think it adds much code.
Honestly I think this should be applied for 6.1, for parity with the
other SoCs that have their serial console enabled by default.
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
>
> > ---
> > arch/riscv/configs/defconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index aed332a9d4ea..0c44484cd3a4 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
> > CONFIG_INPUT_MOUSEDEV=y
> > CONFIG_SERIAL_8250=y
> > CONFIG_SERIAL_8250_CONSOLE=y
> > +CONFIG_SERIAL_8250_DW=y
> > CONFIG_SERIAL_OF_PLATFORM=y
> > CONFIG_VIRTIO_CONSOLE=y
> > CONFIG_HW_RANDOM=y
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Quoting Hal Feng (2022-09-29 10:54:59)
> From: Emil Renner Berthing <[email protected]>
>
> The clock control registers on the StarFive SoCs work identically,
> so factor out the code then drivers for different SoCs can share
> it without depending on each other. No functional change.
Sounds great! No functional change! But to verify that it is pretty
hard. Can you generate the patch with `git format-patch -M -C` and not
rename anything initially? I hope that will allow us to see that really
nothing has changed except code is moved from one file to another. Then
the next patch can be the sed command to rename to starfive.
As the patch is right now, I'm not particularly interested in going
through 700 lines to make sure nothing really changed.
On 30/09/2022 10:06, Hal Feng wrote:
> Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> StarFive JH7110 and JH7100 SoCs to boot with serial ports.
>
> Signed-off-by: Hal Feng <[email protected]>
That might be useful for other users at some point an I don't
think it adds much code.
> ---
> arch/riscv/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index aed332a9d4ea..0c44484cd3a4 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
> CONFIG_INPUT_MOUSEDEV=y
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_DW=y
> CONFIG_SERIAL_OF_PLATFORM=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
Quoting Hal Feng (2022-09-29 10:56:02)
> Clock registers address region is shared with reset controller
> on the new StarFive JH7110 SoC. Change to use regmap framework
> to allow base address sharing and preparation for JH7110 clock
> support.
Do the reset and clk parts share actual registers, where we would need
to lock between rmw? Or is regmap just nice to have because it wraps up
the register APIs with some extra features?
>
> Signed-off-by: Hal Feng <[email protected]>
> ---
[...]
> diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
> index 014e36f17595..410aa6e06842 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7100.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7100.c
> @@ -10,6 +10,7 @@
> #include <linux/clk-provider.h>
> #include <linux/device.h>
> #include <linux/init.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/mod_devicetable.h>
> #include <linux/platform_device.h>
>
> @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> if (!priv)
> return -ENOMEM;
>
> - spin_lock_init(&priv->rmw_lock);
> priv->dev = &pdev->dev;
> - priv->base = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(priv->base))
> - return PTR_ERR(priv->base);
> + priv->regmap = device_node_to_regmap(priv->dev->of_node);
This is sad. Why do we need to make a syscon? Can we instead use the
auxiliary bus to make a reset device that either gets a regmap made here
in this driver or uses a void __iomem * mapped with ioremap
(priv->base)?
> + if (IS_ERR(priv->regmap)) {
> + dev_err(priv->dev, "failed to get regmap (error %ld)\n",
> + PTR_ERR(priv->regmap));
> + return PTR_ERR(priv->regmap);
On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> From: Jianlong Huang <[email protected]>
>
> Add the SoC name to make it more clear. Also the next generation StarFive
> SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> No functional change.
>
> Signed-off-by: Jianlong Huang <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
> arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
> drivers/pinctrl/starfive/Kconfig | 2 +-
> drivers/pinctrl/starfive/Makefile | 2 +-
> .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} | 2 +-
> .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} | 6 +++---
> 6 files changed, 8 insertions(+), 8 deletions(-)
> rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
>
Reviewed-by: Rob Herring <[email protected]>
Would be good to pull this out separately and apply for 6.1. It's kind
of messy with cross tree dependencies.
On Thu, Sep 29, 2022 at 18:59:24 +0100, Conor Dooley wrote:
> On Thu, Sep 29, 2022 at 04:45:26PM +0200, Krzysztof Kozlowski wrote:
> > On 29/09/2022 16:31, Hal Feng wrote:
> >
> > > This series is also available at
> > > https://github.com/hal-feng/linux/commits/visionfive2-minimal
> > >
> > > [1]
> > > https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-c
> > > ore-risc-v-sbc-linux/
> > > [2] https://wiki.rvspace.org/
> > >
> > > Emil Renner Berthing (17):
> > > dt-bindings: riscv: Add StarFive JH7110 bindings
> > > dt-bindings: timer: Add StarFive JH7110 clint
> > > dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> > > dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
> > > soc: sifive: l2 cache: Convert to platform driver
> > > soc: sifive: l2 cache: Add StarFive JH71x0 support
> > > reset: starfive: jh7100: Use 32bit I/O on 32bit registers
> > > dt-bindings: reset: Add StarFive JH7110 reset definitions
> > > clk: starfive: Factor out common clock driver code
> > > dt-bindings: clock: Add StarFive JH7110 system clock definitions
> > > dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
> > > clk: starfive: Add StarFive JH7110 system clock driver
> > > dt-bindings: clock: Add StarFive JH7110 always-on definitions
> > > dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
> > > clk: starfive: Add StarFive JH7110 always-on clock driver
> > > RISC-V: Add initial StarFive JH7110 device tree
> > > RISC-V: Add StarFive JH7110 VisionFive2 board device tree
> >
> > Where is the rest of patches? Lists got only 5 of them. Anyway this is
> > a bit too big patchset. Split per subsystem.
>
> They seem to be coming in over time in dribs and drabs. I assume it is not
a
> mailing list problem given how many lists are CCed on the mail and the
fact
> that they have different providers.
>
> For v2 (or multiple v2s) please fix up your process so that this gets sent
> normally and not a couple of patches every hour.
Our email server has technical issue and we are aware of this.
Will fix in next revision. Sorry for the inconvenience caused.
Best Regards,
Hal
On Fri, Sep 30, 2022 at 03:49:14PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add initial device tree for the JH7110 RISC-V SoC by
> StarFive Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Jianlong Huang <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
There's little point reviewing this dt since there's a load of issues
that you can trivially find by running dtbs_check/dt_binding_check, but
this SoB change is wrong - if Emil wrote the patch, then Jianlong's SoB
is either redundant or should be accompanied by a Co-developed-by tag.
Ditto for patch 28/30 "RISC-V: Add StarFive JH7110 VisionFive2 board
device tree".
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
> 1 file changed, 449 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..46f418d4198a
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +
> + osc: osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + clk_rtc: clk_rtc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac0_rmii_refin: gmac0_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
I assume, given osc has it's frequency set in the board dts, that these
are all oscillators on the SoC?
> + };
> +
> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + gmac1_rmii_refin: gmac1_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> +
> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + i2stx_bclk_ext: i2stx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + };
> +
> + i2stx_lrck_ext: i2stx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <192000>;
> + };
> +
> + i2srx_bclk_ext: i2srx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + };
> +
> + i2srx_lrck_ext: i2srx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <192000>;
> + };
> +
> + tdm_ext: tdm_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <49152000>;
> + };
> +
> + mclk_ext: mclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <49152000>;
> + };
> + syscrg: syscrg@13020000 {
The generic node name for syscons is just "syscon" afaik.
> + compatible = "syscon", "simple-mfd";
> + reg = <0x0 0x13020000 0x0 0x10000>;
> +
> + aoncrg: aoncrg@17000000 {
Again, syscon as the node name?
> + compatible = "syscon", "simple-mfd";
> + reg = <0x0 0x17000000 0x0 0x10000>;
> +
> + gpio: gpio@13040000 {
Someone else (Krzysztof maybe?) should comment, but is "pinctrl" not the
genric node name for pinctrl nodes?
Thanks,
Conor.
> + compatible = "starfive,jh7110-sys-pinctrl";
> + reg = <0x0 0x13040000 0x0 0x10000>;
> + reg-names = "control";
> + clocks = <&syscrg_clk JH7110_SYSCLK_IOMUX>;
> + resets = <&syscrg_rst JH7110_SYSRST_IOMUX>;
> + interrupts = <86>;
> + interrupt-controller;
> + #gpio-cells = <2>;
> + ngpios = <64>;
> + };
> +
> + gpioa: gpio@17020000 {
> + compatible = "starfive,jh7110-aon-pinctrl";
> + reg = <0x0 0x17020000 0x0 0x10000>;
> + reg-names = "control";
> + resets = <&aoncrg_rst JH7110_AONRST_AON_IOMUX>;
> + interrupts = <85>;
> + interrupt-controller;
> + #gpio-cells = <2>;
> + ngpios = <4>;
> + };
> +
> + uart0: serial@10000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10000000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART0_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART0_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART0_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART0_CORE>;
> + interrupts = <32>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@10010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10010000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART1_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART1_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART1_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART1_CORE>;
> + interrupts = <33>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@10020000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10020000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART2_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART2_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART2_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART2_CORE>;
> + interrupts = <34>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@12000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12000000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART3_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART3_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART3_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART3_CORE>;
> + interrupts = <45>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@12010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12010000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART4_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART4_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART4_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART4_CORE>;
> + interrupts = <46>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart5: serial@12020000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12020000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART5_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART5_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART5_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART5_CORE>;
> + interrupts = <47>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> +};
> --
> 2.17.1
>
On Fri, Sep 30, 2022 at 03:53:53PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <[email protected]>
>
> Add a minimal device tree for StarFive JH7110 VisionFive2 board.
> Support booting and basic clock/reset/pinctrl/uart drivers.
>
I would like to see a link to the publicly available datasheet or
documentation for the board (and for the SoC in patch 28) please.
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Jianlong Huang <[email protected]>
Ditto from patch 28 re: the SoB chain.
> Signed-off-by: Hal Feng <[email protected]>
> ---
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> new file mode 100644
> index 000000000000..6b9fe32c7eac
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> +/ {
> + model = "StarFive VisionFive V2";
> + compatible = "starfive,visionfive-v2", "starfive,jh7110";
> +
> + aliases {
> + serial0 = &uart0;
> + };
Should we also have a chosen node here?
> +
> + cpus {
> + timebase-frequency = <4000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
What is going to happen to the 2 GB variant if they attempt to use this
devicetree?
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + linux,cma {
> + compatible = "shared-dma-pool";
> + reusable;
> + size = <0x0 0x20000000>;
> + alignment = <0x0 0x1000>;
> + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
> + linux,cma-default;
> + };
> +
> + e24_mem: e24@c0000000 {
I had a conversation previously with Icenowy [0] about the e24 on the
jh7100 that didn't really come to a conclusion about how to represent
it there - but looks like you've decided that it should be a remoteproc
for the jh7100?
Is this another situation where peripherals appear at different
addresses for the e24 compared to the u74s? Or has that changed for the
jh7100, and really the e24 should be described in the CPUs node? If it
is the latter, you can pick the first patch from [0] into your series.
0 - https://lore.kernel.org/linux-riscv/[email protected]/
> + reg = <0x0 0xc0110000 0x0 0xf0000>;
> + no-map;
> + };
> +
> + xrp_reserved: xrpbuffer@f0000000 {
"Following the generic-names recommended practice, node names should
reflect the purpose of the node (ie. “framebuffer” or “dma-pool”)."
I tried googling around for an explanation for what the xrp was, and all
I could find was this out-of-tree text binding:
https://github.com/foss-xtensa/xrp/blob/master/xrp-kernel/cdns%2Cxrp-hw-simple%2Cv1.txt
Thanks,
Conor.
> + reg = <0x0 0xf0000000 0x0 0x01ffffff>,
> + <0x0 0xf2000000 0x0 0x00001000>,
> + <0x0 0xf2001000 0x0 0x00fff000>,
> + <0x0 0xf3000000 0x0 0x00001000>;
> + };
> +
> + };
> +
> + gpio-restart {
> + compatible = "gpio-restart";
> + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
> + priority = <224>;
> + };
> +};
> +
> +&gpio {
> + uart0_pins: uart0-pins {
> + uart0-pins-tx {
> + starfive,pins = <PAD_GPIO5>;
> + starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
> + starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
> + starfive,pin-gpio-doen = <OEN_LOW>;
> + };
> +
> + uart0-pins-rx {
> + starfive,pins = <PAD_GPIO6>;
> + starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
> + starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
> + starfive,pin-gpio-doen = <OEN_HIGH>;
> + starfive,pin-gpio-din = <GPI_UART0_SIN>;
> + };
> + };
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> --
> 2.17.1
>
Hi Hal,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.0-rc7 next-20220930]
[cannot apply to clk/clk-next linusw-pinctrl/devel pza/reset/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Hal-Feng/Basic-StarFive-JH7110-RISC-V-SoC-support/20220930-202655
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 987a926c1d8a40e4256953b04771fbdb63bc7938
config: riscv-buildonly-randconfig-r006-20220926
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/9ef892ebb8b08cc65ab165f4962864e12b5c216d
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Hal-Feng/Basic-StarFive-JH7110-RISC-V-SoC-support/20220930-202655
git checkout 9ef892ebb8b08cc65ab165f4962864e12b5c216d
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/pinctrl/starfive/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
>> drivers/pinctrl/starfive/pinctrl-starfive.c:462:51: warning: variable 'value' is uninitialized when used here [-Wuninitialized]
ret = info->starfive_iopad_sel_func(pdev, pctl, value);
^~~~~
drivers/pinctrl/starfive/pinctrl-starfive.c:397:11: note: initialize the variable 'value' to silence this warning
u32 value;
^
= 0
drivers/pinctrl/starfive/pinctrl-starfive.c:32:1: warning: unused function 'starfive_pinctrl_find_group_by_name' [-Wunused-function]
starfive_pinctrl_find_group_by_name(struct pinctrl_dev *pctldev,
^
2 warnings generated.
vim +/value +462 drivers/pinctrl/starfive/pinctrl-starfive.c
386
387 int starfive_pinctrl_probe(struct platform_device *pdev,
388 const struct starfive_pinctrl_soc_info *info)
389 {
390 struct device *dev = &pdev->dev;
391 struct pinctrl_desc *starfive_pinctrl_desc;
392 struct starfive_pinctrl *pctl;
393 struct resource *res;
394 struct reset_control *rst;
395 struct clk *clk;
396 int ret, i;
397 u32 value;
398
399 if (!info || !info->pins || !info->npins) {
400 dev_err(&pdev->dev, "wrong pinctrl info\n");
401 return -EINVAL;
402 }
403
404 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
405 if (!pctl)
406 return -ENOMEM;
407
408 pctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
409 sizeof(*pctl->pin_regs),
410 GFP_KERNEL);
411 if (!pctl->pin_regs)
412 return -ENOMEM;
413
414 for (i = 0; i < info->npins; i++) {
415 pctl->pin_regs[i].io_conf_reg = -1;
416 pctl->pin_regs[i].gpo_dout_reg = -1;
417 pctl->pin_regs[i].gpo_doen_reg = -1;
418 pctl->pin_regs[i].func_sel_reg = -1;
419 pctl->pin_regs[i].syscon_reg = -1;
420 pctl->pin_regs[i].pad_sel_reg = -1;
421 }
422
423 pctl->padctl_base = devm_platform_ioremap_resource_byname(pdev, "control");
424 if (IS_ERR(pctl->padctl_base))
425 return PTR_ERR(pctl->padctl_base);
426
427 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
428 if (res) {
429 pctl->gpio_base = devm_ioremap_resource(dev, res);
430 if (IS_ERR(pctl->gpio_base))
431 return PTR_ERR(pctl->gpio_base);
432 }
433
434 clk = devm_clk_get_optional(dev, NULL);
435 if (IS_ERR(clk))
436 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
437
438 rst = devm_reset_control_get_exclusive(dev, NULL);
439 if (IS_ERR(rst))
440 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
441
442 if (clk) {
443 ret = clk_prepare_enable(clk);
444 if (ret)
445 return dev_err_probe(dev, ret, "could not enable clock\n");
446
447 ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
448 if (ret)
449 return ret;
450 }
451
452 /*
453 * We don't want to assert reset and risk undoing pin muxing for the
454 * early boot serial console, but let's make sure the reset line is
455 * deasserted in case someone runs a really minimal bootloader.
456 */
457 ret = reset_control_deassert(rst);
458 if (ret)
459 return dev_err_probe(dev, ret, "could not deassert reset\n");
460
461 if (info->starfive_iopad_sel_func) {
> 462 ret = info->starfive_iopad_sel_func(pdev, pctl, value);
463 if (ret)
464 return ret;
465 }
466
467 starfive_pinctrl_desc = devm_kzalloc(&pdev->dev,
468 sizeof(*starfive_pinctrl_desc),
469 GFP_KERNEL);
470 if (!starfive_pinctrl_desc)
471 return -ENOMEM;
472
473 raw_spin_lock_init(&pctl->lock);
474
475 starfive_pinctrl_desc->name = dev_name(&pdev->dev);
476 starfive_pinctrl_desc->pins = info->pins;
477 starfive_pinctrl_desc->npins = info->npins;
478 starfive_pinctrl_desc->pctlops = &starfive_pctrl_ops;
479 starfive_pinctrl_desc->pmxops = &starfive_pmx_ops;
480 starfive_pinctrl_desc->confops = &starfive_pinconf_ops;
481 starfive_pinctrl_desc->owner = THIS_MODULE;
482
483 mutex_init(&pctl->mutex);
484
485 pctl->info = info;
486 pctl->dev = &pdev->dev;
487 platform_set_drvdata(pdev, pctl);
488 pctl->gc.parent = dev;
489 ret = devm_pinctrl_register_and_init(&pdev->dev,
490 starfive_pinctrl_desc, pctl,
491 &pctl->pctl_dev);
492 if (ret) {
493 dev_err(&pdev->dev,
494 "could not register starfive pinctrl driver\n");
495 return ret;
496 }
497
498 ret = pinctrl_enable(pctl->pctl_dev);
499 if (ret) {
500 dev_err(&pdev->dev,
501 "pin controller failed to start\n");
502 return ret;
503 }
504
505 if (info->starfive_gpio_register) {
506 ret = info->starfive_gpio_register(pdev, pctl);
507 if (ret) {
508 dev_err(&pdev->dev,
509 "starfive_gpio_register failed to register\n");
510 return ret;
511 }
512 }
513
514 return 0;
515 }
516 EXPORT_SYMBOL_GPL(starfive_pinctrl_probe);
517
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On 01/10/2022 12:52, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 03:49:14PM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <[email protected]>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by
>> StarFive Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <[email protected]>
>> Signed-off-by: Jianlong Huang <[email protected]>
>> Signed-off-by: Hal Feng <[email protected]>
>
> There's little point reviewing this dt since there's a load of issues
> that you can trivially find by running dtbs_check/dt_binding_check, but
Yep...
> this SoB change is wrong - if Emil wrote the patch, then Jianlong's SoB
> is either redundant or should be accompanied by a Co-developed-by tag.
Depends. Jianlong might have just rebased the patch.
>
> Ditto for patch 28/30 "RISC-V: Add StarFive JH7110 VisionFive2 board
> device tree".
>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
>> 1 file changed, 449 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..46f418d4198a
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>
>> +
>> + osc: osc {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + clk_rtc: clk_rtc {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac0_rmii_refin: gmac0_rmii_refin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <50000000>;
>
> I assume, given osc has it's frequency set in the board dts, that these
> are all oscillators on the SoC?
>
>> + };
>> +
>> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +
>> + gmac1_rmii_refin: gmac1_rmii_refin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <50000000>;
>> + };
>> +
>> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +
>> + i2stx_bclk_ext: i2stx_bclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <12288000>;
>> + };
>> +
>> + i2stx_lrck_ext: i2stx_lrck_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <192000>;
>> + };
>> +
>> + i2srx_bclk_ext: i2srx_bclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <12288000>;
>> + };
>> +
>> + i2srx_lrck_ext: i2srx_lrck_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <192000>;
>> + };
>> +
>> + tdm_ext: tdm_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <49152000>;
>> + };
>> +
>> + mclk_ext: mclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <49152000>;
>> + };
>
>> + syscrg: syscrg@13020000 {
>
> The generic node name for syscons is just "syscon" afaik.
Yes.
>
>> + compatible = "syscon", "simple-mfd";
And this is not allowed. Needs specific compatible.
>> + reg = <0x0 0x13020000 0x0 0x10000>;
>> +
>
>> + aoncrg: aoncrg@17000000 {
>
> Again, syscon as the node name?
Yes.
>
>> + compatible = "syscon", "simple-mfd";
And this is a NAK.
>> + reg = <0x0 0x17000000 0x0 0x10000>;
>> +
>> + gpio: gpio@13040000 {
>
> Someone else (Krzysztof maybe?) should comment, but is "pinctrl" not the
> genric node name for pinctrl nodes?
Yes, for pin controller nodes, this should be "pinctrl" and schema
requires it. The problem was that his driver did not use generic pinctrl
bindings, which is no-go on its own.
This could be a gpio controller (so "gpio" would be fine), although
compatible suggests otherwise.
Best regards,
Krzysztof
On 29/09/2022 16:33, Conor Dooley wrote:
> On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <[email protected]>
>>
>> This cache controller is also used on the StarFive JH7100 and JH7110
>> SoCs.
>
> Ditto this patch, hopefully [0] will have landed as 6.1 material
> before you get around to an actual v2.
>
> Thanks,
> Conor
>
> 0 - https://lore.kernel.org/linux-riscv/[email protected]/
Also, the l2 cache is being proprely named the ccache (composable cache)
as it is not necessarily an L2 cache.
--
Ben
On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <[email protected]> wrote:
> On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > From: Jianlong Huang <[email protected]>
> >
> > Add the SoC name to make it more clear. Also the next generation StarFive
> > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > No functional change.
> >
> > Signed-off-by: Jianlong Huang <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
> > arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
> > drivers/pinctrl/starfive/Kconfig | 2 +-
> > drivers/pinctrl/starfive/Makefile | 2 +-
> > .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} | 2 +-
> > .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} | 6 +++---
> > 6 files changed, 8 insertions(+), 8 deletions(-)
> > rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> >
>
> Reviewed-by: Rob Herring <[email protected]>
>
> Would be good to pull this out separately and apply for 6.1. It's kind
> of messy with cross tree dependencies.
OK I applied this for V6.1.
Yours,
Linus Walleij
On Fri, Sep 30, 2022 at 8:08 AM Hal Feng
<[email protected]> wrote:
> From: Jianlong Huang <[email protected]>
>
> Move the StarFive JH7100 pinctrl driver to a new subdirectory
> in preparation for adding more StarFive pinctrl drivers. No
> functional change.
>
> Signed-off-by: Jianlong Huang <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
I applied this patch for v6.1 so you don't have to reiterate it, it's clearly
just infrastructure that you'll need going forward.
Yours,
Linus Walleij
On Fri, Sep 30, 2022 at 9:45 AM Hal Feng
<[email protected]> wrote:
> From: Jianlong Huang <[email protected]>
>
> Add pinctrl driver for StarFive JH7110 SoC.
>
> Signed-off-by: Jianlong Huang <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
Since Emil submitted the first driver I would really appreciate his review
on this version.
Yours,
Linus Walleij
On Tue, Oct 4, 2022 at 10:59 AM Conor Dooley <[email protected]> wrote:
> On Tue, Oct 04, 2022 at 10:48:38AM +0200, Linus Walleij wrote:
> > On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <[email protected]> wrote:
> > > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > > From: Jianlong Huang <[email protected]>
> > > >
> > > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > > No functional change.
> > > >
> > > > Signed-off-by: Jianlong Huang <[email protected]>
> > > > Signed-off-by: Hal Feng <[email protected]>
> > > > ---
> > > > .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
> > > > arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
> > > > drivers/pinctrl/starfive/Kconfig | 2 +-
> > > > drivers/pinctrl/starfive/Makefile | 2 +-
> > > > .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} | 2 +-
> > > > .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} | 6 +++---
> > > > 6 files changed, 8 insertions(+), 8 deletions(-)
> > > > rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > > > rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > > >
> > >
> > > Reviewed-by: Rob Herring <[email protected]>
> > >
> > > Would be good to pull this out separately and apply for 6.1. It's kind
> > > of messy with cross tree dependencies.
> >
> > OK I applied this for V6.1.
>
> Will this need to be done immutably so it can be pulled into the riscv
> tree in case this gets applied as a late change for 6.1:
> https://lore.kernel.org/linux-riscv/[email protected]/
Always one finger on the fast-forward button have we? ;)
Rob's point was that I should apply this for v6.1 so that exactly
that kind of cross-dependencies and immutable branches could
be avoided for the v6.2 development cycle.
The merge window is already open, it's a bit late for completely
new stuff I think.
Yours,
Linus Walleij
On Tue, Oct 04, 2022 at 10:48:38AM +0200, Linus Walleij wrote:
> On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <[email protected]> wrote:
> > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > From: Jianlong Huang <[email protected]>
> > >
> > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > No functional change.
> > >
> > > Signed-off-by: Jianlong Huang <[email protected]>
> > > Signed-off-by: Hal Feng <[email protected]>
> > > ---
> > > .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
> > > arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
> > > drivers/pinctrl/starfive/Kconfig | 2 +-
> > > drivers/pinctrl/starfive/Makefile | 2 +-
> > > .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} | 2 +-
> > > .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} | 6 +++---
> > > 6 files changed, 8 insertions(+), 8 deletions(-)
> > > rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > > rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > >
> >
> > Reviewed-by: Rob Herring <[email protected]>
> >
> > Would be good to pull this out separately and apply for 6.1. It's kind
> > of messy with cross tree dependencies.
>
> OK I applied this for V6.1.
Will this need to be done immutably so it can be pulled into the riscv
tree in case this gets applied as a late change for 6.1:
https://lore.kernel.org/linux-riscv/[email protected]/
Thanks,
Conor.
On Tue, Oct 04, 2022 at 11:13:37AM +0200, Linus Walleij wrote:
> On Tue, Oct 4, 2022 at 10:59 AM Conor Dooley <[email protected]> wrote:
> > On Tue, Oct 04, 2022 at 10:48:38AM +0200, Linus Walleij wrote:
> > > On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <[email protected]> wrote:
> > > > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > > > From: Jianlong Huang <[email protected]>
> > > > >
> > > > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > > > No functional change.
> > > > >
> > > > > Signed-off-by: Jianlong Huang <[email protected]>
> > > > > Signed-off-by: Hal Feng <[email protected]>
> > > > > ---
> > > > > .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
> > > > > arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
> > > > > drivers/pinctrl/starfive/Kconfig | 2 +-
> > > > > drivers/pinctrl/starfive/Makefile | 2 +-
> > > > > .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} | 2 +-
> > > > > .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} | 6 +++---
> > > > > 6 files changed, 8 insertions(+), 8 deletions(-)
> > > > > rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > > > > rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > > > >
> > > >
> > > > Reviewed-by: Rob Herring <[email protected]>
> > > >
> > > > Would be good to pull this out separately and apply for 6.1. It's kind
> > > > of messy with cross tree dependencies.
> > >
> > > OK I applied this for V6.1.
> >
> > Will this need to be done immutably so it can be pulled into the riscv
> > tree in case this gets applied as a late change for 6.1:
> > https://lore.kernel.org/linux-riscv/[email protected]/
>
> Always one finger on the fast-forward button have we? ;)
Dunno what you mean by that mate, sorry!
I just saw the mail wanted to have the decency to reply to that fellow
& tell him to rebase after rc1 to avoid a conflict.
> Rob's point was that I should apply this for v6.1 so that exactly
> that kind of cross-dependencies and immutable branches could
> be avoided for the v6.2 development cycle.
>
> The merge window is already open, it's a bit late for completely
> new stuff I think.
History suggests otherwise, but I'd be lying if I said I disagreed.
On Tue, Oct 04, 2022 at 10:21:24AM +0100, Conor Dooley wrote:
> On Tue, Oct 04, 2022 at 11:13:37AM +0200, Linus Walleij wrote:
> > On Tue, Oct 4, 2022 at 10:59 AM Conor Dooley <[email protected]> wrote:
> > > On Tue, Oct 04, 2022 at 10:48:38AM +0200, Linus Walleij wrote:
> > > > On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <[email protected]> wrote:
> > > > > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > > > > From: Jianlong Huang <[email protected]>
> > > > > >
> > > > > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > > > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > > > > No functional change.
> > > > > >
> > > > > > Signed-off-by: Jianlong Huang <[email protected]>
> > > > > > Signed-off-by: Hal Feng <[email protected]>
> > > > > > ---
> > > > > > .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
> > > > > > arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
> > > > > > drivers/pinctrl/starfive/Kconfig | 2 +-
> > > > > > drivers/pinctrl/starfive/Makefile | 2 +-
> > > > > > .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} | 2 +-
> > > > > > .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} | 6 +++---
> > > > > > 6 files changed, 8 insertions(+), 8 deletions(-)
> > > > > > rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > > > > > rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > > > > >
> > > > >
> > > > > Reviewed-by: Rob Herring <[email protected]>
> > > > >
> > > > > Would be good to pull this out separately and apply for 6.1. It's kind
> > > > > of messy with cross tree dependencies.
> > > >
> > > > OK I applied this for V6.1.
> > >
> > > Will this need to be done immutably so it can be pulled into the riscv
> > > tree in case this gets applied as a late change for 6.1:
> > > https://lore.kernel.org/linux-riscv/[email protected]/
> >
> > Always one finger on the fast-forward button have we? ;)
>
> Dunno what you mean by that mate, sorry!
>
> I just saw the mail wanted to have the decency to reply to that fellow
s/wanted/want
> & tell him to rebase after rc1 to avoid a conflict.
>
> > Rob's point was that I should apply this for v6.1 so that exactly
> > that kind of cross-dependencies and immutable branches could
> > be avoided for the v6.2 development cycle.
> >
> > The merge window is already open, it's a bit late for completely
> > new stuff I think.
>
> History suggests otherwise, but I'd be lying if I said I disagreed.
On Thu, 29 Sept 2022 at 16:34, Hal Feng <[email protected]> wrote:
> This series adds basic support for the StarFive JH7110 RISC-V SoC to
> boot up and get a serial console. This series includes basic clock,
> reset, pinctrl and uart drivers, which are necessary for booting.
> It's should be noted that the reset and clock driver codes of JH7110
> are partly common with those of JH7100, so the common codes are
> factored out and can be reused by drivers of JH7110 and other more
> SoCs from StarFive.
>
> The JH7110 is the upgraded version of JH7100 and also the first official
> released version of JH71XX series SoCs from StarFive Technology Ltd.
> The VisionFive 2 boards equipped with JH7110 SoCs are launched
> recently [1]. More information and support can visit RVspace wiki [2].
>
> This series is also available at
> https://github.com/hal-feng/linux/commits/visionfive2-minimal
>
> [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> [2] https://wiki.rvspace.org/
Hi Hal,
Firstly thanks for working on this! And sorry about the late reply. On
the next version could you please cc
[email protected] since it seems to handle the
mailing list a bit better.
I see you've changed the clock/reset and pinctrl quite a bit, so I'll
comment on that separately.
/Emil
> Emil Renner Berthing (17):
> dt-bindings: riscv: Add StarFive JH7110 bindings
> dt-bindings: timer: Add StarFive JH7110 clint
> dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
> soc: sifive: l2 cache: Convert to platform driver
> soc: sifive: l2 cache: Add StarFive JH71x0 support
> reset: starfive: jh7100: Use 32bit I/O on 32bit registers
> dt-bindings: reset: Add StarFive JH7110 reset definitions
> clk: starfive: Factor out common clock driver code
> dt-bindings: clock: Add StarFive JH7110 system clock definitions
> dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
> clk: starfive: Add StarFive JH7110 system clock driver
> dt-bindings: clock: Add StarFive JH7110 always-on definitions
> dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
> clk: starfive: Add StarFive JH7110 always-on clock driver
> RISC-V: Add initial StarFive JH7110 device tree
> RISC-V: Add StarFive JH7110 VisionFive2 board device tree
>
> Hal Feng (8):
> reset: starfive: jh7100: Use regmap APIs to operate registers
> reset: starfive: jh7100: Move necessary properties to device tree
> reset: starfive: Rename 'reset-starfive-jh7100.c' to
> 'reset-starfive.c'
> dt-bindings: reset: Add starfive,jh7110-reset bindings
> reset: starfive: Add StarFive JH7110 SoC support
> clk: starfive: Use regmap APIs to operate registers
> RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
> RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options
>
> Jianlong Huang (5):
> pinctrl: Create subdirectory for StarFive drivers
> pinctrl: starfive: Rename "pinctrl-starfive" to
> "pinctrl-starfive-jh7100"
> dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
> dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings
> pinctrl: starfive: Add StarFive JH7110 driver
>
> .../clock/starfive,jh7110-clkgen-aon.yaml | 62 ++
> .../clock/starfive,jh7110-clkgen-sys.yaml | 69 ++
> .../sifive,plic-1.0.0.yaml | 1 +
> .../pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
> .../pinctrl/starfive,jh7110-pinctrl.yaml | 202 ++++
> .../bindings/reset/starfive,jh7100-reset.yaml | 20 +
> .../bindings/reset/starfive,jh7110-reset.yaml | 54 +
> .../bindings/riscv/sifive-l2-cache.yaml | 4 +
> .../devicetree/bindings/riscv/starfive.yaml | 3 +
> .../bindings/timer/sifive,clint.yaml | 1 +
> MAINTAINERS | 27 +-
> arch/riscv/Kconfig.socs | 28 +-
> arch/riscv/boot/dts/starfive/Makefile | 3 +-
> .../dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
> arch/riscv/boot/dts/starfive/jh7100.dtsi | 3 +
> .../jh7110-starfive-visionfive-v2.dts | 91 ++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++
> arch/riscv/configs/defconfig | 1 +
> drivers/clk/starfive/Kconfig | 29 +-
> drivers/clk/starfive/Makefile | 6 +-
> .../clk/starfive/clk-starfive-jh7100-audio.c | 138 +--
> drivers/clk/starfive/clk-starfive-jh7100.c | 836 +++++-----------
> drivers/clk/starfive/clk-starfive-jh7100.h | 112 ---
> .../clk/starfive/clk-starfive-jh7110-aon.c | 161 +++
> .../clk/starfive/clk-starfive-jh7110-sys.c | 648 ++++++++++++
> drivers/clk/starfive/clk-starfive.c | 349 +++++++
> drivers/clk/starfive/clk-starfive.h | 112 +++
> drivers/pinctrl/Kconfig | 18 +-
> drivers/pinctrl/Makefile | 2 +-
> drivers/pinctrl/starfive/Kconfig | 37 +
> drivers/pinctrl/starfive/Makefile | 8 +
> drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 718 ++++++++++++++
> drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 925 +++++++++++++++++
> .../pinctrl-starfive-jh7100.c} | 10 +-
> drivers/pinctrl/starfive/pinctrl-starfive.c | 539 ++++++++++
> drivers/pinctrl/starfive/pinctrl-starfive.h | 131 +++
> drivers/reset/Kconfig | 7 +-
> drivers/reset/Makefile | 2 +-
> drivers/reset/reset-starfive-jh7100.c | 173 ----
> drivers/reset/reset-starfive.c | 218 ++++
> drivers/soc/Makefile | 2 +-
> drivers/soc/sifive/Kconfig | 2 +-
> drivers/soc/sifive/sifive_l2_cache.c | 86 +-
> .../dt-bindings/clock/starfive-jh7110-aon.h | 26 +
> .../dt-bindings/clock/starfive-jh7110-sys.h | 215 ++++
> ...l-starfive.h => pinctrl-starfive-jh7100.h} | 6 +-
> .../pinctrl/pinctrl-starfive-jh7110.h | 931 ++++++++++++++++++
> include/dt-bindings/reset/starfive-jh7110.h | 154 +++
> 48 files changed, 6604 insertions(+), 1019 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
> create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
> create mode 100644 drivers/clk/starfive/clk-starfive.c
> create mode 100644 drivers/clk/starfive/clk-starfive.h
> create mode 100644 drivers/pinctrl/starfive/Kconfig
> create mode 100644 drivers/pinctrl/starfive/Makefile
> create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
> create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> rename drivers/pinctrl/{pinctrl-starfive.c => starfive/pinctrl-starfive-jh7100.c} (99%)
> create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
> create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h
> delete mode 100644 drivers/reset/reset-starfive-jh7100.c
> create mode 100644 drivers/reset/reset-starfive.c
> create mode 100644 include/dt-bindings/clock/starfive-jh7110-aon.h
> create mode 100644 include/dt-bindings/clock/starfive-jh7110-sys.h
> rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
> create mode 100644 include/dt-bindings/reset/starfive-jh7110.h
>
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Fri, 30 Sept 2022 at 23:50, Stephen Boyd <[email protected]> wrote:
>
> Quoting Hal Feng (2022-09-29 10:56:02)
> > Clock registers address region is shared with reset controller
> > on the new StarFive JH7110 SoC. Change to use regmap framework
> > to allow base address sharing and preparation for JH7110 clock
> > support.
>
> Do the reset and clk parts share actual registers, where we would need
> to lock between rmw? Or is regmap just nice to have because it wraps up
> the register APIs with some extra features?
No, the registers aren't shared, but on the JH7100 clock and reset had
separate ranges, but on the JH7110 there is just one memory range for
each "CRG", clock and reset generator I presume, and the reset
registers are placed after the clock registers in the same range.
> >
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> [...]
> > diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
> > index 014e36f17595..410aa6e06842 100644
> > --- a/drivers/clk/starfive/clk-starfive-jh7100.c
> > +++ b/drivers/clk/starfive/clk-starfive-jh7100.c
> > @@ -10,6 +10,7 @@
> > #include <linux/clk-provider.h>
> > #include <linux/device.h>
> > #include <linux/init.h>
> > +#include <linux/mfd/syscon.h>
> > #include <linux/mod_devicetable.h>
> > #include <linux/platform_device.h>
> >
> > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> > if (!priv)
> > return -ENOMEM;
> >
> > - spin_lock_init(&priv->rmw_lock);
> > priv->dev = &pdev->dev;
> > - priv->base = devm_platform_ioremap_resource(pdev, 0);
> > - if (IS_ERR(priv->base))
> > - return PTR_ERR(priv->base);
> > + priv->regmap = device_node_to_regmap(priv->dev->of_node);
>
> This is sad. Why do we need to make a syscon? Can we instead use the
> auxiliary bus to make a reset device that either gets a regmap made here
> in this driver or uses a void __iomem * mapped with ioremap
> (priv->base)?
In my original code the clock driver just registers the resets too
similar to other combined clock and reset drivers. I wonder what you
think about that approach:
https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
and
https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
> > + if (IS_ERR(priv->regmap)) {
> > + dev_err(priv->dev, "failed to get regmap (error %ld)\n",
> > + PTR_ERR(priv->regmap));
> > + return PTR_ERR(priv->regmap);
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Tue, 4 Oct 2022 at 10:57, Linus Walleij <[email protected]> wrote:
>
> On Fri, Sep 30, 2022 at 9:45 AM Hal Feng
> <[email protected]> wrote:
>
> > From: Jianlong Huang <[email protected]>
> >
> > Add pinctrl driver for StarFive JH7110 SoC.
> >
> > Signed-off-by: Jianlong Huang <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
>
> Since Emil submitted the first driver I would really appreciate his review
> on this version.
I tried really hard to come up with a good way to share code between
the JH7100 and JH7110 drivers, but so many details different on the
JH7110 that it's probably best to just have a separate driver, so that
part is fine.
As mentioned elsewhere this driver certainly shouldn't be accepted
without following the generic pinctrl and pinmux bindings. You can see
the driver I wrote here:
https://github.com/esmil/linux/commit/c2633315385fef1a25aa3711facef07d915820e1
It is certainly not perfect and far from complete, but at least it
does follow the generic bindings. Feel free to copy all or parts of
that.
/Emil
>
> Yours,
> Linus Walleij
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Fri, 30 Sept 2022 at 22:51, Rob Herring <[email protected]> wrote:
>
> On Thu, Sep 29, 2022 at 10:32:04PM +0800, Hal Feng wrote:
> > Store the necessary properties in device tree instead of .c file,
> > in order to apply this reset driver to other StarFive SoCs.
> >
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > .../bindings/reset/starfive,jh7100-reset.yaml | 20 ++++++++
> > arch/riscv/boot/dts/starfive/jh7100.dtsi | 3 ++
> > drivers/reset/reset-starfive-jh7100.c | 50 +++++++++++++------
> > 3 files changed, 57 insertions(+), 16 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> > index 300359a5e14b..3eff3f72a1ed 100644
> > --- a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> > +++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> > @@ -20,19 +20,39 @@ properties:
> > "#reset-cells":
> > const: 1
> >
> > + starfive,assert-offset:
> > + description: Offset of the first ASSERT register
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + starfive,status-offset:
> > + description: Offset of the first STATUS register
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + starfive,nr-resets:
> > + description: Number of reset signals
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > required:
> > - compatible
> > - reg
> > - "#reset-cells"
> > + - starfive,assert-offset
> > + - starfive,status-offset
> > + - starfive,nr-resets
>
> Adding required properties is a red flag. You can't add required
> properties to an existing binding. That breaks the ABI unless the OS
> deals with the properties being absent. If the OS has to do that, then
> why add them in the first place? All this should be implied by the
> compatible string.
Indeed. I really don't understand why this is even necessary. As
mentioned in my reply to the clock driver my original code just had a
combined driver for the whole CRG (clock and reset generator I
presume), and then you just need a simple node like this:
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
clocks = <&osc>, <&gmac1_rmii_refin>,
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
<&tdm_ext>, <&mclk_ext>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
"tdm_ext", "mclk_ext";
#clock-cells = <1>;
#reset-cells = <1>;
};
/Emil
On Thu, 29 Sept 2022 at 19:59, Ben Dooks <[email protected]> wrote:
>
> On 29/09/2022 15:32, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > This converts the driver to use the builtin_platform_driver_probe macro
> > to initialize the driver. This macro ends up calling device_initcall as
> > was used previously, but also allocates a platform device which gives us
> > access to much nicer APIs such as platform_ioremap_resource,
> > platform_get_irq and dev_err_probe.
>
> This is useful, but also there are other changes currently being sorted
> out by Zong Li (cc'd into this message) which have already been reviewed
> and are hopefully queued for the next kernel release.
>
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
I'm ok with something like this being merged, but please note that if
we ever want to support the JH7100 which uses registers in this
peripheral to flush the cache for its non-coherent DMAs then this
driver needs to be loaded before other peripherals or we will trigger
the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
can do that when it's a platform driver. See this patch for an
alternative to support the JH71x0s:
https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
/Emil
> > drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
> > 1 file changed, 40 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> > index 59640a1d0b28..010d612f7420 100644
> > --- a/drivers/soc/sifive/sifive_l2_cache.c
> > +++ b/drivers/soc/sifive/sifive_l2_cache.c
> > @@ -7,9 +7,9 @@
> > */
> > #include <linux/debugfs.h>
> > #include <linux/interrupt.h>
> > -#include <linux/of_irq.h>
> > -#include <linux/of_address.h>
> > -#include <linux/device.h>
> > +#include <linux/io.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/platform_device.h>
> > #include <asm/cacheinfo.h>
> > #include <soc/sifive/sifive_l2_cache.h>
> >
> > @@ -96,12 +96,6 @@ static void l2_config_read(void)
> > pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> > }
> >
> > -static const struct of_device_id sifive_l2_ids[] = {
> > - { .compatible = "sifive,fu540-c000-ccache" },
> > - { .compatible = "sifive,fu740-c000-ccache" },
> > - { /* end of table */ },
> > -};
> > -
> > static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
> >
> > int register_sifive_l2_error_notifier(struct notifier_block *nb)
> > @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
> > return IRQ_HANDLED;
> > }
> >
> > -static int __init sifive_l2_init(void)
> > +static int __init sifive_l2_probe(struct platform_device *pdev)
> > {
> > - struct device_node *np;
> > - struct resource res;
> > - int i, rc, intr_num;
> > -
> > - np = of_find_matching_node(NULL, sifive_l2_ids);
> > - if (!np)
> > - return -ENODEV;
> > -
> > - if (of_address_to_resource(np, 0, &res))
> > - return -ENODEV;
> > -
> > - l2_base = ioremap(res.start, resource_size(&res));
> > - if (!l2_base)
> > - return -ENOMEM;
> > -
> > - intr_num = of_property_count_u32_elems(np, "interrupts");
> > - if (!intr_num) {
> > - pr_err("L2CACHE: no interrupts property\n");
> > - return -ENODEV;
> > - }
> > -
> > - for (i = 0; i < intr_num; i++) {
> > - g_irq[i] = irq_of_parse_and_map(np, i);
> > - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> > - if (rc) {
> > - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> > - return rc;
> > - }
> > + struct device *dev = &pdev->dev;
> > + int nirqs;
> > + int ret;
> > + int i;
> > +
> > + l2_base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(l2_base))
> > + return PTR_ERR(l2_base);
> > +
> > + nirqs = platform_irq_count(pdev);
> > + if (nirqs <= 0)
> > + return dev_err_probe(dev, -ENODEV, "no interrupts\n");
>
> I wonder if zero irqs is an actual issue here?
>
> > + for (i = 0; i < nirqs; i++) {
> > + g_irq[i] = platform_get_irq(pdev, i);
>
> I wonder if we need to keep g_irq[] around now? Is it going to be useful
> in the future?
>
> > + if (g_irq[i] < 0)
> > + return g_irq[i];
> > +
> > + ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
> > }
> >
> > l2_config_read();
> > @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
> > #endif
> > return 0;
> > }
> > -device_initcall(sifive_l2_init);
> > +
> > +static const struct of_device_id sifive_l2_match[] = {
> > + { .compatible = "sifive,fu540-c000-ccache" },
> > + { .compatible = "sifive,fu740-c000-ccache" },
> > + { /* sentinel */ }
> > +};
> > +
> > +static struct platform_driver sifive_l2_driver = {
> > + .driver = {
> > + .name = "sifive_l2_cache",
> > + .of_match_table = sifive_l2_match,
> > + .suppress_bind_attrs = true,
> > + },
> > +};
> > +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, 5 Oct 2022 at 15:48, Ben Dooks <[email protected]> wrote:
>
> On 05/10/2022 14:44, Emil Renner Berthing wrote:
> > On Thu, 29 Sept 2022 at 19:59, Ben Dooks <[email protected]> wrote:
> >>
> >> On 29/09/2022 15:32, Hal Feng wrote:
> >>> From: Emil Renner Berthing <[email protected]>
> >>>
> >>> This converts the driver to use the builtin_platform_driver_probe macro
> >>> to initialize the driver. This macro ends up calling device_initcall as
> >>> was used previously, but also allocates a platform device which gives us
> >>> access to much nicer APIs such as platform_ioremap_resource,
> >>> platform_get_irq and dev_err_probe.
> >>
> >> This is useful, but also there are other changes currently being sorted
> >> out by Zong Li (cc'd into this message) which have already been reviewed
> >> and are hopefully queued for the next kernel release.
> >>
> >>> Signed-off-by: Emil Renner Berthing <[email protected]>
> >>> Signed-off-by: Hal Feng <[email protected]>
> >
> > I'm ok with something like this being merged, but please note that if
> > we ever want to support the JH7100 which uses registers in this
> > peripheral to flush the cache for its non-coherent DMAs then this
> > driver needs to be loaded before other peripherals or we will trigger
> > the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
> > can do that when it's a platform driver. See this patch for an
> > alternative to support the JH71x0s:
> > https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
> >
> > /Emil
>
> Are you replying to your own patch that does the conversion to
> platform driver and then saying that it could actually cause
> issues?
Yes, I can see it seems odd, but this patch lived for a while in the
kernel repo for the JH7100 until I rebased on 6.0-rc1 and realized the
above.
Hal Feng must have based his patches on a version of the code before
that when preparing this series.
> I'm all for dropping this for the moment and keeping the old
> early init for the ccache.
Cool.
/Emil
> >>> drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
> >>> 1 file changed, 40 insertions(+), 39 deletions(-)
> >>>
> >>> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> >>> index 59640a1d0b28..010d612f7420 100644
> >>> --- a/drivers/soc/sifive/sifive_l2_cache.c
> >>> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> >>> @@ -7,9 +7,9 @@
> >>> */
> >>> #include <linux/debugfs.h>
> >>> #include <linux/interrupt.h>
> >>> -#include <linux/of_irq.h>
> >>> -#include <linux/of_address.h>
> >>> -#include <linux/device.h>
> >>> +#include <linux/io.h>
> >>> +#include <linux/mod_devicetable.h>
> >>> +#include <linux/platform_device.h>
> >>> #include <asm/cacheinfo.h>
> >>> #include <soc/sifive/sifive_l2_cache.h>
> >>>
> >>> @@ -96,12 +96,6 @@ static void l2_config_read(void)
> >>> pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> >>> }
> >>>
> >>> -static const struct of_device_id sifive_l2_ids[] = {
> >>> - { .compatible = "sifive,fu540-c000-ccache" },
> >>> - { .compatible = "sifive,fu740-c000-ccache" },
> >>> - { /* end of table */ },
> >>> -};
> >>> -
> >>> static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
> >>>
> >>> int register_sifive_l2_error_notifier(struct notifier_block *nb)
> >>> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
> >>> return IRQ_HANDLED;
> >>> }
> >>>
> >>> -static int __init sifive_l2_init(void)
> >>> +static int __init sifive_l2_probe(struct platform_device *pdev)
> >>> {
> >>> - struct device_node *np;
> >>> - struct resource res;
> >>> - int i, rc, intr_num;
> >>> -
> >>> - np = of_find_matching_node(NULL, sifive_l2_ids);
> >>> - if (!np)
> >>> - return -ENODEV;
> >>> -
> >>> - if (of_address_to_resource(np, 0, &res))
> >>> - return -ENODEV;
> >>> -
> >>> - l2_base = ioremap(res.start, resource_size(&res));
> >>> - if (!l2_base)
> >>> - return -ENOMEM;
> >>> -
> >>> - intr_num = of_property_count_u32_elems(np, "interrupts");
> >>> - if (!intr_num) {
> >>> - pr_err("L2CACHE: no interrupts property\n");
> >>> - return -ENODEV;
> >>> - }
> >>> -
> >>> - for (i = 0; i < intr_num; i++) {
> >>> - g_irq[i] = irq_of_parse_and_map(np, i);
> >>> - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> >>> - if (rc) {
> >>> - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> >>> - return rc;
> >>> - }
> >>> + struct device *dev = &pdev->dev;
> >>> + int nirqs;
> >>> + int ret;
> >>> + int i;
> >>> +
> >>> + l2_base = devm_platform_ioremap_resource(pdev, 0);
> >>> + if (IS_ERR(l2_base))
> >>> + return PTR_ERR(l2_base);
> >>> +
> >>> + nirqs = platform_irq_count(pdev);
> >>> + if (nirqs <= 0)
> >>> + return dev_err_probe(dev, -ENODEV, "no interrupts\n");
> >>
> >> I wonder if zero irqs is an actual issue here?
> >>
> >>> + for (i = 0; i < nirqs; i++) {
> >>> + g_irq[i] = platform_get_irq(pdev, i);
> >>
> >> I wonder if we need to keep g_irq[] around now? Is it going to be useful
> >> in the future?
> >>
> >>> + if (g_irq[i] < 0)
> >>> + return g_irq[i];
> >>> +
> >>> + ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> >>> + if (ret)
> >>> + return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
> >>> }
> >>>
> >>> l2_config_read();
> >>> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
> >>> #endif
> >>> return 0;
> >>> }
> >>> -device_initcall(sifive_l2_init);
> >>> +
> >>> +static const struct of_device_id sifive_l2_match[] = {
> >>> + { .compatible = "sifive,fu540-c000-ccache" },
> >>> + { .compatible = "sifive,fu740-c000-ccache" },
> >>> + { /* sentinel */ }
> >>> +};
> >>> +
> >>> +static struct platform_driver sifive_l2_driver = {
> >>> + .driver = {
> >>> + .name = "sifive_l2_cache",
> >>> + .of_match_table = sifive_l2_match,
> >>> + .suppress_bind_attrs = true,
> >>> + },
> >>> +};
> >>> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> [email protected]
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> > _______________________________________________
> > linux-riscv mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
>
On Wed, Oct 05, 2022 at 03:55:17PM +0200, Emil Renner Berthing wrote:
> On Wed, 5 Oct 2022 at 15:48, Ben Dooks <[email protected]> wrote:
> >
> > On 05/10/2022 14:44, Emil Renner Berthing wrote:
> > > On Thu, 29 Sept 2022 at 19:59, Ben Dooks <[email protected]> wrote:
> > >>
> > >> On 29/09/2022 15:32, Hal Feng wrote:
> > >>> From: Emil Renner Berthing <[email protected]>
> > >>>
> > >>> This converts the driver to use the builtin_platform_driver_probe macro
> > >>> to initialize the driver. This macro ends up calling device_initcall as
> > >>> was used previously, but also allocates a platform device which gives us
> > >>> access to much nicer APIs such as platform_ioremap_resource,
> > >>> platform_get_irq and dev_err_probe.
> > >>
> > >> This is useful, but also there are other changes currently being sorted
> > >> out by Zong Li (cc'd into this message) which have already been reviewed
> > >> and are hopefully queued for the next kernel release.
> > >>
> > >>> Signed-off-by: Emil Renner Berthing <[email protected]>
> > >>> Signed-off-by: Hal Feng <[email protected]>
> > >
> > > I'm ok with something like this being merged, but please note that if
> > > we ever want to support the JH7100 which uses registers in this
> > > peripheral to flush the cache for its non-coherent DMAs then this
> > > driver needs to be loaded before other peripherals or we will trigger
> > > the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
> > > can do that when it's a platform driver. See this patch for an
> > > alternative to support the JH71x0s:
> > > https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
> > >
> > > /Emil
> >
> > Are you replying to your own patch that does the conversion to
> > platform driver and then saying that it could actually cause
> > issues?
>
> Yes, I can see it seems odd, but this patch lived for a while in the
> kernel repo for the JH7100 until I rebased on 6.0-rc1 and realized the
> above.
> Hal Feng must have based his patches on a version of the code before
> that when preparing this series.
>
> > I'm all for dropping this for the moment and keeping the old
> > early init for the ccache.
>
> Cool.
FWIW, if converting to a platform driver will inhibit using the driver
for doing non-coherent stuff I would like to NAK the patch :)
>
> /Emil
>
> > >>> drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
> > >>> 1 file changed, 40 insertions(+), 39 deletions(-)
> > >>>
> > >>> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> > >>> index 59640a1d0b28..010d612f7420 100644
> > >>> --- a/drivers/soc/sifive/sifive_l2_cache.c
> > >>> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> > >>> @@ -7,9 +7,9 @@
> > >>> */
> > >>> #include <linux/debugfs.h>
> > >>> #include <linux/interrupt.h>
> > >>> -#include <linux/of_irq.h>
> > >>> -#include <linux/of_address.h>
> > >>> -#include <linux/device.h>
> > >>> +#include <linux/io.h>
> > >>> +#include <linux/mod_devicetable.h>
> > >>> +#include <linux/platform_device.h>
> > >>> #include <asm/cacheinfo.h>
> > >>> #include <soc/sifive/sifive_l2_cache.h>
> > >>>
> > >>> @@ -96,12 +96,6 @@ static void l2_config_read(void)
> > >>> pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> > >>> }
> > >>>
> > >>> -static const struct of_device_id sifive_l2_ids[] = {
> > >>> - { .compatible = "sifive,fu540-c000-ccache" },
> > >>> - { .compatible = "sifive,fu740-c000-ccache" },
> > >>> - { /* end of table */ },
> > >>> -};
> > >>> -
> > >>> static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
> > >>>
> > >>> int register_sifive_l2_error_notifier(struct notifier_block *nb)
> > >>> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
> > >>> return IRQ_HANDLED;
> > >>> }
> > >>>
> > >>> -static int __init sifive_l2_init(void)
> > >>> +static int __init sifive_l2_probe(struct platform_device *pdev)
> > >>> {
> > >>> - struct device_node *np;
> > >>> - struct resource res;
> > >>> - int i, rc, intr_num;
> > >>> -
> > >>> - np = of_find_matching_node(NULL, sifive_l2_ids);
> > >>> - if (!np)
> > >>> - return -ENODEV;
> > >>> -
> > >>> - if (of_address_to_resource(np, 0, &res))
> > >>> - return -ENODEV;
> > >>> -
> > >>> - l2_base = ioremap(res.start, resource_size(&res));
> > >>> - if (!l2_base)
> > >>> - return -ENOMEM;
> > >>> -
> > >>> - intr_num = of_property_count_u32_elems(np, "interrupts");
> > >>> - if (!intr_num) {
> > >>> - pr_err("L2CACHE: no interrupts property\n");
> > >>> - return -ENODEV;
> > >>> - }
> > >>> -
> > >>> - for (i = 0; i < intr_num; i++) {
> > >>> - g_irq[i] = irq_of_parse_and_map(np, i);
> > >>> - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> > >>> - if (rc) {
> > >>> - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> > >>> - return rc;
> > >>> - }
> > >>> + struct device *dev = &pdev->dev;
> > >>> + int nirqs;
> > >>> + int ret;
> > >>> + int i;
> > >>> +
> > >>> + l2_base = devm_platform_ioremap_resource(pdev, 0);
> > >>> + if (IS_ERR(l2_base))
> > >>> + return PTR_ERR(l2_base);
> > >>> +
> > >>> + nirqs = platform_irq_count(pdev);
> > >>> + if (nirqs <= 0)
> > >>> + return dev_err_probe(dev, -ENODEV, "no interrupts\n");
> > >>
> > >> I wonder if zero irqs is an actual issue here?
> > >>
> > >>> + for (i = 0; i < nirqs; i++) {
> > >>> + g_irq[i] = platform_get_irq(pdev, i);
> > >>
> > >> I wonder if we need to keep g_irq[] around now? Is it going to be useful
> > >> in the future?
> > >>
> > >>> + if (g_irq[i] < 0)
> > >>> + return g_irq[i];
> > >>> +
> > >>> + ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> > >>> + if (ret)
> > >>> + return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
> > >>> }
> > >>>
> > >>> l2_config_read();
> > >>> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
> > >>> #endif
> > >>> return 0;
> > >>> }
> > >>> -device_initcall(sifive_l2_init);
> > >>> +
> > >>> +static const struct of_device_id sifive_l2_match[] = {
> > >>> + { .compatible = "sifive,fu540-c000-ccache" },
> > >>> + { .compatible = "sifive,fu740-c000-ccache" },
> > >>> + { /* sentinel */ }
> > >>> +};
> > >>> +
> > >>> +static struct platform_driver sifive_l2_driver = {
> > >>> + .driver = {
> > >>> + .name = "sifive_l2_cache",
> > >>> + .of_match_table = sifive_l2_match,
> > >>> + .suppress_bind_attrs = true,
> > >>> + },
> > >>> +};
> > >>> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
> > >>
> > >>
> > >> _______________________________________________
> > >> linux-riscv mailing list
> > >> [email protected]
> > >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > [email protected]
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> > >
> >
> > --
> > Ben Dooks http://www.codethink.co.uk/
> > Senior Engineer Codethink - Providing Genius
> >
> > https://www.codethink.co.uk/privacy.html
> >
On 05/10/2022 14:44, Emil Renner Berthing wrote:
> On Thu, 29 Sept 2022 at 19:59, Ben Dooks <[email protected]> wrote:
>>
>> On 29/09/2022 15:32, Hal Feng wrote:
>>> From: Emil Renner Berthing <[email protected]>
>>>
>>> This converts the driver to use the builtin_platform_driver_probe macro
>>> to initialize the driver. This macro ends up calling device_initcall as
>>> was used previously, but also allocates a platform device which gives us
>>> access to much nicer APIs such as platform_ioremap_resource,
>>> platform_get_irq and dev_err_probe.
>>
>> This is useful, but also there are other changes currently being sorted
>> out by Zong Li (cc'd into this message) which have already been reviewed
>> and are hopefully queued for the next kernel release.
>>
>>> Signed-off-by: Emil Renner Berthing <[email protected]>
>>> Signed-off-by: Hal Feng <[email protected]>
>
> I'm ok with something like this being merged, but please note that if
> we ever want to support the JH7100 which uses registers in this
> peripheral to flush the cache for its non-coherent DMAs then this
> driver needs to be loaded before other peripherals or we will trigger
> the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
> can do that when it's a platform driver. See this patch for an
> alternative to support the JH71x0s:
> https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
>
> /Emil
Are you replying to your own patch that does the conversion to
platform driver and then saying that it could actually cause
issues?
I'm all for dropping this for the moment and keeping the old
early init for the ccache.
>>> drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
>>> 1 file changed, 40 insertions(+), 39 deletions(-)
>>>
>>> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
>>> index 59640a1d0b28..010d612f7420 100644
>>> --- a/drivers/soc/sifive/sifive_l2_cache.c
>>> +++ b/drivers/soc/sifive/sifive_l2_cache.c
>>> @@ -7,9 +7,9 @@
>>> */
>>> #include <linux/debugfs.h>
>>> #include <linux/interrupt.h>
>>> -#include <linux/of_irq.h>
>>> -#include <linux/of_address.h>
>>> -#include <linux/device.h>
>>> +#include <linux/io.h>
>>> +#include <linux/mod_devicetable.h>
>>> +#include <linux/platform_device.h>
>>> #include <asm/cacheinfo.h>
>>> #include <soc/sifive/sifive_l2_cache.h>
>>>
>>> @@ -96,12 +96,6 @@ static void l2_config_read(void)
>>> pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
>>> }
>>>
>>> -static const struct of_device_id sifive_l2_ids[] = {
>>> - { .compatible = "sifive,fu540-c000-ccache" },
>>> - { .compatible = "sifive,fu740-c000-ccache" },
>>> - { /* end of table */ },
>>> -};
>>> -
>>> static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
>>>
>>> int register_sifive_l2_error_notifier(struct notifier_block *nb)
>>> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
>>> return IRQ_HANDLED;
>>> }
>>>
>>> -static int __init sifive_l2_init(void)
>>> +static int __init sifive_l2_probe(struct platform_device *pdev)
>>> {
>>> - struct device_node *np;
>>> - struct resource res;
>>> - int i, rc, intr_num;
>>> -
>>> - np = of_find_matching_node(NULL, sifive_l2_ids);
>>> - if (!np)
>>> - return -ENODEV;
>>> -
>>> - if (of_address_to_resource(np, 0, &res))
>>> - return -ENODEV;
>>> -
>>> - l2_base = ioremap(res.start, resource_size(&res));
>>> - if (!l2_base)
>>> - return -ENOMEM;
>>> -
>>> - intr_num = of_property_count_u32_elems(np, "interrupts");
>>> - if (!intr_num) {
>>> - pr_err("L2CACHE: no interrupts property\n");
>>> - return -ENODEV;
>>> - }
>>> -
>>> - for (i = 0; i < intr_num; i++) {
>>> - g_irq[i] = irq_of_parse_and_map(np, i);
>>> - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
>>> - if (rc) {
>>> - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
>>> - return rc;
>>> - }
>>> + struct device *dev = &pdev->dev;
>>> + int nirqs;
>>> + int ret;
>>> + int i;
>>> +
>>> + l2_base = devm_platform_ioremap_resource(pdev, 0);
>>> + if (IS_ERR(l2_base))
>>> + return PTR_ERR(l2_base);
>>> +
>>> + nirqs = platform_irq_count(pdev);
>>> + if (nirqs <= 0)
>>> + return dev_err_probe(dev, -ENODEV, "no interrupts\n");
>>
>> I wonder if zero irqs is an actual issue here?
>>
>>> + for (i = 0; i < nirqs; i++) {
>>> + g_irq[i] = platform_get_irq(pdev, i);
>>
>> I wonder if we need to keep g_irq[] around now? Is it going to be useful
>> in the future?
>>
>>> + if (g_irq[i] < 0)
>>> + return g_irq[i];
>>> +
>>> + ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
>>> + if (ret)
>>> + return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
>>> }
>>>
>>> l2_config_read();
>>> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
>>> #endif
>>> return 0;
>>> }
>>> -device_initcall(sifive_l2_init);
>>> +
>>> +static const struct of_device_id sifive_l2_match[] = {
>>> + { .compatible = "sifive,fu540-c000-ccache" },
>>> + { .compatible = "sifive,fu740-c000-ccache" },
>>> + { /* sentinel */ }
>>> +};
>>> +
>>> +static struct platform_driver sifive_l2_driver = {
>>> + .driver = {
>>> + .name = "sifive_l2_cache",
>>> + .of_match_table = sifive_l2_match,
>>> + .suppress_bind_attrs = true,
>>> + },
>>> +};
>>> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
Hi Linus,
On Tue, Oct 4, 2022 at 10:50 AM Linus Walleij <[email protected]> wrote:
> On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <[email protected]> wrote:
> > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > From: Jianlong Huang <[email protected]>
> > >
> > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > No functional change.
> > >
> > > Signed-off-by: Jianlong Huang <[email protected]>
> > > Signed-off-by: Hal Feng <[email protected]>
> > > ---
> > > .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml | 2 +-
> > > arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 2 +-
> > > drivers/pinctrl/starfive/Kconfig | 2 +-
> > > drivers/pinctrl/starfive/Makefile | 2 +-
> > > .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} | 2 +-
> > > .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} | 6 +++---
> > > 6 files changed, 8 insertions(+), 8 deletions(-)
> > > rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > > rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > >
> >
> > Reviewed-by: Rob Herring <[email protected]>
> >
> > Would be good to pull this out separately and apply for 6.1. It's kind
> > of messy with cross tree dependencies.
>
> OK I applied this for V6.1.
Isn't the name of the DT bindings header file part of the DT bindings,
i.e. it cannot be changed afterwards?
As of v5.17, it is in active use by
arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, 5 Oct 2022 15:05:45 +0200, Emil Renner Berthing wrote:
> On Thu, 29 Sept 2022 at 16:34, Hal Feng <[email protected]> wrote:
> > This series adds basic support for the StarFive JH7110 RISC-V SoC to
> > boot up and get a serial console. This series includes basic clock,
> > reset, pinctrl and uart drivers, which are necessary for booting.
> > It's should be noted that the reset and clock driver codes of JH7110
> > are partly common with those of JH7100, so the common codes are
> > factored out and can be reused by drivers of JH7110 and other more
> > SoCs from StarFive.
> >
> > The JH7110 is the upgraded version of JH7100 and also the first official
> > released version of JH71XX series SoCs from StarFive Technology Ltd.
> > The VisionFive 2 boards equipped with JH7110 SoCs are launched
> > recently [1]. More information and support can visit RVspace wiki [2].
> >
> > This series is also available at
> > https://github.com/hal-feng/linux/commits/visionfive2-minimal
> >
> > [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> > [2] https://wiki.rvspace.org/
>
> Hi Hal,
>
> Firstly thanks for working on this! And sorry about the late reply. On
> the next version could you please cc
> [email protected] since it seems to handle the
> mailing list a bit better.
OK, I will cc to your new email instead on v2.
Best Regards,
Hal
> I see you've changed the clock/reset and pinctrl quite a bit, so I'll
> comment on that separatel
On Wed, 5 Oct 2022 15:05:03 +0100, Conor Dooley wrote:
> On Wed, Oct 05, 2022 at 03:55:17PM +0200, Emil Renner Berthing wrote:
> > On Wed, 5 Oct 2022 at 15:48, Ben Dooks <[email protected]> wrote:
> > >
> > > On 05/10/2022 14:44, Emil Renner Berthing wrote:
> > > > On Thu, 29 Sept 2022 at 19:59, Ben Dooks <[email protected]> wrote:
> > > >>
> > > >> On 29/09/2022 15:32, Hal Feng wrote:
> > > >>> From: Emil Renner Berthing <[email protected]>
> > > >>>
> > > >>> This converts the driver to use the builtin_platform_driver_probe macro
> > > >>> to initialize the driver. This macro ends up calling device_initcall as
> > > >>> was used previously, but also allocates a platform device which gives us
> > > >>> access to much nicer APIs such as platform_ioremap_resource,
> > > >>> platform_get_irq and dev_err_probe.
> > > >>
> > > >> This is useful, but also there are other changes currently being sorted
> > > >> out by Zong Li (cc'd into this message) which have already been reviewed
> > > >> and are hopefully queued for the next kernel release.
> > > >>
> > > >>> Signed-off-by: Emil Renner Berthing <[email protected]>
> > > >>> Signed-off-by: Hal Feng <[email protected]>
> > > >
> > > > I'm ok with something like this being merged, but please note that if
> > > > we ever want to support the JH7100 which uses registers in this
> > > > peripheral to flush the cache for its non-coherent DMAs then this
> > > > driver needs to be loaded before other peripherals or we will trigger
> > > > the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
> > > > can do that when it's a platform driver. See this patch for an
> > > > alternative to support the JH71x0s:
> > > > https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
> > > >
> > > > /Emil
> > >
> > > Are you replying to your own patch that does the conversion to
> > > platform driver and then saying that it could actually cause
> > > issues?
> >
> > Yes, I can see it seems odd, but this patch lived for a while in the
> > kernel repo for the JH7100 until I rebased on 6.0-rc1 and realized the
> > above.
> > Hal Feng must have based his patches on a version of the code before
> > that when preparing this series.
> >
> > > I'm all for dropping this for the moment and keeping the old
> > > early init for the ccache.
> >
> > Cool.
>
> FWIW, if converting to a platform driver will inhibit using the driver
> for doing non-coherent stuff I would like to NAK the patch :)
>
Yeah, I agree, and this patch will be dropped on the next version.
On Mon, 3 Oct 2022 10:26:44 +0100, Ben Dooks wrote:
> On 29/09/2022 16:33, Conor Dooley wrote:
> > On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote:
> >> From: Emil Renner Berthing <[email protected]>
> >>
> >> This cache controller is also used on the StarFive JH7100 and JH7110
> >> SoCs.
> >
> > Ditto this patch, hopefully [0] will have landed as 6.1 material
> > before you get around to an actual v2.
> >
> > Thanks,
> > Conor
> >
> > 0 - https://lore.kernel.org/linux-riscv/[email protected]/
>
> Also, the l2 cache is being proprely named the ccache (composable cache)
> as it is not necessarily an L2 cache.
>
Thanks for reminding. I will modify the code, based on the patches from Zong Li.
I hope his patch series will be merged as soon as possible.
Best regards,
Hal
On Thu, 29 Sep 2022 13:43:49 -0500, Rob Herring wrote:
> On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
> > Add bindings for the reset controller on the JH7110 RISC-V
> > SoC by StarFive Technology Ltd.
> >
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
> > .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
> > 1 file changed, 54 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > new file mode 100644
> > index 000000000000..bb0010c200f9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > @@ -0,0 +1,54 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Emil Renner Berthing <[email protected]>
> > + - Hal Feng <[email protected]>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - starfive,jh7110-reset
>
> 'reg' needed? Is this a sub-block of something else?
Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
You might not see the complete patches at that time due to technical issue of
our smtp email server. Again, I feel so sorry about that.
syscrg: syscrg@13020000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x13020000 0x0 0x10000>;
syscrg_clk: clock-controller@13020000 {
compatible = "starfive,jh7110-clkgen-sys";
clocks = <&osc>, <&gmac1_rmii_refin>,
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
<&tdm_ext>, <&mclk_ext>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
"tdm_ext", "mclk_ext";
#clock-cells = <1>;
};
syscrg_rst: reset-controller@13020000 {
compatible = "starfive,jh7110-reset";
#reset-cells = <1>;
starfive,assert-offset = <0x2F8>;
starfive,status-offset= <0x308>;
starfive,nr-resets = <JH7110_SYSRST_END>;
};
};
In this case, we get the memory mapped space through the parent node with syscon
APIs. You can see patch 13 for detail.
static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
{
struct starfive_reset *data;
int ret;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->regmap = device_node_to_regmap(pdev->dev.of_node); //for JH7100
if (IS_ERR(data->regmap)) {
data->regmap = syscon_node_to_regmap(pdev->dev.of_node->parent); //for JH7110
if (IS_ERR(data->regmap)) {
dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
PTR_ERR(data->regmap));
return PTR_ERR(data->regmap);
}
}
...
}
We use this method to avoid errors when remapping the same address in two
different drivers, because clock and reset of StarFive JH7110 share a common
register address region. For similar implementation, refer to file [1] and [2].
[1] arch/riscv/boot/dts/canaan/k210.dtsi
sysctl: syscon@50440000 {
compatible = "canaan,k210-sysctl",
"syscon", "simple-mfd";
reg = <0x50440000 0x100>;
clocks = <&sysclk K210_CLK_APB1>;
clock-names = "pclk";
sysclk: clock-controller {
#clock-cells = <1>;
compatible = "canaan,k210-clk";
clocks = <&in0>;
};
sysrst: reset-controller {
compatible = "canaan,k210-rst";
#reset-cells = <1>;
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&sysctl>;
offset = <48>;
mask = <1>;
value = <1>;
};
};
[2] drivers/reset/reset-k210.c
>
> > +
> > + "#reset-cells":
> > + const: 1
> > +
> > + starfive,assert-offset:
> > + description: Offset of the first ASSERT register
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + starfive,status-offset:
> > + description: Offset of the first STATUS register
> > + $ref: /schemas/types.yaml#/definitions/uint32
>
> These can't be implied from the compatible string?
These two properties are the key differences among different reset controllers.
There are five memory regions for clock and reset in StarFive JH7110 SoC. They
are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
has different reset ASSERT/STATUS register offset and different number of reset
signals. After storing them in dt, the reset driver can register all reset
controllers with the same compatible string. All we expect is that all reset
controllers in a single SoC use the same compatible string for matching and the
reset driver can be applied to all StarFive SoCs using different compatible strings.
Just like
arch/riscv/boot/dts/starfive/jh7100.dtsi:
rstgen: reset-controller@11840000 {
compatible = "starfive,jh7100-reset";
reg = <0x0 0x11840000 0x0 0x10000>;
#reset-cells = <1>;
starfive,assert-offset = <0x0>;
starfive,status-offset= <0x10>;
starfive,nr-resets = <JH7100_RSTN_END>;
};
arch/riscv/boot/dts/starfive/jh7110.dtsi:
syscrg: syscrg@13020000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x13020000 0x0 0x10000>;
syscrg_clk: clock-controller@13020000 {
compatible = "starfive,jh7110-clkgen-sys";
...
};
syscrg_rst: reset-controller@13020000 {
compatible = "starfive,jh7110-reset";
#reset-cells = <1>;
starfive,assert-offset = <0x2F8>;
starfive,status-offset= <0x308>;
starfive,nr-resets = <JH7110_SYSRST_END>;
};
};
aoncrg: aoncrg@17000000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x17000000 0x0 0x10000>;
aoncrg_clk: clock-controller@17000000 {
compatible = "starfive,jh7110-clkgen-aon";
...
};
aoncrg_rst: reset-controller@17000000 {
compatible = "starfive,jh7110-reset";
#reset-cells = <1>;
starfive,assert-offset = <0x38>;
starfive,status-offset= <0x3C>;
starfive,nr-resets = <JH7110_AONRST_END>;
};
};
stgcrg: stgcrg@10230000 { //Not submmited yet
compatible = "syscon", "simple-mfd";
reg = <0x0 0x10230000 0x0 0x10000>;
stgcrg_clk: clock-controller@10230000 {
compatible = "starfive,jh7110-clkgen-stg";
...
};
stgcrg_rst: reset-controller@10230000 {
compatible = "starfive,jh7110-reset";
#reset-cells = <1>;
starfive,assert-offset = <0x74>;
starfive,status-offset= <0x78>;
starfive,nr-resets = <JH7110_STGRST_END>;
};
};
...
>
> > +
> > + starfive,nr-resets:
> > + description: Number of reset signals
> > + $ref: /schemas/types.yaml#/definitions/uint32
>
> Why do you need this? Most bindings don't. If just to validate 'resets'
> args, then don't.
Can be removed. Instead, the reset driver should includes some related
binding headers or defines some macros for pointing out the number of
reset signals of each reset controller.
Best regards,
Hal
>
>
> > +
> > +required:
> > + - compatible
> > + - "#reset-cells"
> > + - starfive,assert-offset
> > + - starfive,status-offset
> > + - starfive,nr-resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/reset/starfive-jh7110.h>
> > +
> > + syscrg_rst: reset-controller@13020000 {
> > + compatible = "starfive,jh7110-reset";
> > + #reset-cells = <1>;
> > + starfive,assert-offset = <0x2F8>;
> > + starfive,status-offset= <0x308>;
> > + starfive,nr-resets = <JH7110_SYSRST_END>;
> > + };
> > +
> > +...
> > --
> > 2.17.1
> >
> >
>
On 11/10/2022 11:30, Hal Feng wrote:
> On Thu, 29 Sep 2022 13:43:49 -0500, Rob Herring wrote:
>> On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
>>> Add bindings for the reset controller on the JH7110 RISC-V
>>> SoC by StarFive Technology Ltd.
>>>
>>> Signed-off-by: Hal Feng <[email protected]>
>>> ---
>>> .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
>>> 1 file changed, 54 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>> new file mode 100644
>>> index 000000000000..bb0010c200f9
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>> @@ -0,0 +1,54 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
>>> +
>>> +maintainers:
>>> + - Emil Renner Berthing <[email protected]>
>>> + - Hal Feng <[email protected]>
>>> +
>>> +properties:
>>> + compatible:
>>> + enum:
>>> + - starfive,jh7110-reset
>>
>> 'reg' needed? Is this a sub-block of something else?
>
> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
> You might not see the complete patches at that time due to technical issue of
> our smtp email server. Again, I feel so sorry about that.
>
> syscrg: syscrg@13020000 {
> compatible = "syscon", "simple-mfd";
> reg = <0x0 0x13020000 0x0 0x10000>;
>
> syscrg_clk: clock-controller@13020000 {
> compatible = "starfive,jh7110-clkgen-sys";
> clocks = <&osc>, <&gmac1_rmii_refin>,
> <&gmac1_rgmii_rxin>,
> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> <&tdm_ext>, <&mclk_ext>;
> clock-names = "osc", "gmac1_rmii_refin",
> "gmac1_rgmii_rxin",
> "i2stx_bclk_ext", "i2stx_lrck_ext",
> "i2srx_bclk_ext", "i2srx_lrck_ext",
> "tdm_ext", "mclk_ext";
> #clock-cells = <1>;
> };
>
> syscrg_rst: reset-controller@13020000 {
> compatible = "starfive,jh7110-reset";
> #reset-cells = <1>;
So the answer to the "reg needed?" is what? You have unit address but no
reg, so this is not correct.
> starfive,assert-offset = <0x2F8>;
> starfive,status-offset= <0x308>;
> starfive,nr-resets = <JH7110_SYSRST_END>;
> };
> };
>
> In this case, we get the memory mapped space through the parent node with syscon
> APIs. You can see patch 13 for detail.
>
> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
> {
(...)
>
>>
>>> +
>>> + "#reset-cells":
>>> + const: 1
>>> +
>>> + starfive,assert-offset:
>>> + description: Offset of the first ASSERT register
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> +
>>> + starfive,status-offset:
>>> + description: Offset of the first STATUS register
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>
>> These can't be implied from the compatible string?
>
> These two properties are the key differences among different reset controllers.
Different as in different compatibles? Please answer the questions...
> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> has different reset ASSERT/STATUS register offset and different number of reset
> signals.
Then these are not exactly the same devices, so using one compatible for
them does not look correct.
> After storing them in dt, the reset driver can register all reset
> controllers with the same compatible string.
Which is not how the compatible should be used...
> All we expect is that all reset
> controllers in a single SoC use the same compatible string for matching and the
> reset driver can be applied to all StarFive SoCs using different compatible strings.
Keep driver out of the talks.
> Just like
Existing bad pattern is not an argument to keep it going. Fix bad
patterns instead.
>
> arch/riscv/boot/dts/starfive/jh7100.dtsi:
>
> rstgen: reset-controller@11840000 {
> compatible = "starfive,jh7100-reset";
> reg = <0x0 0x11840000 0x0 0x10000>;
> #reset-cells = <1>;
> starfive,assert-offset = <0x0>;
> starfive,status-offset= <0x10>;
> starfive,nr-resets = <JH7100_RSTN_END>;
> };
>
> arch/riscv/boot/dts/starfive/jh7110.dtsi:
>
> syscrg: syscrg@13020000 {
> compatible = "syscon", "simple-mfd";
> reg = <0x0 0x13020000 0x0 0x10000>;
>
> syscrg_clk: clock-controller@13020000 {
> compatible = "starfive,jh7110-clkgen-sys";
> ...
> };
>
> syscrg_rst: reset-controller@13020000 {
> compatible = "starfive,jh7110-reset";
> #reset-cells = <1>;
> starfive,assert-offset = <0x2F8>;
> starfive,status-offset= <0x308>;
> starfive,nr-resets = <JH7110_SYSRST_END>;
> };
> };
>
> aoncrg: aoncrg@17000000 {
> compatible = "syscon", "simple-mfd";
> reg = <0x0 0x17000000 0x0 0x10000>;
>
> aoncrg_clk: clock-controller@17000000 {
> compatible = "starfive,jh7110-clkgen-aon";
> ...
> };
>
> aoncrg_rst: reset-controller@17000000 {
> compatible = "starfive,jh7110-reset";
> #reset-cells = <1>;
> starfive,assert-offset = <0x38>;
> starfive,status-offset= <0x3C>;
> starfive,nr-resets = <JH7110_AONRST_END>;
> };
> };
>
> stgcrg: stgcrg@10230000 { //Not submmited yet
> compatible = "syscon", "simple-mfd";
> reg = <0x0 0x10230000 0x0 0x10000>;
>
> stgcrg_clk: clock-controller@10230000 {
> compatible = "starfive,jh7110-clkgen-stg";
> ...
> };
>
> stgcrg_rst: reset-controller@10230000 {
> compatible = "starfive,jh7110-reset";
> #reset-cells = <1>;
> starfive,assert-offset = <0x74>;
> starfive,status-offset= <0x78>;
> starfive,nr-resets = <JH7110_STGRST_END>;
> };
> };
> ...
>
>>
>>> +
>>> + starfive,nr-resets:
>>> + description: Number of reset signals
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>
>> Why do you need this? Most bindings don't. If just to validate 'resets'
>> args, then don't.
>
> Can be removed. Instead, the reset driver should includes some related
> binding headers or defines some macros for pointing out the number of
> reset signals of each reset controller.
>
> Best regards,
> Hal
>
>>
>>
>>> +
>>> +required:
>>> + - compatible
>>> + - "#reset-cells"
>>> + - starfive,assert-offset
>>> + - starfive,status-offset
>>> + - starfive,nr-resets
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/reset/starfive-jh7110.h>
>>> +
>>> + syscrg_rst: reset-controller@13020000 {
Please test your patches.
Best regards,
Krzysztof
On Fri, 30 Sep 2022 12:59:01 +0200, Krzysztof Kozlowski wrote:
> On 30/09/2022 07:56, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > Add bindings for the always-on clock generator on the JH7110
> > RISC-V SoC by StarFive Technology Ltd.
> >
>
> (...)
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/starfive-jh7110-sys.h>
> > +
> > + aoncrg: clock-controller@17000000 {
>
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
Will rewrite the bindings and test them. Thanks.
Best regards,
Hal
On Fri, 30 Sep 2022 12:58:12 +0200, Krzysztof Kozlowski wrote:
> On 30/09/2022 00:26, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > Add bindings for the system clock generator on the JH7110
> > RISC-V SoC by StarFive Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
>
> (...)
>
> > + '#clock-cells':
> > + const: 1
> > + description:
> > + See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices.
> > +
> > +required:
> > + - compatible
> > + - clocks
> > + - clock-names
> > + - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + syscrg_clk: clock-controller@13020000 {
>
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
Will rewrite the bindings and test them. Thanks.
Best regards,
Hal
On Tue, 11 Oct 2022 at 18:21, Hal Feng <[email protected]> wrote:
>
> On Thu, 29 Sep 2022 13:43:49 -0500, Rob Herring wrote:
> > On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
> > > Add bindings for the reset controller on the JH7110 RISC-V
> > > SoC by StarFive Technology Ltd.
> > >
> > > Signed-off-by: Hal Feng <[email protected]>
> > > ---
> > > .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
> > > 1 file changed, 54 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > > new file mode 100644
> > > index 000000000000..bb0010c200f9
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > > @@ -0,0 +1,54 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Emil Renner Berthing <[email protected]>
> > > + - Hal Feng <[email protected]>
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - starfive,jh7110-reset
> >
> > 'reg' needed? Is this a sub-block of something else?
>
> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
> You might not see the complete patches at that time due to technical issue of
> our smtp email server. Again, I feel so sorry about that.
>
> syscrg: syscrg@13020000 {
> compatible = "syscon", "simple-mfd";
> reg = <0x0 0x13020000 0x0 0x10000>;
>
> syscrg_clk: clock-controller@13020000 {
> compatible = "starfive,jh7110-clkgen-sys";
> clocks = <&osc>, <&gmac1_rmii_refin>,
> <&gmac1_rgmii_rxin>,
> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> <&tdm_ext>, <&mclk_ext>;
> clock-names = "osc", "gmac1_rmii_refin",
> "gmac1_rgmii_rxin",
> "i2stx_bclk_ext", "i2stx_lrck_ext",
> "i2srx_bclk_ext", "i2srx_lrck_ext",
> "tdm_ext", "mclk_ext";
> #clock-cells = <1>;
> };
>
> syscrg_rst: reset-controller@13020000 {
> compatible = "starfive,jh7110-reset";
> #reset-cells = <1>;
> starfive,assert-offset = <0x2F8>;
> starfive,status-offset= <0x308>;
> starfive,nr-resets = <JH7110_SYSRST_END>;
> };
> };
>
> In this case, we get the memory mapped space through the parent node with syscon
> APIs. You can see patch 13 for detail.
>
> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
> {
> struct starfive_reset *data;
> int ret;
>
> data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> if (!data)
> return -ENOMEM;
>
> data->regmap = device_node_to_regmap(pdev->dev.of_node); //for JH7100
> if (IS_ERR(data->regmap)) {
> data->regmap = syscon_node_to_regmap(pdev->dev.of_node->parent); //for JH7110
> if (IS_ERR(data->regmap)) {
> dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
> PTR_ERR(data->regmap));
> return PTR_ERR(data->regmap);
> }
> }
> ...
> }
>
> We use this method to avoid errors when remapping the same address in two
> different drivers, because clock and reset of StarFive JH7110 share a common
> register address region. For similar implementation, refer to file [1] and [2].
>
> [1] arch/riscv/boot/dts/canaan/k210.dtsi
>
> sysctl: syscon@50440000 {
> compatible = "canaan,k210-sysctl",
> "syscon", "simple-mfd";
> reg = <0x50440000 0x100>;
> clocks = <&sysclk K210_CLK_APB1>;
> clock-names = "pclk";
>
> sysclk: clock-controller {
> #clock-cells = <1>;
> compatible = "canaan,k210-clk";
> clocks = <&in0>;
> };
>
> sysrst: reset-controller {
> compatible = "canaan,k210-rst";
> #reset-cells = <1>;
> };
>
> reboot: syscon-reboot {
> compatible = "syscon-reboot";
> regmap = <&sysctl>;
> offset = <48>;
> mask = <1>;
> value = <1>;
> };
> };
>
> [2] drivers/reset/reset-k210.c
Here the syscon makes a little more sense since the same memory area
does at least 3 different things, but on the JH7110 it is a dedicated
"clock and reset generator", CRG. So this is much better modelled with
a single driver taking care of both the clock and resets like the
original driver did. If you do
git grep reset_controller_register drivers/clk
..you can see that there are lots of other drivers for such
peripherals that combine clock and reset.
> >
> > > +
> > > + "#reset-cells":
> > > + const: 1
> > > +
> > > + starfive,assert-offset:
> > > + description: Offset of the first ASSERT register
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > +
> > > + starfive,status-offset:
> > > + description: Offset of the first STATUS register
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> >
> > These can't be implied from the compatible string?
>
> These two properties are the key differences among different reset controllers.
> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> has different reset ASSERT/STATUS register offset and different number of reset
> signals. After storing them in dt, the reset driver can register all reset
> controllers with the same compatible string. All we expect is that all reset
> controllers in a single SoC use the same compatible string for matching and the
> reset driver can be applied to all StarFive SoCs using different compatible strings.
> Just like
>
> arch/riscv/boot/dts/starfive/jh7100.dtsi:
>
> rstgen: reset-controller@11840000 {
> compatible = "starfive,jh7100-reset";
> reg = <0x0 0x11840000 0x0 0x10000>;
> #reset-cells = <1>;
> starfive,assert-offset = <0x0>;
> starfive,status-offset= <0x10>;
> starfive,nr-resets = <JH7100_RSTN_END>;
> };
>
> arch/riscv/boot/dts/starfive/jh7110.dtsi:
>
> syscrg: syscrg@13020000 {
> compatible = "syscon", "simple-mfd";
> reg = <0x0 0x13020000 0x0 0x10000>;
>
> syscrg_clk: clock-controller@13020000 {
> compatible = "starfive,jh7110-clkgen-sys";
> ...
> };
>
> syscrg_rst: reset-controller@13020000 {
> compatible = "starfive,jh7110-reset";
> #reset-cells = <1>;
> starfive,assert-offset = <0x2F8>;
> starfive,status-offset= <0x308>;
> starfive,nr-resets = <JH7110_SYSRST_END>;
> };
> };
>
> aoncrg: aoncrg@17000000 {
> compatible = "syscon", "simple-mfd";
> reg = <0x0 0x17000000 0x0 0x10000>;
>
> aoncrg_clk: clock-controller@17000000 {
> compatible = "starfive,jh7110-clkgen-aon";
> ...
> };
>
> aoncrg_rst: reset-controller@17000000 {
> compatible = "starfive,jh7110-reset";
> #reset-cells = <1>;
> starfive,assert-offset = <0x38>;
> starfive,status-offset= <0x3C>;
> starfive,nr-resets = <JH7110_AONRST_END>;
> };
> };
>
> stgcrg: stgcrg@10230000 { //Not submmited yet
> compatible = "syscon", "simple-mfd";
> reg = <0x0 0x10230000 0x0 0x10000>;
>
> stgcrg_clk: clock-controller@10230000 {
> compatible = "starfive,jh7110-clkgen-stg";
> ...
> };
>
> stgcrg_rst: reset-controller@10230000 {
> compatible = "starfive,jh7110-reset";
> #reset-cells = <1>;
> starfive,assert-offset = <0x74>;
> starfive,status-offset= <0x78>;
> starfive,nr-resets = <JH7110_STGRST_END>;
> };
> };
> ...
>
> >
> > > +
> > > + starfive,nr-resets:
> > > + description: Number of reset signals
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> >
> > Why do you need this? Most bindings don't. If just to validate 'resets'
> > args, then don't.
>
> Can be removed. Instead, the reset driver should includes some related
> binding headers or defines some macros for pointing out the number of
> reset signals of each reset controller.
>
> Best regards,
> Hal
>
> >
> >
> > > +
> > > +required:
> > > + - compatible
> > > + - "#reset-cells"
> > > + - starfive,assert-offset
> > > + - starfive,status-offset
> > > + - starfive,nr-resets
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/reset/starfive-jh7110.h>
> > > +
> > > + syscrg_rst: reset-controller@13020000 {
> > > + compatible = "starfive,jh7110-reset";
> > > + #reset-cells = <1>;
> > > + starfive,assert-offset = <0x2F8>;
> > > + starfive,status-offset= <0x308>;
> > > + starfive,nr-resets = <JH7110_SYSRST_END>;
> > > + };
> > > +
> > > +...
> > > --
> > > 2.17.1
> > >
> > >
> >
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On 12/10/2022 09:16, Hal Feng wrote:
>>>>> +properties:
>>>>> + compatible:
>>>>> + enum:
>>>>> + - starfive,jh7110-reset
>>>>
>>>> 'reg' needed? Is this a sub-block of something else?
>>>
>>> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
>>> You might not see the complete patches at that time due to technical issue of
>>> our smtp email server. Again, I feel so sorry about that.
>>>
>>> syscrg: syscrg@13020000 {
>>> compatible = "syscon", "simple-mfd";
>>> reg = <0x0 0x13020000 0x0 0x10000>;
>>>
>>> syscrg_clk: clock-controller@13020000 {
>>> compatible = "starfive,jh7110-clkgen-sys";
>>> clocks = <&osc>, <&gmac1_rmii_refin>,
>>> <&gmac1_rgmii_rxin>,
>>> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>>> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>>> <&tdm_ext>, <&mclk_ext>;
>>> clock-names = "osc", "gmac1_rmii_refin",
>>> "gmac1_rgmii_rxin",
>>> "i2stx_bclk_ext", "i2stx_lrck_ext",
>>> "i2srx_bclk_ext", "i2srx_lrck_ext",
>>> "tdm_ext", "mclk_ext";
>>> #clock-cells = <1>;
>>> };
>>>
>>> syscrg_rst: reset-controller@13020000 {
>>> compatible = "starfive,jh7110-reset";
>>> #reset-cells = <1>;
>>
>> So the answer to the "reg needed?" is what? You have unit address but no
>> reg, so this is not correct.
>
> Not needed in the reset-controller node, but needed in its parent node.
We do not talk about parent node. Rob's question was in this bindings.
Is this document a binding for the parent node or for this node?
> I am sorry
> for missing description to point it out in the bindings. I will rewrite all bindings
> for the next version. Unit address here should be deleted.
>
>>
>>> starfive,assert-offset = <0x2F8>;
>>> starfive,status-offset= <0x308>;
>>> starfive,nr-resets = <JH7110_SYSRST_END>;
>>> };
>>> };
>>>
>>> In this case, we get the memory mapped space through the parent node with syscon
>>> APIs. You can see patch 13 for detail.
>>>
>>> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
>>> {
>>
>>
>> (...)
>>
>>>
>>>>
>>>>> +
>>>>> + "#reset-cells":
>>>>> + const: 1
>>>>> +
>>>>> + starfive,assert-offset:
>>>>> + description: Offset of the first ASSERT register
>>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>>> +
>>>>> + starfive,status-offset:
>>>>> + description: Offset of the first STATUS register
>>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>>
>>>> These can't be implied from the compatible string?
>
> Definitely can. We do this is for simplifying the reset driver.
The role of the bindings is not to simplify some specific driver in some
specific OS...
> Otherwise, we may need to define more compatibles because there
> are multiple reset blocks in JH7110. Another case can be found at
> https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml
And why is this a problem? You have different hardware, so should have
different compatibles. Otherwise we would have a compatible
"all,everything" and use it in all possible devices.
>>> These two properties are the key differences among different reset controllers.
>>
>> Different as in different compatibles? Please answer the questions..>
>>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
>>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
>>> has different reset ASSERT/STATUS register offset and different number of reset
>>> signals.
>>
>> Then these are not exactly the same devices, so using one compatible for
>> them does not look correct.
>
> One compatible can just be matched by one device? I think this is what
> confuses me.
I don't understand the question.
>
> Best regards,
> Hal
>
Trim the replies - no need to quote everything (entire message following
last reply/quote).
Best regards,
Krzysztof
On Tue, 11 Oct 2022 12:36:08 -0400, Krzysztof Kozlowski wrote:
> On 11/10/2022 11:30, Hal Feng wrote:
>> On Thu, 29 Sep 2022 13:43:49 -0500, Rob Herring wrote:
>>> On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
>>>> Add bindings for the reset controller on the JH7110 RISC-V
>>>> SoC by StarFive Technology Ltd.
>>>>
>>>> Signed-off-by: Hal Feng <[email protected]>
>>>> ---
>>>> .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
>>>> 1 file changed, 54 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>>> new file mode 100644
>>>> index 000000000000..bb0010c200f9
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>>> @@ -0,0 +1,54 @@
>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
>>>> +
>>>> +maintainers:
>>>> + - Emil Renner Berthing <[email protected]>
>>>> + - Hal Feng <[email protected]>
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + enum:
>>>> + - starfive,jh7110-reset
>>>
>>> 'reg' needed? Is this a sub-block of something else?
>>
>> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
>> You might not see the complete patches at that time due to technical issue of
>> our smtp email server. Again, I feel so sorry about that.
>>
>> syscrg: syscrg@13020000 {
>> compatible = "syscon", "simple-mfd";
>> reg = <0x0 0x13020000 0x0 0x10000>;
>>
>> syscrg_clk: clock-controller@13020000 {
>> compatible = "starfive,jh7110-clkgen-sys";
>> clocks = <&osc>, <&gmac1_rmii_refin>,
>> <&gmac1_rgmii_rxin>,
>> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>> <&tdm_ext>, <&mclk_ext>;
>> clock-names = "osc", "gmac1_rmii_refin",
>> "gmac1_rgmii_rxin",
>> "i2stx_bclk_ext", "i2stx_lrck_ext",
>> "i2srx_bclk_ext", "i2srx_lrck_ext",
>> "tdm_ext", "mclk_ext";
>> #clock-cells = <1>;
>> };
>>
>> syscrg_rst: reset-controller@13020000 {
>> compatible = "starfive,jh7110-reset";
>> #reset-cells = <1>;
>
> So the answer to the "reg needed?" is what? You have unit address but no
> reg, so this is not correct.
Not needed in the reset-controller node, but needed in its parent node. I am sorry
for missing description to point it out in the bindings. I will rewrite all bindings
for the next version. Unit address here should be deleted.
>
>> starfive,assert-offset = <0x2F8>;
>> starfive,status-offset= <0x308>;
>> starfive,nr-resets = <JH7110_SYSRST_END>;
>> };
>> };
>>
>> In this case, we get the memory mapped space through the parent node with syscon
>> APIs. You can see patch 13 for detail.
>>
>> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
>> {
>
>
> (...)
>
>>
>>>
>>>> +
>>>> + "#reset-cells":
>>>> + const: 1
>>>> +
>>>> + starfive,assert-offset:
>>>> + description: Offset of the first ASSERT register
>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>> +
>>>> + starfive,status-offset:
>>>> + description: Offset of the first STATUS register
>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>
>>> These can't be implied from the compatible string?
Definitely can. We do this is for simplifying the reset driver.
Otherwise, we may need to define more compatibles because there
are multiple reset blocks in JH7110. Another case can be found at
https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml
>>
>> These two properties are the key differences among different reset controllers.
>
> Different as in different compatibles? Please answer the questions..>
>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
>> has different reset ASSERT/STATUS register offset and different number of reset
>> signals.
>
> Then these are not exactly the same devices, so using one compatible for
> them does not look correct.
One compatible can just be matched by one device? I think this is what
confuses me.
Best regards,
Hal
>
>> After storing them in dt, the reset driver can register all reset
>> controllers with the same compatible string.
>
> Which is not how the compatible should be used...
>
>> All we expect is that all reset
>> controllers in a single SoC use the same compatible string for matching and the
>> reset driver can be applied to all StarFive SoCs using different compatible strings.
>
> Keep driver out of the talks.
>
>> Just like
>
> Existing bad pattern is not an argument to keep it going. Fix bad
> patterns instead.
>
>>
>> arch/riscv/boot/dts/starfive/jh7100.dtsi:
>>
>> rstgen: reset-controller@11840000 {
>> compatible = "starfive,jh7100-reset";
>> reg = <0x0 0x11840000 0x0 0x10000>;
>> #reset-cells = <1>;
>> starfive,assert-offset = <0x0>;
>> starfive,status-offset= <0x10>;
>> starfive,nr-resets = <JH7100_RSTN_END>;
>> };
>>
>> arch/riscv/boot/dts/starfive/jh7110.dtsi:
>>
>> syscrg: syscrg@13020000 {
>> compatible = "syscon", "simple-mfd";
>> reg = <0x0 0x13020000 0x0 0x10000>;
>>
>> syscrg_clk: clock-controller@13020000 {
>> compatible = "starfive,jh7110-clkgen-sys";
>> ...
>> };
>>
>> syscrg_rst: reset-controller@13020000 {
>> compatible = "starfive,jh7110-reset";
>> #reset-cells = <1>;
>> starfive,assert-offset = <0x2F8>;
>> starfive,status-offset= <0x308>;
>> starfive,nr-resets = <JH7110_SYSRST_END>;
>> };
>> };
>>
>> aoncrg: aoncrg@17000000 {
>> compatible = "syscon", "simple-mfd";
>> reg = <0x0 0x17000000 0x0 0x10000>;
>>
>> aoncrg_clk: clock-controller@17000000 {
>> compatible = "starfive,jh7110-clkgen-aon";
>> ...
>> };
>>
>> aoncrg_rst: reset-controller@17000000 {
>> compatible = "starfive,jh7110-reset";
>> #reset-cells = <1>;
>> starfive,assert-offset = <0x38>;
>> starfive,status-offset= <0x3C>;
>> starfive,nr-resets = <JH7110_AONRST_END>;
>> };
>> };
>>
>> stgcrg: stgcrg@10230000 { //Not submmited yet
>> compatible = "syscon", "simple-mfd";
>> reg = <0x0 0x10230000 0x0 0x10000>;
>>
>> stgcrg_clk: clock-controller@10230000 {
>> compatible = "starfive,jh7110-clkgen-stg";
>> ...
>> };
>>
>> stgcrg_rst: reset-controller@10230000 {
>> compatible = "starfive,jh7110-reset";
>> #reset-cells = <1>;
>> starfive,assert-offset = <0x74>;
>> starfive,status-offset= <0x78>;
>> starfive,nr-resets = <JH7110_STGRST_END>;
>> };
>> };
>> ...
>>
>>>
>>>> +
>>>> + starfive,nr-resets:
>>>> + description: Number of reset signals
>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>
>>> Why do you need this? Most bindings don't. If just to validate 'resets'
>>> args, then don't.
>>
>> Can be removed. Instead, the reset driver should includes some related
>> binding headers or defines some macros for pointing out the number of
>> reset signals of each reset controller.
>>
>> Best regards,
>> Hal
>>
>>>
>>>
>>>> +
>>>> +required:
>>>> + - compatible
>>>> + - "#reset-cells"
>>>> + - starfive,assert-offset
>>>> + - starfive,status-offset
>>>> + - starfive,nr-resets
>>>> +
>>>> +additionalProperties: false
>>>> +
>>>> +examples:
>>>> + - |
>>>> + #include <dt-bindings/reset/starfive-jh7110.h>
>>>> +
>>>> + syscrg_rst: reset-controller@13020000 {
>
> Please test your patches.
>
>
> Best regards,
> Krzysztof
>
>
Hey Hal Feng,
On Wed, Oct 12, 2022 at 09:33:42AM -0400, Krzysztof Kozlowski wrote:
> >>> These two properties are the key differences among different reset controllers.
> >>
> >> Different as in different compatibles? Please answer the questions..>
> >>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> >>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> >>> has different reset ASSERT/STATUS register offset and different number of reset
> >>> signals.
> >>
> >> Then these are not exactly the same devices, so using one compatible for
> >> them does not look correct.
> >
> > One compatible can just be matched by one device? I think this is what
> > confuses me.
>
> I don't understand the question.
If two SoCs have exactly the same device/peripheral then they _can_ use
the same compatible. If they share some common, viable feature-set then
one can "fall back" to the other depending on what your Venn diagram of
common features looks like. I've not been following this too closely,
but I think what Krzysztof is suggesting is that you have a jh7100 and
a jh7110 compatible. Then in your driver you just "know" that if you
match against jh7110 which values to use for register offsets & vice
versa for a match against the jh7100. There's many examples over the
tree for how to handle this sort of thing rather than including it in
the devicetree.
Maybe Rob and Krzysztof will scream at me for this description, but
devicetree is about how periperhals etc are connected together in the
system not about the internals of a given peripheral.
Following that logic, the devicetree should not contain register offsets
etc that are a known quanitity once you've determined that you are running
on vendor,soc-foo.
Hopefully that helps with your confusion somewhat?
Conor.
On Wed, 12 Oct 2022 09:33:42 -0400, Krzysztof Kozlowski wrote:
> On 12/10/2022 09:16, Hal Feng wrote:
>>>>>> +properties:
>>>>>> + compatible:
>>>>>> + enum:
>>>>>> + - starfive,jh7110-reset
>>>>>
>>>>> 'reg' needed? Is this a sub-block of something else?
>>>>
>>>> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
>>>> You might not see the complete patches at that time due to technical issue of
>>>> our smtp email server. Again, I feel so sorry about that.
>>>>
>>>> syscrg: syscrg@13020000 {
>>>> compatible = "syscon", "simple-mfd";
>>>> reg = <0x0 0x13020000 0x0 0x10000>;
>>>>
>>>> syscrg_clk: clock-controller@13020000 {
>>>> compatible = "starfive,jh7110-clkgen-sys";
>>>> clocks = <&osc>, <&gmac1_rmii_refin>,
>>>> <&gmac1_rgmii_rxin>,
>>>> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>>>> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>>>> <&tdm_ext>, <&mclk_ext>;
>>>> clock-names = "osc", "gmac1_rmii_refin",
>>>> "gmac1_rgmii_rxin",
>>>> "i2stx_bclk_ext", "i2stx_lrck_ext",
>>>> "i2srx_bclk_ext", "i2srx_lrck_ext",
>>>> "tdm_ext", "mclk_ext";
>>>> #clock-cells = <1>;
>>>> };
>>>>
>>>> syscrg_rst: reset-controller@13020000 {
>>>> compatible = "starfive,jh7110-reset";
>>>> #reset-cells = <1>;
>>>
>>> So the answer to the "reg needed?" is what? You have unit address but no
>>> reg, so this is not correct.
>>
>> Not needed in the reset-controller node, but needed in its parent node.
>
> We do not talk about parent node. Rob's question was in this bindings.
> Is this document a binding for the parent node or for this node?
This node. So not needed.
>
>> I am sorry
>> for missing description to point it out in the bindings. I will rewrite all bindings
>> for the next version. Unit address here should be deleted.
>>
>>>
>>>> starfive,assert-offset = <0x2F8>;
>>>> starfive,status-offset= <0x308>;
>>>> starfive,nr-resets = <JH7110_SYSRST_END>;
>>>> };
>>>> };
>>>>
>>>> In this case, we get the memory mapped space through the parent node with syscon
>>>> APIs. You can see patch 13 for detail.
>>>>
>>>> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
>>>> {
>>>
>>>
>>> (...)
>>>
>>>>
>>>>>
>>>>>> +
>>>>>> + "#reset-cells":
>>>>>> + const: 1
>>>>>> +
>>>>>> + starfive,assert-offset:
>>>>>> + description: Offset of the first ASSERT register
>>>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>>>> +
>>>>>> + starfive,status-offset:
>>>>>> + description: Offset of the first STATUS register
>>>>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>>>>
>>>>> These can't be implied from the compatible string?
>>
>> Definitely can. We do this is for simplifying the reset driver.
>
> The role of the bindings is not to simplify some specific driver in some
> specific OS...
>
>> Otherwise, we may need to define more compatibles because there
>> are multiple reset blocks in JH7110. Another case can be found at
>> https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml
>
> And why is this a problem? You have different hardware, so should have
> different compatibles. Otherwise we would have a compatible
> "all,everything" and use it in all possible devices.
Okay, I get it. Thanks a lot.
Best regards,
Hal
On Wed, 12 Oct 2022 15:05:04 +0100, Conor Dooley wrote:
> Hey Hal Feng,
>
> On Wed, Oct 12, 2022 at 09:33:42AM -0400, Krzysztof Kozlowski wrote:
> > >>> These two properties are the key differences among different reset controllers.
> > >>
> > >> Different as in different compatibles? Please answer the questions..>
> > >>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> > >>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> > >>> has different reset ASSERT/STATUS register offset and different number of reset
> > >>> signals.
> > >>
> > >> Then these are not exactly the same devices, so using one compatible for
> > >> them does not look correct.
> > >
> > > One compatible can just be matched by one device? I think this is what
> > > confuses me.
> >
> > I don't understand the question.
>
> If two SoCs have exactly the same device/peripheral then they _can_ use
> the same compatible. If they share some common, viable feature-set then
> one can "fall back" to the other depending on what your Venn diagram of
> common features looks like. I've not been following this too closely,
> but I think what Krzysztof is suggesting is that you have a jh7100 and
> a jh7110 compatible. Then in your driver you just "know" that if you
> match against jh7110 which values to use for register offsets & vice
> versa for a match against the jh7100. There's many examples over the
> tree for how to handle this sort of thing rather than including it in
> the devicetree.
>
> Maybe Rob and Krzysztof will scream at me for this description, but
> devicetree is about how periperhals etc are connected together in the
> system not about the internals of a given peripheral.
>
> Following that logic, the devicetree should not contain register offsets
> etc that are a known quanitity once you've determined that you are running
> on vendor,soc-foo.
>
> Hopefully that helps with your confusion somewhat?
> Conor.
Yes, anyway, thank you for the detailed reply.
Best regards,
Hal
Quoting Emil Renner Berthing (2022-10-05 06:14:44)
> > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> > > if (!priv)
> > > return -ENOMEM;
> > >
> > > - spin_lock_init(&priv->rmw_lock);
> > > priv->dev = &pdev->dev;
> > > - priv->base = devm_platform_ioremap_resource(pdev, 0);
> > > - if (IS_ERR(priv->base))
> > > - return PTR_ERR(priv->base);
> > > + priv->regmap = device_node_to_regmap(priv->dev->of_node);
> >
> > This is sad. Why do we need to make a syscon? Can we instead use the
> > auxiliary bus to make a reset device that either gets a regmap made here
> > in this driver or uses a void __iomem * mapped with ioremap
> > (priv->base)?
>
> In my original code the clock driver just registers the resets too
> similar to other combined clock and reset drivers. I wonder what you
> think about that approach:
> https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
> and
> https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
I think we should use auxiliary bus and split the driver logically into
a reset driver in drivers/reset and a clk driver in drivers/clk. That
way the appropriate maintainers can review the code. There is only one
platform device with a single reg property and node in DT, but there are
two drivers.
On Wed, 5 Oct 2022 15:31:59 +0200, Emil Renner Berthing wrote:
> On Tue, 4 Oct 2022 at 10:57, Linus Walleij <[email protected]> wrote:
> >
> > On Fri, Sep 30, 2022 at 9:45 AM Hal Feng
> > <[email protected]> wrote:
> >
> > > From: Jianlong Huang <[email protected]>
> > >
> > > Add pinctrl driver for StarFive JH7110 SoC.
> > >
> > > Signed-off-by: Jianlong Huang <[email protected]>
> > > Signed-off-by: Hal Feng <[email protected]>
> >
> > Since Emil submitted the first driver I would really appreciate his review
> > on this version.
>
> I tried really hard to come up with a good way to share code between
> the JH7100 and JH7110 drivers, but so many details different on the
> JH7110 that it's probably best to just have a separate driver, so that
> part is fine.
>
> As mentioned elsewhere this driver certainly shouldn't be accepted
> without following the generic pinctrl and pinmux bindings. You can see
> the driver I wrote here:
> https://github.com/esmil/linux/commit/c2633315385fef1a25aa3711facef07d915820e1
>
> It is certainly not perfect and far from complete, but at least it
> does follow the generic bindings. Feel free to copy all or parts of
> that.
Thanks for your great contribution! We will rewrite the pinctrl driver
and bindings so make them follow the generic pinctrl framework.
Best regards,
Hal
On Fri, 30 Sep 2022 22:41:23 +0100, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 09:54:14PM +0100, Ben Dooks wrote:
> > On 30/09/2022 10:06, Hal Feng wrote:
> > > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> > > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
> > >
> > > Signed-off-by: Hal Feng <[email protected]>
> >
> > That might be useful for other users at some point an I don't
> > think it adds much code.
>
> Honestly I think this should be applied for 6.1, for parity with the
> other SoCs that have their serial console enabled by default.
>
> Reviewed-by: Conor Dooley <[email protected]>
Could this patch be pulled out and applied for v6.1? So the JH7100
and the coming JH7110 can enable serial console by default when
booting. Thanks.
Best regards,
Hal
On Sat, 1 Oct 2022 11:52:00 +0100, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 03:49:14PM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > Add initial device tree for the JH7110 RISC-V SoC by
> > StarFive Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Jianlong Huang <[email protected]>
> > Signed-off-by: Hal Feng <[email protected]>
>
> There's little point reviewing this dt since there's a load of issues
> that you can trivially find by running dtbs_check/dt_binding_check, but
> this SoB change is wrong - if Emil wrote the patch, then Jianlong's SoB
> is either redundant or should be accompanied by a Co-developed-by tag.
>
> Ditto for patch 28/30 "RISC-V: Add StarFive JH7110 VisionFive2 board
> device tree".
Will add Co-developed-by tag for Jianlong. Thanks.
>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
> > 1 file changed, 449 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > new file mode 100644
> > index 000000000000..46f418d4198a
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> > +
> > + osc: osc {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + };
> > +
> > + clk_rtc: clk_rtc {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + };
> > +
> > + gmac0_rmii_refin: gmac0_rmii_refin {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <50000000>;
>
> I assume, given osc has it's frequency set in the board dts, that these
> are all oscillators on the SoC?
These are all on the board. Should move all "clock-frequency" to the board dts.
I will recheck and modify this patch.
Best regards,
Hal
在 2022-09-30星期五的 15:38 +0800，Hal Feng写道：
> From: Jianlong Huang <[email protected]>
>
> Add pinctrl bindings for StarFive JH7110 SoC.
>
> Signed-off-by: Jianlong Huang <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> ---
> .../pinctrl/starfive,jh7110-pinctrl.yaml | 202
> ++++++++++++++++++
> 1 file changed, 202 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> new file mode 100644
> index 000000000000..482012ad8a14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id:
> http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Pin Controller Device Tree Bindings
> +
> +description: |
> + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
> +
> +maintainers:
> + - Jianlong Huang <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - starfive,jh7110-sys-pinctrl
> + - starfive,jh7110-aon-pinctrl
> +
> + reg:
> + minItems: 2
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: control
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + "#gpio-cells":
> + const: 2
> +
> + interrupts:
> + maxItems: 1
> + description: The GPIO parent interrupt.
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 2
> +
> + ngpios:
> + enum:
> + - 64
> + - 4
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - "#gpio-cells"
> + - interrupts
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> +patternProperties:
> + '-[0-9]+$':
> + type: object
> + patternProperties:
> + '-pins$':
> + type: object
> + description: |
> + A pinctrl node should contain at least one subnode
> representing the
> + pinctrl groups available on the machine. Each subnode will
> list the
> + pins it needs, and how they should be configured, with
> regard to
> + muxer configuration, system signal configuration, pin
> groups for
> + vin/vout module, pin voltage, mux functions for output,
> mux functions
> + for output enable, mux functions for input.
> +
> + properties:
> + starfive,pins:
> + description: |
> + The list of pin identifiers that properties in the
> node apply to.
> + This should be set using the PAD_GPIOX macros.
> + This has to be specified.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 63
Hi,
I am adapting for Pine64's Star64 board, which utilizes a JH7110 SoC.
It does not features a USB overcurrent pin as GPIO, thus this pin needs
to be routed in PIO controller to fixed 1 (by writing 1 to
SYS_IOMUX_CFGSAIF__SYSCFG_FMUX_32[22:16]).
I think this kind of situation needs to be considered as part of DT
binding.
BTW if you have any difficulty refactoring the DT binding to standard
pinconf one, I am free to provide help.
Thanks,
Icenowy Zheng
> +
> + starfive,pinmux:
> + description: |
> + The list of GPIOs and their mux functions that
> properties in the
> + node apply to. This should be set using the
> PAD_GPIOX_FUNC_SEL
> + macro with its value.
> + This is optional for some pins.
> + The value of PAD_GPIOX_FUNC_SEL macro can selects:
> + 0: GPIOX mux function 0,
> + 1: GPIOX mux function 1,
> + 2: GPIOX mux function 2.
> +
> + starfive,pin-ioconfig:
> + description: |
> + This is used to configure the core settings of system
> signals.
> + The combination of GPIO_IE or GPIO_DS or GPIO_PU or
> GPIO_PD or
> + GPIO_SLEW or GPIO_SMT or GPIO_POS.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + starfive,padmux:
> + description: |
> + The padmux is for vin/vout module to select pin
> groups.
> + 0: vout will be set at pins from PAD_GPIO7 to
> PAD_GPIO34,
> + when PAD_GPIOX_FUNC_SEL is set as 1.
> + vin will be set at pins from PAD_GPIO6 to
> PAD_GPIO20.
> + when PAD_GPIOX_FUNC_SEL is set as 2.
> + 1: vout will be set at pins from PAD_GPIO36 to
> PAD_GPIO63,
> + when PAD_GPIOX_FUNC_SEL is set as 1.
> + vin will be set at pins from PAD_GPIO21 to
> PAD_GPIO35.
> + when PAD_GPIOX_FUNC_SEL is set as 2.
> + 2: vin will be set at pins from PAD_GPIO36 to
> PAD_GPIO50,
> + when PAD_GPIOX_FUNC_SEL is set as 2
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + starfive,pin-syscon:
> + description: |
> + This is used to set pin voltage,
> + 0: 3.3V, 1: 2.5V, 2: 1.8V.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + starfive,pin-gpio-dout:
> + description: |
> + This is used to set their mux functions for output.
> + This should be set using the GPO_XXX macro,
> + such as GPO_LOW, GPO_UART0_SOUT.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 107
> +
> + starfive,pin-gpio-doen:
> + description: |
> + This is used to set their mux functions for output
> enable.
> + This should be set using the OEN_XXX macro,
> + such as OEN_LOW, OEN_I2C0_IC_CLK_OE.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 49
> +
> + starfive,pin-gpio-din:
> + description: |
> + This is used to set their mux functions for input.
> + This should be set using the GPI_XXX macro,
> + such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 90
> +
> + additionalProperties: false
> +
> + additionalProperties: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive-jh7110-sys.h>
> + #include <dt-bindings/reset/starfive-jh7110.h>
> + #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> + gpio: gpio@13040000 {
> + compatible = "starfive,jh7110-sys-pinctrl";
> + reg = <0x0 0x13040000 0x0 0x10000>;
> + reg-names = "control";
> + clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
> + resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
> + interrupts = <86>;
> + interrupt-controller;
> + #gpio-cells = <2>;
> + ngpios = <64>;
> + status = "okay";
> +
> + uart0_pins: uart0-pins {
> + uart0-pins-tx {
> + starfive,pins = <PAD_GPIO5>;
> + starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
> + starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
> + starfive,pin-gpio-doen = <OEN_LOW>;
> + };
> +
> + uart0-pins-rx {
> + starfive,pins = <PAD_GPIO6>;
> + starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
> + starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
> + starfive,pin-gpio-doen = <OEN_HIGH>;
> + starfive,pin-gpio-din = <GPI_UART0_SIN>;
> + };
> + };
> + };
> +
> + &uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> + };
> +
> +...
On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
> Quoting Emil Renner Berthing (2022-10-05 06:14:44)
> > > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> > > > if (!priv)
> > > > return -ENOMEM;
> > > >
> > > > - spin_lock_init(&priv->rmw_lock);
> > > > priv->dev = &pdev->dev;
> > > > - priv->base = devm_platform_ioremap_resource(pdev, 0);
> > > > - if (IS_ERR(priv->base))
> > > > - return PTR_ERR(priv->base);
> > > > + priv->regmap = device_node_to_regmap(priv->dev->of_node);
> > >
> > > This is sad. Why do we need to make a syscon? Can we instead use the
> > > auxiliary bus to make a reset device that either gets a regmap made here
> > > in this driver or uses a void __iomem * mapped with ioremap
> > > (priv->base)?
> >
> > In my original code the clock driver just registers the resets too
> > similar to other combined clock and reset drivers. I wonder what you
> > think about that approach:
> > https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
> > and
> > https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
>
> I think we should use auxiliary bus and split the driver logically into
> a reset driver in drivers/reset and a clk driver in drivers/clk. That
> way the appropriate maintainers can review the code. There is only one
> platform device with a single reg property and node in DT, but there are
> two drivers.
Yes, I agree that the reset driver and the clock driver should be split.
However, I think using auxiliary bus is a little bit complicated in this
case, because the reset is not a part of functionality of the clock in
JH7110. They just share a common register base address. I think it is
better to use ioremap for the same address, and the dt will be like
syscrg_clk: clock-controller@13020000 {
compatible = "starfive,jh7110-clkgen-sys";
reg = <0x0 0x13020000 0x0 0x10000>;
...
};
syscrg_rst: reset-controller@13020000 {
compatible = "starfive,jh7110-reset-sys";
reg = <0x0 0x13020000 0x0 0x10000>;
...
};
What do you think of this approach? I would appreciate your suggestions.
Best regards,
Hal
On 23 October 2022 05:11:41 IST, Hal Feng <[email protected]> wrote:
>On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
>> Quoting Emil Renner Berthing (2022-10-05 06:14:44)
>> > > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
>> > > > if (!priv)
>> > > > return -ENOMEM;
>> > > >
>> > > > - spin_lock_init(&priv->rmw_lock);
>> > > > priv->dev = &pdev->dev;
>> > > > - priv->base = devm_platform_ioremap_resource(pdev, 0);
>> > > > - if (IS_ERR(priv->base))
>> > > > - return PTR_ERR(priv->base);
>> > > > + priv->regmap = device_node_to_regmap(priv->dev->of_node);
>> > >
>> > > This is sad. Why do we need to make a syscon? Can we instead use the
>> > > auxiliary bus to make a reset device that either gets a regmap made here
>> > > in this driver or uses a void __iomem * mapped with ioremap
>> > > (priv->base)?
>> >
>> > In my original code the clock driver just registers the resets too
>> > similar to other combined clock and reset drivers. I wonder what you
>> > think about that approach:
>> > https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
>> > and
>> > https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
>>
>> I think we should use auxiliary bus and split the driver logically into
>> a reset driver in drivers/reset and a clk driver in drivers/clk. That
>> way the appropriate maintainers can review the code. There is only one
>> platform device with a single reg property and node in DT, but there are
>> two drivers.
>
>Yes, I agree that the reset driver and the clock driver should be split.
>However, I think using auxiliary bus is a little bit complicated in this
>case, because the reset is not a part of functionality of the clock in
>JH7110. They just share a common register base address. I think it is
>better to use ioremap for the same address, and the dt will be like
>
>syscrg_clk: clock-controller@13020000 {
> compatible = "starfive,jh7110-clkgen-sys";
> reg = <0x0 0x13020000 0x0 0x10000>;
> ...
>};
>syscrg_rst: reset-controller@13020000 {
> compatible = "starfive,jh7110-reset-sys";
> reg = <0x0 0x13020000 0x0 0x10000>;
> ...
>};
>
>What do you think of this approach? I would appreciate your suggestions.
No, the dtb checks will all start warning for this.
Aux bus is not that difficult, you can likely copy much of what I did recently in clk-mpfs.c
>
>Best regards,
>Hal
Quoting Hal Feng (2022-10-22 21:11:41)
> On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
> > I think we should use auxiliary bus and split the driver logically into
> > a reset driver in drivers/reset and a clk driver in drivers/clk. That
> > way the appropriate maintainers can review the code. There is only one
> > platform device with a single reg property and node in DT, but there are
> > two drivers.
>
> Yes, I agree that the reset driver and the clock driver should be split.
> However, I think using auxiliary bus is a little bit complicated in this
> case, because the reset is not a part of functionality of the clock in
> JH7110. They just share a common register base address.
That is why auxiliary bus exists.
> I think it is
> better to use ioremap for the same address, and the dt will be like
>
> syscrg_clk: clock-controller@13020000 {
> compatible = "starfive,jh7110-clkgen-sys";
> reg = <0x0 0x13020000 0x0 0x10000>;
> ...
> };
> syscrg_rst: reset-controller@13020000 {
> compatible = "starfive,jh7110-reset-sys";
> reg = <0x0 0x13020000 0x0 0x10000>;
> ...
> };
>
> What do you think of this approach? I would appreciate your suggestions.
>
We shouldn't have two different nodes with the same reg property. Please
ioremap in whatever driver probes and creates the auxiliary device(s)
and then pass the void __iomem * to it.
On Wed, 26 Oct 2022 18:26:03 -0700, Stephen Boyd wrote:
> Quoting Hal Feng (2022-10-22 21:11:41)
> > On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
> > > I think we should use auxiliary bus and split the driver logically into
> > > a reset driver in drivers/reset and a clk driver in drivers/clk. That
> > > way the appropriate maintainers can review the code. There is only one
> > > platform device with a single reg property and node in DT, but there are
> > > two drivers.
> >
> > Yes, I agree that the reset driver and the clock driver should be split.
> > However, I think using auxiliary bus is a little bit complicated in this
> > case, because the reset is not a part of functionality of the clock in
> > JH7110. They just share a common register base address.
>
> That is why auxiliary bus exists.
>
> > I think it is
> > better to use ioremap for the same address, and the dt will be like
> >
> > syscrg_clk: clock-controller@13020000 {
> > compatible = "starfive,jh7110-clkgen-sys";
> > reg = <0x0 0x13020000 0x0 0x10000>;
> > ...
> > };
> > syscrg_rst: reset-controller@13020000 {
> > compatible = "starfive,jh7110-reset-sys";
> > reg = <0x0 0x13020000 0x0 0x10000>;
> > ...
> > };
> >
> > What do you think of this approach? I would appreciate your suggestions.
> >
>
> We shouldn't have two different nodes with the same reg property. Please
> ioremap in whatever driver probes and creates the auxiliary device(s)
> and then pass the void __iomem * to it.
Okay, I will use auxiliary bus for clock and reset driver on the next version.
Best regards,
Hal
On Sun, 23 Oct 2022 11:25:26 +0100, Conor Dooley wrote:
> On 23 October 2022 05:11:41 IST, Hal Feng <[email protected]> wrote:
> >On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
> >> Quoting Emil Renner Berthing (2022-10-05 06:14:44)
> >> > > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> >> > > > if (!priv)
> >> > > > return -ENOMEM;
> >> > > >
> >> > > > - spin_lock_init(&priv->rmw_lock);
> >> > > > priv->dev = &pdev->dev;
> >> > > > - priv->base = devm_platform_ioremap_resource(pdev, 0);
> >> > > > - if (IS_ERR(priv->base))
> >> > > > - return PTR_ERR(priv->base);
> >> > > > + priv->regmap = device_node_to_regmap(priv->dev->of_node);
> >> > >
> >> > > This is sad. Why do we need to make a syscon? Can we instead use the
> >> > > auxiliary bus to make a reset device that either gets a regmap made here
> >> > > in this driver or uses a void __iomem * mapped with ioremap
> >> > > (priv->base)?
> >> >
> >> > In my original code the clock driver just registers the resets too
> >> > similar to other combined clock and reset drivers. I wonder what you
> >> > think about that approach:
> >> > https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
> >> > and
> >> > https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
> >>
> >> I think we should use auxiliary bus and split the driver logically into
> >> a reset driver in drivers/reset and a clk driver in drivers/clk. That
> >> way the appropriate maintainers can review the code. There is only one
> >> platform device with a single reg property and node in DT, but there are
> >> two drivers.
> >
> >Yes, I agree that the reset driver and the clock driver should be split.
> >However, I think using auxiliary bus is a little bit complicated in this
> >case, because the reset is not a part of functionality of the clock in
> >JH7110. They just share a common register base address. I think it is
> >better to use ioremap for the same address, and the dt will be like
> >
> >syscrg_clk: clock-controller@13020000 {
> > compatible = "starfive,jh7110-clkgen-sys";
> > reg = <0x0 0x13020000 0x0 0x10000>;
> > ...
> >};
> >syscrg_rst: reset-controller@13020000 {
> > compatible = "starfive,jh7110-reset-sys";
> > reg = <0x0 0x13020000 0x0 0x10000>;
> > ...
> >};
> >
> >What do you think of this approach? I would appreciate your suggestions.
>
> No, the dtb checks will all start warning for this.
> Aux bus is not that difficult, you can likely copy much of what I did recently in clk-mpfs.c
Thanks for reminding and your helpful example.
Best regards,
Hal
On Sat, 1 Oct 2022 12:14:49 +0100, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 03:53:53PM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <[email protected]>
> >
> > Add a minimal device tree for StarFive JH7110 VisionFive2 board.
> > Support booting and basic clock/reset/pinctrl/uart drivers.
> >
>
> I would like to see a link to the publicly available datasheet or
> documentation for the board (and for the SoC in patch 28) please.
All documents can be found at RVspace Documentation Center maintained
by StarFive. The related documents of JH7110 SoC and VisionFive2 board
are as follows.
StarFive JH7110 SoC:
https://doc-en.rvspace.org/Doc_Center/jh7110.html
StarFive VisionFive2 board:
https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
>
> > Signed-off-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Jianlong Huang <[email protected]>
>
> Ditto from patch 28 re: the SoB chain.
>
> > Signed-off-by: Hal Feng <[email protected]>
> > ---
>
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> > new file mode 100644
> > index 000000000000..6b9fe32c7eac
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> > @@ -0,0 +1,91 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
> > + */
> > +
> > +/dts-v1/;
> > +#include "jh7110.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> > +
> > +/ {
> > + model = "StarFive VisionFive V2";
> > + compatible = "starfive,visionfive-v2", "starfive,jh7110";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
>
> Should we also have a chosen node here?
Will add it. Thanks.
>
> > +
> > + cpus {
> > + timebase-frequency = <4000000>;
> > + };
> > +
> > + memory@40000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x40000000 0x1 0x0>;
>
> What is going to happen to the 2 GB variant if they attempt to use this
> devicetree?
The VisionFive2 board now has 4GB version and 8GB version only. Before
linux startup, we will change this property in dtb through u-boot to
make sure the board can boot up with the correct memory size.
>
> > + };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + linux,cma {
> > + compatible = "shared-dma-pool";
> > + reusable;
> > + size = <0x0 0x20000000>;
> > + alignment = <0x0 0x1000>;
> > + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
> > + linux,cma-default;
> > + };
> > +
> > + e24_mem: e24@c0000000 {
>
> I had a conversation previously with Icenowy [0] about the e24 on the
> jh7100 that didn't really come to a conclusion about how to represent
> it there - but looks like you've decided that it should be a remoteproc
> for the jh7100?
Yes, we treat it as a remoteproc outside the cpus node. But after
communication with my colleagues, I found that all nodes in
"reserved-memory" are not used in the minimal support for VisionFive2
board. So for this series, I would like to remove "reserved-memory"
in v2.
>
> Is this another situation where peripherals appear at different
> addresses for the e24 compared to the u74s? Or has that changed for the> jh7100, and really the e24 should be described in the CPUs node? If it
> is the latter, you can pick the first patch from [0] into your series.
>
> 0 - https://lore.kernel.org/linux-riscv/[email protected]> > + reg = <0x0 0xc0110000 0x0 0xf0000>;
> > + no-map;
> > + };
> > +
> > + xrp_reserved: xrpbuffer@f0000000 {
>
> "Following the generic-names recommended practice, node names should
> reflect the purpose of the node (ie. “framebuffer” or “dma-pool”)."
>
> I tried googling around for an explanation for what the xrp was, and all
> I could find was this out-of-tree text binding:
> https://github.com/foss-xtensa/xrp/blob/master/xrp-kernel/cdns%2Cxrp-hw-simple%2Cv1.txt
The name is from the device driver of HiFi4 DSP provided by Cadence,
which is not in the mainline. "xrp" is a short name of
"Xtensa Remote Processing".
Best regards,
Hal