From: Patrice Chotard <[email protected]>
The goal of this series is to allow to use QSPI bus as a 8 lines communication
channel for specific purpose.
The QSPI block offers the possibility to communicate with 2 flashes in
parrallel using the dual flash mode, 8 data lines are then used.
A new ST specific property need to be created to enable this dual flash mode.
The addition of the legacy transfer_one_message() spi callback is also needed
as currently the stm32-qspi driver only supports spi_controller_mem_ops API.
Patrice Chotard (3):
dt-bindings: spi: stm32: Add st,dual-flash property in
st,stm32-qspi.yaml
spi: stm32_qspi: Add transfer_one_message() spi callback
ARM: dts: stm32: Create separate pinmux for qspi cs pin in
stm32mp15-pinctrl.dtsi
.../bindings/spi/st,stm32-qspi.yaml | 8 ++
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 50 +++++---
arch/arm/boot/dts/stm32mp157c-ev1.dts | 12 +-
drivers/spi/spi-stm32-qspi.c | 111 ++++++++++++++++--
4 files changed, 155 insertions(+), 26 deletions(-)
--
2.25.1
From: Patrice Chotard <[email protected]>
Create a separate pinmux for qspi chip select in stm32mp15-pinctrl.dtsi.
In the case we want to use transfer_one() API to communicate with a SPI
device, chip select signal must be driven individually.
Signed-off-by: Patrice Chotard <[email protected]>
---
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 50 ++++++++++++++++--------
arch/arm/boot/dts/stm32mp157c-ev1.dts | 12 +++++-
2 files changed, 43 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index 6052243ad81c..ade4fab45f14 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -1189,7 +1189,7 @@ pins {
};
qspi_bk1_pins_a: qspi-bk1-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
@@ -1198,12 +1198,6 @@ pins1 {
drive-push-pull;
slew-rate = <1>;
};
- pins2 {
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
};
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
@@ -1211,13 +1205,12 @@ pins {
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
- <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
};
};
qspi_bk2_pins_a: qspi-bk2-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
@@ -1226,7 +1219,34 @@ pins1 {
drive-push-pull;
slew-rate = <1>;
};
- pins2 {
+ };
+
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ qspi_cs2_pins_a: qspi-cs2-0 {
+ pins {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
@@ -1234,13 +1254,9 @@ pins2 {
};
};
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
- <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
};
};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index d142dd30e16b..050c3c27a420 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -255,8 +255,16 @@ &m_can1 {
&qspi {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a
+ &qspi_bk2_pins_a
+ &qspi_cs2_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a
+ &qspi_bk2_sleep_pins_a
+ &qspi_cs2_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
From: Patrice Chotard <[email protected]>
Add new property st,dual-flash which allows to use the QSPI interface as a
communication channel using up to 8 qspi line.
This mode can only be used if cs-gpios property is defined.
Signed-off-by: Patrice Chotard <[email protected]>
---
Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
index 6ec6f556182f..5e4f9109799e 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
@@ -46,6 +46,14 @@ properties:
- const: tx
- const: rx
+ st,dual-flash:
+ type: boolean
+ description:
+ Allows to use 8 data lines in case cs-gpios property is defined.
+
+dependencies:
+ st,dual-flash: [ cs-gpios ]
+
required:
- compatible
- reg
--
2.25.1
From: Patrice Chotard <[email protected]>
Add transfer_one_message() spi callback in order to use the QSPI interface
as a communication channel using up to 8 qspi lines (QSPI configured
in dual flash mode).
Signed-off-by: Patrice Chotard <[email protected]>
---
drivers/spi/spi-stm32-qspi.c | 111 ++++++++++++++++++++++++++++++++---
1 file changed, 104 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c
index f3fe92300639..7f2cdcbaf853 100644
--- a/drivers/spi/spi-stm32-qspi.c
+++ b/drivers/spi/spi-stm32-qspi.c
@@ -15,6 +15,7 @@
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
@@ -355,10 +356,10 @@ static int stm32_qspi_get_mode(u8 buswidth)
return buswidth;
}
-static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
+static int stm32_qspi_send(struct spi_device *spi, const struct spi_mem_op *op)
{
- struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
- struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
+ struct stm32_qspi *qspi = spi_controller_get_devdata(spi->master);
+ struct stm32_qspi_flash *flash = &qspi->flash[spi->chip_select];
u32 ccr, cr;
int timeout, err = 0, err_poll_status = 0;
@@ -465,7 +466,7 @@ static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op *
qspi->fmode = CCR_FMODE_APM;
qspi->status_timeout = timeout_ms;
- ret = stm32_qspi_send(mem, op);
+ ret = stm32_qspi_send(mem->spi, op);
mutex_unlock(&qspi->lock);
pm_runtime_mark_last_busy(qspi->dev);
@@ -489,7 +490,7 @@ static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
else
qspi->fmode = CCR_FMODE_INDW;
- ret = stm32_qspi_send(mem, op);
+ ret = stm32_qspi_send(mem->spi, op);
mutex_unlock(&qspi->lock);
pm_runtime_mark_last_busy(qspi->dev);
@@ -545,7 +546,7 @@ static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
else
qspi->fmode = CCR_FMODE_INDR;
- ret = stm32_qspi_send(desc->mem, &op);
+ ret = stm32_qspi_send(desc->mem->spi, &op);
mutex_unlock(&qspi->lock);
pm_runtime_mark_last_busy(qspi->dev);
@@ -554,6 +555,90 @@ static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
return ret ?: len;
}
+static int stm32_qspi_transfer_one_message(struct spi_controller *ctrl,
+ struct spi_message *msg)
+{
+ struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
+ struct spi_transfer *transfer;
+ struct spi_device *spi = msg->spi;
+ struct spi_mem_op op;
+ int ret;
+
+ if (!spi->cs_gpiod)
+ return -EOPNOTSUPP;
+
+ ret = pm_runtime_get_sync(qspi->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(qspi->dev);
+ return ret;
+ }
+
+ mutex_lock(&qspi->lock);
+
+ gpiod_set_value_cansleep(spi->cs_gpiod, true);
+
+ list_for_each_entry(transfer, &msg->transfers, transfer_list) {
+ u8 dummy_bytes = 0;
+
+ memset(&op, 0, sizeof(op));
+
+ dev_dbg(qspi->dev, "tx_buf:%p tx_nbits:%d rx_buf:%p rx_nbits:%d len:%d dummy_data:%d\n",
+ transfer->tx_buf, transfer->tx_nbits,
+ transfer->rx_buf, transfer->rx_nbits,
+ transfer->len, transfer->dummy_data);
+
+ /*
+ * QSPI hardware supports dummy bytes transfer.
+ * If current transfer is dummy byte, merge it with the next
+ * transfer in order to take into account QSPI block constraint
+ */
+ if (transfer->dummy_data) {
+ op.dummy.buswidth = transfer->tx_nbits;
+ op.dummy.nbytes = transfer->len;
+ dummy_bytes = transfer->len;
+
+ /* if happens, means that message is not correctly built */
+ if (list_is_last(&transfer->transfer_list, &msg->transfers))
+ goto end_of_transfer;
+
+ transfer = list_next_entry(transfer, transfer_list);
+ }
+
+ op.data.nbytes = transfer->len;
+
+ if (transfer->rx_buf) {
+ qspi->fmode = CCR_FMODE_INDR;
+ op.data.buswidth = transfer->rx_nbits;
+ op.data.dir = SPI_MEM_DATA_IN;
+ op.data.buf.in = transfer->rx_buf;
+ } else {
+ qspi->fmode = CCR_FMODE_INDW;
+ op.data.buswidth = transfer->tx_nbits;
+ op.data.dir = SPI_MEM_DATA_OUT;
+ op.data.buf.out = transfer->tx_buf;
+ }
+
+ ret = stm32_qspi_send(spi, &op);
+ if (ret)
+ goto end_of_transfer;
+
+ msg->actual_length += transfer->len + dummy_bytes;
+ }
+
+end_of_transfer:
+ gpiod_set_value_cansleep(spi->cs_gpiod, false);
+
+ mutex_unlock(&qspi->lock);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
+
+ msg->status = ret;
+ spi_finalize_current_message(ctrl);
+
+ return ret;
+}
+
static int stm32_qspi_setup(struct spi_device *spi)
{
struct spi_controller *ctrl = spi->master;
@@ -579,7 +664,7 @@ static int stm32_qspi_setup(struct spi_device *spi)
flash->presc = presc;
mutex_lock(&qspi->lock);
- qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
+ qspi->cr_reg |= CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
/* set dcr fsize to max address */
@@ -741,11 +826,23 @@ static int stm32_qspi_probe(struct platform_device *pdev)
mutex_init(&qspi->lock);
+ /*
+ * Dual flash mode is only enable in case "st,dual-flash" and
+ * "cs-gpios" properties are found in DT
+ */
+ if (of_property_read_bool(dev->of_node, "st,dual-flash") &&
+ of_gpio_named_count(dev->of_node, "cs-gpios")) {
+ qspi->cr_reg = CR_DFM;
+ dev_dbg(dev, "Dual flash mode enable");
+ }
+
ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
| SPI_TX_DUAL | SPI_TX_QUAD;
ctrl->setup = stm32_qspi_setup;
ctrl->bus_num = -1;
ctrl->mem_ops = &stm32_qspi_mem_ops;
+ ctrl->use_gpio_descriptors = true;
+ ctrl->transfer_one_message = stm32_qspi_transfer_one_message;
ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
ctrl->dev.of_node = dev->of_node;
--
2.25.1
On 08/08/2022 10:40, [email protected] wrote:
> From: Patrice Chotard <[email protected]>
>
> Add new property st,dual-flash which allows to use the QSPI interface as a
> communication channel using up to 8 qspi line.
> This mode can only be used if cs-gpios property is defined.
>
> Signed-off-by: Patrice Chotard <[email protected]>
> ---
> Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
> index 6ec6f556182f..5e4f9109799e 100644
> --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
> @@ -46,6 +46,14 @@ properties:
> - const: tx
> - const: rx
>
> + st,dual-flash:
> + type: boolean
> + description:
> + Allows to use 8 data lines in case cs-gpios property is defined.
It's named dual-flash, but what if you want to use QSPI to connect for
example to FPGA?
Also how is this related to parallel-memories property?
Best regards,
Krzysztof
On Mon, Aug 08, 2022 at 09:40:50AM +0200, [email protected] wrote:
> + ret = pm_runtime_get_sync(qspi->dev);
> + if (ret < 0) {
> + pm_runtime_put_noidle(qspi->dev);
> + return ret;
> + }
Use the core runtime PM, there should be no need to open code.
Hi Krzystof
On 8/8/22 11:01, Krzysztof Kozlowski wrote:
> On 08/08/2022 10:40, [email protected] wrote:
>> From: Patrice Chotard <[email protected]>
>>
>> Add new property st,dual-flash which allows to use the QSPI interface as a
>> communication channel using up to 8 qspi line.
>> This mode can only be used if cs-gpios property is defined.
>>
>> Signed-off-by: Patrice Chotard <[email protected]>
>> ---
>> Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>> index 6ec6f556182f..5e4f9109799e 100644
>> --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>> @@ -46,6 +46,14 @@ properties:
>> - const: tx
>> - const: rx
>>
>> + st,dual-flash:
>> + type: boolean
>> + description:
>> + Allows to use 8 data lines in case cs-gpios property is defined.
>
> It's named dual-flash, but what if you want to use QSPI to connect for
> example to FPGA?
>
> Also how is this related to parallel-memories property?
I called it "dual-flash" simply because it enable the dual flash feature of the QSPI block (bit CR_DFM : Dual Flash Mode)
which allows to use the 8 lines simultaneously of our dual QSPI block.
Best regards
Patrice
>
> Best regards,
> Krzysztof
On Mon, Aug 08, 2022 at 06:09:51PM +0200, Patrice CHOTARD wrote:
> On 8/8/22 15:29, Mark Brown wrote:
> > On Mon, Aug 08, 2022 at 09:40:50AM +0200, [email protected] wrote:
> >> + ret = pm_runtime_get_sync(qspi->dev);
> >> + if (ret < 0) {
> >> + pm_runtime_put_noidle(qspi->dev);
> >> + return ret;
> >> + }
> > Use the core runtime PM, there should be no need to open code.
> Right, i will use pm_runtime_resume_and_get() instead.
There's also core SPI support for calling this - set auto_runtime_pm.
Hi Mark
On 8/8/22 15:29, Mark Brown wrote:
> On Mon, Aug 08, 2022 at 09:40:50AM +0200, [email protected] wrote:
>
>> + ret = pm_runtime_get_sync(qspi->dev);
>> + if (ret < 0) {
>> + pm_runtime_put_noidle(qspi->dev);
>> + return ret;
>> + }
>
> Use the core runtime PM, there should be no need to open code.
Right, i will use pm_runtime_resume_and_get() instead.
Thanks
Patrice
On 08/08/2022 19:08, Patrice CHOTARD wrote:
> Hi Krzystof
>
> On 8/8/22 11:01, Krzysztof Kozlowski wrote:
>> On 08/08/2022 10:40, [email protected] wrote:
>>> From: Patrice Chotard <[email protected]>
>>>
>>> Add new property st,dual-flash which allows to use the QSPI interface as a
>>> communication channel using up to 8 qspi line.
>>> This mode can only be used if cs-gpios property is defined.
>>>
>>> Signed-off-by: Patrice Chotard <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>> index 6ec6f556182f..5e4f9109799e 100644
>>> --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>> @@ -46,6 +46,14 @@ properties:
>>> - const: tx
>>> - const: rx
>>>
>>> + st,dual-flash:
>>> + type: boolean
>>> + description:
>>> + Allows to use 8 data lines in case cs-gpios property is defined.
>>
>> It's named dual-flash, but what if you want to use QSPI to connect for
>> example to FPGA?
>>
>> Also how is this related to parallel-memories property?
>
> I called it "dual-flash" simply because it enable the dual flash feature of the QSPI block (bit CR_DFM : Dual Flash Mode)
> which allows to use the 8 lines simultaneously of our dual QSPI block.
And how is it related to existing parallel-memories property?
Best regards,
Krzysztof
On 09/08/2022 07:18, Krzysztof Kozlowski wrote:
> On 08/08/2022 19:08, Patrice CHOTARD wrote:
>> Hi Krzystof
>>
>> On 8/8/22 11:01, Krzysztof Kozlowski wrote:
>>> On 08/08/2022 10:40, [email protected] wrote:
>>>> From: Patrice Chotard <[email protected]>
>>>>
>>>> Add new property st,dual-flash which allows to use the QSPI interface as a
>>>> communication channel using up to 8 qspi line.
>>>> This mode can only be used if cs-gpios property is defined.
>>>>
>>>> Signed-off-by: Patrice Chotard <[email protected]>
>>>> ---
>>>> Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++
>>>> 1 file changed, 8 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>> index 6ec6f556182f..5e4f9109799e 100644
>>>> --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>> @@ -46,6 +46,14 @@ properties:
>>>> - const: tx
>>>> - const: rx
>>>>
>>>> + st,dual-flash:
>>>> + type: boolean
>>>> + description:
>>>> + Allows to use 8 data lines in case cs-gpios property is defined.
>>>
>>> It's named dual-flash, but what if you want to use QSPI to connect for
>>> example to FPGA?
>>>
>>> Also how is this related to parallel-memories property?
>>
>> I called it "dual-flash" simply because it enable the dual flash feature of the QSPI block (bit CR_DFM : Dual Flash Mode)
>> which allows to use the 8 lines simultaneously of our dual QSPI block.
>
> And how is it related to existing parallel-memories property?
Maybe I was not specific enough, so let me rephrase - we have already
parallel-memories property. How this one is different (to justify the
new property)? Is just one memory connected in your case to QSPI over 8
data lines?
Best regards,
Krzysztof
On 09/08/2022 10:52, Patrice CHOTARD wrote:
> Hi Krzystof
>
> On 8/9/22 07:29, Krzysztof Kozlowski wrote:
>> On 09/08/2022 07:18, Krzysztof Kozlowski wrote:
>>> On 08/08/2022 19:08, Patrice CHOTARD wrote:
>>>> Hi Krzystof
>>>>
>>>> On 8/8/22 11:01, Krzysztof Kozlowski wrote:
>>>>> On 08/08/2022 10:40, [email protected] wrote:
>>>>>> From: Patrice Chotard <[email protected]>
>>>>>>
>>>>>> Add new property st,dual-flash which allows to use the QSPI interface as a
>>>>>> communication channel using up to 8 qspi line.
>>>>>> This mode can only be used if cs-gpios property is defined.
>>>>>>
>>>>>> Signed-off-by: Patrice Chotard <[email protected]>
>>>>>> ---
>>>>>> Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++
>>>>>> 1 file changed, 8 insertions(+)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>>> index 6ec6f556182f..5e4f9109799e 100644
>>>>>> --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>>> @@ -46,6 +46,14 @@ properties:
>>>>>> - const: tx
>>>>>> - const: rx
>>>>>>
>>>>>> + st,dual-flash:
>>>>>> + type: boolean
>>>>>> + description:
>>>>>> + Allows to use 8 data lines in case cs-gpios property is defined.
>>>>>
>>>>> It's named dual-flash, but what if you want to use QSPI to connect for
>>>>> example to FPGA?
>>>>>
>>>>> Also how is this related to parallel-memories property?
>>>>
>>>> I called it "dual-flash" simply because it enable the dual flash feature of the QSPI block (bit CR_DFM : Dual Flash Mode)
>>>> which allows to use the 8 lines simultaneously of our dual QSPI block.
>>>
>>> And how is it related to existing parallel-memories property?
>>
>> Maybe I was not specific enough, so let me rephrase - we have already
>> parallel-memories property. How this one is different (to justify the
>> new property)? Is just one memory connected in your case to QSPI over 8
>> data lines?
>
> Our QSPI block is a dual Quad-SPI memory interface, it can managed 2 QSPI flashes independently.
> There is a specific mode, dual flash mode, where the 2 QSPI flashes can be accessed simultaneously
> using 8 data lines. In this case, both throughput and capacity are two fold with this mode.
>
> To illustrate, you can have a look at STM32MP157 reference manual (chapter 27.3.1 figure 172) available here:
> https://www.st.com/resource/en/reference_manual/rm0436-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf
>
> As you mentioned above, the goal is to connect a FPGA to this 8 lines bus.
>
> Hope it clarifies enough ;-)
Only partially. Based on the explanation above, it looks like you want
to use existing parallel-memories property. Please use that one, instead
of adding a new property for the same feature.
Best regards,
Krzysztof
On 8/9/22 09:57, Krzysztof Kozlowski wrote:
> On 09/08/2022 10:52, Patrice CHOTARD wrote:
>> Hi Krzystof
>>
>> On 8/9/22 07:29, Krzysztof Kozlowski wrote:
>>> On 09/08/2022 07:18, Krzysztof Kozlowski wrote:
>>>> On 08/08/2022 19:08, Patrice CHOTARD wrote:
>>>>> Hi Krzystof
>>>>>
>>>>> On 8/8/22 11:01, Krzysztof Kozlowski wrote:
>>>>>> On 08/08/2022 10:40, [email protected] wrote:
>>>>>>> From: Patrice Chotard <[email protected]>
>>>>>>>
>>>>>>> Add new property st,dual-flash which allows to use the QSPI interface as a
>>>>>>> communication channel using up to 8 qspi line.
>>>>>>> This mode can only be used if cs-gpios property is defined.
>>>>>>>
>>>>>>> Signed-off-by: Patrice Chotard <[email protected]>
>>>>>>> ---
>>>>>>> Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++
>>>>>>> 1 file changed, 8 insertions(+)
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>>>> index 6ec6f556182f..5e4f9109799e 100644
>>>>>>> --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>>>> +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>>>> @@ -46,6 +46,14 @@ properties:
>>>>>>> - const: tx
>>>>>>> - const: rx
>>>>>>>
>>>>>>> + st,dual-flash:
>>>>>>> + type: boolean
>>>>>>> + description:
>>>>>>> + Allows to use 8 data lines in case cs-gpios property is defined.
>>>>>>
>>>>>> It's named dual-flash, but what if you want to use QSPI to connect for
>>>>>> example to FPGA?
>>>>>>
>>>>>> Also how is this related to parallel-memories property?
>>>>>
>>>>> I called it "dual-flash" simply because it enable the dual flash feature of the QSPI block (bit CR_DFM : Dual Flash Mode)
>>>>> which allows to use the 8 lines simultaneously of our dual QSPI block.
>>>>
>>>> And how is it related to existing parallel-memories property?
>>>
>>> Maybe I was not specific enough, so let me rephrase - we have already
>>> parallel-memories property. How this one is different (to justify the
>>> new property)? Is just one memory connected in your case to QSPI over 8
>>> data lines?
>>
>> Our QSPI block is a dual Quad-SPI memory interface, it can managed 2 QSPI flashes independently.
>> There is a specific mode, dual flash mode, where the 2 QSPI flashes can be accessed simultaneously
>> using 8 data lines. In this case, both throughput and capacity are two fold with this mode.
>>
>> To illustrate, you can have a look at STM32MP157 reference manual (chapter 27.3.1 figure 172) available here:
>> https://www.st.com/resource/en/reference_manual/rm0436-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf
>>
>> As you mentioned above, the goal is to connect a FPGA to this 8 lines bus.
>>
>> Hope it clarifies enough ;-)
>
> Only partially. Based on the explanation above, it looks like you want
> to use existing parallel-memories property. Please use that one, instead
> of adding a new property for the same feature.
Okay, got it, i didn't notice the parallel-memories property recently added.
Thanks for pointing it.
Patrice
>
> Best regards,
> Krzysztof
Hi Krzystof
On 8/9/22 07:29, Krzysztof Kozlowski wrote:
> On 09/08/2022 07:18, Krzysztof Kozlowski wrote:
>> On 08/08/2022 19:08, Patrice CHOTARD wrote:
>>> Hi Krzystof
>>>
>>> On 8/8/22 11:01, Krzysztof Kozlowski wrote:
>>>> On 08/08/2022 10:40, [email protected] wrote:
>>>>> From: Patrice Chotard <[email protected]>
>>>>>
>>>>> Add new property st,dual-flash which allows to use the QSPI interface as a
>>>>> communication channel using up to 8 qspi line.
>>>>> This mode can only be used if cs-gpios property is defined.
>>>>>
>>>>> Signed-off-by: Patrice Chotard <[email protected]>
>>>>> ---
>>>>> Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++
>>>>> 1 file changed, 8 insertions(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>> index 6ec6f556182f..5e4f9109799e 100644
>>>>> --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>> +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
>>>>> @@ -46,6 +46,14 @@ properties:
>>>>> - const: tx
>>>>> - const: rx
>>>>>
>>>>> + st,dual-flash:
>>>>> + type: boolean
>>>>> + description:
>>>>> + Allows to use 8 data lines in case cs-gpios property is defined.
>>>>
>>>> It's named dual-flash, but what if you want to use QSPI to connect for
>>>> example to FPGA?
>>>>
>>>> Also how is this related to parallel-memories property?
>>>
>>> I called it "dual-flash" simply because it enable the dual flash feature of the QSPI block (bit CR_DFM : Dual Flash Mode)
>>> which allows to use the 8 lines simultaneously of our dual QSPI block.
>>
>> And how is it related to existing parallel-memories property?
>
> Maybe I was not specific enough, so let me rephrase - we have already
> parallel-memories property. How this one is different (to justify the
> new property)? Is just one memory connected in your case to QSPI over 8
> data lines?
Our QSPI block is a dual Quad-SPI memory interface, it can managed 2 QSPI flashes independently.
There is a specific mode, dual flash mode, where the 2 QSPI flashes can be accessed simultaneously
using 8 data lines. In this case, both throughput and capacity are two fold with this mode.
To illustrate, you can have a look at STM32MP157 reference manual (chapter 27.3.1 figure 172) available here:
https://www.st.com/resource/en/reference_manual/rm0436-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf
As you mentioned above, the goal is to connect a FPGA to this 8 lines bus.
Hope it clarifies enough ;-)
Thanks
Patrice
>
> Best regards,
> Krzysztof