From: Conor Dooley <[email protected]>
Hey,
Ever since RISC-V starting using generic arch topology code, the code
paths for cpu-capacity have been there but there's no binding defined to
actually convey the information. Defining the same property as used on
arm seems to be the only logical thing to do, so do it.
It's worth noting that right now, actually putting this property in a DT
will cause allocation failures on RISC-V - but there's already a patch
for that thanks to Ley Foon Tan:
https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/
Thanks,
Conor.
CC: Ley Foon Tan <[email protected]>
CC: Sudeep Holla <[email protected]>
CC: Palmer Dabbelt <[email protected]>
CC: Conor Dooley <[email protected]>
CC: Rob Herring <[email protected]>
CC: Krzysztof Kozlowski <[email protected]>
CC: Jonathan Corbet <[email protected]>
CC: Alex Shi <[email protected]>
CC: Yanteng Si <[email protected]>
CC: Lorenzo Pieralisi <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
Conor Dooley (2):
dt-bindings: arm: move cpu-capacity to a shared loation
dt-bindings: riscv: add a capacity-dmips-mhz cpu property
Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
.../devicetree/bindings/{arm => cpu}/cpu-capacity.txt | 4 ++--
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
Documentation/scheduler/sched-capacity.rst | 2 +-
.../translations/zh_CN/scheduler/sched-capacity.rst | 2 +-
5 files changed, 11 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{arm => cpu}/cpu-capacity.txt (98%)
--
2.39.0
From: Conor Dooley <[email protected]>
Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
RISC-V has used the generic arch topology code, which provides for
disparate CPU capacities. We never defined a binding to acquire this
information from the DT though, so document the one already used by the
generic arch topology code: "capacity-dmips-mhz".
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6720764e765..2480c2460759 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -114,6 +114,12 @@ properties:
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).
+ capacity-dmips-mhz:
+ description:
+ u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
+ DMIPS/MHz, relative to highest capacity-dmips-mhz
+ in the system.
+
required:
- riscv,isa
- interrupt-controller
--
2.39.0
From: Conor Dooley <[email protected]>
RISC-V uses the same generic topology code as arm64 & while there
currently exists no binding for cpu-capacity on RISC-V, the code paths
can be hit if the property is present.
Move the documentation of cpu-capacity to a shared location, ahead of
defining a binding for capacity-dmips-mhz on RISC-V. Update some
references to this document in the process.
Signed-off-by: Conor Dooley <[email protected]>
---
I wasn't sure what to do with reference [1], but since the property will
be the same on RISC-V, I left it as is.
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
.../devicetree/bindings/{arm => cpu}/cpu-capacity.txt | 4 ++--
Documentation/scheduler/sched-capacity.rst | 2 +-
Documentation/translations/zh_CN/scheduler/sched-capacity.rst | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{arm => cpu}/cpu-capacity.txt (98%)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 01b5a9c689a2..a7586295a6f5 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -257,7 +257,7 @@ properties:
capacity-dmips-mhz:
description:
- u32 value representing CPU capacity (see ./cpu-capacity.txt) in
+ u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt
similarity index 98%
rename from Documentation/devicetree/bindings/arm/cpu-capacity.txt
rename to Documentation/devicetree/bindings/cpu/cpu-capacity.txt
index cc5e190390b7..f28e1adad428 100644
--- a/Documentation/devicetree/bindings/arm/cpu-capacity.txt
+++ b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt
@@ -1,12 +1,12 @@
==========================================
-ARM CPUs capacity bindings
+CPU capacity bindings
==========================================
==========================================
1 - Introduction
==========================================
-ARM systems may be configured to have cpus with different power/performance
+Some systems may be configured to have cpus with different power/performance
characteristics within the same chip. In this case, additional information has
to be made available to the kernel for it to be aware of such differences and
take decisions accordingly.
diff --git a/Documentation/scheduler/sched-capacity.rst b/Documentation/scheduler/sched-capacity.rst
index 805f85f330b5..8e2b8538bc2b 100644
--- a/Documentation/scheduler/sched-capacity.rst
+++ b/Documentation/scheduler/sched-capacity.rst
@@ -260,7 +260,7 @@ for that purpose.
The arm and arm64 architectures directly map this to the arch_topology driver
CPU scaling data, which is derived from the capacity-dmips-mhz CPU binding; see
-Documentation/devicetree/bindings/arm/cpu-capacity.txt.
+Documentation/devicetree/bindings/cpu/cpu-capacity.txt.
3.2 Frequency invariance
------------------------
diff --git a/Documentation/translations/zh_CN/scheduler/sched-capacity.rst b/Documentation/translations/zh_CN/scheduler/sched-capacity.rst
index 3a52053c29dc..e07ffdd391d3 100644
--- a/Documentation/translations/zh_CN/scheduler/sched-capacity.rst
+++ b/Documentation/translations/zh_CN/scheduler/sched-capacity.rst
@@ -233,7 +233,7 @@ CFS调度类基于实体负载跟踪机制（Per-Entity Load Tracking, PELT）
arm和arm64架构直接把这个信息映射到arch_topology驱动的CPU scaling数据中（译注：参考
arch_topology.h的percpu变量cpu_scale），它是从capacity-dmips-mhz CPU binding中衍生计算
-出来的。参见Documentation/devicetree/bindings/arm/cpu-capacity.txt。
+出来的。参见Documentation/devicetree/bindings/cpu/cpu-capacity.txt。
3.2 频率不变性
--------------
--
2.39.0
>
> From: Conor Dooley <[email protected]>
>
> RISC-V uses the same generic topology code as arm64 & while there
> currently exists no binding for cpu-capacity on RISC-V, the code paths can be
> hit if the property is present.
>
> Move the documentation of cpu-capacity to a shared location, ahead of
> defining a binding for capacity-dmips-mhz on RISC-V. Update some
> references to this document in the process.
>
> Signed-off-by: Conor Dooley <[email protected]>
Hi Conor
I plan to move cpu-capacity.txt binding to generic directory as well after [1]. Thanks for your patch series helping this.
[1] https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/
Reviewed-by: Ley Foon Tan <[email protected]>
Regards
Ley Foon
> -----Original Message-----
>
> From: Conor Dooley <[email protected]>
>
> Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") RISC-
> V has used the generic arch topology code, which provides for disparate CPU
> capacities. We never defined a binding to acquire this information from the
> DT though, so document the one already used by the generic arch topology
> code: "capacity-dmips-mhz".
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
> b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index c6720764e765..2480c2460759 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -114,6 +114,12 @@ properties:
> List of phandles to idle state nodes supported
> by this hart (see ./idle-states.yaml).
>
> + capacity-dmips-mhz:
> + description:
> + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
> + DMIPS/MHz, relative to highest capacity-dmips-mhz
> + in the system.
> +
> required:
> - riscv,isa
> - interrupt-controller
> --
> 2.39.0
Thanks Conor.
Reviewed-by: Ley Foon Tan <[email protected]>
Regards
Ley Foon
On Wed, 04 Jan 2023 18:05:13 +0000, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> RISC-V uses the same generic topology code as arm64 & while there
> currently exists no binding for cpu-capacity on RISC-V, the code paths
> can be hit if the property is present.
>
> Move the documentation of cpu-capacity to a shared location, ahead of
> defining a binding for capacity-dmips-mhz on RISC-V. Update some
> references to this document in the process.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> I wasn't sure what to do with reference [1], but since the property will
> be the same on RISC-V, I left it as is.
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
> .../devicetree/bindings/{arm => cpu}/cpu-capacity.txt | 4 ++--
> Documentation/scheduler/sched-capacity.rst | 2 +-
> Documentation/translations/zh_CN/scheduler/sched-capacity.rst | 2 +-
> 4 files changed, 5 insertions(+), 5 deletions(-)
> rename Documentation/devicetree/bindings/{arm => cpu}/cpu-capacity.txt (98%)
>
Acked-by: Rob Herring <[email protected]>
On Wed, 04 Jan 2023 18:05:14 +0000, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
> RISC-V has used the generic arch topology code, which provides for
> disparate CPU capacities. We never defined a binding to acquire this
> information from the DT though, so document the one already used by the
> generic arch topology code: "capacity-dmips-mhz".
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
在 1/5/23 02:05, Conor Dooley 写道:
> From: Conor Dooley <[email protected]>
>
> RISC-V uses the same generic topology code as arm64 & while there
> currently exists no binding for cpu-capacity on RISC-V, the code paths
> can be hit if the property is present.
>
> Move the documentation of cpu-capacity to a shared location, ahead of
> defining a binding for capacity-dmips-mhz on RISC-V. Update some
> references to this document in the process.
>
> Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Yanteng Si <[email protected]>
> ---
> I wasn't sure what to do with reference [1], but since the property will
> be the same on RISC-V, I left it as is.
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
> .../devicetree/bindings/{arm => cpu}/cpu-capacity.txt | 4 ++--
> Documentation/scheduler/sched-capacity.rst | 2 +-
> Documentation/translations/zh_CN/scheduler/sched-capacity.rst | 2 +-
> 4 files changed, 5 insertions(+), 5 deletions(-)
> rename Documentation/devicetree/bindings/{arm => cpu}/cpu-capacity.txt (98%)
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index 01b5a9c689a2..a7586295a6f5 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -257,7 +257,7 @@ properties:
>
> capacity-dmips-mhz:
> description:
> - u32 value representing CPU capacity (see ./cpu-capacity.txt) in
> + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
> DMIPS/MHz, relative to highest capacity-dmips-mhz
> in the system.
>
> diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt
> similarity index 98%
> rename from Documentation/devicetree/bindings/arm/cpu-capacity.txt
> rename to Documentation/devicetree/bindings/cpu/cpu-capacity.txt
> index cc5e190390b7..f28e1adad428 100644
> --- a/Documentation/devicetree/bindings/arm/cpu-capacity.txt
> +++ b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt
> @@ -1,12 +1,12 @@
> ==========================================
> -ARM CPUs capacity bindings
> +CPU capacity bindings
> ==========================================
>
> ==========================================
> 1 - Introduction
> ==========================================
>
> -ARM systems may be configured to have cpus with different power/performance
> +Some systems may be configured to have cpus with different power/performance
> characteristics within the same chip. In this case, additional information has
> to be made available to the kernel for it to be aware of such differences and
> take decisions accordingly.
> diff --git a/Documentation/scheduler/sched-capacity.rst b/Documentation/scheduler/sched-capacity.rst
> index 805f85f330b5..8e2b8538bc2b 100644
> --- a/Documentation/scheduler/sched-capacity.rst
> +++ b/Documentation/scheduler/sched-capacity.rst
> @@ -260,7 +260,7 @@ for that purpose.
>
> The arm and arm64 architectures directly map this to the arch_topology driver
> CPU scaling data, which is derived from the capacity-dmips-mhz CPU binding; see
> -Documentation/devicetree/bindings/arm/cpu-capacity.txt.
> +Documentation/devicetree/bindings/cpu/cpu-capacity.txt.
>
> 3.2 Frequency invariance
> ------------------------
> diff --git a/Documentation/translations/zh_CN/scheduler/sched-capacity.rst b/Documentation/translations/zh_CN/scheduler/sched-capacity.rst
> index 3a52053c29dc..e07ffdd391d3 100644
> --- a/Documentation/translations/zh_CN/scheduler/sched-capacity.rst
> +++ b/Documentation/translations/zh_CN/scheduler/sched-capacity.rst
> @@ -233,7 +233,7 @@ CFS调度类基于实体负载跟踪机制（Per-Entity Load Tracking, PELT）
>
> arm和arm64架构直接把这个信息映射到arch_topology驱动的CPU scaling数据中（译注：参考
> arch_topology.h的percpu变量cpu_scale），它是从capacity-dmips-mhz CPU binding中衍生计算
> -出来的。参见Documentation/devicetree/bindings/arm/cpu-capacity.txt。
> +出来的。参见Documentation/devicetree/bindings/cpu/cpu-capacity.txt。
>
> 3.2 频率不变性
> --------------
On Wed, 4 Jan 2023 18:05:12 +0000, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Hey,
>
> Ever since RISC-V starting using generic arch topology code, the code
> paths for cpu-capacity have been there but there's no binding defined to
> actually convey the information. Defining the same property as used on
> arm seems to be the only logical thing to do, so do it.
>
> [...]
Applied, thanks!
[1/2] dt-bindings: arm: move cpu-capacity to a shared loation
https://git.kernel.org/palmer/c/7d2078310cbf
[2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu property
https://git.kernel.org/palmer/c/991994509ee9
Best regards,
--
Palmer Dabbelt <[email protected]>
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:
On Wed, 4 Jan 2023 18:05:12 +0000 you wrote:
> From: Conor Dooley <[email protected]>
>
> Hey,
>
> Ever since RISC-V starting using generic arch topology code, the code
> paths for cpu-capacity have been there but there's no binding defined to
> actually convey the information. Defining the same property as used on
> arm seems to be the only logical thing to do, so do it.
>
> [...]
Here is the summary with links:
- [v1,1/2] dt-bindings: arm: move cpu-capacity to a shared loation
https://git.kernel.org/riscv/c/7d2078310cbf
- [v1,2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu property
https://git.kernel.org/riscv/c/991994509ee9
You are awesome, thank you!
--
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https://korg.docs.kernel.org/patchwork/pwbot.html