The following series of patches add support for the following
on J721S2 common processor board,
- USB
- SerDes
- OSPI
- PCIe
Changes from v1:
* Resolve issues with dt schema reporting
* Minor changes related to consistency on node naming and value
Changes from v2:
* Added PCIe RC + EP enablement patchsets
* Added device-id for j722s2 PCIe host in dt documentation
* Reworked SERDES + WIZ enablement patchset to use properies for clocks
defines versus entire devicetree nodes. Results in cleaner code that
doesn't break dt-schema or the driver functionality.
Changes from v3:
* Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes'
* Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and
send it own series to avoid a dependency that would hold up other patches in this
series
Changes from v4:
* Add my Signed-off-by lines to all patchsets
Changes from v5:
* Removed Cc from commit messages to reduce clutter
* Squashed changes for device tree nodes that get modified latter in the patchset
series
Changes from v6:
* Changes to ti,j721s2-wiz-10g compatible string from ti,am64-wiz-10g but
requires this series to be merged first
Ref: https://lore.kernel.org/linux-arm-kernel/[email protected]/
* Removed unused pcie1_ep based on feedback
* Switch from incorrect "ti,j721e-system-controller", "syscon", "simple-mfd" compatible for
SPI node to "simple-bus"
Changes from v7:
* Fix node names as per bindings document
Changes from v8:
* Update the ti,j721e-system-controller bindings document
* Fix dtbs warnings
Changes from v9:
* Disable nodes in main.dtsi and enable them in the board
specific DT file
Aswath Govindraju (7):
arm64: dts: ti: k3-j721s2-main: Add support for USB
arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
Matt Ranostay (1):
arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
Ravi Gunasekaran (1):
dt-bindings: mfd: ti,j721e-system-controller: Fix mux node regex
.../mfd/ti,j721e-system-controller.yaml | 8 +-
.../dts/ti/k3-j721s2-common-proc-board.dts | 98 ++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 147 ++++++++++++++++++
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 47 ++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 43 +++++
5 files changed, 342 insertions(+), 1 deletion(-)
--
2.17.1
From: Aswath Govindraju <[email protected]>
Add support for single instance of USB 3.0 controller in J721S2 SoC.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
I had reviewed this patch in the v5 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
Links:
[1] - https://lore.kernel.org/all/[email protected]/
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 46 ++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 8915132efcc1..84e5689fff9f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -26,6 +26,20 @@
};
};
+ scm_conf: syscon@104000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00104000 0x00 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00104000 0x18000>;
+
+ usb_serdes_mux: mux-controller@0 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -745,6 +759,38 @@
};
};
+ usbss0: cdns-usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x04104000 0x00 0x100>;
+ clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 360 17>;
+ power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+
+ status = "disabled";
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x06000000 0x00 0x10000>,
+ <0x00 0x06010000 0x00 0x10000>,
+ <0x00 0x06020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+
+ status = "disabled";
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.17.1
From: Aswath Govindraju <[email protected]>
Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
I had reviewed this patch in the v5 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
Links:
[1] - https://lore.kernel.org/all/[email protected]/
.../dts/ti/k3-j721s2-common-proc-board.dts | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index a7aa6cf08acd..907f34ff22a5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -9,6 +9,9 @@
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
@@ -296,6 +299,30 @@
phy-handle = <&phy0>;
};
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+ <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.17.1
From: Aswath Govindraju <[email protected]>
Add PCIe1 RC device tree node for the single PCIe instance present on
the j721s2.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index af6c93f0a055..c3ca8a016793 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -849,6 +849,49 @@
};
};
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 41>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb013>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
+ <0 0 0 2 &pcie1_intc 0>, /* INT B */
+ <0 0 0 3 &pcie1_intc 0>, /* INT C */
+ <0 0 0 4 &pcie1_intc 0>; /* INT D */
+
+ status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.17.1
From: Aswath Govindraju <[email protected]>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 76b420379645..b195f250891a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -386,6 +386,14 @@
};
};
+&pcie1_rc {
+ status = "okay";
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.17.1
From: Aswath Govindraju <[email protected]>
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Reviewed-by: Vaishnav Achath <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 39 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 43 +++++++++++++++++++
2 files changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index fa38940fe6cd..76b420379645 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -206,6 +206,20 @@
J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
>;
};
+
+ mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
+ J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
+ J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
+ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
+ J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
+ J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
+ >;
+ };
};
&main_gpio2 {
@@ -347,6 +361,31 @@
maximum-speed = "high-speed";
};
+&fss {
+ status = "okay";
+};
+
+&ospi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 6930efff8a5a..9fe255f0576e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -39,6 +39,28 @@
};
};
+&wkup_pmx0 {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
+ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
+ J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
+ J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
+ J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
+ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
+ J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
+ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
+ >;
+ };
+};
+
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
@@ -79,3 +101,24 @@
pinctrl-names = "default";
phys = <&transceiver0>;
};
+
+&ospi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
--
2.17.1
mux-controller nodes may not have "reg" property. Update the regex
for such nodes to resolve the dtbs warnings
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
.../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index 76ef4352e13c..532bfa45e6a0 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -45,7 +45,7 @@ properties:
patternProperties:
# Optional children
- "^mux-controller@[0-9a-f]+$":
+ "^mux-controller(@|-)[0-9a-f]+$":
type: object
description:
This is the SERDES lane control mux.
@@ -94,6 +94,12 @@ examples:
/* SERDES4 lane0/1/2/3 select */
};
+ usb_serdes_mux: mux-controller-80 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>;
+ };
+
clock-controller@4140 {
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
reg = <0x4140 0x18>;
--
2.17.1
From: Aswath Govindraju <[email protected]>
The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that up to 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
I had reviewed this patch in the v5 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
Links:
[1] - https://lore.kernel.org/all/[email protected]/
.../dts/ti/k3-j721s2-common-proc-board.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 907f34ff22a5..fa38940fe6cd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -147,6 +147,12 @@
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
&wkup_pmx0 {
@@ -323,6 +329,24 @@
};
};
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.17.1
From: Matt Ranostay <[email protected]>
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Matt Ranostay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
I had reviewed this patch in the v7 series [1].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
Links:
[1] - https://lore.kernel.org/lkml/[email protected]/
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 60 +++++++++++++++++++++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 84e5689fff9f..af6c93f0a055 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -33,11 +44,18 @@
#size-cells = <1>;
ranges = <0x00 0x00 0x00104000 0x18000>;
- usb_serdes_mux: mux-controller@0 {
+ usb_serdes_mux: mux-controller-0 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
+
+ serdes_ln_ctrl: mux-controller-80 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
};
gic500: interrupt-controller@1800000 {
@@ -791,6 +809,46 @@
};
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721s2-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ status = "disabled";
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 365 3>,
+ <&k3_clks 365 3>,
+ <&k3_clks 365 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.17.1
On 17:36-20230221, Ravi Gunasekaran wrote:
> mux-controller nodes may not have "reg" property. Update the regex
> for such nodes to resolve the dtbs warnings
>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> .../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Are you expecting for me to pick this up? Looks like something
Lee Jones needs to pick up? He is'nt in the CC either?
If Lee Jones is willing to give me an immutable tag, I can pick the same
up and pick up dependent patches. Else, please split the series for each
of the maintainers to pick up without dependency.
>
> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> index 76ef4352e13c..532bfa45e6a0 100644
> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> @@ -45,7 +45,7 @@ properties:
>
> patternProperties:
> # Optional children
> - "^mux-controller@[0-9a-f]+$":
> + "^mux-controller(@|-)[0-9a-f]+$":
> type: object
> description:
> This is the SERDES lane control mux.
> @@ -94,6 +94,12 @@ examples:
> /* SERDES4 lane0/1/2/3 select */
> };
>
> + usb_serdes_mux: mux-controller-80 {
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x0 0x8000000>;
> + };
> +
> clock-controller@4140 {
> compatible = "ti,am654-ehrpwm-tbclk", "syscon";
> reg = <0x4140 0x18>;
> --
> 2.17.1
>
From: Aswath Govindraju <[email protected]>
Add support for two instance of OSPI in J721S2 SoC.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Reviewed-by: Vaishnav Achath <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 0af242aa9816..7e0e608578e1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -306,4 +306,51 @@
ti,cpts-periodic-outputs = <2>;
};
};
+
+ fss: bus@47000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ status = "disabled";
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x07 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ };
};
--
2.17.1
On 17:36-20230221, Ravi Gunasekaran wrote:
> From: Aswath Govindraju <[email protected]>
>
> Add support for single instance of USB 3.0 controller in J721S2 SoC.
>
> Signed-off-by: Aswath Govindraju <[email protected]>
> Signed-off-by: Matt Ranostay <[email protected]>
> Link: https://lore.kernel.org/r/[email protected]
Is the link supposed to signify some reference we need to keep for ever?
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> I had reviewed this patch in the v5 series [1].
> Since I'm taking over upstreaming this series, I removed the self
> Reviewed-by tag.
>
> Links:
>
> [1] - https://lore.kernel.org/all/[email protected]/
What changed in this rev of the patch?
>
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 46 ++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 8915132efcc1..84e5689fff9f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -26,6 +26,20 @@
> };
> };
>
> + scm_conf: syscon@104000 {
> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
> + reg = <0x00 0x00104000 0x00 0x18000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00 0x00 0x00104000 0x18000>;
> +
> + usb_serdes_mux: mux-controller@0 {
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
> + };
> + };
> +
> gic500: interrupt-controller@1800000 {
> compatible = "arm,gic-v3";
> #address-cells = <2>;
> @@ -745,6 +759,38 @@
> };
> };
>
> + usbss0: cdns-usb@4104000 {
> + compatible = "ti,j721e-usb";
> + reg = <0x00 0x04104000 0x00 0x100>;
> + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
> + clock-names = "ref", "lpm";
> + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
> + assigned-clock-parents = <&k3_clks 360 17>;
> + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-coherent;
> +
> + status = "disabled";
Why disabled by default?
> +
> + usb0: usb@6000000 {
> + compatible = "cdns,usb3";
> + reg = <0x00 0x06000000 0x00 0x10000>,
> + <0x00 0x06010000 0x00 0x10000>,
> + <0x00 0x06020000 0x00 0x10000>;
> + reg-names = "otg", "xhci", "dev";
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "host", "peripheral", "otg";
> + maximum-speed = "super-speed";
> + dr_mode = "otg";
> +
> + status = "disabled";
Why disabled by default?
> + };
> + };
> +
> main_mcan0: can@2701000 {
> compatible = "bosch,m_can";
> reg = <0x00 0x02701000 0x00 0x200>,
> --
> 2.17.1
>
On 21/02/23 5:36 pm, Ravi Gunasekaran wrote:
> mux-controller nodes may not have "reg" property. Update the regex
> for such nodes to resolve the dtbs warnings
>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> .../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> index 76ef4352e13c..532bfa45e6a0 100644
> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> @@ -45,7 +45,7 @@ properties:
>
> patternProperties:
> # Optional children
> - "^mux-controller@[0-9a-f]+$":
> + "^mux-controller(@|-)[0-9a-f]+$":
Hmm. mmio-mux bindings allow reg property. Why can't we add the same to
mux-controller node in 2/9 ?
> type: object
> description:
> This is the SERDES lane control mux.
> @@ -94,6 +94,12 @@ examples:
> /* SERDES4 lane0/1/2/3 select */
> };
>
> + usb_serdes_mux: mux-controller-80 {
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x0 0x8000000>;
> + };
> +
> clock-controller@4140 {
> compatible = "ti,am654-ehrpwm-tbclk", "syscon";
> reg = <0x4140 0x18>;
On 17:36-20230221, Ravi Gunasekaran wrote:
> From: Matt Ranostay <[email protected]>
>
> Add dt node for the single instance of WIZ (SERDES wrapper) and
> SERDES module shared by PCIe, eDP and USB.
[...]
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 84e5689fff9f..af6c93f0a055 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
[...]
> @@ -33,11 +44,18 @@
> #size-cells = <1>;
> ranges = <0x00 0x00 0x00104000 0x18000>;
>
> - usb_serdes_mux: mux-controller@0 {
> + usb_serdes_mux: mux-controller-0 {
was'nt this just introduced in the patch just prior, if so, NAK,
do the changes where they are introduced.
> compatible = "mmio-mux";
> #mux-control-cells = <1>;
> mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
> };
On Tue, Feb 21, 2023 at 8:00 AM Vignesh Raghavendra <[email protected]> wrote:
> On 21/02/23 5:36 pm, Ravi Gunasekaran wrote:
> > mux-controller nodes may not have "reg" property. Update the regex
> > for such nodes to resolve the dtbs warnings
> >
> > Signed-off-by: Ravi Gunasekaran <[email protected]>
> > ---
Where's the change history? I doubt I ignored the last 9 versions...
> > .../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> > index 76ef4352e13c..532bfa45e6a0 100644
> > --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> > @@ -45,7 +45,7 @@ properties:
> >
> > patternProperties:
> > # Optional children
> > - "^mux-controller@[0-9a-f]+$":
> > + "^mux-controller(@|-)[0-9a-f]+$":
>
> Hmm. mmio-mux bindings allow reg property. Why can't we add the same to
> mux-controller node in 2/9 ?
Yes, do that.
Rob
On 21/02/23 7:11 pm, Nishanth Menon wrote:
> On 17:36-20230221, Ravi Gunasekaran wrote:
>> mux-controller nodes may not have "reg" property. Update the regex
>> for such nodes to resolve the dtbs warnings
>>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> .../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>
>
> Are you expecting for me to pick this up? Looks like something
> Lee Jones needs to pick up? He is'nt in the CC either?
>
> If Lee Jones is willing to give me an immutable tag, I can pick the same
> up and pick up dependent patches. Else, please split the series for each
> of the maintainers to pick up without dependency.
>
I apologize for the inconvenience. Based on the other review comments in this series,
I can update the mux node instead of updating the bindings document.
Regardless of it, in future I will take care of sending the patch to the right
maintainer.
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> index 76ef4352e13c..532bfa45e6a0 100644
>> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> @@ -45,7 +45,7 @@ properties:
>>
>> patternProperties:
>> # Optional children
>> - "^mux-controller@[0-9a-f]+$":
>> + "^mux-controller(@|-)[0-9a-f]+$":
>> type: object
>> description:
>> This is the SERDES lane control mux.
>> @@ -94,6 +94,12 @@ examples:
>> /* SERDES4 lane0/1/2/3 select */
>> };
>>
>> + usb_serdes_mux: mux-controller-80 {
>> + compatible = "mmio-mux";
>> + #mux-control-cells = <1>;
>> + mux-reg-masks = <0x0 0x8000000>;
>> + };
>> +
>> clock-controller@4140 {
>> compatible = "ti,am654-ehrpwm-tbclk", "syscon";
>> reg = <0x4140 0x18>;
>> --
>> 2.17.1
>>
--
Regards,
Ravi
On 21/02/23 7:29 pm, Vignesh Raghavendra wrote:
>
>
> On 21/02/23 5:36 pm, Ravi Gunasekaran wrote:
>> mux-controller nodes may not have "reg" property. Update the regex
>> for such nodes to resolve the dtbs warnings
>>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> .../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> index 76ef4352e13c..532bfa45e6a0 100644
>> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> @@ -45,7 +45,7 @@ properties:
>>
>> patternProperties:
>> # Optional children
>> - "^mux-controller@[0-9a-f]+$":
>> + "^mux-controller(@|-)[0-9a-f]+$":
>
> Hmm. mmio-mux bindings allow reg property. Why can't we add the same to
> mux-controller node in 2/9 ?
"reg" property can be added to the mux-controller node.
I will do so in the next series
>
>> type: object
>> description:
>> This is the SERDES lane control mux.
>> @@ -94,6 +94,12 @@ examples:
>> /* SERDES4 lane0/1/2/3 select */
>> };
>>
>> + usb_serdes_mux: mux-controller-80 {
>> + compatible = "mmio-mux";
>> + #mux-control-cells = <1>;
>> + mux-reg-masks = <0x0 0x8000000>;
>> + };
>> +
>> clock-controller@4140 {
>> compatible = "ti,am654-ehrpwm-tbclk", "syscon";
>> reg = <0x4140 0x18>;
--
Regards,
Ravi
On 21/02/23 10:34 pm, Rob Herring wrote:
> On Tue, Feb 21, 2023 at 8:00 AM Vignesh Raghavendra <[email protected]> wrote:
>> On 21/02/23 5:36 pm, Ravi Gunasekaran wrote:
>>> mux-controller nodes may not have "reg" property. Update the regex
>>> for such nodes to resolve the dtbs warnings
>>>
>>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>>> ---
>
> Where's the change history? I doubt I ignored the last 9 versions...
This change was added newly in v8.
But based on the review comments, dtbs warnings can be fixed without
changes to bindings document. So this patch will be dropped in the next
series.
Ravi
>
>>> .../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++-
>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>>> index 76ef4352e13c..532bfa45e6a0 100644
>>> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>>> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>>> @@ -45,7 +45,7 @@ properties:
>>>
>>> patternProperties:
>>> # Optional children
>>> - "^mux-controller@[0-9a-f]+$":
>>> + "^mux-controller(@|-)[0-9a-f]+$":
>>
>> Hmm. mmio-mux bindings allow reg property. Why can't we add the same to
>> mux-controller node in 2/9 ?
>
> Yes, do that.
>
> Rob
On 21/02/23 7:28 pm, Nishanth Menon wrote:
> On 17:36-20230221, Ravi Gunasekaran wrote:
>> From: Aswath Govindraju <[email protected]>
>>
>> Add support for single instance of USB 3.0 controller in J721S2 SoC.
>>
>> Signed-off-by: Aswath Govindraju <[email protected]>
>> Signed-off-by: Matt Ranostay <[email protected]>
>> Link: https://lore.kernel.org/r/[email protected]
>
> Is the link supposed to signify some reference we need to keep for ever?
No. I will remove the reference to the link. I picked up the v7 series from
previous submitter through "b4" and maintained the Link tag as-is since then.
I will remove the reference to the link in the next series.
>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> I had reviewed this patch in the v5 series [1].
>> Since I'm taking over upstreaming this series, I removed the self
>> Reviewed-by tag.
>>
>> Links:
>>
>> [1] - https://lore.kernel.org/all/[email protected]/
>
>
> What changed in this rev of the patch?
Only one change in the patch since v5; Status of the some nodes introduced
in this patch is set to disabled.
>
>>
>> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 46 ++++++++++++++++++++++
>> 1 file changed, 46 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> index 8915132efcc1..84e5689fff9f 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> @@ -26,6 +26,20 @@
>> };
>> };
>>
>> + scm_conf: syscon@104000 {
>> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
>> + reg = <0x00 0x00104000 0x00 0x18000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x00 0x00 0x00104000 0x18000>;
>> +
>> + usb_serdes_mux: mux-controller@0 {
>> + compatible = "mmio-mux";
>> + #mux-control-cells = <1>;
>> + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
>> + };
>> + };
>> +
>> gic500: interrupt-controller@1800000 {
>> compatible = "arm,gic-v3";
>> #address-cells = <2>;
>> @@ -745,6 +759,38 @@
>> };
>> };
>>
>> + usbss0: cdns-usb@4104000 {
>> + compatible = "ti,j721e-usb";
>> + reg = <0x00 0x04104000 0x00 0x100>;
>> + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
>> + clock-names = "ref", "lpm";
>> + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
>> + assigned-clock-parents = <&k3_clks 360 17>;
>> + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + dma-coherent;
>> +
>> + status = "disabled";
>
> Why disabled by default?
One of the comment received in the v9 series was to disable the node in
the include file and then enable it in the board specific DTS file.
Changes in this series addressed that comment.
>
>> +
>> + usb0: usb@6000000 {
>> + compatible = "cdns,usb3";
>> + reg = <0x00 0x06000000 0x00 0x10000>,
>> + <0x00 0x06010000 0x00 0x10000>,
>> + <0x00 0x06020000 0x00 0x10000>;
>> + reg-names = "otg", "xhci", "dev";
>> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "host", "peripheral", "otg";
>> + maximum-speed = "super-speed";
>> + dr_mode = "otg";
>> +
>> + status = "disabled";
>
> Why disabled by default?
See above.
>
>> + };
>> + };
>> +
>> main_mcan0: can@2701000 {
>> compatible = "bosch,m_can";
>> reg = <0x00 0x02701000 0x00 0x200>,
>> --
>> 2.17.1
>>
--
Regards,
Ravi
On 21/02/23 7:31 pm, Nishanth Menon wrote:
> On 17:36-20230221, Ravi Gunasekaran wrote:
>> From: Matt Ranostay <[email protected]>
>>
>> Add dt node for the single instance of WIZ (SERDES wrapper) and
>> SERDES module shared by PCIe, eDP and USB.
>
> [...]
>
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> index 84e5689fff9f..af6c93f0a055 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> [...]
>> @@ -33,11 +44,18 @@
>> #size-cells = <1>;
>> ranges = <0x00 0x00 0x00104000 0x18000>;
>>
>> - usb_serdes_mux: mux-controller@0 {
>> + usb_serdes_mux: mux-controller-0 {
>
> was'nt this just introduced in the patch just prior, if so, NAK,
> do the changes where they are introduced.
Noted. I will fix this.
Thanks for reviewing.
>
>> compatible = "mmio-mux";
>> #mux-control-cells = <1>;
>> mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
>> };
--
Regards,
Ravi
On 10:21-20230222, Ravi Gunasekaran wrote:
[...]
> >> + usbss0: cdns-usb@4104000 {
> >> + compatible = "ti,j721e-usb";
> >> + reg = <0x00 0x04104000 0x00 0x100>;
> >> + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
> >> + clock-names = "ref", "lpm";
> >> + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
> >> + assigned-clock-parents = <&k3_clks 360 17>;
> >> + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + ranges;
> >> + dma-coherent;
> >> +
> >> + status = "disabled";
> >
> > Why disabled by default?
>
> One of the comment received in the v9 series was to disable the node in
> the include file and then enable it in the board specific DTS file.
> Changes in this series addressed that comment.
Document in the node why it is disabled by default. Also do make sure
All K3 SoCs dtsi nodes follow the same argument.
--
Regards,
Nishanth Menon
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