Add subsystem lvds and mipi. Add pwm and i2c in lvds and mipi.
imx8qm-mek:
- add remove-proc
- fixed gpio number error for vmmc
- add usb3 and typec
- add pwm and i2c in lvds and mipi
DTB_CHECK warning fixed by seperate patches.
arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: usb@5b110000: usb@5b120000: 'port', 'usb-role-switch' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml#
arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: usb@5b120000: 'port', 'usb-role-switch' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
** binding fix patch: https://lore.kernel.org/imx/[email protected]/T/#u
arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: interrupt-controller@56240000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
** binding fix patch: https://lore.kernel.org/imx/[email protected]/T/#me3425d580ba9a086866c3053ef854810ac7a0ef6
arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: pwm@56244000: 'oneOf' conditional failed, one must be fixed:
'interrupts' is a required property
'interrupts-extended' is a required property
from schema $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
** binding fix patch: https://lore.kernel.org/imx/[email protected]/T/#t
from schema $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: imx8qm-cm4-0: power-domains: [[15, 278], [15, 297]] is too short
from schema $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: imx8qm-cm4-1: power-domains: [[15, 298], [15, 317]] is too short
** binding fix patch: https://lore.kernel.org/imx/[email protected]/T/#u
Signed-off-by: Frank Li <[email protected]>
---
Frank Li (7):
arm64: dts: imx8qm: add lvds subsystem
arm64: dts: imx8qm: add mipi subsystem
arm64: dts: imx8qm-mek: add cm4 remote-proc and related memory region
arm64: dts: imx8qm-mek: add pwm and i2c in lvds subsystem
arm64: dts: imx8qm-mek: add i2c in mipi[0,1] subsystem
arm64: dts: imx8qm-mek: fix gpio number for reg_usdhc2_vmmc
arm64: dts: imx8qm-mek: add usb 3.0 and related type C nodes
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 308 +++++++++++++++++++++-
arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 231 ++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | 286 ++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +
4 files changed, 826 insertions(+), 1 deletion(-)
---
base-commit: ee78a17615ad0cfdbbc27182b1047cd36c9d4d5f
change-id: 20240606-imx8qm-dts-usb-9c55d2bfe526
Best regards,
---
Frank Li <[email protected]>
Add irqstear, pwm and i2c in mipi subsystem.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | 286 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
2 files changed, 287 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
new file mode 100644
index 0000000000000..bd18468923e52
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2024 NXP
+ */
+
+/ {
+ dsi_ipg_clk: clock-dsi-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "dsi_ipg_clk";
+ };
+
+ mipi_pll_div2_clk: clock-mipi-div2-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <432000000>;
+ clock-output-names = "mipi_pll_div2_clk";
+ };
+
+ mipi0_subsys: bus@56220000 {
+ compatible = "simple-bus";
+ interrupt-parent = <&irqsteer_mipi0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56220000 0x0 0x56220000 0x10000>;
+
+ irqsteer_mipi0: interrupt-controller@56220000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56220000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ };
+
+ mipi0_lis_lpcg: clock-controller@56223000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ mipi0_pwm_lpcg: clock-controller@5622300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi0_pwm_lpcg_clk",
+ "mipi0_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+ };
+
+ mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622302c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ pwm_mipi0: pwm@56224000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x56224000 0x1000>;
+ clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_mipi0: i2c@56226000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56226000 0x1000>;
+ interrupts = <8>;
+ clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
+ <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ status = "disabled";
+ };
+ };
+
+ mipi1_subsys: bus@57220000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x57220000 0x0 0x57220000 0x10000>;
+
+ irqsteer_mipi1: interrupt-controller@57220000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x57220000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ };
+
+ mipi1_lis_lpcg: clock-controller@57223000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ mipi1_pwm_lpcg: clock-controller@5722300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5722300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi1_pwm_lpcg_clk",
+ "mipi1_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ };
+
+ mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5722301c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c0_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223018 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223024 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57223028 0x4>;
+ #clock-cells = <1>;
+ clocks = <&dsi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5722302c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
+ clock-indices = <IMX_LPCG_CLK_0>;
+ clock-output-names = "mipi1_i2c1_lpcg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ pwm_mipi1: pwm@57224000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x57224000 0x1000>;
+ clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_mipi1: i2c@57226000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57226000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&irqsteer_mipi1>;
+ clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
+ <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ status = "disabled";
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 9f29fe4589668..846b95be22bbe 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -577,3 +577,4 @@ clk_spdif1_rx: clock-spdif1-rx {
#include "imx8qm-ss-lsio.dtsi"
#include "imx8qm-ss-audio.dtsi"
#include "imx8qm-ss-lvds.dtsi"
+#include "imx8qm-ss-mipi.dtsi"
--
2.34.1
Add two cm4 remote-proc and related memory regions.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 93 ++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index c024be33fbcce..dbd478af2e474 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -31,6 +31,68 @@ memory@80000000 {
reg = <0x00000000 0x80000000 0 0x40000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ vdev0vring0: memory@90000000 {
+ reg = <0 0x90000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: memory@90008000 {
+ reg = <0 0x90008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: memory@90010000 {
+ reg = <0 0x90010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: memory@90018000 {
+ reg = <0 0x90018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table0: memory@900ff000 {
+ reg = <0 0x900ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: memory {
+ compatible = "shared-dma-pool";
+ reg = <0 0x90400000 0 0x100000>;
+ no-map;
+ };
+
+ vdev2vring0: memory@90100000 {
+ reg = <0 0x90100000 0 0x8000>;
+ no-map;
+ };
+
+ vdev2vring1: memory@90108000 {
+ reg = <0 0x90108000 0 0x8000>;
+ no-map;
+ };
+
+ vdev3vring0: memory@90110000 {
+ reg = <0 0x90110000 0 0x8000>;
+ no-map;
+ };
+
+ vdev3vring1: memory@90118000 {
+ reg = <0 0x90118000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table1: memory@901ff000 {
+ reg = <0 0x901ff000 0 0x1000>;
+ no-map;
+ };
+ };
+
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@@ -133,6 +195,37 @@ sound-wm8960 {
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
};
+
+ imx8qm-cm4-0 {
+ compatible = "fsl,imx8qm-cm4";
+ clocks = <&clk_dummy>;
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&lsio_mu5 0 1
+ &lsio_mu5 1 1
+ &lsio_mu5 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>;
+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
+
+ fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
+ fsl,entry-address = <0x34fe0000>;
+ };
+
+ imx8qm-cm4-1 {
+ compatible = "fsl,imx8qm-cm4";
+ clocks = <&clk_dummy>;
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&lsio_mu6 0 1
+ &lsio_mu6 1 1
+ &lsio_mu6 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>,
+ <&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>;
+ power-domains = <&pd IMX_SC_R_M4_1_PID0>, <&pd IMX_SC_R_M4_1_MU_1A>;
+
+ fsl,resource-id = <IMX_SC_R_M4_1_PID0>;
+ fsl,entry-address = <0x38fe0000>;
+ };
+
};
&adc0 {
--
2.34.1
Add pwm[0,1] and i2c[0,1] in lvds subsystem.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 92 ++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index dbd478af2e474..80cb834d56bc2 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -93,6 +93,42 @@ rsc_table1: memory@901ff000 {
};
};
+ lvds_backlight0: backlight-lvds0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm_lvds0 0 100000 0>;
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <80>;
+ };
+
+ lvds_backlight1: backlight-lvds1 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm_lvds1 0 100000 0>;
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <80>;
+ };
+
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@@ -334,6 +370,24 @@ wm8960: audio-codec@1a {
};
};
+&i2c1_lvds0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1_lvds1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
@@ -449,6 +503,18 @@ &fec2 {
status = "okay";
};
+&pwm_lvds0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_lvds0>;
+ status = "okay";
+};
+
+&pwm_lvds1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_lvds1>;
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -675,6 +741,32 @@ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
>;
};
+ pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+ fsl,pins = <
+ IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
+ IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+ fsl,pins = <
+ IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
+ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
+ >;
+ };
+
+ pinctrl_pwm_lvds0: pwmlvds0grp {
+ fsl,pins = <
+ IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020
+ >;
+ };
+
+ pinctrl_pwm_lvds1: pwmlvds1grp {
+ fsl,pins = <
+ IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020
+ >;
+ };
+
pinctrl_sai0: sai0grp {
fsl,pins = <
IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c
--
2.34.1
The gpio in "reg_usdhc2_vmmc" should be 7 instead of 19.
Cc: [email protected]
Fixes: 307fd14d4b14 ("arm64: dts: imx: add imx8qm mek support")
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index cdcd5993cc69f..dedcc1b1bf12f 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -134,7 +134,7 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
- gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
--
2.34.1
Add i2c node in mipi[0,1] subystem for imx8qm-mek.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 34 ++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 80cb834d56bc2..cdcd5993cc69f 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -388,6 +388,24 @@ &i2c1_lvds1 {
status = "okay";
};
+&i2c0_mipi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi0_lpi2c0>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c0_mipi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi1_lpi2c0>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
@@ -660,6 +678,22 @@ IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
>;
};
+ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {
+ fsl,pins = <
+ IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
+ IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
+ IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020
+ >;
+ };
+
+ pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {
+ fsl,pins = <
+ IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
+ IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
+ IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020
+ >;
+ };
+
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
--
2.34.1
Add irqstear, pwm and i2c in lvds subsystem.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 231 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
2 files changed, 232 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
new file mode 100644
index 0000000000000..eb8208cddeaf9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2024 NXP
+ */
+
+/{
+
+ lvds1_ipg_clk: lvds0_ipg_clk: clock-controller-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "lvds0_ipg_clk";
+ };
+
+ lvds1_subsys: bus@56240000 {
+ compatible = "simple-bus";
+ interrupt-parent = <&irqsteer_lvds0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56240000 0x0 0x56240000 0x10000>;
+
+ irqsteer_lvds0: interrupt-controller@56240000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56240000 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&lvds0_lis_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ };
+
+ lvds0_lis_lpcg: clock-controller@56243000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&lvds0_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds0_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+ };
+
+ lvds0_pwm_lpcg: clock-controller@5624300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5624300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds0_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds0_pwm_lpcg_clk",
+ "lvds0_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ };
+
+ lvds0_i2c0_lpcg: clock-controller@56243010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds0_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds0_i2c0_lpcg_clk",
+ "lvds0_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ };
+
+ lvds0_i2c1_lpcg: clock-controller@56243014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds0_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds0_i2c1_lpcg_clk",
+ "lvds0_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ };
+
+ pwm_lvds0: pwm@56244000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x56244000 0x1000>;
+ clocks = <&lvds0_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&lvds0_pwm_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_lvds0: i2c@56246000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56246000 0x1000>;
+ interrupts = <8>;
+ clocks = <&lvds0_i2c0_lpcg IMX_LPCG_CLK_0>,
+ <&lvds0_i2c0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ status = "disabled";
+ };
+
+ i2c1_lvds0: i2c@56247000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56247000 0x1000>;
+ interrupts = <9>;
+ clocks = <&lvds0_i2c0_lpcg IMX_LPCG_CLK_0>,
+ <&lvds0_i2c0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+ status = "disabled";
+ };
+ };
+
+ lvds2_subsys: bus@57240000 {
+ compatible = "simple-bus";
+ interrupt-parent = <&irqsteer_lvds1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x57240000 0x0 0x57240000 0x10000>;
+
+ irqsteer_lvds1: interrupt-controller@57240000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x57240000 0x1000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ };
+
+ lvds1_lis_lpcg: clock-controller@57243000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&lvds1_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ };
+
+ lvds1_pwm_lpcg: clock-controller@5724300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5724300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds1_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_pwm_lpcg_clk",
+ "lvds1_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ };
+
+ lvds1_i2c0_lpcg: clock-controller@57243010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds1_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_i2c0_lpcg_clk",
+ "lvds1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ };
+
+ lvds1_i2c1_lpcg: clock-controller@57243014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x57243014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&lvds1_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_i2c1_lpcg_clk",
+ "lvds1_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ };
+
+ pwm_lvds1: pwm@57244000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x57244000 0x1000>;
+ clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
+ <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_lvds1: i2c@57246000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57246000 0x1000>;
+ interrupts = <8>;
+ clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
+ <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ status = "disabled";
+ };
+
+ i2c1_lvds1: i2c@57247000 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x57247000 0x1000>;
+ interrupts = <9>;
+ clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
+ <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 61986e0639e53..9f29fe4589668 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -576,3 +576,4 @@ clk_spdif1_rx: clock-spdif1-rx {
#include "imx8qm-ss-conn.dtsi"
#include "imx8qm-ss-lsio.dtsi"
#include "imx8qm-ss-audio.dtsi"
+#include "imx8qm-ss-lvds.dtsi"
--
2.34.1
Enable usb3.0 and related usb type C nodes.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 87 ++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index dedcc1b1bf12f..f6e2f1573f6ab 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "imx8qm.dtsi"
+#include "dt-bindings/usb/pd.h"
/ {
model = "Freescale i.MX8QM MEK";
@@ -129,6 +130,21 @@ lvds_backlight1: backlight-lvds1 {
default-brightness-level = <80>;
};
+ gpio-sbu-mux {
+ compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec_mux>;
+ select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
+ orientation-switch;
+
+ port {
+ usb3_data_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+ };
+
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@@ -341,6 +357,44 @@ gyrometer@69 {
compatible = "st,l3g4200d-gyro";
reg = <0x69>;
};
+
+ ptn5110: tcpc@51 {
+ compatible = "nxp,ptn5110", "tcpci";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ reg = <0x51>;
+ interrupt-parent = <&lsio_gpio4>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+
+ usb_con1: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "source";
+ data-role = "dual";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec_dr_sw: endpoint {
+ remote-endpoint = <&usb3_drd_sw>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb3_data_ss>;
+ };
+ };
+ };
+ };
+ };
};
&i2c1 {
@@ -553,6 +607,26 @@ &usdhc2 {
status = "okay";
};
+&usb3_phy {
+ status = "okay";
+};
+
+&usbotg3 {
+ status = "okay";
+};
+
+&usbotg3_cdns3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ usb3_drd_sw: endpoint {
+ remote-endpoint = <&typec_dr_sw>;
+ };
+ };
+};
+
&sai0 {
#sound-dai-cells = <0>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
@@ -819,6 +893,19 @@ IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040
>;
};
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
+ >;
+ };
+
+ pinctrl_typec_mux: typecmuxgrp {
+ fsl,pins = <
+ IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60
+ IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
--
2.34.1
> Subject: [PATCH 1/7] arm64: dts: imx8qm: add lvds subsystem
>
> Add irqstear, pwm and i2c in lvds subsystem.
irqsteer
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 231
> ++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
> 2 files changed, 232 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> new file mode 100644
> index 0000000000000..eb8208cddeaf9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> @@ -0,0 +1,231 @@
> +// SPDX-License-Identifier: GPL-2.0+
GPL-2.0-only and MIT?
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +/{
> +
> + lvds1_ipg_clk: lvds0_ipg_clk: clock-controller-lvds-ipg {
Two alias name?
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + clock-output-names = "lvds0_ipg_clk";
> + };
> +
Regards,
Peng.
> Subject: [PATCH 2/7] arm64: dts: imx8qm: add mipi subsystem
>
> Add irqstear, pwm and i2c in mipi subsystem.
irqsteer
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | 286
> ++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
> 2 files changed, 287 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
> new file mode 100644
> index 0000000000000..bd18468923e52
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0+
GPL-2.0-only and MIT?
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +/ {
> + dsi_ipg_clk: clock-dsi-ipg {
In patch 1, you use clock-controller-x, not very sure which is correct,
but please align.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <120000000>;
> + clock-output-names = "dsi_ipg_clk";
> + };
> +
> + mipi_pll_div2_clk: clock-mipi-div2-pll {
Ditto.
Regards,
Peng
> Subject: [PATCH 3/7] arm64: dts: imx8qm-mek: add cm4 remote-proc and
> related memory region
>
> Add two cm4 remote-proc and related memory regions.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
Reviewed-by: Peng Fan <[email protected]>
> Subject: [PATCH 4/7] arm64: dts: imx8qm-mek: add pwm and i2c in lvds
> subsystem
>
> Add pwm[0,1] and i2c[0,1] in lvds subsystem.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
Reviewed-by: Peng Fan <[email protected]>
> Subject: [PATCH 5/7] arm64: dts: imx8qm-mek: add i2c in mipi[0,1]
> subsystem
>
> Add i2c node in mipi[0,1] subystem for imx8qm-mek.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
Reviewed-by: Peng Fan <[email protected]>
> Subject: [PATCH 6/7] arm64: dts: imx8qm-mek: fix gpio number for
> reg_usdhc2_vmmc
>
> The gpio in "reg_usdhc2_vmmc" should be 7 instead of 19.
>
> Cc: [email protected]
> Fixes: 307fd14d4b14 ("arm64: dts: imx: add imx8qm mek support")
> Signed-off-by: Frank Li <[email protected]>
> ---
Reviewed-by: Peng Fan <[email protected]>
On Thu, Jun 6, 2024 at 3:47 PM Frank Li <[email protected]> wrote:
> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
> + 10 11 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27 28 29
> + 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47 48 49
> + 50 51 52 53 54 55 56 57 58 59
> + 60 61 62 63 64 65 66 67 68 69
> + 70 71 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87 88 89
> + 90 91 92 93 94 95 96 97 98 99
> + 100>;
You can use this instead:
num-interpolated-steps = <100>;
> Subject: [PATCH 7/7] arm64: dts: imx8qm-mek: add usb 3.0 and related type
> C nodes
>
> Enable usb3.0 and related usb type C nodes.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 87
> ++++++++++++++++++++++++++++
> 1 file changed, 87 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index dedcc1b1bf12f..f6e2f1573f6ab 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "imx8qm.dtsi"
> +#include "dt-bindings/usb/pd.h"
#include <dt-bindings/usb/pd.h> ? and move before "imx8qm.dtsi" ?
>
> / {
> model = "Freescale i.MX8QM MEK";
> @@ -129,6 +130,21 @@ lvds_backlight1: backlight-lvds1 {
> default-brightness-level = <80>;
> };
>
> + gpio-sbu-mux {
use mux-controller?
Regards,
Peng
Hi,
Am Donnerstag, 6. Juni 2024, 20:46:59 CEST schrieb Frank Li:
> Add i2c node in mipi[0,1] subystem for imx8qm-mek.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 34 ++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index 80cb834d56bc2..cdcd5993cc69f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> @@ -388,6 +388,24 @@ &i2c1_lvds1 {
> status = "okay";
> };
>
> +&i2c0_mipi0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
These two properties should be part of the .dtsi.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mipi0_lpi2c0>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&i2c0_mipi1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
These two properties should be part of the .dtsi.
Best regards,
Alexander
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mipi1_lpi2c0>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> &flexcan1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_flexcan1>;
> @@ -660,6 +678,22 @@ IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
> >;
> };
>
> + pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {
> + fsl,pins = <
> + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
> + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
> + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020
> + >;
> + };
> +
> + pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {
> + fsl,pins = <
> + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
> + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
> + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020
> + >;
> + };
> +
> pinctrl_flexspi0: flexspi0grp {
> fsl,pins = <
> IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
>
>
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/
Hi,
Am Donnerstag, 6. Juni 2024, 20:46:58 CEST schrieb Frank Li:
> Add pwm[0,1] and i2c[0,1] in lvds subsystem.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 92 ++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index dbd478af2e474..80cb834d56bc2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> @@ -93,6 +93,42 @@ rsc_table1: memory@901ff000 {
> };
> };
>
> + lvds_backlight0: backlight-lvds0 {
> + compatible = "pwm-backlight";
> + pwms = <&pwm_lvds0 0 100000 0>;
> +
> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
> + 10 11 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27 28 29
> + 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47 48 49
> + 50 51 52 53 54 55 56 57 58 59
> + 60 61 62 63 64 65 66 67 68 69
> + 70 71 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87 88 89
> + 90 91 92 93 94 95 96 97 98 99
> + 100>;
> + default-brightness-level = <80>;
> + };
> +
> + lvds_backlight1: backlight-lvds1 {
> + compatible = "pwm-backlight";
> + pwms = <&pwm_lvds1 0 100000 0>;
> +
> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
> + 10 11 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27 28 29
> + 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47 48 49
> + 50 51 52 53 54 55 56 57 58 59
> + 60 61 62 63 64 65 66 67 68 69
> + 70 71 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87 88 89
> + 90 91 92 93 94 95 96 97 98 99
> + 100>;
> + default-brightness-level = <80>;
> + };
> +
> reg_usdhc2_vmmc: usdhc2-vmmc {
> compatible = "regulator-fixed";
> regulator-name = "SD1_SPWR";
> @@ -334,6 +370,24 @@ wm8960: audio-codec@1a {
> };
> };
>
> +&i2c1_lvds0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
These two properties should be part of the .dtsi.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&i2c1_lvds1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
These two properties should be part of the .dtsi.
Best regards,
Alexander
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> &flexcan1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_flexcan1>;
> @@ -449,6 +503,18 @@ &fec2 {
> status = "okay";
> };
>
> +&pwm_lvds0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm_lvds0>;
> + status = "okay";
> +};
> +
> +&pwm_lvds1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm_lvds1>;
> + status = "okay";
> +};
> +
> &usdhc1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> @@ -675,6 +741,32 @@ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
> >;
> };
>
> + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
> + fsl,pins = <
> + IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
> + IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
> + >;
> + };
> +
> + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
> + fsl,pins = <
> + IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
> + IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
> + >;
> + };
> +
> + pinctrl_pwm_lvds0: pwmlvds0grp {
> + fsl,pins = <
> + IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020
> + >;
> + };
> +
> + pinctrl_pwm_lvds1: pwmlvds1grp {
> + fsl,pins = <
> + IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020
> + >;
> + };
> +
> pinctrl_sai0: sai0grp {
> fsl,pins = <
> IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c
>
>
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/
Hi,
thanks for the patch.
What are your plans regarding imx8xqp? This memory region
has dual use on imx8qxp mipi/lvds0. I would prefer
imx8-ss-mipi.dtsi with common parts and a imx8qm-ss-mipi.dtsi
adding/modifying imx8qm specific things. I'll send my current WIP
as a response to this.
Best regards,
Alexander
Am Donnerstag, 6. Juni 2024, 20:46:56 CEST schrieb Frank Li:
> Add irqstear, pwm and i2c in mipi subsystem.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | 286 ++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
> 2 files changed, 287 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
> new file mode 100644
> index 0000000000000..bd18468923e52
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +/ {
> + dsi_ipg_clk: clock-dsi-ipg {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <120000000>;
> + clock-output-names = "dsi_ipg_clk";
> + };
> +
> + mipi_pll_div2_clk: clock-mipi-div2-pll {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <432000000>;
> + clock-output-names = "mipi_pll_div2_clk";
> + };
> +
> + mipi0_subsys: bus@56220000 {
> + compatible = "simple-bus";
> + interrupt-parent = <&irqsteer_mipi0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x56220000 0x0 0x56220000 0x10000>;
> +
> + irqsteer_mipi0: interrupt-controller@56220000 {
> + compatible = "fsl,imx-irqsteer";
compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer" or even
compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer". Please refer to [1].
[1] https://lore.kernel.org/all/[email protected]/
> + reg = <0x56220000 0x1000>;
> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <1>;
> + clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> + fsl,channel = <0>;
> + fsl,num-irqs = <32>;
> + };
> +
> + mipi0_lis_lpcg: clock-controller@56223000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223000 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_lis_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> + };
> +
> + mipi0_pwm_lpcg: clock-controller@5622300c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622300c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
> + <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "mipi0_pwm_lpcg_clk",
> + "mipi0_pwm_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> + };
> +
> + mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223014 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223018 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622301c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c0_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + };
> +
> + mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223024 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5622302c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x56223028 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> + };
> +
> + pwm_mipi0: pwm@56224000 {
> + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> + reg = <0x56224000 0x1000>;
> + clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
> + <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + #pwm-cells = <3>;
> + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> + status = "disabled";
> + };
> +
> + i2c0_mipi0: i2c@56226000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x56226000 0x1000>;
> + interrupts = <8>;
> + clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> + <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> + status = "disabled";
> + };
> + };
> +
> + mipi1_subsys: bus@57220000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x57220000 0x0 0x57220000 0x10000>;
> +
> + irqsteer_mipi1: interrupt-controller@57220000 {
> + compatible = "fsl,imx-irqsteer";
> + reg = <0x57220000 0x1000>;
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <1>;
> + clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_MIPI_1>;
> + fsl,channel = <0>;
> + fsl,num-irqs = <32>;
> + };
> +
> + mipi1_lis_lpcg: clock-controller@57223000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223000 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1>;
> + };
> +
> + mipi1_pwm_lpcg: clock-controller@5722300c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722300c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
> + <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "mipi1_pwm_lpcg_clk",
> + "mipi1_pwm_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> + };
> +
> + mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722301c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223014 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223018 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + };
> +
> + mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223024 0x4>;
> + #clock-cells = <1>;
> + clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x57223028 0x4>;
> + #clock-cells = <1>;
> + clocks = <&dsi_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5722302c 0x4>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
> + clock-indices = <IMX_LPCG_CLK_0>;
> + clock-output-names = "mipi1_i2c1_lpcg_clk";
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> + };
> +
> + pwm_mipi1: pwm@57224000 {
> + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> + reg = <0x57224000 0x1000>;
> + clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
> + <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + #pwm-cells = <3>;
> + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> + status = "disabled";
> + };
> +
> + i2c0_mipi1: i2c@57226000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x57226000 0x1000>;
> + interrupts = <8>;
> + interrupt-parent = <&irqsteer_mipi1>;
> + clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> + <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> + status = "disabled";
> + };
> + };
> +};
> +
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> index 9f29fe4589668..846b95be22bbe 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> @@ -577,3 +577,4 @@ clk_spdif1_rx: clock-spdif1-rx {
> #include "imx8qm-ss-lsio.dtsi"
> #include "imx8qm-ss-audio.dtsi"
> #include "imx8qm-ss-lvds.dtsi"
> +#include "imx8qm-ss-mipi.dtsi"
>
>
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/
---
Current WIP ported from downstream kernel. Still a lot of TODOs
and missing parts.
It's the same approach as imx8-ss-lsio.dtsi and friends which are supposed
to be included inside the DT root node, not at the end.
.../boot/dts/freescale/imx8-ss-lvds0.dtsi | 574 ++++++++++++++++++
1 file changed, 574 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
new file mode 100644
index 0000000000000..8ad13962925d0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
@@ -0,0 +1,574 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019 NXP
+ */
+
+mipi_ipg_clk: clock-mipi-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "mipi_ipg_clk";
+};
+
+mipi_pll_div2_clk: clock-mipi-div2-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <432000000>;
+ clock-output-names = "mipi_pll_div2_clk";
+};
+
+lvds_subsys: bus@56200000 {
+ compatible = "simple-bus";
+ reg = <0x56200000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ lvds0_subsys: bus@56220000 {
+ compatible = "simple-bus";
+ reg = <0x56220000 0x30000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&irqsteer_mipi_lvds0>;
+
+ irqsteer_mipi_lvds0: irqsteer@56220000 {
+ compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
+ reg = <0x56220000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&mipi0_lis_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ mipi_lvds0_csr: syscon@56221000 {
+ compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
+ reg = <0x56221000 0x1000>;
+ clocks = <&mipi_lvds0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+ status = "disabled";
+
+ mipi_lvds0_pxl2dpi: pxl2dpi {
+ compatible = "fsl,imx8qxp-pxl2dpi";
+ fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ // mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
+ // reg = <1>;
+ // remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
+ // };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ // mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+ // reg = <1>;
+ // remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+ // };
+ };
+ };
+ };
+
+ mipi_lvds_0_ldb: ldb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>;
+ assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+ status = "disabled";
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ /* ... */
+ };
+ };
+
+ // channel@1 {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // reg = <1>;
+ // phys = <&mipi_lvds_0_phy>;
+ // phy-names = "lvds_phy";
+
+ // port@0 {
+ // reg = <0>;
+
+ // mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+ // remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+ // };
+ // };
+
+ // port@1 {
+ // reg = <1>;
+
+ // /* ... */
+ // };
+ // };
+ };
+ };
+
+ mipi0_lis_lpcg: clock-controller@56223000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi0_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ mipi_lvds0_di_mipi_lvds_regs_lpcg: clock-controller@56223004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223004 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi_lvds0_di_mipi_lvds_regs_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ mipi0_pwm_lpcg: clock-controller@5622300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5622300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>,
+ <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4 IMX_LPCG_CLK_1>;
+ clock-output-names = "mipi0_pwm_lpcg_clk",
+ "mipi0_pwm_lpcg_ipg_clk",
+ "mipi0_pwm_lpcg_32k_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+ };
+
+ mipi0_i2c0_lpcg: clock-controller@56223010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi0_i2c0_lpcg_clk",
+ "mipi0_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ };
+
+ mipi0_i2c1_lpcg: clock-controller@56223014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi0_i2c1_lpcg_clk",
+ "mipi0_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+ };
+
+ pwm_mipi_lvds0: pwm@56224000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x56224000 0x1000>;
+ clocks = <&mipi0_pwm_lpcg 0>,
+ <&mipi0_pwm_lpcg 1>,
+ <&mipi0_pwm_lpcg 2>;
+ clock-names = "per", "ipg", "32k";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_mipi_lvds0: i2c@56226000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56226000 0x1000>;
+ interrupts = <8>;
+ clocks = <&mipi0_i2c0_lpcg 0>,
+ <&mipi0_i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+ status = "disabled";
+ };
+
+ mipi_lvds_0_phy: phy@56228300 {
+ compatible = "fsl,imx8qxp-mipi-dphy";
+ reg = <0x56228300 0x100>;
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>;
+ clock-names = "phy_ref";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>;
+ assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ #phy-cells = <0>;
+ fsl,syscon = <&mipi_lvds0_csr>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ /* TODO MIPI DSI0 */
+ };
+
+ // mipi0_dsi_host: dsi_host@56228000 {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // compatible = "fsl,imx8qx-nwl-dsi";
+ // reg = <0x56228000 0x300>;
+ // clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>,
+ // <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>,
+ // <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>,
+ // <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
+ // <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>,
+ // <&mipi_pll_div2_clk>;
+ // clock-names = "pixel",
+ // "bypass",
+ // "phy_ref",
+ // "tx_esc",
+ // "rx_esc",
+ // "phy_parent";
+ // interrupts = <16>;
+ // power-domains = <&pd IMX_SC_R_MIPI_0>;
+ // phys = <&mipi0_dphy>;
+ // phy-names = "dphy";
+ // csr = <&lvds_region1>;
+ // use-disp-ss;
+ // status = "disabled";
+
+ // ports {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+
+ // mipi0_in: port@0 {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+
+ // reg = <0>;
+ // mipi0_dsi_in: endpoint@0 {
+ // reg = <0>;
+ // remote-endpoint = <&dpu_disp0_mipi_dsi>;
+ // };
+ // };
+ // };
+ // };
+
+ lvds1_subsys: bus@56240000 {
+ compatible = "simple-bus";
+ reg = <0x56240000 0x30000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&irqsteer_mipi_lvds1>;
+
+ irqsteer_mipi_lvds1: irqsteer@56240000 {
+ compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
+ reg = <0x56240000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ fsl,channel = <0>;
+ fsl,num-irqs = <32>;
+ clocks = <&mipi1_lis_lpcg 0>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ mipi_lvds1_csr: syscon@56241000 {
+ compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
+ reg = <0x56241000 0x1000>;
+ clocks = <&mipi_lvds1_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+ status = "disabled";
+
+ mipi_lvds1_pxl2dpi: pxl2dpi {
+ compatible = "fsl,imx8qxp-pxl2dpi";
+ fsl,sc-resource = <IMX_SC_R_MIPI_1>;
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_lvds_1_pxl2dpi_dc0_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc0_pixel_link0_mipi_lvds_1_pxl2dpi>;
+ };
+
+ // mipi_lvds_1_pxl2dpi_dc0_pixel_link1: endpoint@1 {
+ // reg = <1>;
+ // remote-endpoint = <&dc0_pixel_link1_mipi_lvds_1_pxl2dpi>;
+ // };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_1_ldb_ch0_mipi_lvds_1_pxl2dpi>;
+ };
+
+ // mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1: endpoint@1 {
+ // reg = <1>;
+ // remote-endpoint = <&mipi_lvds_1_ldb_ch1_mipi_lvds_1_pxl2dpi>;
+ // };
+ };
+ };
+ };
+
+ mipi_lvds_1_ldb: ldb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>;
+ assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>;
+ power-domains = <&pd IMX_SC_R_LVDS_1>;
+ status = "disabled";
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&mipi_lvds_1_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_1_ldb_ch0_mipi_lvds_1_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ /* ... */
+ };
+ };
+
+ // channel@1 {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // reg = <1>;
+ // phys = <&mipi_lvds_1_phy>;
+ // phy-names = "lvds_phy";
+
+ // port@0 {
+ // reg = <0>;
+
+ // mipi_lvds_1_ldb_ch1_mipi_lvds_1_pxl2dpi: endpoint {
+ // remote-endpoint = <&mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1>;
+ // };
+ // };
+
+ // port@1 {
+ // reg = <1>;
+
+ // /* ... */
+ // };
+ // };
+ };
+ };
+
+ mipi1_lis_lpcg: clock-controller@56243000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ mipi_lvds1_di_mipi_lvds_regs_lpcg: clock-controller@56243004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243004 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi_lvds1_di_mipi_lvds_regs_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ mipi1_pwm_lpcg: clock-controller@5624300c {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5624300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>,
+ <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4 IMX_LPCG_CLK_1>;
+ clock-output-names = "mipi1_pwm_lpcg_clk",
+ "mipi1_pwm_lpcg_ipg_clk",
+ "mipi1_pwm_lpcg_32k_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ };
+
+ mipi1_i2c0_lpcg: clock-controller@56243010 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243010 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi1_i2c0_lpcg_clk",
+ "mipi1_i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ };
+
+ mipi1_i2c1_lpcg: clock-controller@56243014 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56243014 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_PER>,
+ <&mipi_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi1_i2c1_lpcg_clk",
+ "mipi1_i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+ };
+
+ pwm_mipi_lvds1: pwm@56244000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x56244000 0x1000>;
+ clocks = <&mipi1_pwm_lpcg 0>,
+ <&mipi1_pwm_lpcg 1>,
+ <&mipi1_pwm_lpcg 2>;
+ clock-names = "per", "ipg", "32k";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+ status = "disabled";
+ };
+
+ i2c0_mipi_lvds1: i2c@56246000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x56246000 0x1000>;
+ interrupts = <8>;
+ clocks = <&mipi1_i2c0_lpcg 0>,
+ <&mipi1_i2c0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+ status = "disabled";
+ };
+
+ mipi_lvds_1_phy: phy@56248300 {
+ compatible = "fsl,imx8qxp-mipi-dphy";
+ reg = <0x56248300 0x100>;
+ clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>;
+ clock-names = "phy_ref";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>;
+ assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>;
+ #phy-cells = <0>;
+ fsl,syscon = <&mipi_lvds1_csr>;
+ power-domains = <&pd IMX_SC_R_MIPI_1>;
+ };
+
+ /* TODO MIPI DSI1 */
+ };
+
+ // mipi1_dsi_host: dsi_host@56248000 {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // compatible = "fsl,imx8qx-nwl-dsi";
+ // reg = <0x56248000 0x300>;
+ // clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>,
+ // <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>,
+ // <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>,
+ // <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
+ // <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>,
+ // <&mipi_pll_div2_clk>;
+ // clock-names = "pixel",
+ // "bypass",
+ // "phy_ref",
+ // "tx_esc",
+ // "rx_esc",
+ // "phy_parent";
+ // interrupts = <16>;
+ // power-domains = <&pd IMX_SC_R_MIPI_1>;
+ // phys = <&mipi1_dphy>;
+ // phy-names = "dphy";
+ // csr = <&lvds_region2>;
+ // use-disp-ss;
+ // status = "disabled";
+
+ // ports {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+
+ // mipi1_in: port@0 {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+
+ // reg = <0>;
+ // mipi1_dsi_in: endpoint@0 {
+ // reg = <0>;
+ // remote-endpoint = <&dpu_disp1_mipi_dsi>;
+ // };
+ // };
+ // };
+ // };
+
+};
--
2.34.1
On Fri, Jun 07, 2024 at 01:28:35AM +0000, Peng Fan wrote:
> > Subject: [PATCH 1/7] arm64: dts: imx8qm: add lvds subsystem
> >
> > Add irqstear, pwm and i2c in lvds subsystem.
>
> irqsteer
>
> >
> > Signed-off-by: Frank Li <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 231
> > ++++++++++++++++++++++
> > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
> > 2 files changed, 232 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> > new file mode 100644
> > index 0000000000000..eb8208cddeaf9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> > @@ -0,0 +1,231 @@
> > +// SPDX-License-Identifier: GPL-2.0+
>
> GPL-2.0-only and MIT?
>
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +/{
> > +
> > + lvds1_ipg_clk: lvds0_ipg_clk: clock-controller-lvds-ipg {
>
> Two alias name?
It is alllowed by dt. link to one fixed 24M clock. of course we can change
lvds1_ipg_clk to lvds0_ipg_clk.
To avoid confuse, I'd better use two name to align node nams.
Frank
>
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + clock-output-names = "lvds0_ipg_clk";
> > + };
> > +
>
> Regards,
> Peng.