Select the CONFIG_PHY_ROCKCHIP_INNO_USB2 option by default, so that
USB can be functional on RV1108.
Signed-off-by: Otavio Salvador <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 63af6234c1b6..a8ec309d182a 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -947,6 +947,7 @@ CONFIG_PHY_CPCAP_USB=m
CONFIG_PHY_QCOM_APQ8064_SATA=m
CONFIG_PHY_RCAR_GEN2=m
CONFIG_PHY_ROCKCHIP_DP=m
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_SAMSUNG_USB2=m
CONFIG_PHY_MIPHY28LP=y
--
2.19.1
From: Fabio Berton <[email protected]>
Signed-off-by: Fabio Berton <[email protected]>
Signed-off-by: Otavio Salvador <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index a8ec309d182a..34c8a745d951 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -2,7 +2,12 @@ CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CGROUPS=y
+CONFIG_CGROUP_BPF=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_BPF_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_MODULES=y
--
2.19.1
The phy-supply is an optional regulator, so we should not treat
as an error when phy-supply is not passed in the device tree.
This allows the dwmac-rk driver to probe when phy-supply is not
present in the dts.
Signed-off-by: Otavio Salvador <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 7b923362ee55..73855622445b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1205,7 +1205,7 @@ static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
if (!ldo) {
dev_err(dev, "no regulator found\n");
- return -1;
+ return 0;
}
if (enable) {
--
2.19.1
The PHY regulator is optional, so when it is not present move the message
level from error to debug, which is more appropriate.
Signed-off-by: Otavio Salvador <[email protected]>
Signed-off-by: Fabio Berton <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index c895a9a6939a..6b4ea95a30e0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1242,7 +1242,7 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
dev_err(dev, "phy regulator is not available yet, deferred probing\n");
return ERR_PTR(-EPROBE_DEFER);
}
- dev_err(dev, "no regulator found\n");
+ dev_dbg(dev, "no regulator found\n");
bsp_priv->regulator = NULL;
}
--
2.19.1
Add GMAC support for RV1108.
Signed-off-by: Otavio Salvador <[email protected]>
---
arch/arm/boot/dts/rv1108.dtsi | 36 +++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 4f4275599f7a..c7a26f82655b 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -516,6 +516,27 @@
status = "disabled";
};
+ gmac: eth@30200000 {
+ compatible = "rockchip,rv1108-gmac";
+ reg = <0x30200000 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru SCLK_MAC>,
+ <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
+ <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth",
+ "mac_clk_rx", "mac_clk_tx",
+ "clk_mac_ref", "clk_mac_refout",
+ "aclk_mac", "pclk_mac";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -641,6 +662,21 @@
input-enable;
};
+ gmac {
+ rmii_pins: rmii-pins {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
+ <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
+ <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
+ <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
--
2.19.1
As done in the Rockchip vendor tree and also on other
"arm,armv7-timer" instances, the correct GIC_CPU_MASK_SIMPLE mask
is 4 instead of 1.
Signed-off-by: Otavio Salvador <[email protected]>
Signed-off-by: Fabio Berton <[email protected]>
---
arch/arm/boot/dts/rv1108.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index c7a26f82655b..7b331766120d 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -71,8 +71,8 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
--
2.19.1
According to the Rockchip vendor tree the PMU interrupt number is
76, so fix it accordingly.
Signed-off-by: Otavio Salvador <[email protected]>
Signed-off-by: Fabio Berton <[email protected]>
---
arch/arm/boot/dts/rv1108.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 7b331766120d..442b749eb2e9 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -66,7 +66,7 @@
arm-pmu {
compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
--
2.19.1
Add support for the internal timer peripheral on RV1108.
Signed-off-by: Otavio Salvador <[email protected]>
---
arch/arm/boot/dts/rv1108.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 7ef6d965871c..42566adadc83 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -291,6 +291,14 @@
};
};
+ timer: timer@10350000 {
+ compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
+ reg = <0x10350000 0x20>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>, <&cru PCLK_TIMER>;
+ clock-names = "timer", "pclk";
+ };
+
watchdog: wdt@10360000 {
compatible = "snps,dw-wdt";
reg = <0x10360000 0x100>;
--
2.19.1
Like it is done on cpu nodes of other Rockchip SoCs, pass the
'clock-latency' property to the CPU node, so that cpufreq driver
can take the latency into account when switching frequencies.
Signed-off-by: Otavio Salvador <[email protected]>
---
arch/arm/boot/dts/rv1108.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index d96c58728b28..4e1ca13a1636 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -36,6 +36,7 @@
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <75>;
operating-points-v2 = <&cpu_opp_table>;
+ clock-latency = <40000>;
};
};
--
2.19.1
rk_gmac_setup() already prints a message saying that the PHY regulator
is not found, so we should not print it again.
Signed-off-by: Otavio Salvador <[email protected]>
Signed-off-by: Fabio Berton <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 73855622445b..c895a9a6939a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1203,10 +1203,8 @@ static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
int ret;
struct device *dev = &bsp_priv->pdev->dev;
- if (!ldo) {
- dev_err(dev, "no regulator found\n");
+ if (!ldo)
return 0;
- }
if (enable) {
ret = regulator_enable(ldo);
--
2.19.1
It is not correct to assign the 24MHz clock oscillator to the GPIO
ports.
Fix it by assigning the proper GPIO clocks instead.
Signed-off-by: Otavio Salvador <[email protected]>
Signed-off-by: Fabio Berton <[email protected]>
---
arch/arm/boot/dts/rv1108.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 442b749eb2e9..ce5509c4657b 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -562,7 +562,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x20030000 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>;
+ clocks = <&cru PCLK_GPIO0_PMU>;
gpio-controller;
#gpio-cells = <2>;
@@ -575,7 +575,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x10310000 0x100>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>;
+ clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
@@ -588,7 +588,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x10320000 0x100>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>;
+ clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
@@ -601,7 +601,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x10330000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>;
+ clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
--
2.19.1
Pass the 'dmas' property to the UART ports so that DMA can
be supported.
Signed-off-by: Otavio Salvador <[email protected]>
Signed-off-by: Fabio Berton <[email protected]>
---
arch/arm/boot/dts/rv1108.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index ce5509c4657b..7ef6d965871c 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -114,6 +114,8 @@
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ dmas = <&pdma 6>, <&pdma 7>;
+ #dma-cells = <2>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
@@ -128,6 +130,8 @@
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ dmas = <&pdma 4>, <&pdma 5>;
+ #dma-cells = <2>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
@@ -142,6 +146,8 @@
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ dmas = <&pdma 2>, <&pdma 3>;
+ #dma-cells = <2>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
--
2.19.1
Since firmware does not initialize any of the generic timer CPU
registers pass the 'arm,cpu-registers-not-fw-configured' property as
suggested in Documentation/devicetree/bindings/timer/arm,arch_timer.txt.
This also aligns with other Rockchip SoC dtsi files.
Signed-off-by: Otavio Salvador <[email protected]>
---
arch/arm/boot/dts/rv1108.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 42566adadc83..d96c58728b28 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -71,6 +71,7 @@
timer {
compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
--
2.19.1
On Sun, Nov 25, 2018 at 1:19 PM Otavio Salvador <[email protected]> wrote:
>
> From: Fabio Berton <[email protected]>
>
> Signed-off-by: Fabio Berton <[email protected]>
> Signed-off-by: Otavio Salvador <[email protected]>
Hi Otavio,
Thanks for these patches. I don't have a reason to _not_ enable
systemd features, but would you mind providing a brief description of
what's not working without this change? Is it completely broken, or is
it just the random-UID featues that don't work, or something else?.
Useful for others to know what's expected to break if someone turns
them off, etc.
Also, I noticed you posted a series of 13 patches, which includes some
dts files for rv1108, some network driver changes and some of these
more generic defconfig changes. I would suggest that you split up your
patches into independent series where possible, especially when they
end up going to different subsystems. Providing suitable cover letters
for the series when you post them is also useful to help reviewers by
summarizing the series, including changes from last time it was
posted, etc. Please address it to the superset of patch receivers on
the series.
I'm asking for the cover letter because this time I was wondering if
there was a reason for the mix of patches so I went looking for it.
Maybe there is a need to group them together even though the
sub-series seem somewhat independent -- I can't tell from the way they
were posted.
Thanks!
-Olof
Hello Olof,
On Sun, Nov 25, 2018 at 8:25 PM Olof Johansson <[email protected]> wrote:
> Thanks for these patches. I don't have a reason to _not_ enable
> systemd features, but would you mind providing a brief description of
> what's not working without this change? Is it completely broken, or is
> it just the random-UID featues that don't work, or something else?.
> Useful for others to know what's expected to break if someone turns
> them off, etc.
Thank you for your kindness reviewing this. I am not an experienced
Linux kernel contributor so I am going to do some mistakes during this
process.
We usually follow the required feature set listed on Gentoo wiki[1] as
it is usually up to date and avoids a lot of headaches for us when
dealing with boot issues with SystemD.
1. https://wiki.gentoo.org/wiki/Systemd#Kernel
Do you think mentioning where it has been taken from is enough?
> Also, I noticed you posted a series of 13 patches, which includes some
> dts files for rv1108, some network driver changes and some of these
> more generic defconfig changes. I would suggest that you split up your
> patches into independent series where possible, especially when they
> end up going to different subsystems. Providing suitable cover letters
> for the series when you post them is also useful to help reviewers by
> summarizing the series, including changes from last time it was
> posted, etc. Please address it to the superset of patch receivers on
> the series.
I can certainly improve it for the next submission. Should I split
them all and tag them v2 to easy it?
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854 Mobile: +1 (347) 903-9750
Am Sonntag, 25. November 2018, 22:19:01 CET schrieb Otavio Salvador:
> As done in the Rockchip vendor tree and also on other
> "arm,armv7-timer" instances, the correct GIC_CPU_MASK_SIMPLE mask
> is 4 instead of 1.
Nope. That value represents the number of cores in the system.
As the rv1108 only has one core, that should likely stay as it is.
Also, it seems I only got patches 6-13 what happened to 1-5?
Heiko
> Signed-off-by: Otavio Salvador <[email protected]>
> Signed-off-by: Fabio Berton <[email protected]>
> ---
>
> arch/arm/boot/dts/rv1108.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
> index c7a26f82655b..7b331766120d 100644
> --- a/arch/arm/boot/dts/rv1108.dtsi
> +++ b/arch/arm/boot/dts/rv1108.dtsi
> @@ -71,8 +71,8 @@
>
> timer {
> compatible = "arm,armv7-timer";
> - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
> - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> clock-frequency = <24000000>;
> };
>
>
Hi Otavio,
Am Sonntag, 25. November 2018, 22:19:02 CET schrieb Otavio Salvador:
> According to the Rockchip vendor tree the PMU interrupt number is
> 76, so fix it accordingly.
>
> Signed-off-by: Otavio Salvador <[email protected]>
> Signed-off-by: Fabio Berton <[email protected]>
looks ok, especially as the TRM I have doesn't list neither irqs :-)
But please explain the second Signed-off by Fabio?
If Fabio is the original author, the patch From should reflect that
and the Signed-off-by lines should be swapped. As it is now
I would expect Fabio being the one sending the patches.
Or is it supposed to be a "Co-developed-by:"?
See Documentation/process/5.Posting.rst.
Thanks
Heiko
Hi,
Am Sonntag, 25. November 2018, 22:19:05 CET schrieb Otavio Salvador:
> Add support for the internal timer peripheral on RV1108.
>
> Signed-off-by: Otavio Salvador <[email protected]>
> ---
>
> arch/arm/boot/dts/rv1108.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
> index 7ef6d965871c..42566adadc83 100644
> --- a/arch/arm/boot/dts/rv1108.dtsi
> +++ b/arch/arm/boot/dts/rv1108.dtsi
> @@ -291,6 +291,14 @@
> };
> };
>
> + timer: timer@10350000 {
> + compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
please also document that new compatible string in
Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt
Heiko
Am Sonntag, 25. November 2018, 22:19:00 CET schrieb Otavio Salvador:
> Add GMAC support for RV1108.
>
> Signed-off-by: Otavio Salvador <[email protected]>
applied for 4.21 after modifying the subject a bit and adding
a comment explaining that the rv1108 only has that rmii interface.
While the dwmac is definitly a big improvement over the arc-emac
it is still surprising that the gbit mac only gets a 100mbit phy interface.
Heiko
Am Sonntag, 25. November 2018, 22:19:07 CET schrieb Otavio Salvador:
> Like it is done on cpu nodes of other Rockchip SoCs, pass the
> 'clock-latency' property to the CPU node, so that cpufreq driver
> can take the latency into account when switching frequencies.
>
> Signed-off-by: Otavio Salvador <[email protected]>
applied for 4.21 after adapting the subject and moving the property
to its correct alphabetical position in the node.
Thanks
Heiko
Am Sonntag, 25. November 2018, 22:19:06 CET schrieb Otavio Salvador:
> Since firmware does not initialize any of the generic timer CPU
> registers pass the 'arm,cpu-registers-not-fw-configured' property as
> suggested in Documentation/devicetree/bindings/timer/arm,arch_timer.txt.
>
> This also aligns with other Rockchip SoC dtsi files.
>
> Signed-off-by: Otavio Salvador <[email protected]>
applied for 4.21 after adapting the subject a bit.
Thanks
Heiko
Hello Heiko,
On Mon, Nov 26, 2018 at 3:59 AM Heiko Stuebner <[email protected]> wrote:
> Am Sonntag, 25. November 2018, 22:19:02 CET schrieb Otavio Salvador:
> > According to the Rockchip vendor tree the PMU interrupt number is
> > 76, so fix it accordingly.
> >
> > Signed-off-by: Otavio Salvador <[email protected]>
> > Signed-off-by: Fabio Berton <[email protected]>
>
> looks ok, especially as the TRM I have doesn't list neither irqs :-)
> But please explain the second Signed-off by Fabio?
>
> If Fabio is the original author, the patch From should reflect that
> and the Signed-off-by lines should be swapped. As it is now
> I would expect Fabio being the one sending the patches.
> Or is it supposed to be a "Co-developed-by:"?
> See Documentation/process/5.Posting.rst.
He works with me and he applied and tested it in our internal tree for
our customer. He reviewed and tested this with me, so I'd like to
provide him credit as well.
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854 Mobile: +1 (347) 903-9750
On Mon, Nov 26, 2018 at 3:27 AM Heiko Stuebner <[email protected]> wrote:
> Am Sonntag, 25. November 2018, 22:19:01 CET schrieb Otavio Salvador:
> > As done in the Rockchip vendor tree and also on other
> > "arm,armv7-timer" instances, the correct GIC_CPU_MASK_SIMPLE mask
> > is 4 instead of 1.
>
> Nope. That value represents the number of cores in the system.
> As the rv1108 only has one core, that should likely stay as it is.
I see, I will drop it for v2.
> Also, it seems I only got patches 6-13 what happened to 1-5?
It went to other mailing lists, I think. I will add you on Cc to all for v2.
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854 Mobile: +1 (347) 903-9750
Am Montag, 26. November 2018, 14:36:01 CET schrieb Otavio Salvador:
> Hello Heiko,
>
> On Mon, Nov 26, 2018 at 3:59 AM Heiko Stuebner <[email protected]> wrote:
> > Am Sonntag, 25. November 2018, 22:19:02 CET schrieb Otavio Salvador:
> > > According to the Rockchip vendor tree the PMU interrupt number is
> > > 76, so fix it accordingly.
> > >
> > > Signed-off-by: Otavio Salvador <[email protected]>
> > > Signed-off-by: Fabio Berton <[email protected]>
> >
> > looks ok, especially as the TRM I have doesn't list neither irqs :-)
> > But please explain the second Signed-off by Fabio?
> >
> > If Fabio is the original author, the patch From should reflect that
> > and the Signed-off-by lines should be swapped. As it is now
> > I would expect Fabio being the one sending the patches.
> > Or is it supposed to be a "Co-developed-by:"?
> > See Documentation/process/5.Posting.rst.
>
> He works with me and he applied and tested it in our internal tree for
> our customer. He reviewed and tested this with me, so I'd like to
> provide him credit as well.
Reviewed-by:
Tested-by:
perhaps then? :-)
Heiko