From: Chen Wang <[email protected]>
This series adds reset controller support for Sophgo SG2042 using
reset-simple driver.
Thanks,
Chen
---
Changes in v3:
This patch series is based on v6.8-rc2, which has included the missed patch I
mentioned in v2.
- As suggested by Philipp, drop the Kconfig for SG2042, just add a default
y if ARCH_SOPHGO to RESET_SIMPLE.
Changes in v2:
This patch series is based on v6.8-rc1. You can simply review or test the
patches at the link [3].
- fixed some minor formatting issues.
Note that if you need to pass dtb check, you need to apply a patch. This
patch is missing in v6.8-rc1. For details, please see [2].
Changes in v1:
The patch series is based on v6.7. You can simply review or test the
patches at the link [1].
Link: https://lore.kernel.org/linux-riscv/[email protected]/ [1]
Link: https://lore.kernel.org/linux-riscv/MA0P287MB28228572C526C5099A8BDA2DFE7B2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM/T/#u [2]
Link: https://lore.kernel.org/linux-riscv/[email protected]/ [3]
---
Chen Wang (4):
dt-bindings: reset: sophgo: support SG2042
reset: simple: add support for Sophgo SG2042
riscv: dts: add reset generator for Sophgo SG2042 SoC
riscv: dts: add resets property for uart node
.../bindings/reset/sophgo,sg2042-reset.yaml | 35 ++++++++
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 9 ++
drivers/reset/Kconfig | 3 +-
drivers/reset/reset-simple.c | 2 +
.../dt-bindings/reset/sophgo,sg2042-reset.h | 87 +++++++++++++++++++
5 files changed, 135 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h
base-commit: 41bccc98fb7931d63d03f326a746ac4d429c1dd3
--
2.25.1
From: Chen Wang <[email protected]>
Reuse reset-simple driver for the Sophgo SG2042 reset generator.
Signed-off-by: Chen Wang <[email protected]>
---
drivers/reset/Kconfig | 3 ++-
drivers/reset/reset-simple.c | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index ccd59ddd7610..2034f69d5953 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -213,7 +213,7 @@ config RESET_SCMI
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
- default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
+ default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
depends on HAS_IOMEM
help
This enables a simple reset controller driver for reset lines that
@@ -228,6 +228,7 @@ config RESET_SIMPLE
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
- SiFive FU740 SoCs
+ - Sophgo SoCs
config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index 818cabcc9fb7..276067839830 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
{ .compatible = "snps,dw-high-reset" },
{ .compatible = "snps,dw-low-reset",
.data = &reset_simple_active_low },
+ { .compatible = "sophgo,sg2042-reset",
+ .data = &reset_simple_active_low },
{ /* sentinel */ },
};
--
2.25.1
From: Chen Wang <[email protected]>
Add reset generator node to device tree for SG2042.
Signed-off-by: Chen Wang <[email protected]>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index ead1cc35d88b..eeb341e16bfd 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -6,6 +6,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sophgo,sg2042-reset.h>
+
#include "sg2042-cpus.dtsi"
/ {
@@ -327,6 +329,12 @@ intc: interrupt-controller@7090000000 {
riscv,ndev = <224>;
};
+ rstgen: reset-controller@7030013000 {
+ compatible = "sophgo,sg2042-reset";
+ reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
+ #reset-cells = <1>;
+ };
+
uart0: serial@7040000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
--
2.25.1
From: Chen Wang <[email protected]>
Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.
Signed-off-by: Chen Wang <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/reset/sophgo,sg2042-reset.yaml | 35 ++++++++
.../dt-bindings/reset/sophgo,sg2042-reset.h | 87 +++++++++++++++++++
2 files changed, 122 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h
diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
new file mode 100644
index 000000000000..76e1931f0908
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 SoC Reset Controller
+
+maintainers:
+ - Chen Wang <[email protected]>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ rstgen: reset-controller@c00 {
+ compatible = "sophgo,sg2042-reset";
+ reg = <0xc00 0xc>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/reset/sophgo,sg2042-reset.h b/include/dt-bindings/reset/sophgo,sg2042-reset.h
new file mode 100644
index 000000000000..9ab0980625c1
--- /dev/null
+++ b/include/dt-bindings/reset/sophgo,sg2042-reset.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
+#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
+
+#define RST_MAIN_AP 0
+#define RST_RISCV_CPU 1
+#define RST_RISCV_LOW_SPEED_LOGIC 2
+#define RST_RISCV_CMN 3
+#define RST_HSDMA 4
+#define RST_SYSDMA 5
+#define RST_EFUSE0 6
+#define RST_EFUSE1 7
+#define RST_RTC 8
+#define RST_TIMER 9
+#define RST_WDT 10
+#define RST_AHB_ROM0 11
+#define RST_AHB_ROM1 12
+#define RST_I2C0 13
+#define RST_I2C1 14
+#define RST_I2C2 15
+#define RST_I2C3 16
+#define RST_GPIO0 17
+#define RST_GPIO1 18
+#define RST_GPIO2 19
+#define RST_PWM 20
+#define RST_AXI_SRAM0 21
+#define RST_AXI_SRAM1 22
+#define RST_SF0 23
+#define RST_SF1 24
+#define RST_LPC 25
+#define RST_ETH0 26
+#define RST_EMMC 27
+#define RST_SD 28
+#define RST_UART0 29
+#define RST_UART1 30
+#define RST_UART2 31
+#define RST_UART3 32
+#define RST_SPI0 33
+#define RST_SPI1 34
+#define RST_DBG_I2C 35
+#define RST_PCIE0 36
+#define RST_PCIE1 37
+#define RST_DDR0 38
+#define RST_DDR1 39
+#define RST_DDR2 40
+#define RST_DDR3 41
+#define RST_FAU0 42
+#define RST_FAU1 43
+#define RST_FAU2 44
+#define RST_RXU0 45
+#define RST_RXU1 46
+#define RST_RXU2 47
+#define RST_RXU3 48
+#define RST_RXU4 49
+#define RST_RXU5 50
+#define RST_RXU6 51
+#define RST_RXU7 52
+#define RST_RXU8 53
+#define RST_RXU9 54
+#define RST_RXU10 55
+#define RST_RXU11 56
+#define RST_RXU12 57
+#define RST_RXU13 58
+#define RST_RXU14 59
+#define RST_RXU15 60
+#define RST_RXU16 61
+#define RST_RXU17 62
+#define RST_RXU18 63
+#define RST_RXU19 64
+#define RST_RXU20 65
+#define RST_RXU21 66
+#define RST_RXU22 67
+#define RST_RXU23 68
+#define RST_RXU24 69
+#define RST_RXU25 70
+#define RST_RXU26 71
+#define RST_RXU27 72
+#define RST_RXU28 73
+#define RST_RXU29 74
+#define RST_RXU30 75
+#define RST_RXU31 76
+
+#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */
--
2.25.1
From: Chen Wang <[email protected]>
Add resets property for uart0 for completeness, although it is
deasserted by default.
Signed-off-by: Chen Wang <[email protected]>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index eeb341e16bfd..81fda312f988 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -343,6 +343,7 @@ uart0: serial@7040000000 {
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rstgen RST_UART0>;
status = "disabled";
};
};
--
2.25.1
ping ~~~
On 2024/1/30 9:49, Chen Wang wrote:
> From: Chen Wang <[email protected]>
>
> This series adds reset controller support for Sophgo SG2042 using
> reset-simple driver.
>
> Thanks,
> Chen
>
> ---
>
> Changes in v3:
> This patch series is based on v6.8-rc2, which has included the missed patch I
> mentioned in v2.
> - As suggested by Philipp, drop the Kconfig for SG2042, just add a default
> y if ARCH_SOPHGO to RESET_SIMPLE.
hello, Philipp,
Can you please have a look of this, I have fixed the issue you raised in
last version, any question please feel free let me know.
Thanks,
Chen
>
> Changes in v2:
> This patch series is based on v6.8-rc1. You can simply review or test the
> patches at the link [3].
> - fixed some minor formatting issues.
> Note that if you need to pass dtb check, you need to apply a patch. This
> patch is missing in v6.8-rc1. For details, please see [2].
>
> Changes in v1:
> The patch series is based on v6.7. You can simply review or test the
> patches at the link [1].
>
> Link: https://lore.kernel.org/linux-riscv/[email protected]/ [1]
> Link: https://lore.kernel.org/linux-riscv/MA0P287MB28228572C526C5099A8BDA2DFE7B2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM/T/#u [2]
> Link: https://lore.kernel.org/linux-riscv/[email protected]/ [3]
>
> ---
>
> Chen Wang (4):
> dt-bindings: reset: sophgo: support SG2042
> reset: simple: add support for Sophgo SG2042
> riscv: dts: add reset generator for Sophgo SG2042 SoC
> riscv: dts: add resets property for uart node
>
> .../bindings/reset/sophgo,sg2042-reset.yaml | 35 ++++++++
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 9 ++
> drivers/reset/Kconfig | 3 +-
> drivers/reset/reset-simple.c | 2 +
> .../dt-bindings/reset/sophgo,sg2042-reset.h | 87 +++++++++++++++++++
> 5 files changed, 135 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h
>
>
> base-commit: 41bccc98fb7931d63d03f326a746ac4d429c1dd3
ping ~~~
On 2024/1/30 9:50, Chen Wang wrote:
> From: Chen Wang <[email protected]>
>
> Reuse reset-simple driver for the Sophgo SG2042 reset generator.
>
> Signed-off-by: Chen Wang <[email protected]>
> ---
> drivers/reset/Kconfig | 3 ++-
> drivers/reset/reset-simple.c | 2 ++
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index ccd59ddd7610..2034f69d5953 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -213,7 +213,7 @@ config RESET_SCMI
>
> config RESET_SIMPLE
> bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
> - default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
> + default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
> depends on HAS_IOMEM
> help
> This enables a simple reset controller driver for reset lines that
> @@ -228,6 +228,7 @@ config RESET_SIMPLE
> - RCC reset controller in STM32 MCUs
> - Allwinner SoCs
> - SiFive FU740 SoCs
> + - Sophgo SoCs
>
> config RESET_SOCFPGA
> bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
> diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
> index 818cabcc9fb7..276067839830 100644
> --- a/drivers/reset/reset-simple.c
> +++ b/drivers/reset/reset-simple.c
> @@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
> { .compatible = "snps,dw-high-reset" },
> { .compatible = "snps,dw-low-reset",
> .data = &reset_simple_active_low },
> + { .compatible = "sophgo,sg2042-reset",
> + .data = &reset_simple_active_low },
> { /* sentinel */ },
> };
>
hello, Philipp,
Can you please have a look of this, I have fixed the issue you raised in
last version, any question please feel free let me know.
BTW, will you pick this for v6.9 if it is ok to you.
Thanks,
Chen
On Di, 2024-01-30 at 09:50 +0800, Chen Wang wrote:
> From: Chen Wang <[email protected]>
>
> Reuse reset-simple driver for the Sophgo SG2042 reset generator.
>
> Signed-off-by: Chen Wang <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
regards
Philipp
Hi Chen,
On Do, 2024-02-15 at 16:59 +0800, Chen Wang wrote:
> ping ~~~
>
[...]
>
> hello, Philipp,
>
> Can you please have a look of this, I have fixed the issue you raised in
> last version, any question please feel free let me know.
>
> BTW, will you pick this for v6.9 if it is ok to you.
Yes, I intend to do this tomorrow.
regards
Philipp
On 2024/2/15 20:46, Philipp Zabel wrote:
> Hi Chen,
>
> On Do, 2024-02-15 at 16:59 +0800, Chen Wang wrote:
>> ping ~~~
>>
> [...]
>> hello, Philipp,
>>
>> Can you please have a look of this, I have fixed the issue you raised in
>> last version, any question please feel free let me know.
>>
>> BTW, will you pick this for v6.9 if it is ok to you.
> Yes, I intend to do this tomorrow.
>
> regards
> Philipp
Thank you Philipp. One more question, when you pick this patch (I mean
2/4), will you pick the bindings (1/4 of this patchset). I will hanlde
other patches about dts.
On Tue, 30 Jan 2024 09:49:08 +0800, Chen Wang wrote:
> From: Chen Wang <[email protected]>
>
> This series adds reset controller support for Sophgo SG2042 using
> reset-simple driver.
>
> Thanks,
> Chen
>
> [...]
Applied patches 1-2 to reset/next, thanks!
[1/4] dt-bindings: reset: sophgo: support SG2042
https://git.pengutronix.de/cgit/pza/linux/commit/?id=41197eb5f993
[2/4] reset: simple: add support for Sophgo SG2042
https://git.pengutronix.de/cgit/pza/linux/commit/?id=a6166a4da5e4
regards
Philipp
On 2024/2/21 19:14, Philipp Zabel wrote:
> On Tue, 30 Jan 2024 09:49:08 +0800, Chen Wang wrote:
>> From: Chen Wang <[email protected]>
>>
>> This series adds reset controller support for Sophgo SG2042 using
>> reset-simple driver.
>>
>> Thanks,
>> Chen
>>
>> [...]
> Applied patches 1-2 to reset/next, thanks!
>
> [1/4] dt-bindings: reset: sophgo: support SG2042
> https://git.pengutronix.de/cgit/pza/linux/commit/?id=41197eb5f993
> [2/4] reset: simple: add support for Sophgo SG2042
> https://git.pengutronix.de/cgit/pza/linux/commit/?id=a6166a4da5e4
>
> regards
> Philipp
>
Thank you Philipp.
LGTM
Reviewed-by: Inochi Amaoto <[email protected]>
On Tue, Jan 30, 2024 at 09:50:32AM +0800, Chen Wang wrote:
> From: Chen Wang <[email protected]>
>
> Add reset generator node to device tree for SG2042.
>
> Signed-off-by: Chen Wang <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index ead1cc35d88b..eeb341e16bfd 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -6,6 +6,8 @@
> /dts-v1/;
> #include <dt-bindings/interrupt-controller/irq.h>
>
> +#include <dt-bindings/reset/sophgo,sg2042-reset.h>
> +
> #include "sg2042-cpus.dtsi"
>
> / {
> @@ -327,6 +329,12 @@ intc: interrupt-controller@7090000000 {
> riscv,ndev = <224>;
> };
>
> + rstgen: reset-controller@7030013000 {
> + compatible = "sophgo,sg2042-reset";
> + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
> + #reset-cells = <1>;
> + };
> +
> uart0: serial@7040000000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
> --
> 2.25.1
>
LGTM
Reviewed-by: Inochi Amaoto <[email protected]>
On Tue, Jan 30, 2024 at 09:50:51AM +0800, Chen Wang wrote:
> From: Chen Wang <[email protected]>
>
> Add resets property for uart0 for completeness, although it is
> deasserted by default.
>
> Signed-off-by: Chen Wang <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index eeb341e16bfd..81fda312f988 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -343,6 +343,7 @@ uart0: serial@7040000000 {
> clock-frequency = <500000000>;
> reg-shift = <2>;
> reg-io-width = <4>;
> + resets = <&rstgen RST_UART0>;
> status = "disabled";
> };
> };
> --
> 2.25.1
>
On Tue, 30 Jan 2024 09:49:08 +0800, Chen Wang wrote:
> From: Chen Wang <[email protected]>
>
> This series adds reset controller support for Sophgo SG2042 using
> reset-simple driver.
>
> Thanks,
> Chen
>
> [...]
Applied to sophgo/for-next, thanks!
[3/4] riscv: dts: add reset generator for Sophgo SG2042 SoC
https://github.com/sophgo/linux/commit/1ce7587e507e1762df1dadc22affcd41376040d5
[4/4] riscv: dts: add resets property for uart node
https://github.com/sophgo/linux/commit/08573ba006ab7bc29c183e0b3c362a0b34f1d87b
Thanks,
Inochi
On Mon, 29 Jan 2024 17:49:45 PST (-0800), [email protected] wrote:
> From: Chen Wang <[email protected]>
>
> Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.
>
> Signed-off-by: Chen Wang <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/reset/sophgo,sg2042-reset.yaml | 35 ++++++++
> .../dt-bindings/reset/sophgo,sg2042-reset.h | 87 +++++++++++++++++++
> 2 files changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h
>
> diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> new file mode 100644
> index 000000000000..76e1931f0908
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> @@ -0,0 +1,35 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo SG2042 SoC Reset Controller
> +
> +maintainers:
> + - Chen Wang <[email protected]>
> +
> +properties:
> + compatible:
> + const: sophgo,sg2042-reset
> +
> + reg:
> + maxItems: 1
> +
> + "#reset-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + rstgen: reset-controller@c00 {
> + compatible = "sophgo,sg2042-reset";
> + reg = <0xc00 0xc>;
> + #reset-cells = <1>;
> + };
> diff --git a/include/dt-bindings/reset/sophgo,sg2042-reset.h b/include/dt-bindings/reset/sophgo,sg2042-reset.h
> new file mode 100644
> index 000000000000..9ab0980625c1
> --- /dev/null
> +++ b/include/dt-bindings/reset/sophgo,sg2042-reset.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/*
> + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
> +#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_
> +
> +#define RST_MAIN_AP 0
> +#define RST_RISCV_CPU 1
> +#define RST_RISCV_LOW_SPEED_LOGIC 2
> +#define RST_RISCV_CMN 3
> +#define RST_HSDMA 4
> +#define RST_SYSDMA 5
> +#define RST_EFUSE0 6
> +#define RST_EFUSE1 7
> +#define RST_RTC 8
> +#define RST_TIMER 9
> +#define RST_WDT 10
> +#define RST_AHB_ROM0 11
> +#define RST_AHB_ROM1 12
> +#define RST_I2C0 13
> +#define RST_I2C1 14
> +#define RST_I2C2 15
> +#define RST_I2C3 16
> +#define RST_GPIO0 17
> +#define RST_GPIO1 18
> +#define RST_GPIO2 19
> +#define RST_PWM 20
> +#define RST_AXI_SRAM0 21
> +#define RST_AXI_SRAM1 22
> +#define RST_SF0 23
> +#define RST_SF1 24
> +#define RST_LPC 25
> +#define RST_ETH0 26
> +#define RST_EMMC 27
> +#define RST_SD 28
> +#define RST_UART0 29
> +#define RST_UART1 30
> +#define RST_UART2 31
> +#define RST_UART3 32
> +#define RST_SPI0 33
> +#define RST_SPI1 34
> +#define RST_DBG_I2C 35
> +#define RST_PCIE0 36
> +#define RST_PCIE1 37
> +#define RST_DDR0 38
> +#define RST_DDR1 39
> +#define RST_DDR2 40
> +#define RST_DDR3 41
> +#define RST_FAU0 42
> +#define RST_FAU1 43
> +#define RST_FAU2 44
> +#define RST_RXU0 45
> +#define RST_RXU1 46
> +#define RST_RXU2 47
> +#define RST_RXU3 48
> +#define RST_RXU4 49
> +#define RST_RXU5 50
> +#define RST_RXU6 51
> +#define RST_RXU7 52
> +#define RST_RXU8 53
> +#define RST_RXU9 54
> +#define RST_RXU10 55
> +#define RST_RXU11 56
> +#define RST_RXU12 57
> +#define RST_RXU13 58
> +#define RST_RXU14 59
> +#define RST_RXU15 60
> +#define RST_RXU16 61
> +#define RST_RXU17 62
> +#define RST_RXU18 63
> +#define RST_RXU19 64
> +#define RST_RXU20 65
> +#define RST_RXU21 66
> +#define RST_RXU22 67
> +#define RST_RXU23 68
> +#define RST_RXU24 69
> +#define RST_RXU25 70
> +#define RST_RXU26 71
> +#define RST_RXU27 72
> +#define RST_RXU28 73
> +#define RST_RXU29 74
> +#define RST_RXU30 75
> +#define RST_RXU31 76
> +
> +#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */
This is now
Fixes: 1ce7587e507e ("riscv: dts: add reset generator for Sophgo SG2042 SoC")
which landed in Linus' tree. Looks like that went up via Inochi and
Arnd. I don't have that in my for-next yet, so I'm just stashing away
this patch for my tester.
I'm happy to pick this up if folks want, but it'll probably be cleaner
somewhere else.
On 2024/3/14 23:17, Palmer Dabbelt wrote:
> On Mon, 29 Jan 2024 17:49:45 PST (-0800), [email protected] wrote:
>> From: Chen Wang <[email protected]>
>>
>> Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.
>>
>>
[...]
>
> This is now
>
> Fixes: 1ce7587e507e ("riscv: dts: add reset generator for Sophgo
> SG2042 SoC")
>
> which landed in Linus' tree. Looks like that went up via Inochi and
> Arnd. I don't have that in my for-next yet, so I'm just stashing away
> this patch for my tester.
>
> I'm happy to pick this up if folks want, but it'll probably be cleaner
> somewhere else.
Hi, Palmer,
I see Arnd has prepared a tag
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/tag/?h=soc-late-6.9
which contains the bindings part changes for sg2042 reset driver.
Let's wait for Arnd to submit, although I haven't seen this in Linus's
tree and not sure if Arnd have submitted this.
Thanks,
Chen
On Thu, 14 Mar 2024 17:15:11 PDT (-0700), [email protected] wrote:
>
> On 2024/3/14 23:17, Palmer Dabbelt wrote:
>> On Mon, 29 Jan 2024 17:49:45 PST (-0800), [email protected] wrote:
>>> From: Chen Wang <[email protected]>
>>>
>>> Add bindings for the reset generator on the SOPHGO SG2042 RISC-V SoC.
>>>
>>>
> [...]
>>
>> This is now
>>
>> Fixes: 1ce7587e507e ("riscv: dts: add reset generator for Sophgo
>> SG2042 SoC")
>>
>> which landed in Linus' tree. Looks like that went up via Inochi and
>> Arnd. I don't have that in my for-next yet, so I'm just stashing away
>> this patch for my tester.
>>
>> I'm happy to pick this up if folks want, but it'll probably be cleaner
>> somewhere else.
>
> Hi, Palmer,
>
> I see Arnd has prepared a tag
> https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/tag/?h=soc-late-6.9
> which contains the bindings part changes for sg2042 reset driver.
>
> Let's wait for Arnd to submit, although I haven't seen this in Linus's
> tree and not sure if Arnd have submitted this.
OK, sounds good. I realized I dropped the ball on a fix, so I'm not
sending a PR this morning either way (I hadn't picked this up yet,
though, so shouldn't make much of a difference).
I'll just leave this in my not-for-next until it gets sorted out.
Thanks!
>
> Thanks,
>
> Chen
On 2024/3/16 1:21, Palmer Dabbelt wrote:
> [...]
>>>
>>> This is now
>>>
>>> Fixes: 1ce7587e507e ("riscv: dts: add reset generator for Sophgo
>>> SG2042 SoC")
>>>
>>> which landed in Linus' tree. Looks like that went up via Inochi and
>>> Arnd. I don't have that in my for-next yet, so I'm just stashing away
>>> this patch for my tester.
>>>
>>> I'm happy to pick this up if folks want, but it'll probably be cleaner
>>> somewhere else.
>>
>> Hi, Palmer,
>>
>> I see Arnd has prepared a tag
>> https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/tag/?h=soc-late-6.9
>>
>> which contains the bindings part changes for sg2042 reset driver.
>>
>> Let's wait for Arnd to submit, although I haven't seen this in Linus's
>> tree and not sure if Arnd have submitted this.
>
> OK, sounds good. I realized I dropped the ball on a fix, so I'm not
> sending a PR this morning either way (I hadn't picked this up yet,
> though, so shouldn't make much of a difference).
>
> I'll just leave this in my not-for-next until it gets sorted out.
FYI, I see soc-late-6.9 has been on the master of Linus's tree.
>
> Thanks!
>
>>
>> Thanks,
>>
>> Chen
Hello:
This series was applied to riscv/linux.git (fixes)
by Inochi Amaoto <[email protected]>:
On Tue, 30 Jan 2024 09:49:08 +0800 you wrote:
> From: Chen Wang <[email protected]>
>
> This series adds reset controller support for Sophgo SG2042 using
> reset-simple driver.
>
> Thanks,
> Chen
>
> [...]
Here is the summary with links:
- [v3,1/4] dt-bindings: reset: sophgo: support SG2042
(no matching commit)
- [v3,2/4] reset: simple: add support for Sophgo SG2042
(no matching commit)
- [v3,3/4] riscv: dts: add reset generator for Sophgo SG2042 SoC
https://git.kernel.org/riscv/c/1ce7587e507e
- [v3,4/4] riscv: dts: add resets property for uart node
https://git.kernel.org/riscv/c/08573ba006ab
You are awesome, thank you!
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