PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
are found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane
Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
This series adds support for enabling the same
DTS patch is based on the crashdump series
https://lore.kernel.org/linux-arm-kernel/[email protected]/
Devi Priya (7):
dt-bindings: PCI: qcom: Add IPQ9574 specific compatible
PCI: qcom: Add IPQ9574 PCIe support
dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 compatible
phy: qcom-qmp-pcie: Add support for IPQ9574 platform
dt-bindings: clock: Add PCIe pipe clock definitions
clk: qcom: gcc-ipq9574: Add PCIe related clocks
arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes
.../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++-
.../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 28 +
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 +++++++++++++++++-
drivers/clk/qcom/gcc-ipq9574.c | 76 +++
drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 309 ++++++++++++
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 26 +-
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 3 +
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 276 +++++-----
10 files changed, 1264 insertions(+), 150 deletions(-)
base-commit: 3ebb0ac55efaf1d0fb1b106f852c114e5021f7eb
--
2.17.1
Document the compatible for IPQ9574
Signed-off-by: Devi Priya <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 872817d6d2bd..dabdf2684e2d 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,pcie-ipq8064-v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
+ - qcom,pcie-ipq9574
- qcom,pcie-msm8996
- qcom,pcie-qcs404
- qcom,pcie-sa8540p
@@ -44,11 +45,11 @@ properties:
reg:
minItems: 4
- maxItems: 5
+ maxItems: 6
reg-names:
minItems: 4
- maxItems: 5
+ maxItems: 6
interrupts:
minItems: 1
@@ -105,6 +106,8 @@ properties:
items:
- const: pciephy
+ msi-parent: true
+
power-domains:
maxItems: 1
@@ -173,6 +176,27 @@ allOf:
- const: parf # Qualcomm specific registers
- const: config # PCIe configuration space
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq9574
+ then:
+ properties:
+ reg:
+ minItems: 5
+ maxItems: 6
+ reg-names:
+ minItems: 5
+ items:
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: parf # Qualcomm specific registers
+ - const: config # PCIe configuration space
+ - const: aggr_noc #PCIe aggr_noc
+
- if:
properties:
compatible:
@@ -365,6 +389,39 @@ allOf:
- const: ahb # AHB Reset
- const: axi_m_sticky # AXI Master Sticky reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq9574
+ then:
+ properties:
+ clocks:
+ minItems: 6
+ maxItems: 6
+ clock-names:
+ items:
+ - const: ahb # AHB clock
+ - const: aux # Auxiliary clock
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: axi_bridge # AXI bridge clock
+ - const: rchng
+ resets:
+ minItems: 8
+ maxItems: 8
+ reset-names:
+ items:
+ - const: pipe # PIPE reset
+ - const: sticky # Core Sticky reset
+ - const: axi_s_sticky # AXI Slave Sticky reset
+ - const: axi_s # AXI Slave reset
+ - const: axi_m_sticky # AXI Master Sticky reset
+ - const: axi_m # AXI Master reset
+ - const: aux # AUX Reset
+ - const: ahb # AHB Reset
+
- if:
properties:
compatible:
@@ -681,6 +738,16 @@ allOf:
- interconnects
- interconnect-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq9574
+ then:
+ required:
+ - msi-parent
+
- if:
not:
properties:
@@ -693,6 +760,7 @@ allOf:
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
+ - qcom,pcie-ipq9574
- qcom,pcie-qcs404
then:
required:
--
2.17.1
Adding PCIe support for IPQ9574 SoC
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
1 file changed, 119 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index a232b04af048..57606c113d45 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
struct reset_control *rst;
};
+struct qcom_pcie_resources_1_27_0 {
+ struct clk_bulk_data *clks;
+ struct reset_control *rst;
+ int num_clks;
+};
+
union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
@@ -201,6 +207,7 @@ union qcom_pcie_resources {
struct qcom_pcie_resources_2_4_0 v2_4_0;
struct qcom_pcie_resources_2_7_0 v2_7_0;
struct qcom_pcie_resources_2_9_0 v2_9_0;
+ struct qcom_pcie_resources_1_27_0 v1_27_0;
};
struct qcom_pcie;
@@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
return 0;
}
+static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+
+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
+ if (res->clks < 0)
+ return res->num_clks;
+
+ res->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(res->rst))
+ return PTR_ERR(res->rst);
+
+ return 0;
+}
+
+static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
+
+ clk_bulk_disable_unprepare(res->num_clks, res->clks);
+}
+
+static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
+ struct device *dev = pcie->pci->dev;
+ int ret;
+
+ ret = reset_control_assert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset assert failed (%d)\n", ret);
+ return ret;
+ }
+
+ /*
+ * Delay periods before and after reset deassert are working values
+ * from downstream Codeaurora kernel
+ */
+ usleep_range(2000, 2500);
+
+ ret = reset_control_deassert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset deassert failed (%d)\n", ret);
+ return ret;
+ }
+
+ usleep_range(2000, 2500);
+
+ return clk_bulk_prepare_enable(res->num_clks, res->clks);
+}
+
+static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
+{
+ struct dw_pcie *pci = pcie->pci;
+ u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ u32 val;
+ int i;
+
+ writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
+
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
+ writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
+ pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+ writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
+ GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
+ pci->dbi_base + GEN3_RELATED_OFF);
+
+ writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
+ SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
+ AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
+ pcie->parf + PCIE20_PARF_SYS_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
+
+ dw_pcie_dbi_ro_wr_en(pci);
+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+
+ val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
+ val &= ~PCI_EXP_LNKCAP_ASPMS;
+ writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
+
+ writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
+ PCI_EXP_DEVCTL2);
+
+ for (i = 0; i < 256; i++)
+ writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
+
+ return 0;
+}
+
static int qcom_pcie_link_up(struct dw_pcie *pci)
{
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
@@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
};
+/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
+static const struct qcom_pcie_ops ops_1_27_0 = {
+ .get_resources = qcom_pcie_get_resources_1_27_0,
+ .init = qcom_pcie_init_1_27_0,
+ .post_init = qcom_pcie_post_init_1_27_0,
+ .deinit = qcom_pcie_deinit_1_27_0,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+};
+
static const struct qcom_pcie_cfg cfg_1_0_0 = {
.ops = &ops_1_0_0,
};
@@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
.ops = &ops_2_9_0,
};
+static const struct qcom_pcie_cfg cfg_1_27_0 = {
+ .ops = &ops_1_27_0,
+};
+
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
.start_link = qcom_pcie_start_link,
@@ -1829,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
+ { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
--
2.17.1
Add the compatible for the PCIe QMP PHYs found on IPQ9574
Signed-off-by: Devi Priya <[email protected]>
---
.../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
index 62045dcfb20c..1131f0d87a9c 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
@@ -22,6 +22,8 @@ properties:
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
+ - qcom,ipq9574-qmp-gen3x1-pcie-phy
+ - qcom,ipq9574-qmp-gen3x2-pcie-phy
- qcom,msm8998-qmp-pcie-phy
- qcom,sc8180x-qmp-pcie-phy
- qcom,sdm845-qhp-pcie-phy
@@ -165,6 +167,30 @@ allOf:
- const: phy
- const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq9574-qmp-gen3x1-pcie-phy
+ - qcom,ipq9574-qmp-gen3x2-pcie-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: anoc_lane
+ - const: snoc_lane
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
- if:
properties:
compatible:
@@ -203,6 +229,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,ipq9574-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8450-qmp-gen4x2-pcie-phy
@@ -224,6 +251,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,ipq9574-qmp-gen3x1-pcie-phy
- qcom,sc8180x-qmp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
--
2.17.1
Add support for a single-lane and two-lane PCIe PHYs
found on Qualcomm IPQ9574 platform.
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 309 ++++++++++++++++++
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 26 +-
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 3 +
3 files changed, 332 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 5182aeac43ee..92561a1ba279 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -515,6 +515,250 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
};
+static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xFF),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xAB),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xD4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xA0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xA0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xB4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7D),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xFF),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xAB),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xD4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xA0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xA0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xB4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7D),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_pcie_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1C),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1E),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0C),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xC8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xB1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xC8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xB1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xF0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2F),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xD3),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xC0),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xAA),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0D),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0D),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0B),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1A),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xC1),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0D),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xAA),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1D),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0B),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2A),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xC1),
+};
+
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -1866,6 +2110,10 @@ static const char * const ipq8074_pciephy_clk_l[] = {
"aux", "cfg_ahb",
};
+static const char * const ipq9574_pciephy_clk_l[] = {
+ "aux", "cfg_ahb", "anoc_lane", "snoc_lane",
+};
+
static const char * const msm8996_phy_clk_l[] = {
"aux", "cfg_ahb", "ref",
};
@@ -1998,6 +2246,61 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.phy_status = PHYSTATUS,
};
+static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = {
+ .lanes = 1,
+
+ .tbls = {
+ .serdes = ipq9574_gen3x1_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl),
+ .tx = ipq9574_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(ipq9574_pcie_tx_tbl),
+ .rx = ipq9574_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
+ .pcs = ipq9574_gen3x1_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl),
+ .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl),
+ },
+ .clk_list = ipq9574_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq9574_pciephy_clk_l),
+ .reset_list = ipq8074_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+ .vreg_list = NULL,
+ .num_vregs = 0,
+ .regs = pciephy_v4_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+};
+
+static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {
+ .lanes = 2,
+
+ .tbls = {
+ .serdes = ipq9574_gen3x2_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
+ .tx = ipq9574_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(ipq9574_pcie_tx_tbl),
+ .rx = ipq9574_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
+ .pcs = ipq9574_gen3x2_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl),
+ .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
+ },
+ .clk_list = ipq9574_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq9574_pciephy_clk_l),
+ .reset_list = ipq8074_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+ .vreg_list = NULL,
+ .num_vregs = 0,
+ .regs = pciephy_v4_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+
+};
+
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
.lanes = 1,
@@ -3156,6 +3459,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
}, {
.compatible = "qcom,ipq8074-qmp-pcie-phy",
.data = &ipq8074_pciephy_cfg,
+ }, {
+ .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
+ .data = &ipq9574_gen3x1_pciephy_cfg,
+ }, {
+ .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
+ .data = &ipq9574_gen3x2_pciephy_cfg,
}, {
.compatible = "qcom,msm8998-qmp-pcie-phy",
.data = &msm8998_pciephy_cfg,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
index a469ae2a10a1..5f002b150cea 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
@@ -8,11 +8,25 @@
#define QCOM_PHY_QMP_PCS_PCIE_V5_H_
/* Only for QMP V5 PHY - PCS_PCIE registers */
-#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
-#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
-#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
-#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
-#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
-#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
+#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
+#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
+#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
+#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44
+#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48
+#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c
+#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50
+#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
+#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4
+#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
+#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0
+#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
index ad326e301a3a..231e59364e31 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
@@ -8,6 +8,9 @@
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
+#define QSERDES_PLL_SSC_EN_CENTER 0x010
+#define QSERDES_PLL_SSC_ADJ_PER1 0x014
+#define QSERDES_PLL_SSC_ADJ_PER2 0x018
#define QSERDES_PLL_SSC_PER1 0x01c
#define QSERDES_PLL_SSC_PER2 0x020
#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
--
2.17.1
Add PCIe clock definitions for IPQ9574 SoC
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 276 ++++++++++---------
1 file changed, 140 insertions(+), 136 deletions(-)
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index feedfdd5e00a..c89e96d568c6 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -74,140 +74,144 @@
#define GCC_PCIE3_AXI_S_BRIDGE_CLK 65
#define GCC_PCIE3_AXI_S_CLK 66
#define PCIE0_PIPE_CLK_SRC 67
-#define PCIE1_PIPE_CLK_SRC 68
-#define PCIE2_PIPE_CLK_SRC 69
-#define PCIE3_PIPE_CLK_SRC 70
-#define PCIE_AUX_CLK_SRC 71
-#define GCC_PCIE0_AUX_CLK 72
-#define GCC_PCIE1_AUX_CLK 73
-#define GCC_PCIE2_AUX_CLK 74
-#define GCC_PCIE3_AUX_CLK 75
-#define PCIE0_RCHNG_CLK_SRC 76
-#define GCC_PCIE0_RCHNG_CLK 77
-#define PCIE1_RCHNG_CLK_SRC 78
-#define GCC_PCIE1_RCHNG_CLK 79
-#define PCIE2_RCHNG_CLK_SRC 80
-#define GCC_PCIE2_RCHNG_CLK 81
-#define PCIE3_RCHNG_CLK_SRC 82
-#define GCC_PCIE3_RCHNG_CLK 83
-#define GCC_PCIE0_AHB_CLK 84
-#define GCC_PCIE1_AHB_CLK 85
-#define GCC_PCIE2_AHB_CLK 86
-#define GCC_PCIE3_AHB_CLK 87
-#define USB0_AUX_CLK_SRC 88
-#define GCC_USB0_AUX_CLK 89
-#define USB0_MASTER_CLK_SRC 90
-#define GCC_USB0_MASTER_CLK 91
-#define GCC_SNOC_USB_CLK 92
-#define GCC_ANOC_USB_AXI_CLK 93
-#define USB0_MOCK_UTMI_CLK_SRC 94
-#define USB0_MOCK_UTMI_DIV_CLK_SRC 95
-#define GCC_USB0_MOCK_UTMI_CLK 96
-#define USB0_PIPE_CLK_SRC 97
-#define GCC_USB0_PHY_CFG_AHB_CLK 98
-#define SDCC1_APPS_CLK_SRC 99
-#define GCC_SDCC1_APPS_CLK 100
-#define SDCC1_ICE_CORE_CLK_SRC 101
-#define GCC_SDCC1_ICE_CORE_CLK 102
-#define GCC_SDCC1_AHB_CLK 103
-#define PCNOC_BFDCD_CLK_SRC 104
-#define GCC_NSSCFG_CLK 105
-#define GCC_NSSNOC_NSSCC_CLK 106
-#define GCC_NSSCC_CLK 107
-#define GCC_NSSNOC_PCNOC_1_CLK 108
-#define GCC_QDSS_DAP_AHB_CLK 109
-#define GCC_QDSS_CFG_AHB_CLK 110
-#define GCC_QPIC_AHB_CLK 111
-#define GCC_QPIC_CLK 112
-#define GCC_BLSP1_AHB_CLK 113
-#define GCC_MDIO_AHB_CLK 114
-#define GCC_PRNG_AHB_CLK 115
-#define GCC_UNIPHY0_AHB_CLK 116
-#define GCC_UNIPHY1_AHB_CLK 117
-#define GCC_UNIPHY2_AHB_CLK 118
-#define GCC_CMN_12GPLL_AHB_CLK 119
-#define GCC_CMN_12GPLL_APU_CLK 120
-#define SYSTEM_NOC_BFDCD_CLK_SRC 121
-#define GCC_NSSNOC_SNOC_CLK 122
-#define GCC_NSSNOC_SNOC_1_CLK 123
-#define GCC_QDSS_ETR_USB_CLK 124
-#define WCSS_AHB_CLK_SRC 125
-#define GCC_Q6_AHB_CLK 126
-#define GCC_Q6_AHB_S_CLK 127
-#define GCC_WCSS_ECAHB_CLK 128
-#define GCC_WCSS_ACMT_CLK 129
-#define GCC_SYS_NOC_WCSS_AHB_CLK 130
-#define WCSS_AXI_M_CLK_SRC 131
-#define GCC_ANOC_WCSS_AXI_M_CLK 132
-#define QDSS_AT_CLK_SRC 133
-#define GCC_Q6SS_ATBM_CLK 134
-#define GCC_WCSS_DBG_IFC_ATB_CLK 135
-#define GCC_NSSNOC_ATB_CLK 136
-#define GCC_QDSS_AT_CLK 137
-#define GCC_SYS_NOC_AT_CLK 138
-#define GCC_PCNOC_AT_CLK 139
-#define GCC_USB0_EUD_AT_CLK 140
-#define GCC_QDSS_EUD_AT_CLK 141
-#define QDSS_STM_CLK_SRC 142
-#define GCC_QDSS_STM_CLK 143
-#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 144
-#define QDSS_TRACECLKIN_CLK_SRC 145
-#define GCC_QDSS_TRACECLKIN_CLK 146
-#define QDSS_TSCTR_CLK_SRC 147
-#define GCC_Q6_TSCTR_1TO2_CLK 148
-#define GCC_WCSS_DBG_IFC_NTS_CLK 149
-#define GCC_QDSS_TSCTR_DIV2_CLK 150
-#define GCC_QDSS_TS_CLK 151
-#define GCC_QDSS_TSCTR_DIV4_CLK 152
-#define GCC_NSS_TS_CLK 153
-#define GCC_QDSS_TSCTR_DIV8_CLK 154
-#define GCC_QDSS_TSCTR_DIV16_CLK 155
-#define GCC_Q6SS_PCLKDBG_CLK 156
-#define GCC_Q6SS_TRIG_CLK 157
-#define GCC_WCSS_DBG_IFC_APB_CLK 158
-#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159
-#define GCC_QDSS_DAP_CLK 160
-#define GCC_QDSS_APB2JTAG_CLK 161
-#define GCC_QDSS_TSCTR_DIV3_CLK 162
-#define QPIC_IO_MACRO_CLK_SRC 163
-#define GCC_QPIC_IO_MACRO_CLK 164
-#define Q6_AXI_CLK_SRC 165
-#define GCC_Q6_AXIM_CLK 166
-#define GCC_WCSS_Q6_TBU_CLK 167
-#define GCC_MEM_NOC_Q6_AXI_CLK 168
-#define Q6_AXIM2_CLK_SRC 169
-#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170
-#define GCC_NSSNOC_MEMNOC_CLK 171
-#define GCC_NSSNOC_MEM_NOC_1_CLK 172
-#define GCC_NSS_TBU_CLK 173
-#define GCC_MEM_NOC_NSSNOC_CLK 174
-#define LPASS_AXIM_CLK_SRC 175
-#define LPASS_SWAY_CLK_SRC 176
-#define ADSS_PWM_CLK_SRC 177
-#define GCC_ADSS_PWM_CLK 178
-#define GP1_CLK_SRC 179
-#define GP2_CLK_SRC 180
-#define GP3_CLK_SRC 181
-#define DDRSS_SMS_SLOW_CLK_SRC 182
-#define GCC_XO_CLK_SRC 183
-#define GCC_XO_CLK 184
-#define GCC_NSSNOC_QOSGEN_REF_CLK 185
-#define GCC_NSSNOC_TIMEOUT_REF_CLK 186
-#define GCC_XO_DIV4_CLK 187
-#define GCC_UNIPHY0_SYS_CLK 188
-#define GCC_UNIPHY1_SYS_CLK 189
-#define GCC_UNIPHY2_SYS_CLK 190
-#define GCC_CMN_12GPLL_SYS_CLK 191
-#define GCC_NSSNOC_XO_DCD_CLK 192
-#define GCC_Q6SS_BOOT_CLK 193
-#define UNIPHY_SYS_CLK_SRC 194
-#define NSS_TS_CLK_SRC 195
-#define GCC_ANOC_PCIE0_1LANE_M_CLK 196
-#define GCC_ANOC_PCIE1_1LANE_M_CLK 197
-#define GCC_ANOC_PCIE2_2LANE_M_CLK 198
-#define GCC_ANOC_PCIE3_2LANE_M_CLK 199
-#define GCC_SNOC_PCIE0_1LANE_S_CLK 200
-#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
-#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
-#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
+#define GCC_PCIE0_PIPE_CLK 68
+#define PCIE1_PIPE_CLK_SRC 69
+#define GCC_PCIE1_PIPE_CLK 70
+#define PCIE2_PIPE_CLK_SRC 71
+#define GCC_PCIE2_PIPE_CLK 72
+#define PCIE3_PIPE_CLK_SRC 73
+#define GCC_PCIE3_PIPE_CLK 74
+#define PCIE_AUX_CLK_SRC 75
+#define GCC_PCIE0_AUX_CLK 76
+#define GCC_PCIE1_AUX_CLK 77
+#define GCC_PCIE2_AUX_CLK 78
+#define GCC_PCIE3_AUX_CLK 79
+#define PCIE0_RCHNG_CLK_SRC 80
+#define GCC_PCIE0_RCHNG_CLK 81
+#define PCIE1_RCHNG_CLK_SRC 82
+#define GCC_PCIE1_RCHNG_CLK 83
+#define PCIE2_RCHNG_CLK_SRC 84
+#define GCC_PCIE2_RCHNG_CLK 85
+#define PCIE3_RCHNG_CLK_SRC 86
+#define GCC_PCIE3_RCHNG_CLK 87
+#define GCC_PCIE0_AHB_CLK 88
+#define GCC_PCIE1_AHB_CLK 89
+#define GCC_PCIE2_AHB_CLK 90
+#define GCC_PCIE3_AHB_CLK 91
+#define USB0_AUX_CLK_SRC 92
+#define GCC_USB0_AUX_CLK 93
+#define USB0_MASTER_CLK_SRC 94
+#define GCC_USB0_MASTER_CLK 95
+#define GCC_SNOC_USB_CLK 96
+#define GCC_ANOC_USB_AXI_CLK 97
+#define USB0_MOCK_UTMI_CLK_SRC 98
+#define USB0_MOCK_UTMI_DIV_CLK_SRC 99
+#define GCC_USB0_MOCK_UTMI_CLK 100
+#define USB0_PIPE_CLK_SRC 101
+#define GCC_USB0_PHY_CFG_AHB_CLK 102
+#define SDCC1_APPS_CLK_SRC 103
+#define GCC_SDCC1_APPS_CLK 104
+#define SDCC1_ICE_CORE_CLK_SRC 105
+#define GCC_SDCC1_ICE_CORE_CLK 106
+#define GCC_SDCC1_AHB_CLK 107
+#define PCNOC_BFDCD_CLK_SRC 108
+#define GCC_NSSCFG_CLK 109
+#define GCC_NSSNOC_NSSCC_CLK 110
+#define GCC_NSSCC_CLK 111
+#define GCC_NSSNOC_PCNOC_1_CLK 112
+#define GCC_QDSS_DAP_AHB_CLK 113
+#define GCC_QDSS_CFG_AHB_CLK 114
+#define GCC_QPIC_AHB_CLK 115
+#define GCC_QPIC_CLK 116
+#define GCC_BLSP1_AHB_CLK 117
+#define GCC_MDIO_AHB_CLK 118
+#define GCC_PRNG_AHB_CLK 119
+#define GCC_UNIPHY0_AHB_CLK 120
+#define GCC_UNIPHY1_AHB_CLK 121
+#define GCC_UNIPHY2_AHB_CLK 122
+#define GCC_CMN_12GPLL_AHB_CLK 123
+#define GCC_CMN_12GPLL_APU_CLK 124
+#define SYSTEM_NOC_BFDCD_CLK_SRC 125
+#define GCC_NSSNOC_SNOC_CLK 126
+#define GCC_NSSNOC_SNOC_1_CLK 127
+#define GCC_QDSS_ETR_USB_CLK 128
+#define WCSS_AHB_CLK_SRC 129
+#define GCC_Q6_AHB_CLK 130
+#define GCC_Q6_AHB_S_CLK 131
+#define GCC_WCSS_ECAHB_CLK 132
+#define GCC_WCSS_ACMT_CLK 133
+#define GCC_SYS_NOC_WCSS_AHB_CLK 134
+#define WCSS_AXI_M_CLK_SRC 135
+#define GCC_ANOC_WCSS_AXI_M_CLK 136
+#define QDSS_AT_CLK_SRC 137
+#define GCC_Q6SS_ATBM_CLK 138
+#define GCC_WCSS_DBG_IFC_ATB_CLK 139
+#define GCC_NSSNOC_ATB_CLK 140
+#define GCC_QDSS_AT_CLK 141
+#define GCC_SYS_NOC_AT_CLK 142
+#define GCC_PCNOC_AT_CLK 143
+#define GCC_USB0_EUD_AT_CLK 144
+#define GCC_QDSS_EUD_AT_CLK 145
+#define QDSS_STM_CLK_SRC 146
+#define GCC_QDSS_STM_CLK 147
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 148
+#define QDSS_TRACECLKIN_CLK_SRC 149
+#define GCC_QDSS_TRACECLKIN_CLK 150
+#define QDSS_TSCTR_CLK_SRC 151
+#define GCC_Q6_TSCTR_1TO2_CLK 152
+#define GCC_WCSS_DBG_IFC_NTS_CLK 153
+#define GCC_QDSS_TSCTR_DIV2_CLK 154
+#define GCC_QDSS_TS_CLK 155
+#define GCC_QDSS_TSCTR_DIV4_CLK 156
+#define GCC_NSS_TS_CLK 157
+#define GCC_QDSS_TSCTR_DIV8_CLK 158
+#define GCC_QDSS_TSCTR_DIV16_CLK 159
+#define GCC_Q6SS_PCLKDBG_CLK 160
+#define GCC_Q6SS_TRIG_CLK 161
+#define GCC_WCSS_DBG_IFC_APB_CLK 162
+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 163
+#define GCC_QDSS_DAP_CLK 164
+#define GCC_QDSS_APB2JTAG_CLK 165
+#define GCC_QDSS_TSCTR_DIV3_CLK 166
+#define QPIC_IO_MACRO_CLK_SRC 167
+#define GCC_QPIC_IO_MACRO_CLK 168
+#define Q6_AXI_CLK_SRC 169
+#define GCC_Q6_AXIM_CLK 170
+#define GCC_WCSS_Q6_TBU_CLK 171
+#define GCC_MEM_NOC_Q6_AXI_CLK 172
+#define Q6_AXIM2_CLK_SRC 173
+#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 174
+#define GCC_NSSNOC_MEMNOC_CLK 175
+#define GCC_NSSNOC_MEM_NOC_1_CLK 176
+#define GCC_NSS_TBU_CLK 177
+#define GCC_MEM_NOC_NSSNOC_CLK 178
+#define LPASS_AXIM_CLK_SRC 179
+#define LPASS_SWAY_CLK_SRC 180
+#define ADSS_PWM_CLK_SRC 181
+#define GCC_ADSS_PWM_CLK 182
+#define GP1_CLK_SRC 183
+#define GP2_CLK_SRC 184
+#define GP3_CLK_SRC 185
+#define DDRSS_SMS_SLOW_CLK_SRC 186
+#define GCC_XO_CLK_SRC 187
+#define GCC_XO_CLK 188
+#define GCC_NSSNOC_QOSGEN_REF_CLK 189
+#define GCC_NSSNOC_TIMEOUT_REF_CLK 190
+#define GCC_XO_DIV4_CLK 191
+#define GCC_UNIPHY0_SYS_CLK 192
+#define GCC_UNIPHY1_SYS_CLK 193
+#define GCC_UNIPHY2_SYS_CLK 194
+#define GCC_CMN_12GPLL_SYS_CLK 195
+#define GCC_NSSNOC_XO_DCD_CLK 196
+#define GCC_Q6SS_BOOT_CLK 197
+#define UNIPHY_SYS_CLK_SRC 198
+#define NSS_TS_CLK_SRC 199
+#define GCC_ANOC_PCIE0_1LANE_M_CLK 200
+#define GCC_ANOC_PCIE1_1LANE_M_CLK 201
+#define GCC_ANOC_PCIE2_2LANE_M_CLK 202
+#define GCC_ANOC_PCIE3_2LANE_M_CLK 203
+#define GCC_SNOC_PCIE0_1LANE_S_CLK 204
+#define GCC_SNOC_PCIE1_1LANE_S_CLK 205
+#define GCC_SNOC_PCIE2_2LANE_S_CLK 206
+#define GCC_SNOC_PCIE3_2LANE_S_CLK 207
#endif
--
2.17.1
Add the clocks needed for enabling PCIe in IPQ9574
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index b2a2d618a5ec..1bf33d582dc2 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x28044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x28044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
.reg = 0x29064,
.clkr = {
@@ -1552,6 +1570,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 0x29044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x29044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
.reg = 0x2a064,
.clkr = {
@@ -1566,6 +1602,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie2_pipe_clk = {
+ .halt_reg = 0x2a044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2a044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie2_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie2_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
.reg = 0x2b064,
.clkr = {
@@ -1580,6 +1634,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie3_pipe_clk = {
+ .halt_reg = 0x2b044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2b044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie3_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie3_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
@@ -3901,9 +3973,13 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
+ [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
+ [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
--
2.17.1
Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 ++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 ++++++++++++++++++-
2 files changed, 499 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
index 2c8430197ec0..21b53f34ce84 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
@@ -8,6 +8,7 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "ipq9574.dtsi"
/ {
@@ -29,6 +30,33 @@
status = "okay";
};
+&pcie1_phy {
+ status = "okay";
+};
+
+&pcie1_x1 {
+ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ status = "okay";
+};
+
+&pcie2_x2 {
+ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie3_phy {
+ status = "okay";
+};
+
+&pcie3_x2 {
+ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 062f80798ebb..a32dbdeb5bed 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -6,8 +6,8 @@
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
/ {
@@ -22,11 +22,41 @@
#clock-cells = <0>;
};
+ pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ #clock-cells = <0>;
+ };
+
+ pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ #clock-cells = <0>;
+ };
+
+ pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ #clock-cells = <0>;
+ };
+
+ pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ #clock-cells = <0>;
+ };
+
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
+ usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ #clock-cells = <0>;
+ };
+
xo_board_clk: xo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -121,6 +151,155 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ pcie0_phy: phy@84000 {
+ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+ reg = <0x00084000 0x1bc>; /* Serdes PLL */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>;
+ clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
+
+ assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
+ assigned-clock-rates = <20000000>;
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+
+ status = "disabled";
+
+ pcie0_lane: phy@84200 {
+ reg = <0x00084200 0x16c>, /* Serdes Tx */
+ <0x00084400 0x200>, /* Serdes Rx */
+ <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x00084c00 0xf4>; /* pcs_misc */
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ #clock-cells = <0>;
+ };
+ };
+
+ pcie2_phy: phy@8c000 {
+ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+ reg = <0x0008c000 0x1bc>; /* Serdes PLL */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE2_AUX_CLK>,
+ <&gcc GCC_PCIE2_AHB_CLK>,
+ <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
+ clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
+
+ assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
+ assigned-clock-rates = <20000000>;
+
+ resets = <&gcc GCC_PCIE2_PHY_BCR>,
+ <&gcc GCC_PCIE2PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+
+ status = "disabled";
+
+ pcie2_lanes: phy@8c200 {
+ reg = <0x0008c200 0x16c>, /* Serdes Tx0 */
+ <0x0008c400 0x200>, /* Serdes Rx0 */
+ <0x0008d000 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x0008c600 0x16c>, /* Serdes Tx1 */
+ <0x0008c800 0x200>, /* Serdes Rx1 */
+ <0x0008d400 0x0f8>; /* pcs_misc */
+
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE2_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie2_pipe_clk_src";
+ #clock-cells = <0>;
+ };
+ };
+
+ pcie3_phy: phy@f4000 {
+ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+ reg = <0x000f4000 0x1bc>; /* Serdes PLL */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE3_AUX_CLK>,
+ <&gcc GCC_PCIE3_AHB_CLK>,
+ <&gcc GCC_ANOC_PCIE3_2LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>;
+ clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
+
+ assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
+ assigned-clock-rates = <20000000>;
+
+ resets = <&gcc GCC_PCIE3_PHY_BCR>,
+ <&gcc GCC_PCIE3PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+
+ status = "disabled";
+
+ pcie3_lanes: phy@f4200 {
+ reg = <0x000f4200 0x16c>, /* Serdes Tx0 */
+ <0x000f4400 0x200>, /* Serdes Rx0 */
+ <0x000f5000 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x000f4600 0x16c>, /* Serdes Tx1 */
+ <0x000f4800 0x200>, /* Serdes Rx1 */
+ <0x000f5400 0x0f8>; /* pcs_misc */
+
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE3_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie3_pipe_clk_src";
+ #clock-cells = <0>;
+ };
+ };
+
+ pcie1_phy: phy@fc000 {
+ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+ reg = <0x000fc000 0x1bc>; /* Serdes PLL */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_ANOC_PCIE1_1LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE1_1LANE_S_CLK>;
+ clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
+
+ assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
+ assigned-clock-rates = <20000000>;
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+
+ status = "disabled";
+
+ pcie1_lane: phy@fc200 {
+ reg = <0x000fc200 0x16c>, /* Serdes Tx */
+ <0x000fc400 0x200>, /* Serdes Rx */
+ <0x000fc800 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x000fcc00 0xf4>; /* pcs_misc */
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie1_pipe_clk_src";
+ #clock-cells = <0>;
+ };
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq9574-tlmm";
reg = <0x01000000 0x300000>;
@@ -145,11 +324,11 @@
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&bias_pll_ubi_nc_clk>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&pcie30_phy0_pipe_clk>,
+ <&pcie30_phy1_pipe_clk>,
+ <&pcie30_phy2_pipe_clk>,
+ <&pcie30_phy3_pipe_clk>,
+ <&usb3phy_0_cc_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -282,6 +461,292 @@
status = "disabled";
};
};
+
+ pcie1_x1: pci@10000000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x10000000 0xf1d>,
+ <0x10000F20 0xa8>,
+ <0x10001000 0x1000>,
+ <0x000F8000 0x4000>,
+ <0x10100000 0x1000>,
+ <0x00618108 0x4>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config", "aggr_noc";
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x10200000 0x10200000
+ 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x10300000 0x10300000
+ 0 0x07d00000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 35
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 49
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 84
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 85
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global_irq";
+
+ /* clocks and clock-names are used to enable the clock in CBCR */
+ clocks = <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE1_RCHNG_CLK>;
+ clock-names = "ahb",
+ "aux",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_S_ARES>,
+ <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_M_ARES>,
+ <&gcc GCC_PCIE1_AUX_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie1_lane>;
+ phy-names = "pciephy";
+ msi-parent = <&v2m0>;
+ status = "disabled";
+ };
+
+ pcie3_x2: pci@18000000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x18000000 0xf1d>,
+ <0x18000F20 0xa8>,
+ <0x18001000 0x1000>,
+ <0x000F0000 0x4000>,
+ <0x18100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <4>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x18200000 0x18200000
+ 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x18300000 0x18300000
+ 0 0x07d00000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 189
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 190
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 191
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 192
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global_irq";
+
+ /* clocks and clock-names are used to enable the clock in CBCR */
+ clocks = <&gcc GCC_PCIE3_AHB_CLK>,
+ <&gcc GCC_PCIE3_AUX_CLK>,
+ <&gcc GCC_PCIE3_AXI_M_CLK>,
+ <&gcc GCC_PCIE3_AXI_S_CLK>,
+ <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3_RCHNG_CLK>;
+ clock-names = "ahb",
+ "aux",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE3_PIPE_ARES>,
+ <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3_AXI_S_ARES>,
+ <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3_AXI_M_ARES>,
+ <&gcc GCC_PCIE3_AUX_ARES>,
+ <&gcc GCC_PCIE3_AHB_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie3_lanes>;
+ phy-names = "pciephy";
+ msi-parent = <&v2m0>;
+ status = "disabled";
+ };
+
+ pcie2_x2: pci@20000000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x20000000 0xf1d>,
+ <0x20000F20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x00088000 0x4000>,
+ <0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <3>;
+ bus-range = <0x00 0xff>;
+ num-lanes =<2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x20200000 0x20200000
+ 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x20300000 0x20300000
+ 0 0x07d00000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 164
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 165
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 186
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 187
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global_irq";
+
+ /* clocks and clock-names are used to enable the clock in CBCR */
+ clocks = <&gcc GCC_PCIE2_AHB_CLK>,
+ <&gcc GCC_PCIE2_AUX_CLK>,
+ <&gcc GCC_PCIE2_AXI_M_CLK>,
+ <&gcc GCC_PCIE2_AXI_S_CLK>,
+ <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE2_RCHNG_CLK>;
+ clock-names = "ahb",
+ "aux",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE2_PIPE_ARES>,
+ <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AXI_S_ARES>,
+ <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AXI_M_ARES>,
+ <&gcc GCC_PCIE2_AUX_ARES>,
+ <&gcc GCC_PCIE2_AHB_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie2_lanes>;
+ phy-names = "pciephy";
+ msi-parent = <&v2m0>;
+ status = "disabled";
+ };
+
+ pcie0_x1: pci@28000000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x28000000 0xf1d>,
+ <0x28000F20 0xa8>,
+ <0x28001000 0x1000>,
+ <0x00080000 0x2000>,
+ <0x28100000 0x1000>,
+ <0x00618088 0x4>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config", "aggr_noc";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x28200000 0x28200000
+ 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x28300000 0x28300000
+ 0 0x07d00000>; /* non-prefetchable memory */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global_irq";
+
+ /* clocks and clock-names are used to enable the clock in CBCR */
+ clocks = <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE0_RCHNG_CLK>;
+ clock-names = "ahb",
+ "aux",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_S_ARES>,
+ <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_M_ARES>,
+ <&gcc GCC_PCIE0_AUX_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie0_lane>;
+ phy-names = "pciephy";
+ msi-parent = <&v2m0>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
Quoting Devi Priya (2023-02-14 08:41:33)
> Add PCIe clock definitions for IPQ9574 SoC
>
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 276 ++++++++++---------
> 1 file changed, 140 insertions(+), 136 deletions(-)
>
> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> index feedfdd5e00a..c89e96d568c6 100644
> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> @@ -74,140 +74,144 @@
> #define GCC_PCIE3_AXI_S_BRIDGE_CLK 65
> #define GCC_PCIE3_AXI_S_CLK 66
> #define PCIE0_PIPE_CLK_SRC 67
> -#define PCIE1_PIPE_CLK_SRC 68
Just add the new define at the end. This number and define is ABI
forever and shouldn't change.
> -#define PCIE2_PIPE_CLK_SRC 69
> -#define PCIE3_PIPE_CLK_SRC 70
Thanks for taking time to review the patch!
On 2/15/2023 8:00 AM, Stephen Boyd wrote:
> Quoting Devi Priya (2023-02-14 08:41:33)
>> Add PCIe clock definitions for IPQ9574 SoC
>>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 276 ++++++++++---------
>> 1 file changed, 140 insertions(+), 136 deletions(-)
>>
>> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> index feedfdd5e00a..c89e96d568c6 100644
>> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> @@ -74,140 +74,144 @@
>> #define GCC_PCIE3_AXI_S_BRIDGE_CLK 65
>> #define GCC_PCIE3_AXI_S_CLK 66
>> #define PCIE0_PIPE_CLK_SRC 67
>> -#define PCIE1_PIPE_CLK_SRC 68
>
> Just add the new define at the end. This number and define is ABI
> forever and shouldn't change.
Sure, will update
>
>> -#define PCIE2_PIPE_CLK_SRC 69
>> -#define PCIE3_PIPE_CLK_SRC 70
Best Regards,
Devi Priya
On 14/02/2023 17:41, Devi Priya wrote:
> Document the compatible for IPQ9574
>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
> 1 file changed, 70 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 872817d6d2bd..dabdf2684e2d 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -26,6 +26,7 @@ properties:
> - qcom,pcie-ipq8064-v2
> - qcom,pcie-ipq8074
> - qcom,pcie-ipq8074-gen3
> + - qcom,pcie-ipq9574
> - qcom,pcie-msm8996
> - qcom,pcie-qcs404
> - qcom,pcie-sa8540p
> @@ -44,11 +45,11 @@ properties:
>
> reg:
> minItems: 4
> - maxItems: 5
> + maxItems: 6
>
> reg-names:
> minItems: 4
> - maxItems: 5
> + maxItems: 6
>
> interrupts:
> minItems: 1
> @@ -105,6 +106,8 @@ properties:
> items:
> - const: pciephy
>
> + msi-parent: true
> +
> power-domains:
> maxItems: 1
>
> @@ -173,6 +176,27 @@ allOf:
> - const: parf # Qualcomm specific registers
> - const: config # PCIe configuration space
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq9574
> + then:
> + properties:
> + reg:
> + minItems: 5
> + maxItems: 6
> + reg-names:
> + minItems: 5
> + items:
> + - const: dbi # DesignWare PCIe registers
> + - const: elbi # External local bus interface registers
> + - const: atu # ATU address space
> + - const: parf # Qualcomm specific registers
> + - const: config # PCIe configuration space
> + - const: aggr_noc #PCIe aggr_noc
Why last one is optional? I would assume device either has it or has not.
Best regards,
Krzysztof
On 14/02/2023 17:41, Devi Priya wrote:
> Add the compatible for the PCIe QMP PHYs found on IPQ9574
>
> Signed-off-by: Devi Priya <[email protected]>
> ---
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Hi Devi,
On 2/14/2023 10:11 PM, Devi Priya wrote:
> Adding PCIe support for IPQ9574 SoC
>
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
> 1 file changed, 119 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index a232b04af048..57606c113d45 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
> struct reset_control *rst;
> };
>
> +struct qcom_pcie_resources_1_27_0 {
> + struct clk_bulk_data *clks;
> + struct reset_control *rst;
> + int num_clks;
> +};
> +
> union qcom_pcie_resources {
> struct qcom_pcie_resources_1_0_0 v1_0_0;
> struct qcom_pcie_resources_2_1_0 v2_1_0;
> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
> struct qcom_pcie_resources_2_4_0 v2_4_0;
> struct qcom_pcie_resources_2_7_0 v2_7_0;
> struct qcom_pcie_resources_2_9_0 v2_9_0;
> + struct qcom_pcie_resources_1_27_0 v1_27_0;
> };
>
> struct qcom_pcie;
> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
> return 0;
> }
>
> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
> +{
> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> + struct dw_pcie *pci = pcie->pci;
> + struct device *dev = pci->dev;
> +
> + res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
> + if (res->clks < 0)
> + return res->num_clks;
> +
> + res->rst = devm_reset_control_array_get_exclusive(dev);
> + if (IS_ERR(res->rst))
> + return PTR_ERR(res->rst);
> +
> + return 0;
> +}
> +
> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
> +{
> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +
> + clk_bulk_disable_unprepare(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
> +{
> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> + struct device *dev = pcie->pci->dev;
> + int ret;
> +
> + ret = reset_control_assert(res->rst);
> + if (ret) {
> + dev_err(dev, "reset assert failed (%d)\n", ret);
> + return ret;
> + }
> +
> + /*
> + * Delay periods before and after reset deassert are working values
> + * from downstream Codeaurora kernel
> + */
> + usleep_range(2000, 2500);
> +
> + ret = reset_control_deassert(res->rst);
> + if (ret) {
> + dev_err(dev, "reset deassert failed (%d)\n", ret);
> + return ret;
> + }
> +
> + usleep_range(2000, 2500);
> +
> + return clk_bulk_prepare_enable(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
> +{
> + struct dw_pcie *pci = pcie->pci;
> + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + u32 val;
> + int i;
> +
> + writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
> +
> + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> + val &= ~BIT(0);
> + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> +
> + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
> +
> + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
> + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
> + pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
> + writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
> + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
> + pci->dbi_base + GEN3_RELATED_OFF);
> +
> + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
> + SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
> + AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
> + pcie->parf + PCIE20_PARF_SYS_CTRL);
> +
> + writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
> +
> + dw_pcie_dbi_ro_wr_en(pci);
> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> +
> + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> + val &= ~PCI_EXP_LNKCAP_ASPMS;
> + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
> +
> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
> + PCI_EXP_DEVCTL2);
> +
> + for (i = 0; i < 256; i++)
> + writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
> +
> + return 0;
> +}
> +
> static int qcom_pcie_link_up(struct dw_pcie *pci)
> {
> u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
> .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> };
>
> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
> +static const struct qcom_pcie_ops ops_1_27_0 = {
> + .get_resources = qcom_pcie_get_resources_1_27_0,
> + .init = qcom_pcie_init_1_27_0,
> + .post_init = qcom_pcie_post_init_1_27_0,
> + .deinit = qcom_pcie_deinit_1_27_0,
> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> +};
> +
> static const struct qcom_pcie_cfg cfg_1_0_0 = {
> .ops = &ops_1_0_0,
> };
> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
> .ops = &ops_2_9_0,
> };
>
> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
> + .ops = &ops_1_27_0,
> +};
> +
> static const struct dw_pcie_ops dw_pcie_ops = {
> .link_up = qcom_pcie_link_up,
> .start_link = qcom_pcie_start_link,
> @@ -1829,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
> { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
> { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
> + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
I do not see much difference between 2_9_0 and 1_27_0. Is this patch
really required. Can you check if it works with 2_9_0 itself ?
Regards,
Sricharan
Hi Devi,
On 2/14/2023 10:11 PM, Devi Priya wrote:
> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
> found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 ++
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 ++++++++++++++++++-
> 2 files changed, 499 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> index 2c8430197ec0..21b53f34ce84 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -8,6 +8,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> #include "ipq9574.dtsi"
>
> / {
> @@ -29,6 +30,33 @@
> status = "okay";
> };
>
> +&pcie1_phy {
> + status = "okay";
> +};
> +
> +&pcie1_x1 {
> + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> +&pcie2_phy {
> + status = "okay";
> +};
> +
> +&pcie2_x2 {
> + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> +&pcie3_phy {
> + status = "okay";
> +};
> +
> +&pcie3_x2 {
> + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> &sdhc_1 {
> pinctrl-0 = <&sdc_default_state>;
> pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 062f80798ebb..a32dbdeb5bed 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -6,8 +6,8 @@
> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> -#include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>
> / {
> @@ -22,11 +22,41 @@
> #clock-cells = <0>;
> };
>
> + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> };
>
> + usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + #clock-cells = <0>;
> + };
> +
Why is the usb clock added here ?
> xo_board_clk: xo-board-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -121,6 +151,155 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + pcie0_phy: phy@84000 {
> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> + reg = <0x00084000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
> + <&gcc GCC_PCIE0_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
> +
> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie0_lane: phy@84200 {
> + reg = <0x00084200 0x16c>, /* Serdes Tx */
> + <0x00084400 0x200>, /* Serdes Rx */
> + <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x00084c00 0xf4>; /* pcs_misc */
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie0_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
> + pcie2_phy: phy@8c000 {
Can the phy/pcie nodes labelled in order ?
Currently it 0/2/3/1 ?
> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
> + reg = <0x0008c000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_PCIE2_AUX_CLK>,
> + <&gcc GCC_PCIE2_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
> +
> + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE2_PHY_BCR>,
> + <&gcc GCC_PCIE2PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie2_lanes: phy@8c200 {
> + reg = <0x0008c200 0x16c>, /* Serdes Tx0 */
> + <0x0008c400 0x200>, /* Serdes Rx0 */
> + <0x0008d000 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x0008c600 0x16c>, /* Serdes Tx1 */
> + <0x0008c800 0x200>, /* Serdes Rx1 */
> + <0x0008d400 0x0f8>; /* pcs_misc */
> +
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE2_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie2_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
> + pcie3_phy: phy@f4000 {
> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
> + reg = <0x000f4000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_PCIE3_AUX_CLK>,
> + <&gcc GCC_PCIE3_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE3_2LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
> +
> + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE3_PHY_BCR>,
> + <&gcc GCC_PCIE3PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie3_lanes: phy@f4200 {
> + reg = <0x000f4200 0x16c>, /* Serdes Tx0 */
> + <0x000f4400 0x200>, /* Serdes Rx0 */
> + <0x000f5000 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x000f4600 0x16c>, /* Serdes Tx1 */
> + <0x000f4800 0x200>, /* Serdes Rx1 */
> + <0x000f5400 0x0f8>; /* pcs_misc */
> +
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE3_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie3_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
> + pcie1_phy: phy@fc000 {
> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> + reg = <0x000fc000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_PCIE1_AUX_CLK>,
> + <&gcc GCC_PCIE1_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE1_1LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE1_1LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
> +
> + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie1_lane: phy@fc200 {
> + reg = <0x000fc200 0x16c>, /* Serdes Tx */
> + <0x000fc400 0x200>, /* Serdes Rx */
> + <0x000fc800 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x000fcc00 0xf4>; /* pcs_misc */
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie1_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
> tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq9574-tlmm";
> reg = <0x01000000 0x300000>;
> @@ -145,11 +324,11 @@
> clocks = <&xo_board_clk>,
> <&sleep_clk>,
> <&bias_pll_ubi_nc_clk>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> - <0>;
> + <&pcie30_phy0_pipe_clk>,
> + <&pcie30_phy1_pipe_clk>,
> + <&pcie30_phy2_pipe_clk>,
> + <&pcie30_phy3_pipe_clk>,
> + <&usb3phy_0_cc_pipe_clk>;
Same , why usb3 clk is added here ?
Regards,
Sricharan
Hi Devi,
On 2/14/2023 10:11 PM, Devi Priya wrote:
> Add the clocks needed for enabling PCIe in IPQ9574
>
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index b2a2d618a5ec..1bf33d582dc2 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
> },
> };
>
> +static struct clk_branch gcc_pcie0_pipe_clk = {
> + .halt_reg = 0x28044,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x28044,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie0_pipe_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie0_pipe_clk_src.clkr.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
> .reg = 0x29064,
> .clkr = {
> @@ -1552,6 +1570,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
> },
> };
>
> +static struct clk_branch gcc_pcie1_pipe_clk = {
> + .halt_reg = 0x29044,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x29044,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie1_pipe_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie1_pipe_clk_src.clkr.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
Looks like indentation issue for the above hunk.
Regards,
Sricharan
Hi Devi,
On 2/14/2023 10:11 PM, Devi Priya wrote:
> Add the clocks needed for enabling PCIe in IPQ9574
>
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index b2a2d618a5ec..1bf33d582dc2 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
> },
> };
>
> +static struct clk_branch gcc_pcie0_pipe_clk = {
> + .halt_reg = 0x28044,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x28044,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie0_pipe_clk",
> + .parent_hws = (const struct clk_hw *[]) {
> + &pcie0_pipe_clk_src.clkr.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
Also, this patch should come before your phy driver updates.
Regards,
Sricharan
On 2/14/2023 10:11 PM, Devi Priya wrote:
> PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
> are found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane
> Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>
> This series adds support for enabling the same
>
<[email protected]> --> This is bouncing, please remove it
Regards,
Sricharan
Hi Krzysztof,
Thanks for taking time to review the patch!
On 2/16/2023 3:59 PM, Krzysztof Kozlowski wrote:
> On 14/02/2023 17:41, Devi Priya wrote:
>> Document the compatible for IPQ9574
>>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
>> 1 file changed, 70 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> index 872817d6d2bd..dabdf2684e2d 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> @@ -26,6 +26,7 @@ properties:
>> - qcom,pcie-ipq8064-v2
>> - qcom,pcie-ipq8074
>> - qcom,pcie-ipq8074-gen3
>> + - qcom,pcie-ipq9574
>> - qcom,pcie-msm8996
>> - qcom,pcie-qcs404
>> - qcom,pcie-sa8540p
>> @@ -44,11 +45,11 @@ properties:
>>
>> reg:
>> minItems: 4
>> - maxItems: 5
>> + maxItems: 6
>>
>> reg-names:
>> minItems: 4
>> - maxItems: 5
>> + maxItems: 6
>>
>> interrupts:
>> minItems: 1
>> @@ -105,6 +106,8 @@ properties:
>> items:
>> - const: pciephy
>>
>> + msi-parent: true
>> +
>> power-domains:
>> maxItems: 1
>>
>> @@ -173,6 +176,27 @@ allOf:
>> - const: parf # Qualcomm specific registers
>> - const: config # PCIe configuration space
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,pcie-ipq9574
>> + then:
>> + properties:
>> + reg:
>> + minItems: 5
>> + maxItems: 6
>> + reg-names:
>> + minItems: 5
>> + items:
>> + - const: dbi # DesignWare PCIe registers
>> + - const: elbi # External local bus interface registers
>> + - const: atu # ATU address space
>> + - const: parf # Qualcomm specific registers
>> + - const: config # PCIe configuration space
>> + - const: aggr_noc #PCIe aggr_noc
>
> Why last one is optional? I would assume device either has it or has not.
>
Yes right, the device has aggr_noc.
The rate adapter update was required only for 1-lane PCIe
But will check and update this accordingly in the next spin.
>
> Best regards,
> Krzysztof
>
Best Regards,
Devi Priya
Hi Sri,
Thanks for taking time to review the patch!
On 2/16/2023 5:08 PM, Sricharan Ramabadhran wrote:
> Hi Devi,
>
> On 2/14/2023 10:11 PM, Devi Priya wrote:
>> Adding PCIe support for IPQ9574 SoC
>>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
>> 1 file changed, 119 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
>> b/drivers/pci/controller/dwc/pcie-qcom.c
>> index a232b04af048..57606c113d45 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>> struct reset_control *rst;
>> };
>> +struct qcom_pcie_resources_1_27_0 {
>> + struct clk_bulk_data *clks;
>> + struct reset_control *rst;
>> + int num_clks;
>> +};
>> +
>> union qcom_pcie_resources {
>> struct qcom_pcie_resources_1_0_0 v1_0_0;
>> struct qcom_pcie_resources_2_1_0 v2_1_0;
>> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>> struct qcom_pcie_resources_2_4_0 v2_4_0;
>> struct qcom_pcie_resources_2_7_0 v2_7_0;
>> struct qcom_pcie_resources_2_9_0 v2_9_0;
>> + struct qcom_pcie_resources_1_27_0 v1_27_0;
>> };
>> struct qcom_pcie;
>> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct
>> qcom_pcie *pcie)
>> return 0;
>> }
>> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> + struct dw_pcie *pci = pcie->pci;
>> + struct device *dev = pci->dev;
>> +
>> + res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
>> + if (res->clks < 0)
>> + return res->num_clks;
>> +
>> + res->rst = devm_reset_control_array_get_exclusive(dev);
>> + if (IS_ERR(res->rst))
>> + return PTR_ERR(res->rst);
>> +
>> + return 0;
>> +}
>> +
>> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> +
>> + clk_bulk_disable_unprepare(res->num_clks, res->clks);
>> +}
>> +
>> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> + struct device *dev = pcie->pci->dev;
>> + int ret;
>> +
>> + ret = reset_control_assert(res->rst);
>> + if (ret) {
>> + dev_err(dev, "reset assert failed (%d)\n", ret);
>> + return ret;
>> + }
>> +
>> + /*
>> + * Delay periods before and after reset deassert are working values
>> + * from downstream Codeaurora kernel
>> + */
>> + usleep_range(2000, 2500);
>> +
>> + ret = reset_control_deassert(res->rst);
>> + if (ret) {
>> + dev_err(dev, "reset deassert failed (%d)\n", ret);
>> + return ret;
>> + }
>> +
>> + usleep_range(2000, 2500);
>> +
>> + return clk_bulk_prepare_enable(res->num_clks, res->clks);
>> +}
>> +
>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + struct dw_pcie *pci = pcie->pci;
>> + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> + u32 val;
>> + int i;
>> +
>> + writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
>> +
>> + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>> + val &= ~BIT(0);
>> + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>> +
>> + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
>> +
>> + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
>> + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
>> + pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>> + writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
>> + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
>> + pci->dbi_base + GEN3_RELATED_OFF);
>> +
>> + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
>> + SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
>> + AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
>> + pcie->parf + PCIE20_PARF_SYS_CTRL);
>> +
>> + writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
>> +
>> + dw_pcie_dbi_ro_wr_en(pci);
>> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>> +
>> + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> + val &= ~PCI_EXP_LNKCAP_ASPMS;
>> + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> +
>> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>> + PCI_EXP_DEVCTL2);
>> +
>> + for (i = 0; i < 256; i++)
>> + writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 *
>> i));
>> +
>> + return 0;
>> +}
>> +
>> static int qcom_pcie_link_up(struct dw_pcie *pci)
>> {
>> u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>> .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>> };
>> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
>> +static const struct qcom_pcie_ops ops_1_27_0 = {
>> + .get_resources = qcom_pcie_get_resources_1_27_0,
>> + .init = qcom_pcie_init_1_27_0,
>> + .post_init = qcom_pcie_post_init_1_27_0,
>> + .deinit = qcom_pcie_deinit_1_27_0,
>> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>> +};
>> +
>> static const struct qcom_pcie_cfg cfg_1_0_0 = {
>> .ops = &ops_1_0_0,
>> };
>> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>> .ops = &ops_2_9_0,
>> };
>> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
>> + .ops = &ops_1_27_0,
>> +};
>> +
>> static const struct dw_pcie_ops dw_pcie_ops = {
>> .link_up = qcom_pcie_link_up,
>> .start_link = qcom_pcie_start_link,
>> @@ -1829,6 +1947,7 @@ static const struct of_device_id
>> qcom_pcie_match[] = {
>> { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>> { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>> { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>> + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
>
> I do not see much difference between 2_9_0 and 1_27_0. Is this patch
> really required. Can you check if it works with 2_9_0 itself ?
Yes right Sri, Only the clocks seem to differ between 2_9_0 and 1_27_0.
Will update 2_9_0 ops to get the clocks from the DT and use the same for
ipq9574 in the next spin.
Best Regards,
Devi Priya
>
> Regards,
> Sricharan
On 2/17/2023 2:11 PM, Sricharan Ramabadhran wrote:
> Hi Devi,
>
> On 2/14/2023 10:11 PM, Devi Priya wrote:
>> Add the clocks needed for enabling PCIe in IPQ9574
>>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 76 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c
>> b/drivers/clk/qcom/gcc-ipq9574.c
>> index b2a2d618a5ec..1bf33d582dc2 100644
>> --- a/drivers/clk/qcom/gcc-ipq9574.c
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux
>> pcie0_pipe_clk_src = {
>> },
>> };
>> +static struct clk_branch gcc_pcie0_pipe_clk = {
>> + .halt_reg = 0x28044,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x28044,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie0_pipe_clk",
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &pcie0_pipe_clk_src.clkr.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
>> .reg = 0x29064,
>> .clkr = {
>> @@ -1552,6 +1570,24 @@ static struct clk_regmap_phy_mux
>> pcie1_pipe_clk_src = {
>> },
>> };
>> +static struct clk_branch gcc_pcie1_pipe_clk = {
>> + .halt_reg = 0x29044,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x29044,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie1_pipe_clk",
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &pcie1_pipe_clk_src.clkr.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>
> Looks like indentation issue for the above hunk.
Sure, will update this in V2
Best Regards,
Devi Priya
>
> Regards,
> Sricharan
On 2/17/2023 2:13 PM, Sricharan Ramabadhran wrote:
> Hi Devi,
>
> On 2/14/2023 10:11 PM, Devi Priya wrote:
>> Add the clocks needed for enabling PCIe in IPQ9574
>>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 76 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c
>> b/drivers/clk/qcom/gcc-ipq9574.c
>> index b2a2d618a5ec..1bf33d582dc2 100644
>> --- a/drivers/clk/qcom/gcc-ipq9574.c
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux
>> pcie0_pipe_clk_src = {
>> },
>> };
>> +static struct clk_branch gcc_pcie0_pipe_clk = {
>> + .halt_reg = 0x28044,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x28044,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie0_pipe_clk",
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &pcie0_pipe_clk_src.clkr.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>
> Also, this patch should come before your phy driver updates.
Sure got it, will reorder the patches in V2
>
> Regards,
> Sricharan
>
Best Regards,
Devi Priya
On 2/17/2023 2:05 PM, Sricharan Ramabadhran wrote:
>
> Hi Devi,
>
> On 2/14/2023 10:11 PM, Devi Priya wrote:
>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>> found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 ++
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 ++++++++++++++++++-
>> 2 files changed, 499 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> index 2c8430197ec0..21b53f34ce84 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -8,6 +8,7 @@
>> /dts-v1/;
>> +#include <dt-bindings/gpio/gpio.h>
>> #include "ipq9574.dtsi"
>> / {
>> @@ -29,6 +30,33 @@
>> status = "okay";
>> };
>> +&pcie1_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie1_x1 {
>> + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> +&pcie2_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie2_x2 {
>> + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> +&pcie3_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie3_x2 {
>> + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> pinctrl-0 = <&sdc_default_state>;
>> pinctrl-names = "default";
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 062f80798ebb..a32dbdeb5bed 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -6,8 +6,8 @@
>> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> */
>> -#include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> / {
>> @@ -22,11 +22,41 @@
>> #clock-cells = <0>;
>> };
>> + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> sleep_clk: sleep-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> };
>> + usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <125000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>
> Why is the usb clock added here ?
As we have brought in the QMP PHY support, added the usb pipe clock too.
Will drop it as it is unrelated to the series.
>
>> xo_board_clk: xo-board-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> @@ -121,6 +151,155 @@
>> #size-cells = <1>;
>> ranges = <0 0 0 0xffffffff>;
>> + pcie0_phy: phy@84000 {
>> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> + reg = <0x00084000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
>> + <&gcc GCC_PCIE0_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie0_lane: phy@84200 {
>> + reg = <0x00084200 0x16c>, /* Serdes Tx */
>> + <0x00084400 0x200>, /* Serdes Rx */
>> + <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x00084c00 0xf4>; /* pcs_misc */
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie0_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + pcie2_phy: phy@8c000 {
>
> Can the phy/pcie nodes labelled in order ?
> Currently it 0/2/3/1 ?
Sure, okay
>
>> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
>> + reg = <0x0008c000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_PCIE2_AUX_CLK>,
>> + <&gcc GCC_PCIE2_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE2_PHY_BCR>,
>> + <&gcc GCC_PCIE2PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie2_lanes: phy@8c200 {
>> + reg = <0x0008c200 0x16c>, /* Serdes Tx0 */
>> + <0x0008c400 0x200>, /* Serdes Rx0 */
>> + <0x0008d000 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x0008c600 0x16c>, /* Serdes Tx1 */
>> + <0x0008c800 0x200>, /* Serdes Rx1 */
>> + <0x0008d400 0x0f8>; /* pcs_misc */
>> +
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE2_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie2_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + pcie3_phy: phy@f4000 {
>> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
>> + reg = <0x000f4000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_PCIE3_AUX_CLK>,
>> + <&gcc GCC_PCIE3_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE3_2LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE3_PHY_BCR>,
>> + <&gcc GCC_PCIE3PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie3_lanes: phy@f4200 {
>> + reg = <0x000f4200 0x16c>, /* Serdes Tx0 */
>> + <0x000f4400 0x200>, /* Serdes Rx0 */
>> + <0x000f5000 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x000f4600 0x16c>, /* Serdes Tx1 */
>> + <0x000f4800 0x200>, /* Serdes Rx1 */
>> + <0x000f5400 0x0f8>; /* pcs_misc */
>> +
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE3_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie3_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + pcie1_phy: phy@fc000 {
>> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> + reg = <0x000fc000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_PCIE1_AUX_CLK>,
>> + <&gcc GCC_PCIE1_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE1_1LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE1_1LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
>> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie1_lane: phy@fc200 {
>> + reg = <0x000fc200 0x16c>, /* Serdes Tx */
>> + <0x000fc400 0x200>, /* Serdes Rx */
>> + <0x000fc800 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x000fcc00 0xf4>; /* pcs_misc */
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie1_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> tlmm: pinctrl@1000000 {
>> compatible = "qcom,ipq9574-tlmm";
>> reg = <0x01000000 0x300000>;
>> @@ -145,11 +324,11 @@
>> clocks = <&xo_board_clk>,
>> <&sleep_clk>,
>> <&bias_pll_ubi_nc_clk>,
>> - <0>,
>> - <0>,
>> - <0>,
>> - <0>,
>> - <0>;
>> + <&pcie30_phy0_pipe_clk>,
>> + <&pcie30_phy1_pipe_clk>,
>> + <&pcie30_phy2_pipe_clk>,
>> + <&pcie30_phy3_pipe_clk>,
>> + <&usb3phy_0_cc_pipe_clk>;
>
> Same , why usb3 clk is added here ?
Sure, will drop it
>
> Regards,
> Sricharan
>
Best Regards,
Devi Priya
On 2/17/2023 2:18 PM, Sricharan Ramabadhran wrote:
>
>
> On 2/14/2023 10:11 PM, Devi Priya wrote:
>> PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>> are found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane
>> Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>
>> This series adds support for enabling the same
>>
>
>
> <[email protected]> --> This is bouncing, please remove it
>
Sure, okay
> Regards,
> Sricharan
Best Regards,
Devi Priya
On 2/20/2023 7:11 PM, Devi Priya wrote:
> Hi Sri,
> Thanks for taking time to review the patch!
>
> On 2/16/2023 5:08 PM, Sricharan Ramabadhran wrote:
>> Hi Devi,
>>
>> On 2/14/2023 10:11 PM, Devi Priya wrote:
>>> Adding PCIe support for IPQ9574 SoC
>>>
>>> Co-developed-by: Anusha Rao <[email protected]>
>>> Signed-off-by: Anusha Rao <[email protected]>
>>> Signed-off-by: Devi Priya <[email protected]>
>>> ---
>>> drivers/pci/controller/dwc/pcie-qcom.c | 119
>>> +++++++++++++++++++++++++
>>> 1 file changed, 119 insertions(+)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
>>> b/drivers/pci/controller/dwc/pcie-qcom.c
>>> index a232b04af048..57606c113d45 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>>> struct reset_control *rst;
>>> };
>>> +struct qcom_pcie_resources_1_27_0 {
>>> + struct clk_bulk_data *clks;
>>> + struct reset_control *rst;
>>> + int num_clks;
>>> +};
>>> +
>>> union qcom_pcie_resources {
>>> struct qcom_pcie_resources_1_0_0 v1_0_0;
>>> struct qcom_pcie_resources_2_1_0 v2_1_0;
>>> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>>> struct qcom_pcie_resources_2_4_0 v2_4_0;
>>> struct qcom_pcie_resources_2_7_0 v2_7_0;
>>> struct qcom_pcie_resources_2_9_0 v2_9_0;
>>> + struct qcom_pcie_resources_1_27_0 v1_27_0;
>>> };
>>> struct qcom_pcie;
>>> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct
>>> qcom_pcie *pcie)
>>> return 0;
>>> }
>>> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
>>> +{
>>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>> + struct dw_pcie *pci = pcie->pci;
>>> + struct device *dev = pci->dev;
>>> +
>>> + res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
>>> + if (res->clks < 0)
>>> + return res->num_clks;
>>> +
>>> + res->rst = devm_reset_control_array_get_exclusive(dev);
>>> + if (IS_ERR(res->rst))
>>> + return PTR_ERR(res->rst);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
>>> +{
>>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>> +
>>> + clk_bulk_disable_unprepare(res->num_clks, res->clks);
>>> +}
>>> +
>>> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
>>> +{
>>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>> + struct device *dev = pcie->pci->dev;
>>> + int ret;
>>> +
>>> + ret = reset_control_assert(res->rst);
>>> + if (ret) {
>>> + dev_err(dev, "reset assert failed (%d)\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + /*
>>> + * Delay periods before and after reset deassert are working
>>> values
>>> + * from downstream Codeaurora kernel
>>> + */
>>> + usleep_range(2000, 2500);
>>> +
>>> + ret = reset_control_deassert(res->rst);
>>> + if (ret) {
>>> + dev_err(dev, "reset deassert failed (%d)\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + usleep_range(2000, 2500);
>>> +
>>> + return clk_bulk_prepare_enable(res->num_clks, res->clks);
>>> +}
>>> +
>>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>>> +{
>>> + struct dw_pcie *pci = pcie->pci;
>>> + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>> + u32 val;
>>> + int i;
>>> +
>>> + writel(0x8000000, pcie->parf +
>>> PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
Devi,
Above statement also differs. You need to consider this also when you
use the 2_9_0 ops.
Thanks,
>>> +
>>> + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>>> + val &= ~BIT(0);
>>> + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>>> +
>>> + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
>>> +
>>> + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
>>> + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
>>> + pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>>> + writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
>>> + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
>>> + pci->dbi_base + GEN3_RELATED_OFF);
>>> +
>>> + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
>>> + SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
>>> + AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
>>> + pcie->parf + PCIE20_PARF_SYS_CTRL);
>>> +
>>> + writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
>>> +
>>> + dw_pcie_dbi_ro_wr_en(pci);
>>> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset +
>>> PCI_EXP_SLTCAP);
>>> +
>>> + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>> + val &= ~PCI_EXP_LNKCAP_ASPMS;
>>> + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>> +
>>> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>>> + PCI_EXP_DEVCTL2);
>>> +
>>> + for (i = 0; i < 256; i++)
>>> + writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4
>>> * i));
>>> +
>>> + return 0;
>>> +}
>>> +
>>> static int qcom_pcie_link_up(struct dw_pcie *pci)
>>> {
>>> u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>>> .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>> };
>>> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
>>> +static const struct qcom_pcie_ops ops_1_27_0 = {
>>> + .get_resources = qcom_pcie_get_resources_1_27_0,
>>> + .init = qcom_pcie_init_1_27_0,
>>> + .post_init = qcom_pcie_post_init_1_27_0,
>>> + .deinit = qcom_pcie_deinit_1_27_0,
>>> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>> +};
>>> +
>>> static const struct qcom_pcie_cfg cfg_1_0_0 = {
>>> .ops = &ops_1_0_0,
>>> };
>>> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>>> .ops = &ops_2_9_0,
>>> };
>>> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
>>> + .ops = &ops_1_27_0,
>>> +};
>>> +
>>> static const struct dw_pcie_ops dw_pcie_ops = {
>>> .link_up = qcom_pcie_link_up,
>>> .start_link = qcom_pcie_start_link,
>>> @@ -1829,6 +1947,7 @@ static const struct of_device_id
>>> qcom_pcie_match[] = {
>>> { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>>> { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>>> { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>>> + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
>>
>> I do not see much difference between 2_9_0 and 1_27_0. Is this patch
>> really required. Can you check if it works with 2_9_0 itself ?
> Yes right Sri, Only the clocks seem to differ between 2_9_0 and 1_27_0.
> Will update 2_9_0 ops to get the clocks from the DT and use the same
> for ipq9574 in the next spin.
>
> Best Regards,
> Devi Priya
>>
>> Regards,
>> Sricharan
On 2/20/2023 8:21 PM, Kathiravan T wrote:
>
> On 2/20/2023 7:11 PM, Devi Priya wrote:
>> Hi Sri,
>> Thanks for taking time to review the patch!
>>
>> On 2/16/2023 5:08 PM, Sricharan Ramabadhran wrote:
>>> Hi Devi,
>>>
>>> On 2/14/2023 10:11 PM, Devi Priya wrote:
>>>> Adding PCIe support for IPQ9574 SoC
>>>>
>>>> Co-developed-by: Anusha Rao <[email protected]>
>>>> Signed-off-by: Anusha Rao <[email protected]>
>>>> Signed-off-by: Devi Priya <[email protected]>
>>>> ---
>>>> drivers/pci/controller/dwc/pcie-qcom.c | 119
>>>> +++++++++++++++++++++++++
>>>> 1 file changed, 119 insertions(+)
>>>>
>>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
>>>> b/drivers/pci/controller/dwc/pcie-qcom.c
>>>> index a232b04af048..57606c113d45 100644
>>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>>> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>>>> struct reset_control *rst;
>>>> };
>>>> +struct qcom_pcie_resources_1_27_0 {
>>>> + struct clk_bulk_data *clks;
>>>> + struct reset_control *rst;
>>>> + int num_clks;
>>>> +};
>>>> +
>>>> union qcom_pcie_resources {
>>>> struct qcom_pcie_resources_1_0_0 v1_0_0;
>>>> struct qcom_pcie_resources_2_1_0 v2_1_0;
>>>> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>>>> struct qcom_pcie_resources_2_4_0 v2_4_0;
>>>> struct qcom_pcie_resources_2_7_0 v2_7_0;
>>>> struct qcom_pcie_resources_2_9_0 v2_9_0;
>>>> + struct qcom_pcie_resources_1_27_0 v1_27_0;
>>>> };
>>>> struct qcom_pcie;
>>>> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct
>>>> qcom_pcie *pcie)
>>>> return 0;
>>>> }
>>>> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
>>>> +{
>>>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>>> + struct dw_pcie *pci = pcie->pci;
>>>> + struct device *dev = pci->dev;
>>>> +
>>>> + res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
>>>> + if (res->clks < 0)
>>>> + return res->num_clks;
>>>> +
>>>> + res->rst = devm_reset_control_array_get_exclusive(dev);
>>>> + if (IS_ERR(res->rst))
>>>> + return PTR_ERR(res->rst);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
>>>> +{
>>>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>>> +
>>>> + clk_bulk_disable_unprepare(res->num_clks, res->clks);
>>>> +}
>>>> +
>>>> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
>>>> +{
>>>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>>>> + struct device *dev = pcie->pci->dev;
>>>> + int ret;
>>>> +
>>>> + ret = reset_control_assert(res->rst);
>>>> + if (ret) {
>>>> + dev_err(dev, "reset assert failed (%d)\n", ret);
>>>> + return ret;
>>>> + }
>>>> +
>>>> + /*
>>>> + * Delay periods before and after reset deassert are working
>>>> values
>>>> + * from downstream Codeaurora kernel
>>>> + */
>>>> + usleep_range(2000, 2500);
>>>> +
>>>> + ret = reset_control_deassert(res->rst);
>>>> + if (ret) {
>>>> + dev_err(dev, "reset deassert failed (%d)\n", ret);
>>>> + return ret;
>>>> + }
>>>> +
>>>> + usleep_range(2000, 2500);
>>>> +
>>>> + return clk_bulk_prepare_enable(res->num_clks, res->clks);
>>>> +}
>>>> +
>>>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>>>> +{
>>>> + struct dw_pcie *pci = pcie->pci;
>>>> + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>>> + u32 val;
>>>> + int i;
>>>> +
>>>> + writel(0x8000000, pcie->parf +
>>>> PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
>
>
> Devi,
>
>
> Above statement also differs. You need to consider this also when you
> use the 2_9_0 ops.
>
Sure, thanks kathir. Will take care of this as well
>
Best Regards,
Devi Priya
> Thanks,
>
>
>>>> +
>>>> + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>>>> + val &= ~BIT(0);
>>>> + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>>>> +
>>>> + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
>>>> +
>>>> + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
>>>> + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
>>>> + pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>>>> + writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
>>>> + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
>>>> + pci->dbi_base + GEN3_RELATED_OFF);
>>>> +
>>>> + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
>>>> + SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
>>>> + AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
>>>> + pcie->parf + PCIE20_PARF_SYS_CTRL);
>>>> +
>>>> + writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
>>>> +
>>>> + dw_pcie_dbi_ro_wr_en(pci);
>>>> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset +
>>>> PCI_EXP_SLTCAP);
>>>> +
>>>> + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>>> + val &= ~PCI_EXP_LNKCAP_ASPMS;
>>>> + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>>> +
>>>> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>>>> + PCI_EXP_DEVCTL2);
>>>> +
>>>> + for (i = 0; i < 256; i++)
>>>> + writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4
>>>> * i));
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> static int qcom_pcie_link_up(struct dw_pcie *pci)
>>>> {
>>>> u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>>>> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>>>> .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>>> };
>>>> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
>>>> +static const struct qcom_pcie_ops ops_1_27_0 = {
>>>> + .get_resources = qcom_pcie_get_resources_1_27_0,
>>>> + .init = qcom_pcie_init_1_27_0,
>>>> + .post_init = qcom_pcie_post_init_1_27_0,
>>>> + .deinit = qcom_pcie_deinit_1_27_0,
>>>> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>>>> +};
>>>> +
>>>> static const struct qcom_pcie_cfg cfg_1_0_0 = {
>>>> .ops = &ops_1_0_0,
>>>> };
>>>> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>>>> .ops = &ops_2_9_0,
>>>> };
>>>> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
>>>> + .ops = &ops_1_27_0,
>>>> +};
>>>> +
>>>> static const struct dw_pcie_ops dw_pcie_ops = {
>>>> .link_up = qcom_pcie_link_up,
>>>> .start_link = qcom_pcie_start_link,
>>>> @@ -1829,6 +1947,7 @@ static const struct of_device_id
>>>> qcom_pcie_match[] = {
>>>> { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>>>> { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>>>> { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>>>> + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
>>>
>>> I do not see much difference between 2_9_0 and 1_27_0. Is this patch
>>> really required. Can you check if it works with 2_9_0 itself ?
>> Yes right Sri, Only the clocks seem to differ between 2_9_0 and 1_27_0.
>> Will update 2_9_0 ops to get the clocks from the DT and use the same
>> for ipq9574 in the next spin.
>>
>> Best Regards,
>> Devi Priya
>>>
>>> Regards,
>>> Sricharan
On 2/14/2023 10:11 PM, Devi Priya wrote:
> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
> found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 ++
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 ++++++++++++++++++-
> 2 files changed, 499 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> index 2c8430197ec0..21b53f34ce84 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -8,6 +8,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> #include "ipq9574.dtsi"
>
> / {
> @@ -29,6 +30,33 @@
> status = "okay";
> };
>
> +&pcie1_phy {
> + status = "okay";
> +};
> +
> +&pcie1_x1 {
> + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> +&pcie2_phy {
> + status = "okay";
> +};
> +
> +&pcie2_x2 {
> + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> +&pcie3_phy {
> + status = "okay";
> +};
> +
> +&pcie3_x2 {
> + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> &sdhc_1 {
> pinctrl-0 = <&sdc_default_state>;
> pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 062f80798ebb..a32dbdeb5bed 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -6,8 +6,8 @@
> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> -#include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>
> / {
> @@ -22,11 +22,41 @@
> #clock-cells = <0>;
> };
>
> + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> };
>
> + usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + #clock-cells = <0>;
> + };
> +
> xo_board_clk: xo-board-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -121,6 +151,155 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + pcie0_phy: phy@84000 {
> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> + reg = <0x00084000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
> + <&gcc GCC_PCIE0_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
> +
> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie0_lane: phy@84200 {
> + reg = <0x00084200 0x16c>, /* Serdes Tx */
> + <0x00084400 0x200>, /* Serdes Rx */
> + <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x00084c00 0xf4>; /* pcs_misc */
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie0_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
> + pcie2_phy: phy@8c000 {
> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
> + reg = <0x0008c000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_PCIE2_AUX_CLK>,
> + <&gcc GCC_PCIE2_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
> +
> + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE2_PHY_BCR>,
> + <&gcc GCC_PCIE2PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie2_lanes: phy@8c200 {
> + reg = <0x0008c200 0x16c>, /* Serdes Tx0 */
> + <0x0008c400 0x200>, /* Serdes Rx0 */
> + <0x0008d000 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x0008c600 0x16c>, /* Serdes Tx1 */
> + <0x0008c800 0x200>, /* Serdes Rx1 */
> + <0x0008d400 0x0f8>; /* pcs_misc */
> +
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE2_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie2_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
> + pcie3_phy: phy@f4000 {
> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
> + reg = <0x000f4000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_PCIE3_AUX_CLK>,
> + <&gcc GCC_PCIE3_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE3_2LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
> +
> + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE3_PHY_BCR>,
> + <&gcc GCC_PCIE3PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie3_lanes: phy@f4200 {
> + reg = <0x000f4200 0x16c>, /* Serdes Tx0 */
> + <0x000f4400 0x200>, /* Serdes Rx0 */
> + <0x000f5000 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x000f4600 0x16c>, /* Serdes Tx1 */
> + <0x000f4800 0x200>, /* Serdes Rx1 */
> + <0x000f5400 0x0f8>; /* pcs_misc */
> +
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE3_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie3_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
> + pcie1_phy: phy@fc000 {
> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> + reg = <0x000fc000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_PCIE1_AUX_CLK>,
> + <&gcc GCC_PCIE1_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE1_1LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE1_1LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
> +
> + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie1_lane: phy@fc200 {
> + reg = <0x000fc200 0x16c>, /* Serdes Tx */
> + <0x000fc400 0x200>, /* Serdes Rx */
> + <0x000fc800 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x000fcc00 0xf4>; /* pcs_misc */
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie1_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
> tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq9574-tlmm";
> reg = <0x01000000 0x300000>;
> @@ -145,11 +324,11 @@
> clocks = <&xo_board_clk>,
> <&sleep_clk>,
> <&bias_pll_ubi_nc_clk>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> - <0>;
> + <&pcie30_phy0_pipe_clk>,
> + <&pcie30_phy1_pipe_clk>,
> + <&pcie30_phy2_pipe_clk>,
> + <&pcie30_phy3_pipe_clk>,
> + <&usb3phy_0_cc_pipe_clk>;
pipe clock source is PHY. So should we add the pcie_phy phandle here and
use it like how it is done in other targets, ex: sm8550.dtsi?
> #clock-cells = <1>;
> #reset-cells = <1>;
> #power-domain-cells = <1>;
> @@ -282,6 +461,292 @@
> status = "disabled";
> };
> };
> +
> + pcie1_x1: pci@10000000 {
> + compatible = "qcom,pcie-ipq9574";
> + reg = <0x10000000 0xf1d>,
> + <0x10000F20 0xa8>,
> + <0x10001000 0x1000>,
> + <0x000F8000 0x4000>,
> + <0x10100000 0x1000>,
> + <0x00618108 0x4>;
> + reg-names = "dbi", "elbi", "atu", "parf", "config", "aggr_noc";
> + device_type = "pci";
> + linux,pci-domain = <2>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0x10200000 0x10200000
> + 0 0x00100000 /* downstream I/O */
> + 0x82000000 0 0x10300000 0x10300000
> + 0 0x07d00000>; /* non-prefetchable memory */
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 35
> + IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 49
> + IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 84
> + IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 85
> + IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "global_irq";
Controller driver doesn't support the "global_irq" yet. Please correct
me If I am wrong.
Thanks, Kathiravan T.
On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
> Document the compatible for IPQ9574
>
You didn't mention about the "msi-parent" property that is being added
by this patch.
> Signed-off-by: Devi Priya <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
> 1 file changed, 70 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 872817d6d2bd..dabdf2684e2d 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -26,6 +26,7 @@ properties:
> - qcom,pcie-ipq8064-v2
> - qcom,pcie-ipq8074
> - qcom,pcie-ipq8074-gen3
> + - qcom,pcie-ipq9574
> - qcom,pcie-msm8996
> - qcom,pcie-qcs404
> - qcom,pcie-sa8540p
> @@ -44,11 +45,11 @@ properties:
>
> reg:
> minItems: 4
> - maxItems: 5
> + maxItems: 6
>
> reg-names:
> minItems: 4
> - maxItems: 5
> + maxItems: 6
>
> interrupts:
> minItems: 1
> @@ -105,6 +106,8 @@ properties:
> items:
> - const: pciephy
>
> + msi-parent: true
> +
> power-domains:
> maxItems: 1
>
> @@ -173,6 +176,27 @@ allOf:
> - const: parf # Qualcomm specific registers
> - const: config # PCIe configuration space
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq9574
> + then:
> + properties:
> + reg:
> + minItems: 5
> + maxItems: 6
> + reg-names:
> + minItems: 5
> + items:
> + - const: dbi # DesignWare PCIe registers
> + - const: elbi # External local bus interface registers
> + - const: atu # ATU address space
> + - const: parf # Qualcomm specific registers
> + - const: config # PCIe configuration space
> + - const: aggr_noc #PCIe aggr_noc
Why do you need this region unlike other SoCs? Is the driver making use of it?
Thanks,
Mani
> +
> - if:
> properties:
> compatible:
> @@ -365,6 +389,39 @@ allOf:
> - const: ahb # AHB Reset
> - const: axi_m_sticky # AXI Master Sticky reset
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq9574
> + then:
> + properties:
> + clocks:
> + minItems: 6
> + maxItems: 6
> + clock-names:
> + items:
> + - const: ahb # AHB clock
> + - const: aux # Auxiliary clock
> + - const: axi_m # AXI Master clock
> + - const: axi_s # AXI Slave clock
> + - const: axi_bridge # AXI bridge clock
> + - const: rchng
> + resets:
> + minItems: 8
> + maxItems: 8
> + reset-names:
> + items:
> + - const: pipe # PIPE reset
> + - const: sticky # Core Sticky reset
> + - const: axi_s_sticky # AXI Slave Sticky reset
> + - const: axi_s # AXI Slave reset
> + - const: axi_m_sticky # AXI Master Sticky reset
> + - const: axi_m # AXI Master reset
> + - const: aux # AUX Reset
> + - const: ahb # AHB Reset
> +
> - if:
> properties:
> compatible:
> @@ -681,6 +738,16 @@ allOf:
> - interconnects
> - interconnect-names
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq9574
> + then:
> + required:
> + - msi-parent
> +
> - if:
> not:
> properties:
> @@ -693,6 +760,7 @@ allOf:
> - qcom,pcie-ipq8064v2
> - qcom,pcie-ipq8074
> - qcom,pcie-ipq8074-gen3
> + - qcom,pcie-ipq9574
> - qcom,pcie-qcs404
> then:
> required:
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
On Tue, Feb 14, 2023 at 10:11:30PM +0530, Devi Priya wrote:
> Adding PCIe support for IPQ9574 SoC
>
Please add some information about the PCIe IP in the commit message.
Like, the Synopsys IP version, Gen speed etc... and how the support
is added (using existing config or a new one).
As others have mentioned, you could reuse the existing config. In that
case, add the info in commit message as I suggested above.
And the PCI patch should come last in the series after bindings and dts
patches.
Thanks,
Mani
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
> 1 file changed, 119 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index a232b04af048..57606c113d45 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
> struct reset_control *rst;
> };
>
> +struct qcom_pcie_resources_1_27_0 {
> + struct clk_bulk_data *clks;
> + struct reset_control *rst;
> + int num_clks;
> +};
> +
> union qcom_pcie_resources {
> struct qcom_pcie_resources_1_0_0 v1_0_0;
> struct qcom_pcie_resources_2_1_0 v2_1_0;
> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
> struct qcom_pcie_resources_2_4_0 v2_4_0;
> struct qcom_pcie_resources_2_7_0 v2_7_0;
> struct qcom_pcie_resources_2_9_0 v2_9_0;
> + struct qcom_pcie_resources_1_27_0 v1_27_0;
> };
>
> struct qcom_pcie;
> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
> return 0;
> }
>
> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
> +{
> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> + struct dw_pcie *pci = pcie->pci;
> + struct device *dev = pci->dev;
> +
> + res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
> + if (res->clks < 0)
> + return res->num_clks;
> +
> + res->rst = devm_reset_control_array_get_exclusive(dev);
> + if (IS_ERR(res->rst))
> + return PTR_ERR(res->rst);
> +
> + return 0;
> +}
> +
> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
> +{
> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +
> + clk_bulk_disable_unprepare(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
> +{
> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> + struct device *dev = pcie->pci->dev;
> + int ret;
> +
> + ret = reset_control_assert(res->rst);
> + if (ret) {
> + dev_err(dev, "reset assert failed (%d)\n", ret);
> + return ret;
> + }
> +
> + /*
> + * Delay periods before and after reset deassert are working values
> + * from downstream Codeaurora kernel
> + */
> + usleep_range(2000, 2500);
> +
> + ret = reset_control_deassert(res->rst);
> + if (ret) {
> + dev_err(dev, "reset deassert failed (%d)\n", ret);
> + return ret;
> + }
> +
> + usleep_range(2000, 2500);
> +
> + return clk_bulk_prepare_enable(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
> +{
> + struct dw_pcie *pci = pcie->pci;
> + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + u32 val;
> + int i;
> +
> + writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
> +
> + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> + val &= ~BIT(0);
> + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> +
> + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
> +
> + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
> + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
> + pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
> + writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
> + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
> + pci->dbi_base + GEN3_RELATED_OFF);
> +
> + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
> + SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
> + AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
> + pcie->parf + PCIE20_PARF_SYS_CTRL);
> +
> + writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
> +
> + dw_pcie_dbi_ro_wr_en(pci);
> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> +
> + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> + val &= ~PCI_EXP_LNKCAP_ASPMS;
> + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
> +
> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
> + PCI_EXP_DEVCTL2);
> +
> + for (i = 0; i < 256; i++)
> + writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
> +
> + return 0;
> +}
> +
> static int qcom_pcie_link_up(struct dw_pcie *pci)
> {
> u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
> .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> };
>
> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
> +static const struct qcom_pcie_ops ops_1_27_0 = {
> + .get_resources = qcom_pcie_get_resources_1_27_0,
> + .init = qcom_pcie_init_1_27_0,
> + .post_init = qcom_pcie_post_init_1_27_0,
> + .deinit = qcom_pcie_deinit_1_27_0,
> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> +};
> +
> static const struct qcom_pcie_cfg cfg_1_0_0 = {
> .ops = &ops_1_0_0,
> };
> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
> .ops = &ops_2_9_0,
> };
>
> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
> + .ops = &ops_1_27_0,
> +};
> +
> static const struct dw_pcie_ops dw_pcie_ops = {
> .link_up = qcom_pcie_link_up,
> .start_link = qcom_pcie_start_link,
> @@ -1829,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
> { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
> { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
> + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
> { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
> { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
> { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
On Tue, Feb 14, 2023 at 10:11:35PM +0530, Devi Priya wrote:
> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
> found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>
Please split the board devicetree changes into a separate patch.
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 ++
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 ++++++++++++++++++-
> 2 files changed, 499 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> index 2c8430197ec0..21b53f34ce84 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -8,6 +8,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> #include "ipq9574.dtsi"
>
> / {
> @@ -29,6 +30,33 @@
> status = "okay";
> };
>
> +&pcie1_phy {
> + status = "okay";
No PHY power supply needed? Same comment for rest of the PHY nodes.
> +};
> +
> +&pcie1_x1 {
No need to add a suffix to node label indicating the lane config.
> + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
What about "wake" pin? Don't you need pinctrl definitions for these GPIOs?
Same comment for rest of the PCIe nodes.
> + status = "okay";
> +};
> +
> +&pcie2_phy {
> + status = "okay";
> +};
> +
> +&pcie2_x2 {
> + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> +&pcie3_phy {
> + status = "okay";
> +};
> +
> +&pcie3_x2 {
> + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> &sdhc_1 {
> pinctrl-0 = <&sdc_default_state>;
> pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 062f80798ebb..a32dbdeb5bed 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -6,8 +6,8 @@
> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> -#include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>
> / {
> @@ -22,11 +22,41 @@
> #clock-cells = <0>;
> };
>
> + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
> +
> + pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <250000000>;
> + #clock-cells = <0>;
> + };
Why PIPE clocks are modeled as fixed clocks unlike other SoCs?
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> };
>
> + usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + #clock-cells = <0>;
> + };
Spurious?
> +
> xo_board_clk: xo-board-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -121,6 +151,155 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + pcie0_phy: phy@84000 {
> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> + reg = <0x00084000 0x1bc>; /* Serdes PLL */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
> + <&gcc GCC_PCIE0_AHB_CLK>,
> + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>;
> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
Care to explain what these anoc_lane and snoc_lane clocks are?
> +
> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
> + assigned-clock-rates = <20000000>;
> +
> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> + reset-names = "phy", "common";
> +
> + status = "disabled";
> +
> + pcie0_lane: phy@84200 {
> + reg = <0x00084200 0x16c>, /* Serdes Tx */
> + <0x00084400 0x200>, /* Serdes Rx */
> + <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */
> + <0x00084c00 0xf4>; /* pcs_misc */
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_pcie0_pipe_clk_src";
> + #clock-cells = <0>;
> + };
> + };
> +
[...]
> + pcie1_x1: pci@10000000 {
> + compatible = "qcom,pcie-ipq9574";
> + reg = <0x10000000 0xf1d>,
> + <0x10000F20 0xa8>,
> + <0x10001000 0x1000>,
> + <0x000F8000 0x4000>,
> + <0x10100000 0x1000>,
> + <0x00618108 0x4>;
> + reg-names = "dbi", "elbi", "atu", "parf", "config", "aggr_noc";
As I asked in the binding patch, why "aggr_noc" region is required?
> + device_type = "pci";
> + linux,pci-domain = <2>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0x10200000 0x10200000
> + 0 0x00100000 /* downstream I/O */
> + 0x82000000 0 0x10300000 0x10300000
> + 0 0x07d00000>; /* non-prefetchable memory */
Don't split the ranges and encode them in a single line.
Also, the I'm not sure why you have set the relocatable flag (n) for both
ranges i.e., in 0x81000000 and 0x82000000.
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 35
> + IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 49
> + IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 84
> + IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 85
> + IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
Again, wrap the interrupts in a single line.
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "global_irq";
> +
Linux doesn't support global_irq yet. But since devicetree is supposed to
describe the hardware, you can keep it.
Above comment applies to rest of the PCIe nodes.
> + /* clocks and clock-names are used to enable the clock in CBCR */
> + clocks = <&gcc GCC_PCIE1_AHB_CLK>,
> + <&gcc GCC_PCIE1_AUX_CLK>,
> + <&gcc GCC_PCIE1_AXI_M_CLK>,
> + <&gcc GCC_PCIE1_AXI_S_CLK>,
> + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_PCIE1_RCHNG_CLK>;
> + clock-names = "ahb",
> + "aux",
> + "axi_m",
> + "axi_s",
> + "axi_bridge",
> + "rchng";
> +
> + resets = <&gcc GCC_PCIE1_PIPE_ARES>,
> + <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
> + <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
> + <&gcc GCC_PCIE1_AXI_S_ARES>,
> + <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
> + <&gcc GCC_PCIE1_AXI_M_ARES>,
> + <&gcc GCC_PCIE1_AUX_ARES>,
> + <&gcc GCC_PCIE1_AHB_ARES>;
> + reset-names = "pipe",
> + "sticky",
> + "axi_s_sticky",
> + "axi_s",
> + "axi_m_sticky",
> + "axi_m",
> + "aux",
> + "ahb";
> +
> + phys = <&pcie1_lane>;
> + phy-names = "pciephy";
> + msi-parent = <&v2m0>;
> + status = "disabled";
> + };
> +
[...]
> + pcie2_x2: pci@20000000 {
> + compatible = "qcom,pcie-ipq9574";
> + reg = <0x20000000 0xf1d>,
> + <0x20000F20 0xa8>,
> + <0x20001000 0x1000>,
> + <0x00088000 0x4000>,
> + <0x20100000 0x1000>;
> + reg-names = "dbi", "elbi", "atu", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <3>;
> + bus-range = <0x00 0xff>;
> + num-lanes =<2>;
Space after =
Thanks,
Mani
--
மணிவண்ணன் சதாசிவம்
On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
> On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
>> Document the compatible for IPQ9574
>>
Hi Mani, Thanks for taking time to review the patch.
>
> You didn't mention about the "msi-parent" property that is being added
> by this patch
Sure, will update the commit message in the next spin
>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
>> 1 file changed, 70 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> index 872817d6d2bd..dabdf2684e2d 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> @@ -26,6 +26,7 @@ properties:
>> - qcom,pcie-ipq8064-v2
>> - qcom,pcie-ipq8074
>> - qcom,pcie-ipq8074-gen3
>> + - qcom,pcie-ipq9574
>> - qcom,pcie-msm8996
>> - qcom,pcie-qcs404
>> - qcom,pcie-sa8540p
>> @@ -44,11 +45,11 @@ properties:
>>
>> reg:
>> minItems: 4
>> - maxItems: 5
>> + maxItems: 6
>>
>> reg-names:
>> minItems: 4
>> - maxItems: 5
>> + maxItems: 6
>>
>> interrupts:
>> minItems: 1
>> @@ -105,6 +106,8 @@ properties:
>> items:
>> - const: pciephy
>>
>> + msi-parent: true
>> +
>> power-domains:
>> maxItems: 1
>>
>> @@ -173,6 +176,27 @@ allOf:
>> - const: parf # Qualcomm specific registers
>> - const: config # PCIe configuration space
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,pcie-ipq9574
>> + then:
>> + properties:
>> + reg:
>> + minItems: 5
>> + maxItems: 6
>> + reg-names:
>> + minItems: 5
>> + items:
>> + - const: dbi # DesignWare PCIe registers
>> + - const: elbi # External local bus interface registers
>> + - const: atu # ATU address space
>> + - const: parf # Qualcomm specific registers
>> + - const: config # PCIe configuration space
>> + - const: aggr_noc #PCIe aggr_noc
>
> Why do you need this region unlike other SoCs? Is the driver making use of it?
We have the aggr_noc region in ipq9574 to achieve higher throughput & to
handle multiple PCIe instances. The driver uses it to rate adapt 1-lane
PCIe clocks. My bad, missed it. Will add the driver changes in V2.
>
> Thanks,
> Mani
>
>> +
>> - if:
>> properties:
>> compatible:
>> @@ -365,6 +389,39 @@ allOf:
>> - const: ahb # AHB Reset
>> - const: axi_m_sticky # AXI Master Sticky reset
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,pcie-ipq9574
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 6
>> + maxItems: 6
>> + clock-names:
>> + items:
>> + - const: ahb # AHB clock
>> + - const: aux # Auxiliary clock
>> + - const: axi_m # AXI Master clock
>> + - const: axi_s # AXI Slave clock
>> + - const: axi_bridge # AXI bridge clock
>> + - const: rchng
>> + resets:
>> + minItems: 8
>> + maxItems: 8
>> + reset-names:
>> + items:
>> + - const: pipe # PIPE reset
>> + - const: sticky # Core Sticky reset
>> + - const: axi_s_sticky # AXI Slave Sticky reset
>> + - const: axi_s # AXI Slave reset
>> + - const: axi_m_sticky # AXI Master Sticky reset
>> + - const: axi_m # AXI Master reset
>> + - const: aux # AUX Reset
>> + - const: ahb # AHB Reset
>> +
>> - if:
>> properties:
>> compatible:
>> @@ -681,6 +738,16 @@ allOf:
>> - interconnects
>> - interconnect-names
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,pcie-ipq9574
>> + then:
>> + required:
>> + - msi-parent
>> +
>> - if:
>> not:
>> properties:
>> @@ -693,6 +760,7 @@ allOf:
>> - qcom,pcie-ipq8064v2
>> - qcom,pcie-ipq8074
>> - qcom,pcie-ipq8074-gen3
>> + - qcom,pcie-ipq9574
>> - qcom,pcie-qcs404
>> then:
>> required:
>> --
>> 2.17.1
>>
>
Thanks,
Devi Priya
On 2/24/2023 1:59 PM, Manivannan Sadhasivam wrote:
> On Tue, Feb 14, 2023 at 10:11:30PM +0530, Devi Priya wrote:
>> Adding PCIe support for IPQ9574 SoC
>>
>
> Please add some information about the PCIe IP in the commit message.
> Like, the Synopsys IP version, Gen speed etc... and how the support
> is added (using existing config or a new one).
>
> As others have mentioned, you could reuse the existing config. In that
> case, add the info in commit message as I suggested above.
>
> And the PCI patch should come last in the series after bindings and dts
> patches.
>
Sure, will update this accordingly in the next spin
> Thanks,
> Mani
>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
>> 1 file changed, 119 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index a232b04af048..57606c113d45 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>> struct reset_control *rst;
>> };
>>
>> +struct qcom_pcie_resources_1_27_0 {
>> + struct clk_bulk_data *clks;
>> + struct reset_control *rst;
>> + int num_clks;
>> +};
>> +
>> union qcom_pcie_resources {
>> struct qcom_pcie_resources_1_0_0 v1_0_0;
>> struct qcom_pcie_resources_2_1_0 v2_1_0;
>> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>> struct qcom_pcie_resources_2_4_0 v2_4_0;
>> struct qcom_pcie_resources_2_7_0 v2_7_0;
>> struct qcom_pcie_resources_2_9_0 v2_9_0;
>> + struct qcom_pcie_resources_1_27_0 v1_27_0;
>> };
>>
>> struct qcom_pcie;
>> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
>> return 0;
>> }
>>
>> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> + struct dw_pcie *pci = pcie->pci;
>> + struct device *dev = pci->dev;
>> +
>> + res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
>> + if (res->clks < 0)
>> + return res->num_clks;
>> +
>> + res->rst = devm_reset_control_array_get_exclusive(dev);
>> + if (IS_ERR(res->rst))
>> + return PTR_ERR(res->rst);
>> +
>> + return 0;
>> +}
>> +
>> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> +
>> + clk_bulk_disable_unprepare(res->num_clks, res->clks);
>> +}
>> +
>> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
>> + struct device *dev = pcie->pci->dev;
>> + int ret;
>> +
>> + ret = reset_control_assert(res->rst);
>> + if (ret) {
>> + dev_err(dev, "reset assert failed (%d)\n", ret);
>> + return ret;
>> + }
>> +
>> + /*
>> + * Delay periods before and after reset deassert are working values
>> + * from downstream Codeaurora kernel
>> + */
>> + usleep_range(2000, 2500);
>> +
>> + ret = reset_control_deassert(res->rst);
>> + if (ret) {
>> + dev_err(dev, "reset deassert failed (%d)\n", ret);
>> + return ret;
>> + }
>> +
>> + usleep_range(2000, 2500);
>> +
>> + return clk_bulk_prepare_enable(res->num_clks, res->clks);
>> +}
>> +
>> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
>> +{
>> + struct dw_pcie *pci = pcie->pci;
>> + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> + u32 val;
>> + int i;
>> +
>> + writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
>> +
>> + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
>> + val &= ~BIT(0);
>> + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>> +
>> + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
>> +
>> + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
>> + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
>> + pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>> + writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
>> + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
>> + pci->dbi_base + GEN3_RELATED_OFF);
>> +
>> + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
>> + SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
>> + AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
>> + pcie->parf + PCIE20_PARF_SYS_CTRL);
>> +
>> + writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
>> +
>> + dw_pcie_dbi_ro_wr_en(pci);
>> + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>> +
>> + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> + val &= ~PCI_EXP_LNKCAP_ASPMS;
>> + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
>> +
>> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>> + PCI_EXP_DEVCTL2);
>> +
>> + for (i = 0; i < 256; i++)
>> + writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
>> +
>> + return 0;
>> +}
>> +
>> static int qcom_pcie_link_up(struct dw_pcie *pci)
>> {
>> u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>> .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>> };
>>
>> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
>> +static const struct qcom_pcie_ops ops_1_27_0 = {
>> + .get_resources = qcom_pcie_get_resources_1_27_0,
>> + .init = qcom_pcie_init_1_27_0,
>> + .post_init = qcom_pcie_post_init_1_27_0,
>> + .deinit = qcom_pcie_deinit_1_27_0,
>> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>> +};
>> +
>> static const struct qcom_pcie_cfg cfg_1_0_0 = {
>> .ops = &ops_1_0_0,
>> };
>> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>> .ops = &ops_2_9_0,
>> };
>>
>> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
>> + .ops = &ops_1_27_0,
>> +};
>> +
>> static const struct dw_pcie_ops dw_pcie_ops = {
>> .link_up = qcom_pcie_link_up,
>> .start_link = qcom_pcie_start_link,
>> @@ -1829,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>> { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>> { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>> { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
>> + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },
>> { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
>> { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
>> { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
>> --
>> 2.17.1
>>
>
Thanks,
Devi Priya
On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
>
>
> On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
> > On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
> > > Document the compatible for IPQ9574
> > >
> Hi Mani, Thanks for taking time to review the patch.
> >
> > You didn't mention about the "msi-parent" property that is being added
> > by this patch
> Sure, will update the commit message in the next spin
> >
> > > Signed-off-by: Devi Priya <[email protected]>
> > > ---
> > > .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
> > > 1 file changed, 70 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > index 872817d6d2bd..dabdf2684e2d 100644
> > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > @@ -26,6 +26,7 @@ properties:
> > > - qcom,pcie-ipq8064-v2
> > > - qcom,pcie-ipq8074
> > > - qcom,pcie-ipq8074-gen3
> > > + - qcom,pcie-ipq9574
> > > - qcom,pcie-msm8996
> > > - qcom,pcie-qcs404
> > > - qcom,pcie-sa8540p
> > > @@ -44,11 +45,11 @@ properties:
> > > reg:
> > > minItems: 4
> > > - maxItems: 5
> > > + maxItems: 6
> > > reg-names:
> > > minItems: 4
> > > - maxItems: 5
> > > + maxItems: 6
> > > interrupts:
> > > minItems: 1
> > > @@ -105,6 +106,8 @@ properties:
> > > items:
> > > - const: pciephy
> > > + msi-parent: true
> > > +
> > > power-domains:
> > > maxItems: 1
> > > @@ -173,6 +176,27 @@ allOf:
> > > - const: parf # Qualcomm specific registers
> > > - const: config # PCIe configuration space
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,pcie-ipq9574
> > > + then:
> > > + properties:
> > > + reg:
> > > + minItems: 5
> > > + maxItems: 6
> > > + reg-names:
> > > + minItems: 5
> > > + items:
> > > + - const: dbi # DesignWare PCIe registers
> > > + - const: elbi # External local bus interface registers
> > > + - const: atu # ATU address space
> > > + - const: parf # Qualcomm specific registers
> > > + - const: config # PCIe configuration space
> > > + - const: aggr_noc #PCIe aggr_noc
> >
> > Why do you need this region unlike other SoCs? Is the driver making use of it?
> We have the aggr_noc region in ipq9574 to achieve higher throughput & to
> handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
> clocks. My bad, missed it. Will add the driver changes in V2.
Hmm, this is something new. How can you achieve higher throughput with this
region? Can you explain more on how it is used?
Thanks,
Mani
> >
> > Thanks,
> > Mani
> >
> > > +
> > > - if:
> > > properties:
> > > compatible:
> > > @@ -365,6 +389,39 @@ allOf:
> > > - const: ahb # AHB Reset
> > > - const: axi_m_sticky # AXI Master Sticky reset
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,pcie-ipq9574
> > > + then:
> > > + properties:
> > > + clocks:
> > > + minItems: 6
> > > + maxItems: 6
> > > + clock-names:
> > > + items:
> > > + - const: ahb # AHB clock
> > > + - const: aux # Auxiliary clock
> > > + - const: axi_m # AXI Master clock
> > > + - const: axi_s # AXI Slave clock
> > > + - const: axi_bridge # AXI bridge clock
> > > + - const: rchng
> > > + resets:
> > > + minItems: 8
> > > + maxItems: 8
> > > + reset-names:
> > > + items:
> > > + - const: pipe # PIPE reset
> > > + - const: sticky # Core Sticky reset
> > > + - const: axi_s_sticky # AXI Slave Sticky reset
> > > + - const: axi_s # AXI Slave reset
> > > + - const: axi_m_sticky # AXI Master Sticky reset
> > > + - const: axi_m # AXI Master reset
> > > + - const: aux # AUX Reset
> > > + - const: ahb # AHB Reset
> > > +
> > > - if:
> > > properties:
> > > compatible:
> > > @@ -681,6 +738,16 @@ allOf:
> > > - interconnects
> > > - interconnect-names
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,pcie-ipq9574
> > > + then:
> > > + required:
> > > + - msi-parent
> > > +
> > > - if:
> > > not:
> > > properties:
> > > @@ -693,6 +760,7 @@ allOf:
> > > - qcom,pcie-ipq8064v2
> > > - qcom,pcie-ipq8074
> > > - qcom,pcie-ipq8074-gen3
> > > + - qcom,pcie-ipq9574
> > > - qcom,pcie-qcs404
> > > then:
> > > required:
> > > --
> > > 2.17.1
> > >
> >
> Thanks,
> Devi Priya
--
மணிவண்ணன் சதாசிவம்
On 2/24/2023 12:27 PM, Kathiravan T wrote:
>
> On 2/14/2023 10:11 PM, Devi Priya wrote:
>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>> found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 ++
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 ++++++++++++++++++-
>> 2 files changed, 499 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> index 2c8430197ec0..21b53f34ce84 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -8,6 +8,7 @@
>> /dts-v1/;
>> +#include <dt-bindings/gpio/gpio.h>
>> #include "ipq9574.dtsi"
>> / {
>> @@ -29,6 +30,33 @@
>> status = "okay";
>> };
>> +&pcie1_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie1_x1 {
>> + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> +&pcie2_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie2_x2 {
>> + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> +&pcie3_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie3_x2 {
>> + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> pinctrl-0 = <&sdc_default_state>;
>> pinctrl-names = "default";
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 062f80798ebb..a32dbdeb5bed 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -6,8 +6,8 @@
>> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> */
>> -#include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> / {
>> @@ -22,11 +22,41 @@
>> #clock-cells = <0>;
>> };
>> + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> sleep_clk: sleep-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> };
>> + usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <125000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> xo_board_clk: xo-board-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> @@ -121,6 +151,155 @@
>> #size-cells = <1>;
>> ranges = <0 0 0 0xffffffff>;
>> + pcie0_phy: phy@84000 {
>> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> + reg = <0x00084000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
>> + <&gcc GCC_PCIE0_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie0_lane: phy@84200 {
>> + reg = <0x00084200 0x16c>, /* Serdes Tx */
>> + <0x00084400 0x200>, /* Serdes Rx */
>> + <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x00084c00 0xf4>; /* pcs_misc */
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie0_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + pcie2_phy: phy@8c000 {
>> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
>> + reg = <0x0008c000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_PCIE2_AUX_CLK>,
>> + <&gcc GCC_PCIE2_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE2_PHY_BCR>,
>> + <&gcc GCC_PCIE2PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie2_lanes: phy@8c200 {
>> + reg = <0x0008c200 0x16c>, /* Serdes Tx0 */
>> + <0x0008c400 0x200>, /* Serdes Rx0 */
>> + <0x0008d000 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x0008c600 0x16c>, /* Serdes Tx1 */
>> + <0x0008c800 0x200>, /* Serdes Rx1 */
>> + <0x0008d400 0x0f8>; /* pcs_misc */
>> +
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE2_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie2_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + pcie3_phy: phy@f4000 {
>> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
>> + reg = <0x000f4000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_PCIE3_AUX_CLK>,
>> + <&gcc GCC_PCIE3_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE3_2LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE3_PHY_BCR>,
>> + <&gcc GCC_PCIE3PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie3_lanes: phy@f4200 {
>> + reg = <0x000f4200 0x16c>, /* Serdes Tx0 */
>> + <0x000f4400 0x200>, /* Serdes Rx0 */
>> + <0x000f5000 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x000f4600 0x16c>, /* Serdes Tx1 */
>> + <0x000f4800 0x200>, /* Serdes Rx1 */
>> + <0x000f5400 0x0f8>; /* pcs_misc */
>> +
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE3_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie3_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + pcie1_phy: phy@fc000 {
>> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> + reg = <0x000fc000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_PCIE1_AUX_CLK>,
>> + <&gcc GCC_PCIE1_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE1_1LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE1_1LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
>> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie1_lane: phy@fc200 {
>> + reg = <0x000fc200 0x16c>, /* Serdes Tx */
>> + <0x000fc400 0x200>, /* Serdes Rx */
>> + <0x000fc800 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x000fcc00 0xf4>; /* pcs_misc */
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie1_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> tlmm: pinctrl@1000000 {
>> compatible = "qcom,ipq9574-tlmm";
>> reg = <0x01000000 0x300000>;
>> @@ -145,11 +324,11 @@
>> clocks = <&xo_board_clk>,
>> <&sleep_clk>,
>> <&bias_pll_ubi_nc_clk>,
>> - <0>,
>> - <0>,
>> - <0>,
>> - <0>,
>> - <0>;
>> + <&pcie30_phy0_pipe_clk>,
>> + <&pcie30_phy1_pipe_clk>,
>> + <&pcie30_phy2_pipe_clk>,
>> + <&pcie30_phy3_pipe_clk>,
>> + <&usb3phy_0_cc_pipe_clk>;
>
>
> pipe clock source is PHY. So should we add the pcie_phy phandle here and
> use it like how it is done in other targets, ex: sm8550.dtsi?
Yes sure kathir. Will update this in the next series
>
>
>> #clock-cells = <1>;
>> #reset-cells = <1>;
>> #power-domain-cells = <1>;
>> @@ -282,6 +461,292 @@
>> status = "disabled";
>> };
>> };
>> +
>> + pcie1_x1: pci@10000000 {
>> + compatible = "qcom,pcie-ipq9574";
>> + reg = <0x10000000 0xf1d>,
>> + <0x10000F20 0xa8>,
>> + <0x10001000 0x1000>,
>> + <0x000F8000 0x4000>,
>> + <0x10100000 0x1000>,
>> + <0x00618108 0x4>;
>> + reg-names = "dbi", "elbi", "atu", "parf", "config",
>> "aggr_noc";
>> + device_type = "pci";
>> + linux,pci-domain = <2>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <1>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + ranges = <0x81000000 0 0x10200000 0x10200000
>> + 0 0x00100000 /* downstream I/O */
>> + 0x82000000 0 0x10300000 0x10300000
>> + 0 0x07d00000>; /* non-prefetchable memory */
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 35
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>> + <0 0 0 2 &intc 0 49
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_b */
>> + <0 0 0 3 &intc 0 84
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_c */
>> + <0 0 0 4 &intc 0 85
>> + IRQ_TYPE_LEVEL_HIGH>; /* int_d */
>> +
>> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "global_irq";
>
>
> Controller driver doesn't support the "global_irq" yet. Please correct
> me If I am wrong.
>
>
> Thanks, Kathiravan T.
>
Regards,
Devi Priya
28 февраля 2023 г. 08:33:58 GMT+02:00, Manivannan Sadhasivam <[email protected]> пишет:
>On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
>>
>>
>> On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
>> > On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
>> > > Document the compatible for IPQ9574
>> > >
>> Hi Mani, Thanks for taking time to review the patch.
>> >
>> > You didn't mention about the "msi-parent" property that is being added
>> > by this patch
>> Sure, will update the commit message in the next spin
>> >
>> > > Signed-off-by: Devi Priya <[email protected]>
>> > > ---
>> > > .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
>> > > 1 file changed, 70 insertions(+), 2 deletions(-)
>> > >
>> > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> > > index 872817d6d2bd..dabdf2684e2d 100644
>> > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> > > @@ -26,6 +26,7 @@ properties:
>> > > - qcom,pcie-ipq8064-v2
>> > > - qcom,pcie-ipq8074
>> > > - qcom,pcie-ipq8074-gen3
>> > > + - qcom,pcie-ipq9574
>> > > - qcom,pcie-msm8996
>> > > - qcom,pcie-qcs404
>> > > - qcom,pcie-sa8540p
>> > > @@ -44,11 +45,11 @@ properties:
>> > > reg:
>> > > minItems: 4
>> > > - maxItems: 5
>> > > + maxItems: 6
>> > > reg-names:
>> > > minItems: 4
>> > > - maxItems: 5
>> > > + maxItems: 6
>> > > interrupts:
>> > > minItems: 1
>> > > @@ -105,6 +106,8 @@ properties:
>> > > items:
>> > > - const: pciephy
>> > > + msi-parent: true
>> > > +
>> > > power-domains:
>> > > maxItems: 1
>> > > @@ -173,6 +176,27 @@ allOf:
>> > > - const: parf # Qualcomm specific registers
>> > > - const: config # PCIe configuration space
>> > > + - if:
>> > > + properties:
>> > > + compatible:
>> > > + contains:
>> > > + enum:
>> > > + - qcom,pcie-ipq9574
>> > > + then:
>> > > + properties:
>> > > + reg:
>> > > + minItems: 5
>> > > + maxItems: 6
>> > > + reg-names:
>> > > + minItems: 5
>> > > + items:
>> > > + - const: dbi # DesignWare PCIe registers
>> > > + - const: elbi # External local bus interface registers
>> > > + - const: atu # ATU address space
>> > > + - const: parf # Qualcomm specific registers
>> > > + - const: config # PCIe configuration space
>> > > + - const: aggr_noc #PCIe aggr_noc
>> >
>> > Why do you need this region unlike other SoCs? Is the driver making use of it?
>> We have the aggr_noc region in ipq9574 to achieve higher throughput & to
>> handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
>> clocks. My bad, missed it. Will add the driver changes in V2.
>
>Hmm, this is something new. How can you achieve higher throughput with this
>region? Can you explain more on how it is used?
Based on the name of the region, it looks like it is an interconnect region.
Devi, if this is the case, then you have to handle it through the interconnect driver, rather than poking directly into these registers.
>
>Thanks,
>Mani
>
>> >
>> > Thanks,
>> > Mani
>> >
>> > > +
>> > > - if:
>> > > properties:
>> > > compatible:
>> > > @@ -365,6 +389,39 @@ allOf:
>> > > - const: ahb # AHB Reset
>> > > - const: axi_m_sticky # AXI Master Sticky reset
>> > > + - if:
>> > > + properties:
>> > > + compatible:
>> > > + contains:
>> > > + enum:
>> > > + - qcom,pcie-ipq9574
>> > > + then:
>> > > + properties:
>> > > + clocks:
>> > > + minItems: 6
>> > > + maxItems: 6
>> > > + clock-names:
>> > > + items:
>> > > + - const: ahb # AHB clock
>> > > + - const: aux # Auxiliary clock
>> > > + - const: axi_m # AXI Master clock
>> > > + - const: axi_s # AXI Slave clock
>> > > + - const: axi_bridge # AXI bridge clock
>> > > + - const: rchng
>> > > + resets:
>> > > + minItems: 8
>> > > + maxItems: 8
>> > > + reset-names:
>> > > + items:
>> > > + - const: pipe # PIPE reset
>> > > + - const: sticky # Core Sticky reset
>> > > + - const: axi_s_sticky # AXI Slave Sticky reset
>> > > + - const: axi_s # AXI Slave reset
>> > > + - const: axi_m_sticky # AXI Master Sticky reset
>> > > + - const: axi_m # AXI Master reset
>> > > + - const: aux # AUX Reset
>> > > + - const: ahb # AHB Reset
>> > > +
>> > > - if:
>> > > properties:
>> > > compatible:
>> > > @@ -681,6 +738,16 @@ allOf:
>> > > - interconnects
>> > > - interconnect-names
>> > > + - if:
>> > > + properties:
>> > > + compatible:
>> > > + contains:
>> > > + enum:
>> > > + - qcom,pcie-ipq9574
>> > > + then:
>> > > + required:
>> > > + - msi-parent
>> > > +
>> > > - if:
>> > > not:
>> > > properties:
>> > > @@ -693,6 +760,7 @@ allOf:
>> > > - qcom,pcie-ipq8064v2
>> > > - qcom,pcie-ipq8074
>> > > - qcom,pcie-ipq8074-gen3
>> > > + - qcom,pcie-ipq9574
>> > > - qcom,pcie-qcs404
>> > > then:
>> > > required:
>> > > --
>> > > 2.17.1
>> > >
>> >
>> Thanks,
>> Devi Priya
>
On Fri, Mar 03, 2023 at 05:16:58PM +0200, Dmitry Baryshkov wrote:
> 28 февраля 2023 г. 08:33:58 GMT+02:00, Manivannan Sadhasivam <[email protected]> пишет:
> >On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
> >>
> >>
> >> On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
> >> > On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
> >> > > Document the compatible for IPQ9574
> >> > >
> >> Hi Mani, Thanks for taking time to review the patch.
> >> >
> >> > You didn't mention about the "msi-parent" property that is being added
> >> > by this patch
> >> Sure, will update the commit message in the next spin
> >> >
> >> > > Signed-off-by: Devi Priya <[email protected]>
> >> > > ---
> >> > > .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
> >> > > 1 file changed, 70 insertions(+), 2 deletions(-)
> >> > >
> >> > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >> > > index 872817d6d2bd..dabdf2684e2d 100644
> >> > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >> > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >> > > @@ -26,6 +26,7 @@ properties:
> >> > > - qcom,pcie-ipq8064-v2
> >> > > - qcom,pcie-ipq8074
> >> > > - qcom,pcie-ipq8074-gen3
> >> > > + - qcom,pcie-ipq9574
> >> > > - qcom,pcie-msm8996
> >> > > - qcom,pcie-qcs404
> >> > > - qcom,pcie-sa8540p
> >> > > @@ -44,11 +45,11 @@ properties:
> >> > > reg:
> >> > > minItems: 4
> >> > > - maxItems: 5
> >> > > + maxItems: 6
> >> > > reg-names:
> >> > > minItems: 4
> >> > > - maxItems: 5
> >> > > + maxItems: 6
> >> > > interrupts:
> >> > > minItems: 1
> >> > > @@ -105,6 +106,8 @@ properties:
> >> > > items:
> >> > > - const: pciephy
> >> > > + msi-parent: true
> >> > > +
> >> > > power-domains:
> >> > > maxItems: 1
> >> > > @@ -173,6 +176,27 @@ allOf:
> >> > > - const: parf # Qualcomm specific registers
> >> > > - const: config # PCIe configuration space
> >> > > + - if:
> >> > > + properties:
> >> > > + compatible:
> >> > > + contains:
> >> > > + enum:
> >> > > + - qcom,pcie-ipq9574
> >> > > + then:
> >> > > + properties:
> >> > > + reg:
> >> > > + minItems: 5
> >> > > + maxItems: 6
> >> > > + reg-names:
> >> > > + minItems: 5
> >> > > + items:
> >> > > + - const: dbi # DesignWare PCIe registers
> >> > > + - const: elbi # External local bus interface registers
> >> > > + - const: atu # ATU address space
> >> > > + - const: parf # Qualcomm specific registers
> >> > > + - const: config # PCIe configuration space
> >> > > + - const: aggr_noc #PCIe aggr_noc
> >> >
> >> > Why do you need this region unlike other SoCs? Is the driver making use of it?
> >> We have the aggr_noc region in ipq9574 to achieve higher throughput & to
> >> handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
> >> clocks. My bad, missed it. Will add the driver changes in V2.
> >
> >Hmm, this is something new. How can you achieve higher throughput with this
> >region? Can you explain more on how it is used?
>
> Based on the name of the region, it looks like it is an interconnect region.
>
Well, we only have BCM based interconnects so far. That's why I was curious
about this region and its purpose.
> Devi, if this is the case, then you have to handle it through the interconnect driver, rather than poking directly into these registers.
If that so, it doesn't need to be added in this series itself. I believe that
without aggr_noc region, the PCIe controller can still function properly with
reduced performance. But you can add the interconnect support later as a
separate series.
Thanks,
Mani
>
>
> >
> >Thanks,
> >Mani
> >
> >> >
> >> > Thanks,
> >> > Mani
> >> >
> >> > > +
> >> > > - if:
> >> > > properties:
> >> > > compatible:
> >> > > @@ -365,6 +389,39 @@ allOf:
> >> > > - const: ahb # AHB Reset
> >> > > - const: axi_m_sticky # AXI Master Sticky reset
> >> > > + - if:
> >> > > + properties:
> >> > > + compatible:
> >> > > + contains:
> >> > > + enum:
> >> > > + - qcom,pcie-ipq9574
> >> > > + then:
> >> > > + properties:
> >> > > + clocks:
> >> > > + minItems: 6
> >> > > + maxItems: 6
> >> > > + clock-names:
> >> > > + items:
> >> > > + - const: ahb # AHB clock
> >> > > + - const: aux # Auxiliary clock
> >> > > + - const: axi_m # AXI Master clock
> >> > > + - const: axi_s # AXI Slave clock
> >> > > + - const: axi_bridge # AXI bridge clock
> >> > > + - const: rchng
> >> > > + resets:
> >> > > + minItems: 8
> >> > > + maxItems: 8
> >> > > + reset-names:
> >> > > + items:
> >> > > + - const: pipe # PIPE reset
> >> > > + - const: sticky # Core Sticky reset
> >> > > + - const: axi_s_sticky # AXI Slave Sticky reset
> >> > > + - const: axi_s # AXI Slave reset
> >> > > + - const: axi_m_sticky # AXI Master Sticky reset
> >> > > + - const: axi_m # AXI Master reset
> >> > > + - const: aux # AUX Reset
> >> > > + - const: ahb # AHB Reset
> >> > > +
> >> > > - if:
> >> > > properties:
> >> > > compatible:
> >> > > @@ -681,6 +738,16 @@ allOf:
> >> > > - interconnects
> >> > > - interconnect-names
> >> > > + - if:
> >> > > + properties:
> >> > > + compatible:
> >> > > + contains:
> >> > > + enum:
> >> > > + - qcom,pcie-ipq9574
> >> > > + then:
> >> > > + required:
> >> > > + - msi-parent
> >> > > +
> >> > > - if:
> >> > > not:
> >> > > properties:
> >> > > @@ -693,6 +760,7 @@ allOf:
> >> > > - qcom,pcie-ipq8064v2
> >> > > - qcom,pcie-ipq8074
> >> > > - qcom,pcie-ipq8074-gen3
> >> > > + - qcom,pcie-ipq9574
> >> > > - qcom,pcie-qcs404
> >> > > then:
> >> > > required:
> >> > > --
> >> > > 2.17.1
> >> > >
> >> >
> >> Thanks,
> >> Devi Priya
> >
>
--
மணிவண்ணன் சதாசிவம்
On 3/3/2023 11:10 PM, Manivannan Sadhasivam wrote:
> On Fri, Mar 03, 2023 at 05:16:58PM +0200, Dmitry Baryshkov wrote:
>> 28 февраля 2023 г. 08:33:58 GMT+02:00, Manivannan Sadhasivam <[email protected]> пишет:
>>> On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
>>>>
>>>>
>>>> On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
>>>>> On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
>>>>>> Document the compatible for IPQ9574
>>>>>>
>>>> Hi Mani, Thanks for taking time to review the patch.
>>>>>
>>>>> You didn't mention about the "msi-parent" property that is being added
>>>>> by this patch
>>>> Sure, will update the commit message in the next spin
>>>>>
>>>>>> Signed-off-by: Devi Priya <[email protected]>
>>>>>> ---
>>>>>> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
>>>>>> 1 file changed, 70 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>> index 872817d6d2bd..dabdf2684e2d 100644
>>>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>> @@ -26,6 +26,7 @@ properties:
>>>>>> - qcom,pcie-ipq8064-v2
>>>>>> - qcom,pcie-ipq8074
>>>>>> - qcom,pcie-ipq8074-gen3
>>>>>> + - qcom,pcie-ipq9574
>>>>>> - qcom,pcie-msm8996
>>>>>> - qcom,pcie-qcs404
>>>>>> - qcom,pcie-sa8540p
>>>>>> @@ -44,11 +45,11 @@ properties:
>>>>>> reg:
>>>>>> minItems: 4
>>>>>> - maxItems: 5
>>>>>> + maxItems: 6
>>>>>> reg-names:
>>>>>> minItems: 4
>>>>>> - maxItems: 5
>>>>>> + maxItems: 6
>>>>>> interrupts:
>>>>>> minItems: 1
>>>>>> @@ -105,6 +106,8 @@ properties:
>>>>>> items:
>>>>>> - const: pciephy
>>>>>> + msi-parent: true
>>>>>> +
>>>>>> power-domains:
>>>>>> maxItems: 1
>>>>>> @@ -173,6 +176,27 @@ allOf:
>>>>>> - const: parf # Qualcomm specific registers
>>>>>> - const: config # PCIe configuration space
>>>>>> + - if:
>>>>>> + properties:
>>>>>> + compatible:
>>>>>> + contains:
>>>>>> + enum:
>>>>>> + - qcom,pcie-ipq9574
>>>>>> + then:
>>>>>> + properties:
>>>>>> + reg:
>>>>>> + minItems: 5
>>>>>> + maxItems: 6
>>>>>> + reg-names:
>>>>>> + minItems: 5
>>>>>> + items:
>>>>>> + - const: dbi # DesignWare PCIe registers
>>>>>> + - const: elbi # External local bus interface registers
>>>>>> + - const: atu # ATU address space
>>>>>> + - const: parf # Qualcomm specific registers
>>>>>> + - const: config # PCIe configuration space
>>>>>> + - const: aggr_noc #PCIe aggr_noc
>>>>>
>>>>> Why do you need this region unlike other SoCs? Is the driver making use of it?
>>>> We have the aggr_noc region in ipq9574 to achieve higher throughput & to
>>>> handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
>>>> clocks. My bad, missed it. Will add the driver changes in V2.
>>>
>>> Hmm, this is something new. How can you achieve higher throughput with this
>>> region? Can you explain more on how it is used?
>>
>> Based on the name of the region, it looks like it is an interconnect region.
>>
>
> Well, we only have BCM based interconnects so far. That's why I was curious
> about this region and its purpose.
For connected PCIe slave devices that are running at frequency lesser
than the ANOC frequency (342MHz), the rate adapter of ANOC needs to be
configured
>
>> Devi, if this is the case, then you have to handle it through the interconnect driver, rather than poking directly into these registers.
>
> If that so, it doesn't need to be added in this series itself. I believe that
> without aggr_noc region, the PCIe controller can still function properly with
> reduced performance. But you can add the interconnect support later as a
> separate series.
Sure, okay. The ANOC runs at a fixed frequency of 342MHz and the
interconnect clocks are not scaled. The aggr_noc register is just a
magic register for configuring it's rate adapter to ensure no wait
cycles are inserted.
>
> Thanks,
> Mani
>
>>
>>
>>>
>>> Thanks,
>>> Mani
>>>
>>>>>
>>>>> Thanks,
>>>>> Mani
>>>>>
>>>>>> +
>>>>>> - if:
>>>>>> properties:
>>>>>> compatible:
>>>>>> @@ -365,6 +389,39 @@ allOf:
>>>>>> - const: ahb # AHB Reset
>>>>>> - const: axi_m_sticky # AXI Master Sticky reset
>>>>>> + - if:
>>>>>> + properties:
>>>>>> + compatible:
>>>>>> + contains:
>>>>>> + enum:
>>>>>> + - qcom,pcie-ipq9574
>>>>>> + then:
>>>>>> + properties:
>>>>>> + clocks:
>>>>>> + minItems: 6
>>>>>> + maxItems: 6
>>>>>> + clock-names:
>>>>>> + items:
>>>>>> + - const: ahb # AHB clock
>>>>>> + - const: aux # Auxiliary clock
>>>>>> + - const: axi_m # AXI Master clock
>>>>>> + - const: axi_s # AXI Slave clock
>>>>>> + - const: axi_bridge # AXI bridge clock
>>>>>> + - const: rchng
>>>>>> + resets:
>>>>>> + minItems: 8
>>>>>> + maxItems: 8
>>>>>> + reset-names:
>>>>>> + items:
>>>>>> + - const: pipe # PIPE reset
>>>>>> + - const: sticky # Core Sticky reset
>>>>>> + - const: axi_s_sticky # AXI Slave Sticky reset
>>>>>> + - const: axi_s # AXI Slave reset
>>>>>> + - const: axi_m_sticky # AXI Master Sticky reset
>>>>>> + - const: axi_m # AXI Master reset
>>>>>> + - const: aux # AUX Reset
>>>>>> + - const: ahb # AHB Reset
>>>>>> +
>>>>>> - if:
>>>>>> properties:
>>>>>> compatible:
>>>>>> @@ -681,6 +738,16 @@ allOf:
>>>>>> - interconnects
>>>>>> - interconnect-names
>>>>>> + - if:
>>>>>> + properties:
>>>>>> + compatible:
>>>>>> + contains:
>>>>>> + enum:
>>>>>> + - qcom,pcie-ipq9574
>>>>>> + then:
>>>>>> + required:
>>>>>> + - msi-parent
>>>>>> +
>>>>>> - if:
>>>>>> not:
>>>>>> properties:
>>>>>> @@ -693,6 +760,7 @@ allOf:
>>>>>> - qcom,pcie-ipq8064v2
>>>>>> - qcom,pcie-ipq8074
>>>>>> - qcom,pcie-ipq8074-gen3
>>>>>> + - qcom,pcie-ipq9574
>>>>>> - qcom,pcie-qcs404
>>>>>> then:
>>>>>> required:
>>>>>> --
>>>>>> 2.17.1
>>>>>>
>>>>>
>>>> Thanks,
>>>> Devi Priya
>>>
>>
>
Thanks,
Devi Priya
On Tue, 7 Mar 2023 at 11:45, Devi Priya <[email protected]> wrote:
>
>
>
> On 3/3/2023 11:10 PM, Manivannan Sadhasivam wrote:
> > On Fri, Mar 03, 2023 at 05:16:58PM +0200, Dmitry Baryshkov wrote:
> >> 28 февраля 2023 г. 08:33:58 GMT+02:00, Manivannan Sadhasivam <[email protected]> пишет:
> >>> On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
> >>>>
> >>>>
> >>>> On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
> >>>>> On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
> >>>>>> Document the compatible for IPQ9574
> >>>>>>
> >>>> Hi Mani, Thanks for taking time to review the patch.
> >>>>>
> >>>>> You didn't mention about the "msi-parent" property that is being added
> >>>>> by this patch
> >>>> Sure, will update the commit message in the next spin
> >>>>>
> >>>>>> Signed-off-by: Devi Priya <[email protected]>
> >>>>>> ---
> >>>>>> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
> >>>>>> 1 file changed, 70 insertions(+), 2 deletions(-)
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >>>>>> index 872817d6d2bd..dabdf2684e2d 100644
> >>>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >>>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >>>>>> @@ -26,6 +26,7 @@ properties:
> >>>>>> - qcom,pcie-ipq8064-v2
> >>>>>> - qcom,pcie-ipq8074
> >>>>>> - qcom,pcie-ipq8074-gen3
> >>>>>> + - qcom,pcie-ipq9574
> >>>>>> - qcom,pcie-msm8996
> >>>>>> - qcom,pcie-qcs404
> >>>>>> - qcom,pcie-sa8540p
> >>>>>> @@ -44,11 +45,11 @@ properties:
> >>>>>> reg:
> >>>>>> minItems: 4
> >>>>>> - maxItems: 5
> >>>>>> + maxItems: 6
> >>>>>> reg-names:
> >>>>>> minItems: 4
> >>>>>> - maxItems: 5
> >>>>>> + maxItems: 6
> >>>>>> interrupts:
> >>>>>> minItems: 1
> >>>>>> @@ -105,6 +106,8 @@ properties:
> >>>>>> items:
> >>>>>> - const: pciephy
> >>>>>> + msi-parent: true
> >>>>>> +
> >>>>>> power-domains:
> >>>>>> maxItems: 1
> >>>>>> @@ -173,6 +176,27 @@ allOf:
> >>>>>> - const: parf # Qualcomm specific registers
> >>>>>> - const: config # PCIe configuration space
> >>>>>> + - if:
> >>>>>> + properties:
> >>>>>> + compatible:
> >>>>>> + contains:
> >>>>>> + enum:
> >>>>>> + - qcom,pcie-ipq9574
> >>>>>> + then:
> >>>>>> + properties:
> >>>>>> + reg:
> >>>>>> + minItems: 5
> >>>>>> + maxItems: 6
> >>>>>> + reg-names:
> >>>>>> + minItems: 5
> >>>>>> + items:
> >>>>>> + - const: dbi # DesignWare PCIe registers
> >>>>>> + - const: elbi # External local bus interface registers
> >>>>>> + - const: atu # ATU address space
> >>>>>> + - const: parf # Qualcomm specific registers
> >>>>>> + - const: config # PCIe configuration space
> >>>>>> + - const: aggr_noc #PCIe aggr_noc
> >>>>>
> >>>>> Why do you need this region unlike other SoCs? Is the driver making use of it?
> >>>> We have the aggr_noc region in ipq9574 to achieve higher throughput & to
> >>>> handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
> >>>> clocks. My bad, missed it. Will add the driver changes in V2.
> >>>
> >>> Hmm, this is something new. How can you achieve higher throughput with this
> >>> region? Can you explain more on how it is used?
> >>
> >> Based on the name of the region, it looks like it is an interconnect region.
> >>
> >
> > Well, we only have BCM based interconnects so far. That's why I was curious
> > about this region and its purpose.
> For connected PCIe slave devices that are running at frequency lesser
> than the ANOC frequency (342MHz), the rate adapter of ANOC needs to be
> configured
> >
> >> Devi, if this is the case, then you have to handle it through the interconnect driver, rather than poking directly into these registers.
> >
> > If that so, it doesn't need to be added in this series itself. I believe that
> > without aggr_noc region, the PCIe controller can still function properly with
> > reduced performance. But you can add the interconnect support later as a
> > separate series.
> Sure, okay. The ANOC runs at a fixed frequency of 342MHz and the
> interconnect clocks are not scaled. The aggr_noc register is just a
> magic register for configuring it's rate adapter to ensure no wait
> cycles are inserted.
I have been hesitant at some point, but this looks more and more like
a special kind of interconnect. Please consider moving all the NoC
stuff into a separate driver implementing the ICC API.
>
> >
> > Thanks,
> > Mani
> >
> >>
> >>
> >>>
> >>> Thanks,
> >>> Mani
> >>>
> >>>>>
> >>>>> Thanks,
> >>>>> Mani
> >>>>>
> >>>>>> +
> >>>>>> - if:
> >>>>>> properties:
> >>>>>> compatible:
> >>>>>> @@ -365,6 +389,39 @@ allOf:
> >>>>>> - const: ahb # AHB Reset
> >>>>>> - const: axi_m_sticky # AXI Master Sticky reset
> >>>>>> + - if:
> >>>>>> + properties:
> >>>>>> + compatible:
> >>>>>> + contains:
> >>>>>> + enum:
> >>>>>> + - qcom,pcie-ipq9574
> >>>>>> + then:
> >>>>>> + properties:
> >>>>>> + clocks:
> >>>>>> + minItems: 6
> >>>>>> + maxItems: 6
> >>>>>> + clock-names:
> >>>>>> + items:
> >>>>>> + - const: ahb # AHB clock
> >>>>>> + - const: aux # Auxiliary clock
> >>>>>> + - const: axi_m # AXI Master clock
> >>>>>> + - const: axi_s # AXI Slave clock
> >>>>>> + - const: axi_bridge # AXI bridge clock
> >>>>>> + - const: rchng
> >>>>>> + resets:
> >>>>>> + minItems: 8
> >>>>>> + maxItems: 8
> >>>>>> + reset-names:
> >>>>>> + items:
> >>>>>> + - const: pipe # PIPE reset
> >>>>>> + - const: sticky # Core Sticky reset
> >>>>>> + - const: axi_s_sticky # AXI Slave Sticky reset
> >>>>>> + - const: axi_s # AXI Slave reset
> >>>>>> + - const: axi_m_sticky # AXI Master Sticky reset
> >>>>>> + - const: axi_m # AXI Master reset
> >>>>>> + - const: aux # AUX Reset
> >>>>>> + - const: ahb # AHB Reset
> >>>>>> +
> >>>>>> - if:
> >>>>>> properties:
> >>>>>> compatible:
> >>>>>> @@ -681,6 +738,16 @@ allOf:
> >>>>>> - interconnects
> >>>>>> - interconnect-names
> >>>>>> + - if:
> >>>>>> + properties:
> >>>>>> + compatible:
> >>>>>> + contains:
> >>>>>> + enum:
> >>>>>> + - qcom,pcie-ipq9574
> >>>>>> + then:
> >>>>>> + required:
> >>>>>> + - msi-parent
> >>>>>> +
> >>>>>> - if:
> >>>>>> not:
> >>>>>> properties:
> >>>>>> @@ -693,6 +760,7 @@ allOf:
> >>>>>> - qcom,pcie-ipq8064v2
> >>>>>> - qcom,pcie-ipq8074
> >>>>>> - qcom,pcie-ipq8074-gen3
> >>>>>> + - qcom,pcie-ipq9574
> >>>>>> - qcom,pcie-qcs404
> >>>>>> then:
> >>>>>> required:
> >>>>>> --
> >>>>>> 2.17.1
> >>>>>>
> >>>>>
> >>>> Thanks,
> >>>> Devi Priya
> >>>
> >>
> >
> Thanks,
> Devi Priya
--
With best wishes
Dmitry
On Tue, Mar 07, 2023 at 03:15:08PM +0530, Devi Priya wrote:
>
>
> On 3/3/2023 11:10 PM, Manivannan Sadhasivam wrote:
> > On Fri, Mar 03, 2023 at 05:16:58PM +0200, Dmitry Baryshkov wrote:
> > > 28 февраля 2023 г. 08:33:58 GMT+02:00, Manivannan Sadhasivam <[email protected]> пишет:
> > > > On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
> > > > >
> > > > >
> > > > > On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
> > > > > > On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
> > > > > > > Document the compatible for IPQ9574
> > > > > > >
> > > > > Hi Mani, Thanks for taking time to review the patch.
> > > > > >
> > > > > > You didn't mention about the "msi-parent" property that is being added
> > > > > > by this patch
> > > > > Sure, will update the commit message in the next spin
> > > > > >
> > > > > > > Signed-off-by: Devi Priya <[email protected]>
> > > > > > > ---
> > > > > > > .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
> > > > > > > 1 file changed, 70 insertions(+), 2 deletions(-)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > > > > > index 872817d6d2bd..dabdf2684e2d 100644
> > > > > > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > > > > > @@ -26,6 +26,7 @@ properties:
> > > > > > > - qcom,pcie-ipq8064-v2
> > > > > > > - qcom,pcie-ipq8074
> > > > > > > - qcom,pcie-ipq8074-gen3
> > > > > > > + - qcom,pcie-ipq9574
> > > > > > > - qcom,pcie-msm8996
> > > > > > > - qcom,pcie-qcs404
> > > > > > > - qcom,pcie-sa8540p
> > > > > > > @@ -44,11 +45,11 @@ properties:
> > > > > > > reg:
> > > > > > > minItems: 4
> > > > > > > - maxItems: 5
> > > > > > > + maxItems: 6
> > > > > > > reg-names:
> > > > > > > minItems: 4
> > > > > > > - maxItems: 5
> > > > > > > + maxItems: 6
> > > > > > > interrupts:
> > > > > > > minItems: 1
> > > > > > > @@ -105,6 +106,8 @@ properties:
> > > > > > > items:
> > > > > > > - const: pciephy
> > > > > > > + msi-parent: true
> > > > > > > +
> > > > > > > power-domains:
> > > > > > > maxItems: 1
> > > > > > > @@ -173,6 +176,27 @@ allOf:
> > > > > > > - const: parf # Qualcomm specific registers
> > > > > > > - const: config # PCIe configuration space
> > > > > > > + - if:
> > > > > > > + properties:
> > > > > > > + compatible:
> > > > > > > + contains:
> > > > > > > + enum:
> > > > > > > + - qcom,pcie-ipq9574
> > > > > > > + then:
> > > > > > > + properties:
> > > > > > > + reg:
> > > > > > > + minItems: 5
> > > > > > > + maxItems: 6
> > > > > > > + reg-names:
> > > > > > > + minItems: 5
> > > > > > > + items:
> > > > > > > + - const: dbi # DesignWare PCIe registers
> > > > > > > + - const: elbi # External local bus interface registers
> > > > > > > + - const: atu # ATU address space
> > > > > > > + - const: parf # Qualcomm specific registers
> > > > > > > + - const: config # PCIe configuration space
> > > > > > > + - const: aggr_noc #PCIe aggr_noc
> > > > > >
> > > > > > Why do you need this region unlike other SoCs? Is the driver making use of it?
> > > > > We have the aggr_noc region in ipq9574 to achieve higher throughput & to
> > > > > handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
> > > > > clocks. My bad, missed it. Will add the driver changes in V2.
> > > >
> > > > Hmm, this is something new. How can you achieve higher throughput with this
> > > > region? Can you explain more on how it is used?
> > >
> > > Based on the name of the region, it looks like it is an interconnect region.
> > >
> >
> > Well, we only have BCM based interconnects so far. That's why I was curious
> > about this region and its purpose.
> For connected PCIe slave devices that are running at frequency lesser
> than the ANOC frequency (342MHz), the rate adapter of ANOC needs to be
> configured
> >
> > > Devi, if this is the case, then you have to handle it through the interconnect driver, rather than poking directly into these registers.
> >
> > If that so, it doesn't need to be added in this series itself. I believe that
> > without aggr_noc region, the PCIe controller can still function properly with
> > reduced performance. But you can add the interconnect support later as a
> > separate series.
> Sure, okay. The ANOC runs at a fixed frequency of 342MHz and the
> interconnect clocks are not scaled. The aggr_noc register is just a magic
> register for configuring it's rate adapter to ensure no wait cycles are
> inserted.
>
If the purpose of the aggr_noc region is to configure the interconnect clock,
then it should be modeled as an interconnect driver.
Thanks,
Mani
> >
> > Thanks,
> > Mani
> >
> > >
> > >
> > > >
> > > > Thanks,
> > > > Mani
> > > >
> > > > > >
> > > > > > Thanks,
> > > > > > Mani
> > > > > >
> > > > > > > +
> > > > > > > - if:
> > > > > > > properties:
> > > > > > > compatible:
> > > > > > > @@ -365,6 +389,39 @@ allOf:
> > > > > > > - const: ahb # AHB Reset
> > > > > > > - const: axi_m_sticky # AXI Master Sticky reset
> > > > > > > + - if:
> > > > > > > + properties:
> > > > > > > + compatible:
> > > > > > > + contains:
> > > > > > > + enum:
> > > > > > > + - qcom,pcie-ipq9574
> > > > > > > + then:
> > > > > > > + properties:
> > > > > > > + clocks:
> > > > > > > + minItems: 6
> > > > > > > + maxItems: 6
> > > > > > > + clock-names:
> > > > > > > + items:
> > > > > > > + - const: ahb # AHB clock
> > > > > > > + - const: aux # Auxiliary clock
> > > > > > > + - const: axi_m # AXI Master clock
> > > > > > > + - const: axi_s # AXI Slave clock
> > > > > > > + - const: axi_bridge # AXI bridge clock
> > > > > > > + - const: rchng
> > > > > > > + resets:
> > > > > > > + minItems: 8
> > > > > > > + maxItems: 8
> > > > > > > + reset-names:
> > > > > > > + items:
> > > > > > > + - const: pipe # PIPE reset
> > > > > > > + - const: sticky # Core Sticky reset
> > > > > > > + - const: axi_s_sticky # AXI Slave Sticky reset
> > > > > > > + - const: axi_s # AXI Slave reset
> > > > > > > + - const: axi_m_sticky # AXI Master Sticky reset
> > > > > > > + - const: axi_m # AXI Master reset
> > > > > > > + - const: aux # AUX Reset
> > > > > > > + - const: ahb # AHB Reset
> > > > > > > +
> > > > > > > - if:
> > > > > > > properties:
> > > > > > > compatible:
> > > > > > > @@ -681,6 +738,16 @@ allOf:
> > > > > > > - interconnects
> > > > > > > - interconnect-names
> > > > > > > + - if:
> > > > > > > + properties:
> > > > > > > + compatible:
> > > > > > > + contains:
> > > > > > > + enum:
> > > > > > > + - qcom,pcie-ipq9574
> > > > > > > + then:
> > > > > > > + required:
> > > > > > > + - msi-parent
> > > > > > > +
> > > > > > > - if:
> > > > > > > not:
> > > > > > > properties:
> > > > > > > @@ -693,6 +760,7 @@ allOf:
> > > > > > > - qcom,pcie-ipq8064v2
> > > > > > > - qcom,pcie-ipq8074
> > > > > > > - qcom,pcie-ipq8074-gen3
> > > > > > > + - qcom,pcie-ipq9574
> > > > > > > - qcom,pcie-qcs404
> > > > > > > then:
> > > > > > > required:
> > > > > > > --
> > > > > > > 2.17.1
> > > > > > >
> > > > > >
> > > > > Thanks,
> > > > > Devi Priya
> > > >
> > >
> >
> Thanks,
> Devi Priya
--
மணிவண்ணன் சதாசிவம்
On 3/7/2023 6:26 PM, Manivannan Sadhasivam wrote:
> On Tue, Mar 07, 2023 at 03:15:08PM +0530, Devi Priya wrote:
>>
>>
>> On 3/3/2023 11:10 PM, Manivannan Sadhasivam wrote:
>>> On Fri, Mar 03, 2023 at 05:16:58PM +0200, Dmitry Baryshkov wrote:
>>>> 28 февраля 2023 г. 08:33:58 GMT+02:00, Manivannan Sadhasivam <[email protected]> пишет:
>>>>> On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
>>>>>>
>>>>>>
>>>>>> On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
>>>>>>> On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
>>>>>>>> Document the compatible for IPQ9574
>>>>>>>>
>>>>>> Hi Mani, Thanks for taking time to review the patch.
>>>>>>>
>>>>>>> You didn't mention about the "msi-parent" property that is being added
>>>>>>> by this patch
>>>>>> Sure, will update the commit message in the next spin
>>>>>>>
>>>>>>>> Signed-off-by: Devi Priya <[email protected]>
>>>>>>>> ---
>>>>>>>> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
>>>>>>>> 1 file changed, 70 insertions(+), 2 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>>>> index 872817d6d2bd..dabdf2684e2d 100644
>>>>>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>>>> @@ -26,6 +26,7 @@ properties:
>>>>>>>> - qcom,pcie-ipq8064-v2
>>>>>>>> - qcom,pcie-ipq8074
>>>>>>>> - qcom,pcie-ipq8074-gen3
>>>>>>>> + - qcom,pcie-ipq9574
>>>>>>>> - qcom,pcie-msm8996
>>>>>>>> - qcom,pcie-qcs404
>>>>>>>> - qcom,pcie-sa8540p
>>>>>>>> @@ -44,11 +45,11 @@ properties:
>>>>>>>> reg:
>>>>>>>> minItems: 4
>>>>>>>> - maxItems: 5
>>>>>>>> + maxItems: 6
>>>>>>>> reg-names:
>>>>>>>> minItems: 4
>>>>>>>> - maxItems: 5
>>>>>>>> + maxItems: 6
>>>>>>>> interrupts:
>>>>>>>> minItems: 1
>>>>>>>> @@ -105,6 +106,8 @@ properties:
>>>>>>>> items:
>>>>>>>> - const: pciephy
>>>>>>>> + msi-parent: true
>>>>>>>> +
>>>>>>>> power-domains:
>>>>>>>> maxItems: 1
>>>>>>>> @@ -173,6 +176,27 @@ allOf:
>>>>>>>> - const: parf # Qualcomm specific registers
>>>>>>>> - const: config # PCIe configuration space
>>>>>>>> + - if:
>>>>>>>> + properties:
>>>>>>>> + compatible:
>>>>>>>> + contains:
>>>>>>>> + enum:
>>>>>>>> + - qcom,pcie-ipq9574
>>>>>>>> + then:
>>>>>>>> + properties:
>>>>>>>> + reg:
>>>>>>>> + minItems: 5
>>>>>>>> + maxItems: 6
>>>>>>>> + reg-names:
>>>>>>>> + minItems: 5
>>>>>>>> + items:
>>>>>>>> + - const: dbi # DesignWare PCIe registers
>>>>>>>> + - const: elbi # External local bus interface registers
>>>>>>>> + - const: atu # ATU address space
>>>>>>>> + - const: parf # Qualcomm specific registers
>>>>>>>> + - const: config # PCIe configuration space
>>>>>>>> + - const: aggr_noc #PCIe aggr_noc
>>>>>>>
>>>>>>> Why do you need this region unlike other SoCs? Is the driver making use of it?
>>>>>> We have the aggr_noc region in ipq9574 to achieve higher throughput & to
>>>>>> handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
>>>>>> clocks. My bad, missed it. Will add the driver changes in V2.
>>>>>
>>>>> Hmm, this is something new. How can you achieve higher throughput with this
>>>>> region? Can you explain more on how it is used?
>>>>
>>>> Based on the name of the region, it looks like it is an interconnect region.
>>>>
>>>
>>> Well, we only have BCM based interconnects so far. That's why I was curious
>>> about this region and its purpose.
>> For connected PCIe slave devices that are running at frequency lesser
>> than the ANOC frequency (342MHz), the rate adapter of ANOC needs to be
>> configured
>>>
>>>> Devi, if this is the case, then you have to handle it through the interconnect driver, rather than poking directly into these registers.
>>>
>>> If that so, it doesn't need to be added in this series itself. I believe that
>>> without aggr_noc region, the PCIe controller can still function properly with
>>> reduced performance. But you can add the interconnect support later as a
>>> separate series.
>> Sure, okay. The ANOC runs at a fixed frequency of 342MHz and the
>> interconnect clocks are not scaled. The aggr_noc register is just a magic
>> register for configuring it's rate adapter to ensure no wait cycles are
>> inserted.
>>
>
> If the purpose of the aggr_noc region is to configure the interconnect clock,
> then it should be modeled as an interconnect driver.
Can we use 'syscon' here, as we are not scaling the interconnect
frequency and this is just a single register write for setting
the rate adapter?
>
> Thanks,
> Mani
>
>>>
>>> Thanks,
>>> Mani
>>>
>>>>
>>>>
>>>>>
>>>>> Thanks,
>>>>> Mani
>>>>>
>>>>>>>
>>>>>>> Thanks,
>>>>>>> Mani
>>>>>>>
>>>>>>>> +
>>>>>>>> - if:
>>>>>>>> properties:
>>>>>>>> compatible:
>>>>>>>> @@ -365,6 +389,39 @@ allOf:
>>>>>>>> - const: ahb # AHB Reset
>>>>>>>> - const: axi_m_sticky # AXI Master Sticky reset
>>>>>>>> + - if:
>>>>>>>> + properties:
>>>>>>>> + compatible:
>>>>>>>> + contains:
>>>>>>>> + enum:
>>>>>>>> + - qcom,pcie-ipq9574
>>>>>>>> + then:
>>>>>>>> + properties:
>>>>>>>> + clocks:
>>>>>>>> + minItems: 6
>>>>>>>> + maxItems: 6
>>>>>>>> + clock-names:
>>>>>>>> + items:
>>>>>>>> + - const: ahb # AHB clock
>>>>>>>> + - const: aux # Auxiliary clock
>>>>>>>> + - const: axi_m # AXI Master clock
>>>>>>>> + - const: axi_s # AXI Slave clock
>>>>>>>> + - const: axi_bridge # AXI bridge clock
>>>>>>>> + - const: rchng
>>>>>>>> + resets:
>>>>>>>> + minItems: 8
>>>>>>>> + maxItems: 8
>>>>>>>> + reset-names:
>>>>>>>> + items:
>>>>>>>> + - const: pipe # PIPE reset
>>>>>>>> + - const: sticky # Core Sticky reset
>>>>>>>> + - const: axi_s_sticky # AXI Slave Sticky reset
>>>>>>>> + - const: axi_s # AXI Slave reset
>>>>>>>> + - const: axi_m_sticky # AXI Master Sticky reset
>>>>>>>> + - const: axi_m # AXI Master reset
>>>>>>>> + - const: aux # AUX Reset
>>>>>>>> + - const: ahb # AHB Reset
>>>>>>>> +
>>>>>>>> - if:
>>>>>>>> properties:
>>>>>>>> compatible:
>>>>>>>> @@ -681,6 +738,16 @@ allOf:
>>>>>>>> - interconnects
>>>>>>>> - interconnect-names
>>>>>>>> + - if:
>>>>>>>> + properties:
>>>>>>>> + compatible:
>>>>>>>> + contains:
>>>>>>>> + enum:
>>>>>>>> + - qcom,pcie-ipq9574
>>>>>>>> + then:
>>>>>>>> + required:
>>>>>>>> + - msi-parent
>>>>>>>> +
>>>>>>>> - if:
>>>>>>>> not:
>>>>>>>> properties:
>>>>>>>> @@ -693,6 +760,7 @@ allOf:
>>>>>>>> - qcom,pcie-ipq8064v2
>>>>>>>> - qcom,pcie-ipq8074
>>>>>>>> - qcom,pcie-ipq8074-gen3
>>>>>>>> + - qcom,pcie-ipq9574
>>>>>>>> - qcom,pcie-qcs404
>>>>>>>> then:
>>>>>>>> required:
>>>>>>>> --
>>>>>>>> 2.17.1
>>>>>>>>
>>>>>>>
>>>>>> Thanks,
>>>>>> Devi Priya
>>>>>
>>>>
>>>
>> Thanks,
>> Devi Priya
>
On 2/24/2023 2:29 PM, Manivannan Sadhasivam wrote:
> On Tue, Feb 14, 2023 at 10:11:35PM +0530, Devi Priya wrote:
>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>> found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>
>
> Please split the board devicetree changes into a separate patch.
Sure, okay
>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 28 ++
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 477 ++++++++++++++++++-
>> 2 files changed, 499 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> index 2c8430197ec0..21b53f34ce84 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -8,6 +8,7 @@
>>
>> /dts-v1/;
>>
>> +#include <dt-bindings/gpio/gpio.h>
>> #include "ipq9574.dtsi"
>>
>> / {
>> @@ -29,6 +30,33 @@
>> status = "okay";
>> };
>>
>> +&pcie1_phy {
>> + status = "okay";
>
> No PHY power supply needed? Same comment for rest of the PHY nodes.
The PHY power supplies (VDDA_0P9 and VDDA_1P8) would be turned 'on'
by default and so no supply is added here
>
>> +};
>> +
>> +&pcie1_x1 {
>
> No need to add a suffix to node label indicating the lane config.
Okay
>
>> + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
>
> What about "wake" pin? Don't you need pinctrl definitions for these GPIOs?
> Same comment for rest of the PCIe nodes.
In IPQ9574, Wake pin isn't required as the slave devices are not
hot-pluggable & they get enumerated during the bootup. Will add the
pinctrl definition for the Perst gpio in V2
>
>> + status = "okay";
>> +};
>> +
>> +&pcie2_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie2_x2 {
>> + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> +&pcie3_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie3_x2 {
>> + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> pinctrl-0 = <&sdc_default_state>;
>> pinctrl-names = "default";
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 062f80798ebb..a32dbdeb5bed 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -6,8 +6,8 @@
>> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> */
>>
>> -#include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>>
>> / {
>> @@ -22,11 +22,41 @@
>> #clock-cells = <0>;
>> };
>>
>> + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <250000000>;
>> + #clock-cells = <0>;
>> + };
>
> Why PIPE clocks are modeled as fixed clocks unlike other SoCs?
Sure, will add the clocks to corresponding PHY node and use the phandle
similar to other targets
>
>> +
>> sleep_clk: sleep-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> };
>>
>> + usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <125000000>;
>> + #clock-cells = <0>;
>> + };
>
> Spurious?
Will drop it
>
>> +
>> xo_board_clk: xo-board-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> @@ -121,6 +151,155 @@
>> #size-cells = <1>;
>> ranges = <0 0 0 0xffffffff>;
>>
>> + pcie0_phy: phy@84000 {
>> + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> + reg = <0x00084000 0x1bc>; /* Serdes PLL */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + clocks = <&gcc GCC_PCIE0_AUX_CLK>,
>> + <&gcc GCC_PCIE0_AHB_CLK>,
>> + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
>> + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>;
>> + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
>
> Care to explain what these anoc_lane and snoc_lane clocks are?
snoc & anoc lane clocks are used in the SNOC/ANOC Network Interface Unit
(NIU) which connects to the corresponding PCIE master/slave interface
>
>> +
>> + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
>> + assigned-clock-rates = <20000000>;
>> +
>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> + reset-names = "phy", "common";
>> +
>> + status = "disabled";
>> +
>> + pcie0_lane: phy@84200 {
>> + reg = <0x00084200 0x16c>, /* Serdes Tx */
>> + <0x00084400 0x200>, /* Serdes Rx */
>> + <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */
>> + <0x00084c00 0xf4>; /* pcs_misc */
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_pcie0_pipe_clk_src";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>
> [...]
>
>> + pcie1_x1: pci@10000000 {
>> + compatible = "qcom,pcie-ipq9574";
>> + reg = <0x10000000 0xf1d>,
>> + <0x10000F20 0xa8>,
>> + <0x10001000 0x1000>,
>> + <0x000F8000 0x4000>,
>> + <0x10100000 0x1000>,
>> + <0x00618108 0x4>;
>> + reg-names = "dbi", "elbi", "atu", "parf", "config", "aggr_noc";
>
> As I asked in the binding patch, why "aggr_noc" region is required?
The ANOC runs at a fixed frequency of 342MHz.
For the connected PCIe slave devices that run at lesser frequency,
the aggr_noc's rate adapter register is updated to configure
the packet transmission rate to ensure no wait cycles are inserted.
Can we use the 'syscon' property here to set the rate adapter?
>
>> + device_type = "pci";
>> + linux,pci-domain = <2>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <1>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + ranges = <0x81000000 0 0x10200000 0x10200000
>> + 0 0x00100000 /* downstream I/O */
>> + 0x82000000 0 0x10300000 0x10300000
>> + 0 0x07d00000>; /* non-prefetchable memory */
>
> Don't split the ranges and encode them in a single line.
Okay
>
> Also, the I'm not sure why you have set the relocatable flag (n) for both
> ranges i.e., in 0x81000000 and 0x82000000.
Will check and add comment in V2
>
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 35
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>> + <0 0 0 2 &intc 0 49
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_b */
>> + <0 0 0 3 &intc 0 84
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_c */
>> + <0 0 0 4 &intc 0 85
>> + IRQ_TYPE_LEVEL_HIGH>; /* int_d */
>> +
>
> Again, wrap the interrupts in a single line.
Sure, okay
>
>> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "global_irq";
>> +
>
> Linux doesn't support global_irq yet. But since devicetree is supposed to
> describe the hardware, you can keep it.
Okay
>
> Above comment applies to rest of the PCIe nodes.
>
>> + /* clocks and clock-names are used to enable the clock in CBCR */
>> + clocks = <&gcc GCC_PCIE1_AHB_CLK>,
>> + <&gcc GCC_PCIE1_AUX_CLK>,
>> + <&gcc GCC_PCIE1_AXI_M_CLK>,
>> + <&gcc GCC_PCIE1_AXI_S_CLK>,
>> + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
>> + <&gcc GCC_PCIE1_RCHNG_CLK>;
>> + clock-names = "ahb",
>> + "aux",
>> + "axi_m",
>> + "axi_s",
>> + "axi_bridge",
>> + "rchng";
>> +
>> + resets = <&gcc GCC_PCIE1_PIPE_ARES>,
>> + <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
>> + <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
>> + <&gcc GCC_PCIE1_AXI_S_ARES>,
>> + <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
>> + <&gcc GCC_PCIE1_AXI_M_ARES>,
>> + <&gcc GCC_PCIE1_AUX_ARES>,
>> + <&gcc GCC_PCIE1_AHB_ARES>;
>> + reset-names = "pipe",
>> + "sticky",
>> + "axi_s_sticky",
>> + "axi_s",
>> + "axi_m_sticky",
>> + "axi_m",
>> + "aux",
>> + "ahb";
>> +
>> + phys = <&pcie1_lane>;
>> + phy-names = "pciephy";
>> + msi-parent = <&v2m0>;
>> + status = "disabled";
>> + };
>> +
>
> [...]
>
>> + pcie2_x2: pci@20000000 {
>> + compatible = "qcom,pcie-ipq9574";
>> + reg = <0x20000000 0xf1d>,
>> + <0x20000F20 0xa8>,
>> + <0x20001000 0x1000>,
>> + <0x00088000 0x4000>,
>> + <0x20100000 0x1000>;
>> + reg-names = "dbi", "elbi", "atu", "parf", "config";
>> + device_type = "pci";
>> + linux,pci-domain = <3>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes =<2>;
>
> Space after =
Sure, okay
>
> Thanks,
> Mani
>
On Tue, 7 Mar 2023 at 16:40, Devi Priya <[email protected]> wrote:
>
>
>
> On 3/7/2023 6:26 PM, Manivannan Sadhasivam wrote:
> > On Tue, Mar 07, 2023 at 03:15:08PM +0530, Devi Priya wrote:
> >>
> >>
> >> On 3/3/2023 11:10 PM, Manivannan Sadhasivam wrote:
> >>> On Fri, Mar 03, 2023 at 05:16:58PM +0200, Dmitry Baryshkov wrote:
> >>>> 28 февраля 2023 г. 08:33:58 GMT+02:00, Manivannan Sadhasivam <[email protected]> пишет:
> >>>>> On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
> >>>>>>
> >>>>>>
> >>>>>> On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
> >>>>>>> On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
> >>>>>>>> Document the compatible for IPQ9574
> >>>>>>>>
> >>>>>> Hi Mani, Thanks for taking time to review the patch.
> >>>>>>>
> >>>>>>> You didn't mention about the "msi-parent" property that is being added
> >>>>>>> by this patch
> >>>>>> Sure, will update the commit message in the next spin
> >>>>>>>
> >>>>>>>> Signed-off-by: Devi Priya <[email protected]>
> >>>>>>>> ---
> >>>>>>>> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
> >>>>>>>> 1 file changed, 70 insertions(+), 2 deletions(-)
> >>>>>>>>
> >>>>>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >>>>>>>> index 872817d6d2bd..dabdf2684e2d 100644
> >>>>>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >>>>>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> >>>>>>>> @@ -26,6 +26,7 @@ properties:
> >>>>>>>> - qcom,pcie-ipq8064-v2
> >>>>>>>> - qcom,pcie-ipq8074
> >>>>>>>> - qcom,pcie-ipq8074-gen3
> >>>>>>>> + - qcom,pcie-ipq9574
> >>>>>>>> - qcom,pcie-msm8996
> >>>>>>>> - qcom,pcie-qcs404
> >>>>>>>> - qcom,pcie-sa8540p
> >>>>>>>> @@ -44,11 +45,11 @@ properties:
> >>>>>>>> reg:
> >>>>>>>> minItems: 4
> >>>>>>>> - maxItems: 5
> >>>>>>>> + maxItems: 6
> >>>>>>>> reg-names:
> >>>>>>>> minItems: 4
> >>>>>>>> - maxItems: 5
> >>>>>>>> + maxItems: 6
> >>>>>>>> interrupts:
> >>>>>>>> minItems: 1
> >>>>>>>> @@ -105,6 +106,8 @@ properties:
> >>>>>>>> items:
> >>>>>>>> - const: pciephy
> >>>>>>>> + msi-parent: true
> >>>>>>>> +
> >>>>>>>> power-domains:
> >>>>>>>> maxItems: 1
> >>>>>>>> @@ -173,6 +176,27 @@ allOf:
> >>>>>>>> - const: parf # Qualcomm specific registers
> >>>>>>>> - const: config # PCIe configuration space
> >>>>>>>> + - if:
> >>>>>>>> + properties:
> >>>>>>>> + compatible:
> >>>>>>>> + contains:
> >>>>>>>> + enum:
> >>>>>>>> + - qcom,pcie-ipq9574
> >>>>>>>> + then:
> >>>>>>>> + properties:
> >>>>>>>> + reg:
> >>>>>>>> + minItems: 5
> >>>>>>>> + maxItems: 6
> >>>>>>>> + reg-names:
> >>>>>>>> + minItems: 5
> >>>>>>>> + items:
> >>>>>>>> + - const: dbi # DesignWare PCIe registers
> >>>>>>>> + - const: elbi # External local bus interface registers
> >>>>>>>> + - const: atu # ATU address space
> >>>>>>>> + - const: parf # Qualcomm specific registers
> >>>>>>>> + - const: config # PCIe configuration space
> >>>>>>>> + - const: aggr_noc #PCIe aggr_noc
> >>>>>>>
> >>>>>>> Why do you need this region unlike other SoCs? Is the driver making use of it?
> >>>>>> We have the aggr_noc region in ipq9574 to achieve higher throughput & to
> >>>>>> handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
> >>>>>> clocks. My bad, missed it. Will add the driver changes in V2.
> >>>>>
> >>>>> Hmm, this is something new. How can you achieve higher throughput with this
> >>>>> region? Can you explain more on how it is used?
> >>>>
> >>>> Based on the name of the region, it looks like it is an interconnect region.
> >>>>
> >>>
> >>> Well, we only have BCM based interconnects so far. That's why I was curious
> >>> about this region and its purpose.
> >> For connected PCIe slave devices that are running at frequency lesser
> >> than the ANOC frequency (342MHz), the rate adapter of ANOC needs to be
> >> configured
> >>>
> >>>> Devi, if this is the case, then you have to handle it through the interconnect driver, rather than poking directly into these registers.
> >>>
> >>> If that so, it doesn't need to be added in this series itself. I believe that
> >>> without aggr_noc region, the PCIe controller can still function properly with
> >>> reduced performance. But you can add the interconnect support later as a
> >>> separate series.
> >> Sure, okay. The ANOC runs at a fixed frequency of 342MHz and the
> >> interconnect clocks are not scaled. The aggr_noc register is just a magic
> >> register for configuring it's rate adapter to ensure no wait cycles are
> >> inserted.
> >>
> >
> > If the purpose of the aggr_noc region is to configure the interconnect clock,
> > then it should be modeled as an interconnect driver.
> Can we use 'syscon' here, as we are not scaling the interconnect
> frequency and this is just a single register write for setting
> the rate adapter?
It should be done outside of the PCIe driver.
It is not "just a single register". It is also setting the anoc/snoc
clocks for USB. And maybe something else, which we haven't seen at
this moment. You are still setting up the NoC, even if the icc
frequency is not scaled.
--
With best wishes
Dmitry
On 3/7/2023 8:26 PM, Dmitry Baryshkov wrote:
> On Tue, 7 Mar 2023 at 16:40, Devi Priya <[email protected]> wrote:
>>
>>
>>
>> On 3/7/2023 6:26 PM, Manivannan Sadhasivam wrote:
>>> On Tue, Mar 07, 2023 at 03:15:08PM +0530, Devi Priya wrote:
>>>>
>>>>
>>>> On 3/3/2023 11:10 PM, Manivannan Sadhasivam wrote:
>>>>> On Fri, Mar 03, 2023 at 05:16:58PM +0200, Dmitry Baryshkov wrote:
>>>>>> 28 февраля 2023 г. 08:33:58 GMT+02:00, Manivannan Sadhasivam <[email protected]> пишет:
>>>>>>> On Tue, Feb 28, 2023 at 10:56:53AM +0530, Devi Priya wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 2/24/2023 1:53 PM, Manivannan Sadhasivam wrote:
>>>>>>>>> On Tue, Feb 14, 2023 at 10:11:29PM +0530, Devi Priya wrote:
>>>>>>>>>> Document the compatible for IPQ9574
>>>>>>>>>>
>>>>>>>> Hi Mani, Thanks for taking time to review the patch.
>>>>>>>>>
>>>>>>>>> You didn't mention about the "msi-parent" property that is being added
>>>>>>>>> by this patch
>>>>>>>> Sure, will update the commit message in the next spin
>>>>>>>>>
>>>>>>>>>> Signed-off-by: Devi Priya <[email protected]>
>>>>>>>>>> ---
>>>>>>>>>> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
>>>>>>>>>> 1 file changed, 70 insertions(+), 2 deletions(-)
>>>>>>>>>>
>>>>>>>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>>>>>> index 872817d6d2bd..dabdf2684e2d 100644
>>>>>>>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>>>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>>>>>>> @@ -26,6 +26,7 @@ properties:
>>>>>>>>>> - qcom,pcie-ipq8064-v2
>>>>>>>>>> - qcom,pcie-ipq8074
>>>>>>>>>> - qcom,pcie-ipq8074-gen3
>>>>>>>>>> + - qcom,pcie-ipq9574
>>>>>>>>>> - qcom,pcie-msm8996
>>>>>>>>>> - qcom,pcie-qcs404
>>>>>>>>>> - qcom,pcie-sa8540p
>>>>>>>>>> @@ -44,11 +45,11 @@ properties:
>>>>>>>>>> reg:
>>>>>>>>>> minItems: 4
>>>>>>>>>> - maxItems: 5
>>>>>>>>>> + maxItems: 6
>>>>>>>>>> reg-names:
>>>>>>>>>> minItems: 4
>>>>>>>>>> - maxItems: 5
>>>>>>>>>> + maxItems: 6
>>>>>>>>>> interrupts:
>>>>>>>>>> minItems: 1
>>>>>>>>>> @@ -105,6 +106,8 @@ properties:
>>>>>>>>>> items:
>>>>>>>>>> - const: pciephy
>>>>>>>>>> + msi-parent: true
>>>>>>>>>> +
>>>>>>>>>> power-domains:
>>>>>>>>>> maxItems: 1
>>>>>>>>>> @@ -173,6 +176,27 @@ allOf:
>>>>>>>>>> - const: parf # Qualcomm specific registers
>>>>>>>>>> - const: config # PCIe configuration space
>>>>>>>>>> + - if:
>>>>>>>>>> + properties:
>>>>>>>>>> + compatible:
>>>>>>>>>> + contains:
>>>>>>>>>> + enum:
>>>>>>>>>> + - qcom,pcie-ipq9574
>>>>>>>>>> + then:
>>>>>>>>>> + properties:
>>>>>>>>>> + reg:
>>>>>>>>>> + minItems: 5
>>>>>>>>>> + maxItems: 6
>>>>>>>>>> + reg-names:
>>>>>>>>>> + minItems: 5
>>>>>>>>>> + items:
>>>>>>>>>> + - const: dbi # DesignWare PCIe registers
>>>>>>>>>> + - const: elbi # External local bus interface registers
>>>>>>>>>> + - const: atu # ATU address space
>>>>>>>>>> + - const: parf # Qualcomm specific registers
>>>>>>>>>> + - const: config # PCIe configuration space
>>>>>>>>>> + - const: aggr_noc #PCIe aggr_noc
>>>>>>>>>
>>>>>>>>> Why do you need this region unlike other SoCs? Is the driver making use of it?
>>>>>>>> We have the aggr_noc region in ipq9574 to achieve higher throughput & to
>>>>>>>> handle multiple PCIe instances. The driver uses it to rate adapt 1-lane PCIe
>>>>>>>> clocks. My bad, missed it. Will add the driver changes in V2.
>>>>>>>
>>>>>>> Hmm, this is something new. How can you achieve higher throughput with this
>>>>>>> region? Can you explain more on how it is used?
>>>>>>
>>>>>> Based on the name of the region, it looks like it is an interconnect region.
>>>>>>
>>>>>
>>>>> Well, we only have BCM based interconnects so far. That's why I was curious
>>>>> about this region and its purpose.
>>>> For connected PCIe slave devices that are running at frequency lesser
>>>> than the ANOC frequency (342MHz), the rate adapter of ANOC needs to be
>>>> configured
>>>>>
>>>>>> Devi, if this is the case, then you have to handle it through the interconnect driver, rather than poking directly into these registers.
>>>>>
>>>>> If that so, it doesn't need to be added in this series itself. I believe that
>>>>> without aggr_noc region, the PCIe controller can still function properly with
>>>>> reduced performance. But you can add the interconnect support later as a
>>>>> separate series.
>>>> Sure, okay. The ANOC runs at a fixed frequency of 342MHz and the
>>>> interconnect clocks are not scaled. The aggr_noc register is just a magic
>>>> register for configuring it's rate adapter to ensure no wait cycles are
>>>> inserted.
>>>>
>>>
>>> If the purpose of the aggr_noc region is to configure the interconnect clock,
>>> then it should be modeled as an interconnect driver.
>> Can we use 'syscon' here, as we are not scaling the interconnect
>> frequency and this is just a single register write for setting
>> the rate adapter?
>
> It should be done outside of the PCIe driver.
> It is not "just a single register". It is also setting the anoc/snoc
> clocks for USB. And maybe something else, which we haven't seen at
> this moment. You are still setting up the NoC, even if the icc
> frequency is not scaled.
>
Sure Dmitry, Got it
Regards,
Devi Priya