There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
transfer to be send twice in DMA mode. Please get more information from:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
new sdma ram script which works in XCH mode as PIO inside sdma instead
of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
exist on all legacy i.mx6/7 soc family before i.mx6ul.
NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
or not.
The first two reverted patches should be the same issue, though, it
seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
have the chance to test this patch set if could fix their issues.
Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
on i.mx8mm because the event id is zero.
PS:
Please get sdma firmware from below linux-firmware and copy it to your
local rootfs /lib/firmware/imx/sdma.
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/imx/sdma
v2:
1.Add commit log for reverted patches.
2.Add comment for 'ecspi_fixed' in sdma driver.
3.Add 'fsl,imx6sll-ecspi' compatible instead of 'fsl,imx6ul-ecspi'
rather than remove.
v3:
1.Confirm with design team make sure ERR009165 fixed on i.mx6ul/i.mx6ull
/i.mx6sll, not fixed on i.mx8m/8mm and other i.mx6/7 legacy chips.
Correct dts related dts patch in v2.
2.Clean eratta information in binding doc and new 'tx_glitch_fixed' flag
in spi-imx driver to state ERR009165 fixed or not.
3.Enlarge burst size to fifo size for tx since tx_wml set to 0 in the
errata workaroud, thus improve performance as possible.
v4:
1.Add Ack tag from Mark and Vinod
2.Remove checking 'event_id1' zero as 'event_id0'.
v5:
1.Add the last patch for compatible with the current uart driver which
using rom script, so both uart ram script and rom script supported
in latest firmware, by default uart rom script used. UART driver
will be broken without this patch.
v6:
1.Resend after rebase the latest next branch.
2.Remove below No.13~No.15 patches of v5 because they were mergered.
ARM: dts: imx6ul: add dma support on ecspi
ARM: dts: imx6sll: correct sdma compatible
arm64: defconfig: Enable SDMA on i.mx8mq/8mm
3.Revert "dmaengine: imx-sdma: fix context cache" since
'context_loaded' removed.
v7:
1.Put the last patch 13/13 'Revert "dmaengine: imx-sdma: fix context
cache"' to the ahead of 03/13 'Revert "dmaengine: imx-sdma: refine
to load context only once" so that no building waring during comes out
during bisect.
2.Address Sascha's comments, including eliminating any i.mx6sx in this
series, adding new 'is_imx6ul_ecspi()' instead imx in imx51 and taking
care SMC bit for PIO.
3.Add back missing 'Reviewed-by' tag on 08/15(v5):09/13(v7)
'spi: imx: add new i.mx6ul compatible name in binding doc'
v8:
1.remove 0003-Revert-dmaengine-imx-sdma-fix-context-cache.patch and merge
it into 04/13 of v7
2.add 0005-spi-imx-fallback-to-PIO-if-dma-setup-failure.patch for no any
ecspi function broken even if sdma firmware not updated.
3.merge 'tx.dst_maxburst' changes in the two continous patches into one
patch to avoid confusion.
4.fix typo 'duplicated'.
v9:
1. add "spi: imx: add dma_sync_sg_for_device after fallback from dma"
to fix the potential issue brought by commit bcd8e7761ec9("spi: imx:
fallback to PIO if dma setup failure") which is the only one patch
of v8 merged. Thanks Matthias for reporting:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
2. remove 05/13 of v8 "spi: imx:fallback to PIO if dma setup failure"
since it's been merged.
v10:
1. remove 01/13 "spi: imx: add dma_sync_sg_for_device after fallback from dma"
since there is another independent patch merged:
-- commit 809b1b04df898 ("spi: introduce fallback to pio")
2. add "dmaengine: dma: imx-sdma: add fw_loaded and is_ram_script" which
is used to fix the potential dma_alloc_coherent() failure while this
patchset applied but sdma firmware may not be ready for long time.
3. burst size change back from fifo size to normal wml to align with nxp
internal tree which has been test for years. Overnight with loopback
test with spidev failed with fifo size, but pass with wml(half of fifo
size).Seems the whole fifo size fed may cause rxfifo overflow during
tx shift out while rx shift in.
"spi: imx: remove ERR009165 workaround on i.mx6ul"
4. remove 12/13 'dmaengine: imx-sdma: fix ecspi1 rx dma not work on i.mx8mm'
since below two similar patches merged:
-- commit 25962e1a7f1d ("dmaengine: imx-sdma: Fix the event id check to
include RX event for UART6")
-- commit 2f57b8d57673 ("dmaengine: imx-sdma: Fix: Remove 'always true'
comparison")
v11:
1. change dev_err() to dev_warn_once() in case sdma firmware not loaded to
eliminate meaningless duplicate log print.
v12:
1. take care uart_2_mcu_addr/uartsh_2_mcu_addr since such rom scripts are
now located in the bottom part of sdma_script_start_addrs which are beyond
the SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1. Reported by Frieder as below:
https://www.mail-archive.com/[email protected]/msg2263544.html
v13:
1. rebase with latest linux-next.
2. remove 09/12 'spi: imx: add new i.mx6ul compatible name in binding doc'
since it's been converted to yaml already.
3. add 'Fixes', 'Cc: [email protected]' and 'Test-by' tags for 03,04
since they are confirmed fix by Richard Leitner:
https://lkml.org/lkml/2020/8/17/39
https://www.spinics.net/lists/dmaengine/msg23489.html
4. fix potential descriptor free unexpected on the next transfer before
the last channel terminated:
https://www.spinics.net/lists/dmaengine/msg23400.html
v14:
1. rebase with latest linux-next.
Robin Gong (12):
Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core"
Revert "ARM: dts: imx6: Use correct SDMA script for SPI cores"
Revert "dmaengine: imx-sdma: refine to load context only once"
dmaengine: imx-sdma: remove duplicated sdma_load_context
dmaengine: dma: imx-sdma: add fw_loaded and is_ram_script
dmaengine: imx-sdma: add mcu_2_ecspi script
spi: imx: fix ERR009165
spi: imx: remove ERR009165 workaround on i.mx6ul
dmaengine: imx-sdma: remove ERR009165 on i.mx6ul
dma: imx-sdma: add i.mx6ul compatible name
dmaengine: imx-sdma: add uart rom script
dmaengine: imx-sdma: add terminated list for freed descriptor in
worker
.../devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
arch/arm/boot/dts/imx6q.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl.dtsi | 8 +-
drivers/dma/imx-sdma.c | 90 ++++++++++++++++------
drivers/spi/spi-imx.c | 49 ++++++++++--
include/linux/platform_data/dma-imx-sdma.h | 8 +-
6 files changed, 122 insertions(+), 36 deletions(-)
--
2.7.4
Add mcu_2_ecspi script to fix ecspi errata ERR009165.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 78dcfe2..86bd383 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -892,6 +892,10 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
break;
case IMX_DMATYPE_CSPI:
+ per_2_emi = sdma->script_addrs->app_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
+ sdmac->is_ram_script = true;
+ break;
case IMX_DMATYPE_EXT:
case IMX_DMATYPE_SSI:
case IMX_DMATYPE_SAI:
--
2.7.4
ERR009165 fixed on i.mx6ul/6ull/6sll. All other i.mx6/7 and
i.mx8m/8mm still need this errata. Please refer to nxp official
errata document from https://www.nxp.com/ .
For removing workaround on those chips. Add new i.mx6ul type.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Mark Brown <[email protected]>
---
drivers/spi/spi-imx.c | 47 +++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index cf235b9..d18ee25 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -59,6 +59,7 @@ enum spi_imx_devtype {
IMX35_CSPI, /* CSPI on all i.mx except above */
IMX51_ECSPI, /* ECSPI on i.mx51 */
IMX53_ECSPI, /* ECSPI on i.mx53 and later */
+ IMX6UL_ECSPI, /* ERR009165 fix from i.mx6ul */
};
struct spi_imx_data;
@@ -78,6 +79,11 @@ struct spi_imx_devtype_data {
bool has_slavemode;
unsigned int fifo_size;
bool dynamic_burst;
+ /*
+ * ERR009165 fixed or not:
+ * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+ */
+ bool tx_glitch_fixed;
enum spi_imx_devtype devtype;
};
@@ -134,6 +140,11 @@ static inline int is_imx51_ecspi(struct spi_imx_data *d)
return d->devtype_data->devtype == IMX51_ECSPI;
}
+static inline int is_imx6ul_ecspi(struct spi_imx_data *d)
+{
+ return d->devtype_data->devtype == IMX6UL_ECSPI;
+}
+
static inline int is_imx53_ecspi(struct spi_imx_data *d)
{
return d->devtype_data->devtype == IMX53_ECSPI;
@@ -593,8 +604,14 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
- /* ERR009165: work in XHC mode as PIO */
- ctrl &= ~MX51_ECSPI_CTRL_SMC;
+ /*
+ * ERR009165: work in XHC mode instead of SMC as PIO on the chips
+ * before i.mx6ul.
+ */
+ if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
+ ctrl |= MX51_ECSPI_CTRL_SMC;
+ else
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -620,12 +637,16 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
static void mx51_setup_wml(struct spi_imx_data *spi_imx)
{
+ u32 tx_wml = 0;
+
+ if (spi_imx->devtype_data->tx_glitch_fixed)
+ tx_wml = spi_imx->wml;
/*
* Configure the DMA register: setup the watermark
* and enable DMA request.
*/
writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
- MX51_ECSPI_DMA_TX_WML(0) |
+ MX51_ECSPI_DMA_TX_WML(tx_wml) |
MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
@@ -1019,6 +1040,23 @@ static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
.devtype = IMX53_ECSPI,
};
+static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
+ .intctrl = mx51_ecspi_intctrl,
+ .prepare_message = mx51_ecspi_prepare_message,
+ .prepare_transfer = mx51_ecspi_prepare_transfer,
+ .trigger = mx51_ecspi_trigger,
+ .rx_available = mx51_ecspi_rx_available,
+ .reset = mx51_ecspi_reset,
+ .setup_wml = mx51_setup_wml,
+ .fifo_size = 64,
+ .has_dmamode = true,
+ .dynamic_burst = true,
+ .has_slavemode = true,
+ .tx_glitch_fixed = true,
+ .disable = mx51_ecspi_disable,
+ .devtype = IMX6UL_ECSPI,
+};
+
static const struct of_device_id spi_imx_dt_ids[] = {
{ .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
{ .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
@@ -1027,6 +1065,7 @@ static const struct of_device_id spi_imx_dt_ids[] = {
{ .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
{ .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
{ .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
+ { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
@@ -1604,7 +1643,7 @@ static int spi_imx_probe(struct platform_device *pdev)
spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
| SPI_NO_CS;
if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
- is_imx53_ecspi(spi_imx))
+ is_imx53_ecspi(spi_imx) || is_imx6ul_ecspi(spi_imx))
spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
spi_imx->spi_drctl = spi_drctl;
--
2.7.4
ECSPI issue fixed from i.mx6ul at hardware level, no need
ERR009165 anymore on those chips such as i.mx8mq.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 86bd383..af85116 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -422,6 +422,13 @@ struct sdma_driver_data {
int num_events;
struct sdma_script_start_addrs *script_addrs;
bool check_ratio;
+ /*
+ * ecspi ERR009165 fixed should be done in sdma script
+ * and it has been fixed in soc from i.mx6ul.
+ * please get more information from the below link:
+ * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+ */
+ bool ecspi_fixed;
};
struct sdma_engine {
@@ -542,6 +549,13 @@ static struct sdma_driver_data sdma_imx6q = {
.script_addrs = &sdma_script_imx6q,
};
+static struct sdma_driver_data sdma_imx6ul = {
+ .chnenbl0 = SDMA_CHNENBL0_IMX35,
+ .num_events = 48,
+ .script_addrs = &sdma_script_imx6q,
+ .ecspi_fixed = true,
+};
+
static struct sdma_script_start_addrs sdma_script_imx7d = {
.ap_2_ap_addr = 644,
.uart_2_mcu_addr = 819,
@@ -575,6 +589,7 @@ static const struct of_device_id sdma_dt_ids[] = {
{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
{ .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
+ { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
{ .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
{ /* sentinel */ }
};
@@ -1144,8 +1159,17 @@ static int sdma_config_channel(struct dma_chan *chan)
if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac);
- } else
+ } else {
+ /*
+ * ERR009165 fixed from i.mx6ul, no errata need,
+ * set bit31 to let sdma script skip the errata.
+ */
+ if (sdmac->peripheral_type == IMX_DMATYPE_CSPI &&
+ sdmac->direction == DMA_MEM_TO_DEV &&
+ sdmac->sdma->drvdata->ecspi_fixed)
+ __set_bit(31, &sdmac->watermark_level);
__set_bit(sdmac->event_id0, sdmac->event_mask);
+ }
/* Address */
sdmac->shp_addr = sdmac->per_address;
--
2.7.4
Add i.mx6ul compatible name in binding doc.
Signed-off-by: Robin Gong <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index c9e9740..12c316f 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -9,6 +9,7 @@ Required properties:
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
"fsl,imx7d-sdma"
+ "fsl,imx6ul-sdma"
"fsl,imx8mq-sdma"
"fsl,imx8mm-sdma"
"fsl,imx8mn-sdma"
--
2.7.4
Change to XCH mode even in dma mode, please refer to the below
errata:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Mark Brown <[email protected]>
---
drivers/spi/spi-imx.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 4fe767a..cf235b9 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -593,8 +593,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
- if (spi_imx->usedma)
- ctrl |= MX51_ECSPI_CTRL_SMC;
+ /* ERR009165: work in XHC mode as PIO */
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -625,7 +625,7 @@ static void mx51_setup_wml(struct spi_imx_data *spi_imx)
* and enable DMA request.
*/
writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
- MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
+ MX51_ECSPI_DMA_TX_WML(0) |
MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
@@ -1234,10 +1234,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
{
int ret;
- /* use pio mode for i.mx6dl chip TKT238285 */
- if (of_machine_is_compatible("fsl,imx6dl"))
- return 0;
-
spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
/* Prepare for TX DMA: */
--
2.7.4
There are two ways for SDMA accessing SPBA devices: one is SDMA->AIPS
->SPBA(masterA port), another is SDMA->SPBA(masterC port). Please refer
to the 'Figure 58-1. i.MX 6Dual/6Quad SPBA connectivity' of i.mx6DQ
Reference Manual. SDMA provide the corresponding app_2_mcu/mcu_2_app and
shp_2_mcu/mcu_2_shp script for such two options. So both AIPS and SPBA
scripts should keep the same behaviour, the issue only caught in AIPS
script sounds not solide.
The issue is more likely as the ecspi errata
ERR009165(http://www.nxp.com/docs/en/errata/IMX6DQCE.pdf):
eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to
be sent twice
So revert commit 'dd4b487b32a3' firstly.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Sascha Hauer <[email protected]>
---
arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 82e01ce..89c342f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -334,7 +334,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
<&clks IMX6QDL_CLK_ECSPI1>;
clock-names = "ipg", "per";
- dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
+ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -348,7 +348,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI2>,
<&clks IMX6QDL_CLK_ECSPI2>;
clock-names = "ipg", "per";
- dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
+ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -362,7 +362,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI3>,
<&clks IMX6QDL_CLK_ECSPI3>;
clock-names = "ipg", "per";
- dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
+ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -376,7 +376,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI4>,
<&clks IMX6QDL_CLK_ECSPI4>;
clock-names = "ipg", "per";
- dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
+ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
--
2.7.4
Add 'fw_loaded' and 'is_ram_script' to check if the script used by channel
is ram script and it's loaded or not, so that could prevent meaningless
following malloc dma descriptor and bd allocate in sdma_transfer_init(),
otherwise memory may be consumed out potentially without free in case
that spi fallback into pio while dma transfer failed by sdma firmware not
ready(next ERR009165 patch depends on sdma RAM scripts/firmware).
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1c636d2..78dcfe2 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -381,6 +381,7 @@ struct sdma_channel {
enum dma_status status;
struct imx_dma_data data;
struct work_struct terminate_worker;
+ bool is_ram_script;
};
#define IMX_DMA_SG_LOOP BIT(0)
@@ -444,6 +445,7 @@ struct sdma_engine {
struct sdma_buffer_descriptor *bd0;
/* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
bool clk_ratio;
+ bool fw_loaded;
};
static int sdma_config_write(struct dma_chan *chan,
@@ -899,6 +901,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
case IMX_DMATYPE_SSI_DUAL:
per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
+ sdmac->is_ram_script = true;
break;
case IMX_DMATYPE_SSI_SP:
case IMX_DMATYPE_MMC:
@@ -913,6 +916,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
per_2_per = sdma->script_addrs->per_2_per_addr;
+ sdmac->is_ram_script = true;
break;
case IMX_DMATYPE_ASRC_SP:
per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
@@ -1309,6 +1313,11 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
{
struct sdma_desc *desc;
+ if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
+ dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
+ goto err_out;
+ }
+
desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
if (!desc)
goto err_out;
@@ -1559,6 +1568,8 @@ static int sdma_config_write(struct dma_chan *chan,
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
+ sdmac->is_ram_script = false;
+
if (direction == DMA_DEV_TO_MEM) {
sdmac->per_address = dmaengine_cfg->src_addr;
sdmac->watermark_level = dmaengine_cfg->src_maxburst *
@@ -1738,6 +1749,8 @@ static void sdma_load_firmware(const struct firmware *fw, void *context)
sdma_add_scripts(sdma, addr);
+ sdma->fw_loaded = true;
+
dev_info(sdma->dev, "loaded firmware %d.%d\n",
header->version_major,
header->version_minor);
--
2.7.4
Since sdma_transfer_init() will do sdma_load_context before any
sdma transfer, no need once more in sdma_config_channel().
Fixes: ad0d92d7ba6a ("dmaengine: imx-sdma: refine to load context only once")
Cc: <[email protected]>
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
Tested-by: Richard Leitner <[email protected]>
---
drivers/dma/imx-sdma.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 02f8584..1c636d2 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1107,7 +1107,6 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
static int sdma_config_channel(struct dma_chan *chan)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
- int ret;
sdma_disable_channel(chan);
@@ -1147,9 +1146,7 @@ static int sdma_config_channel(struct dma_chan *chan)
sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
}
- ret = sdma_load_context(sdmac);
-
- return ret;
+ return 0;
}
static int sdma_set_channel_priority(struct sdma_channel *sdmac,
--
2.7.4
For the compatibility of NXP internal legacy kernel before 4.19 which
is based on uart ram script and upstreaming kernel based on uart rom
script, add both uart ram/rom script in latest sdma firmware. By default
uart rom script used.
Besides, add two multi-fifo scripts for SAI/PDM on i.mx8m/8mm and add
back qspi script miss for v4(i.mx7d/8m/8mm family, but v3 is for i.mx6).
rom script:
uart_2_mcu_addr
uartsh_2_mcu_addr /* through spba bus */
am script:
uart_2_mcu_ram_addr
uartsh_2_mcu_ram_addr /* through spba bus */
Please get latest sdma firmware from the below and put them into the path
(/lib/firmware/imx/sdma/):
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
/tree/imx/sdma
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 17 +++++++++++++++--
include/linux/platform_data/dma-imx-sdma.h | 8 ++++++--
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index af85116..9519b41 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1696,8 +1696,8 @@ static void sdma_issue_pending(struct dma_chan *chan)
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
-#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
-#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45
+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46
static void sdma_add_scripts(struct sdma_engine *sdma,
const struct sdma_script_start_addrs *addr)
@@ -1721,6 +1721,19 @@ static void sdma_add_scripts(struct sdma_engine *sdma,
for (i = 0; i < sdma->script_number; i++)
if (addr_arr[i] > 0)
saddr_arr[i] = addr_arr[i];
+
+ /*
+ * get uart_2_mcu_addr/uartsh_2_mcu_addr rom script specially because
+ * they are now replaced by uart_2_mcu_ram_addr/uartsh_2_mcu_ram_addr
+ * to be compatible with legacy freescale/nxp sdma firmware, and they
+ * are located in the bottom part of sdma_script_start_addrs which are
+ * beyond the SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1.
+ */
+ if (addr->uart_2_mcu_addr)
+ sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_addr;
+ if (addr->uartsh_2_mcu_addr)
+ sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_addr;
+
}
static void sdma_load_firmware(const struct firmware *fw, void *context)
diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h
index 725602d..91dac29 100644
--- a/include/linux/platform_data/dma-imx-sdma.h
+++ b/include/linux/platform_data/dma-imx-sdma.h
@@ -20,12 +20,12 @@ struct sdma_script_start_addrs {
s32 per_2_firi_addr;
s32 mcu_2_firi_addr;
s32 uart_2_per_addr;
- s32 uart_2_mcu_addr;
+ s32 uart_2_mcu_ram_addr;
s32 per_2_app_addr;
s32 mcu_2_app_addr;
s32 per_2_per_addr;
s32 uartsh_2_per_addr;
- s32 uartsh_2_mcu_addr;
+ s32 uartsh_2_mcu_ram_addr;
s32 per_2_shp_addr;
s32 mcu_2_shp_addr;
s32 ata_2_mcu_addr;
@@ -52,6 +52,10 @@ struct sdma_script_start_addrs {
s32 zcanfd_2_mcu_addr;
s32 zqspi_2_mcu_addr;
s32 mcu_2_ecspi_addr;
+ s32 mcu_2_sai_addr;
+ s32 sai_2_mcu_addr;
+ s32 uart_2_mcu_addr;
+ s32 uartsh_2_mcu_addr;
/* End of v3 array */
s32 mcu_2_zqspi_addr;
/* End of v4 array */
--
2.7.4
Add terminated list for keeping descriptor so that it could be freed in
worker without any potential involving next descriptor raised up before
this descriptor freed, because vchan_get_all_descriptors get all
descriptors including the last terminated descriptor and the next
descriptor, hence, the next descriptor maybe freed unexpectly when it's
done in worker without this patch.
https://www.spinics.net/lists/dmaengine/msg23367.html
Signed-off-by: Robin Gong <[email protected]>
Reported-by: Richard Leitner <[email protected]>
---
drivers/dma/imx-sdma.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 9519b41..4174580 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -381,6 +381,7 @@ struct sdma_channel {
enum dma_status status;
struct imx_dma_data data;
struct work_struct terminate_worker;
+ struct list_head terminated;
bool is_ram_script;
};
@@ -1041,9 +1042,6 @@ static void sdma_channel_terminate_work(struct work_struct *work)
{
struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
terminate_worker);
- unsigned long flags;
- LIST_HEAD(head);
-
/*
* According to NXP R&D team a delay of one BD SDMA cost time
* (maximum is 1ms) should be added after disable of the channel
@@ -1052,10 +1050,7 @@ static void sdma_channel_terminate_work(struct work_struct *work)
*/
usleep_range(1000, 2000);
- spin_lock_irqsave(&sdmac->vc.lock, flags);
- vchan_get_all_descriptors(&sdmac->vc, &head);
- spin_unlock_irqrestore(&sdmac->vc.lock, flags);
- vchan_dma_desc_free_list(&sdmac->vc, &head);
+ vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated);
}
static int sdma_terminate_all(struct dma_chan *chan)
@@ -1069,6 +1064,13 @@ static int sdma_terminate_all(struct dma_chan *chan)
if (sdmac->desc) {
vchan_terminate_vdesc(&sdmac->desc->vd);
+ /*
+ * move out current descriptor into terminated list so that
+ * it could be free in sdma_channel_terminate_work alone
+ * later without potential involving next descriptor raised
+ * up before the last descriptor terminated.
+ */
+ vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated);
sdmac->desc = NULL;
schedule_work(&sdmac->terminate_worker);
}
@@ -2075,6 +2077,7 @@ static int sdma_probe(struct platform_device *pdev)
sdmac->channel = i;
sdmac->vc.desc_free = sdma_desc_free;
+ INIT_LIST_HEAD(&sdmac->terminated);
INIT_WORK(&sdmac->terminate_worker,
sdma_channel_terminate_work);
/*
--
2.7.4
On 07-04-21, 23:30, Robin Gong wrote:
> Add terminated list for keeping descriptor so that it could be freed in
> worker without any potential involving next descriptor raised up before
> this descriptor freed, because vchan_get_all_descriptors get all
> descriptors including the last terminated descriptor and the next
> descriptor, hence, the next descriptor maybe freed unexpectly when it's
> done in worker without this patch.
> https://www.spinics.net/lists/dmaengine/msg23367.html
Sound like you should implement .device_synchronize() and do the actual
work there..?
>
> Signed-off-by: Robin Gong <[email protected]>
> Reported-by: Richard Leitner <[email protected]>
> ---
> drivers/dma/imx-sdma.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 9519b41..4174580 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -381,6 +381,7 @@ struct sdma_channel {
> enum dma_status status;
> struct imx_dma_data data;
> struct work_struct terminate_worker;
> + struct list_head terminated;
> bool is_ram_script;
> };
>
> @@ -1041,9 +1042,6 @@ static void sdma_channel_terminate_work(struct work_struct *work)
> {
> struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
> terminate_worker);
> - unsigned long flags;
> - LIST_HEAD(head);
> -
> /*
> * According to NXP R&D team a delay of one BD SDMA cost time
> * (maximum is 1ms) should be added after disable of the channel
> @@ -1052,10 +1050,7 @@ static void sdma_channel_terminate_work(struct work_struct *work)
> */
> usleep_range(1000, 2000);
>
> - spin_lock_irqsave(&sdmac->vc.lock, flags);
> - vchan_get_all_descriptors(&sdmac->vc, &head);
> - spin_unlock_irqrestore(&sdmac->vc.lock, flags);
> - vchan_dma_desc_free_list(&sdmac->vc, &head);
> + vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated);
> }
>
> static int sdma_terminate_all(struct dma_chan *chan)
> @@ -1069,6 +1064,13 @@ static int sdma_terminate_all(struct dma_chan *chan)
>
> if (sdmac->desc) {
> vchan_terminate_vdesc(&sdmac->desc->vd);
> + /*
> + * move out current descriptor into terminated list so that
> + * it could be free in sdma_channel_terminate_work alone
> + * later without potential involving next descriptor raised
> + * up before the last descriptor terminated.
> + */
> + vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated);
> sdmac->desc = NULL;
> schedule_work(&sdmac->terminate_worker);
> }
> @@ -2075,6 +2077,7 @@ static int sdma_probe(struct platform_device *pdev)
>
> sdmac->channel = i;
> sdmac->vc.desc_free = sdma_desc_free;
> + INIT_LIST_HEAD(&sdmac->terminated);
> INIT_WORK(&sdmac->terminate_worker,
> sdma_channel_terminate_work);
> /*
> --
> 2.7.4
--
~Vinod
On 2021/04/12 17:39, Vinod Koul <[email protected]> wrote:
> On 07-04-21, 23:30, Robin Gong wrote:
> > Add terminated list for keeping descriptor so that it could be freed
> > in worker without any potential involving next descriptor raised up
> > before this descriptor freed, because vchan_get_all_descriptors get
> > all descriptors including the last terminated descriptor and the next
> > descriptor, hence, the next descriptor maybe freed unexpectly when
> > it's done in worker without this patch.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
> >
> spinics.net%2Flists%2Fdmaengine%2Fmsg23367.html&data=04%7C01%
> 7Cyib
> >
> in.gong%40nxp.com%7Cf255f329c8de459ffbaf08d8fd96d6c5%7C686ea1d3bc
> 2b4c6
> >
> fa92cd99c5c301635%7C0%7C0%7C637538171591949442%7CUnknown%7CT
> WFpbGZsb3d
> >
> 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C
> >
> 1000&sdata=3YFgzHFDNwRnogvxZpNcwVKOKpk4GHrgScdrbuMKjwE%3D
> &rese
> > rved=0
>
> Sound like you should implement .device_synchronize() and do the actual
> work there..?
Yes, I believe no issue here if call dmaengine_terminate_sync() always since
flush_work(&sdmac->terminate_worker) has already been in .device_synchronize() of
sdma driver. But unfortunately, have to use dmaengine_terminate_all() instead in some
non-atomic case like ALSA.
Hi Robin,
On Wed, Apr 7, 2021 at 4:15 AM Robin Gong <[email protected]> wrote:
>
> There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> transfer to be send twice in DMA mode. Please get more information from:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
> new sdma ram script which works in XCH mode as PIO inside sdma instead
> of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
> exist on all legacy i.mx6/7 soc family before i.mx6ul.
> NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
> 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
> still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
> for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
> or not.
> The first two reverted patches should be the same issue, though, it
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the event id is zero.
>
> PS:
> Please get sdma firmware from below linux-firmware and copy it to your
> local rootfs /lib/firmware/imx/sdma.
> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/imx/sdma
Without this series, SPI DMA does not work on i.MX8MM:
[ 41.315984] spi_master spi1: I/O Error in DMA RX
I applied your series and SPI DMA works now:
Reviewed-by: Fabio Estevam <[email protected]>
Thanks
On 06/11/21 21:51 Fabio Estevam <[email protected]> wrote:
> Hi Robin,
>
> On Wed, Apr 7, 2021 at 4:15 AM Robin Gong <[email protected]> wrote:
> >
> > There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> > transfer to be send twice in DMA mode. Please get more information from:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
> >
> nxp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=04%7C01%7
> Cyibin.g
> >
> ong%40nxp.com%7Cab59d4a2e95a4351e48708d92cdffc09%7C686ea1d3bc2
> b4c6fa92
> >
> cd99c5c301635%7C0%7C1%7C637590162781662129%7CUnknown%7CTWF
> pbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVC
> I6Mn0%3D%7C1000&sdata=DIbrrAYvpoJ4lKrkDJYvyoixR9DcMCgVDwuW
> gI5fuVw%3D&reserved=0. The workaround is adding new sdma ram
> script which works in XCH mode as PIO inside sdma instead of SMC mode,
> meanwhile, 'TX_THRESHOLD' should be 0. The issue should be exist on all
> legacy i.mx6/7 soc family before i.mx6ul.
> > NXP fix this design issue from i.mx6ul, so newer chips including
> > i.mx6ul/ 6ull/6sll do not need this workaroud anymore. All other
> > i.mx6/7/8 chips still need this workaroud. This patch set add new
> 'fsl,imx6ul-ecspi'
> > for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need
> > errata or not.
> > The first two reverted patches should be the same issue, though, it
> > seems 'fixed' by changing to other shp script. Hope Sean or Sascha
> > could have the chance to test this patch set if could fix their issues.
> > Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> > on i.mx8mm because the event id is zero.
> >
> > PS:
> > Please get sdma firmware from below linux-firmware and copy it to
> > your local rootfs /lib/firmware/imx/sdma.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.
> >
> kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ffirmware%2Flinux-fir
> mw
> >
> are.git%2Ftree%2Fimx%2Fsdma&data=04%7C01%7Cyibin.gong%40nxp.c
> om%7C
> >
> ab59d4a2e95a4351e48708d92cdffc09%7C686ea1d3bc2b4c6fa92cd99c5c301
> 635%7C
> >
> 0%7C1%7C637590162781662129%7CUnknown%7CTWFpbGZsb3d8eyJWIjoi
> MC4wLjAwMDA
> >
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=uL
> %2F
> >
> 6w%2F7JF76dqTfKYk4BT%2F5flWr0d3U2O86ABSq2UhI%3D&reserved=0
>
> Without this series, SPI DMA does not work on i.MX8MM:
>
> [ 41.315984] spi_master spi1: I/O Error in DMA RX
>
> I applied your series and SPI DMA works now:
>
> Reviewed-by: Fabio Estevam <[email protected]>
Thanks Fabio.
Hello Vinod, Mark,
Is my patch set good enough to merge? I remember someone else are
requesting it from last year like Fabio.
On 06/15/21 10:13 Fabio Estevam <[email protected]> wrote:
> Hi Robin,
>
> On Wed, Apr 7, 2021 at 4:15 AM Robin Gong <[email protected]> wrote:
> >
> > There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> > transfer to be send twice in DMA mode. Please get more information from:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
> >
> nxp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=04%7C01%7
> Cyibin.g
> >
> ong%40nxp.com%7C3c61a5cfd0574c1bc4eb08d92fa31257%7C686ea1d3bc2
> b4c6fa92
> >
> cd99c5c301635%7C0%7C1%7C637593199700307681%7CUnknown%7CTWF
> pbGZsb3d8eyJ
> >
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7
> C1000
> >
> &sdata=g2%2FwpDG22czIhj7ELil2kiiGPG0d74Ac7D8H3g0YtJc%3D&r
> eserv
> > ed=0. The workaround is adding new sdma ram script which works in XCH
> > mode as PIO inside sdma instead of SMC mode, meanwhile, 'TX_THRESHOLD'
> > should be 0. The issue should be
>
> Could you please confirm whether the sdma-imx7d.bin firmware available at
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kern
> el.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ffirmware%2Flinux-firmwa
> re.git%2Flog%2Fimx%2Fsdma%2Fsdma-imx7d.bin&data=04%7C01%7Cyi
> bin.gong%40nxp.com%7C3c61a5cfd0574c1bc4eb08d92fa31257%7C686ea1d
> 3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637593199700307681%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1
> haWwiLCJXVCI6Mn0%3D%7C1000&sdata=6UDEjl3ehC49af38OI%2FQhE
> mbeLYgQSJB91Kriihw1Jk%3D&reserved=0
>
> contains the "new sdma ram script which works in XCH mode as PIO inside
> sdma instead of SMC mode" fix?
Yes, it contains.
Hi Robin,
On Wed, Apr 7, 2021 at 4:15 AM Robin Gong <[email protected]> wrote:
>
> There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> transfer to be send twice in DMA mode. Please get more information from:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
> new sdma ram script which works in XCH mode as PIO inside sdma instead
> of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
Could you please confirm whether the sdma-imx7d.bin firmware available at
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/log/imx/sdma/sdma-imx7d.bin
contains the "new sdma ram script which works in XCH mode as PIO
inside sdma instead
of SMC mode" fix?
Thanks,
Fabio Estevam
On 07-04-21, 23:30, Robin Gong wrote:
> Add terminated list for keeping descriptor so that it could be freed in
> worker without any potential involving next descriptor raised up before
> this descriptor freed, because vchan_get_all_descriptors get all
> descriptors including the last terminated descriptor and the next
> descriptor, hence, the next descriptor maybe freed unexpectly when it's
> done in worker without this patch.
> https://www.spinics.net/lists/dmaengine/msg23367.html
Acked-By: Vinod Koul <[email protected]>
--
~Vinod
On 15-06-21, 01:55, Robin Gong wrote:
> On 06/11/21 21:51 Fabio Estevam <[email protected]> wrote:
> > Without this series, SPI DMA does not work on i.MX8MM:
> >
> > [ 41.315984] spi_master spi1: I/O Error in DMA RX
> >
> > I applied your series and SPI DMA works now:
> >
> > Reviewed-by: Fabio Estevam <[email protected]>
> Thanks Fabio.
> Hello Vinod, Mark,
> Is my patch set good enough to merge? I remember someone else are
> requesting it from last year like Fabio.
I have acked the last dmaengine patch, is there any else required from
me? Which tree will be this merged thru?
--
~Vinod
On 15/06/21 14:08 Vinod Koul <[email protected]> wrote:
> On 15-06-21, 01:55, Robin Gong wrote:
> > On 06/11/21 21:51 Fabio Estevam <[email protected]> wrote:
>
> > > Without this series, SPI DMA does not work on i.MX8MM:
> > >
> > > [ 41.315984] spi_master spi1: I/O Error in DMA RX
> > >
> > > I applied your series and SPI DMA works now:
> > >
> > > Reviewed-by: Fabio Estevam <[email protected]>
> > Thanks Fabio.
> > Hello Vinod, Mark,
> > Is my patch set good enough to merge? I remember someone else are
> > requesting it from last year like Fabio.
>
> I have acked the last dmaengine patch, is there any else required from me?
> Which tree will be this merged thru?
Thanks Vinod, mainline is enough I think.
On 15-06-21, 06:36, Robin Gong wrote:
> On 15/06/21 14:08 Vinod Koul <[email protected]> wrote:
> > On 15-06-21, 01:55, Robin Gong wrote:
> > > On 06/11/21 21:51 Fabio Estevam <[email protected]> wrote:
> >
> > > > Without this series, SPI DMA does not work on i.MX8MM:
> > > >
> > > > [ 41.315984] spi_master spi1: I/O Error in DMA RX
> > > >
> > > > I applied your series and SPI DMA works now:
> > > >
> > > > Reviewed-by: Fabio Estevam <[email protected]>
> > > Thanks Fabio.
> > > Hello Vinod, Mark,
> > > Is my patch set good enough to merge? I remember someone else are
> > > requesting it from last year like Fabio.
> >
> > I have acked the last dmaengine patch, is there any else required from me?
> > Which tree will be this merged thru?
> Thanks Vinod, mainline is enough I think.
I meant which subsystem tree will this go thru :)
--
~Vinod
On 15/06/21 20:08 Vinod Koul <[email protected]> wrote:
> On 15-06-21, 06:36, Robin Gong wrote:
> > On 15/06/21 14:08 Vinod Koul <[email protected]> wrote:
> > > On 15-06-21, 01:55, Robin Gong wrote:
> > > > On 06/11/21 21:51 Fabio Estevam <[email protected]> wrote:
> > >
> > > > > Without this series, SPI DMA does not work on i.MX8MM:
> > > > >
> > > > > [ 41.315984] spi_master spi1: I/O Error in DMA RX
> > > > >
> > > > > I applied your series and SPI DMA works now:
> > > > >
> > > > > Reviewed-by: Fabio Estevam <[email protected]>
> > > > Thanks Fabio.
> > > > Hello Vinod, Mark,
> > > > Is my patch set good enough to merge? I remember someone else are
> > > > requesting it from last year like Fabio.
> > >
> > > I have acked the last dmaengine patch, is there any else required from me?
> > > Which tree will be this merged thru?
> > Thanks Vinod, mainline is enough I think.
>
> I meant which subsystem tree will this go thru :)
I thought the patches with 'spi' tag could be merged into spi tree while
'dmaengine' merged into dmaengine tree, the rest of dts patch merged
into i.mx branch. But from HW errata view, maybe merging all into i.mx
branch is a better way?
On 15-06-21, 14:10, Robin Gong wrote:
> On 15/06/21 20:08 Vinod Koul <[email protected]> wrote:
> > On 15-06-21, 06:36, Robin Gong wrote:
> > > On 15/06/21 14:08 Vinod Koul <[email protected]> wrote:
> > > > On 15-06-21, 01:55, Robin Gong wrote:
> > > > > On 06/11/21 21:51 Fabio Estevam <[email protected]> wrote:
> > > >
> > > > > > Without this series, SPI DMA does not work on i.MX8MM:
> > > > > >
> > > > > > [ 41.315984] spi_master spi1: I/O Error in DMA RX
> > > > > >
> > > > > > I applied your series and SPI DMA works now:
> > > > > >
> > > > > > Reviewed-by: Fabio Estevam <[email protected]>
> > > > > Thanks Fabio.
> > > > > Hello Vinod, Mark,
> > > > > Is my patch set good enough to merge? I remember someone else are
> > > > > requesting it from last year like Fabio.
> > > >
> > > > I have acked the last dmaengine patch, is there any else required from me?
> > > > Which tree will be this merged thru?
> > > Thanks Vinod, mainline is enough I think.
> >
> > I meant which subsystem tree will this go thru :)
> I thought the patches with 'spi' tag could be merged into spi tree while
> 'dmaengine' merged into dmaengine tree, the rest of dts patch merged
> into i.mx branch. But from HW errata view, maybe merging all into i.mx
> branch is a better way?
Are there any dependecies between patches? If not all can merge thru
respective subsystem. You already have the ack, so I dont mind if you
pick thru imx tree
--
~Vinod
On 16/06/21 18:16 Vinod Koul <[email protected]> wrote:
> On 15-06-21, 14:10, Robin Gong wrote:
> > On 15/06/21 20:08 Vinod Koul <[email protected]> wrote:
> > I thought the patches with 'spi' tag could be merged into spi tree
> > while 'dmaengine' merged into dmaengine tree, the rest of dts patch
> > merged into i.mx branch. But from HW errata view, maybe merging all
> > into i.mx branch is a better way?
>
> Are there any dependecies between patches? If not all can merge thru
> respective subsystem. You already have the ack, so I dont mind if you pick thru
> imx tree
Yes, this errata need both spi/dma work together, thanks Vinod.
Hi Shawn,
Do you have any comment for v14? If not, could it be
merged into imx tree including spi/dmaengine?
Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> Add 'fw_loaded' and 'is_ram_script' to check if the script used by channel
> is ram script and it's loaded or not, so that could prevent meaningless
> following malloc dma descriptor and bd allocate in sdma_transfer_init(),
> otherwise memory may be consumed out potentially without free in case
> that spi fallback into pio while dma transfer failed by sdma firmware not
> ready(next ERR009165 patch depends on sdma RAM scripts/firmware).
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Vinod Koul <[email protected]>
> ---
> drivers/dma/imx-sdma.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 1c636d2..78dcfe2 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -381,6 +381,7 @@ struct sdma_channel {
> enum dma_status status;
> struct imx_dma_data data;
> struct work_struct terminate_worker;
> + bool is_ram_script;
> };
>
> #define IMX_DMA_SG_LOOP BIT(0)
> @@ -444,6 +445,7 @@ struct sdma_engine {
> struct sdma_buffer_descriptor *bd0;
> /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
> bool clk_ratio;
> + bool fw_loaded;
> };
>
> static int sdma_config_write(struct dma_chan *chan,
> @@ -899,6 +901,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
> case IMX_DMATYPE_SSI_DUAL:
> per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
> emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
> + sdmac->is_ram_script = true;
> break;
> case IMX_DMATYPE_SSI_SP:
> case IMX_DMATYPE_MMC:
> @@ -913,6 +916,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
> per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
> emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
> per_2_per = sdma->script_addrs->per_2_per_addr;
> + sdmac->is_ram_script = true;
> break;
> case IMX_DMATYPE_ASRC_SP:
> per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
> @@ -1309,6 +1313,11 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
> {
> struct sdma_desc *desc;
>
> + if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
> + dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
> + goto err_out;
> + }
> +
> desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
> if (!desc)
> goto err_out;
> @@ -1559,6 +1568,8 @@ static int sdma_config_write(struct dma_chan *chan,
> {
> struct sdma_channel *sdmac = to_sdma_chan(chan);
>
> + sdmac->is_ram_script = false;
> +
While it's working correctly, I find it confusing to have this
initialization at this point in the code. Please fold this into
sdma_get_pc(), where it gets changed as needed.
Other than this small issue, this patch is:
Reviewed-by: Lucas Stach <[email protected]>
> if (direction == DMA_DEV_TO_MEM) {
> sdmac->per_address = dmaengine_cfg->src_addr;
> sdmac->watermark_level = dmaengine_cfg->src_maxburst *
> @@ -1738,6 +1749,8 @@ static void sdma_load_firmware(const struct firmware *fw, void *context)
>
> sdma_add_scripts(sdma, addr);
>
> + sdma->fw_loaded = true;
> +
> dev_info(sdma->dev, "loaded firmware %d.%d\n",
> header->version_major,
> header->version_minor);
Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> Add mcu_2_ecspi script to fix ecspi errata ERR009165.
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Vinod Koul <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
> ---
> drivers/dma/imx-sdma.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 78dcfe2..86bd383 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -892,6 +892,10 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
> emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
> break;
> case IMX_DMATYPE_CSPI:
> + per_2_emi = sdma->script_addrs->app_2_mcu_addr;
> + emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
> + sdmac->is_ram_script = true;
> + break;
> case IMX_DMATYPE_EXT:
> case IMX_DMATYPE_SSI:
> case IMX_DMATYPE_SAI:
Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> Change to XCH mode even in dma mode, please refer to the below
> errata:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Mark Brown <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
> ---
> drivers/spi/spi-imx.c | 10 +++-------
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> index 4fe767a..cf235b9 100644
> --- a/drivers/spi/spi-imx.c
> +++ b/drivers/spi/spi-imx.c
> @@ -593,8 +593,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
> ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> spi_imx->spi_bus_clk = clk;
>
> - if (spi_imx->usedma)
> - ctrl |= MX51_ECSPI_CTRL_SMC;
> + /* ERR009165: work in XHC mode as PIO */
> + ctrl &= ~MX51_ECSPI_CTRL_SMC;
>
> writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
>
> @@ -625,7 +625,7 @@ static void mx51_setup_wml(struct spi_imx_data *spi_imx)
> * and enable DMA request.
> */
> writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> - MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
> + MX51_ECSPI_DMA_TX_WML(0) |
> MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> @@ -1234,10 +1234,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
> {
> int ret;
>
> - /* use pio mode for i.mx6dl chip TKT238285 */
> - if (of_machine_is_compatible("fsl,imx6dl"))
> - return 0;
> -
> spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
>
> /* Prepare for TX DMA: */
Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> ERR009165 fixed on i.mx6ul/6ull/6sll. All other i.mx6/7 and
> i.mx8m/8mm still need this errata. Please refer to nxp official
> errata document from https://www.nxp.com/ .
>
> For removing workaround on those chips. Add new i.mx6ul type.
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Mark Brown <[email protected]>
> ---
> drivers/spi/spi-imx.c | 47 +++++++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 43 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> index cf235b9..d18ee25 100644
> --- a/drivers/spi/spi-imx.c
> +++ b/drivers/spi/spi-imx.c
> @@ -59,6 +59,7 @@ enum spi_imx_devtype {
> IMX35_CSPI, /* CSPI on all i.mx except above */
> IMX51_ECSPI, /* ECSPI on i.mx51 */
> IMX53_ECSPI, /* ECSPI on i.mx53 and later */
> + IMX6UL_ECSPI, /* ERR009165 fix from i.mx6ul */
This patch could be a lot smaller if you didn't introduce a new
devtype. You could just use the IMX51_ECSPI in
imx6ul_ecspi_devtype_data, as all you care about as a relevant
difference is the tx_glitch_fixed property, which isn't tied to the
devtype.
Regards,
Lucas
> };
>
> struct spi_imx_data;
> @@ -78,6 +79,11 @@ struct spi_imx_devtype_data {
> bool has_slavemode;
> unsigned int fifo_size;
> bool dynamic_burst;
> + /*
> + * ERR009165 fixed or not:
> + * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
> + */
> + bool tx_glitch_fixed;
> enum spi_imx_devtype devtype;
> };
>
> @@ -134,6 +140,11 @@ static inline int is_imx51_ecspi(struct spi_imx_data *d)
> return d->devtype_data->devtype == IMX51_ECSPI;
> }
>
> +static inline int is_imx6ul_ecspi(struct spi_imx_data *d)
> +{
> + return d->devtype_data->devtype == IMX6UL_ECSPI;
> +}
> +
> static inline int is_imx53_ecspi(struct spi_imx_data *d)
> {
> return d->devtype_data->devtype == IMX53_ECSPI;
> @@ -593,8 +604,14 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
> ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> spi_imx->spi_bus_clk = clk;
>
> - /* ERR009165: work in XHC mode as PIO */
> - ctrl &= ~MX51_ECSPI_CTRL_SMC;
> + /*
> + * ERR009165: work in XHC mode instead of SMC as PIO on the chips
> + * before i.mx6ul.
> + */
> + if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
> + ctrl |= MX51_ECSPI_CTRL_SMC;
> + else
> + ctrl &= ~MX51_ECSPI_CTRL_SMC;
>
> writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
>
> @@ -620,12 +637,16 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
>
> static void mx51_setup_wml(struct spi_imx_data *spi_imx)
> {
> + u32 tx_wml = 0;
> +
> + if (spi_imx->devtype_data->tx_glitch_fixed)
> + tx_wml = spi_imx->wml;
> /*
> * Configure the DMA register: setup the watermark
> * and enable DMA request.
> */
> writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> - MX51_ECSPI_DMA_TX_WML(0) |
> + MX51_ECSPI_DMA_TX_WML(tx_wml) |
> MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> @@ -1019,6 +1040,23 @@ static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
> .devtype = IMX53_ECSPI,
> };
>
> +static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
> + .intctrl = mx51_ecspi_intctrl,
> + .prepare_message = mx51_ecspi_prepare_message,
> + .prepare_transfer = mx51_ecspi_prepare_transfer,
> + .trigger = mx51_ecspi_trigger,
> + .rx_available = mx51_ecspi_rx_available,
> + .reset = mx51_ecspi_reset,
> + .setup_wml = mx51_setup_wml,
> + .fifo_size = 64,
> + .has_dmamode = true,
> + .dynamic_burst = true,
> + .has_slavemode = true,
> + .tx_glitch_fixed = true,
> + .disable = mx51_ecspi_disable,
> + .devtype = IMX6UL_ECSPI,
> +};
> +
> static const struct of_device_id spi_imx_dt_ids[] = {
> { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
> { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
> @@ -1027,6 +1065,7 @@ static const struct of_device_id spi_imx_dt_ids[] = {
> { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
> { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
> { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
> + { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
> @@ -1604,7 +1643,7 @@ static int spi_imx_probe(struct platform_device *pdev)
> spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
> | SPI_NO_CS;
> if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
> - is_imx53_ecspi(spi_imx))
> + is_imx53_ecspi(spi_imx) || is_imx6ul_ecspi(spi_imx))
> spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
>
> spi_imx->spi_drctl = spi_drctl;
Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> ECSPI issue fixed from i.mx6ul at hardware level, no need
> ERR009165 anymore on those chips such as i.mx8mq.
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Vinod Koul <[email protected]>
> ---
> drivers/dma/imx-sdma.c | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 86bd383..af85116 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -422,6 +422,13 @@ struct sdma_driver_data {
> int num_events;
> struct sdma_script_start_addrs *script_addrs;
> bool check_ratio;
> + /*
> + * ecspi ERR009165 fixed should be done in sdma script
> + * and it has been fixed in soc from i.mx6ul.
> + * please get more information from the below link:
> + * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
> + */
> + bool ecspi_fixed;
> };
>
> struct sdma_engine {
> @@ -542,6 +549,13 @@ static struct sdma_driver_data sdma_imx6q = {
> .script_addrs = &sdma_script_imx6q,
> };
>
> +static struct sdma_driver_data sdma_imx6ul = {
> + .chnenbl0 = SDMA_CHNENBL0_IMX35,
> + .num_events = 48,
> + .script_addrs = &sdma_script_imx6q,
> + .ecspi_fixed = true,
> +};
> +
> static struct sdma_script_start_addrs sdma_script_imx7d = {
> .ap_2_ap_addr = 644,
> .uart_2_mcu_addr = 819,
> @@ -575,6 +589,7 @@ static const struct of_device_id sdma_dt_ids[] = {
> { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
> { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
> { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
> + { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
> { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
> { /* sentinel */ }
> };
> @@ -1144,8 +1159,17 @@ static int sdma_config_channel(struct dma_chan *chan)
> if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
> sdmac->peripheral_type == IMX_DMATYPE_ASRC)
> sdma_set_watermarklevel_for_p2p(sdmac);
> - } else
> + } else {
> + /*
> + * ERR009165 fixed from i.mx6ul, no errata need,
> + * set bit31 to let sdma script skip the errata.
> + */
> + if (sdmac->peripheral_type == IMX_DMATYPE_CSPI &&
> + sdmac->direction == DMA_MEM_TO_DEV &&
> + sdmac->sdma->drvdata->ecspi_fixed)
> + __set_bit(31, &sdmac->watermark_level);
Hm, I don't care much either way, but couldn't we just return the
regular mcu_2_app script in sdma_get_pc when ecspi_fixed == true? Seems
like this would be a simpler and more targeted code change.
Regards,
Lucas
> __set_bit(sdmac->event_id0, sdmac->event_mask);
> + }
>
> /* Address */
> sdmac->shp_addr = sdmac->per_address;
Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> Add terminated list for keeping descriptor so that it could be freed in
> worker without any potential involving next descriptor raised up before
> this descriptor freed, because vchan_get_all_descriptors get all
> descriptors including the last terminated descriptor and the next
> descriptor, hence, the next descriptor maybe freed unexpectly when it's
> done in worker without this patch.
> https://www.spinics.net/lists/dmaengine/msg23367.html
>
> Signed-off-by: Robin Gong <[email protected]>
> Reported-by: Richard Leitner <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
> ---
> drivers/dma/imx-sdma.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 9519b41..4174580 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -381,6 +381,7 @@ struct sdma_channel {
> enum dma_status status;
> struct imx_dma_data data;
> struct work_struct terminate_worker;
> + struct list_head terminated;
> bool is_ram_script;
> };
>
> @@ -1041,9 +1042,6 @@ static void sdma_channel_terminate_work(struct work_struct *work)
> {
> struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
> terminate_worker);
> - unsigned long flags;
> - LIST_HEAD(head);
> -
> /*
> * According to NXP R&D team a delay of one BD SDMA cost time
> * (maximum is 1ms) should be added after disable of the channel
> @@ -1052,10 +1050,7 @@ static void sdma_channel_terminate_work(struct work_struct *work)
> */
> usleep_range(1000, 2000);
>
> - spin_lock_irqsave(&sdmac->vc.lock, flags);
> - vchan_get_all_descriptors(&sdmac->vc, &head);
> - spin_unlock_irqrestore(&sdmac->vc.lock, flags);
> - vchan_dma_desc_free_list(&sdmac->vc, &head);
> + vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated);
> }
>
> static int sdma_terminate_all(struct dma_chan *chan)
> @@ -1069,6 +1064,13 @@ static int sdma_terminate_all(struct dma_chan *chan)
>
> if (sdmac->desc) {
> vchan_terminate_vdesc(&sdmac->desc->vd);
> + /*
> + * move out current descriptor into terminated list so that
> + * it could be free in sdma_channel_terminate_work alone
> + * later without potential involving next descriptor raised
> + * up before the last descriptor terminated.
> + */
> + vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated);
> sdmac->desc = NULL;
> schedule_work(&sdmac->terminate_worker);
> }
> @@ -2075,6 +2077,7 @@ static int sdma_probe(struct platform_device *pdev)
>
> sdmac->channel = i;
> sdmac->vc.desc_free = sdma_desc_free;
> + INIT_LIST_HEAD(&sdmac->terminated);
> INIT_WORK(&sdmac->terminate_worker,
> sdma_channel_terminate_work);
> /*
Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> For the compatibility of NXP internal legacy kernel before 4.19 which
> is based on uart ram script and upstreaming kernel based on uart rom
> script, add both uart ram/rom script in latest sdma firmware. By default
> uart rom script used.
> Besides, add two multi-fifo scripts for SAI/PDM on i.mx8m/8mm and add
> back qspi script miss for v4(i.mx7d/8m/8mm family, but v3 is for i.mx6).
>
> rom script:
> uart_2_mcu_addr
> uartsh_2_mcu_addr /* through spba bus */
> am script:
> uart_2_mcu_ram_addr
> uartsh_2_mcu_ram_addr /* through spba bus */
>
> Please get latest sdma firmware from the below and put them into the path
> (/lib/firmware/imx/sdma/):
> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
> /tree/imx/sdma
>
> Signed-off-by: Robin Gong <[email protected]>
> Acked-by: Vinod Koul <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
> ---
> drivers/dma/imx-sdma.c | 17 +++++++++++++++--
> include/linux/platform_data/dma-imx-sdma.h | 8 ++++++--
> 2 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index af85116..9519b41 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -1696,8 +1696,8 @@ static void sdma_issue_pending(struct dma_chan *chan)
>
> #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
> #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
> -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
> -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
> +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45
> +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46
>
> static void sdma_add_scripts(struct sdma_engine *sdma,
> const struct sdma_script_start_addrs *addr)
> @@ -1721,6 +1721,19 @@ static void sdma_add_scripts(struct sdma_engine *sdma,
> for (i = 0; i < sdma->script_number; i++)
> if (addr_arr[i] > 0)
> saddr_arr[i] = addr_arr[i];
> +
> + /*
> + * get uart_2_mcu_addr/uartsh_2_mcu_addr rom script specially because
> + * they are now replaced by uart_2_mcu_ram_addr/uartsh_2_mcu_ram_addr
> + * to be compatible with legacy freescale/nxp sdma firmware, and they
> + * are located in the bottom part of sdma_script_start_addrs which are
> + * beyond the SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1.
> + */
> + if (addr->uart_2_mcu_addr)
> + sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_addr;
> + if (addr->uartsh_2_mcu_addr)
> + sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_addr;
> +
> }
>
> static void sdma_load_firmware(const struct firmware *fw, void *context)
> diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h
> index 725602d..91dac29 100644
> --- a/include/linux/platform_data/dma-imx-sdma.h
> +++ b/include/linux/platform_data/dma-imx-sdma.h
> @@ -20,12 +20,12 @@ struct sdma_script_start_addrs {
> s32 per_2_firi_addr;
> s32 mcu_2_firi_addr;
> s32 uart_2_per_addr;
> - s32 uart_2_mcu_addr;
> + s32 uart_2_mcu_ram_addr;
> s32 per_2_app_addr;
> s32 mcu_2_app_addr;
> s32 per_2_per_addr;
> s32 uartsh_2_per_addr;
> - s32 uartsh_2_mcu_addr;
> + s32 uartsh_2_mcu_ram_addr;
> s32 per_2_shp_addr;
> s32 mcu_2_shp_addr;
> s32 ata_2_mcu_addr;
> @@ -52,6 +52,10 @@ struct sdma_script_start_addrs {
> s32 zcanfd_2_mcu_addr;
> s32 zqspi_2_mcu_addr;
> s32 mcu_2_ecspi_addr;
> + s32 mcu_2_sai_addr;
> + s32 sai_2_mcu_addr;
> + s32 uart_2_mcu_addr;
> + s32 uartsh_2_mcu_addr;
> /* End of v3 array */
> s32 mcu_2_zqspi_addr;
> /* End of v4 array */
On 09/07/21 17:25 Lucas Stach <[email protected]> wrote:
> Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> > Add 'fw_loaded' and 'is_ram_script' to check if the script used by
> > channel is ram script and it's loaded or not, so that could prevent
> > meaningless following malloc dma descriptor and bd allocate in
> > sdma_transfer_init(), otherwise memory may be consumed out potentially
> > without free in case that spi fallback into pio while dma transfer
> > failed by sdma firmware not ready(next ERR009165 patch depends on sdma
> RAM scripts/firmware).
> >
> > Signed-off-by: Robin Gong <[email protected]>
> > Acked-by: Vinod Koul <[email protected]>
> > ---
> > drivers/dma/imx-sdma.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index
> > 1c636d2..78dcfe2 100644
> > --- a/drivers/dma/imx-sdma.c
> > +++ b/drivers/dma/imx-sdma.c
> > @@ -381,6 +381,7 @@ struct sdma_channel {
> > enum dma_status status;
> > struct imx_dma_data data;
> > struct work_struct terminate_worker;
> > + bool is_ram_script;
> > };
> >
> > #define IMX_DMA_SG_LOOP BIT(0)
> > @@ -444,6 +445,7 @@ struct sdma_engine {
> > struct sdma_buffer_descriptor *bd0;
> > /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
> > bool clk_ratio;
> > + bool fw_loaded;
> > };
> >
> > static int sdma_config_write(struct dma_chan *chan, @@ -899,6 +901,7
> > @@ static void sdma_get_pc(struct sdma_channel *sdmac,
> > case IMX_DMATYPE_SSI_DUAL:
> > per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
> > emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
> > + sdmac->is_ram_script = true;
> > break;
> > case IMX_DMATYPE_SSI_SP:
> > case IMX_DMATYPE_MMC:
> > @@ -913,6 +916,7 @@ static void sdma_get_pc(struct sdma_channel
> *sdmac,
> > per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
> > emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
> > per_2_per = sdma->script_addrs->per_2_per_addr;
> > + sdmac->is_ram_script = true;
> > break;
> > case IMX_DMATYPE_ASRC_SP:
> > per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
> > @@ -1309,6 +1313,11 @@ static struct sdma_desc
> > *sdma_transfer_init(struct sdma_channel *sdmac, {
> > struct sdma_desc *desc;
> >
> > + if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
> > + dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
> > + goto err_out;
> > + }
> > +
> > desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
> > if (!desc)
> > goto err_out;
> > @@ -1559,6 +1568,8 @@ static int sdma_config_write(struct dma_chan
> > *chan, {
> > struct sdma_channel *sdmac = to_sdma_chan(chan);
> >
> > + sdmac->is_ram_script = false;
> > +
> While it's working correctly, I find it confusing to have this initialization at this
> point in the code. Please fold this into sdma_get_pc(), where it gets changed as
> needed.
Here 'is_ram_script = false' just clear is_ram_script so that the later sdma_get_pc()
could set is_ram_script correctly if it's a ram script. Yes, move it to early part of sdma_get_pc
also works.
>
> Other than this small issue, this patch is:
> Reviewed-by: Lucas Stach <[email protected]>
>
> > if (direction == DMA_DEV_TO_MEM) {
> > sdmac->per_address = dmaengine_cfg->src_addr;
> > sdmac->watermark_level = dmaengine_cfg->src_maxburst * @@
> -1738,6
> > +1749,8 @@ static void sdma_load_firmware(const struct firmware *fw,
> > void *context)
> >
> > sdma_add_scripts(sdma, addr);
> >
> > + sdma->fw_loaded = true;
> > +
> > dev_info(sdma->dev, "loaded firmware %d.%d\n",
> > header->version_major,
> > header->version_minor);
>
On 09/07/21 17:42 Lucas Stach <[email protected]> wrote:
> Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> > ERR009165 fixed on i.mx6ul/6ull/6sll. All other i.mx6/7 and i.mx8m/8mm
> > still need this errata. Please refer to nxp official errata document
> > from
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.n
> xp.com%2F&data=04%7C01%7Cyibin.gong%40nxp.com%7C48156bc93d
> c84ac26e9d08d942bdc0ac%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> 7C1%7C637614205017900475%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> mp;sdata=keYQubzt1jWrKhaxXr40RL41vzFuIn7x1Sasa3p%2F9Xo%3D&res
> erved=0 .
> >
> > For removing workaround on those chips. Add new i.mx6ul type.
> >
> > Signed-off-by: Robin Gong <[email protected]>
> > Acked-by: Mark Brown <[email protected]>
> > ---
> > drivers/spi/spi-imx.c | 47
> > +++++++++++++++++++++++++++++++++++++++++++----
> > 1 file changed, 43 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > cf235b9..d18ee25 100644
> > --- a/drivers/spi/spi-imx.c
> > +++ b/drivers/spi/spi-imx.c
> > @@ -59,6 +59,7 @@ enum spi_imx_devtype {
> > IMX35_CSPI, /* CSPI on all i.mx except above */
> > IMX51_ECSPI, /* ECSPI on i.mx51 */
> > IMX53_ECSPI, /* ECSPI on i.mx53 and later */
> > + IMX6UL_ECSPI, /* ERR009165 fix from i.mx6ul */
>
> This patch could be a lot smaller if you didn't introduce a new devtype. You
> could just use the IMX51_ECSPI in imx6ul_ecspi_devtype_data, as all you care
> about as a relevant difference is the tx_glitch_fixed property, which isn't tied
> to the devtype.
I knew tx_glitch_fixed was enough but I still prefer to add new 'IMX6UL_ECSPI' because
we can clearly choose the right IP which has fix the issue while legacy IMX51 if it's not
fixed by dts.
> > };
> >
> > struct spi_imx_data;
> > @@ -78,6 +79,11 @@ struct spi_imx_devtype_data {
> > bool has_slavemode;
> > unsigned int fifo_size;
> > bool dynamic_burst;
> > + /*
> > + * ERR009165 fixed or not:
> > + *
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.n
> xp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=04%7C01%7C
> yibin.gong%40nxp.com%7C48156bc93dc84ac26e9d08d942bdc0ac%7C686ea
> 1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637614205017900475%7CU
> nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6
> Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=J9iZb93uN1VEriN%2F2GAE
> TWxdv4n%2FD6ZXteMCFkB8KHM%3D&reserved=0
> > + */
> > + bool tx_glitch_fixed;
> > enum spi_imx_devtype devtype;
> > };
> >
> > @@ -134,6 +140,11 @@ static inline int is_imx51_ecspi(struct spi_imx_data
> *d)
> > return d->devtype_data->devtype == IMX51_ECSPI; }
> >
> > +static inline int is_imx6ul_ecspi(struct spi_imx_data *d) {
> > + return d->devtype_data->devtype == IMX6UL_ECSPI; }
> > +
> > static inline int is_imx53_ecspi(struct spi_imx_data *d) {
> > return d->devtype_data->devtype == IMX53_ECSPI; @@ -593,8 +604,14
> @@
> > static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
> > ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> > spi_imx->spi_bus_clk = clk;
> >
> > - /* ERR009165: work in XHC mode as PIO */
> > - ctrl &= ~MX51_ECSPI_CTRL_SMC;
> > + /*
> > + * ERR009165: work in XHC mode instead of SMC as PIO on the chips
> > + * before i.mx6ul.
> > + */
> > + if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
> > + ctrl |= MX51_ECSPI_CTRL_SMC;
> > + else
> > + ctrl &= ~MX51_ECSPI_CTRL_SMC;
> >
> > writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
> >
> > @@ -620,12 +637,16 @@ static int mx51_ecspi_prepare_transfer(struct
> > spi_imx_data *spi_imx,
> >
> > static void mx51_setup_wml(struct spi_imx_data *spi_imx) {
> > + u32 tx_wml = 0;
> > +
> > + if (spi_imx->devtype_data->tx_glitch_fixed)
> > + tx_wml = spi_imx->wml;
> > /*
> > * Configure the DMA register: setup the watermark
> > * and enable DMA request.
> > */
> > writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> > - MX51_ECSPI_DMA_TX_WML(0) |
> > + MX51_ECSPI_DMA_TX_WML(tx_wml) |
> > MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> > MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> > MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> @@ -1019,6
> > +1040,23 @@ static struct spi_imx_devtype_data
> imx53_ecspi_devtype_data = {
> > .devtype = IMX53_ECSPI,
> > };
> >
> > +static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
> > + .intctrl = mx51_ecspi_intctrl,
> > + .prepare_message = mx51_ecspi_prepare_message,
> > + .prepare_transfer = mx51_ecspi_prepare_transfer,
> > + .trigger = mx51_ecspi_trigger,
> > + .rx_available = mx51_ecspi_rx_available,
> > + .reset = mx51_ecspi_reset,
> > + .setup_wml = mx51_setup_wml,
> > + .fifo_size = 64,
> > + .has_dmamode = true,
> > + .dynamic_burst = true,
> > + .has_slavemode = true,
> > + .tx_glitch_fixed = true,
> > + .disable = mx51_ecspi_disable,
> > + .devtype = IMX6UL_ECSPI,
> > +};
> > +
> > static const struct of_device_id spi_imx_dt_ids[] = {
> > { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
> > { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data,
> > }, @@ -1027,6 +1065,7 @@ static const struct of_device_id spi_imx_dt_ids[]
> = {
> > { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
> > { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
> > { .compatible = "fsl,imx53-ecspi", .data =
> > &imx53_ecspi_devtype_data, },
> > + { .compatible = "fsl,imx6ul-ecspi", .data =
> > +&imx6ul_ecspi_devtype_data, },
> > { /* sentinel */ }
> > };
> > MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); @@ -1604,7 +1643,7 @@
> static
> > int spi_imx_probe(struct platform_device *pdev)
> > spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA |
> SPI_CS_HIGH \
> > | SPI_NO_CS;
> > if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
> > - is_imx53_ecspi(spi_imx))
> > + is_imx53_ecspi(spi_imx) || is_imx6ul_ecspi(spi_imx))
> > spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
> >
> > spi_imx->spi_drctl = spi_drctl;
>
On 09/07/21 17:45 Lucas Stach <[email protected]> wrote:
> Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> > ECSPI issue fixed from i.mx6ul at hardware level, no need
> > ERR009165 anymore on those chips such as i.mx8mq.
> >
> > Signed-off-by: Robin Gong <[email protected]>
> > Acked-by: Vinod Koul <[email protected]>
> > ---
> > drivers/dma/imx-sdma.c | 26 +++++++++++++++++++++++++-
> > 1 file changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index
> > 86bd383..af85116 100644
> > --- a/drivers/dma/imx-sdma.c
> > +++ b/drivers/dma/imx-sdma.c
> > @@ -422,6 +422,13 @@ struct sdma_driver_data {
> > int num_events;
> > struct sdma_script_start_addrs *script_addrs;
> > bool check_ratio;
> > + /*
> > + * ecspi ERR009165 fixed should be done in sdma script
> > + * and it has been fixed in soc from i.mx6ul.
> > + * please get more information from the below link:
> > + *
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.n
> xp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=04%7C01%7C
> yibin.gong%40nxp.com%7Cc950b1bdb6544eda369408d942be35d9%7C686ea
> 1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637614206980361737%7CU
> nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6
> Ik1haWwiLCJXVCI6Mn0%3D%7C2000&sdata=6iT6%2FbzJHyWnkhkDynY
> wmK9nn2hgCDy1GyzELeEk9K8%3D&reserved=0
> > + */
> > + bool ecspi_fixed;
> > };
> >
> > struct sdma_engine {
> > @@ -542,6 +549,13 @@ static struct sdma_driver_data sdma_imx6q = {
> > .script_addrs = &sdma_script_imx6q,
> > };
> >
> > +static struct sdma_driver_data sdma_imx6ul = {
> > + .chnenbl0 = SDMA_CHNENBL0_IMX35,
> > + .num_events = 48,
> > + .script_addrs = &sdma_script_imx6q,
> > + .ecspi_fixed = true,
> > +};
> > +
> > static struct sdma_script_start_addrs sdma_script_imx7d = {
> > .ap_2_ap_addr = 644,
> > .uart_2_mcu_addr = 819,
> > @@ -575,6 +589,7 @@ static const struct of_device_id sdma_dt_ids[] = {
> > { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
> > { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
> > { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
> > + { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
> > { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
> > { /* sentinel */ }
> > };
> > @@ -1144,8 +1159,17 @@ static int sdma_config_channel(struct dma_chan
> *chan)
> > if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
> > sdmac->peripheral_type == IMX_DMATYPE_ASRC)
> > sdma_set_watermarklevel_for_p2p(sdmac);
> > - } else
> > + } else {
> > + /*
> > + * ERR009165 fixed from i.mx6ul, no errata need,
> > + * set bit31 to let sdma script skip the errata.
> > + */
> > + if (sdmac->peripheral_type == IMX_DMATYPE_CSPI &&
> > + sdmac->direction == DMA_MEM_TO_DEV &&
> > + sdmac->sdma->drvdata->ecspi_fixed)
> > + __set_bit(31, &sdmac->watermark_level);
>
> Hm, I don't care much either way, but couldn't we just return the regular
> mcu_2_app script in sdma_get_pc when ecspi_fixed == true? Seems like this
> would be a simpler and more targeted code change.
Yes, return mcu_2_app if ecspi_fixed == true also works, but since sdma firmware
have already been here to fix ERR009165 on most of legacy i.mx6/7/8 chips, so choosing
firmware/ram script to do like ROM/mcu_2_app is okay too since both ram script and rom
script in case of ecspi_fixed are almost same.
>
> > __set_bit(sdmac->event_id0, sdmac->event_mask);
> > + }
> >
> > /* Address */
> > sdmac->shp_addr = sdmac->per_address;
>
Am Montag, dem 12.07.2021 um 03:48 +0000 schrieb Robin Gong:
> On 09/07/21 17:42 Lucas Stach <[email protected]> wrote:
> > Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> > > ERR009165 fixed on i.mx6ul/6ull/6sll. All other i.mx6/7 and i.mx8m/8mm
> > > still need this errata. Please refer to nxp official errata document
> > > from
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.n
> > xp.com%2F&data=04%7C01%7Cyibin.gong%40nxp.com%7C48156bc93d
> > c84ac26e9d08d942bdc0ac%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> > 7C1%7C637614205017900475%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> > wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> > mp;sdata=keYQubzt1jWrKhaxXr40RL41vzFuIn7x1Sasa3p%2F9Xo%3D&res
> > erved=0 .
> > >
> > > For removing workaround on those chips. Add new i.mx6ul type.
> > >
> > > Signed-off-by: Robin Gong <[email protected]>
> > > Acked-by: Mark Brown <[email protected]>
> > > ---
> > > drivers/spi/spi-imx.c | 47
> > > +++++++++++++++++++++++++++++++++++++++++++----
> > > 1 file changed, 43 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > > cf235b9..d18ee25 100644
> > > --- a/drivers/spi/spi-imx.c
> > > +++ b/drivers/spi/spi-imx.c
> > > @@ -59,6 +59,7 @@ enum spi_imx_devtype {
> > > IMX35_CSPI, /* CSPI on all i.mx except above */
> > > IMX51_ECSPI, /* ECSPI on i.mx51 */
> > > IMX53_ECSPI, /* ECSPI on i.mx53 and later */
> > > + IMX6UL_ECSPI, /* ERR009165 fix from i.mx6ul */
> >
> > This patch could be a lot smaller if you didn't introduce a new devtype. You
> > could just use the IMX51_ECSPI in imx6ul_ecspi_devtype_data, as all you care
> > about as a relevant difference is the tx_glitch_fixed property, which isn't tied
> > to the devtype.
> I knew tx_glitch_fixed was enough but I still prefer to add new 'IMX6UL_ECSPI' because
> we can clearly choose the right IP which has fix the issue while legacy IMX51 if it's not
> fixed by dts.
>
Sorry, I don't follow this reasoning. You are not using the new
IMX6UL_ECSPI devtype in any way in this patch, other than a single
location, where you just handle it the same as the IMX51_ECSPI devtype.
Regards,
Lucas
>
>
> > > };
> > >
> > > struct spi_imx_data;
> > > @@ -78,6 +79,11 @@ struct spi_imx_devtype_data {
> > > bool has_slavemode;
> > > unsigned int fifo_size;
> > > bool dynamic_burst;
> > > + /*
> > > + * ERR009165 fixed or not:
> > > + *
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.n
> > xp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=04%7C01%7C
> > yibin.gong%40nxp.com%7C48156bc93dc84ac26e9d08d942bdc0ac%7C686ea
> > 1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637614205017900475%7CU
> > nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6
> > Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=J9iZb93uN1VEriN%2F2GAE
> > TWxdv4n%2FD6ZXteMCFkB8KHM%3D&reserved=0
> > > + */
> > > + bool tx_glitch_fixed;
> > > enum spi_imx_devtype devtype;
> > > };
> > >
> > > @@ -134,6 +140,11 @@ static inline int is_imx51_ecspi(struct spi_imx_data
> > *d)
> > > return d->devtype_data->devtype == IMX51_ECSPI; }
> > >
> > > +static inline int is_imx6ul_ecspi(struct spi_imx_data *d) {
> > > + return d->devtype_data->devtype == IMX6UL_ECSPI; }
> > > +
> > > static inline int is_imx53_ecspi(struct spi_imx_data *d) {
> > > return d->devtype_data->devtype == IMX53_ECSPI; @@ -593,8 +604,14
> > @@
> > > static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
> > > ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> > > spi_imx->spi_bus_clk = clk;
> > >
> > > - /* ERR009165: work in XHC mode as PIO */
> > > - ctrl &= ~MX51_ECSPI_CTRL_SMC;
> > > + /*
> > > + * ERR009165: work in XHC mode instead of SMC as PIO on the chips
> > > + * before i.mx6ul.
> > > + */
> > > + if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
> > > + ctrl |= MX51_ECSPI_CTRL_SMC;
> > > + else
> > > + ctrl &= ~MX51_ECSPI_CTRL_SMC;
> > >
> > > writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
> > >
> > > @@ -620,12 +637,16 @@ static int mx51_ecspi_prepare_transfer(struct
> > > spi_imx_data *spi_imx,
> > >
> > > static void mx51_setup_wml(struct spi_imx_data *spi_imx) {
> > > + u32 tx_wml = 0;
> > > +
> > > + if (spi_imx->devtype_data->tx_glitch_fixed)
> > > + tx_wml = spi_imx->wml;
> > > /*
> > > * Configure the DMA register: setup the watermark
> > > * and enable DMA request.
> > > */
> > > writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> > > - MX51_ECSPI_DMA_TX_WML(0) |
> > > + MX51_ECSPI_DMA_TX_WML(tx_wml) |
> > > MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> > > MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> > > MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
> > @@ -1019,6
> > > +1040,23 @@ static struct spi_imx_devtype_data
> > imx53_ecspi_devtype_data = {
> > > .devtype = IMX53_ECSPI,
> > > };
> > >
> > > +static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
> > > + .intctrl = mx51_ecspi_intctrl,
> > > + .prepare_message = mx51_ecspi_prepare_message,
> > > + .prepare_transfer = mx51_ecspi_prepare_transfer,
> > > + .trigger = mx51_ecspi_trigger,
> > > + .rx_available = mx51_ecspi_rx_available,
> > > + .reset = mx51_ecspi_reset,
> > > + .setup_wml = mx51_setup_wml,
> > > + .fifo_size = 64,
> > > + .has_dmamode = true,
> > > + .dynamic_burst = true,
> > > + .has_slavemode = true,
> > > + .tx_glitch_fixed = true,
> > > + .disable = mx51_ecspi_disable,
> > > + .devtype = IMX6UL_ECSPI,
> > > +};
> > > +
> > > static const struct of_device_id spi_imx_dt_ids[] = {
> > > { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
> > > { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data,
> > > }, @@ -1027,6 +1065,7 @@ static const struct of_device_id spi_imx_dt_ids[]
> > = {
> > > { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
> > > { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
> > > { .compatible = "fsl,imx53-ecspi", .data =
> > > &imx53_ecspi_devtype_data, },
> > > + { .compatible = "fsl,imx6ul-ecspi", .data =
> > > +&imx6ul_ecspi_devtype_data, },
> > > { /* sentinel */ }
> > > };
> > > MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); @@ -1604,7 +1643,7 @@
> > static
> > > int spi_imx_probe(struct platform_device *pdev)
> > > spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA |
> > SPI_CS_HIGH \
> > > | SPI_NO_CS;
> > > if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
> > > - is_imx53_ecspi(spi_imx))
> > > + is_imx53_ecspi(spi_imx) || is_imx6ul_ecspi(spi_imx))
> > > spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
> > >
> > > spi_imx->spi_drctl = spi_drctl;
> >
>
Am Montag, dem 12.07.2021 um 04:03 +0000 schrieb Robin Gong:
> On 09/07/21 17:45 Lucas Stach <[email protected]> wrote:
> > Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> > > ECSPI issue fixed from i.mx6ul at hardware level, no need
> > > ERR009165 anymore on those chips such as i.mx8mq.
> > >
> > > Signed-off-by: Robin Gong <[email protected]>
> > > Acked-by: Vinod Koul <[email protected]>
> > > ---
> > > drivers/dma/imx-sdma.c | 26 +++++++++++++++++++++++++-
> > > 1 file changed, 25 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index
> > > 86bd383..af85116 100644
> > > --- a/drivers/dma/imx-sdma.c
> > > +++ b/drivers/dma/imx-sdma.c
> > > @@ -422,6 +422,13 @@ struct sdma_driver_data {
> > > int num_events;
> > > struct sdma_script_start_addrs *script_addrs;
> > > bool check_ratio;
> > > + /*
> > > + * ecspi ERR009165 fixed should be done in sdma script
> > > + * and it has been fixed in soc from i.mx6ul.
> > > + * please get more information from the below link:
> > > + *
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.n
> > xp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=04%7C01%7C
> > yibin.gong%40nxp.com%7Cc950b1bdb6544eda369408d942be35d9%7C686ea
> > 1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637614206980361737%7CU
> > nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6
> > Ik1haWwiLCJXVCI6Mn0%3D%7C2000&sdata=6iT6%2FbzJHyWnkhkDynY
> > wmK9nn2hgCDy1GyzELeEk9K8%3D&reserved=0
> > > + */
> > > + bool ecspi_fixed;
> > > };
> > >
> > > struct sdma_engine {
> > > @@ -542,6 +549,13 @@ static struct sdma_driver_data sdma_imx6q = {
> > > .script_addrs = &sdma_script_imx6q,
> > > };
> > >
> > > +static struct sdma_driver_data sdma_imx6ul = {
> > > + .chnenbl0 = SDMA_CHNENBL0_IMX35,
> > > + .num_events = 48,
> > > + .script_addrs = &sdma_script_imx6q,
> > > + .ecspi_fixed = true,
> > > +};
> > > +
> > > static struct sdma_script_start_addrs sdma_script_imx7d = {
> > > .ap_2_ap_addr = 644,
> > > .uart_2_mcu_addr = 819,
> > > @@ -575,6 +589,7 @@ static const struct of_device_id sdma_dt_ids[] = {
> > > { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
> > > { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
> > > { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
> > > + { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
> > > { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
> > > { /* sentinel */ }
> > > };
> > > @@ -1144,8 +1159,17 @@ static int sdma_config_channel(struct dma_chan
> > *chan)
> > > if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
> > > sdmac->peripheral_type == IMX_DMATYPE_ASRC)
> > > sdma_set_watermarklevel_for_p2p(sdmac);
> > > - } else
> > > + } else {
> > > + /*
> > > + * ERR009165 fixed from i.mx6ul, no errata need,
> > > + * set bit31 to let sdma script skip the errata.
> > > + */
> > > + if (sdmac->peripheral_type == IMX_DMATYPE_CSPI &&
> > > + sdmac->direction == DMA_MEM_TO_DEV &&
> > > + sdmac->sdma->drvdata->ecspi_fixed)
> > > + __set_bit(31, &sdmac->watermark_level);
> >
> > Hm, I don't care much either way, but couldn't we just return the regular
> > mcu_2_app script in sdma_get_pc when ecspi_fixed == true? Seems like this
> > would be a simpler and more targeted code change.
> Yes, return mcu_2_app if ecspi_fixed == true also works, but since sdma firmware
> have already been here to fix ERR009165 on most of legacy i.mx6/7/8 chips, so choosing
> firmware/ram script to do like ROM/mcu_2_app is okay too since both ram script and rom
> script in case of ecspi_fixed are almost same.
>
Actually, while thinking some more about this: it is preferable to
return mcu_2_app in the ecspi_fixed case, as this allows proper DMA
support on the fixed SoCs without loading the firmware. The way you do
it here still requires the RAM firmware to be loaded in order to get
DMA support at all.
Regards,
Lucas
> >
> > > __set_bit(sdmac->event_id0, sdmac->event_mask);
> > > + }
> > >
> > > /* Address */
> > > sdmac->shp_addr = sdmac->per_address;
> >
>
On 12/07/21 17:31 Lucas Stach <[email protected]> wrote:
> Am Montag, dem 12.07.2021 um 03:48 +0000 schrieb Robin Gong:
> > On 09/07/21 17:42 Lucas Stach <[email protected]> wrote:
> > > Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> > > > ERR009165 fixed on i.mx6ul/6ull/6sll. All other i.mx6/7 and
> > > > i.mx8m/8mm still need this errata. Please refer to nxp official
> > > > errata document from
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fww
> > > w.n
> xp.com%2F&data=04%7C01%7Cyibin.gong%40nxp.com%7C48156bc93d
> > >
> c84ac26e9d08d942bdc0ac%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> > >
> 7C1%7C637614205017900475%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> > >
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> > >
> mp;sdata=keYQubzt1jWrKhaxXr40RL41vzFuIn7x1Sasa3p%2F9Xo%3D&res
> > > erved=0 .
> > > >
> > > > For removing workaround on those chips. Add new i.mx6ul type.
> > > >
> > > > Signed-off-by: Robin Gong <[email protected]>
> > > > Acked-by: Mark Brown <[email protected]>
> > > > ---
> > > > drivers/spi/spi-imx.c | 47
> > > > +++++++++++++++++++++++++++++++++++++++++++----
> > > > 1 file changed, 43 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > > > cf235b9..d18ee25 100644
> > > > --- a/drivers/spi/spi-imx.c
> > > > +++ b/drivers/spi/spi-imx.c
> > > > @@ -59,6 +59,7 @@ enum spi_imx_devtype {
> > > > IMX35_CSPI, /* CSPI on all i.mx except above */
> > > > IMX51_ECSPI, /* ECSPI on i.mx51 */
> > > > IMX53_ECSPI, /* ECSPI on i.mx53 and later */
> > > > + IMX6UL_ECSPI, /* ERR009165 fix from i.mx6ul */
> > >
> > > This patch could be a lot smaller if you didn't introduce a new
> > > devtype. You could just use the IMX51_ECSPI in
> > > imx6ul_ecspi_devtype_data, as all you care about as a relevant
> > > difference is the tx_glitch_fixed property, which isn't tied to the devtype.
> > I knew tx_glitch_fixed was enough but I still prefer to add new
> > 'IMX6UL_ECSPI' because we can clearly choose the right IP which has
> > fix the issue while legacy IMX51 if it's not fixed by dts.
> >
> Sorry, I don't follow this reasoning. You are not using the new IMX6UL_ECSPI
> devtype in any way in this patch, other than a single location, where you just
> handle it the same as the IMX51_ECSPI devtype.
Okay, will reuse IMX51_ECSPI as devtype, but will still keep "fsl,imx6ul-ecspi".
>
> >
> >
> > > > };
> > > >
> > > > struct spi_imx_data;
> > > > @@ -78,6 +79,11 @@ struct spi_imx_devtype_data {
> > > > bool has_slavemode;
> > > > unsigned int fifo_size;
> > > > bool dynamic_burst;
> > > > + /*
> > > > + * ERR009165 fixed or not:
> > > > + *
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fww
> > > w.n
> xp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=04%7C01%7C
> > >
> yibin.gong%40nxp.com%7C48156bc93dc84ac26e9d08d942bdc0ac%7C686ea
> > >
> 1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637614205017900475%7CU
> > >
> nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6
> > >
> Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=J9iZb93uN1VEriN%2F2GAE
> > > TWxdv4n%2FD6ZXteMCFkB8KHM%3D&reserved=0
> > > > + */
> > > > + bool tx_glitch_fixed;
> > > > enum spi_imx_devtype devtype;
> > > > };
> > > >
> > > > @@ -134,6 +140,11 @@ static inline int is_imx51_ecspi(struct
> > > > spi_imx_data
> > > *d)
> > > > return d->devtype_data->devtype == IMX51_ECSPI; }
> > > >
> > > > +static inline int is_imx6ul_ecspi(struct spi_imx_data *d) {
> > > > + return d->devtype_data->devtype == IMX6UL_ECSPI; }
> > > > +
> > > > static inline int is_imx53_ecspi(struct spi_imx_data *d) {
> > > > return d->devtype_data->devtype == IMX53_ECSPI; @@ -593,8
> > > > +604,14
> > > @@
> > > > static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
> > > > ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
> > > > spi_imx->spi_bus_clk = clk;
> > > >
> > > > - /* ERR009165: work in XHC mode as PIO */
> > > > - ctrl &= ~MX51_ECSPI_CTRL_SMC;
> > > > + /*
> > > > + * ERR009165: work in XHC mode instead of SMC as PIO on the
> chips
> > > > + * before i.mx6ul.
> > > > + */
> > > > + if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
> > > > + ctrl |= MX51_ECSPI_CTRL_SMC;
> > > > + else
> > > > + ctrl &= ~MX51_ECSPI_CTRL_SMC;
> > > >
> > > > writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
> > > >
> > > > @@ -620,12 +637,16 @@ static int
> > > > mx51_ecspi_prepare_transfer(struct
> > > > spi_imx_data *spi_imx,
> > > >
> > > > static void mx51_setup_wml(struct spi_imx_data *spi_imx) {
> > > > + u32 tx_wml = 0;
> > > > +
> > > > + if (spi_imx->devtype_data->tx_glitch_fixed)
> > > > + tx_wml = spi_imx->wml;
> > > > /*
> > > > * Configure the DMA register: setup the watermark
> > > > * and enable DMA request.
> > > > */
> > > > writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
> > > > - MX51_ECSPI_DMA_TX_WML(0) |
> > > > + MX51_ECSPI_DMA_TX_WML(tx_wml) |
> > > > MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
> > > > MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
> > > > MX51_ECSPI_DMA_RXTDEN, spi_imx->base +
> MX51_ECSPI_DMA);
> > > @@ -1019,6
> > > > +1040,23 @@ static struct spi_imx_devtype_data
> > > imx53_ecspi_devtype_data = {
> > > > .devtype = IMX53_ECSPI,
> > > > };
> > > >
> > > > +static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
> > > > + .intctrl = mx51_ecspi_intctrl,
> > > > + .prepare_message = mx51_ecspi_prepare_message,
> > > > + .prepare_transfer = mx51_ecspi_prepare_transfer,
> > > > + .trigger = mx51_ecspi_trigger,
> > > > + .rx_available = mx51_ecspi_rx_available,
> > > > + .reset = mx51_ecspi_reset,
> > > > + .setup_wml = mx51_setup_wml,
> > > > + .fifo_size = 64,
> > > > + .has_dmamode = true,
> > > > + .dynamic_burst = true,
> > > > + .has_slavemode = true,
> > > > + .tx_glitch_fixed = true,
> > > > + .disable = mx51_ecspi_disable,
> > > > + .devtype = IMX6UL_ECSPI,
> > > > +};
> > > > +
> > > > static const struct of_device_id spi_imx_dt_ids[] = {
> > > > { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
> > > > { .compatible = "fsl,imx21-cspi", .data =
> > > > &imx21_cspi_devtype_data, }, @@ -1027,6 +1065,7 @@ static const
> > > > struct of_device_id spi_imx_dt_ids[]
> > > = {
> > > > { .compatible = "fsl,imx35-cspi", .data =
> &imx35_cspi_devtype_data, },
> > > > { .compatible = "fsl,imx51-ecspi", .data =
> &imx51_ecspi_devtype_data, },
> > > > { .compatible = "fsl,imx53-ecspi", .data =
> > > > &imx53_ecspi_devtype_data, },
> > > > + { .compatible = "fsl,imx6ul-ecspi", .data =
> > > > +&imx6ul_ecspi_devtype_data, },
> > > > { /* sentinel */ }
> > > > };
> > > > MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); @@ -1604,7 +1643,7
> @@
> > > static
> > > > int spi_imx_probe(struct platform_device *pdev)
> > > > spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA |
> > > SPI_CS_HIGH \
> > > > | SPI_NO_CS;
> > > > if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
> > > > - is_imx53_ecspi(spi_imx))
> > > > + is_imx53_ecspi(spi_imx) || is_imx6ul_ecspi(spi_imx))
> > > > spi_imx->bitbang.master->mode_bits |= SPI_LOOP |
> SPI_READY;
> > > >
> > > > spi_imx->spi_drctl = spi_drctl;
> > >
> >
>
On 12/07/21 17:33 Lucas Stach <[email protected]> wrote:
> Am Montag, dem 12.07.2021 um 04:03 +0000 schrieb Robin Gong:
> > On 09/07/21 17:45 Lucas Stach <[email protected]> wrote:
> > > Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> > > > ECSPI issue fixed from i.mx6ul at hardware level, no need
> > > > ERR009165 anymore on those chips such as i.mx8mq.
> > > >
> > > > Signed-off-by: Robin Gong <[email protected]>
> > > > Acked-by: Vinod Koul <[email protected]>
> > > > ---
> > > > drivers/dma/imx-sdma.c | 26 +++++++++++++++++++++++++-
> > > > 1 file changed, 25 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index
> > > > 86bd383..af85116 100644
> > > > --- a/drivers/dma/imx-sdma.c
> > > > +++ b/drivers/dma/imx-sdma.c
> > > > @@ -422,6 +422,13 @@ struct sdma_driver_data {
> > > > int num_events;
> > > > struct sdma_script_start_addrs *script_addrs;
> > > > bool check_ratio;
> > > > + /*
> > > > + * ecspi ERR009165 fixed should be done in sdma script
> > > > + * and it has been fixed in soc from i.mx6ul.
> > > > + * please get more information from the below link:
> > > > + *
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fww
> > > w.n
> xp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=04%7C01%7C
> > >
> yibin.gong%40nxp.com%7Cc950b1bdb6544eda369408d942be35d9%7C686ea
> > >
> 1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637614206980361737%7CU
> > >
> nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6
> > >
> Ik1haWwiLCJXVCI6Mn0%3D%7C2000&sdata=6iT6%2FbzJHyWnkhkDynY
> > > wmK9nn2hgCDy1GyzELeEk9K8%3D&reserved=0
> > > > + */
> > > > + bool ecspi_fixed;
> > > > };
> > > >
> > > > struct sdma_engine {
> > > > @@ -542,6 +549,13 @@ static struct sdma_driver_data sdma_imx6q = {
> > > > .script_addrs = &sdma_script_imx6q, };
> > > >
> > > > +static struct sdma_driver_data sdma_imx6ul = {
> > > > + .chnenbl0 = SDMA_CHNENBL0_IMX35,
> > > > + .num_events = 48,
> > > > + .script_addrs = &sdma_script_imx6q,
> > > > + .ecspi_fixed = true,
> > > > +};
> > > > +
> > > > static struct sdma_script_start_addrs sdma_script_imx7d = {
> > > > .ap_2_ap_addr = 644,
> > > > .uart_2_mcu_addr = 819,
> > > > @@ -575,6 +589,7 @@ static const struct of_device_id sdma_dt_ids[] = {
> > > > { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
> > > > { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
> > > > { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
> > > > + { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
> > > > { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
> > > > { /* sentinel */ }
> > > > };
> > > > @@ -1144,8 +1159,17 @@ static int sdma_config_channel(struct
> > > > dma_chan
> > > *chan)
> > > > if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
> > > > sdmac->peripheral_type == IMX_DMATYPE_ASRC)
> > > > sdma_set_watermarklevel_for_p2p(sdmac);
> > > > - } else
> > > > + } else {
> > > > + /*
> > > > + * ERR009165 fixed from i.mx6ul, no errata need,
> > > > + * set bit31 to let sdma script skip the errata.
> > > > + */
> > > > + if (sdmac->peripheral_type == IMX_DMATYPE_CSPI &&
> > > > + sdmac->direction == DMA_MEM_TO_DEV &&
> > > > + sdmac->sdma->drvdata->ecspi_fixed)
> > > > + __set_bit(31, &sdmac->watermark_level);
> > >
> > > Hm, I don't care much either way, but couldn't we just return the
> > > regular mcu_2_app script in sdma_get_pc when ecspi_fixed == true?
> > > Seems like this would be a simpler and more targeted code change.
> > Yes, return mcu_2_app if ecspi_fixed == true also works, but since
> > sdma firmware have already been here to fix ERR009165 on most of
> > legacy i.mx6/7/8 chips, so choosing firmware/ram script to do like
> > ROM/mcu_2_app is okay too since both ram script and rom script in case of
> ecspi_fixed are almost same.
> >
> Actually, while thinking some more about this: it is preferable to return
> mcu_2_app in the ecspi_fixed case, as this allows proper DMA support on the
> fixed SoCs without loading the firmware. The way you do it here still requires
> the RAM firmware to be loaded in order to get DMA support at all.
Okay, will change to mcu_2_app v15.
>
>
> > >
> > > > __set_bit(sdmac->event_id0, sdmac->event_mask);
> > > > + }
> > > >
> > > > /* Address */
> > > > sdmac->shp_addr = sdmac->per_address;
> > >
> >
>
Am Dienstag, dem 13.07.2021 um 09:12 +0000 schrieb Robin Gong:
> On 12/07/21 17:31 Lucas Stach <[email protected]> wrote:
> > Am Montag, dem 12.07.2021 um 03:48 +0000 schrieb Robin Gong:
> > > On 09/07/21 17:42 Lucas Stach <[email protected]> wrote:
> > > > Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> > > > > ERR009165 fixed on i.mx6ul/6ull/6sll. All other i.mx6/7 and
> > > > > i.mx8m/8mm still need this errata. Please refer to nxp official
> > > > > errata document from
> > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fww
> > > > w.n
> > xp.com%2F&data=04%7C01%7Cyibin.gong%40nxp.com%7C48156bc93d
> > > >
> > c84ac26e9d08d942bdc0ac%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> > > >
> > 7C1%7C637614205017900475%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> > > >
> > wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> > > >
> > mp;sdata=keYQubzt1jWrKhaxXr40RL41vzFuIn7x1Sasa3p%2F9Xo%3D&res
> > > > erved=0 .
> > > > >
> > > > > For removing workaround on those chips. Add new i.mx6ul type.
> > > > >
> > > > > Signed-off-by: Robin Gong <[email protected]>
> > > > > Acked-by: Mark Brown <[email protected]>
> > > > > ---
> > > > > drivers/spi/spi-imx.c | 47
> > > > > +++++++++++++++++++++++++++++++++++++++++++----
> > > > > 1 file changed, 43 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index
> > > > > cf235b9..d18ee25 100644
> > > > > --- a/drivers/spi/spi-imx.c
> > > > > +++ b/drivers/spi/spi-imx.c
> > > > > @@ -59,6 +59,7 @@ enum spi_imx_devtype {
> > > > > IMX35_CSPI, /* CSPI on all i.mx except above */
> > > > > IMX51_ECSPI, /* ECSPI on i.mx51 */
> > > > > IMX53_ECSPI, /* ECSPI on i.mx53 and later */
> > > > > + IMX6UL_ECSPI, /* ERR009165 fix from i.mx6ul */
> > > >
> > > > This patch could be a lot smaller if you didn't introduce a new
> > > > devtype. You could just use the IMX51_ECSPI in
> > > > imx6ul_ecspi_devtype_data, as all you care about as a relevant
> > > > difference is the tx_glitch_fixed property, which isn't tied to the devtype.
> > > I knew tx_glitch_fixed was enough but I still prefer to add new
> > > 'IMX6UL_ECSPI' because we can clearly choose the right IP which has
> > > fix the issue while legacy IMX51 if it's not fixed by dts.
> > >
> > Sorry, I don't follow this reasoning. You are not using the new IMX6UL_ECSPI
> > devtype in any way in this patch, other than a single location, where you just
> > handle it the same as the IMX51_ECSPI devtype.
> Okay, will reuse IMX51_ECSPI as devtype, but will still keep "fsl,imx6ul-ecspi".
>
That's exactly what I meant: have a "fsl,imx6ul-ecspi" compatible with
it's own imx6ul_ecspi_devtype_data, but reuse the IMX51_ECSPI devtype.
Glad we are on the same page now.
Regards,
Lucas