by kernel test robot

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Subject: Re: [PATCH v6 4/9] counter: 104-quad-8: Add Generic Counter interface support

2018-05-19 13:56:40

by William Breathitt Gray

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Subject: Re: [PATCH v6 4/9] counter: 104-quad-8: Add Generic Counter interface support

On Sat, May 19, 2018 at 09:16:55PM +0800, kbuild test robot wrote:
>Hi William,
>
>I love your patch! Perhaps something to improve:
>
>[auto build test WARNING on linus/master]
>[also build test WARNING on v4.17-rc5 next-20180517]
>[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
>url: https://github.com/0day-ci/linux/commits/William-Breathitt-Gray/Introduce-the-Counter-subsystem/20180519-151353
>reproduce:
> # apt-get install sparse
> make ARCH=x86_64 allmodconfig
> make C=1 CF=-D__CHECK_ENDIAN__
>
>
>sparse warnings: (new ones prefixed by >>)
>
>>> drivers/counter/104-quad-8.c:803:26: sparse: symbol 'quad8_ops' was not declared. Should it be static?
>
>Please review and possibly fold the followup patch.

Ah, yes it should be static -- looks like I made a minor mistake. I'll
squash the fix into the next revision of this patchset.

Thank you,

William Breathitt Gray

>
>---
>0-DAY kernel test infrastructure Open Source Technology Center
>https://lists.01.org/pipermail/kbuild-all Intel Corporation

2018-05-19 15:32:12

2018-05-18 18:28 GMT+02:00 Rob Herring <[email protected]>:
> On Thu, May 17, 2018 at 08:59:40PM +0200, Benjamin Gaignard wrote:
>> 2018-05-17 18:23 GMT+02:00 Rob Herring <[email protected]>:
>> > On Wed, May 16, 2018 at 12:51 PM, William Breathitt Gray
>> > <[email protected]> wrote:
>> >> From: Benjamin Gaignard <[email protected]>
>> >
>> > v6? Where's v1-v5?
>> >
>> >> Add bindings for STM32 Timer quadrature encoder.
>> >> It is a sub-node of STM32 Timer which implement the
>> >> counter part of the hardware.
>> >>
>> >> Cc: Rob Herring <[email protected]>
>> >> Cc: Mark Rutland <[email protected]>
>> >> Signed-off-by: Benjamin Gaignard <[email protected]>
>> >> Signed-off-by: William Breathitt Gray <[email protected]>
>> >> ---
>> >> .../bindings/counter/stm32-timer-cnt.txt | 26 +++++++++++++++++++
>> >> .../devicetree/bindings/mfd/stm32-timers.txt | 7 +++++
>> >> 2 files changed, 33 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt
>> >> new file mode 100644
>> >> index 000000000000..377728128bef
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt
>> >> @@ -0,0 +1,26 @@
>> >> +STMicroelectronics STM32 Timer quadrature encoder
>> >> +
>> >> +STM32 Timer provides quadrature encoder counter mode to detect
>> >
>> > 'mode' does not sound like a sub-block of the timers block.
>>
>> quadrature encoding is one of the counting modes of this hardware
>> block which is enable to count on other signals/triggers
>
> You don't need a child node and compatible to set a mode.

"mode" isn't the good word here because quadratic encoder enable a
sub-block of this hardware.
Timer internal counter input could be internal or external clocks,
some IIO triggers
or the output of the quadratic encoder sub-block.
It is a child like pwm or IIO trigger.

>
>> >> +angular position and direction of rotary elements,
>> >> +from IN1 and IN2 input signals.
>> >> +
>> >> +Must be a sub-node of an STM32 Timer device tree node.
>> >> +See ../mfd/stm32-timers.txt for details about the parent node.
>> >> +
>> >> +Required properties:
>> >> +- compatible: Must be "st,stm32-timer-counter".
>> >> +- pinctrl-names: Set to "default".
>> >> +- pinctrl-0: List of phandles pointing to pin configuration nodes,
>> >> + to set IN1/IN2 pins in mode of operation for Low-Power
>> >> + Timer input on external pin.
>> >> +
>> >> +Example:
>> >> + timers@40010000 {
>> >> + compatible = "st,stm32-timers";
>> >> + ...
>> >> + counter {
>> >> + compatible = "st,stm32-timer-counter";
>> >
>> > Is there only 1? How is the counter addressed?
>>
>> Yes there is only one counter per hardware block.
>> Counter is addressed like the two others sub-nodes and the details
>> about parent mode are describe in stm32-timers.txt
>> Should I add them here too ? so example will be like that:
>
> No, you should drop the child node and add pinctrl to the parent.
>
> Any other functions this block has that you plan on adding? Please make
> bindings as complete as possible, not what you currently have drivers
> for.

Counter framework didn't exist when I pushed timer node but thanks to
William's effort
it will allow us to use this kindf of hardware

Benjamin

>
>> timers@40010000 {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> compatible = "st,stm32-timers";
>> reg = <0x40010000 0x400>;
>> clocks = <&rcc 0 160>;
>> clock-names = "int";
>> counter {
>> compatible = "st,stm32-timer-counter";
>> pinctrl-names = "default";
>> pinctrl-0 = <&tim1_in_pins>;
>> };
>> };
>>
>> Benjamin
>> >
>> > _______________________________________________
>> > linux-arm-kernel mailing list
>> > [email protected]
>> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

--
Benjamin Gaignard

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