Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by Scan at Field (SAF).
Unlike SAF, Array BIST doesn't require any test content to be loaded.
Jithu Joseph (5):
x86/include/asm/msr-index.h: Add IFS Array test bits
platform/x86/intel/ifs: Introduce Array Scan test to IFS
platform/x86/intel/ifs: Sysfs interface for Array BIST
platform/x86/intel/ifs: Implement Array BIST test
platform/x86/intel/ifs: Trace support for array test
arch/x86/include/asm/msr-index.h | 2 +
drivers/platform/x86/intel/ifs/ifs.h | 18 ++++
include/trace/events/intel_ifs.h | 27 ++++++
drivers/platform/x86/intel/ifs/core.c | 82 ++++++++++++------
drivers/platform/x86/intel/ifs/runtest.c | 104 ++++++++++++++++++++++-
drivers/platform/x86/intel/ifs/sysfs.c | 17 +++-
6 files changed, 223 insertions(+), 27 deletions(-)
base-commit: 6d796c50f84ca79f1722bb131799e5a5710c4700
--
2.25.1
Define MSR bitfields for enumerating support for Array BIST test.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
arch/x86/include/asm/msr-index.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index d3fe82c5d6b6..ad8997773ad3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -197,6 +197,8 @@
/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
#define MSR_INTEGRITY_CAPS 0x000002d9
+#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2
+#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
--
2.25.1
Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by the first test type
i.e Scan at Field (SAF).
Make changes in the device driver init flow to register this new test
type with the device driver framework. Each test will have its own
sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
accommodate for the differences in test type and how they are initiated.
Upcoming patches will add actual support.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 5 ++
drivers/platform/x86/intel/ifs/core.c | 70 ++++++++++++++++++---------
2 files changed, 52 insertions(+), 23 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 046e39304fd5..2cef88a88aa9 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -137,6 +137,11 @@
#define SCAN_TEST_PASS 1
#define SCAN_TEST_FAIL 2
+enum test_types {
+ IFS_SAF,
+ IFS_ARRAY,
+};
+
/* MSR_SCAN_HASHES_STATUS bit fields */
union ifs_scan_hashes_status {
u64 data;
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 206a617c2e02..ab234620ef4c 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -16,27 +16,44 @@
static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
X86_MATCH(SAPPHIRERAPIDS_X),
+ X86_MATCH(EMERALDRAPIDS_X),
{}
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
-static struct ifs_device ifs_device = {
- .data = {
- .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
- .test_num = 0,
+static struct ifs_device ifs_devices[] = {
+ [IFS_SAF] = {
+ .data = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
+ .test_num = IFS_SAF,
+ },
+ .misc = {
+ .name = "intel_ifs_0",
+ .nodename = "intel_ifs/0",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
- .misc = {
- .name = "intel_ifs_0",
- .nodename = "intel_ifs/0",
- .minor = MISC_DYNAMIC_MINOR,
+ [IFS_ARRAY] = {
+ .data = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
+ .test_num = IFS_ARRAY,
+ },
+ .misc = {
+ .name = "intel_ifs_1",
+ .nodename = "intel_ifs/1",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
};
+#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
+
static int __init ifs_init(void)
{
const struct x86_cpu_id *m;
+ int ndevices = 0;
u64 msrval;
- int ret;
+ int i;
m = x86_match_cpu(ifs_cpu_ids);
if (!m)
@@ -51,28 +68,35 @@ static int __init ifs_init(void)
if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
return -ENODEV;
- ifs_device.misc.groups = ifs_get_groups();
-
- if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
- return -ENODEV;
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit)))
+ continue;
- ifs_device.data.pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
- if (!ifs_device.data.pkg_auth)
- return -ENOMEM;
+ ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
+ sizeof(bool), GFP_KERNEL);
+ if (!ifs_devices[i].data.pkg_auth)
+ continue;
+ ifs_devices[i].misc.groups = ifs_get_groups();
- ret = misc_register(&ifs_device.misc);
- if (ret) {
- kfree(ifs_device.data.pkg_auth);
- return ret;
+ if (misc_register(&ifs_devices[i].misc))
+ kfree(ifs_devices[i].data.pkg_auth);
+ else
+ ndevices++;
}
- return 0;
+ return ndevices ? 0 : -ENODEV;
}
static void __exit ifs_exit(void)
{
- misc_deregister(&ifs_device.misc);
- kfree(ifs_device.data.pkg_auth);
+ int i;
+
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (ifs_devices[i].misc.this_device) {
+ misc_deregister(&ifs_devices[i].misc);
+ kfree(ifs_devices[i].data.pkg_auth);
+ }
+ }
}
module_init(ifs_init);
--
2.25.1
The interface to trigger Array BIST test and obtain its result
is similar to the existing scan test. The only notable
difference is that, Array BIST doesn't require any test content
to be loaded. So binary load related options are not needed for
this test.
Add sysfs interface array BIST test, the testing support will
be added by subsequent patch.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 1 +
drivers/platform/x86/intel/ifs/core.c | 18 +++++++++++++-----
drivers/platform/x86/intel/ifs/runtest.c | 11 ++++++++++-
drivers/platform/x86/intel/ifs/sysfs.c | 17 ++++++++++++++++-
4 files changed, 40 insertions(+), 7 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 2cef88a88aa9..07423bc4e368 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -249,5 +249,6 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
int ifs_load_firmware(struct device *dev);
int do_core_test(int cpu, struct device *dev);
const struct attribute_group **ifs_get_groups(void);
+const struct attribute_group **ifs_get_array_groups(void);
#endif
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index ab234620ef4c..2b7a49fd473d 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -25,6 +25,7 @@ static struct ifs_device ifs_devices[] = {
[IFS_SAF] = {
.data = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
+ .pkg_auth = NULL,
.test_num = IFS_SAF,
},
.misc = {
@@ -36,6 +37,7 @@ static struct ifs_device ifs_devices[] = {
[IFS_ARRAY] = {
.data = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
+ .pkg_auth = NULL,
.test_num = IFS_ARRAY,
},
.misc = {
@@ -72,11 +74,17 @@ static int __init ifs_init(void)
if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit)))
continue;
- ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
- sizeof(bool), GFP_KERNEL);
- if (!ifs_devices[i].data.pkg_auth)
- continue;
- ifs_devices[i].misc.groups = ifs_get_groups();
+ switch (ifs_devices[i].data.test_num) {
+ case IFS_SAF:
+ ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
+ sizeof(bool), GFP_KERNEL);
+ if (!ifs_devices[i].data.pkg_auth)
+ continue;
+ ifs_devices[i].misc.groups = ifs_get_groups();
+ break;
+ case IFS_ARRAY:
+ ifs_devices[i].misc.groups = ifs_get_array_groups();
+ }
if (misc_register(&ifs_devices[i].misc))
kfree(ifs_devices[i].data.pkg_auth);
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 0bfd8fcdd7e8..65e08af70994 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -236,6 +236,7 @@ static void ifs_test_core(int cpu, struct device *dev)
*/
int do_core_test(int cpu, struct device *dev)
{
+ struct ifs_data *ifsd = ifs_get_data(dev);
int ret = 0;
/* Prevent CPUs from being taken offline during the scan test */
@@ -247,7 +248,15 @@ int do_core_test(int cpu, struct device *dev)
goto out;
}
- ifs_test_core(cpu, dev);
+ switch (ifsd->test_num) {
+ case IFS_SAF:
+ ifs_test_core(cpu, dev);
+ break;
+ case IFS_ARRAY:
+ default:
+ return -EINVAL;
+ }
+
out:
cpus_read_unlock();
return ret;
diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
index ee636a76b083..7cf32184ce6a 100644
--- a/drivers/platform/x86/intel/ifs/sysfs.c
+++ b/drivers/platform/x86/intel/ifs/sysfs.c
@@ -75,7 +75,7 @@ static ssize_t run_test_store(struct device *dev,
if (down_interruptible(&ifs_sem))
return -EINTR;
- if (!ifsd->loaded)
+ if (ifsd->test_num != IFS_ARRAY && !ifsd->loaded)
rc = -EPERM;
else
rc = do_core_test(cpu, dev);
@@ -156,3 +156,18 @@ const struct attribute_group **ifs_get_groups(void)
{
return plat_ifs_groups;
}
+
+/* global array sysfs attributes */
+static struct attribute *plat_ifs_array_attrs[] = {
+ &dev_attr_details.attr,
+ &dev_attr_status.attr,
+ &dev_attr_run_test.attr,
+ NULL
+};
+
+ATTRIBUTE_GROUPS(plat_ifs_array);
+
+const struct attribute_group **ifs_get_array_groups(void)
+{
+ return plat_ifs_array_groups;
+}
--
2.25.1
Array BIST test (for a particlular core) is triggered by writing
to MSR_ARRAY_BIST from one sibling of the core.
This will initiate a test for all supported arrays on that
CPU. Array BIST test may be aborted before completing all the
arrays in the event of an interrupt or other reasons.
In this case, kernel will restart the test from that point
onwards. Array test will also be aborted when the test fails,
in which case the test is stopped immediately without further
retry.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 12 ++++
drivers/platform/x86/intel/ifs/runtest.c | 92 ++++++++++++++++++++++++
2 files changed, 104 insertions(+)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 07423bc4e368..b1a997e39216 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -127,6 +127,7 @@
#include <linux/device.h>
#include <linux/miscdevice.h>
+#define MSR_ARRAY_BIST 0x00000105
#define MSR_COPY_SCAN_HASHES 0x000002c2
#define MSR_SCAN_HASHES_STATUS 0x000002c3
#define MSR_AUTHENTICATE_AND_COPY_CHUNK 0x000002c4
@@ -194,6 +195,17 @@ union ifs_status {
};
};
+/* MSR_ARRAY_BIST bit fields */
+union ifs_array {
+ u64 data;
+ struct {
+ u32 array_bitmask :32;
+ u32 array_bank :16;
+ u32 rsvd :15;
+ u32 ctrl_result :1;
+ };
+};
+
/*
* Driver populated error-codes
* 0xFD: Test timed out before completing all the chunks.
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 65e08af70994..ec0ceb6b5890 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -229,6 +229,96 @@ static void ifs_test_core(int cpu, struct device *dev)
}
}
+#define SPINUNIT 100 /* 100 nsec */
+static atomic_t array_cpus_out;
+
+/*
+ * Simplified cpu sibling rendezvous loop based on microcode loader __wait_for_cpus()
+ */
+static void wait_for_sibling_cpu(atomic_t *t, long long timeout)
+{
+ int cpu = smp_processor_id();
+ const struct cpumask *smt_mask = cpu_smt_mask(cpu);
+ int all_cpus = cpumask_weight(smt_mask);
+
+ atomic_inc(t);
+ while (atomic_read(t) < all_cpus) {
+ if (timeout < SPINUNIT)
+ return;
+ ndelay(SPINUNIT);
+ timeout -= SPINUNIT;
+ touch_nmi_watchdog();
+ }
+}
+
+static int do_array_test(void *data)
+{
+ int cpu = smp_processor_id();
+ u64 *msrs = data;
+ int first;
+
+ /*
+ * Only one logical CPU on a core needs to trigger the Array test via MSR write.
+ */
+ first = cpumask_first(cpu_smt_mask(cpu));
+
+ if (cpu == first) {
+ wrmsrl(MSR_ARRAY_BIST, msrs[0]);
+ /* Pass back the result of the test */
+ rdmsrl(MSR_ARRAY_BIST, msrs[1]);
+ }
+
+ /* Tests complete faster if the sibling is spinning here */
+ wait_for_sibling_cpu(&array_cpus_out, NSEC_PER_SEC);
+
+ return 0;
+}
+
+static void ifs_array_test_core(int cpu, struct device *dev)
+{
+ union ifs_array activate, status;
+ bool timed_out = false;
+ struct ifs_data *ifsd;
+ unsigned long timeout;
+ u64 msrvals[2];
+
+ ifsd = ifs_get_data(dev);
+
+ activate.data = 0;
+ activate.array_bitmask = ~0U;
+ activate.ctrl_result = 0;
+ timeout = jiffies + HZ / 2;
+
+ do {
+ if (time_after(jiffies, timeout)) {
+ timed_out = true;
+ break;
+ }
+
+ msrvals[0] = activate.data;
+
+ atomic_set(&array_cpus_out, 0);
+ stop_core_cpuslocked(cpu, do_array_test, msrvals);
+ status.data = msrvals[1];
+
+ if (status.ctrl_result)
+ break;
+
+ activate.array_bitmask = status.array_bitmask;
+ activate.array_bank = status.array_bank;
+
+ } while (status.array_bitmask);
+
+ ifsd->scan_details = status.data;
+
+ if (status.ctrl_result)
+ ifsd->status = SCAN_TEST_FAIL;
+ else if (timed_out || status.array_bitmask)
+ ifsd->status = SCAN_NOT_TESTED;
+ else
+ ifsd->status = SCAN_TEST_PASS;
+}
+
/*
* Initiate per core test. It wakes up work queue threads on the target cpu and
* its sibling cpu. Once all sibling threads wake up, the scan test gets executed and
@@ -253,6 +343,8 @@ int do_core_test(int cpu, struct device *dev)
ifs_test_core(cpu, dev);
break;
case IFS_ARRAY:
+ ifs_array_test_core(cpu, dev);
+ break;
default:
return -EINVAL;
}
--
2.25.1
Enable tracing support in array test flow.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
include/trace/events/intel_ifs.h | 27 ++++++++++++++++++++++++
drivers/platform/x86/intel/ifs/runtest.c | 1 +
2 files changed, 28 insertions(+)
diff --git a/include/trace/events/intel_ifs.h b/include/trace/events/intel_ifs.h
index d7353024016c..db43df4139a2 100644
--- a/include/trace/events/intel_ifs.h
+++ b/include/trace/events/intel_ifs.h
@@ -35,6 +35,33 @@ TRACE_EVENT(ifs_status,
__entry->status)
);
+TRACE_EVENT(ifs_array,
+
+ TP_PROTO(int cpu, union ifs_array activate, union ifs_array status),
+
+ TP_ARGS(cpu, activate, status),
+
+ TP_STRUCT__entry(
+ __field( u64, status )
+ __field( int, cpu )
+ __field( u32, arrays )
+ __field( u16, bank )
+ ),
+
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->arrays = activate.array_bitmask;
+ __entry->bank = activate.array_bank;
+ __entry->status = status.data;
+ ),
+
+ TP_printk("cpu: %d, array_list: %.8x, array_bank: %.4x, status: %.16llx",
+ __entry->cpu,
+ __entry->arrays,
+ __entry->bank,
+ __entry->status)
+);
+
#endif /* _TRACE_IFS_H */
/* This part must be outside protection */
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index ec0ceb6b5890..4fd80d91ea29 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -301,6 +301,7 @@ static void ifs_array_test_core(int cpu, struct device *dev)
stop_core_cpuslocked(cpu, do_array_test, msrvals);
status.data = msrvals[1];
+ trace_ifs_array(cpu, activate, status);
if (status.ctrl_result)
break;
--
2.25.1
On Tue, Jan 31, 2023 at 03:43:01PM -0800, Jithu Joseph wrote:
> Array BIST test (for a particlular core) is triggered by writing
> to MSR_ARRAY_BIST from one sibling of the core.
>
> This will initiate a test for all supported arrays on that
> CPU. Array BIST test may be aborted before completing all the
> arrays in the event of an interrupt or other reasons.
> In this case, kernel will restart the test from that point
> onwards. Array test will also be aborted when the test fails,
> in which case the test is stopped immediately without further
> retry.
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> drivers/platform/x86/intel/ifs/ifs.h | 12 ++++
> drivers/platform/x86/intel/ifs/runtest.c | 92 ++++++++++++++++++++++++
> 2 files changed, 104 insertions(+)
>
> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
> index 07423bc4e368..b1a997e39216 100644
> --- a/drivers/platform/x86/intel/ifs/ifs.h
> +++ b/drivers/platform/x86/intel/ifs/ifs.h
> @@ -127,6 +127,7 @@
> #include <linux/device.h>
> #include <linux/miscdevice.h>
>
> +#define MSR_ARRAY_BIST 0x00000105
> #define MSR_COPY_SCAN_HASHES 0x000002c2
> #define MSR_SCAN_HASHES_STATUS 0x000002c3
> #define MSR_AUTHENTICATE_AND_COPY_CHUNK 0x000002c4
> @@ -194,6 +195,17 @@ union ifs_status {
> };
> };
>
> +/* MSR_ARRAY_BIST bit fields */
> +union ifs_array {
> + u64 data;
> + struct {
> + u32 array_bitmask :32;
> + u32 array_bank :16;
> + u32 rsvd :15;
> + u32 ctrl_result :1;
This isn't going to work well over time, just mask the bits you want off
properly, don't rely on the compiler to lay them out like this.
Note, we have bitmask and bitfield operations, please use them.
thanks,
greg k-h
On Tue, Jan 31, 2023 at 03:43:00PM -0800, Jithu Joseph wrote:
> The interface to trigger Array BIST test and obtain its result
> is similar to the existing scan test. The only notable
> difference is that, Array BIST doesn't require any test content
> to be loaded. So binary load related options are not needed for
> this test.
>
> Add sysfs interface array BIST test, the testing support will
> be added by subsequent patch.
What is "sysfs interface array" exactly?
Where is the new Documentation/ABI/ entries for these new sysfs files
you added?
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> drivers/platform/x86/intel/ifs/ifs.h | 1 +
> drivers/platform/x86/intel/ifs/core.c | 18 +++++++++++++-----
> drivers/platform/x86/intel/ifs/runtest.c | 11 ++++++++++-
> drivers/platform/x86/intel/ifs/sysfs.c | 17 ++++++++++++++++-
> 4 files changed, 40 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
> index 2cef88a88aa9..07423bc4e368 100644
> --- a/drivers/platform/x86/intel/ifs/ifs.h
> +++ b/drivers/platform/x86/intel/ifs/ifs.h
> @@ -249,5 +249,6 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
> int ifs_load_firmware(struct device *dev);
> int do_core_test(int cpu, struct device *dev);
> const struct attribute_group **ifs_get_groups(void);
> +const struct attribute_group **ifs_get_array_groups(void);
>
> #endif
> diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
> index ab234620ef4c..2b7a49fd473d 100644
> --- a/drivers/platform/x86/intel/ifs/core.c
> +++ b/drivers/platform/x86/intel/ifs/core.c
> @@ -25,6 +25,7 @@ static struct ifs_device ifs_devices[] = {
> [IFS_SAF] = {
> .data = {
> .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> + .pkg_auth = NULL,
> .test_num = IFS_SAF,
> },
> .misc = {
> @@ -36,6 +37,7 @@ static struct ifs_device ifs_devices[] = {
> [IFS_ARRAY] = {
> .data = {
> .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
> + .pkg_auth = NULL,
> .test_num = IFS_ARRAY,
> },
> .misc = {
> @@ -72,11 +74,17 @@ static int __init ifs_init(void)
> if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit)))
> continue;
>
> - ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
> - sizeof(bool), GFP_KERNEL);
> - if (!ifs_devices[i].data.pkg_auth)
> - continue;
> - ifs_devices[i].misc.groups = ifs_get_groups();
> + switch (ifs_devices[i].data.test_num) {
> + case IFS_SAF:
> + ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
> + sizeof(bool), GFP_KERNEL);
> + if (!ifs_devices[i].data.pkg_auth)
> + continue;
> + ifs_devices[i].misc.groups = ifs_get_groups();
> + break;
> + case IFS_ARRAY:
> + ifs_devices[i].misc.groups = ifs_get_array_groups();
> + }
>
> if (misc_register(&ifs_devices[i].misc))
> kfree(ifs_devices[i].data.pkg_auth);
> diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
> index 0bfd8fcdd7e8..65e08af70994 100644
> --- a/drivers/platform/x86/intel/ifs/runtest.c
> +++ b/drivers/platform/x86/intel/ifs/runtest.c
> @@ -236,6 +236,7 @@ static void ifs_test_core(int cpu, struct device *dev)
> */
> int do_core_test(int cpu, struct device *dev)
> {
> + struct ifs_data *ifsd = ifs_get_data(dev);
> int ret = 0;
>
> /* Prevent CPUs from being taken offline during the scan test */
> @@ -247,7 +248,15 @@ int do_core_test(int cpu, struct device *dev)
> goto out;
> }
>
> - ifs_test_core(cpu, dev);
> + switch (ifsd->test_num) {
> + case IFS_SAF:
> + ifs_test_core(cpu, dev);
> + break;
> + case IFS_ARRAY:
> + default:
> + return -EINVAL;
> + }
> +
> out:
> cpus_read_unlock();
> return ret;
> diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
> index ee636a76b083..7cf32184ce6a 100644
> --- a/drivers/platform/x86/intel/ifs/sysfs.c
> +++ b/drivers/platform/x86/intel/ifs/sysfs.c
> @@ -75,7 +75,7 @@ static ssize_t run_test_store(struct device *dev,
> if (down_interruptible(&ifs_sem))
> return -EINTR;
>
> - if (!ifsd->loaded)
> + if (ifsd->test_num != IFS_ARRAY && !ifsd->loaded)
> rc = -EPERM;
> else
> rc = do_core_test(cpu, dev);
> @@ -156,3 +156,18 @@ const struct attribute_group **ifs_get_groups(void)
> {
> return plat_ifs_groups;
> }
> +
> +/* global array sysfs attributes */
> +static struct attribute *plat_ifs_array_attrs[] = {
> + &dev_attr_details.attr,
> + &dev_attr_status.attr,
> + &dev_attr_run_test.attr,
> + NULL
> +};
> +
> +ATTRIBUTE_GROUPS(plat_ifs_array);
> +
> +const struct attribute_group **ifs_get_array_groups(void)
> +{
> + return plat_ifs_array_groups;
> +}
Why do you need a function to get access to a static variable? Just
make the variable not static.
thanks,
greg k-h
> > +/* MSR_ARRAY_BIST bit fields */
> > +union ifs_array {
> > + u64 data;
> > + struct {
> > + u32 array_bitmask :32;
> > + u32 array_bank :16;
> > + u32 rsvd :15;
> > + u32 ctrl_result :1;
>
> This isn't going to work well over time, just mask the bits you want off
> properly, don't rely on the compiler to lay them out like this.
What is this "time" issue? This driver is X86_64 specific (and it seems
incredibly unlikely that some other architecture will copy this h/w
interface so closely that they want to re-use this driver. There's an x86_64
ABI that says how bitfields in C are allocated. So should not break moving
to other C compilers.
Is there going to be a "re-write all drivers in Rust" edict coming soon?
> Note, we have bitmask and bitfield operations, please use them.
We do, but code written using them is not as easy to read (unless
you wrap in even more macros, which has its own maintainability
issues).
There are already thousands of bitfields in Linux kernel source:
$ git grep ':[1-9][0-9]*;' -- include/ | wc -l
2251
Has there been a change in attitude at the kernel maintainers summit?
-Tony
On Wed, Feb 01, 2023 at 05:22:18PM +0000, Luck, Tony wrote:
> > > +/* MSR_ARRAY_BIST bit fields */
> > > +union ifs_array {
> > > + u64 data;
> > > + struct {
> > > + u32 array_bitmask :32;
> > > + u32 array_bank :16;
> > > + u32 rsvd :15;
> > > + u32 ctrl_result :1;
> >
> > This isn't going to work well over time, just mask the bits you want off
> > properly, don't rely on the compiler to lay them out like this.
>
> What is this "time" issue? This driver is X86_64 specific (and it seems
> incredibly unlikely that some other architecture will copy this h/w
> interface so closely that they want to re-use this driver. There's an x86_64
> ABI that says how bitfields in C are allocated. So should not break moving
> to other C compilers.
Ok, but generally this is considered a "bad idea" that you should not
do. It's been this way for many many years, just because this file only
runs on one system now, doesn't mean you shouldn't use the proper apis.
Also, odds are, using the proper apis will get you faster/smaller code
than using a bitfield like this as compilers were notorious for doing
odd things here in the past.
> Is there going to be a "re-write all drivers in Rust" edict coming soon?
Don't be silly, it's been this way for drivers for decades.
>
> > Note, we have bitmask and bitfield operations, please use them.
>
> We do, but code written using them is not as easy to read (unless
> you wrap in even more macros, which has its own maintainability
> issues).
It shouldn't be that hard, lots of people use them today.
Try and see!
thanks,
greg k-h
On Wed, Feb 01, 2023 at 07:19:15PM +0100, Greg KH wrote:
> It shouldn't be that hard, lots of people use them today.
>
> Try and see!
Extract from the first of our in-field-scan tests:
while (activate.start <= activate.stop) {
... trigger scan ...
if (status.chunk_num == activate.start) {
... check for too many retries on same chunk ...
} else {
activate.start = status.chunk_num;
}
}
using <linux/bitfield.h> becomes:
while (FIELD_GET(GENMASK(7, 0), activate) <= FIELD_GET(GENMASK(15, 8), activate) {
if (FIELD_GET(GENMASK(7, 0), status) == FIELD_GET(GENMASK(7, 0), activate) {
...
} else {
activate &= ~GENMASK(7, 0);
activate |= FIELD_PREP(GENMASK(7, 0), FIELD_GET(GENMASK(7, 0), status));
}
}
While I can make that more legible with some helper #defines for the
fields, it becomes more difficult to write, and no easier to read (since
I then have to chase down what the macros are doing).
If this were in some performance critical path, I might worry about
whether the generated code was good enough. But this code path isn't
remotely critical to anyone. The test takes up to 200 usec, so saving
a handful of cycles in the surrounding code will be in the noise.
-Tony
On 1/31/23 15:43, Jithu Joseph wrote:
> +union ifs_array {
> + u64 data;
> + struct {
> + u32 array_bitmask :32;
> + u32 array_bank :16;
> + u32 rsvd :15;
> + u32 ctrl_result :1;
> + };
> +};
Why bother with a bitfield? Just do:
union ifs_array {
u64 data;
struct {
u32 array_bitmask;
u16 array_bank;
u16 flags;
};
};
Then you only need to mask 'ctrl_result' out of flags. You don't need
any crazy macros.
> Why bother with a bitfield? Just do:
How much "bother" is a bitfield?
> union ifs_array {
> u64 data;
> struct {
> u32 array_bitmask;
> u16 array_bank;
> u16 flags;
> };
>};
>
> Then you only need to mask 'ctrl_result' out of flags. You don't need
> any crazy macros.
"only need" to special case this one field ... but that's extra
code for humans to read (and humans aren't good at that)
rather than the computer (compiler) which is really good at
doing this.
Using bitfields is also following the existing style of this driver.
-Tony
On 1/31/23 15:43, Jithu Joseph wrote:
> +static void ifs_array_test_core(int cpu, struct device *dev)
> +{
> + union ifs_array activate, status;
> + bool timed_out = false;
> + struct ifs_data *ifsd;
> + unsigned long timeout;
> + u64 msrvals[2];
> +
> + ifsd = ifs_get_data(dev);
> +
> + activate.data = 0;
> + activate.array_bitmask = ~0U;
> + activate.ctrl_result = 0;
I think this whole 'ifs_array' as a union thing is bogus. It's actually
obfuscating and *COMPLICATING* the code more than anything. Look what
you have:
union ifs_array activate; // declare it on the stack, unzeroed
activate.data = 0; // zero the structure;
activate.array_bitmask = ~0U; // set one field
activate.ctrl_result = 0; // set the field to zero again???
Can we make it less obfuscated? How about:
struct ifs_array activate = {}; // zero it
...
activate.array_bitmask = ~0U; // set the only nonzero field
Voila! Less code, less obfuscation, less duplicated effort. Or, worst
case:
struct ifs_array activate;
...
memset(&activate, 0, sizeof(activate));
activate.array_bitmask = ~0U;
That's sane and everyone knows what it does and doesn't have to know
what unions are involved or how they are used. It's correct code no
matter *WHAT* craziness lies within 'activate'.
On 2/1/23 11:43, Luck, Tony wrote:
>> Why bother with a bitfield? Just do:
> How much "bother" is a bitfield?
>
>> union ifs_array {
>> u64 data;
>> struct {
>> u32 array_bitmask;
>> u16 array_bank;
>> u16 flags;
>> };
>> };
>>
>> Then you only need to mask 'ctrl_result' out of flags. You don't need
>> any crazy macros.
> "only need" to special case this one field ... but that's extra
> code for humans to read (and humans aren't good at that)
> rather than the computer (compiler) which is really good at
> doing this.
I don't follow.
If you have:
struct foo {
u16 rsvd :15;
u16 ctrl_result :1;
};
versus:
struct bar {
u16 flags;
};
and you do:
if (foo->ctrl_result)
something();
versus:
if (bar->flags & CTRL_RESULT_MASK)
something();
I think both of those are quite readable. I'd argue that humans will be
less _surprised_ by 'bar'. I also like to write portable code even if
it's going to be x86 only. It helps people who are used to reading
portable generic code read and find bugs in x86 only code.
On 2/1/2023 11:45 AM, Dave Hansen wrote:
> On 1/31/23 15:43, Jithu Joseph wrote:
>> +static void ifs_array_test_core(int cpu, struct device *dev)
>> +{
>> + union ifs_array activate, status;
>> + bool timed_out = false;
>> + struct ifs_data *ifsd;
>> + unsigned long timeout;
>> + u64 msrvals[2];
>> +
>> + ifsd = ifs_get_data(dev);
>> +
>> + activate.data = 0;
>> + activate.array_bitmask = ~0U;
>> + activate.ctrl_result = 0;
>
> I think this whole 'ifs_array' as a union thing is bogus. It's actually
> obfuscating and *COMPLICATING* the code more than anything. Look what
> you have:
>
> union ifs_array activate; // declare it on the stack, unzeroed
>
> activate.data = 0; // zero the structure;
> activate.array_bitmask = ~0U; // set one field
> activate.ctrl_result = 0; // set the field to zero again???
>
> Can we make it less obfuscated? How about:
>
> struct ifs_array activate = {}; // zero it
> ...
> activate.array_bitmask = ~0U; // set the only nonzero field
>
> Voila! Less code, less obfuscation, less duplicated effort. Or, worst
Agreed, will modify it as you suggest above to remove the duplicate zero assignments
> case:
>
> struct ifs_array activate;
> ...
> memset(&activate, 0, sizeof(activate));
> activate.array_bitmask = ~0U;
>
> That's sane and everyone knows what it does and doesn't have to know
> what unions are involved or how they are used. It's correct code no
> matter *WHAT* craziness lies within 'activate'.
On 2/1/23 11:56, Joseph, Jithu wrote:
>> Voila! Less code, less obfuscation, less duplicated effort. Or, worst
> Agreed, will modify it as you suggest above to remove the duplicate zero assignments
... and the union ... and the _unnecessary_ bitfields. You can make an
argument that ->ctrl_result should be a bitfield. The other
structure members, not so much. Make them standalone unsigned integers.
But, when it's down to a single bit in an otherwise completely
unpopulated byte-sized field, your arguments for using a bitfield kinda
dry up. But, heck, if that's the hill you want to die on, who am I to
stop you?
On 1/31/2023 9:04 PM, Greg KH wrote:
> On Tue, Jan 31, 2023 at 03:43:00PM -0800, Jithu Joseph wrote:
>> The interface to trigger Array BIST test and obtain its result
>> is similar to the existing scan test. The only notable
>> difference is that, Array BIST doesn't require any test content
>> to be loaded. So binary load related options are not needed for
>> this test.
>>
>> Add sysfs interface array BIST test, the testing support will
>> be added by subsequent patch.
>
> What is "sysfs interface array" exactly?
Pardon the typo ... meant to write "sysfs interface for array BIST test ..."
sysfs entries for this new test will appear under "/sys/devices/virtual/misc/intel_ifs_1/"
(whereas the existing scan test entries will be under "/sys/devices/virtual/misc/intel_ifs_0/")
>
> Where is the new Documentation/ABI/ entries for these new sysfs files
> you added?
>
Current documentation and ABI entries are somewhat generalized (we mention intel_ifs_<n>).
Pasting a small snippet below for reference from Documentation/ABI/testing/sysfs-platform-intel-ifs
<snip>
What: /sys/devices/virtual/misc/intel_ifs_<N>/run_test
Date: Nov 16 2022
KernelVersion: 6.2
Contact: "Jithu Joseph" <[email protected]>
Description: Write <cpu#> to trigger IFS test for one online core.
Note that the test is per core. The cpu# can be
...
</snip>
I can take another pass through both, to call out the differences wherever applicable
(like test image loading is not applicable for array BIST test)
...
>> @@ -156,3 +156,18 @@ const struct attribute_group **ifs_get_groups(void)
>> {
>> return plat_ifs_groups;
>> }
>> +
>> +/* global array sysfs attributes */
>> +static struct attribute *plat_ifs_array_attrs[] = {
>> + &dev_attr_details.attr,
>> + &dev_attr_status.attr,
>> + &dev_attr_run_test.attr,
>> + NULL
>> +};
>> +
>> +ATTRIBUTE_GROUPS(plat_ifs_array);
>> +
>> +const struct attribute_group **ifs_get_array_groups(void)
>> +{
>> + return plat_ifs_array_groups;
>> +}
>
> Why do you need a function to get access to a static variable? Just
> make the variable not static.
The above was in-line with the existing driver style for the first test
But if it is more appropriate, I can move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c (where it is consumed) and drop the function
Jithu
> But, when it's down to a single bit in an otherwise completely
> unpopulated byte-sized field, your arguments for using a bitfield kinda
> dry up. But, heck, if that's the hill you want to die on, who am I to
> stop you?
It helps for consistency of style with all the other definitions here where
some other registers don't have such trivial mappings of fields to C base types.
I know that using bitfields in arch independent code is fraught with problems.
But these definitions are for the bits in Intel MSRs (model specific registers).
This seems to be an open & shut case that this code is never going to be
used on some other architecture.
-Tony
On Tue, 31 Jan 2023 15:43:02 -0800
Jithu Joseph <[email protected]> wrote:
> diff --git a/include/trace/events/intel_ifs.h b/include/trace/events/intel_ifs.h
> index d7353024016c..db43df4139a2 100644
> --- a/include/trace/events/intel_ifs.h
> +++ b/include/trace/events/intel_ifs.h
> @@ -35,6 +35,33 @@ TRACE_EVENT(ifs_status,
> __entry->status)
> );
>
> +TRACE_EVENT(ifs_array,
> +
> + TP_PROTO(int cpu, union ifs_array activate, union ifs_array status),
> +
> + TP_ARGS(cpu, activate, status),
> +
> + TP_STRUCT__entry(
> + __field( u64, status )
> + __field( int, cpu )
> + __field( u32, arrays )
> + __field( u16, bank )
> + ),
> +
> + TP_fast_assign(
> + __entry->cpu = cpu;
> + __entry->arrays = activate.array_bitmask;
> + __entry->bank = activate.array_bank;
Regardless of the "bitfield" discussion on the other patches, this part
is considered a fast path (although if where it is called, then it may
not be). I would just have:
__field( u64, data )
__entry->data = status.data;
> + __entry->status = status.data;
> + ),
> +
> + TP_printk("cpu: %d, array_list: %.8x, array_bank: %.4x, status: %.16llx",
> + __entry->cpu,
> + __entry->arrays,
> + __entry->bank,
__entry->data >> 32,
(__entry->data >> 16) & 0xffff,
Or something similar. That is, move the parsing of the bits to the
output. libtraceevent should still be able to handle this.
-- Steve
> + __entry->status)
> +);
> +
Thanks for the review
On 2/6/2023 8:40 AM, Steven Rostedt wrote:
> On Tue, 31 Jan 2023 15:43:02 -0800
> Jithu Joseph <[email protected]> wrote:
>
>> diff --git a/include/trace/events/intel_ifs.h b/include/trace/events/intel_ifs.h
>> index d7353024016c..db43df4139a2 100644
>> --- a/include/trace/events/intel_ifs.h
>> +++ b/include/trace/events/intel_ifs.h
>> @@ -35,6 +35,33 @@ TRACE_EVENT(ifs_status,
>> __entry->status)
>> );
>>
>> +TRACE_EVENT(ifs_array,
>> +
>> + TP_PROTO(int cpu, union ifs_array activate, union ifs_array status),
>> +
>> + TP_ARGS(cpu, activate, status),
>> +
>> + TP_STRUCT__entry(
>> + __field( u64, status )
>> + __field( int, cpu )
>> + __field( u32, arrays )
>> + __field( u16, bank )
>> + ),
>> +
>> + TP_fast_assign(
>> + __entry->cpu = cpu;
>> + __entry->arrays = activate.array_bitmask;
>> + __entry->bank = activate.array_bank;
>
> Regardless of the "bitfield" discussion on the other patches, this part
> is considered a fast path (although if where it is called, then it may
> not be). I would just have:
>
> __field( u64, data )
>
> __entry->data = status.data;
Will modify it as given below (in-line with your suggestion)
TP_STRUCT__entry(
__field( u64, activate )
__field( u64, status )
__field( int, cpu )
),
TP_fast_assign(
__entry->activate = activate.data;
__entry->status = status.data;
__entry->cpu = cpu;
),
TP_printk("cpu: %d, array_list: %.8llx, array_bank: %.4llx, status: %.16llx",
__entry->cpu,
__entry->activate & 0xffffffff,
(__entry->activate >> 32) & 0xffff,
__entry->status)
In general this is not called from a fast path within, i.e rate of triggering the tests is likely to be
"per minute" (Though in certain scenarios of driver retries it can be more frequent than that)
>
> __entry->data >> 32,
> (__entry->data >> 16) & 0xffff,
>
> Or something similar. That is, move the parsing of the bits to the
> output. libtraceevent should still be able to handle this.
>
Jithu
Changes in v2
- remove duplicate initializations from ifs_array_test_core()
(Dave Hansen, patch 4/7)
- remove bit parsing from tracing fast path to tracing
output (Steven Rostedt, patch 5/7)
- move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
- Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)
v1 submission:
Link: https://lore.kernel.org/lkml/[email protected]/
Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by Scan at Field (SAF).
Unlike SAF, Array BIST doesn't require any test content to be loaded.
Jithu Joseph (7):
x86/include/asm/msr-index.h: Add IFS Array test bits
platform/x86/intel/ifs: Introduce Array Scan test to IFS
platform/x86/intel/ifs: Sysfs interface for Array BIST
platform/x86/intel/ifs: Implement Array BIST test
platform/x86/intel/ifs: Trace support for array test
platform/x86/intel/ifs: Update IFS doc
Documentation/ABI: Update IFS ABI doc
arch/x86/include/asm/msr-index.h | 2 +
drivers/platform/x86/intel/ifs/ifs.h | 41 +++++--
include/trace/events/intel_ifs.h | 25 +++++
drivers/platform/x86/intel/ifs/core.c | 85 ++++++++++-----
drivers/platform/x86/intel/ifs/runtest.c | 102 +++++++++++++++++-
drivers/platform/x86/intel/ifs/sysfs.c | 10 +-
.../ABI/testing/sysfs-platform-intel-ifs | 8 +-
7 files changed, 233 insertions(+), 40 deletions(-)
base-commit: ceaa837f96adb69c0df0397937cd74991d5d821a
--
2.25.1
Define MSR bitfields for enumerating support for Array BIST test.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
arch/x86/include/asm/msr-index.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index d3fe82c5d6b6..ad8997773ad3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -197,6 +197,8 @@
/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
#define MSR_INTEGRITY_CAPS 0x000002d9
+#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2
+#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
--
2.25.1
Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by the first test type
i.e Scan at Field (SAF).
Make changes in the device driver init flow to register this new test
type with the device driver framework. Each test will have its own
sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
accommodate for the differences in test type and how they are initiated.
Upcoming patches will add actual support.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 5 ++
drivers/platform/x86/intel/ifs/core.c | 70 ++++++++++++++++++---------
2 files changed, 52 insertions(+), 23 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 046e39304fd5..2cef88a88aa9 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -137,6 +137,11 @@
#define SCAN_TEST_PASS 1
#define SCAN_TEST_FAIL 2
+enum test_types {
+ IFS_SAF,
+ IFS_ARRAY,
+};
+
/* MSR_SCAN_HASHES_STATUS bit fields */
union ifs_scan_hashes_status {
u64 data;
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 206a617c2e02..ab234620ef4c 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -16,27 +16,44 @@
static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
X86_MATCH(SAPPHIRERAPIDS_X),
+ X86_MATCH(EMERALDRAPIDS_X),
{}
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
-static struct ifs_device ifs_device = {
- .data = {
- .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
- .test_num = 0,
+static struct ifs_device ifs_devices[] = {
+ [IFS_SAF] = {
+ .data = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
+ .test_num = IFS_SAF,
+ },
+ .misc = {
+ .name = "intel_ifs_0",
+ .nodename = "intel_ifs/0",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
- .misc = {
- .name = "intel_ifs_0",
- .nodename = "intel_ifs/0",
- .minor = MISC_DYNAMIC_MINOR,
+ [IFS_ARRAY] = {
+ .data = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
+ .test_num = IFS_ARRAY,
+ },
+ .misc = {
+ .name = "intel_ifs_1",
+ .nodename = "intel_ifs/1",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
};
+#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
+
static int __init ifs_init(void)
{
const struct x86_cpu_id *m;
+ int ndevices = 0;
u64 msrval;
- int ret;
+ int i;
m = x86_match_cpu(ifs_cpu_ids);
if (!m)
@@ -51,28 +68,35 @@ static int __init ifs_init(void)
if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
return -ENODEV;
- ifs_device.misc.groups = ifs_get_groups();
-
- if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
- return -ENODEV;
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit)))
+ continue;
- ifs_device.data.pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
- if (!ifs_device.data.pkg_auth)
- return -ENOMEM;
+ ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
+ sizeof(bool), GFP_KERNEL);
+ if (!ifs_devices[i].data.pkg_auth)
+ continue;
+ ifs_devices[i].misc.groups = ifs_get_groups();
- ret = misc_register(&ifs_device.misc);
- if (ret) {
- kfree(ifs_device.data.pkg_auth);
- return ret;
+ if (misc_register(&ifs_devices[i].misc))
+ kfree(ifs_devices[i].data.pkg_auth);
+ else
+ ndevices++;
}
- return 0;
+ return ndevices ? 0 : -ENODEV;
}
static void __exit ifs_exit(void)
{
- misc_deregister(&ifs_device.misc);
- kfree(ifs_device.data.pkg_auth);
+ int i;
+
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (ifs_devices[i].misc.this_device) {
+ misc_deregister(&ifs_devices[i].misc);
+ kfree(ifs_devices[i].data.pkg_auth);
+ }
+ }
}
module_init(ifs_init);
--
2.25.1
The interface to trigger Array BIST test and obtain its result
is similar to the existing scan test. The only notable
difference is that, Array BIST doesn't require any test content
to be loaded. So binary load related options are not needed for
this test.
Add sysfs interface for array BIST test, the testing support will
be added by subsequent patch.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 1 +
drivers/platform/x86/intel/ifs/core.c | 21 ++++++++++++++++-----
drivers/platform/x86/intel/ifs/runtest.c | 11 ++++++++++-
drivers/platform/x86/intel/ifs/sysfs.c | 10 +++++++++-
4 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 2cef88a88aa9..a0cb2696c1d9 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -249,5 +249,6 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
int ifs_load_firmware(struct device *dev);
int do_core_test(int cpu, struct device *dev);
const struct attribute_group **ifs_get_groups(void);
+extern struct attribute *plat_ifs_array_attrs[];
#endif
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index ab234620ef4c..d0d4e1fb62f6 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -25,6 +25,7 @@ static struct ifs_device ifs_devices[] = {
[IFS_SAF] = {
.data = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
+ .pkg_auth = NULL,
.test_num = IFS_SAF,
},
.misc = {
@@ -36,6 +37,7 @@ static struct ifs_device ifs_devices[] = {
[IFS_ARRAY] = {
.data = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
+ .pkg_auth = NULL,
.test_num = IFS_ARRAY,
},
.misc = {
@@ -48,6 +50,8 @@ static struct ifs_device ifs_devices[] = {
#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
+ATTRIBUTE_GROUPS(plat_ifs_array);
+
static int __init ifs_init(void)
{
const struct x86_cpu_id *m;
@@ -72,11 +76,18 @@ static int __init ifs_init(void)
if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit)))
continue;
- ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
- sizeof(bool), GFP_KERNEL);
- if (!ifs_devices[i].data.pkg_auth)
- continue;
- ifs_devices[i].misc.groups = ifs_get_groups();
+ switch (ifs_devices[i].data.test_num) {
+ case IFS_SAF:
+ ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
+ sizeof(bool), GFP_KERNEL);
+ if (!ifs_devices[i].data.pkg_auth)
+ continue;
+ ifs_devices[i].misc.groups = ifs_get_groups();
+ break;
+ case IFS_ARRAY:
+ ifs_devices[i].misc.groups = plat_ifs_array_groups;
+ break;
+ }
if (misc_register(&ifs_devices[i].misc))
kfree(ifs_devices[i].data.pkg_auth);
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 0bfd8fcdd7e8..65e08af70994 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -236,6 +236,7 @@ static void ifs_test_core(int cpu, struct device *dev)
*/
int do_core_test(int cpu, struct device *dev)
{
+ struct ifs_data *ifsd = ifs_get_data(dev);
int ret = 0;
/* Prevent CPUs from being taken offline during the scan test */
@@ -247,7 +248,15 @@ int do_core_test(int cpu, struct device *dev)
goto out;
}
- ifs_test_core(cpu, dev);
+ switch (ifsd->test_num) {
+ case IFS_SAF:
+ ifs_test_core(cpu, dev);
+ break;
+ case IFS_ARRAY:
+ default:
+ return -EINVAL;
+ }
+
out:
cpus_read_unlock();
return ret;
diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
index ee636a76b083..3e205fead7ab 100644
--- a/drivers/platform/x86/intel/ifs/sysfs.c
+++ b/drivers/platform/x86/intel/ifs/sysfs.c
@@ -75,7 +75,7 @@ static ssize_t run_test_store(struct device *dev,
if (down_interruptible(&ifs_sem))
return -EINTR;
- if (!ifsd->loaded)
+ if (ifsd->test_num != IFS_ARRAY && !ifsd->loaded)
rc = -EPERM;
else
rc = do_core_test(cpu, dev);
@@ -156,3 +156,11 @@ const struct attribute_group **ifs_get_groups(void)
{
return plat_ifs_groups;
}
+
+/* global array sysfs attributes */
+struct attribute *plat_ifs_array_attrs[] = {
+ &dev_attr_details.attr,
+ &dev_attr_status.attr,
+ &dev_attr_run_test.attr,
+ NULL
+};
--
2.25.1
Array BIST test (for a particlular core) is triggered by writing
to MSR_ARRAY_BIST from one sibling of the core.
This will initiate a test for all supported arrays on that
CPU. Array BIST test may be aborted before completing all the
arrays in the event of an interrupt or other reasons.
In this case, kernel will restart the test from that point
onwards. Array test will also be aborted when the test fails,
in which case the test is stopped immediately without further
retry.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 12 ++++
drivers/platform/x86/intel/ifs/runtest.c | 90 ++++++++++++++++++++++++
2 files changed, 102 insertions(+)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index a0cb2696c1d9..e5375191b56d 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -127,6 +127,7 @@
#include <linux/device.h>
#include <linux/miscdevice.h>
+#define MSR_ARRAY_BIST 0x00000105
#define MSR_COPY_SCAN_HASHES 0x000002c2
#define MSR_SCAN_HASHES_STATUS 0x000002c3
#define MSR_AUTHENTICATE_AND_COPY_CHUNK 0x000002c4
@@ -194,6 +195,17 @@ union ifs_status {
};
};
+/* MSR_ARRAY_BIST bit fields */
+union ifs_array {
+ u64 data;
+ struct {
+ u32 array_bitmask :32;
+ u32 array_bank :16;
+ u32 rsvd :15;
+ u32 ctrl_result :1;
+ };
+};
+
/*
* Driver populated error-codes
* 0xFD: Test timed out before completing all the chunks.
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 65e08af70994..12880fca0aa8 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -229,6 +229,94 @@ static void ifs_test_core(int cpu, struct device *dev)
}
}
+#define SPINUNIT 100 /* 100 nsec */
+static atomic_t array_cpus_out;
+
+/*
+ * Simplified cpu sibling rendezvous loop based on microcode loader __wait_for_cpus()
+ */
+static void wait_for_sibling_cpu(atomic_t *t, long long timeout)
+{
+ int cpu = smp_processor_id();
+ const struct cpumask *smt_mask = cpu_smt_mask(cpu);
+ int all_cpus = cpumask_weight(smt_mask);
+
+ atomic_inc(t);
+ while (atomic_read(t) < all_cpus) {
+ if (timeout < SPINUNIT)
+ return;
+ ndelay(SPINUNIT);
+ timeout -= SPINUNIT;
+ touch_nmi_watchdog();
+ }
+}
+
+static int do_array_test(void *data)
+{
+ int cpu = smp_processor_id();
+ u64 *msrs = data;
+ int first;
+
+ /*
+ * Only one logical CPU on a core needs to trigger the Array test via MSR write.
+ */
+ first = cpumask_first(cpu_smt_mask(cpu));
+
+ if (cpu == first) {
+ wrmsrl(MSR_ARRAY_BIST, msrs[0]);
+ /* Pass back the result of the test */
+ rdmsrl(MSR_ARRAY_BIST, msrs[1]);
+ }
+
+ /* Tests complete faster if the sibling is spinning here */
+ wait_for_sibling_cpu(&array_cpus_out, NSEC_PER_SEC);
+
+ return 0;
+}
+
+static void ifs_array_test_core(int cpu, struct device *dev)
+{
+ union ifs_array activate, status = {0};
+ bool timed_out = false;
+ struct ifs_data *ifsd;
+ unsigned long timeout;
+ u64 msrvals[2];
+
+ ifsd = ifs_get_data(dev);
+
+ activate.array_bitmask = ~0U;
+ timeout = jiffies + HZ / 2;
+
+ do {
+ if (time_after(jiffies, timeout)) {
+ timed_out = true;
+ break;
+ }
+
+ msrvals[0] = activate.data;
+
+ atomic_set(&array_cpus_out, 0);
+ stop_core_cpuslocked(cpu, do_array_test, msrvals);
+ status.data = msrvals[1];
+
+ if (status.ctrl_result)
+ break;
+
+ activate.array_bitmask = status.array_bitmask;
+ activate.array_bank = status.array_bank;
+
+ } while (status.array_bitmask);
+
+ ifsd->scan_details = status.data;
+
+ if (status.ctrl_result)
+ ifsd->status = SCAN_TEST_FAIL;
+ else if (timed_out || status.array_bitmask)
+ ifsd->status = SCAN_NOT_TESTED;
+ else
+ ifsd->status = SCAN_TEST_PASS;
+}
+
/*
* Initiate per core test. It wakes up work queue threads on the target cpu and
* its sibling cpu. Once all sibling threads wake up, the scan test gets executed and
@@ -253,6 +341,8 @@ int do_core_test(int cpu, struct device *dev)
ifs_test_core(cpu, dev);
break;
case IFS_ARRAY:
+ ifs_array_test_core(cpu, dev);
+ break;
default:
return -EINVAL;
}
--
2.25.1
Enable tracing support in array test flow.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
include/trace/events/intel_ifs.h | 25 ++++++++++++++++++++++++
drivers/platform/x86/intel/ifs/runtest.c | 1 +
2 files changed, 26 insertions(+)
diff --git a/include/trace/events/intel_ifs.h b/include/trace/events/intel_ifs.h
index d7353024016c..d15037943b80 100644
--- a/include/trace/events/intel_ifs.h
+++ b/include/trace/events/intel_ifs.h
@@ -35,6 +35,31 @@ TRACE_EVENT(ifs_status,
__entry->status)
);
+TRACE_EVENT(ifs_array,
+
+ TP_PROTO(int cpu, union ifs_array activate, union ifs_array status),
+
+ TP_ARGS(cpu, activate, status),
+
+ TP_STRUCT__entry(
+ __field( u64, activate )
+ __field( u64, status )
+ __field( int, cpu )
+ ),
+
+ TP_fast_assign(
+ __entry->activate = activate.data;
+ __entry->status = status.data;
+ __entry->cpu = cpu;
+ ),
+
+ TP_printk("cpu: %d, array_list: %.8llx, array_bank: %.4llx, status: %.16llx",
+ __entry->cpu,
+ __entry->activate & 0xffffffff,
+ (__entry->activate >> 32) & 0xffff,
+ __entry->status)
+);
+
#endif /* _TRACE_IFS_H */
/* This part must be outside protection */
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 12880fca0aa8..e74004fab1aa 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -299,6 +299,7 @@ static void ifs_array_test_core(int cpu, struct device *dev)
stop_core_cpuslocked(cpu, do_array_test, msrvals);
status.data = msrvals[1];
+ trace_ifs_array(cpu, activate, status);
if (status.ctrl_result)
break;
--
2.25.1
Array BIST is the second test supported by IFS. Modify IFS doc
entry to be more general.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index e5375191b56d..00bc86db1193 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -17,7 +17,7 @@
* In Field Scan (IFS) is a hardware feature to run circuit level tests on
* a CPU core to detect problems that are not caught by parity or ECC checks.
* Future CPUs will support more than one type of test which will show up
- * with a new platform-device instance-id, for now only .0 is exposed.
+ * with a new platform-device instance-id.
*
*
* IFS Image
@@ -25,7 +25,10 @@
*
* Intel provides a firmware file containing the scan tests via
* github [#f1]_. Similar to microcode there is a separate file for each
- * family-model-stepping.
+ * family-model-stepping. IFS Images are not applicable for some test types.
+ * Wherever applicable the sysfs directory would provide a "current_batch" file
+ * (see below) for loading the image.
+ *
*
* IFS Image Loading
* -----------------
@@ -35,7 +38,7 @@
* SHA hashes for the test. Then the tests themselves. Status MSRs provide
* feedback on the success/failure of these steps.
*
- * The test files are kept in a fixed location: /lib/firmware/intel/ifs_0/
+ * The test files are kept in a fixed location: /lib/firmware/intel/ifs_<n>/
* For e.g if there are 3 test files, they would be named in the following
* fashion:
* ff-mm-ss-01.scan
@@ -47,7 +50,7 @@
* (e.g 1, 2 or 3 in the above scenario) into the curent_batch file.
* To load ff-mm-ss-02.scan, the following command can be used::
*
- * # echo 2 > /sys/devices/virtual/misc/intel_ifs_0/current_batch
+ * # echo 2 > /sys/devices/virtual/misc/intel_ifs_<n>/current_batch
*
* The above file can also be read to know the currently loaded image.
*
@@ -69,16 +72,16 @@
* to migrate those applications to other cores before running a core test.
* It may also be necessary to redirect interrupts to other CPUs.
*
- * In all cases reading the SCAN_STATUS MSR provides details on what
+ * In all cases reading the corresponding test's STATUS MSR provides details on what
* happened. The driver makes the value of this MSR visible to applications
* via the "details" file (see below). Interrupted tests may be restarted.
*
- * The IFS driver provides sysfs interfaces via /sys/devices/virtual/misc/intel_ifs_0/
+ * The IFS driver provides sysfs interfaces via /sys/devices/virtual/misc/intel_ifs_<n>/
* to control execution:
*
* Test a specific core::
*
- * # echo <cpu#> > /sys/devices/virtual/misc/intel_ifs_0/run_test
+ * # echo <cpu#> > /sys/devices/virtual/misc/intel_ifs_<n>/run_test
*
* when HT is enabled any of the sibling cpu# can be specified to test
* its corresponding physical core. Since the tests are per physical core,
@@ -87,18 +90,18 @@
*
* For e.g. to test core corresponding to cpu5
*
- * # echo 5 > /sys/devices/virtual/misc/intel_ifs_0/run_test
+ * # echo 5 > /sys/devices/virtual/misc/intel_ifs_<n>/run_test
*
* Results of the last test is provided in /sys::
*
- * $ cat /sys/devices/virtual/misc/intel_ifs_0/status
+ * $ cat /sys/devices/virtual/misc/intel_ifs_<n>/status
* pass
*
* Status can be one of pass, fail, untested
*
* Additional details of the last test is provided by the details file::
*
- * $ cat /sys/devices/virtual/misc/intel_ifs_0/details
+ * $ cat /sys/devices/virtual/misc/intel_ifs_<n>/details
* 0x8081
*
* The details file reports the hex value of the SCAN_STATUS MSR.
--
2.25.1
Array BIST test doesn't need an IFS test image to operate unlike
the SCAN test. Consequently current_batch and image_version
files are not applicable for Array BIST IFS device instance,
clarify this in the ABI doc.
Also given that multiple tests are supported, take the opportunity
to generalize descriptions wherever applicable.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
Documentation/ABI/testing/sysfs-platform-intel-ifs | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-platform-intel-ifs b/Documentation/ABI/testing/sysfs-platform-intel-ifs
index 55991983d0d0..c0cc5ef0739a 100644
--- a/Documentation/ABI/testing/sysfs-platform-intel-ifs
+++ b/Documentation/ABI/testing/sysfs-platform-intel-ifs
@@ -21,15 +21,16 @@ Date: Nov 16 2022
KernelVersion: 6.2
Contact: "Jithu Joseph" <[email protected]>
Description: Additional information regarding the last test. The details file reports
- the hex value of the SCAN_STATUS MSR. Note that the error_code field
+ the hex value of the STATUS MSR for this test. Note that the error_code field
may contain driver defined software code not defined in the Intel SDM.
What: /sys/devices/virtual/misc/intel_ifs_<N>/image_version
Date: Nov 16 2022
KernelVersion: 6.2
Contact: "Jithu Joseph" <[email protected]>
-Description: Version (hexadecimal) of loaded IFS binary image. If no scan image
- is loaded reports "none".
+Description: Version (hexadecimal) of loaded IFS test image. If no test image
+ is loaded reports "none". Only present for device instances where a test image
+ is applicable.
What: /sys/devices/virtual/misc/intel_ifs_<N>/current_batch
Date: Nov 16 2022
@@ -39,3 +40,4 @@ Description: Write a number less than or equal to 0xff to load an IFS test image
The number written treated as the 2 digit suffix in the following file name:
/lib/firmware/intel/ifs_<N>/ff-mm-ss-02x.scan
Reading the file will provide the suffix of the currently loaded IFS test image.
+ This file is present only for device instances where a test image is applicable.
--
2.25.1
On 2/14/23 15:44, Jithu Joseph wrote:
> +/* MSR_ARRAY_BIST bit fields */
> +union ifs_array {
> + u64 data;
> + struct {
> + u32 array_bitmask :32;
> + u32 array_bank :16;
> + u32 rsvd :15;
> + u32 ctrl_result :1;
> + };
> +};
Wow, after all that, the bitfield remains! Even the totally unnecessary
parts, like the 32-bit wide bitfield in the 32-bit value. The *LEAST*
you can do is this:
struct ifs_array {
u32 array_bitmask;
u16 array_bank
u16 rsvd :15;
u16 ctrl_result :1;
};
to at least minimize the *ENTIRELY* unnecessary bitfields. I'm also not
quite sure why I'm going to the trouble of writing another one of these
things since the last set of things I suggested were not incorporated.
Or, what the obsession is with u32.
I also think the union is a bit silly. You could literally just do:
msrvals[0] = (u64 *)&activate;
or
memcpy(&msrvals[0], &activate, sizeof(activate));
and probably end up with exactly the same instructions. There's no type
safety here either way. The cast, for instance, at least makes the lack
of type safety obvious.
> +static void ifs_array_test_core(int cpu, struct device *dev)
> +{
> + union ifs_array activate, status = {0};
So, 'status' here is initialized to 0. But, 'activate'... hmmm
Here's 1 of the 4 fields getting initialized:
> + activate.array_bitmask = ~0U;
> + timeout = jiffies + HZ / 2;
> +
> + do {
> + if (time_after(jiffies, timeout)) {
> + timed_out = true;
> + break;
> + }
> +
> + msrvals[0] = activate.data;
and then the *WHOLE* union is read here. What *is* the uninitialized
member behavior of a bitfield? I actually haven't the foggiest idea
since I never use them. Is there some subtly C voodoo that initializes
the other 3 fields?
BTW, ifs_test_core() seems to be doing basically the same thing with
ifs_status.
> + atomic_set(&array_cpus_out, 0);
> + stop_core_cpuslocked(cpu, do_array_test, msrvals);
> + status.data = msrvals[1];
> +
> + if (status.ctrl_result)
> + break;
> +
> + activate.array_bitmask = status.array_bitmask;
> + activate.array_bank = status.array_bank;
> +
> + } while (status.array_bitmask);
> +
> + ifsd->scan_details = status.data;
Beautiful. It passes raw MSR values back out to userspace in sysfs.
OK, so all this union.data nonsense is to, in the end, pass two MSR
values through an array over to the do_array_test() function. That
function, in the end, just does:
+ if (cpu == first) {
+ wrmsrl(MSR_ARRAY_BIST, msrs[0]);
+ /* Pass back the result of the test */
+ rdmsrl(MSR_ARRAY_BIST, msrs[1]);
+ }
with them. It doesn't even reuse msrs[0]. It also doesn't bother to
even give them symbolic names, like command and result. The msrs[]
values are also totally hard coded.
I'd probably do something like the attached patch. It gets rid of
'data' and uses sane types for the bitfield. It does away with separate
variables and munging into/out of the msr[] array and just passes a
single command struct to the work function. It doesn't have any
uninitialized structure/bitfield fields.
Oh, and it's less code.
> + if (status.ctrl_result)
> + ifsd->status = SCAN_TEST_FAIL;
> + else if (timed_out || status.array_bitmask)
> + ifsd->status = SCAN_NOT_TESTED;
> + else
> + ifsd->status = SCAN_TEST_PASS;
> +}
> +
> /*
> * Initiate per core test. It wakes up work queue threads on the target cpu and
> * its sibling cpu. Once all sibling threads wake up, the scan test gets executed and
> @@ -253,6 +341,8 @@ int do_core_test(int cpu, struct device *dev)
> ifs_test_core(cpu, dev);
> break;
> case IFS_ARRAY:
> + ifs_array_test_core(cpu, dev);
> + break;
> default:
> return -EINVAL;
> }
On 2/15/23 08:58, Dave Hansen wrote:
> On 2/14/23 15:44, Jithu Joseph wrote:
> I'd probably do something like the attached patch. It gets rid of
> 'data' and uses sane types for the bitfield. It does away with separate
> variables and munging into/out of the msr[] array and just passes a
> single command struct to the work function. It doesn't have any
> uninitialized structure/bitfield fields.
Real patch attached now.
On 2/15/2023 8:58 AM, Dave Hansen wrote:
> On 2/14/23 15:44, Jithu Joseph wrote:
...
>
>> +static void ifs_array_test_core(int cpu, struct device *dev)
>> +{
>> + union ifs_array activate, status = {0};
>
> So, 'status' here is initialized to 0. But, 'activate'... hmmm
>
> Here's 1 of the 4 fields getting initialized:
>
>> + activate.array_bitmask = ~0U;
>> + timeout = jiffies + HZ / 2;
>> +
>> + do {
>> + if (time_after(jiffies, timeout)) {
>> + timed_out = true;
>> + break;
>> + }
>> +
>> + msrvals[0] = activate.data;
>
> and then the *WHOLE* union is read here. What *is* the uninitialized
> member behavior of a bitfield? I actually haven't the foggiest idea
> since I never use them. Is there some subtly C voodoo that initializes
> the other 3 fields?
Thanks for pointing the mistake Dave. I see the bug w.r.t not initializing activate to
zero.
Thanks Dave for the proposed patch . Let me get back after taking a detailed look
Jithu
On 2/15/2023 9:11 AM, Dave Hansen wrote:
> On 2/15/23 08:58, Dave Hansen wrote:
>> On 2/14/23 15:44, Jithu Joseph wrote:
>> I'd probably do something like the attached patch. It gets rid of
>> 'data' and uses sane types for the bitfield. It does away with separate
>> variables and munging into/out of the msr[] array and just passes a
>> single command struct to the work function. It doesn't have any
>> uninitialized structure/bitfield fields.
>
> Real patch attached now.
I did try out Dave's suggested patch. With few additional type castings, I could get it to work.
We can go with this. I will incorporate this while posting v3.
(Will await a few day for additional comments before posting v3)
Jithu
For context, the functions under discussion incorporating Dave's changes would look as below:
static int do_array_test(void *data)
{
struct ifs_array *command = data;
int cpu = smp_processor_id();
int first;
/*
* Only one logical CPU on a core needs to trigger the Array test via MSR write.
*/
first = cpumask_first(cpu_smt_mask(cpu));
if (cpu == first) {
wrmsrl(MSR_ARRAY_BIST, *((u64 *)command));
/* Pass back the result of the test */
rdmsrl(MSR_ARRAY_BIST, *((u64 *)command));
}
/* Tests complete faster if the sibling is spinning here */
wait_for_sibling_cpu(&array_cpus_out, NSEC_PER_SEC);
return 0;
}
static void ifs_array_test_core(int cpu, struct device *dev)
{
struct ifs_array command = {};
bool timed_out = false;
struct ifs_data *ifsd;
unsigned long timeout;
ifsd = ifs_get_data(dev);
command.array_bitmask = ~0U;
timeout = jiffies + HZ / 2;
do {
struct ifs_array before = command;
if (time_after(jiffies, timeout)) {
timed_out = true;
break;
}
atomic_set(&array_cpus_out, 0);
stop_core_cpuslocked(cpu, do_array_test, &command);
trace_ifs_array(cpu, *((u64 *)&before), *((u64 *)&command));
if (command.ctrl_result)
break;
} while (command.array_bitmask);
ifsd->scan_details = *((u64 *)&command);
if (command.ctrl_result)
ifsd->status = SCAN_TEST_FAIL;
else if (timed_out || command.array_bitmask)
ifsd->status = SCAN_NOT_TESTED;
else
ifsd->status = SCAN_TEST_PASS;
}
On 2/15/23 12:22, Joseph, Jithu wrote:
> trace_ifs_array(cpu, *((u64 *)&before), *((u64 *)&command));
Uhh, you control the types in the tracepoint. Just make them compatible
so you don't need casts.
On 2/15/2023 12:26 PM, Dave Hansen wrote:
> On 2/15/23 12:22, Joseph, Jithu wrote:
>> trace_ifs_array(cpu, *((u64 *)&before), *((u64 *)&command));
>
> Uhh, you control the types in the tracepoint. Just make them compatible
> so you don't need casts.
will change it to:
trace_ifs_array(cpu, before.array_bitmask, before.array_bank, *((u64 *)&command));
i.e will pass compatible types for array_list and array_bank. And for the last argument, we need to dump the whole 64 bits within "command"
into trace output . Since the suggested change replaced the union with a struct, it is simplest to cast it to u64 needed by traceoutput.
So I would prefer to keep the cast for the last argument alone.
sample trace output ...
<snip>
bash-4562 [001] ..... 761.563749: ifs_array: cpu: 10, array_list: 00007fe0, array_bank: 0101, status: 0000000200007fe0
bash-4562 [001] ..... 761.563772: ifs_array: cpu: 10, array_list: 00007fe0, array_bank: 0002, status: 0000010200007fe0
</snip>
On 2/15/23 13:13, Joseph, Jithu wrote:
>
> On 2/15/2023 12:26 PM, Dave Hansen wrote:
>> On 2/15/23 12:22, Joseph, Jithu wrote:
>>> trace_ifs_array(cpu, *((u64 *)&before), *((u64 *)&command));
>> Uhh, you control the types in the tracepoint. Just make them compatible
>> so you don't need casts.
> will change it to:
> trace_ifs_array(cpu, before.array_bitmask, before.array_bank, *((u64 *)&command));
>
> i.e will pass compatible types for array_list and array_bank. And for the last argument, we need to dump the whole 64 bits within "command"
> into trace output . Since the suggested change replaced the union with a struct, it is simplest to cast it to u64 needed by traceoutput.
> So I would prefer to keep the cast for the last argument alone.
<sigh>
Your trace even can literally be:
+ TP_STRUCT__entry(
+ __field(struct ifs_foo, before )
+ __field(struct ifs_foo, after )
+ __field( int, cpu )
+ ),
and then you can just use structure assignment or a memcpy. *That* is
what I mean by compatible types.
But, also, I'm not sure these tracepoints even make any sense. You're
passing raw MSR contents back and forth. Why not just use the MSR
tracepoints? They'll give you the same data.
On Tue, 14 Feb 2023 15:44:24 -0800
Jithu Joseph <[email protected]> wrote:
> Enable tracing support in array test flow.
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
From the tracing POV:
Reviewed-by: Steven Rostedt (Google) <[email protected]>
-- Steve
> ---
> include/trace/events/intel_ifs.h | 25 ++++++++++++++++++++++++
> drivers/platform/x86/intel/ifs/runtest.c | 1 +
> 2 files changed, 26 insertions(+)
>
> diff --git a/include/trace/events/intel_ifs.h b/include/trace/events/intel_ifs.h
> index d7353024016c..d15037943b80 100644
> --- a/include/trace/events/intel_ifs.h
On Tue, Feb 14, 2023 at 03:44:21PM -0800, Jithu Joseph wrote:
> Array BIST is a new type of core test introduced under the Intel Infield
> Scan (IFS) suite of tests.
>
> Emerald Rapids (EMR) is the first CPU to support Array BIST.
> Array BIST performs tests on some portions of the core logic such as
> caches and register files. These are different portions of the silicon
> compared to the parts tested by the first test type
> i.e Scan at Field (SAF).
>
> Make changes in the device driver init flow to register this new test
> type with the device driver framework. Each test will have its own
> sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
> accommodate for the differences in test type and how they are initiated.
>
> Upcoming patches will add actual support.
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> drivers/platform/x86/intel/ifs/ifs.h | 5 ++
> drivers/platform/x86/intel/ifs/core.c | 70 ++++++++++++++++++---------
> 2 files changed, 52 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
> index 046e39304fd5..2cef88a88aa9 100644
> --- a/drivers/platform/x86/intel/ifs/ifs.h
> +++ b/drivers/platform/x86/intel/ifs/ifs.h
> @@ -137,6 +137,11 @@
> #define SCAN_TEST_PASS 1
> #define SCAN_TEST_FAIL 2
>
> +enum test_types {
> + IFS_SAF,
> + IFS_ARRAY,
As you are using this enum to index an array, don't you need to set the
starting value to be sure it's 0?
But note, that's a horrid name of an enumerated type that is in a .h
file, either put it only in the .c file, or give it a name that makes
more sense that it belongs only to this driver.
Yes, naming is hard.
Wait, you don't even use the enumerated type anywhere in this patch
series only the value, did you mean for this to happen? Why name it
anything?
> +};
> +
> /* MSR_SCAN_HASHES_STATUS bit fields */
> union ifs_scan_hashes_status {
> u64 data;
> diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
> index 206a617c2e02..ab234620ef4c 100644
> --- a/drivers/platform/x86/intel/ifs/core.c
> +++ b/drivers/platform/x86/intel/ifs/core.c
> @@ -16,27 +16,44 @@
>
> static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
> X86_MATCH(SAPPHIRERAPIDS_X),
> + X86_MATCH(EMERALDRAPIDS_X),
> {}
> };
> MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
>
> -static struct ifs_device ifs_device = {
> - .data = {
> - .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> - .test_num = 0,
> +static struct ifs_device ifs_devices[] = {
> + [IFS_SAF] = {
> + .data = {
> + .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> + .test_num = IFS_SAF,
> + },
> + .misc = {
> + .name = "intel_ifs_0",
> + .nodename = "intel_ifs/0",
I just noticed this, a device node called "0" is not good, why do you
need this in a subdir at all?
> + .minor = MISC_DYNAMIC_MINOR,
> + },
> },
> - .misc = {
> - .name = "intel_ifs_0",
> - .nodename = "intel_ifs/0",
> - .minor = MISC_DYNAMIC_MINOR,
> + [IFS_ARRAY] = {
> + .data = {
> + .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
> + .test_num = IFS_ARRAY,
> + },
> + .misc = {
> + .name = "intel_ifs_1",
> + .nodename = "intel_ifs/1",
Again, a device node called "1"?
> + .minor = MISC_DYNAMIC_MINOR,
> + },
> },
> };
>
> +#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
Don't do this, just have a list with a NULL entry at the end, makes
things much simpler and easier over time.
> +
> static int __init ifs_init(void)
> {
> const struct x86_cpu_id *m;
> + int ndevices = 0;
> u64 msrval;
> - int ret;
> + int i;
>
> m = x86_match_cpu(ifs_cpu_ids);
> if (!m)
> @@ -51,28 +68,35 @@ static int __init ifs_init(void)
> if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
> return -ENODEV;
>
> - ifs_device.misc.groups = ifs_get_groups();
> -
> - if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
> - return -ENODEV;
> + for (i = 0; i < IFS_NUMTESTS; i++) {
> + if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit)))
> + continue;
>
> - ifs_device.data.pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
> - if (!ifs_device.data.pkg_auth)
> - return -ENOMEM;
> + ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
> + sizeof(bool), GFP_KERNEL);
> + if (!ifs_devices[i].data.pkg_auth)
> + continue;
You have a static array of a structure that contains both things that
describe the devices being used, as well as dynamic data with no real
lifespan rules. Please don't perputate this common design pattern
mistake.
Always try to make static data constant and make dynamic data dynamic
with proper reference counted lifetime rules. People converting this
code into rust in the future will thank you :)
thanks,
greg k-h
>> +enum test_types {
>> + IFS_SAF,
>> + IFS_ARRAY,
>
> As you are using this enum to index an array, don't you need to set the
> starting value to be sure it's 0?
C standard says: "The value of the first enumerator (if it does not use = constant-expression) is zero."
>> +#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
>
> Don't do this, just have a list with a NULL entry at the end, makes
> things much simpler and easier over time.
Maintainers seem to be divided over this. Personally, I'm also
in favor of a NULL entry to mark the last entry (I think it was one
of Kernighan and Plauger's style guides "End markers are better
than counts"). But the tiny footprint folks have beaten me up in
the past for wasting a whole extra structure element just to include
a terminator. :-(
-Tony
On 2/16/2023 4:40 AM, Greg KH wrote:
> On Tue, Feb 14, 2023 at 03:44:21PM -0800, Jithu Joseph wrote:
> But note, that's a horrid name of an enumerated type that is in a .h
> file, either put it only in the .c file, or give it a name that makes
> more sense that it belongs only to this driver.
>
> Yes, naming is hard.
Even for a driver local header, I agree that "enum ifs_test_type" would have been
more appropriate than "enum test_types
>
> Wait, you don't even use the enumerated type anywhere in this patch
> series only the value, did you mean for this to happen? Why name it
> anything?
>
Since I am only using the values as you said, I will remove the type and
use #defines
>> +static struct ifs_device ifs_devices[] = {
>> + [IFS_SAF] = {
>> + .data = {
>> + .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
>> + .test_num = IFS_SAF,
>> + },
>> + .misc = {
>> + .name = "intel_ifs_0",
>> + .nodename = "intel_ifs/0",
>
> I just noticed this, a device node called "0" is not good, why do you
> need this in a subdir at all?
There is no need for the device nodename in /dev to have a distinct ".nodename" from the sysfs "name"
I will remove the separate .nodename line so that /dev entries are created with the same name as
the sysfs directories.
>
>> + .minor = MISC_DYNAMIC_MINOR,
>> + },
>> },
>> - .misc = {
>> - .name = "intel_ifs_0",
>> - .nodename = "intel_ifs/0",
>> - .minor = MISC_DYNAMIC_MINOR,
>> + [IFS_ARRAY] = {
>> + .data = {
>> + .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
>> + .test_num = IFS_ARRAY,
>> + },
>> + .misc = {
>> + .name = "intel_ifs_1",
>> + .nodename = "intel_ifs/1",
>
> Again, a device node called "1"?
Will remove this distinct "nodename" too
>
>> +
>> static int __init ifs_init(void)
>> {
>> const struct x86_cpu_id *m;
>> + int ndevices = 0;
>> u64 msrval;
>> - int ret;
>> + int i;
>>
>> m = x86_match_cpu(ifs_cpu_ids);
>> if (!m)
>> @@ -51,28 +68,35 @@ static int __init ifs_init(void)
>> if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
>> return -ENODEV;
>>
>> - ifs_device.misc.groups = ifs_get_groups();
>> -
>> - if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
>> - return -ENODEV;
>> + for (i = 0; i < IFS_NUMTESTS; i++) {
>> + if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit)))
>> + continue;
>>
>> - ifs_device.data.pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
>> - if (!ifs_device.data.pkg_auth)
>> - return -ENOMEM;
>> + ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
>> + sizeof(bool), GFP_KERNEL);
>> + if (!ifs_devices[i].data.pkg_auth)
>> + continue;
>
> You have a static array of a structure that contains both things that
> describe the devices being used, as well as dynamic data with no real
> lifespan rules. Please don't perputate this common design pattern
> mistake.
>
> Always try to make static data constant and make dynamic data dynamic
> with proper reference counted lifetime rules. People converting this
> code into rust in the future will thank you :)
I may not have fully understood your comment. So pardon me if the following description
on the lifecycle of the dynamic allocated memory is not to the point.
The lifetime of this allocation matches the load time of the driver (allocated on init, freed on exit).
There are no further / allocations or freeing anywhere within the driver.
There is only a single place where this memory is used, whose access is serialized via a semaphore.
Given the above, does moving this one and only allocation to use a global pointer instead of one embedded in the structure is what is needed. ?
Jithu
On Thu, Feb 16, 2023 at 02:57:13PM -0800, Joseph, Jithu wrote:
> On 2/16/2023 4:40 AM, Greg KH wrote:
> >> + ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
> >> + sizeof(bool), GFP_KERNEL);
> >> + if (!ifs_devices[i].data.pkg_auth)
> >> + continue;
> >
> > You have a static array of a structure that contains both things that
> > describe the devices being used, as well as dynamic data with no real
> > lifespan rules. Please don't perputate this common design pattern
> > mistake.
> >
> > Always try to make static data constant and make dynamic data dynamic
> > with proper reference counted lifetime rules. People converting this
> > code into rust in the future will thank you :)
>
> I may not have fully understood your comment. So pardon me if the following description
> on the lifecycle of the dynamic allocated memory is not to the point.
>
> The lifetime of this allocation matches the load time of the driver (allocated on init, freed on exit).
> There are no further / allocations or freeing anywhere within the driver.
> There is only a single place where this memory is used, whose access is serialized via a semaphore.
But the memory is associated with "something" that has a lifetime,
right? This is either a misc device, or a cpu, or a platform device, or
something that you have to determine that you need to allocate it.
So use that as the thing you hang your dynamic data off of, don't use a
static array. Allow that static array to be put into read-only memory
(i.e. it is const and can not be changed by your code accidentally or on
purpose.)
Does that help explain things better?
thanks,
greg k-h
On 2/15/23 13:13, Joseph, Jithu wrote:
> And for the last argument, we need to dump the whole 64 bits within "command"
> into trace output .
No, no you don't.
Just split it up in to human-readable logical pieces. You don't need to
dump the whole 'command'. If you want to trace the completion mask,
then extract the mask and print *that* with a proper field name.
I actually really think this tracing should go away, *ESPECIALLY* if you
insist on dumping out raw, non-human-readable MSR values.
I say NAK on the tracing. You haven't convinced me that it's necessary
on top of what we have today (MSR tracing).
On 2/22/2023 12:12 PM, Dave Hansen wrote:
>
> I actually really think this tracing should go away, *ESPECIALLY* if you
> insist on dumping out raw, non-human-readable MSR values.
>
> I say NAK on the tracing. You haven't convinced me that it's necessary
> on top of what we have today (MSR tracing).
Thanks for the pointer on MSR trace. I agree that setting the appropriate filter ("msr == 0x105") would generate the read and write values (snip2 below).
The primary value addition for the custom trace added by this driver was readability / convenience (snip1 below). The format it is dumping today is most convenient for tracking the progress of this test from start to completion. (Two formatted input fields (wrmsr) and one output field (rdmsr) on the same line ).
Another convenience is that, by enabling the high-level intel_ifs trace, we can see all activity related to all IFS tests (and not having to explicitly remember and enable the MSRs corresponding to each of the IFS tests)
Since the trace has to be explicitly enabled (I thought it is okay to add a more convenient custom one only to be enabled for detailed analysis when required).
<Snip 1 added by driver>
bash-9411 [123] ..... 423555.355664: ifs_array: cpu: 10, array_list: ffffffff, array_bank: 0000, status: 0000010000007ff2
bash-9411 [123] ..... 423555.355858: ifs_array: cpu: 10, array_list: 00007ff2, array_bank: 0100, status: 0000000000007fe0
bash-9411 [123] ..... 423555.355891: ifs_array: cpu: 10, array_list: 00007fe0, array_bank: 0000, status: 0000010000007fe0
bash-9411 [123] ..... 423555.355923: ifs_array: cpu: 10, array_list: 00007fe0, array_bank: 0100, status: 0000000100007fe0
</snip1>
<snip2 using msr trace>
migration/10-76 [010] d..1. 423672.955522: write_msr: 105, value ffffffff
migration/10-76 [010] d..1. 423672.955525: read_msr: 105, value 10000007ff2
migration/10-76 [010] d..1. 423672.955733: write_msr: 105, value 10000007ff2
migration/10-76 [010] d..1. 423672.955736: read_msr: 105, value 7fe0
migration/10-76 [010] d..1. 423672.955783: write_msr: 105, value 7fe0
migration/10-76 [010] d..1. 423672.955786: read_msr: 105, value 10000007fe0
migration/10-76 [010] d..1. 423672.955819: write_msr: 105, value 10000007fe0
migration/10-76 [010] d..1. 423672.955822: read_msr: 105, value 100007fe0
</snip2 msr trace>
Jithu
On 2/22/23 14:07, Joseph, Jithu wrote:
> Since the trace has to be explicitly enabled (I thought it is okay to
> add a more convenient custom one only to be enabled for detailed
> analysis when required).
man perf-script
You should be able to write one to do exactly what you need in about 10
minutes. No new tracepoints, no new kernel code to maintain. Knock
yourself out with whatever conveniences you want. Just do it in userspace.
I still think this patch should go away.
On Wed, 22 Feb 2023 14:28:55 -0800
Dave Hansen <[email protected]> wrote:
> On 2/22/23 14:07, Joseph, Jithu wrote:
> > Since the trace has to be explicitly enabled (I thought it is okay to
> > add a more convenient custom one only to be enabled for detailed
> > analysis when required).
>
> man perf-script
Or do it in C with tracefs :-)
https://www.trace-cmd.org/Documentation/libtracefs/
-- Steve
>
> You should be able to write one to do exactly what you need in about 10
> minutes. No new tracepoints, no new kernel code to maintain. Knock
> yourself out with whatever conveniences you want. Just do it in userspace.
>
> I still think this patch should go away.
On 2/22/2023 2:28 PM, Dave Hansen wrote:
> On 2/22/23 14:07, Joseph, Jithu wrote:
>> Since the trace has to be explicitly enabled (I thought it is okay to
>> add a more convenient custom one only to be enabled for detailed
>> analysis when required).
>
> man perf-script
>
> You should be able to write one to do exactly what you need in about 10
> minutes. No new tracepoints, no new kernel code to maintain. Knock
Thanks for the pointers. I gather that user level tools might be able to format the
msr trace output in a more convenient way (perhaps as generated by the custom driver trace)
There is still the other convenience of not having to look-up the
MSRs addresses corresponding to all the individual tests and setting the filter on them to
analyze IFS test activity (rather than enabling it via echo 1 > /sys/kernel/debug/tracing/events/intel_ifs/enable)
Agreed that for array test it is a single MSR. For other test, it is 2 separate MSRs ... there could be additional
tests in the future.
Jithu
On 2/22/23 15:32, Joseph, Jithu wrote:
> On 2/22/2023 2:28 PM, Dave Hansen wrote:
>> On 2/22/23 14:07, Joseph, Jithu wrote:
>>> Since the trace has to be explicitly enabled (I thought it is okay to
>>> add a more convenient custom one only to be enabled for detailed
>>> analysis when required).
>> man perf-script
>>
>> You should be able to write one to do exactly what you need in about 10
>> minutes. No new tracepoints, no new kernel code to maintain. Knock
> Thanks for the pointers. I gather that user level tools might be able to format the
> msr trace output in a more convenient way (perhaps as generated by the custom driver trace)
>
> There is still the other convenience of not having to look-up the
> MSRs addresses corresponding to all the individual tests and setting the filter on them to
> analyze IFS test activity (rather than enabling it via echo 1 > /sys/kernel/debug/tracing/events/intel_ifs/enable)
Jithu, the perf-script tooling that I suggested wraps can abstract away
the sysfs interface. I suspect you might also have discovered this in
the process of exploring my (and others') suggestions.
Please go invest some time there. Feel free to come back to this thread
if you get stuck or have done your due diligence exhausted the
userspace-only path.
Changes in v3
- GregKH
- Separating read-only fields from rw fields in
struct ifs_device (patch 1/8)
- Remove the subdirectory intel_ifs/<n> for devicenode (patch 2/8)
- Replaced an enum with #define (patch 4/8)
- Dave Hansen
- Remove tracing patch
- ifs_array_test_core() (patch 6/8)
- fix an initialization bug
- other suggested changes
- Use basic types in ifs_array for first two fields. (kept
the union to avoid type castings)
v2 submission:
Link: https://lore.kernel.org/lkml/[email protected]/
Changes in v2
- remove duplicate initializations from ifs_array_test_core()
(Dave Hansen, patch 4/7)
- remove bit parsing from tracing fast path to tracing
output (Steven Rostedt, patch 5/7)
- move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
- Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)
v1 submission:
Link: https://lore.kernel.org/lkml/[email protected]/
Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by Scan at Field (SAF).
Unlike SAF, Array BIST doesn't require any test content to be loaded.
Jithu Joseph (8):
platform/x86/intel/ifs: Reorganize driver data
platform/x86/intel/ifs: IFS cleanup
x86/include/asm/msr-index.h: Add IFS Array test bits
platform/x86/intel/ifs: Introduce Array Scan test to IFS
platform/x86/intel/ifs: Sysfs interface for Array BIST
platform/x86/intel/ifs: Implement Array BIST test
platform/x86/intel/ifs: Update IFS doc
Documentation/ABI: Update IFS ABI doc
arch/x86/include/asm/msr-index.h | 2 +
drivers/platform/x86/intel/ifs/ifs.h | 62 +++++++++----
drivers/platform/x86/intel/ifs/core.c | 92 ++++++++++++++-----
drivers/platform/x86/intel/ifs/load.c | 8 +-
drivers/platform/x86/intel/ifs/runtest.c | 91 +++++++++++++++++-
drivers/platform/x86/intel/ifs/sysfs.c | 17 ++--
.../ABI/testing/sysfs-platform-intel-ifs | 8 +-
7 files changed, 221 insertions(+), 59 deletions(-)
--
2.25.1
Cleanup incorporating misc review comments
- Remove the subdirectory intel_ifs/0 for devicenode [1]
- Make plat_ifs_groups non static and use it directly without using a
function [2]
Link: https://lore.kernel.org/lkml/[email protected]/ [1]
Link: https://lore.kernel.org/lkml/[email protected]/ [2]
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 2 +-
drivers/platform/x86/intel/ifs/core.c | 6 +++---
drivers/platform/x86/intel/ifs/sysfs.c | 9 +--------
3 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index e07463c794d4..ab168ddf28f1 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -246,6 +246,6 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
extern bool *ifs_pkg_auth;
int ifs_load_firmware(struct device *dev);
int do_core_test(int cpu, struct device *dev);
-const struct attribute_group **ifs_get_groups(void);
+extern struct attribute *plat_ifs_attrs[];
#endif
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index b518b661daf0..62c44dbae757 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -20,6 +20,8 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
+ATTRIBUTE_GROUPS(plat_ifs);
+
bool *ifs_pkg_auth;
static struct ifs_device ifs_device = {
@@ -29,8 +31,8 @@ static struct ifs_device ifs_device = {
},
.misc = {
.name = "intel_ifs_0",
- .nodename = "intel_ifs/0",
.minor = MISC_DYNAMIC_MINOR,
+ .groups = plat_ifs_groups,
},
};
@@ -53,8 +55,6 @@ static int __init ifs_init(void)
if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
return -ENODEV;
- ifs_device.misc.groups = ifs_get_groups();
-
if (!(msrval & BIT(ifs_device.ro_data.integrity_cap_bit)))
return -ENODEV;
diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
index ee636a76b083..2007d8054f04 100644
--- a/drivers/platform/x86/intel/ifs/sysfs.c
+++ b/drivers/platform/x86/intel/ifs/sysfs.c
@@ -141,7 +141,7 @@ static ssize_t image_version_show(struct device *dev,
static DEVICE_ATTR_RO(image_version);
/* global scan sysfs attributes */
-static struct attribute *plat_ifs_attrs[] = {
+struct attribute *plat_ifs_attrs[] = {
&dev_attr_details.attr,
&dev_attr_status.attr,
&dev_attr_run_test.attr,
@@ -149,10 +149,3 @@ static struct attribute *plat_ifs_attrs[] = {
&dev_attr_image_version.attr,
NULL
};
-
-ATTRIBUTE_GROUPS(plat_ifs);
-
-const struct attribute_group **ifs_get_groups(void)
-{
- return plat_ifs_groups;
-}
--
2.25.1
The struct holding device driver data contained both read only(ro)
and read write(rw) fields.
Separating ro fields from rw fields was recommended as
a preferable design pattern during review[1].
Group the rw fields into a separate struct whose memory is allocated
during driver_init(). Associate it to the miscdevice being registered
by keeping it in the same container struct as the miscdevice.
Also in prepration to supporting additional tests, move ifs_pkg_auth
to a global as it is only applicable for the first test type.
Link: https://lore.kernel.org/lkml/[email protected]/ [1]
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 19 +++++++++-------
drivers/platform/x86/intel/ifs/core.c | 31 ++++++++++++++++++---------
drivers/platform/x86/intel/ifs/load.c | 8 +++----
3 files changed, 36 insertions(+), 22 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 046e39304fd5..e07463c794d4 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -197,22 +197,23 @@ union ifs_status {
#define IFS_SW_TIMEOUT 0xFD
#define IFS_SW_PARTIAL_COMPLETION 0xFE
+struct ifs_const_data {
+ int integrity_cap_bit;
+ int test_num;
+};
+
/**
* struct ifs_data - attributes related to intel IFS driver
- * @integrity_cap_bit: MSR_INTEGRITY_CAPS bit enumerating this test
* @loaded_version: stores the currently loaded ifs image version.
- * @pkg_auth: array of bool storing per package auth status
* @loaded: If a valid test binary has been loaded into the memory
* @loading_error: Error occurred on another CPU while loading image
* @valid_chunks: number of chunks which could be validated.
* @status: it holds simple status pass/fail/untested
* @scan_details: opaque scan status code from h/w
* @cur_batch: number indicating the currently loaded test file
- * @test_num: number indicating the test type
+ * @ro_info: ptr to struct holding fixed details
*/
struct ifs_data {
- int integrity_cap_bit;
- bool *pkg_auth;
int loaded_version;
bool loaded;
bool loading_error;
@@ -220,7 +221,7 @@ struct ifs_data {
int status;
u64 scan_details;
u32 cur_batch;
- int test_num;
+ struct ifs_const_data *ro_info;
};
struct ifs_work {
@@ -229,7 +230,8 @@ struct ifs_work {
};
struct ifs_device {
- struct ifs_data data;
+ struct ifs_const_data ro_data;
+ struct ifs_data *rw_data;
struct miscdevice misc;
};
@@ -238,9 +240,10 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
struct miscdevice *m = dev_get_drvdata(dev);
struct ifs_device *d = container_of(m, struct ifs_device, misc);
- return &d->data;
+ return d->rw_data;
}
+extern bool *ifs_pkg_auth;
int ifs_load_firmware(struct device *dev);
int do_core_test(int cpu, struct device *dev);
const struct attribute_group **ifs_get_groups(void);
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 206a617c2e02..b518b661daf0 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -20,8 +20,10 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
+bool *ifs_pkg_auth;
+
static struct ifs_device ifs_device = {
- .data = {
+ .ro_data = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
.test_num = 0,
},
@@ -35,8 +37,8 @@ static struct ifs_device ifs_device = {
static int __init ifs_init(void)
{
const struct x86_cpu_id *m;
+ struct ifs_data *ifsd;
u64 msrval;
- int ret;
m = x86_match_cpu(ifs_cpu_ids);
if (!m)
@@ -53,26 +55,35 @@ static int __init ifs_init(void)
ifs_device.misc.groups = ifs_get_groups();
- if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
+ if (!(msrval & BIT(ifs_device.ro_data.integrity_cap_bit)))
return -ENODEV;
- ifs_device.data.pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
- if (!ifs_device.data.pkg_auth)
+ ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
+ if (!ifs_pkg_auth)
+ return -ENOMEM;
+
+ ifsd = kzalloc(sizeof(*ifsd), GFP_KERNEL);
+ if (!ifsd)
return -ENOMEM;
- ret = misc_register(&ifs_device.misc);
- if (ret) {
- kfree(ifs_device.data.pkg_auth);
- return ret;
+ ifsd->ro_info = &ifs_device.ro_data;
+ ifs_device.rw_data = ifsd;
+
+ if (misc_register(&ifs_device.misc)) {
+ kfree(ifsd);
+ kfree(ifs_pkg_auth);
+ return -ENODEV;
}
return 0;
+
}
static void __exit ifs_exit(void)
{
misc_deregister(&ifs_device.misc);
- kfree(ifs_device.data.pkg_auth);
+ kfree(ifs_device.rw_data);
+ kfree(ifs_pkg_auth);
}
module_init(ifs_init);
diff --git a/drivers/platform/x86/intel/ifs/load.c b/drivers/platform/x86/intel/ifs/load.c
index c5c24e6fdc43..cdec3316c08d 100644
--- a/drivers/platform/x86/intel/ifs/load.c
+++ b/drivers/platform/x86/intel/ifs/load.c
@@ -192,7 +192,7 @@ static int scan_chunks_sanity_check(struct device *dev)
struct ifs_work local_work;
int curr_pkg, cpu, ret;
- memset(ifsd->pkg_auth, 0, (topology_max_packages() * sizeof(bool)));
+ memset(ifs_pkg_auth, 0, (topology_max_packages() * sizeof(bool)));
ret = validate_ifs_metadata(dev);
if (ret)
return ret;
@@ -204,7 +204,7 @@ static int scan_chunks_sanity_check(struct device *dev)
cpus_read_lock();
for_each_online_cpu(cpu) {
curr_pkg = topology_physical_package_id(cpu);
- if (ifsd->pkg_auth[curr_pkg])
+ if (ifs_pkg_auth[curr_pkg])
continue;
reinit_completion(&ifs_done);
local_work.dev = dev;
@@ -215,7 +215,7 @@ static int scan_chunks_sanity_check(struct device *dev)
ret = -EIO;
goto out;
}
- ifsd->pkg_auth[curr_pkg] = 1;
+ ifs_pkg_auth[curr_pkg] = 1;
}
ret = 0;
out:
@@ -263,7 +263,7 @@ int ifs_load_firmware(struct device *dev)
int ret = -EINVAL;
snprintf(scan_path, sizeof(scan_path), "intel/ifs_%d/%02x-%02x-%02x-%02x.scan",
- ifsd->test_num, boot_cpu_data.x86, boot_cpu_data.x86_model,
+ ifsd->ro_info->test_num, boot_cpu_data.x86, boot_cpu_data.x86_model,
boot_cpu_data.x86_stepping, ifsd->cur_batch);
ret = request_firmware_direct(&fw, scan_path, dev);
--
2.25.1
Define MSR bitfields for enumerating support for Array BIST test.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
arch/x86/include/asm/msr-index.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index d3fe82c5d6b6..ad8997773ad3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -197,6 +197,8 @@
/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
#define MSR_INTEGRITY_CAPS 0x000002d9
+#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2
+#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
--
2.25.1
The interface to trigger Array BIST test and obtain its result
is similar to the existing scan test. The only notable
difference is that, Array BIST doesn't require any test content
to be loaded. So binary load related options are not needed for
this test.
Add sysfs interface for array BIST test, the testing support will
be added by subsequent patch.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 1 +
drivers/platform/x86/intel/ifs/core.c | 2 ++
drivers/platform/x86/intel/ifs/runtest.c | 10 +++++++++-
drivers/platform/x86/intel/ifs/sysfs.c | 10 +++++++++-
4 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index b8b956e29653..f31966e291df 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -250,5 +250,6 @@ extern bool *ifs_pkg_auth;
int ifs_load_firmware(struct device *dev);
int do_core_test(int cpu, struct device *dev);
extern struct attribute *plat_ifs_attrs[];
+extern struct attribute *plat_ifs_array_attrs[];
#endif
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 2237aaba7078..c74accedfc8d 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -22,6 +22,7 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
ATTRIBUTE_GROUPS(plat_ifs);
+ATTRIBUTE_GROUPS(plat_ifs_array);
bool *ifs_pkg_auth;
@@ -45,6 +46,7 @@ static struct ifs_device ifs_devices[] = {
.misc = {
.name = "intel_ifs_1",
.minor = MISC_DYNAMIC_MINOR,
+ .groups = plat_ifs_array_groups,
},
},
};
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 0bfd8fcdd7e8..969b3e0946d5 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -236,6 +236,7 @@ static void ifs_test_core(int cpu, struct device *dev)
*/
int do_core_test(int cpu, struct device *dev)
{
+ struct ifs_data *ifsd = ifs_get_data(dev);
int ret = 0;
/* Prevent CPUs from being taken offline during the scan test */
@@ -247,7 +248,14 @@ int do_core_test(int cpu, struct device *dev)
goto out;
}
- ifs_test_core(cpu, dev);
+ switch (ifsd->ro_info->test_num) {
+ case IFS_TYPE_SAF:
+ ifs_test_core(cpu, dev);
+ break;
+ case IFS_TYPE_ARRAY_BIST:
+ default:
+ return -EINVAL;
+ }
out:
cpus_read_unlock();
return ret;
diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
index 2007d8054f04..88234798080a 100644
--- a/drivers/platform/x86/intel/ifs/sysfs.c
+++ b/drivers/platform/x86/intel/ifs/sysfs.c
@@ -75,7 +75,7 @@ static ssize_t run_test_store(struct device *dev,
if (down_interruptible(&ifs_sem))
return -EINTR;
- if (!ifsd->loaded)
+ if (ifsd->ro_info->test_num != IFS_TYPE_ARRAY_BIST && !ifsd->loaded)
rc = -EPERM;
else
rc = do_core_test(cpu, dev);
@@ -149,3 +149,11 @@ struct attribute *plat_ifs_attrs[] = {
&dev_attr_image_version.attr,
NULL
};
+
+/* global array sysfs attributes */
+struct attribute *plat_ifs_array_attrs[] = {
+ &dev_attr_details.attr,
+ &dev_attr_status.attr,
+ &dev_attr_run_test.attr,
+ NULL
+};
--
2.25.1
Array BIST test (for a particlular core) is triggered by writing
to MSR_ARRAY_BIST from one sibling of the core.
This will initiate a test for all supported arrays on that
CPU. Array BIST test may be aborted before completing all the
arrays in the event of an interrupt or other reasons.
In this case, kernel will restart the test from that point
onwards. Array test will also be aborted when the test fails,
in which case the test is stopped immediately without further
retry.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 12 ++++
drivers/platform/x86/intel/ifs/runtest.c | 81 ++++++++++++++++++++++++
2 files changed, 93 insertions(+)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index f31966e291df..1228101de201 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -127,6 +127,7 @@
#include <linux/device.h>
#include <linux/miscdevice.h>
+#define MSR_ARRAY_BIST 0x00000105
#define MSR_COPY_SCAN_HASHES 0x000002c2
#define MSR_SCAN_HASHES_STATUS 0x000002c3
#define MSR_AUTHENTICATE_AND_COPY_CHUNK 0x000002c4
@@ -192,6 +193,17 @@ union ifs_status {
};
};
+/* MSR_ARRAY_BIST bit fields */
+union ifs_array {
+ u64 data;
+ struct {
+ u32 array_bitmask;
+ u16 array_bank;
+ u16 rsvd :15;
+ u16 ctrl_result :1;
+ };
+};
+
/*
* Driver populated error-codes
* 0xFD: Test timed out before completing all the chunks.
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 969b3e0946d5..3a5442796c7d 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -229,6 +229,85 @@ static void ifs_test_core(int cpu, struct device *dev)
}
}
+#define SPINUNIT 100 /* 100 nsec */
+static atomic_t array_cpus_out;
+
+/*
+ * Simplified cpu sibling rendezvous loop based on microcode loader __wait_for_cpus()
+ */
+static void wait_for_sibling_cpu(atomic_t *t, long long timeout)
+{
+ int cpu = smp_processor_id();
+ const struct cpumask *smt_mask = cpu_smt_mask(cpu);
+ int all_cpus = cpumask_weight(smt_mask);
+
+ atomic_inc(t);
+ while (atomic_read(t) < all_cpus) {
+ if (timeout < SPINUNIT)
+ return;
+ ndelay(SPINUNIT);
+ timeout -= SPINUNIT;
+ touch_nmi_watchdog();
+ }
+}
+
+static int do_array_test(void *data)
+{
+ union ifs_array *command = data;
+ int cpu = smp_processor_id();
+ int first;
+
+ /*
+ * Only one logical CPU on a core needs to trigger the Array test via MSR write.
+ */
+ first = cpumask_first(cpu_smt_mask(cpu));
+
+ if (cpu == first) {
+ wrmsrl(MSR_ARRAY_BIST, command->data);
+ /* Pass back the result of the test */
+ rdmsrl(MSR_ARRAY_BIST, command->data);
+ }
+
+ /* Tests complete faster if the sibling is spinning here */
+ wait_for_sibling_cpu(&array_cpus_out, NSEC_PER_SEC);
+
+ return 0;
+}
+
+static void ifs_array_test_core(int cpu, struct device *dev)
+{
+ union ifs_array command = {};
+ bool timed_out = false;
+ struct ifs_data *ifsd;
+ unsigned long timeout;
+
+ ifsd = ifs_get_data(dev);
+
+ command.array_bitmask = ~0U;
+ timeout = jiffies + HZ / 2;
+
+ do {
+ if (time_after(jiffies, timeout)) {
+ timed_out = true;
+ break;
+ }
+ atomic_set(&array_cpus_out, 0);
+ stop_core_cpuslocked(cpu, do_array_test, &command);
+
+ if (command.ctrl_result)
+ break;
+ } while (command.array_bitmask);
+
+ ifsd->scan_details = command.data;
+
+ if (command.ctrl_result)
+ ifsd->status = SCAN_TEST_FAIL;
+ else if (timed_out || command.array_bitmask)
+ ifsd->status = SCAN_NOT_TESTED;
+ else
+ ifsd->status = SCAN_TEST_PASS;
+}
+
/*
* Initiate per core test. It wakes up work queue threads on the target cpu and
* its sibling cpu. Once all sibling threads wake up, the scan test gets executed and
@@ -253,6 +332,8 @@ int do_core_test(int cpu, struct device *dev)
ifs_test_core(cpu, dev);
break;
case IFS_TYPE_ARRAY_BIST:
+ ifs_array_test_core(cpu, dev);
+ break;
default:
return -EINVAL;
}
--
2.25.1
Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by the first test type
i.e Scan at Field (SAF).
Make changes in the device driver init flow to register this new test
type with the device driver framework. Each test will have its own
sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
accommodate for the differences in test type and how they are initiated.
Upcoming patches will add actual support.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 3 +
drivers/platform/x86/intel/ifs/core.c | 85 +++++++++++++++++++--------
2 files changed, 62 insertions(+), 26 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index ab168ddf28f1..b8b956e29653 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -137,6 +137,9 @@
#define SCAN_TEST_PASS 1
#define SCAN_TEST_FAIL 2
+#define IFS_TYPE_SAF 0
+#define IFS_TYPE_ARRAY_BIST 1
+
/* MSR_SCAN_HASHES_STATUS bit fields */
union ifs_scan_hashes_status {
u64 data;
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 62c44dbae757..2237aaba7078 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -16,6 +16,7 @@
static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
X86_MATCH(SAPPHIRERAPIDS_X),
+ X86_MATCH(EMERALDRAPIDS_X),
{}
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
@@ -24,23 +25,51 @@ ATTRIBUTE_GROUPS(plat_ifs);
bool *ifs_pkg_auth;
-static struct ifs_device ifs_device = {
- .ro_data = {
- .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
- .test_num = 0,
+static struct ifs_device ifs_devices[] = {
+ [IFS_TYPE_SAF] = {
+ .ro_data = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
+ .test_num = IFS_TYPE_SAF,
+ },
+ .misc = {
+ .name = "intel_ifs_0",
+ .minor = MISC_DYNAMIC_MINOR,
+ .groups = plat_ifs_groups,
+ },
},
- .misc = {
- .name = "intel_ifs_0",
- .minor = MISC_DYNAMIC_MINOR,
- .groups = plat_ifs_groups,
+ [IFS_TYPE_ARRAY_BIST] = {
+ .ro_data = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
+ .test_num = IFS_TYPE_ARRAY_BIST,
+ },
+ .misc = {
+ .name = "intel_ifs_1",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
};
+#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
+
+static void ifs_cleanup(void)
+{
+ int i;
+
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (ifs_devices[i].misc.this_device) {
+ misc_deregister(&ifs_devices[i].misc);
+ kfree(ifs_devices[i].rw_data);
+ }
+ }
+ kfree(ifs_pkg_auth);
+}
+
static int __init ifs_init(void)
{
const struct x86_cpu_id *m;
struct ifs_data *ifsd;
u64 msrval;
+ int i, ret;
m = x86_match_cpu(ifs_cpu_ids);
if (!m)
@@ -55,35 +84,39 @@ static int __init ifs_init(void)
if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
return -ENODEV;
- if (!(msrval & BIT(ifs_device.ro_data.integrity_cap_bit)))
- return -ENODEV;
-
ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
if (!ifs_pkg_auth)
return -ENOMEM;
- ifsd = kzalloc(sizeof(*ifsd), GFP_KERNEL);
- if (!ifsd)
- return -ENOMEM;
-
- ifsd->ro_info = &ifs_device.ro_data;
- ifs_device.rw_data = ifsd;
-
- if (misc_register(&ifs_device.misc)) {
- kfree(ifsd);
- kfree(ifs_pkg_auth);
- return -ENODEV;
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ ifsd = NULL;
+ if (!(msrval & BIT(ifs_devices[i].ro_data.integrity_cap_bit)))
+ continue;
+
+ ifsd = kzalloc(sizeof(*ifsd), GFP_KERNEL);
+ if (!ifsd) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+ ifsd->ro_info = &ifs_devices[i].ro_data;
+ ifs_devices[i].rw_data = ifsd;
+
+ if (misc_register(&ifs_devices[i].misc)) {
+ ret = -ENODEV;
+ kfree(ifsd);
+ goto err_exit;
+ }
}
-
return 0;
+err_exit:
+ ifs_cleanup();
+ return ret;
}
static void __exit ifs_exit(void)
{
- misc_deregister(&ifs_device.misc);
- kfree(ifs_device.rw_data);
- kfree(ifs_pkg_auth);
+ ifs_cleanup();
}
module_init(ifs_init);
--
2.25.1
Array BIST is the second test supported by IFS. Modify IFS doc
entry to be more general.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 1228101de201..34f68778c8b5 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -17,7 +17,7 @@
* In Field Scan (IFS) is a hardware feature to run circuit level tests on
* a CPU core to detect problems that are not caught by parity or ECC checks.
* Future CPUs will support more than one type of test which will show up
- * with a new platform-device instance-id, for now only .0 is exposed.
+ * with a new platform-device instance-id.
*
*
* IFS Image
@@ -25,7 +25,10 @@
*
* Intel provides a firmware file containing the scan tests via
* github [#f1]_. Similar to microcode there is a separate file for each
- * family-model-stepping.
+ * family-model-stepping. IFS Images are not applicable for some test types.
+ * Wherever applicable the sysfs directory would provide a "current_batch" file
+ * (see below) for loading the image.
+ *
*
* IFS Image Loading
* -----------------
@@ -35,7 +38,7 @@
* SHA hashes for the test. Then the tests themselves. Status MSRs provide
* feedback on the success/failure of these steps.
*
- * The test files are kept in a fixed location: /lib/firmware/intel/ifs_0/
+ * The test files are kept in a fixed location: /lib/firmware/intel/ifs_<n>/
* For e.g if there are 3 test files, they would be named in the following
* fashion:
* ff-mm-ss-01.scan
@@ -47,7 +50,7 @@
* (e.g 1, 2 or 3 in the above scenario) into the curent_batch file.
* To load ff-mm-ss-02.scan, the following command can be used::
*
- * # echo 2 > /sys/devices/virtual/misc/intel_ifs_0/current_batch
+ * # echo 2 > /sys/devices/virtual/misc/intel_ifs_<n>/current_batch
*
* The above file can also be read to know the currently loaded image.
*
@@ -69,16 +72,16 @@
* to migrate those applications to other cores before running a core test.
* It may also be necessary to redirect interrupts to other CPUs.
*
- * In all cases reading the SCAN_STATUS MSR provides details on what
+ * In all cases reading the corresponding test's STATUS MSR provides details on what
* happened. The driver makes the value of this MSR visible to applications
* via the "details" file (see below). Interrupted tests may be restarted.
*
- * The IFS driver provides sysfs interfaces via /sys/devices/virtual/misc/intel_ifs_0/
+ * The IFS driver provides sysfs interfaces via /sys/devices/virtual/misc/intel_ifs_<n>/
* to control execution:
*
* Test a specific core::
*
- * # echo <cpu#> > /sys/devices/virtual/misc/intel_ifs_0/run_test
+ * # echo <cpu#> > /sys/devices/virtual/misc/intel_ifs_<n>/run_test
*
* when HT is enabled any of the sibling cpu# can be specified to test
* its corresponding physical core. Since the tests are per physical core,
@@ -87,21 +90,21 @@
*
* For e.g. to test core corresponding to cpu5
*
- * # echo 5 > /sys/devices/virtual/misc/intel_ifs_0/run_test
+ * # echo 5 > /sys/devices/virtual/misc/intel_ifs_<n>/run_test
*
* Results of the last test is provided in /sys::
*
- * $ cat /sys/devices/virtual/misc/intel_ifs_0/status
+ * $ cat /sys/devices/virtual/misc/intel_ifs_<n>/status
* pass
*
* Status can be one of pass, fail, untested
*
* Additional details of the last test is provided by the details file::
*
- * $ cat /sys/devices/virtual/misc/intel_ifs_0/details
+ * $ cat /sys/devices/virtual/misc/intel_ifs_<n>/details
* 0x8081
*
- * The details file reports the hex value of the SCAN_STATUS MSR.
+ * The details file reports the hex value of the test specific status MSR.
* Hardware defined error codes are documented in volume 4 of the Intel
* Software Developer's Manual but the error_code field may contain one of
* the following driver defined software codes:
--
2.25.1
Array BIST test doesn't need an IFS test image to operate unlike
the SCAN test. Consequently current_batch and image_version
files are not applicable for Array BIST IFS device instance,
clarify this in the ABI doc.
Also given that multiple tests are supported, take the opportunity
to generalize descriptions wherever applicable.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
Documentation/ABI/testing/sysfs-platform-intel-ifs | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-platform-intel-ifs b/Documentation/ABI/testing/sysfs-platform-intel-ifs
index 55991983d0d0..c0cc5ef0739a 100644
--- a/Documentation/ABI/testing/sysfs-platform-intel-ifs
+++ b/Documentation/ABI/testing/sysfs-platform-intel-ifs
@@ -21,15 +21,16 @@ Date: Nov 16 2022
KernelVersion: 6.2
Contact: "Jithu Joseph" <[email protected]>
Description: Additional information regarding the last test. The details file reports
- the hex value of the SCAN_STATUS MSR. Note that the error_code field
+ the hex value of the STATUS MSR for this test. Note that the error_code field
may contain driver defined software code not defined in the Intel SDM.
What: /sys/devices/virtual/misc/intel_ifs_<N>/image_version
Date: Nov 16 2022
KernelVersion: 6.2
Contact: "Jithu Joseph" <[email protected]>
-Description: Version (hexadecimal) of loaded IFS binary image. If no scan image
- is loaded reports "none".
+Description: Version (hexadecimal) of loaded IFS test image. If no test image
+ is loaded reports "none". Only present for device instances where a test image
+ is applicable.
What: /sys/devices/virtual/misc/intel_ifs_<N>/current_batch
Date: Nov 16 2022
@@ -39,3 +40,4 @@ Description: Write a number less than or equal to 0xff to load an IFS test image
The number written treated as the 2 digit suffix in the following file name:
/lib/firmware/intel/ifs_<N>/ff-mm-ss-02x.scan
Reading the file will provide the suffix of the currently loaded IFS test image.
+ This file is present only for device instances where a test image is applicable.
--
2.25.1
Hi Jithu,
On 3/1/23 02:59, Jithu Joseph wrote:
> Changes in v3
> - GregKH
> - Separating read-only fields from rw fields in
> struct ifs_device (patch 1/8)
> - Remove the subdirectory intel_ifs/<n> for devicenode (patch 2/8)
> - Replaced an enum with #define (patch 4/8)
> - Dave Hansen
> - Remove tracing patch
> - ifs_array_test_core() (patch 6/8)
> - fix an initialization bug
> - other suggested changes
> - Use basic types in ifs_array for first two fields. (kept
> the union to avoid type castings)
Thank you for the new version. Given all the feedback on
the previous 2 versions I'm going to wait a bit to see if more
feedback comes in before reviewing this myself.
Regards,
Hans
> v2 submission:
> Link: https://lore.kernel.org/lkml/[email protected]/
>
> Changes in v2
> - remove duplicate initializations from ifs_array_test_core()
> (Dave Hansen, patch 4/7)
> - remove bit parsing from tracing fast path to tracing
> output (Steven Rostedt, patch 5/7)
> - move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
> exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
> - Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)
>
> v1 submission:
> Link: https://lore.kernel.org/lkml/[email protected]/
>
> Array BIST is a new type of core test introduced under the Intel Infield
> Scan (IFS) suite of tests.
>
> Emerald Rapids (EMR) is the first CPU to support Array BIST.
> Array BIST performs tests on some portions of the core logic such as
> caches and register files. These are different portions of the silicon
> compared to the parts tested by Scan at Field (SAF).
>
> Unlike SAF, Array BIST doesn't require any test content to be loaded.
>
> Jithu Joseph (8):
> platform/x86/intel/ifs: Reorganize driver data
> platform/x86/intel/ifs: IFS cleanup
> x86/include/asm/msr-index.h: Add IFS Array test bits
> platform/x86/intel/ifs: Introduce Array Scan test to IFS
> platform/x86/intel/ifs: Sysfs interface for Array BIST
> platform/x86/intel/ifs: Implement Array BIST test
> platform/x86/intel/ifs: Update IFS doc
> Documentation/ABI: Update IFS ABI doc
>
> arch/x86/include/asm/msr-index.h | 2 +
> drivers/platform/x86/intel/ifs/ifs.h | 62 +++++++++----
> drivers/platform/x86/intel/ifs/core.c | 92 ++++++++++++++-----
> drivers/platform/x86/intel/ifs/load.c | 8 +-
> drivers/platform/x86/intel/ifs/runtest.c | 91 +++++++++++++++++-
> drivers/platform/x86/intel/ifs/sysfs.c | 17 ++--
> .../ABI/testing/sysfs-platform-intel-ifs | 8 +-
> 7 files changed, 221 insertions(+), 59 deletions(-)
>
Hi Jithu,
On 3/1/23 02:59, Jithu Joseph wrote:
> The struct holding device driver data contained both read only(ro)
> and read write(rw) fields.
>
> Separating ro fields from rw fields was recommended as
> a preferable design pattern during review[1].
>
> Group the rw fields into a separate struct whose memory is allocated
> during driver_init(). Associate it to the miscdevice being registered
> by keeping it in the same container struct as the miscdevice.
>
> Also in prepration to supporting additional tests, move ifs_pkg_auth
> to a global as it is only applicable for the first test type.
If you are writing "Also ..." into a commit message and the
changes for the "Also ..." are more then a single line change,
then that change really should be split out into a separate patch.
Please split the "move ifs_pkg_auth to a global" changes into their
own separate patch.
>
> Link: https://lore.kernel.org/lkml/[email protected]/ [1]
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> drivers/platform/x86/intel/ifs/ifs.h | 19 +++++++++-------
> drivers/platform/x86/intel/ifs/core.c | 31 ++++++++++++++++++---------
> drivers/platform/x86/intel/ifs/load.c | 8 +++----
> 3 files changed, 36 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
> index 046e39304fd5..e07463c794d4 100644
> --- a/drivers/platform/x86/intel/ifs/ifs.h
> +++ b/drivers/platform/x86/intel/ifs/ifs.h
> @@ -197,22 +197,23 @@ union ifs_status {
> #define IFS_SW_TIMEOUT 0xFD
> #define IFS_SW_PARTIAL_COMPLETION 0xFE
>
> +struct ifs_const_data {
> + int integrity_cap_bit;
> + int test_num;
> +};
> +
This is a description of the specific capabilties / bits of
the IFS on e.g. Saphire Rapids, so please name this appropriately
for example:
struct ifs_hw_caps {
int integrity_cap_bit;
int test_num;
};
> /**
> * struct ifs_data - attributes related to intel IFS driver
> - * @integrity_cap_bit: MSR_INTEGRITY_CAPS bit enumerating this test
> * @loaded_version: stores the currently loaded ifs image version.
> - * @pkg_auth: array of bool storing per package auth status
> * @loaded: If a valid test binary has been loaded into the memory
> * @loading_error: Error occurred on another CPU while loading image
> * @valid_chunks: number of chunks which could be validated.
> * @status: it holds simple status pass/fail/untested
> * @scan_details: opaque scan status code from h/w
> * @cur_batch: number indicating the currently loaded test file
> - * @test_num: number indicating the test type
> + * @ro_info: ptr to struct holding fixed details
> */
> struct ifs_data {
> - int integrity_cap_bit;
> - bool *pkg_auth;
> int loaded_version;
> bool loaded;
> bool loading_error;
> @@ -220,7 +221,7 @@ struct ifs_data {
> int status;
> u64 scan_details;
> u32 cur_batch;
> - int test_num;
> + struct ifs_const_data *ro_info;
> };
>
> struct ifs_work {
> @@ -229,7 +230,8 @@ struct ifs_work {
> };
>
> struct ifs_device {
> - struct ifs_data data;
> + struct ifs_const_data ro_data;
> + struct ifs_data *rw_data;
> struct miscdevice misc;
> };
>
You got this exactly the wrong way around, there should be a single
static const struct ifs_hw_caps saphire_rapids_caps = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
.test_num = 0,
};
And then struct ifs_device { } should have a "const struct ifs_hw_caps *hw_caps"
which gets initialized to point to &saphire_rapids_caps. So that your const
data is actually const.
Where as since the r/w data's lifetime is couple to the misc-device lifetime
there is no need to dynamically allocate it just keep that embedded, so that
together you get:
struct ifs_device {
const struct ifs_hw_caps *hw_caps;
struct ifs_data data;
struct miscdevice misc;
};
Regards,
Hans
> @@ -238,9 +240,10 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
> struct miscdevice *m = dev_get_drvdata(dev);
> struct ifs_device *d = container_of(m, struct ifs_device, misc);
>
> - return &d->data;
> + return d->rw_data;
> }
>
> +extern bool *ifs_pkg_auth;
> int ifs_load_firmware(struct device *dev);
> int do_core_test(int cpu, struct device *dev);
> const struct attribute_group **ifs_get_groups(void);
> diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
> index 206a617c2e02..b518b661daf0 100644
> --- a/drivers/platform/x86/intel/ifs/core.c
> +++ b/drivers/platform/x86/intel/ifs/core.c
> @@ -20,8 +20,10 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
> };
> MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
>
> +bool *ifs_pkg_auth;
> +
> static struct ifs_device ifs_device = {
> - .data = {
> + .ro_data = {
> .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> .test_num = 0,
> },
> @@ -35,8 +37,8 @@ static struct ifs_device ifs_device = {
> static int __init ifs_init(void)
> {
> const struct x86_cpu_id *m;
> + struct ifs_data *ifsd;
> u64 msrval;
> - int ret;
>
> m = x86_match_cpu(ifs_cpu_ids);
> if (!m)
> @@ -53,26 +55,35 @@ static int __init ifs_init(void)
>
> ifs_device.misc.groups = ifs_get_groups();
>
> - if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
> + if (!(msrval & BIT(ifs_device.ro_data.integrity_cap_bit)))
> return -ENODEV;
>
> - ifs_device.data.pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
> - if (!ifs_device.data.pkg_auth)
> + ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
> + if (!ifs_pkg_auth)
> + return -ENOMEM;
> +
> + ifsd = kzalloc(sizeof(*ifsd), GFP_KERNEL);
> + if (!ifsd)
> return -ENOMEM;
>
> - ret = misc_register(&ifs_device.misc);
> - if (ret) {
> - kfree(ifs_device.data.pkg_auth);
> - return ret;
> + ifsd->ro_info = &ifs_device.ro_data;
> + ifs_device.rw_data = ifsd;
> +
> + if (misc_register(&ifs_device.misc)) {
> + kfree(ifsd);
> + kfree(ifs_pkg_auth);
> + return -ENODEV;
> }
>
> return 0;
> +
> }
>
> static void __exit ifs_exit(void)
> {
> misc_deregister(&ifs_device.misc);
> - kfree(ifs_device.data.pkg_auth);
> + kfree(ifs_device.rw_data);
> + kfree(ifs_pkg_auth);
> }
>
> module_init(ifs_init);
> diff --git a/drivers/platform/x86/intel/ifs/load.c b/drivers/platform/x86/intel/ifs/load.c
> index c5c24e6fdc43..cdec3316c08d 100644
> --- a/drivers/platform/x86/intel/ifs/load.c
> +++ b/drivers/platform/x86/intel/ifs/load.c
> @@ -192,7 +192,7 @@ static int scan_chunks_sanity_check(struct device *dev)
> struct ifs_work local_work;
> int curr_pkg, cpu, ret;
>
> - memset(ifsd->pkg_auth, 0, (topology_max_packages() * sizeof(bool)));
> + memset(ifs_pkg_auth, 0, (topology_max_packages() * sizeof(bool)));
> ret = validate_ifs_metadata(dev);
> if (ret)
> return ret;
> @@ -204,7 +204,7 @@ static int scan_chunks_sanity_check(struct device *dev)
> cpus_read_lock();
> for_each_online_cpu(cpu) {
> curr_pkg = topology_physical_package_id(cpu);
> - if (ifsd->pkg_auth[curr_pkg])
> + if (ifs_pkg_auth[curr_pkg])
> continue;
> reinit_completion(&ifs_done);
> local_work.dev = dev;
> @@ -215,7 +215,7 @@ static int scan_chunks_sanity_check(struct device *dev)
> ret = -EIO;
> goto out;
> }
> - ifsd->pkg_auth[curr_pkg] = 1;
> + ifs_pkg_auth[curr_pkg] = 1;
> }
> ret = 0;
> out:
> @@ -263,7 +263,7 @@ int ifs_load_firmware(struct device *dev)
> int ret = -EINVAL;
>
> snprintf(scan_path, sizeof(scan_path), "intel/ifs_%d/%02x-%02x-%02x-%02x.scan",
> - ifsd->test_num, boot_cpu_data.x86, boot_cpu_data.x86_model,
> + ifsd->ro_info->test_num, boot_cpu_data.x86, boot_cpu_data.x86_model,
> boot_cpu_data.x86_stepping, ifsd->cur_batch);
>
> ret = request_firmware_direct(&fw, scan_path, dev);
Hi,
On 3/1/23 02:59, Jithu Joseph wrote:
> Cleanup incorporating misc review comments
>
> - Remove the subdirectory intel_ifs/0 for devicenode [1]
> - Make plat_ifs_groups non static and use it directly without using a
> function [2]
>
> Link: https://lore.kernel.org/lkml/[email protected]/ [1]
> Link: https://lore.kernel.org/lkml/[email protected]/ [2]
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
Thanks, patch looks good to me:
Reviewed-by: Hans de Goede <[email protected]>
Please add my Reviewed-by to this patch for the next version of
the series, so that I know which patches I have already reviewed.
Regards,
Hans
> ---
> drivers/platform/x86/intel/ifs/ifs.h | 2 +-
> drivers/platform/x86/intel/ifs/core.c | 6 +++---
> drivers/platform/x86/intel/ifs/sysfs.c | 9 +--------
> 3 files changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
> index e07463c794d4..ab168ddf28f1 100644
> --- a/drivers/platform/x86/intel/ifs/ifs.h
> +++ b/drivers/platform/x86/intel/ifs/ifs.h
> @@ -246,6 +246,6 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
> extern bool *ifs_pkg_auth;
> int ifs_load_firmware(struct device *dev);
> int do_core_test(int cpu, struct device *dev);
> -const struct attribute_group **ifs_get_groups(void);
> +extern struct attribute *plat_ifs_attrs[];
>
> #endif
> diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
> index b518b661daf0..62c44dbae757 100644
> --- a/drivers/platform/x86/intel/ifs/core.c
> +++ b/drivers/platform/x86/intel/ifs/core.c
> @@ -20,6 +20,8 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
> };
> MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
>
> +ATTRIBUTE_GROUPS(plat_ifs);
> +
> bool *ifs_pkg_auth;
>
> static struct ifs_device ifs_device = {
> @@ -29,8 +31,8 @@ static struct ifs_device ifs_device = {
> },
> .misc = {
> .name = "intel_ifs_0",
> - .nodename = "intel_ifs/0",
> .minor = MISC_DYNAMIC_MINOR,
> + .groups = plat_ifs_groups,
> },
> };
>
> @@ -53,8 +55,6 @@ static int __init ifs_init(void)
> if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
> return -ENODEV;
>
> - ifs_device.misc.groups = ifs_get_groups();
> -
> if (!(msrval & BIT(ifs_device.ro_data.integrity_cap_bit)))
> return -ENODEV;
>
> diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
> index ee636a76b083..2007d8054f04 100644
> --- a/drivers/platform/x86/intel/ifs/sysfs.c
> +++ b/drivers/platform/x86/intel/ifs/sysfs.c
> @@ -141,7 +141,7 @@ static ssize_t image_version_show(struct device *dev,
> static DEVICE_ATTR_RO(image_version);
>
> /* global scan sysfs attributes */
> -static struct attribute *plat_ifs_attrs[] = {
> +struct attribute *plat_ifs_attrs[] = {
> &dev_attr_details.attr,
> &dev_attr_status.attr,
> &dev_attr_run_test.attr,
> @@ -149,10 +149,3 @@ static struct attribute *plat_ifs_attrs[] = {
> &dev_attr_image_version.attr,
> NULL
> };
> -
> -ATTRIBUTE_GROUPS(plat_ifs);
> -
> -const struct attribute_group **ifs_get_groups(void)
> -{
> - return plat_ifs_groups;
> -}
Hi,
On 3/1/23 02:59, Jithu Joseph wrote:
> Define MSR bitfields for enumerating support for Array BIST test.
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> arch/x86/include/asm/msr-index.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index d3fe82c5d6b6..ad8997773ad3 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -197,6 +197,8 @@
>
> /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
> #define MSR_INTEGRITY_CAPS 0x000002d9
> +#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2
> +#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
> #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
> #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
>
Thanks, patch looks good to me:
Reviewed-by: Hans de Goede <[email protected]>
Regards,
Hans
Hi,
On 3/1/23 02:59, Jithu Joseph wrote:
> Array BIST is a new type of core test introduced under the Intel Infield
> Scan (IFS) suite of tests.
>
> Emerald Rapids (EMR) is the first CPU to support Array BIST.
> Array BIST performs tests on some portions of the core logic such as
> caches and register files. These are different portions of the silicon
> compared to the parts tested by the first test type
> i.e Scan at Field (SAF).
>
> Make changes in the device driver init flow to register this new test
> type with the device driver framework. Each test will have its own
> sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
> accommodate for the differences in test type and how they are initiated.
>
> Upcoming patches will add actual support.
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> drivers/platform/x86/intel/ifs/ifs.h | 3 +
> drivers/platform/x86/intel/ifs/core.c | 85 +++++++++++++++++++--------
> 2 files changed, 62 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
> index ab168ddf28f1..b8b956e29653 100644
> --- a/drivers/platform/x86/intel/ifs/ifs.h
> +++ b/drivers/platform/x86/intel/ifs/ifs.h
> @@ -137,6 +137,9 @@
> #define SCAN_TEST_PASS 1
> #define SCAN_TEST_FAIL 2
>
> +#define IFS_TYPE_SAF 0
> +#define IFS_TYPE_ARRAY_BIST 1
> +
> /* MSR_SCAN_HASHES_STATUS bit fields */
> union ifs_scan_hashes_status {
> u64 data;
> diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
> index 62c44dbae757..2237aaba7078 100644
> --- a/drivers/platform/x86/intel/ifs/core.c
> +++ b/drivers/platform/x86/intel/ifs/core.c
> @@ -16,6 +16,7 @@
>
> static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
> X86_MATCH(SAPPHIRERAPIDS_X),
> + X86_MATCH(EMERALDRAPIDS_X),
> {}
> };
> MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
Note you can add driver_data to a match table like this. What you should
do here is use the driver data to point to the const ifs_hw_caps discussed
before, so what you get here is:
#define X86_MATCH(model, data) \
X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
INTEL_FAM6_##model, X86_FEATURE_CORE_CAPABILITIES, (unsigned long)(data))
static const struct ifs_hw_caps saphire_rapids_caps = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
.test_num = 0,
};
static const struct ifs_hw_caps emerald_rapids_caps = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
.test_num = 0,
};
static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
X86_MATCH(SAPPHIRERAPIDS_X, &saphire_rapids_caps),
X86_MATCH(EMERALDRAPIDS_X, &emerald_rapids_caps),
{}
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
and then drop all the code related to having an array of ifs_device structs
(of which only 1 will ever get used) and instead at the beginning of
ifs_init(void), after:
m = x86_match_cpu(ifs_cpu_ids);
if (!m)
return -ENODEV;
add:
ifs_device.hwcaps = (const struct ifs_hw_caps *)m->driver_data;
And then you can pretty much drop all the rest of this patch and we
end up with much nicer code for differentiating between the models :)
Regards,
Hans
> @@ -24,23 +25,51 @@ ATTRIBUTE_GROUPS(plat_ifs);
>
> bool *ifs_pkg_auth;
>
> -static struct ifs_device ifs_device = {
> - .ro_data = {
> - .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> - .test_num = 0,
> +static struct ifs_device ifs_devices[] = {
> + [IFS_TYPE_SAF] = {
> + .ro_data = {
> + .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> + .test_num = IFS_TYPE_SAF,
> + },
> + .misc = {
> + .name = "intel_ifs_0",
> + .minor = MISC_DYNAMIC_MINOR,
> + .groups = plat_ifs_groups,
> + },
> },
> - .misc = {
> - .name = "intel_ifs_0",
> - .minor = MISC_DYNAMIC_MINOR,
> - .groups = plat_ifs_groups,
> + [IFS_TYPE_ARRAY_BIST] = {
> + .ro_data = {
> + .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
> + .test_num = IFS_TYPE_ARRAY_BIST,
> + },
> + .misc = {
> + .name = "intel_ifs_1",
> + .minor = MISC_DYNAMIC_MINOR,
> + },
> },
> };
>
> +#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
> +
> +static void ifs_cleanup(void)
> +{
> + int i;
> +
> + for (i = 0; i < IFS_NUMTESTS; i++) {
> + if (ifs_devices[i].misc.this_device) {
> + misc_deregister(&ifs_devices[i].misc);
> + kfree(ifs_devices[i].rw_data);
> + }
> + }
> + kfree(ifs_pkg_auth);
> +}
> +
> static int __init ifs_init(void)
> {
> const struct x86_cpu_id *m;
> struct ifs_data *ifsd;
> u64 msrval;
> + int i, ret;
>
> m = x86_match_cpu(ifs_cpu_ids);
> if (!m)
> @@ -55,35 +84,39 @@ static int __init ifs_init(void)
> if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
> return -ENODEV;
>
> - if (!(msrval & BIT(ifs_device.ro_data.integrity_cap_bit)))
> - return -ENODEV;
> -
> ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
> if (!ifs_pkg_auth)
> return -ENOMEM;
>
> - ifsd = kzalloc(sizeof(*ifsd), GFP_KERNEL);
> - if (!ifsd)
> - return -ENOMEM;
> -
> - ifsd->ro_info = &ifs_device.ro_data;
> - ifs_device.rw_data = ifsd;
> -
> - if (misc_register(&ifs_device.misc)) {
> - kfree(ifsd);
> - kfree(ifs_pkg_auth);
> - return -ENODEV;
> + for (i = 0; i < IFS_NUMTESTS; i++) {
> + ifsd = NULL;
> + if (!(msrval & BIT(ifs_devices[i].ro_data.integrity_cap_bit)))
> + continue;
> +
> + ifsd = kzalloc(sizeof(*ifsd), GFP_KERNEL);
> + if (!ifsd) {
> + ret = -ENOMEM;
> + goto err_exit;
> + }
> + ifsd->ro_info = &ifs_devices[i].ro_data;
> + ifs_devices[i].rw_data = ifsd;
> +
> + if (misc_register(&ifs_devices[i].misc)) {
> + ret = -ENODEV;
> + kfree(ifsd);
> + goto err_exit;
> + }
> }
> -
> return 0;
>
> +err_exit:
> + ifs_cleanup();
> + return ret;
> }
>
> static void __exit ifs_exit(void)
> {
> - misc_deregister(&ifs_device.misc);
> - kfree(ifs_device.rw_data);
> - kfree(ifs_pkg_auth);
> + ifs_cleanup();
> }
>
> module_init(ifs_init);
Hi,
On 3/1/23 02:59, Jithu Joseph wrote:
> The interface to trigger Array BIST test and obtain its result
> is similar to the existing scan test. The only notable
> difference is that, Array BIST doesn't require any test content
> to be loaded. So binary load related options are not needed for
> this test.
>
> Add sysfs interface for array BIST test, the testing support will
> be added by subsequent patch.
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> drivers/platform/x86/intel/ifs/ifs.h | 1 +
> drivers/platform/x86/intel/ifs/core.c | 2 ++
> drivers/platform/x86/intel/ifs/runtest.c | 10 +++++++++-
> drivers/platform/x86/intel/ifs/sysfs.c | 10 +++++++++-
> 4 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
> index b8b956e29653..f31966e291df 100644
> --- a/drivers/platform/x86/intel/ifs/ifs.h
> +++ b/drivers/platform/x86/intel/ifs/ifs.h
> @@ -250,5 +250,6 @@ extern bool *ifs_pkg_auth;
> int ifs_load_firmware(struct device *dev);
> int do_core_test(int cpu, struct device *dev);
> extern struct attribute *plat_ifs_attrs[];
> +extern struct attribute *plat_ifs_array_attrs[];
>
> #endif
> diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
> index 2237aaba7078..c74accedfc8d 100644
> --- a/drivers/platform/x86/intel/ifs/core.c
> +++ b/drivers/platform/x86/intel/ifs/core.c
> @@ -22,6 +22,7 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
> MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
>
> ATTRIBUTE_GROUPS(plat_ifs);
> +ATTRIBUTE_GROUPS(plat_ifs_array);
>
> bool *ifs_pkg_auth;
>
> @@ -45,6 +46,7 @@ static struct ifs_device ifs_devices[] = {
> .misc = {
> .name = "intel_ifs_1",
> .minor = MISC_DYNAMIC_MINOR,
> + .groups = plat_ifs_array_groups,
> },
> },
> };
> diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
> index 0bfd8fcdd7e8..969b3e0946d5 100644
> --- a/drivers/platform/x86/intel/ifs/runtest.c
> +++ b/drivers/platform/x86/intel/ifs/runtest.c
> @@ -236,6 +236,7 @@ static void ifs_test_core(int cpu, struct device *dev)
> */
> int do_core_test(int cpu, struct device *dev)
> {
> + struct ifs_data *ifsd = ifs_get_data(dev);
> int ret = 0;
>
> /* Prevent CPUs from being taken offline during the scan test */
> @@ -247,7 +248,14 @@ int do_core_test(int cpu, struct device *dev)
> goto out;
> }
>
> - ifs_test_core(cpu, dev);
> + switch (ifsd->ro_info->test_num) {
> + case IFS_TYPE_SAF:
> + ifs_test_core(cpu, dev);
> + break;
> + case IFS_TYPE_ARRAY_BIST:
> + default:
> + return -EINVAL;
> + }
> out:
> cpus_read_unlock();
> return ret;
> diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
> index 2007d8054f04..88234798080a 100644
> --- a/drivers/platform/x86/intel/ifs/sysfs.c
> +++ b/drivers/platform/x86/intel/ifs/sysfs.c
> @@ -75,7 +75,7 @@ static ssize_t run_test_store(struct device *dev,
> if (down_interruptible(&ifs_sem))
> return -EINTR;
>
> - if (!ifsd->loaded)
> + if (ifsd->ro_info->test_num != IFS_TYPE_ARRAY_BIST && !ifsd->loaded)
> rc = -EPERM;
> else
> rc = do_core_test(cpu, dev);
> @@ -149,3 +149,11 @@ struct attribute *plat_ifs_attrs[] = {
> &dev_attr_image_version.attr,
> NULL
> };
> +
> +/* global array sysfs attributes */
> +struct attribute *plat_ifs_array_attrs[] = {
> + &dev_attr_details.attr,
> + &dev_attr_status.attr,
> + &dev_attr_run_test.attr,
> + NULL
> +};
Since you need 2 different groups now, please:
1. Add a "struct attribute **groups" member to struct ifs_hw_caps
2. Set it to the right attrs[] array for the CPU type in the
2 const struct if_hw_caps instances.
3. in probe() add:
ifs_device.misc_device.groups = ifs_device.hw_caps->groups;
before registering the misc_device.
Regards,
Hans
Hi,
On 3/1/23 02:59, Jithu Joseph wrote:
> Array BIST test (for a particlular core) is triggered by writing
> to MSR_ARRAY_BIST from one sibling of the core.
>
> This will initiate a test for all supported arrays on that
> CPU. Array BIST test may be aborted before completing all the
> arrays in the event of an interrupt or other reasons.
> In this case, kernel will restart the test from that point
> onwards. Array test will also be aborted when the test fails,
> in which case the test is stopped immediately without further
> retry.
>
> Signed-off-by: Jithu Joseph <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> drivers/platform/x86/intel/ifs/ifs.h | 12 ++++
> drivers/platform/x86/intel/ifs/runtest.c | 81 ++++++++++++++++++++++++
> 2 files changed, 93 insertions(+)
>
> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
> index f31966e291df..1228101de201 100644
> --- a/drivers/platform/x86/intel/ifs/ifs.h
> +++ b/drivers/platform/x86/intel/ifs/ifs.h
> @@ -127,6 +127,7 @@
> #include <linux/device.h>
> #include <linux/miscdevice.h>
>
> +#define MSR_ARRAY_BIST 0x00000105
> #define MSR_COPY_SCAN_HASHES 0x000002c2
> #define MSR_SCAN_HASHES_STATUS 0x000002c3
> #define MSR_AUTHENTICATE_AND_COPY_CHUNK 0x000002c4
> @@ -192,6 +193,17 @@ union ifs_status {
> };
> };
>
> +/* MSR_ARRAY_BIST bit fields */
> +union ifs_array {
> + u64 data;
> + struct {
> + u32 array_bitmask;
> + u16 array_bank;
> + u16 rsvd :15;
> + u16 ctrl_result :1;
> + };
> +};
> +
> /*
> * Driver populated error-codes
> * 0xFD: Test timed out before completing all the chunks.
> diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
> index 969b3e0946d5..3a5442796c7d 100644
> --- a/drivers/platform/x86/intel/ifs/runtest.c
> +++ b/drivers/platform/x86/intel/ifs/runtest.c
> @@ -229,6 +229,85 @@ static void ifs_test_core(int cpu, struct device *dev)
> }
> }
>
> +#define SPINUNIT 100 /* 100 nsec */
> +static atomic_t array_cpus_out;
This variable is only inc-ed + read, it is never reset to 0
so the "while (atomic_read(t) < all_cpus)"
check only works for the first test run.
Also even static atomic_t variables must be initialized, you cannot
assume that using using zeroed mem is a valid value for an atomic_t.
And this is also shared between all smt pairs, so if 2 "real"
CPU cores with both 2 sibblings are asked to run IFS tests at
the same time, then array_cpus_out will get increased 4 times
in total, breaking the wait_for_sibbling loop as soon as
the counter reaches 2, so before the tests are done.
It looks like this bit needs to be reworked so that the busy spinning
the sibbling uses per "real" cpu core data and so that the counter
is reset before the tests are started.
Regards,
Hans
> +
> +/*
> + * Simplified cpu sibling rendezvous loop based on microcode loader __wait_for_cpus()
> + */
> +static void wait_for_sibling_cpu(atomic_t *t, long long timeout)
> +{
> + int cpu = smp_processor_id();
> + const struct cpumask *smt_mask = cpu_smt_mask(cpu);
> + int all_cpus = cpumask_weight(smt_mask);
> +
> + atomic_inc(t);
> + while (atomic_read(t) < all_cpus) {
> + if (timeout < SPINUNIT)
> + return;
> + ndelay(SPINUNIT);
> + timeout -= SPINUNIT;
> + touch_nmi_watchdog();
> + }
> +}
> +
> +static int do_array_test(void *data)
> +{
> + union ifs_array *command = data;
> + int cpu = smp_processor_id();
> + int first;
> +
> + /*
> + * Only one logical CPU on a core needs to trigger the Array test via MSR write.
> + */
> + first = cpumask_first(cpu_smt_mask(cpu));
> +
> + if (cpu == first) {
> + wrmsrl(MSR_ARRAY_BIST, command->data);
> + /* Pass back the result of the test */
> + rdmsrl(MSR_ARRAY_BIST, command->data);
> + }
> +
> + /* Tests complete faster if the sibling is spinning here */
> + wait_for_sibling_cpu(&array_cpus_out, NSEC_PER_SEC);
> +
> + return 0;
> +}
> +
> +static void ifs_array_test_core(int cpu, struct device *dev)
> +{
> + union ifs_array command = {};
> + bool timed_out = false;
> + struct ifs_data *ifsd;
> + unsigned long timeout;
> +
> + ifsd = ifs_get_data(dev);
> +
> + command.array_bitmask = ~0U;
> + timeout = jiffies + HZ / 2;
> +
> + do {
> + if (time_after(jiffies, timeout)) {
> + timed_out = true;
> + break;
> + }
> + atomic_set(&array_cpus_out, 0);
> + stop_core_cpuslocked(cpu, do_array_test, &command);
> +
> + if (command.ctrl_result)
> + break;
> + } while (command.array_bitmask);
> +
> + ifsd->scan_details = command.data;
> +
> + if (command.ctrl_result)
> + ifsd->status = SCAN_TEST_FAIL;
> + else if (timed_out || command.array_bitmask)
> + ifsd->status = SCAN_NOT_TESTED;
> + else
> + ifsd->status = SCAN_TEST_PASS;
> +}
> +
> /*
> * Initiate per core test. It wakes up work queue threads on the target cpu and
> * its sibling cpu. Once all sibling threads wake up, the scan test gets executed and
> @@ -253,6 +332,8 @@ int do_core_test(int cpu, struct device *dev)
> ifs_test_core(cpu, dev);
> break;
> case IFS_TYPE_ARRAY_BIST:
> + ifs_array_test_core(cpu, dev);
> + break;
> default:
> return -EINVAL;
> }
Hi,
On 3/13/23 17:10, Hans de Goede wrote:
> Hi,
>
> On 3/1/23 02:59, Jithu Joseph wrote:
>> Array BIST is a new type of core test introduced under the Intel Infield
>> Scan (IFS) suite of tests.
>>
>> Emerald Rapids (EMR) is the first CPU to support Array BIST.
>> Array BIST performs tests on some portions of the core logic such as
>> caches and register files. These are different portions of the silicon
>> compared to the parts tested by the first test type
>> i.e Scan at Field (SAF).
>>
>> Make changes in the device driver init flow to register this new test
>> type with the device driver framework. Each test will have its own
>> sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
>> accommodate for the differences in test type and how they are initiated.
>>
>> Upcoming patches will add actual support.
>>
>> Signed-off-by: Jithu Joseph <[email protected]>
>> Reviewed-by: Tony Luck <[email protected]>
>> ---
>> drivers/platform/x86/intel/ifs/ifs.h | 3 +
>> drivers/platform/x86/intel/ifs/core.c | 85 +++++++++++++++++++--------
>> 2 files changed, 62 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
>> index ab168ddf28f1..b8b956e29653 100644
>> --- a/drivers/platform/x86/intel/ifs/ifs.h
>> +++ b/drivers/platform/x86/intel/ifs/ifs.h
>> @@ -137,6 +137,9 @@
>> #define SCAN_TEST_PASS 1
>> #define SCAN_TEST_FAIL 2
>>
>> +#define IFS_TYPE_SAF 0
>> +#define IFS_TYPE_ARRAY_BIST 1
>> +
>> /* MSR_SCAN_HASHES_STATUS bit fields */
>> union ifs_scan_hashes_status {
>> u64 data;
>> diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
>> index 62c44dbae757..2237aaba7078 100644
>> --- a/drivers/platform/x86/intel/ifs/core.c
>> +++ b/drivers/platform/x86/intel/ifs/core.c
>> @@ -16,6 +16,7 @@
>>
>> static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
>> X86_MATCH(SAPPHIRERAPIDS_X),
>> + X86_MATCH(EMERALDRAPIDS_X),
>> {}
>> };
>> MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
>
> Note you can add driver_data to a match table like this. What you should
> do here is use the driver data to point to the const ifs_hw_caps discussed
> before, so what you get here is:
>
> #define X86_MATCH(model, data) \
> X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
> INTEL_FAM6_##model, X86_FEATURE_CORE_CAPABILITIES, (unsigned long)(data))
>
> static const struct ifs_hw_caps saphire_rapids_caps = {
> .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> .test_num = 0,
> };
>
> static const struct ifs_hw_caps emerald_rapids_caps = {
> .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> .test_num = 0,
> };
>
> static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
> X86_MATCH(SAPPHIRERAPIDS_X, &saphire_rapids_caps),
> X86_MATCH(EMERALDRAPIDS_X, &emerald_rapids_caps),
> {}
> };
> MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
>
> and then drop all the code related to having an array of ifs_device structs
> (of which only 1 will ever get used) and instead at the beginning of
> ifs_init(void), after:
>
> m = x86_match_cpu(ifs_cpu_ids);
> if (!m)
> return -ENODEV;
>
> add:
>
> ifs_device.hwcaps = (const struct ifs_hw_caps *)m->driver_data;
>
> And then you can pretty much drop all the rest of this patch and we
> end up with much nicer code for differentiating between the models :)
Upon reading the rest of the series, I think the above might be based
on me misunderstanding this bit.
If I understand things correctly then what is new with emerald_rapids
is support for a second set/type of tests called " Array Scan test"
and the old test method / test-type is also still supported.
And you have chosen to register 2 misc-devices , one per supported
test type ?
Have I understood that correcty?
May I ask why use 1 misc device per test-type. Why not just add
a single new sysfs_attr to the existing misc device to trigger
the new test-type ?
Regards,
Hans
>> @@ -24,23 +25,51 @@ ATTRIBUTE_GROUPS(plat_ifs);
>>
>> bool *ifs_pkg_auth;
>>
>> -static struct ifs_device ifs_device = {
>> - .ro_data = {
>> - .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
>> - .test_num = 0,
>> +static struct ifs_device ifs_devices[] = {
>> + [IFS_TYPE_SAF] = {
>> + .ro_data = {
>> + .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
>> + .test_num = IFS_TYPE_SAF,
>> + },
>> + .misc = {
>> + .name = "intel_ifs_0",
>> + .minor = MISC_DYNAMIC_MINOR,
>> + .groups = plat_ifs_groups,
>> + },
>> },
>> - .misc = {
>> - .name = "intel_ifs_0",
>> - .minor = MISC_DYNAMIC_MINOR,
>> - .groups = plat_ifs_groups,
>> + [IFS_TYPE_ARRAY_BIST] = {
>> + .ro_data = {
>> + .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
>> + .test_num = IFS_TYPE_ARRAY_BIST,
>> + },
>> + .misc = {
>> + .name = "intel_ifs_1",
>> + .minor = MISC_DYNAMIC_MINOR,
>> + },
>> },
>> };
>>
>> +#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
>> +
>> +static void ifs_cleanup(void)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < IFS_NUMTESTS; i++) {
>> + if (ifs_devices[i].misc.this_device) {
>> + misc_deregister(&ifs_devices[i].misc);
>> + kfree(ifs_devices[i].rw_data);
>> + }
>> + }
>> + kfree(ifs_pkg_auth);
>> +}
>> +
>> static int __init ifs_init(void)
>> {
>> const struct x86_cpu_id *m;
>> struct ifs_data *ifsd;
>> u64 msrval;
>> + int i, ret;
>>
>> m = x86_match_cpu(ifs_cpu_ids);
>> if (!m)
>> @@ -55,35 +84,39 @@ static int __init ifs_init(void)
>> if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
>> return -ENODEV;
>>
>> - if (!(msrval & BIT(ifs_device.ro_data.integrity_cap_bit)))
>> - return -ENODEV;
>> -
>> ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
>> if (!ifs_pkg_auth)
>> return -ENOMEM;
>>
>> - ifsd = kzalloc(sizeof(*ifsd), GFP_KERNEL);
>> - if (!ifsd)
>> - return -ENOMEM;
>> -
>> - ifsd->ro_info = &ifs_device.ro_data;
>> - ifs_device.rw_data = ifsd;
>> -
>> - if (misc_register(&ifs_device.misc)) {
>> - kfree(ifsd);
>> - kfree(ifs_pkg_auth);
>> - return -ENODEV;
>> + for (i = 0; i < IFS_NUMTESTS; i++) {
>> + ifsd = NULL;
>> + if (!(msrval & BIT(ifs_devices[i].ro_data.integrity_cap_bit)))
>> + continue;
>> +
>> + ifsd = kzalloc(sizeof(*ifsd), GFP_KERNEL);
>> + if (!ifsd) {
>> + ret = -ENOMEM;
>> + goto err_exit;
>> + }
>> + ifsd->ro_info = &ifs_devices[i].ro_data;
>> + ifs_devices[i].rw_data = ifsd;
>> +
>> + if (misc_register(&ifs_devices[i].misc)) {
>> + ret = -ENODEV;
>> + kfree(ifsd);
>> + goto err_exit;
>> + }
>> }
>> -
>> return 0;
>>
>> +err_exit:
>> + ifs_cleanup();
>> + return ret;
>> }
>>
>> static void __exit ifs_exit(void)
>> {
>> - misc_deregister(&ifs_device.misc);
>> - kfree(ifs_device.rw_data);
>> - kfree(ifs_pkg_auth);
>> + ifs_cleanup();
>> }
>>
>> module_init(ifs_init);
Hans,
Thank-you very much for the review.
On 3/13/2023 9:24 AM, Hans de Goede wrote:
>>
>> +#define SPINUNIT 100 /* 100 nsec */
>> +static atomic_t array_cpus_out;
>
> This variable is only inc-ed + read, it is never reset to 0
> so the "while (atomic_read(t) < all_cpus)"
> check only works for the first test run.
>
It is reset to zero as annotated below. Let me know if this doesn't address your concern.
> Also even static atomic_t variables must be initialized, you cannot
> assume that using using zeroed mem is a valid value for an atomic_t.
>
> And this is also shared between all smt pairs, so if 2 "real"
> CPU cores with both 2 sibblings are asked to run IFS tests at
> the same time, then array_cpus_out will get increased 4 times
> in total, breaking the wait_for_sibbling loop as soon as
> the counter reaches 2, so before the tests are done.
Only one IFS test is allowed at a time. This is done using "ifs_sem" defined in sysfs.c
...
>> +static void ifs_array_test_core(int cpu, struct device *dev)
>> +{
>> + union ifs_array command = {};
>> + bool timed_out = false;
>> + struct ifs_data *ifsd;
>> + unsigned long timeout;
>> +
>> + ifsd = ifs_get_data(dev);
>> +
>> + command.array_bitmask = ~0U;
>> + timeout = jiffies + HZ / 2;
>> +
>> + do {
>> + if (time_after(jiffies, timeout)) {
>> + timed_out = true;
>> + break;
>> + }
>> + atomic_set(&array_cpus_out, 0);
The above line is where the zero initialization happens before every test.
>> + stop_core_cpuslocked(cpu, do_array_test, &command);
>> +
>> + if (command.ctrl_result)
>> + break;
>> + } while (command.array_bitmask);
>> +
>> + ifsd->scan_details = command.data;
>> +
>> + if (command.ctrl_result)
>> + ifsd->status = SCAN_TEST_FAIL;
>> + else if (timed_out || command.array_bitmask)
>> + ifsd->status = SCAN_NOT_TESTED;
>> + else
>> + ifsd->status = SCAN_TEST_PASS;
>> +}
Jithu
> Upon reading the rest of the series, I think the above might be based
> on me misunderstanding this bit.
>
> If I understand things correctly then what is new with emerald_rapids
> is support for a second set/type of tests called " Array Scan test"
> and the old test method / test-type is also still supported.
Yes. Emerald Rapids supports the new array scan test *in addition to*
the existing scan test. Future CPUs will support both of these tests
and may add additional tests. Further in the future if some new tests
cover the same functionality as older tests, some of the older tests
may be dropped.
So the INTEGRITY_CAPABILITIES MSR is a bitmap enumerating
which tests are supported on each model.
> And you have chosen to register 2 misc-devices , one per supported
> test type ?
>
> Have I understood that correctly?
Yes.
> May I ask why use 1 misc device per test-type. Why not just add
> a single new sysfs_attr to the existing misc device to trigger
> the new test-type ?
That's an interesting idea. So we'd have:
# echo $cpu > run_test
# cat status
...
# cat details
...
for our first type of test (introduced with Sapphire Rapids). Then
in the same directory add a new file to run the array test (on Emerald
Rapids andother future CPUs that support it)
# echo $cpu > run_array_test
# cat status
...
# cat details
...
But I see a problem with the "current_batch" file (that will show up if a future
test also needs to load some test data ... spoiler ... it will).
We can't do:
# echo 2 > current_batch
... what should this load, don't know until the user types one of
# echo $cpu > run_test
or
# echo $cpu > run_${name}_test
Perhaps also have per test type names to load the test images?
# echo 2 > current_${name}_batch
# echo $cpu > run_${name}_test
I'm not sure this is better than splitting the tests into different directories.
-Tony
On 3/13/2023 7:46 AM, Hans de Goede wrote:
> Hi Jithu,
>
> On 3/1/23 02:59, Jithu Joseph wrote:
>>
>> +struct ifs_const_data {
>> + int integrity_cap_bit;
>> + int test_num;
>> +};
>> +
>
> This is a description of the specific capabilties / bits of
> the IFS on e.g. Saphire Rapids, so please name this appropriately
> for example:
>
> struct ifs_hw_caps {
> int integrity_cap_bit;
> int test_num;
> };
This can be renamed to ifs_test_caps as it holds test specific fields.
...
>
> You got this exactly the wrong way around, there should be a single
>
> static const struct ifs_hw_caps saphire_rapids_caps = {
> .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> .test_num = 0,
> };
>
> And then struct ifs_device { } should have a "const struct ifs_hw_caps *hw_caps"
> which gets initialized to point to &saphire_rapids_caps. So that your const
> data is actually const.
>
> Where as since the r/w data's lifetime is couple to the misc-device lifetime
> there is no need to dynamically allocate it just keep that embedded, so that
> together you get:
Noted
>
> struct ifs_device {
> const struct ifs_hw_caps *hw_caps;
> struct ifs_data data;
> struct miscdevice misc;
> };
>
The initialization portion, taking into account your suggestion above, translates to:
static const struct ifs_test_caps scan_test = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
.test_num = IFS_TYPE_SAF,
};
static const struct ifs_test_caps array_test = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
.test_num = IFS_TYPE_ARRAY_BIST,
};
static struct ifs_device ifs_devices[] = {
[IFS_TYPE_SAF] = {
.test_caps = &scan_test,
.misc = {
.name = "intel_ifs_0",
.minor = MISC_DYNAMIC_MINOR,
.groups = plat_ifs_groups,
},
},
[IFS_TYPE_ARRAY_BIST] = {
.test_caps = &array_test,
.misc = {
.name = "intel_ifs_1",
.minor = MISC_DYNAMIC_MINOR,
.groups = plat_ifs_array_groups,
},
},
};
Jithu
On 3/13/2023 10:21 AM, Luck, Tony wrote:
>
>
> I'm not sure this is better than splitting the tests into different directories.
>
To provide a bit more context to Tony's response -
There are similarities between tests (one of the test inputs is cpu number , which is
common among different tests , so are the test outputs described via status / details attributes)
and some differences too (distinct to each test are the test patterns, some tests needs to
load test patterns appropriate for that test type and some does not)
Current approach of keeping each test's attributes in its own directory (intel_ifs_n)
allows the driver to account for the differences naturally, for e.g load test file
suited for a specific test. (I.e if the load is issued from intel_ifs_<n> , the driver
will load test patterns from /lib/firmware/intel/ifs/ifs_<n>/ff-mm-ss-xx.<type_n>).
If load is not applicable for a test type , test directory doesn’t show load and image_version attributes).
As Tony mentioned, similar effect might be achieved using distinct load / run (and image_version)
files for each test type, but the current approach of organizing files per test feels a little
bit more intuitive.
Grouping attributes per test was the original design intent , when the first test was introduced,
as indicated by the existing ABI doc (Documentation/ABI/testing/sysfs-platform-intel-ifs),
wherein attributes are described under /sys/devices/virtual/misc/intel_ifs_<N>/ …
Hans, Shall I revise the series incorporating the rest of your comments ?
Jithu
Hi,
On 3/13/23 22:34, Joseph, Jithu wrote:
>
>
> On 3/13/2023 7:46 AM, Hans de Goede wrote:
>> Hi Jithu,
>>
>> On 3/1/23 02:59, Jithu Joseph wrote:
>
>>>
>>> +struct ifs_const_data {
>>> + int integrity_cap_bit;
>>> + int test_num;
>>> +};
>>> +
>>
>> This is a description of the specific capabilties / bits of
>> the IFS on e.g. Saphire Rapids, so please name this appropriately
>> for example:
>>
>> struct ifs_hw_caps {
>> int integrity_cap_bit;
>> int test_num;
>> };
>
> This can be renamed to ifs_test_caps as it holds test specific fields.
Ack.
>>
>> You got this exactly the wrong way around, there should be a single
>>
>> static const struct ifs_hw_caps saphire_rapids_caps = {
>> .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
>> .test_num = 0,
>> };
>>
>> And then struct ifs_device { } should have a "const struct ifs_hw_caps *hw_caps"
>> which gets initialized to point to &saphire_rapids_caps. So that your const
>> data is actually const.
>>
>> Where as since the r/w data's lifetime is couple to the misc-device lifetime
>> there is no need to dynamically allocate it just keep that embedded, so that
>> together you get:
>
> Noted
>
>>
>> struct ifs_device {
>> const struct ifs_hw_caps *hw_caps;
>> struct ifs_data data;
>> struct miscdevice misc;
>> };
>>
>
> The initialization portion, taking into account your suggestion above, translates to:
Yes, assuming we go with 1 ifs_device per test type.
Regards,
Hans
> static const struct ifs_test_caps scan_test = {
> .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
> .test_num = IFS_TYPE_SAF,
> };
>
> static const struct ifs_test_caps array_test = {
> .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
> .test_num = IFS_TYPE_ARRAY_BIST,
> };
>
> static struct ifs_device ifs_devices[] = {
> [IFS_TYPE_SAF] = {
> .test_caps = &scan_test,
> .misc = {
> .name = "intel_ifs_0",
> .minor = MISC_DYNAMIC_MINOR,
> .groups = plat_ifs_groups,
> },
> },
> [IFS_TYPE_ARRAY_BIST] = {
> .test_caps = &array_test,
> .misc = {
> .name = "intel_ifs_1",
> .minor = MISC_DYNAMIC_MINOR,
> .groups = plat_ifs_array_groups,
> },
> },
> };
>
> Jithu
>
Hi,
On 3/15/23 20:29, Joseph, Jithu wrote:
>
>
> On 3/13/2023 10:21 AM, Luck, Tony wrote:
>
>>
>>
>> I'm not sure this is better than splitting the tests into different directories.
>>
>
> To provide a bit more context to Tony's response -
> There are similarities between tests (one of the test inputs is cpu number , which is
> common among different tests , so are the test outputs described via status / details attributes)
> and some differences too (distinct to each test are the test patterns, some tests needs to
> load test patterns appropriate for that test type and some does not)
>
> Current approach of keeping each test's attributes in its own directory (intel_ifs_n)
> allows the driver to account for the differences naturally, for e.g load test file
> suited for a specific test. (I.e if the load is issued from intel_ifs_<n> , the driver
> will load test patterns from /lib/firmware/intel/ifs/ifs_<n>/ff-mm-ss-xx.<type_n>).
> If load is not applicable for a test type , test directory doesn’t show load and image_version attributes).
>
> As Tony mentioned, similar effect might be achieved using distinct load / run (and image_version)
> files for each test type, but the current approach of organizing files per test feels a little
> bit more intuitive.
>
> Grouping attributes per test was the original design intent , when the first test was introduced,
> as indicated by the existing ABI doc (Documentation/ABI/testing/sysfs-platform-intel-ifs),
> wherein attributes are described under /sys/devices/virtual/misc/intel_ifs_<N>/ …
Ok I see, lets go with 1 intel_ifs device per test-type then.
If I understood things correctly esp. also with the /lib/firmware path then the <N> in intel_ifs_<N> basically specifies the test-type, correct ?
If I have that correct please add this to the ABI documentation in the form of a list with
intel_ifs_<N> <-> test-type
mappings. And also add documentation to each attribute for which test-types the attribute is valid (this can be "all" for e.g. status, to avoid churn when adding more test types).
> Hans, Shall I revise the series incorporating the rest of your comments ?
Yes please.
Regards,
Hans
Hi,
On 3/13/23 17:37, Joseph, Jithu wrote:
> Hans,
>
> Thank-you very much for the review.
>
> On 3/13/2023 9:24 AM, Hans de Goede wrote:
>
>
>>>
>>> +#define SPINUNIT 100 /* 100 nsec */
>>> +static atomic_t array_cpus_out;
>>
>> This variable is only inc-ed + read, it is never reset to 0
>> so the "while (atomic_read(t) < all_cpus)"
>> check only works for the first test run.
>>
>
> It is reset to zero as annotated below. Let me know if this doesn't address your concern.
Ah, I somehow missed that despite looking for it twice, yes that is fine.
>> Also even static atomic_t variables must be initialized, you cannot
>> assume that using using zeroed mem is a valid value for an atomic_t.
>>
>> And this is also shared between all smt pairs, so if 2 "real"
>> CPU cores with both 2 sibblings are asked to run IFS tests at
>> the same time, then array_cpus_out will get increased 4 times
>> in total, breaking the wait_for_sibbling loop as soon as
>> the counter reaches 2, so before the tests are done.
>
> Only one IFS test is allowed at a time. This is done using "ifs_sem" defined in sysfs.c
Ah I see.
After taking a closer look I do see one unrelated issue with this patch
sysfs.c: run_test_store() does:
if (!ifsd->loaded)
rc = -EPERM;
else
rc = do_core_test(cpu, dev);
But AFAICT the loaded check really only applies to the first (intel_ifs_0 device) test type and the
Array BIST test should work fine when loaded is false.
So I think that the if (!ifsd->loaded) error check should be moved to
ifs_test_core() ?
Regards,
Hans
>
> ...
>
>>> +static void ifs_array_test_core(int cpu, struct device *dev)
>>> +{
>>> + union ifs_array command = {};
>>> + bool timed_out = false;
>>> + struct ifs_data *ifsd;
>>> + unsigned long timeout;
>>> +
>>> + ifsd = ifs_get_data(dev);
>>> +
>>> + command.array_bitmask = ~0U;
>>> + timeout = jiffies + HZ / 2;
>>> +
>>> + do {
>>> + if (time_after(jiffies, timeout)) {
>>> + timed_out = true;
>>> + break;
>>> + }
>>> + atomic_set(&array_cpus_out, 0);
>
> The above line is where the zero initialization happens before every test.
>
>>> + stop_core_cpuslocked(cpu, do_array_test, &command);
>>> +
>>> + if (command.ctrl_result)
>>> + break;
>>> + } while (command.array_bitmask);
>>> +
>>> + ifsd->scan_details = command.data;
>>> +
>>> + if (command.ctrl_result)
>>> + ifsd->status = SCAN_TEST_FAIL;
>>> + else if (timed_out || command.array_bitmask)
>>> + ifsd->status = SCAN_NOT_TESTED;
>>> + else
>>> + ifsd->status = SCAN_TEST_PASS;
>>> +}
>
> Jithu
>
On 3/16/2023 2:59 AM, Hans de Goede wrote:
>>
>> Only one IFS test is allowed at a time. This is done using "ifs_sem" defined in sysfs.c
>
> Ah I see.
>
> After taking a closer look I do see one unrelated issue with this patch
> sysfs.c: run_test_store() does:
>
> if (!ifsd->loaded)
> rc = -EPERM;
> else
> rc = do_core_test(cpu, dev);
>
> But AFAICT the loaded check really only applies to the first (intel_ifs_0 device) test type and the
> Array BIST test should work fine when loaded is false.
This is true, the load check only applies to first test. And the patch (5/8) in this series adds the
check you are suggesting to allow the second test to proceed (as given below)
if (ifsd->ro_info->test_num != IFS_TYPE_ARRAY_BIST && !ifsd->loaded)
rc = -EPERM;
else
rc = do_core_test(cpu, dev);
It is possible that the snippet you pasted above was from an earlier state.
Jithu
On 3/16/2023 2:59 AM, Hans de Goede wrote:
>
> After taking a closer look I do see one unrelated issue with this patch
> sysfs.c: run_test_store() does:
>
> if (!ifsd->loaded)
> rc = -EPERM;
> else
> rc = do_core_test(cpu, dev);
>
> But AFAICT the loaded check really only applies to the first (intel_ifs_0 device) test type and the
> Array BIST test should work fine when loaded is false.
>
> So I think that the if (!ifsd->loaded) error check should be moved to
> ifs_test_core() ?
>
It is possible that I misinterpreted your comment in my earlier reply. (Thanks Tony for pointing it out)
Yes I think moving the load check into ifs_test_core() is better than doing it in run_test_store()
Jithu
Hi,
On 3/16/23 19:11, Joseph, Jithu wrote:
>
>
> On 3/16/2023 2:59 AM, Hans de Goede wrote:
>
>>
>> After taking a closer look I do see one unrelated issue with this patch
>> sysfs.c: run_test_store() does:
>>
>> if (!ifsd->loaded)
>> rc = -EPERM;
>> else
>> rc = do_core_test(cpu, dev);
>>
>> But AFAICT the loaded check really only applies to the first (intel_ifs_0 device) test type and the
>> Array BIST test should work fine when loaded is false.
>>
>> So I think that the if (!ifsd->loaded) error check should be moved to
>> ifs_test_core() ?
>>
>
> It is possible that I misinterpreted your comment in my earlier reply. (Thanks Tony for pointing it out)
No you were right I was looking at the current code, not the code after this patch-set is applied.
> Yes I think moving the load check into ifs_test_core() is better than doing it in run_test_store()
Ack, doing that is still a cleaner way of dealing with this.
Regards,
Hans
On 3/16/2023 2:50 AM, Hans de Goede wrote:
> Ok I see, lets go with 1 intel_ifs device per test-type then.
>
> If I understood things correctly esp. also with the /lib/firmware path then the <N> in intel_ifs_<N> basically specifies the test-type, correct ?
>
Correct
> If I have that correct please add this to the ABI documentation in the form of a list with
>
> intel_ifs_<N> <-> test-type
>
> mappings. And also add documentation to each attribute for which test-types the attribute is valid (this can be "all" for e.g. status, to avoid churn when adding more test types).
Will do. Thanks for the review comments
Jithu
Changes in v4
- Hans de Goede
- Separate patch 1/9 (Separate ifs_pkg_auth) from reorganize
driver data patch
- Rework patch 2/9 (Reorganize driver data) to define const
ifs_test_caps struct and associate its pointer to miscdevice
and to remove dynamic allocation for ifs_data as was done in v3
- Move load check from run_test_store to do_core_test()
- Expand ABI doc to qualify which devices support which attribrutes
and the device instance to test mapping
V3 submission:
Link: https://lore.kernel.org/lkml/[email protected]/
Changes in v3
- GregKH
- Separating read-only fields from rw fields in
struct ifs_device (patch 1/8)
- Remove the subdirectory intel_ifs/<n> for devicenode (patch 2/8)
- Replaced an enum with #define (patch 4/8)
- Dave Hansen
- Remove tracing patch
- ifs_array_test_core() (patch 6/8)
- fix an initialization bug
- other suggested changes
- Use basic types in ifs_array for first two fields. (kept
the union to avoid type castings)
v2 submission:
Link: https://lore.kernel.org/lkml/[email protected]/
Changes in v2
- remove duplicate initializations from ifs_array_test_core()
(Dave Hansen, patch 4/7)
- remove bit parsing from tracing fast path to tracing
output (Steven Rostedt, patch 5/7)
- move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
- Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)
v1 submission:
Link: https://lore.kernel.org/lkml/[email protected]/
Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by Scan at Field (SAF).
Unlike SAF, Array BIST doesn't require any test content to be loaded.
Jithu Joseph (9):
platform/x86/intel/ifs: Separate ifs_pkg_auth from ifs_data
platform/x86/intel/ifs: Reorganize driver data
platform/x86/intel/ifs: IFS cleanup
x86/include/asm/msr-index.h: Add IFS Array test bits
platform/x86/intel/ifs: Introduce Array Scan test to IFS
platform/x86/intel/ifs: Sysfs interface for Array BIST
platform/x86/intel/ifs: Implement Array BIST test
platform/x86/intel/ifs: Update IFS doc
Documentation/ABI: Update IFS ABI doc
arch/x86/include/asm/msr-index.h | 2 +
drivers/platform/x86/intel/ifs/ifs.h | 68 ++++++++++----
drivers/platform/x86/intel/ifs/core.c | 81 +++++++++++-----
drivers/platform/x86/intel/ifs/load.c | 9 +-
drivers/platform/x86/intel/ifs/runtest.c | 94 ++++++++++++++++++-
drivers/platform/x86/intel/ifs/sysfs.c | 21 ++---
.../ABI/testing/sysfs-platform-intel-ifs | 17 +++-
7 files changed, 229 insertions(+), 63 deletions(-)
base-commit: e8d018dd0257f744ca50a729e3d042cf2ec9da65
--
2.25.1
In preparation to supporting additional tests, remove ifs_pkg_auth
from per-test scope, as it is only applicable for one test type.
This will simplify ifs_init() flow when multiple tests are added.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 3 +--
drivers/platform/x86/intel/ifs/core.c | 10 ++++++----
drivers/platform/x86/intel/ifs/load.c | 6 +++---
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 046e39304fd5..221413b79281 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -201,7 +201,6 @@ union ifs_status {
* struct ifs_data - attributes related to intel IFS driver
* @integrity_cap_bit: MSR_INTEGRITY_CAPS bit enumerating this test
* @loaded_version: stores the currently loaded ifs image version.
- * @pkg_auth: array of bool storing per package auth status
* @loaded: If a valid test binary has been loaded into the memory
* @loading_error: Error occurred on another CPU while loading image
* @valid_chunks: number of chunks which could be validated.
@@ -212,7 +211,6 @@ union ifs_status {
*/
struct ifs_data {
int integrity_cap_bit;
- bool *pkg_auth;
int loaded_version;
bool loaded;
bool loading_error;
@@ -241,6 +239,7 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
return &d->data;
}
+extern bool *ifs_pkg_auth;
int ifs_load_firmware(struct device *dev);
int do_core_test(int cpu, struct device *dev);
const struct attribute_group **ifs_get_groups(void);
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 206a617c2e02..3176d94b1fe5 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -20,6 +20,8 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
+bool *ifs_pkg_auth;
+
static struct ifs_device ifs_device = {
.data = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
@@ -56,13 +58,13 @@ static int __init ifs_init(void)
if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
return -ENODEV;
- ifs_device.data.pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
- if (!ifs_device.data.pkg_auth)
+ ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
+ if (!ifs_pkg_auth)
return -ENOMEM;
ret = misc_register(&ifs_device.misc);
if (ret) {
- kfree(ifs_device.data.pkg_auth);
+ kfree(ifs_pkg_auth);
return ret;
}
@@ -72,7 +74,7 @@ static int __init ifs_init(void)
static void __exit ifs_exit(void)
{
misc_deregister(&ifs_device.misc);
- kfree(ifs_device.data.pkg_auth);
+ kfree(ifs_pkg_auth);
}
module_init(ifs_init);
diff --git a/drivers/platform/x86/intel/ifs/load.c b/drivers/platform/x86/intel/ifs/load.c
index c5c24e6fdc43..74a50e99cacd 100644
--- a/drivers/platform/x86/intel/ifs/load.c
+++ b/drivers/platform/x86/intel/ifs/load.c
@@ -192,7 +192,7 @@ static int scan_chunks_sanity_check(struct device *dev)
struct ifs_work local_work;
int curr_pkg, cpu, ret;
- memset(ifsd->pkg_auth, 0, (topology_max_packages() * sizeof(bool)));
+ memset(ifs_pkg_auth, 0, (topology_max_packages() * sizeof(bool)));
ret = validate_ifs_metadata(dev);
if (ret)
return ret;
@@ -204,7 +204,7 @@ static int scan_chunks_sanity_check(struct device *dev)
cpus_read_lock();
for_each_online_cpu(cpu) {
curr_pkg = topology_physical_package_id(cpu);
- if (ifsd->pkg_auth[curr_pkg])
+ if (ifs_pkg_auth[curr_pkg])
continue;
reinit_completion(&ifs_done);
local_work.dev = dev;
@@ -215,7 +215,7 @@ static int scan_chunks_sanity_check(struct device *dev)
ret = -EIO;
goto out;
}
- ifsd->pkg_auth[curr_pkg] = 1;
+ ifs_pkg_auth[curr_pkg] = 1;
}
ret = 0;
out:
--
2.25.1
Cleanup incorporating misc review comments
- Remove the subdirectory intel_ifs/0 for devicenode [1]
- Make plat_ifs_groups non static and use it directly without using a
function [2]
Link: https://lore.kernel.org/lkml/[email protected]/ [1]
Link: https://lore.kernel.org/lkml/[email protected]/ [2]
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 2 +-
drivers/platform/x86/intel/ifs/core.c | 6 +++---
drivers/platform/x86/intel/ifs/sysfs.c | 9 +--------
3 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index d9c1a1f3e31d..55bcc70c2966 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -252,6 +252,6 @@ static inline const struct ifs_test_caps *ifs_get_test_caps(struct device *dev)
extern bool *ifs_pkg_auth;
int ifs_load_firmware(struct device *dev);
int do_core_test(int cpu, struct device *dev);
-const struct attribute_group **ifs_get_groups(void);
+extern struct attribute *plat_ifs_attrs[];
#endif
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index e2bf728eefdf..f272644617a3 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -20,6 +20,8 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
+ATTRIBUTE_GROUPS(plat_ifs);
+
bool *ifs_pkg_auth;
static const struct ifs_test_caps scan_test = {
@@ -31,8 +33,8 @@ static struct ifs_device ifs_device = {
.test_caps = &scan_test,
.misc = {
.name = "intel_ifs_0",
- .nodename = "intel_ifs/0",
.minor = MISC_DYNAMIC_MINOR,
+ .groups = plat_ifs_groups,
},
};
@@ -55,8 +57,6 @@ static int __init ifs_init(void)
if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
return -ENODEV;
- ifs_device.misc.groups = ifs_get_groups();
-
if (!(msrval & BIT(ifs_device.test_caps->integrity_cap_bit)))
return -ENODEV;
diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
index ee636a76b083..2007d8054f04 100644
--- a/drivers/platform/x86/intel/ifs/sysfs.c
+++ b/drivers/platform/x86/intel/ifs/sysfs.c
@@ -141,7 +141,7 @@ static ssize_t image_version_show(struct device *dev,
static DEVICE_ATTR_RO(image_version);
/* global scan sysfs attributes */
-static struct attribute *plat_ifs_attrs[] = {
+struct attribute *plat_ifs_attrs[] = {
&dev_attr_details.attr,
&dev_attr_status.attr,
&dev_attr_run_test.attr,
@@ -149,10 +149,3 @@ static struct attribute *plat_ifs_attrs[] = {
&dev_attr_image_version.attr,
NULL
};
-
-ATTRIBUTE_GROUPS(plat_ifs);
-
-const struct attribute_group **ifs_get_groups(void)
-{
- return plat_ifs_groups;
-}
--
2.25.1
Define MSR bitfields for enumerating support for Array BIST test.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
---
arch/x86/include/asm/msr-index.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ad35355ee43e..3aedae61af4f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -206,6 +206,8 @@
/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
#define MSR_INTEGRITY_CAPS 0x000002d9
+#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2
+#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
--
2.25.1
Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by the first test type
i.e Scan at Field (SAF).
Make changes in the device driver init flow to register this new test
type with the device driver framework. Each test will have its own
sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
accommodate for the differences in test type and how they are initiated.
Upcoming patches will add actual support.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 3 ++
drivers/platform/x86/intel/ifs/core.c | 65 +++++++++++++++++++--------
2 files changed, 50 insertions(+), 18 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 55bcc70c2966..14789b156299 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -137,6 +137,9 @@
#define SCAN_TEST_PASS 1
#define SCAN_TEST_FAIL 2
+#define IFS_TYPE_SAF 0
+#define IFS_TYPE_ARRAY_BIST 1
+
/* MSR_SCAN_HASHES_STATUS bit fields */
union ifs_scan_hashes_status {
u64 data;
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index f272644617a3..0067eee25f3c 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -16,6 +16,7 @@
static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
X86_MATCH(SAPPHIRERAPIDS_X),
+ X86_MATCH(EMERALDRAPIDS_X),
{}
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
@@ -26,23 +27,50 @@ bool *ifs_pkg_auth;
static const struct ifs_test_caps scan_test = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
- .test_num = 0,
+ .test_num = IFS_TYPE_SAF,
};
-static struct ifs_device ifs_device = {
- .test_caps = &scan_test,
- .misc = {
- .name = "intel_ifs_0",
- .minor = MISC_DYNAMIC_MINOR,
- .groups = plat_ifs_groups,
+static const struct ifs_test_caps array_test = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
+ .test_num = IFS_TYPE_ARRAY_BIST,
+};
+
+static struct ifs_device ifs_devices[] = {
+ [IFS_TYPE_SAF] = {
+ .test_caps = &scan_test,
+ .misc = {
+ .name = "intel_ifs_0",
+ .minor = MISC_DYNAMIC_MINOR,
+ .groups = plat_ifs_groups,
+ },
+ },
+ [IFS_TYPE_ARRAY_BIST] = {
+ .test_caps = &array_test,
+ .misc = {
+ .name = "intel_ifs_1",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
};
+#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
+
+static void ifs_cleanup(void)
+{
+ int i;
+
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (ifs_devices[i].misc.this_device)
+ misc_deregister(&ifs_devices[i].misc);
+ }
+ kfree(ifs_pkg_auth);
+}
+
static int __init ifs_init(void)
{
const struct x86_cpu_id *m;
u64 msrval;
- int ret;
+ int i, ret;
m = x86_match_cpu(ifs_cpu_ids);
if (!m)
@@ -57,26 +85,27 @@ static int __init ifs_init(void)
if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
return -ENODEV;
- if (!(msrval & BIT(ifs_device.test_caps->integrity_cap_bit)))
- return -ENODEV;
-
ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
if (!ifs_pkg_auth)
return -ENOMEM;
- ret = misc_register(&ifs_device.misc);
- if (ret) {
- kfree(ifs_pkg_auth);
- return ret;
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (!(msrval & BIT(ifs_devices[i].test_caps->integrity_cap_bit)))
+ continue;
+ ret = misc_register(&ifs_devices[i].misc);
+ if (ret)
+ goto err_exit;
}
-
return 0;
+
+err_exit:
+ ifs_cleanup();
+ return ret;
}
static void __exit ifs_exit(void)
{
- misc_deregister(&ifs_device.misc);
- kfree(ifs_pkg_auth);
+ ifs_cleanup();
}
module_init(ifs_init);
--
2.25.1
The interface to trigger Array BIST test and obtain its result
is similar to the existing scan test. The only notable
difference is that, Array BIST doesn't require any test content
to be loaded. So binary load related options are not needed for
this test.
Add sysfs interface for array BIST test, the testing support will
be added by subsequent patch.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 1 +
drivers/platform/x86/intel/ifs/core.c | 2 ++
drivers/platform/x86/intel/ifs/runtest.c | 13 ++++++++++++-
drivers/platform/x86/intel/ifs/sysfs.c | 14 +++++++++-----
4 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 14789b156299..a7d87fb4c412 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -256,5 +256,6 @@ extern bool *ifs_pkg_auth;
int ifs_load_firmware(struct device *dev);
int do_core_test(int cpu, struct device *dev);
extern struct attribute *plat_ifs_attrs[];
+extern struct attribute *plat_ifs_array_attrs[];
#endif
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 0067eee25f3c..306f886b52d2 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -22,6 +22,7 @@ static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
ATTRIBUTE_GROUPS(plat_ifs);
+ATTRIBUTE_GROUPS(plat_ifs_array);
bool *ifs_pkg_auth;
@@ -49,6 +50,7 @@ static struct ifs_device ifs_devices[] = {
.misc = {
.name = "intel_ifs_1",
.minor = MISC_DYNAMIC_MINOR,
+ .groups = plat_ifs_array_groups,
},
},
};
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 0bfd8fcdd7e8..323752fe5034 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -236,6 +236,8 @@ static void ifs_test_core(int cpu, struct device *dev)
*/
int do_core_test(int cpu, struct device *dev)
{
+ const struct ifs_test_caps *test = ifs_get_test_caps(dev);
+ struct ifs_data *ifsd = ifs_get_data(dev);
int ret = 0;
/* Prevent CPUs from being taken offline during the scan test */
@@ -247,7 +249,16 @@ int do_core_test(int cpu, struct device *dev)
goto out;
}
- ifs_test_core(cpu, dev);
+ switch (test->test_num) {
+ case IFS_TYPE_SAF:
+ if (!ifsd->loaded)
+ return -EPERM;
+ ifs_test_core(cpu, dev);
+ break;
+ case IFS_TYPE_ARRAY_BIST:
+ default:
+ return -EINVAL;
+ }
out:
cpus_read_unlock();
return ret;
diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/intel/ifs/sysfs.c
index 2007d8054f04..d856d6b8fc03 100644
--- a/drivers/platform/x86/intel/ifs/sysfs.c
+++ b/drivers/platform/x86/intel/ifs/sysfs.c
@@ -64,7 +64,6 @@ static ssize_t run_test_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
- struct ifs_data *ifsd = ifs_get_data(dev);
unsigned int cpu;
int rc;
@@ -75,10 +74,7 @@ static ssize_t run_test_store(struct device *dev,
if (down_interruptible(&ifs_sem))
return -EINTR;
- if (!ifsd->loaded)
- rc = -EPERM;
- else
- rc = do_core_test(cpu, dev);
+ rc = do_core_test(cpu, dev);
up(&ifs_sem);
@@ -149,3 +145,11 @@ struct attribute *plat_ifs_attrs[] = {
&dev_attr_image_version.attr,
NULL
};
+
+/* global array sysfs attributes */
+struct attribute *plat_ifs_array_attrs[] = {
+ &dev_attr_details.attr,
+ &dev_attr_status.attr,
+ &dev_attr_run_test.attr,
+ NULL
+};
--
2.25.1
Array BIST is the second test supported by IFS. Modify IFS doc
entry to be more general.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 048131df13bc..93191855890f 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -17,7 +17,7 @@
* In Field Scan (IFS) is a hardware feature to run circuit level tests on
* a CPU core to detect problems that are not caught by parity or ECC checks.
* Future CPUs will support more than one type of test which will show up
- * with a new platform-device instance-id, for now only .0 is exposed.
+ * with a new platform-device instance-id.
*
*
* IFS Image
@@ -25,7 +25,10 @@
*
* Intel provides a firmware file containing the scan tests via
* github [#f1]_. Similar to microcode there is a separate file for each
- * family-model-stepping.
+ * family-model-stepping. IFS Images are not applicable for some test types.
+ * Wherever applicable the sysfs directory would provide a "current_batch" file
+ * (see below) for loading the image.
+ *
*
* IFS Image Loading
* -----------------
@@ -35,7 +38,7 @@
* SHA hashes for the test. Then the tests themselves. Status MSRs provide
* feedback on the success/failure of these steps.
*
- * The test files are kept in a fixed location: /lib/firmware/intel/ifs_0/
+ * The test files are kept in a fixed location: /lib/firmware/intel/ifs_<n>/
* For e.g if there are 3 test files, they would be named in the following
* fashion:
* ff-mm-ss-01.scan
@@ -47,7 +50,7 @@
* (e.g 1, 2 or 3 in the above scenario) into the curent_batch file.
* To load ff-mm-ss-02.scan, the following command can be used::
*
- * # echo 2 > /sys/devices/virtual/misc/intel_ifs_0/current_batch
+ * # echo 2 > /sys/devices/virtual/misc/intel_ifs_<n>/current_batch
*
* The above file can also be read to know the currently loaded image.
*
@@ -69,16 +72,16 @@
* to migrate those applications to other cores before running a core test.
* It may also be necessary to redirect interrupts to other CPUs.
*
- * In all cases reading the SCAN_STATUS MSR provides details on what
+ * In all cases reading the corresponding test's STATUS MSR provides details on what
* happened. The driver makes the value of this MSR visible to applications
* via the "details" file (see below). Interrupted tests may be restarted.
*
- * The IFS driver provides sysfs interfaces via /sys/devices/virtual/misc/intel_ifs_0/
+ * The IFS driver provides sysfs interfaces via /sys/devices/virtual/misc/intel_ifs_<n>/
* to control execution:
*
* Test a specific core::
*
- * # echo <cpu#> > /sys/devices/virtual/misc/intel_ifs_0/run_test
+ * # echo <cpu#> > /sys/devices/virtual/misc/intel_ifs_<n>/run_test
*
* when HT is enabled any of the sibling cpu# can be specified to test
* its corresponding physical core. Since the tests are per physical core,
@@ -87,21 +90,21 @@
*
* For e.g. to test core corresponding to cpu5
*
- * # echo 5 > /sys/devices/virtual/misc/intel_ifs_0/run_test
+ * # echo 5 > /sys/devices/virtual/misc/intel_ifs_<n>/run_test
*
* Results of the last test is provided in /sys::
*
- * $ cat /sys/devices/virtual/misc/intel_ifs_0/status
+ * $ cat /sys/devices/virtual/misc/intel_ifs_<n>/status
* pass
*
* Status can be one of pass, fail, untested
*
* Additional details of the last test is provided by the details file::
*
- * $ cat /sys/devices/virtual/misc/intel_ifs_0/details
+ * $ cat /sys/devices/virtual/misc/intel_ifs_<n>/details
* 0x8081
*
- * The details file reports the hex value of the SCAN_STATUS MSR.
+ * The details file reports the hex value of the test specific status MSR.
* Hardware defined error codes are documented in volume 4 of the Intel
* Software Developer's Manual but the error_code field may contain one of
* the following driver defined software codes:
--
2.25.1
Array BIST test doesn't need an IFS test image to operate unlike
the SCAN test. Consequently current_batch and image_version
files are not applicable for Array BIST IFS device instance,
clarify this in the ABI doc.
Also given that multiple tests are supported, take the opportunity
to generalize descriptions wherever applicable.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
.../ABI/testing/sysfs-platform-intel-ifs | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-platform-intel-ifs b/Documentation/ABI/testing/sysfs-platform-intel-ifs
index 55991983d0d0..41b4d5b1e21c 100644
--- a/Documentation/ABI/testing/sysfs-platform-intel-ifs
+++ b/Documentation/ABI/testing/sysfs-platform-intel-ifs
@@ -1,3 +1,7 @@
+Device instance to test mapping
+intel_ifs_0 -> Scan Test
+intel_ifs_1 -> Array BIST test
+
What: /sys/devices/virtual/misc/intel_ifs_<N>/run_test
Date: Nov 16 2022
KernelVersion: 6.2
@@ -8,6 +12,7 @@ Description: Write <cpu#> to trigger IFS test for one online core.
completes the test for the core containing that thread.
Example: to test the core containing cpu5: echo 5 >
/sys/devices/virtual/misc/intel_ifs_<N>/run_test
+Devices: all
What: /sys/devices/virtual/misc/intel_ifs_<N>/status
Date: Nov 16 2022
@@ -15,21 +20,25 @@ KernelVersion: 6.2
Contact: "Jithu Joseph" <[email protected]>
Description: The status of the last test. It can be one of "pass", "fail"
or "untested".
+Devices: all
What: /sys/devices/virtual/misc/intel_ifs_<N>/details
Date: Nov 16 2022
KernelVersion: 6.2
Contact: "Jithu Joseph" <[email protected]>
Description: Additional information regarding the last test. The details file reports
- the hex value of the SCAN_STATUS MSR. Note that the error_code field
+ the hex value of the STATUS MSR for this test. Note that the error_code field
may contain driver defined software code not defined in the Intel SDM.
+Devices: all
What: /sys/devices/virtual/misc/intel_ifs_<N>/image_version
Date: Nov 16 2022
KernelVersion: 6.2
Contact: "Jithu Joseph" <[email protected]>
-Description: Version (hexadecimal) of loaded IFS binary image. If no scan image
- is loaded reports "none".
+Description: Version (hexadecimal) of loaded IFS test image. If no test image
+ is loaded reports "none". Only present for device instances where a test image
+ is applicable.
+Devices: intel_ifs_0
What: /sys/devices/virtual/misc/intel_ifs_<N>/current_batch
Date: Nov 16 2022
@@ -39,3 +48,5 @@ Description: Write a number less than or equal to 0xff to load an IFS test image
The number written treated as the 2 digit suffix in the following file name:
/lib/firmware/intel/ifs_<N>/ff-mm-ss-02x.scan
Reading the file will provide the suffix of the currently loaded IFS test image.
+ This file is present only for device instances where a test image is applicable.
+Devices: intel_ifs_0
--
2.25.1
The struct holding device driver data contained both read only(ro)
and read write(rw) fields.
Separating ro fields from rw fields was recommended as
a preferable design pattern during review[1].
Group ro fields into a separate const struct. Associate it to
the miscdevice being registered by keeping its pointer in the
same container struct as the miscdevice.
Link: https://lore.kernel.org/lkml/[email protected]/ [1]
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 22 ++++++++++++++++------
drivers/platform/x86/intel/ifs/core.c | 12 +++++++-----
drivers/platform/x86/intel/ifs/load.c | 3 ++-
3 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 221413b79281..d9c1a1f3e31d 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -197,9 +197,13 @@ union ifs_status {
#define IFS_SW_TIMEOUT 0xFD
#define IFS_SW_PARTIAL_COMPLETION 0xFE
+struct ifs_test_caps {
+ int integrity_cap_bit;
+ int test_num;
+};
+
/**
* struct ifs_data - attributes related to intel IFS driver
- * @integrity_cap_bit: MSR_INTEGRITY_CAPS bit enumerating this test
* @loaded_version: stores the currently loaded ifs image version.
* @loaded: If a valid test binary has been loaded into the memory
* @loading_error: Error occurred on another CPU while loading image
@@ -207,10 +211,8 @@ union ifs_status {
* @status: it holds simple status pass/fail/untested
* @scan_details: opaque scan status code from h/w
* @cur_batch: number indicating the currently loaded test file
- * @test_num: number indicating the test type
*/
struct ifs_data {
- int integrity_cap_bit;
int loaded_version;
bool loaded;
bool loading_error;
@@ -218,7 +220,6 @@ struct ifs_data {
int status;
u64 scan_details;
u32 cur_batch;
- int test_num;
};
struct ifs_work {
@@ -227,7 +228,8 @@ struct ifs_work {
};
struct ifs_device {
- struct ifs_data data;
+ const struct ifs_test_caps *test_caps;
+ struct ifs_data rw_data;
struct miscdevice misc;
};
@@ -236,7 +238,15 @@ static inline struct ifs_data *ifs_get_data(struct device *dev)
struct miscdevice *m = dev_get_drvdata(dev);
struct ifs_device *d = container_of(m, struct ifs_device, misc);
- return &d->data;
+ return &d->rw_data;
+}
+
+static inline const struct ifs_test_caps *ifs_get_test_caps(struct device *dev)
+{
+ struct miscdevice *m = dev_get_drvdata(dev);
+ struct ifs_device *d = container_of(m, struct ifs_device, misc);
+
+ return d->test_caps;
}
extern bool *ifs_pkg_auth;
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 3176d94b1fe5..e2bf728eefdf 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -22,11 +22,13 @@ MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
bool *ifs_pkg_auth;
+static const struct ifs_test_caps scan_test = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
+ .test_num = 0,
+};
+
static struct ifs_device ifs_device = {
- .data = {
- .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
- .test_num = 0,
- },
+ .test_caps = &scan_test,
.misc = {
.name = "intel_ifs_0",
.nodename = "intel_ifs/0",
@@ -55,7 +57,7 @@ static int __init ifs_init(void)
ifs_device.misc.groups = ifs_get_groups();
- if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
+ if (!(msrval & BIT(ifs_device.test_caps->integrity_cap_bit)))
return -ENODEV;
ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
diff --git a/drivers/platform/x86/intel/ifs/load.c b/drivers/platform/x86/intel/ifs/load.c
index 74a50e99cacd..61dffb4c8a1d 100644
--- a/drivers/platform/x86/intel/ifs/load.c
+++ b/drivers/platform/x86/intel/ifs/load.c
@@ -257,13 +257,14 @@ static int image_sanity_check(struct device *dev, const struct microcode_header_
*/
int ifs_load_firmware(struct device *dev)
{
+ const struct ifs_test_caps *test = ifs_get_test_caps(dev);
struct ifs_data *ifsd = ifs_get_data(dev);
const struct firmware *fw;
char scan_path[64];
int ret = -EINVAL;
snprintf(scan_path, sizeof(scan_path), "intel/ifs_%d/%02x-%02x-%02x-%02x.scan",
- ifsd->test_num, boot_cpu_data.x86, boot_cpu_data.x86_model,
+ test->test_num, boot_cpu_data.x86, boot_cpu_data.x86_model,
boot_cpu_data.x86_stepping, ifsd->cur_batch);
ret = request_firmware_direct(&fw, scan_path, dev);
--
2.25.1
Array BIST test (for a particular core) is triggered by writing
to MSR_ARRAY_BIST from one sibling of the core.
This will initiate a test for all supported arrays on that
CPU. Array BIST test may be aborted before completing all the
arrays in the event of an interrupt or other reasons.
In this case, kernel will restart the test from that point
onwards. Array test will also be aborted when the test fails,
in which case the test is stopped immediately without further
retry.
Signed-off-by: Jithu Joseph <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
---
drivers/platform/x86/intel/ifs/ifs.h | 12 ++++
drivers/platform/x86/intel/ifs/runtest.c | 81 ++++++++++++++++++++++++
2 files changed, 93 insertions(+)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index a7d87fb4c412..048131df13bc 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -127,6 +127,7 @@
#include <linux/device.h>
#include <linux/miscdevice.h>
+#define MSR_ARRAY_BIST 0x00000105
#define MSR_COPY_SCAN_HASHES 0x000002c2
#define MSR_SCAN_HASHES_STATUS 0x000002c3
#define MSR_AUTHENTICATE_AND_COPY_CHUNK 0x000002c4
@@ -192,6 +193,17 @@ union ifs_status {
};
};
+/* MSR_ARRAY_BIST bit fields */
+union ifs_array {
+ u64 data;
+ struct {
+ u32 array_bitmask;
+ u16 array_bank;
+ u16 rsvd :15;
+ u16 ctrl_result :1;
+ };
+};
+
/*
* Driver populated error-codes
* 0xFD: Test timed out before completing all the chunks.
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index 323752fe5034..1061eb7ec399 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -229,6 +229,85 @@ static void ifs_test_core(int cpu, struct device *dev)
}
}
+#define SPINUNIT 100 /* 100 nsec */
+static atomic_t array_cpus_out;
+
+/*
+ * Simplified cpu sibling rendezvous loop based on microcode loader __wait_for_cpus()
+ */
+static void wait_for_sibling_cpu(atomic_t *t, long long timeout)
+{
+ int cpu = smp_processor_id();
+ const struct cpumask *smt_mask = cpu_smt_mask(cpu);
+ int all_cpus = cpumask_weight(smt_mask);
+
+ atomic_inc(t);
+ while (atomic_read(t) < all_cpus) {
+ if (timeout < SPINUNIT)
+ return;
+ ndelay(SPINUNIT);
+ timeout -= SPINUNIT;
+ touch_nmi_watchdog();
+ }
+}
+
+static int do_array_test(void *data)
+{
+ union ifs_array *command = data;
+ int cpu = smp_processor_id();
+ int first;
+
+ /*
+ * Only one logical CPU on a core needs to trigger the Array test via MSR write.
+ */
+ first = cpumask_first(cpu_smt_mask(cpu));
+
+ if (cpu == first) {
+ wrmsrl(MSR_ARRAY_BIST, command->data);
+ /* Pass back the result of the test */
+ rdmsrl(MSR_ARRAY_BIST, command->data);
+ }
+
+ /* Tests complete faster if the sibling is spinning here */
+ wait_for_sibling_cpu(&array_cpus_out, NSEC_PER_SEC);
+
+ return 0;
+}
+
+static void ifs_array_test_core(int cpu, struct device *dev)
+{
+ union ifs_array command = {};
+ bool timed_out = false;
+ struct ifs_data *ifsd;
+ unsigned long timeout;
+
+ ifsd = ifs_get_data(dev);
+
+ command.array_bitmask = ~0U;
+ timeout = jiffies + HZ / 2;
+
+ do {
+ if (time_after(jiffies, timeout)) {
+ timed_out = true;
+ break;
+ }
+ atomic_set(&array_cpus_out, 0);
+ stop_core_cpuslocked(cpu, do_array_test, &command);
+
+ if (command.ctrl_result)
+ break;
+ } while (command.array_bitmask);
+
+ ifsd->scan_details = command.data;
+
+ if (command.ctrl_result)
+ ifsd->status = SCAN_TEST_FAIL;
+ else if (timed_out || command.array_bitmask)
+ ifsd->status = SCAN_NOT_TESTED;
+ else
+ ifsd->status = SCAN_TEST_PASS;
+}
+
/*
* Initiate per core test. It wakes up work queue threads on the target cpu and
* its sibling cpu. Once all sibling threads wake up, the scan test gets executed and
@@ -256,6 +335,8 @@ int do_core_test(int cpu, struct device *dev)
ifs_test_core(cpu, dev);
break;
case IFS_TYPE_ARRAY_BIST:
+ ifs_array_test_core(cpu, dev);
+ break;
default:
return -EINVAL;
}
--
2.25.1
Hi,
On 3/22/23 01:33, Jithu Joseph wrote:
> Changes in v4
> - Hans de Goede
> - Separate patch 1/9 (Separate ifs_pkg_auth) from reorganize
> driver data patch
> - Rework patch 2/9 (Reorganize driver data) to define const
> ifs_test_caps struct and associate its pointer to miscdevice
> and to remove dynamic allocation for ifs_data as was done in v3
> - Move load check from run_test_store to do_core_test()
> - Expand ABI doc to qualify which devices support which attribrutes
> and the device instance to test mapping
>
> V3 submission:
> Link: https://lore.kernel.org/lkml/[email protected]/
>
> Changes in v3
> - GregKH
> - Separating read-only fields from rw fields in
> struct ifs_device (patch 1/8)
> - Remove the subdirectory intel_ifs/<n> for devicenode (patch 2/8)
> - Replaced an enum with #define (patch 4/8)
> - Dave Hansen
> - Remove tracing patch
> - ifs_array_test_core() (patch 6/8)
> - fix an initialization bug
> - other suggested changes
> - Use basic types in ifs_array for first two fields. (kept
> the union to avoid type castings)
>
> v2 submission:
> Link: https://lore.kernel.org/lkml/[email protected]/
>
> Changes in v2
> - remove duplicate initializations from ifs_array_test_core()
> (Dave Hansen, patch 4/7)
> - remove bit parsing from tracing fast path to tracing
> output (Steven Rostedt, patch 5/7)
> - move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
> exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
> - Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)
>
> v1 submission:
> Link: https://lore.kernel.org/lkml/[email protected]/
>
> Array BIST is a new type of core test introduced under the Intel Infield
> Scan (IFS) suite of tests.
>
> Emerald Rapids (EMR) is the first CPU to support Array BIST.
> Array BIST performs tests on some portions of the core logic such as
> caches and register files. These are different portions of the silicon
> compared to the parts tested by Scan at Field (SAF).
>
> Unlike SAF, Array BIST doesn't require any test content to be loaded.
Thank you for your patch-series, I've applied the series to my
review-hans branch:
https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git/log/?h=review-hans
Note it will show up in my review-hans branch once I've pushed my
local branch there, which might take a while.
Once I've run some tests on this branch the patches there will be
added to the platform-drivers-x86/for-next branch and eventually
will be included in the pdx86 pull-request to Linus for the next
merge-window.
Regards,
Hans
>
> Jithu Joseph (9):
> platform/x86/intel/ifs: Separate ifs_pkg_auth from ifs_data
> platform/x86/intel/ifs: Reorganize driver data
> platform/x86/intel/ifs: IFS cleanup
> x86/include/asm/msr-index.h: Add IFS Array test bits
> platform/x86/intel/ifs: Introduce Array Scan test to IFS
> platform/x86/intel/ifs: Sysfs interface for Array BIST
> platform/x86/intel/ifs: Implement Array BIST test
> platform/x86/intel/ifs: Update IFS doc
> Documentation/ABI: Update IFS ABI doc
>
> arch/x86/include/asm/msr-index.h | 2 +
> drivers/platform/x86/intel/ifs/ifs.h | 68 ++++++++++----
> drivers/platform/x86/intel/ifs/core.c | 81 +++++++++++-----
> drivers/platform/x86/intel/ifs/load.c | 9 +-
> drivers/platform/x86/intel/ifs/runtest.c | 94 ++++++++++++++++++-
> drivers/platform/x86/intel/ifs/sysfs.c | 21 ++---
> .../ABI/testing/sysfs-platform-intel-ifs | 17 +++-
> 7 files changed, 229 insertions(+), 63 deletions(-)
>
>
> base-commit: e8d018dd0257f744ca50a729e3d042cf2ec9da65
Hi Jithu and Hans,
On 2023-03-27 at 21:10:45 +0800, Hans de Goede wrote:
> Hi,
>
> On 3/22/23 01:33, Jithu Joseph wrote:
> > Changes in v4
> > - Hans de Goede
> > - Separate patch 1/9 (Separate ifs_pkg_auth) from reorganize
> > driver data patch
> > - Rework patch 2/9 (Reorganize driver data) to define const
> > ifs_test_caps struct and associate its pointer to miscdevice
> > and to remove dynamic allocation for ifs_data as was done in v3
> > - Move load check from run_test_store to do_core_test()
> > - Expand ABI doc to qualify which devices support which attribrutes
> > and the device instance to test mapping
> >
> > V3 submission:
> > Link: https://lore.kernel.org/lkml/[email protected]/
> >
> > Changes in v3
> > - GregKH
> > - Separating read-only fields from rw fields in
> > struct ifs_device (patch 1/8)
> > - Remove the subdirectory intel_ifs/<n> for devicenode (patch 2/8)
> > - Replaced an enum with #define (patch 4/8)
> > - Dave Hansen
> > - Remove tracing patch
> > - ifs_array_test_core() (patch 6/8)
> > - fix an initialization bug
> > - other suggested changes
> > - Use basic types in ifs_array for first two fields. (kept
> > the union to avoid type castings)
> >
> > v2 submission:
> > Link: https://lore.kernel.org/lkml/[email protected]/
> >
> > Changes in v2
> > - remove duplicate initializations from ifs_array_test_core()
> > (Dave Hansen, patch 4/7)
> > - remove bit parsing from tracing fast path to tracing
> > output (Steven Rostedt, patch 5/7)
> > - move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
> > exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
> > - Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)
> >
> > v1 submission:
> > Link: https://lore.kernel.org/lkml/[email protected]/
> >
> > Array BIST is a new type of core test introduced under the Intel Infield
> > Scan (IFS) suite of tests.
> >
> > Emerald Rapids (EMR) is the first CPU to support Array BIST.
> > Array BIST performs tests on some portions of the core logic such as
> > caches and register files. These are different portions of the silicon
> > compared to the parts tested by Scan at Field (SAF).
> >
> > Unlike SAF, Array BIST doesn't require any test content to be loaded.
>
> Thank you for your patch-series, I've applied the series to my
> review-hans branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git/log/?h=review-hans
>
> Note it will show up in my review-hans branch once I've pushed my
> local branch there, which might take a while.
>
> Once I've run some tests on this branch the patches there will be
> added to the platform-drivers-x86/for-next branch and eventually
> will be included in the pdx86 pull-request to Linus for the next
> merge-window.
>
> Regards,
>
> Hans
>
I have tested the IFS Array BIST function on EMR and Array BIST function
was passed.
Tested-by: Pengfei Xu <[email protected]>
Thanks!
BR.
-Pengfei
>
>
>
> >
> > Jithu Joseph (9):
> > platform/x86/intel/ifs: Separate ifs_pkg_auth from ifs_data
> > platform/x86/intel/ifs: Reorganize driver data
> > platform/x86/intel/ifs: IFS cleanup
> > x86/include/asm/msr-index.h: Add IFS Array test bits
> > platform/x86/intel/ifs: Introduce Array Scan test to IFS
> > platform/x86/intel/ifs: Sysfs interface for Array BIST
> > platform/x86/intel/ifs: Implement Array BIST test
> > platform/x86/intel/ifs: Update IFS doc
> > Documentation/ABI: Update IFS ABI doc
> >
> > arch/x86/include/asm/msr-index.h | 2 +
> > drivers/platform/x86/intel/ifs/ifs.h | 68 ++++++++++----
> > drivers/platform/x86/intel/ifs/core.c | 81 +++++++++++-----
> > drivers/platform/x86/intel/ifs/load.c | 9 +-
> > drivers/platform/x86/intel/ifs/runtest.c | 94 ++++++++++++++++++-
> > drivers/platform/x86/intel/ifs/sysfs.c | 21 ++---
> > .../ABI/testing/sysfs-platform-intel-ifs | 17 +++-
> > 7 files changed, 229 insertions(+), 63 deletions(-)
> >
> >
> > base-commit: e8d018dd0257f744ca50a729e3d042cf2ec9da65
>