Add cm40 subsystem.
Add cm40_lpuart and lpurt1 for 8dxl evk boards.
Signed-off-by: Frank Li <[email protected]>
---
Changes in v2:
- commit message "Adding" to Add
- fixed regulator@101 warning
- remove 'modem reset'
- order nodes by access
- move interrupt-parent under top bus
- clean up other dtb check warning
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Alice Guo (1):
arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
Dong Aisheng (1):
arm64: dts: imx8: add cm40 subsystem dtsi
Frank Li (2):
arm64: dts: imx8dxl: update cm40 irq number informaiton
dts: arm64: imx8dxl-evk: add lpuart1 and cm40 uart
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 91 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 37 ++++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 13 ++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
4 files changed, 142 insertions(+)
---
base-commit: 9acc053fc8f256959e849cb6588a054074daebcd
change-id: 20240228-m4_lpuart-30791c032f2a
Best regards,
--
Frank Li <[email protected]>
From: Dong Aisheng <[email protected]>
Add cm40 subsystem dtsi.
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
3 files changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
new file mode 100644
index 0000000000000..68043ab74e765
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <[email protected]>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+cm40_ipg_clk: clock-cm40-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <132000000>;
+ clock-output-names = "cm40_ipg_clk";
+};
+
+cm40_subsys: bus@34000000 {
+ compatible = "simple-bus";
+ interrupt-parent = <&cm40_intmux>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+
+ cm40_i2c: i2c@37230000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x37230000 0x1000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cm40_i2c_lpcg 0>,
+ <&cm40_i2c_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ status = "disabled";
+ };
+
+ cm40_intmux: intmux@37400000 {
+ compatible = "fsl,imx-intmux";
+ reg = <0x37400000 0x1000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ clocks = <&cm40_ipg_clk>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
+ status = "disabled";
+ };
+
+ cm40_i2c_lpcg: clock-controller@37630000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37630000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "cm40_lpcg_i2c_clk",
+ "cm40_lpcg_i2c_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index a0674c5c55766..9d49c75a26222 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
};
/* sorted in register address */
+ #include "imx8-ss-cm40.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 10e16d84c0c3b..0313f295de2e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -317,6 +317,7 @@ map0 {
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
+ #include "imx8-ss-cm40.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
--
2.34.1
From: Alice Guo <[email protected]>
Add lpuart device in cm40 subsystem.
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
index 68043ab74e765..b6af85b20ddd7 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -20,6 +20,18 @@ cm40_subsys: bus@34000000 {
#size-cells = <1>;
ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+ cm40_lpuart: serial@37220000 {
+ compatible = "fsl,imx8qxp-lpuart";
+ reg = <0x37220000 0x1000>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ status = "disabled";
+ };
+
cm40_i2c: i2c@37230000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x37230000 0x1000>;
@@ -53,6 +65,18 @@ cm40_intmux: intmux@37400000 {
status = "disabled";
};
+ cm40_uart_lpcg: clock-controller@37620000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37620000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
+ clock-output-names = "cm40_lpcg_uart_clk",
+ "cm40_lpcg_uart_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ };
+
cm40_i2c_lpcg: clock-controller@37630000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37630000 0x1000>;
--
2.34.1
Update cm40 irq number for imx8dxl chip.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index 9d49c75a26222..b9d137d69f5a7 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -243,3 +243,14 @@ xtal24m: clock-xtal24m {
#include "imx8dxl-ss-conn.dtsi"
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-ddr.dtsi"
+
+&cm40_intmux {
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.34.1
Add lpuart1 and cm40 uart.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 37 +++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 2123d431e0613..737bacacc2da1 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -16,6 +16,8 @@ aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial6 = &cm40_lpuart;
};
chosen {
@@ -51,6 +53,16 @@ linux,cma {
};
};
+ m2_uart1_sel: fixedregulator-101 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "m2_uart1_sel";
+ gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
mux3_en: regulator-0 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
@@ -340,6 +352,12 @@ &lpuart0 {
status = "okay";
};
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
@@ -354,6 +372,16 @@ &flexcan3 {
status = "okay";
};
+&cm40_intmux {
+ status = "disabled";
+};
+
+&cm40_lpuart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cm40_lpuart>;
+ status = "disabled";
+};
+
&lsio_gpio4 {
status = "okay";
};
@@ -595,6 +623,15 @@ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
--
2.34.1
Hi Frank,
thanks for the update.
Am Samstag, 2. M?rz 2024, 17:27:44 CET schrieb Frank Li:
> From: Dong Aisheng <[email protected]>
>
> Add cm40 subsystem dtsi.
>
> Signed-off-by: Dong Aisheng <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
> 3 files changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> new file mode 100644
> index 0000000000000..68043ab74e765
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + * Dong Aisheng <[email protected]>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +cm40_ipg_clk: clock-cm40-ipg {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <132000000>;
> + clock-output-names = "cm40_ipg_clk";
> +};
> +
> +cm40_subsys: bus@34000000 {
> + compatible = "simple-bus";
> + interrupt-parent = <&cm40_intmux>;
I would have put that below ranges, but it might be just personal preference.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x34000000 0x0 0x34000000 0x4000000>;
> +
> + cm40_i2c: i2c@37230000 {
> + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x37230000 0x1000>;
> + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cm40_i2c_lpcg 0>,
> + <&cm40_i2c_lpcg 1>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_M4_0_I2C>;
> + status = "disabled";
> + };
> +
> + cm40_intmux: intmux@37400000 {
> + compatible = "fsl,imx-intmux";
> + reg = <0x37400000 0x1000>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
Please put this above interrupt property, you are mixing interrupt
properties of the device itself with interrupt-controller properties.
With these things addressed:
Reviewed-by: Alexander Stein <[email protected]>
> + #interrupt-cells = <2>;
> + clocks = <&cm40_ipg_clk>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
> + status = "disabled";
> + };
> +
> + cm40_i2c_lpcg: clock-controller@37630000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x37630000 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
> + <&cm40_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "cm40_lpcg_i2c_clk",
> + "cm40_lpcg_i2c_ipg_clk";
> + power-domains = <&pd IMX_SC_R_M4_0_I2C>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> index a0674c5c55766..9d49c75a26222 100644
> --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> @@ -5,6 +5,7 @@
>
> #include <dt-bindings/clock/imx8-clock.h>
> #include <dt-bindings/dma/fsl-edma.h>
> +#include <dt-bindings/clock/imx8-lpcg.h>
> #include <dt-bindings/firmware/imx/rsrc.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
> };
>
> /* sorted in register address */
> + #include "imx8-ss-cm40.dtsi"
> #include "imx8-ss-adma.dtsi"
> #include "imx8-ss-conn.dtsi"
> #include "imx8-ss-ddr.dtsi"
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 10e16d84c0c3b..0313f295de2e9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -317,6 +317,7 @@ map0 {
> /* sorted in register address */
> #include "imx8-ss-img.dtsi"
> #include "imx8-ss-vpu.dtsi"
> + #include "imx8-ss-cm40.dtsi"
> #include "imx8-ss-gpu0.dtsi"
> #include "imx8-ss-adma.dtsi"
> #include "imx8-ss-conn.dtsi"
>
>
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/
Hi Frank,
thanks for the update.
Am Samstag, 2. M?rz 2024, 17:27:45 CET schrieb Frank Li:
> From: Alice Guo <[email protected]>
>
> Add lpuart device in cm40 subsystem.
>
> Signed-off-by: Alice Guo <[email protected]>
> Reviewed-by: Peng Fan <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
Reviewed-by: Alexander Stein <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> index 68043ab74e765..b6af85b20ddd7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> @@ -20,6 +20,18 @@ cm40_subsys: bus@34000000 {
> #size-cells = <1>;
> ranges = <0x34000000 0x0 0x34000000 0x4000000>;
>
> + cm40_lpuart: serial@37220000 {
> + compatible = "fsl,imx8qxp-lpuart";
> + reg = <0x37220000 0x1000>;
> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>;
> + clock-names = "ipg", "baud";
> + assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_M4_0_UART>;
> + status = "disabled";
> + };
> +
> cm40_i2c: i2c@37230000 {
> compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> reg = <0x37230000 0x1000>;
> @@ -53,6 +65,18 @@ cm40_intmux: intmux@37400000 {
> status = "disabled";
> };
>
> + cm40_uart_lpcg: clock-controller@37620000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x37620000 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
> + <&cm40_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
> + clock-output-names = "cm40_lpcg_uart_clk",
> + "cm40_lpcg_uart_ipg_clk";
> + power-domains = <&pd IMX_SC_R_M4_0_UART>;
> + };
> +
> cm40_i2c_lpcg: clock-controller@37630000 {
> compatible = "fsl,imx8qxp-lpcg";
> reg = <0x37630000 0x1000>;
>
>
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/