Hello,
Here I'd like to propose a patchset, which is initial upstream support for NXP
S32G2. S32G is a processor family developed by NXP for automotive solutions,
such as vehicle networking and automotive high-performance processing. This
series focuses on S32G2, which is the latest generation we can find at the
moment. As the first round to support S32G2, this patchset only enables basic
components and interfaces the SoC must have while kernel booting, which aims
to have minimum hardware enablement for these two boards, S32G-VNP-EVB and
S32G-VNP-RDB2. The concepts of how these boards work are originated from the
downstream kernel tree[1] developed by NXP, which provides lots of details
about the SoC S32G274A and its integrated boards. This series has been
verified with downstream ATF[2] & U-Boot[3] based on the ATF boot flow.
Thanks,
Chester
[1] https://source.codeaurora.org/external/autobsps32/linux/
[2] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/
[3] https://source.codeaurora.org/external/autobsps32/u-boot/
Chester Lin (8):
dt-bindings: arm: fsl: add NXP S32G2 boards
dt-bindings: serial: fsl-linflexuart: convert to json-schema format
dt-bindings: serial: fsl-linflexuart: Add compatible for S32G2
arm64: dts: add NXP S32G2 support
arm64: dts: s32g2: add serial/uart support
arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support
arm64: dts: s32g2: add memory nodes for evb and rdb2
MAINTAINERS: Add an entry for NXP S32G2 boards
.../devicetree/bindings/arm/fsl.yaml | 7 +
.../bindings/serial/fsl,s32-linflexuart.txt | 22 ---
.../bindings/serial/fsl,s32-linflexuart.yaml | 66 +++++++++
MAINTAINERS | 6 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
arch/arm64/boot/dts/freescale/s32g2.dtsi | 129 ++++++++++++++++++
.../arm64/boot/dts/freescale/s32g274a-evb.dts | 29 ++++
.../boot/dts/freescale/s32g274a-rdb2.dts | 33 +++++
8 files changed, 272 insertions(+), 22 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt
create mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-evb.dts
create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
--
2.30.0
Add an initial dtsi file for generic SoC features of NXP S32G2.
Signed-off-by: Chester Lin <[email protected]>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++
1 file changed, 98 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
new file mode 100644
index 000000000000..3321819c1a2d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 SUSE LLC
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "fsl,s32g2";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cluster0_l2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ cluster1_l2: l2-cache1 {
+ compatible = "cache";
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges;
+
+ gic: interrupt-controller@50800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0x50800000 0 0x10000>,
+ <0 0x50880000 0 0x200000>,
+ <0 0x50400000 0 0x2000>,
+ <0 0x50410000 0 0x2000>,
+ <0 0x50420000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+};
--
2.30.0
Add serial/uart support for NXP S32G2.
Signed-off-by: Chester Lin <[email protected]>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 31 ++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 3321819c1a2d..0076eacad8a6 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
+ * Copyright 2017-2020 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -11,6 +12,12 @@ / {
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,6 +89,30 @@ soc {
ranges;
+ uart0: serial@401c8000 {
+ compatible = "fsl,s32g2-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0 0x401c8000 0 0x3000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ uart1: serial@401cc000 {
+ compatible = "fsl,s32g2-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0 0x401cc000 0 0x3000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ uart2: serial@402bc000 {
+ compatible = "fsl,s32g2-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0 0x402bc000 0 0x3000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.30.0
Add a new entry for the maintenance of NXP S32G2 DT files.
Signed-off-by: Chester Lin <[email protected]>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 36aee8517ab0..3c6ba6cefd8f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2281,6 +2281,12 @@ F: arch/arm/boot/dts/nuvoton-wpcm450*
F: arch/arm/mach-npcm/wpcm450.c
F: drivers/*/*wpcm*
+ARM/NXP S32G2 ARCHITECTURE
+M: Chester Lin <[email protected]>
+L: [email protected] (moderated for non-subscribers)
+S: Maintained
+F: arch/arm64/boot/dts/freescale/s32g2*
+
ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
L: [email protected] (subscribers-only)
S: Orphan
--
2.30.0
On 05/08/2021 08:54, Chester Lin wrote:
> Add a new entry for the maintenance of NXP S32G2 DT files.
>
> Signed-off-by: Chester Lin <[email protected]>
> ---
> MAINTAINERS | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 36aee8517ab0..3c6ba6cefd8f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2281,6 +2281,12 @@ F: arch/arm/boot/dts/nuvoton-wpcm450*
> F: arch/arm/mach-npcm/wpcm450.c
> F: drivers/*/*wpcm*
>
> +ARM/NXP S32G2 ARCHITECTURE
> +M: Chester Lin <[email protected]>
> +L: [email protected] (moderated for non-subscribers)
> +S: Maintained
> +F: arch/arm64/boot/dts/freescale/s32g2*
I support the idea of sub-sub-architecture maintainers but I think idea
of in-file addresses was preferred:
https://lore.kernel.org/lkml/[email protected]/
Best regards,
Krzysztof
On Thu, Aug 05, 2021 at 09:49:51AM +0200, Krzysztof Kozlowski wrote:
> On 05/08/2021 08:54, Chester Lin wrote:
> > Add a new entry for the maintenance of NXP S32G2 DT files.
> >
> > Signed-off-by: Chester Lin <[email protected]>
> > ---
> > MAINTAINERS | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 36aee8517ab0..3c6ba6cefd8f 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -2281,6 +2281,12 @@ F: arch/arm/boot/dts/nuvoton-wpcm450*
> > F: arch/arm/mach-npcm/wpcm450.c
> > F: drivers/*/*wpcm*
> >
> > +ARM/NXP S32G2 ARCHITECTURE
> > +M: Chester Lin <[email protected]>
> > +L: [email protected] (moderated for non-subscribers)
> > +S: Maintained
> > +F: arch/arm64/boot/dts/freescale/s32g2*
>
> I support the idea of sub-sub-architecture maintainers but I think idea
> of in-file addresses was preferred:
> https://lore.kernel.org/lkml/[email protected]/
Thanks for reminding that the patch didn't land. I just resent it with
your Reviewed-by tag added. Thanks!
Shawn
On Thu, Aug 05, 2021 at 02:54:21PM +0800, Chester Lin wrote:
> Hello,
>
> Here I'd like to propose a patchset, which is initial upstream support for NXP
> S32G2. S32G is a processor family developed by NXP for automotive solutions,
> such as vehicle networking and automotive high-performance processing. This
> series focuses on S32G2, which is the latest generation we can find at the
> moment. As the first round to support S32G2, this patchset only enables basic
> components and interfaces the SoC must have while kernel booting, which aims
> to have minimum hardware enablement for these two boards, S32G-VNP-EVB and
> S32G-VNP-RDB2. The concepts of how these boards work are originated from the
> downstream kernel tree[1] developed by NXP, which provides lots of details
> about the SoC S32G274A and its integrated boards. This series has been
> verified with downstream ATF[2] & U-Boot[3] based on the ATF boot flow.
>
> Thanks,
> Chester
>
> [1] https://source.codeaurora.org/external/autobsps32/linux/
> [2] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/
> [3] https://source.codeaurora.org/external/autobsps32/u-boot/
>
> Chester Lin (8):
> dt-bindings: arm: fsl: add NXP S32G2 boards
> dt-bindings: serial: fsl-linflexuart: convert to json-schema format
> dt-bindings: serial: fsl-linflexuart: Add compatible for S32G2
> arm64: dts: add NXP S32G2 support
> arm64: dts: s32g2: add serial/uart support
> arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support
> arm64: dts: s32g2: add memory nodes for evb and rdb2
The dts changes look good to me. I will pick up the series once
bindings gets acked by Rob.
Shawn
> MAINTAINERS: Add an entry for NXP S32G2 boards
>
> .../devicetree/bindings/arm/fsl.yaml | 7 +
> .../bindings/serial/fsl,s32-linflexuart.txt | 22 ---
> .../bindings/serial/fsl,s32-linflexuart.yaml | 66 +++++++++
> MAINTAINERS | 6 +
> arch/arm64/boot/dts/freescale/Makefile | 2 +
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 129 ++++++++++++++++++
> .../arm64/boot/dts/freescale/s32g274a-evb.dts | 29 ++++
> .../boot/dts/freescale/s32g274a-rdb2.dts | 33 +++++
> 8 files changed, 272 insertions(+), 22 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt
> create mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
> create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
>
> --
> 2.30.0
>
On 12/08/2021 17:30, Andreas Färber wrote:
> Hello Shawn and Krzysztof,
>
> On 09.08.21 10:03, Shawn Guo wrote:
>> On Thu, Aug 05, 2021 at 09:49:51AM +0200, Krzysztof Kozlowski wrote:
>>> On 05/08/2021 08:54, Chester Lin wrote:
>>>> Add a new entry for the maintenance of NXP S32G2 DT files.
>>>>
>>>> Signed-off-by: Chester Lin <[email protected]>
>>>> ---
>>>> MAINTAINERS | 6 ++++++
>>>> 1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>> index 36aee8517ab0..3c6ba6cefd8f 100644
>>>> --- a/MAINTAINERS
>>>> +++ b/MAINTAINERS
>>>> @@ -2281,6 +2281,12 @@ F: arch/arm/boot/dts/nuvoton-wpcm450*
>>>> F: arch/arm/mach-npcm/wpcm450.c
>>>> F: drivers/*/*wpcm*
>>>>
>>>> +ARM/NXP S32G2 ARCHITECTURE
>
> Suggestion from NXP is to use the broader S32G name.
>
>>>> +M: Chester Lin <[email protected]>
>>>> +L: [email protected] (moderated for non-subscribers)
>>>> +S: Maintained
>>>> +F: arch/arm64/boot/dts/freescale/s32g2*
>>>
>>> I support the idea of sub-sub-architecture maintainers but I think idea
>>> of in-file addresses was preferred:
>>> https://lore.kernel.org/lkml/[email protected]/
>
> I had specifically asked Chester to add a MAINTAINERS section.
>
> Is your apparent suggestion of not accepting this MAINTAINERS patch
> based on the assumption that we're dealing with only one email address
> in three files? What do you see as the threshold to warrant a section?
>
> From my point of view, above MAINTAINERS entry is incomplete, as we
> should CC the full team working on S32G for patch review, not just
> Chester himself.
> So that would in my mind have been additional R: and L: entries in that
> MAINTAINERS section.
I assumed this is a sub-sub-architecture (something coming from
Layerscape or i.MX) but it seems it's not, therefore I don't mind having
separate entry in MAINTAINERS. The idea of in-file maintainers was for
specific boards and SoCs belonging to existing sub-architectures.
I agree with your following reasons.
>
>> Thanks for reminding that the patch didn't land. I just resent it with
>> your Reviewed-by tag added. Thanks!
>
> Your above patch does not make clear to me what syntax we should use for
> adding email addresses to .dts[i] files now:
>
> https://lore.kernel.org/lkml/20210809081033.GQ30984@dragon/
>
> Especially when not dealing with file authors.
>
> I get the impression it is not a replacement for an F: wildcard used in
> MAINTAINERS, but rather a complement?
>
> Please understand that this is not about a single .dts file, as your
> patch suggests, but about a complete SoC family consisting of s32g*.dts*
> as well as in the future drivers specific to this platform. It seems way
> easier to specify the list of maintainers/reviewers in MAINTAINERS once
> with suitable wildcard paths, than copying them into each and every
> .dtsi and .dts file and driver .c/.h and later needing to sync multiple
> places. If a bot or user has fixes or cleanups for the S32G code, we
> want to know about it, so that NXP can consider it for their BSP
> branches and SUSE for our SLE branches, and obviously for follow-up
> patch series that are already in the works and waiting on this one.
>
> Once merged, I would expect Chester or someone from NXP to set up an
> S32G tree on kernel.org that gets integrated into linux-next and sends
> pull requests to the SoC tree maintainers without bothering i.MX and
> Layerscape maintainers. Did you handle that differently for S32V?
>
> Thanks,
> Andreas
>
> P.S. Have you checked or considered whether your script change might
> start to CC non-existing email addresses, since we wouldn't be allowed
> to remove them from copyright or authorship statements to prevent that?
The same can happen for DT bindings maintainers.
Best regards,
Krzysztof
Hello Shawn and Krzysztof,
On 09.08.21 10:03, Shawn Guo wrote:
> On Thu, Aug 05, 2021 at 09:49:51AM +0200, Krzysztof Kozlowski wrote:
>> On 05/08/2021 08:54, Chester Lin wrote:
>>> Add a new entry for the maintenance of NXP S32G2 DT files.
>>>
>>> Signed-off-by: Chester Lin <[email protected]>
>>> ---
>>> MAINTAINERS | 6 ++++++
>>> 1 file changed, 6 insertions(+)
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 36aee8517ab0..3c6ba6cefd8f 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -2281,6 +2281,12 @@ F: arch/arm/boot/dts/nuvoton-wpcm450*
>>> F: arch/arm/mach-npcm/wpcm450.c
>>> F: drivers/*/*wpcm*
>>>
>>> +ARM/NXP S32G2 ARCHITECTURE
Suggestion from NXP is to use the broader S32G name.
>>> +M: Chester Lin <[email protected]>
>>> +L: [email protected] (moderated for non-subscribers)
>>> +S: Maintained
>>> +F: arch/arm64/boot/dts/freescale/s32g2*
>>
>> I support the idea of sub-sub-architecture maintainers but I think idea
>> of in-file addresses was preferred:
>> https://lore.kernel.org/lkml/[email protected]/
I had specifically asked Chester to add a MAINTAINERS section.
Is your apparent suggestion of not accepting this MAINTAINERS patch
based on the assumption that we're dealing with only one email address
in three files? What do you see as the threshold to warrant a section?
From my point of view, above MAINTAINERS entry is incomplete, as we
should CC the full team working on S32G for patch review, not just
Chester himself.
So that would in my mind have been additional R: and L: entries in that
MAINTAINERS section.
> Thanks for reminding that the patch didn't land. I just resent it with
> your Reviewed-by tag added. Thanks!
Your above patch does not make clear to me what syntax we should use for
adding email addresses to .dts[i] files now:
https://lore.kernel.org/lkml/20210809081033.GQ30984@dragon/
Especially when not dealing with file authors.
I get the impression it is not a replacement for an F: wildcard used in
MAINTAINERS, but rather a complement?
Please understand that this is not about a single .dts file, as your
patch suggests, but about a complete SoC family consisting of s32g*.dts*
as well as in the future drivers specific to this platform. It seems way
easier to specify the list of maintainers/reviewers in MAINTAINERS once
with suitable wildcard paths, than copying them into each and every
.dtsi and .dts file and driver .c/.h and later needing to sync multiple
places. If a bot or user has fixes or cleanups for the S32G code, we
want to know about it, so that NXP can consider it for their BSP
branches and SUSE for our SLE branches, and obviously for follow-up
patch series that are already in the works and waiting on this one.
Once merged, I would expect Chester or someone from NXP to set up an
S32G tree on kernel.org that gets integrated into linux-next and sends
pull requests to the SoC tree maintainers without bothering i.MX and
Layerscape maintainers. Did you handle that differently for S32V?
Thanks,
Andreas
P.S. Have you checked or considered whether your script change might
start to CC non-existing email addresses, since we wouldn't be allowed
to remove them from copyright or authorship statements to prevent that?
--
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer
HRB 36809 (AG Nürnberg)
Hi Chester et al.,
On 05.08.21 08:54, Chester Lin wrote:
> Add an initial dtsi file for generic SoC features of NXP S32G2.
>
> Signed-off-by: Chester Lin <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++
> 1 file changed, 98 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> new file mode 100644
> index 000000000000..3321819c1a2d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
Note: This DT is for running on the Cortex-A53 cores, but S32G2 also has
Cortex-M7 cores. For Vybrid SoCs, DTs later got contributed to also run
on its Cortex-M4 core:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf610.dtsi
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf500.dtsi
vs.
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf610m4.dtsi
Should we plan for this in our file naming here and in following patches
(e.g., s32g2-a53* vs. s32g2-m7*)? To me, a later concatenation of
s32g274am7* would look awkward, and s32g274a-m7* would sort between -evb
and -rdb2.
> @@ -0,0 +1,98 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
* NXP S32G2 SoC family
*
?
@NXP: Are any models other than 274A in the queue that we should
distinguish between s32g2.dtsi and s32g274a.dtsi here already?
> + * Copyright (c) 2021 SUSE LLC
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "fsl,s32g2";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&cluster0_l2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&cluster0_l2>;
> + };
> +
> + cpu2: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x100>;
> + enable-method = "psci";
> + next-level-cache = <&cluster1_l2>;
> + };
> +
> + cpu3: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x101>;
> + enable-method = "psci";
> + next-level-cache = <&cluster1_l2>;
> + };
> +
> + cluster0_l2: l2-cache0 {
> + compatible = "cache";
> + };
> +
> + cluster1_l2: l2-cache1 {
> + compatible = "cache";
> + };
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
Should we move this into a /firmware node, to group with future OP-TEE?
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&gic>;
Duplicate, already set on root node.
> + #address-cells = <2>;
> + #size-cells = <2>;
Why? Does it have any peripherals that go beyond 32-bit space?
For 64-bit Realtek platforms Rob had asked me to use 1, if possible.
I do understand that for /memory nodes we do have high-memory addresses,
so 2 for the root node looks correct.
> +
Please drop this white line.
> + ranges;
According to Rob, the /soc ranges should exclude any RAM ranges for
safety reasons. Compare:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/realtek/rtd129x.dtsi
If you're lacking the maximum RAM areas to carve out, NXP is in CC to
help out :) and the EVB and RDB2 boards should give you starting numbers
that could be enlarged later if needed.
> +
> + gic: interrupt-controller@50800000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0 0x50800000 0 0x10000>,
> + <0 0x50880000 0 0x200000>,
> + <0 0x50400000 0 0x2000>,
> + <0 0x50410000 0 0x2000>,
> + <0 0x50420000 0 0x2000>;
Please order reg after compatible by convention, and sort
interrupt-controller or at least #interrupt-cells (applying to
consumers) last, after the below one applying to this device itself.
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + };
CC'ing Marc for additional GIC scrutiny, often the sizes are wrong.
> + };
> +};
Thanks,
Andreas
--
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer
HRB 36809 (AG Nürnberg)
Hi Chester et al.,
On 05.08.21 08:54, Chester Lin wrote:
> Add serial/uart support for NXP S32G2.
You might mention here that (following our initial stub) this commit is
now apparently based on the CodeAurora BSP branch foo (and therefore
adding its last-year copyright below and separate from 4/8).
>
@NXP: If there are downstream Signed-off-bys that you would like to see
included for this portion here, please speak up.
> Signed-off-by: Chester Lin <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 31 ++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 3321819c1a2d..0076eacad8a6 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> /*
> * Copyright (c) 2021 SUSE LLC
> + * Copyright 2017-2020 NXP
@NXP: Should this be updated to include 2021 from your latest BSP
releases? Do you want it visually aligned by adding the ASCII-art?
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -11,6 +12,12 @@ / {
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + };
Note: In the past there had been controversies as to whether to define
aliases globally for a SoC or in a .dts specific to a board's usage.
In this case it does not seem to matter much, as uart0 is being used as
console on the reference boards.
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -82,6 +89,30 @@ soc {
>
> ranges;
>
> + uart0: serial@401c8000 {
> + compatible = "fsl,s32g2-linflexuart",
> + "fsl,s32v234-linflexuart";
> + reg = <0 0x401c8000 0 0x3000>;
> + interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
> + status = "disabled";
> + };
> +
> + uart1: serial@401cc000 {
> + compatible = "fsl,s32g2-linflexuart",
> + "fsl,s32v234-linflexuart";
> + reg = <0 0x401cc000 0 0x3000>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
> + status = "disabled";
> + };
> +
> + uart2: serial@402bc000 {
> + compatible = "fsl,s32g2-linflexuart",
> + "fsl,s32v234-linflexuart";
> + reg = <0 0x402bc000 0 0x3000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@50800000 {
> compatible = "arm,gic-v3";
> #interrupt-cells = <3>;
Regards,
Andreas
--
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer
HRB 36809 (AG Nürnberg)
On Thu, Aug 12, 2021 at 07:26:28PM +0200, Andreas F?rber wrote:
> Hi Chester et al.,
>
> On 05.08.21 08:54, Chester Lin wrote:
> > Add an initial dtsi file for generic SoC features of NXP S32G2.
> >
> > Signed-off-by: Chester Lin <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++
> > 1 file changed, 98 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > new file mode 100644
> > index 000000000000..3321819c1a2d
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>
> Note: This DT is for running on the Cortex-A53 cores, but S32G2 also has
> Cortex-M7 cores. For Vybrid SoCs, DTs later got contributed to also run
> on its Cortex-M4 core:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf610.dtsi
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf500.dtsi
> vs.
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf610m4.dtsi
>
> Should we plan for this in our file naming here and in following patches
> (e.g., s32g2-a53* vs. s32g2-m7*)? To me, a later concatenation of
> s32g274am7* would look awkward, and s32g274a-m7* would sort between -evb
> and -rdb2.
>
> > @@ -0,0 +1,98 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > +/*
>
> * NXP S32G2 SoC family
> *
> ?
Will add it.
>
> @NXP: Are any models other than 274A in the queue that we should
> distinguish between s32g2.dtsi and s32g274a.dtsi here already?
>
> > + * Copyright (c) 2021 SUSE LLC
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + compatible = "fsl,s32g2";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0>;
> > + enable-method = "psci";
> > + next-level-cache = <&cluster0_l2>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x1>;
> > + enable-method = "psci";
> > + next-level-cache = <&cluster0_l2>;
> > + };
> > +
> > + cpu2: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x100>;
> > + enable-method = "psci";
> > + next-level-cache = <&cluster1_l2>;
> > + };
> > +
> > + cpu3: cpu@101 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x101>;
> > + enable-method = "psci";
> > + next-level-cache = <&cluster1_l2>;
> > + };
> > +
> > + cluster0_l2: l2-cache0 {
> > + compatible = "cache";
> > + };
> > +
> > + cluster1_l2: l2-cache1 {
> > + compatible = "cache";
> > + };
> > + };
> > +
> > + pmu {
> > + compatible = "arm,cortex-a53-pmu";
> > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>
> interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
Actually I traced the pmu_parse_irqs() and found that this SoC never falls into
the pmu_has_irq_affinity() check because it's a percpu IRQ so the flow ends at
pmu_parse_percpu_irq(). But it looks good to me to have an interrupt-affinity
to indicate that each core has an associated PPI for PMU events as the binding
file has suggested.
>
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
>
> Should we move this into a /firmware node, to group with future OP-TEE?
>
So far I can only see a few examples [e.g. ti/k3-*] which add the psci node
into /firmware but logically we should do it.
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&gic>;
>
> Duplicate, already set on root node.
Will remove it.
>
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> Why? Does it have any peripherals that go beyond 32-bit space?
> For 64-bit Realtek platforms Rob had asked me to use 1, if possible.
> I do understand that for /memory nodes we do have high-memory addresses,
> so 2 for the root node looks correct.
Actually it's a limitation due to [PATCH 7/8] "arm64: dts: s32g2: add memory
nodes for evb and rdb2", which adds memory nodes to indicate maximum system
RAM size combined by two separated memory banks, and the second bank starts
from the offset 0x880000000 so that's why we need 64-bit address space here.
Please feel free to let me know if any suggestion.
>
> > +
>
> Please drop this white line.
>
Will do.
> > + ranges;
>
> According to Rob, the /soc ranges should exclude any RAM ranges for
> safety reasons. Compare:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/realtek/rtd129x.dtsi
>
> If you're lacking the maximum RAM areas to carve out, NXP is in CC to
> help out :) and the EVB and RDB2 boards should give you starting numbers
> that could be enlarged later if needed.
I added memory nodes in [PATCH 7/8] "arm64: dts: s32g2: add memory nodes for
evb and rdb2" to describe maximum RAM areas, which are based on the information
we found in NXP BSP and boards.
@NXP: Please feel free to correct me if anything wrong, thanks.
>
> > +
> > + gic: interrupt-controller@50800000 {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0 0x50800000 0 0x10000>,
> > + <0 0x50880000 0 0x200000>,
> > + <0 0x50400000 0 0x2000>,
> > + <0 0x50410000 0 0x2000>,
> > + <0 0x50420000 0 0x2000>;
>
> Please order reg after compatible by convention, and sort
> interrupt-controller or at least #interrupt-cells (applying to
> consumers) last, after the below one applying to this device itself.
>
Will do.
> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> > + IRQ_TYPE_LEVEL_HIGH)>;
> > + };
>
> CC'ing Marc for additional GIC scrutiny, often the sizes are wrong.
>
IIRC, gic-v3 shouldn't have this kind of interrupt specifier. It's my fault and
will fix it. Feel free to let me know if any suggestions.
> > + };
> > +};
>
> Thanks,
> Andreas
>
> --
> SUSE Software Solutions Germany GmbH
> Maxfeldstr. 5, 90409 N?rnberg, Germany
> GF: Felix Imend?rffer
> HRB 36809 (AG N?rnberg)
>
Hi Chester,
On 13.08.21 05:28, Chester Lin wrote:
> On Thu, Aug 12, 2021 at 07:26:28PM +0200, Andreas Färber wrote:
>> On 05.08.21 08:54, Chester Lin wrote:
>>> Add an initial dtsi file for generic SoC features of NXP S32G2.
>>>
>>> Signed-off-by: Chester Lin <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++
>>> 1 file changed, 98 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>>> new file mode 100644
>>> index 000000000000..3321819c1a2d
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>>
>> Note: This DT is for running on the Cortex-A53 cores, but S32G2 also has
>> Cortex-M7 cores. For Vybrid SoCs, DTs later got contributed to also run
>> on its Cortex-M4 core:
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf610.dtsi
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf500.dtsi
>> vs.
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/vf610m4.dtsi
>>
>> Should we plan for this in our file naming here and in following patches
>> (e.g., s32g2-a53* vs. s32g2-m7*)? To me, a later concatenation of
>> s32g274am7* would look awkward, and s32g274a-m7* would sort between -evb
>> and -rdb2.
>>
>>> @@ -0,0 +1,98 @@
>>> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>>> +/*
>>
>> * NXP S32G2 SoC family
>> *
>> ?
>
> Will add it.
>
>>
>> @NXP: Are any models other than 274A in the queue that we should
>> distinguish between s32g2.dtsi and s32g274a.dtsi here already?
>>
>>> + * Copyright (c) 2021 SUSE LLC
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> + compatible = "fsl,s32g2";
>>> + interrupt-parent = <&gic>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
[...]
>>> + pmu {
>>> + compatible = "arm,cortex-a53-pmu";
>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>>
>> interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
>
> Actually I traced the pmu_parse_irqs() and found that this SoC never falls into
> the pmu_has_irq_affinity() check because it's a percpu IRQ so the flow ends at
> pmu_parse_percpu_irq(). But it looks good to me to have an interrupt-affinity
> to indicate that each core has an associated PPI for PMU events as the binding
> file has suggested.
My comment was based on the DT binding requesting it also for PPI and
previous review requests for me to add it elsewhere, so it's quite
possible that your code analysis is correct.
FWIW also the cache nodes were not evaluated last time I checked,
although the specs do show those nodes and properties.
https://github.com/devicetree-org/devicetree-specification/blob/v0.3/source/devicenodes.rst
>>> + };
[...]
>>> +
>>> + soc {
>>> + compatible = "simple-bus";
[...]
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>
>> Why? Does it have any peripherals that go beyond 32-bit space?
>> For 64-bit Realtek platforms Rob had asked me to use 1, if possible.
>> I do understand that for /memory nodes we do have high-memory addresses,
>> so 2 for the root node looks correct.
>
> Actually it's a limitation due to [PATCH 7/8] "arm64: dts: s32g2: add memory
> nodes for evb and rdb2", which adds memory nodes to indicate maximum system
> RAM size combined by two separated memory banks, and the second bank starts
> from the offset 0x880000000 so that's why we need 64-bit address space here.
> Please feel free to let me know if any suggestion.
The /memory nodes are on the root node and thus only use #address-cells
and #size-cells from /, not from /soc here. Thus the only criterium is
whether something within /soc needs it.
PCI controllers may have 3 address cells, SPI/I2C controllers 1, so you
can have multiple sizes within one DT, you just need suitable ranges
wherever mappings to the parent address space are needed.
(I thought you had that distinction in an earlier draft I reviewed.)
Similarly, /reserved-memory would be outside the /soc node and use the
root node's #(address|size)-cells.
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
Note: I'm assuming that if someone were to add a DT for the Cortex-M7s,
the address space mapping of any shared peripherals will likely differ,
as would the interrupts obviously, so I assume no direct .dtsi sharing
of /soc sub-nodes could sensibly be applied here.
@NXP: Please correct me if I'm wrong in either M7 not having access to
DDR RAM or large enough SRAM for Linux or another DT-consuming OS (and
this line of thinking not being applicable then) or you having use cases
to factor out some of the /soc sub-nodes for sharing between the two
(which would then give another reason for #address-/size-cells = <1> for
32-bit Cortex-M7).
[...]
>>> + ranges;
>>
>> According to Rob, the /soc ranges should exclude any RAM ranges for
>> safety reasons. Compare:
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/realtek/rtd129x.dtsi
>>
>> If you're lacking the maximum RAM areas to carve out, NXP is in CC to
>> help out :) and the EVB and RDB2 boards should give you starting numbers
>> that could be enlarged later if needed.
>
> I added memory nodes in [PATCH 7/8] "arm64: dts: s32g2: add memory nodes for
> evb and rdb2" to describe maximum RAM areas, which are based on the information
> we found in NXP BSP and boards.
Yes, as discussed in 7/8, you should be using here:
ranges = <0x0 0 0x0 0x80000000>; /* excluding 4 GiB RAM */
https://github.com/devicetree-org/devicetree-specification/blob/v0.3/source/devicetree-basics.rst
> @NXP: Please feel free to correct me if anything wrong, thanks.
>
>>
>>> +
>>> + gic: interrupt-controller@50800000 {
>>> + compatible = "arm,gic-v3";
>>> + #interrupt-cells = <3>;
>>> + interrupt-controller;
>>> + reg = <0 0x50800000 0 0x10000>,
>>> + <0 0x50880000 0 0x200000>,
>>> + <0 0x50400000 0 0x2000>,
>>> + <0 0x50410000 0 0x2000>,
>>> + <0 0x50420000 0 0x2000>;
>>
>> Please order reg after compatible by convention, and sort
>> interrupt-controller or at least #interrupt-cells (applying to
>> consumers) last, after the below one applying to this device itself.
>>
>
> Will do.
>
>>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
>>> + IRQ_TYPE_LEVEL_HIGH)>;
>>> + };
>>
>> CC'ing Marc for additional GIC scrutiny, often the sizes are wrong.
>>
>
> IIRC, gic-v3 shouldn't have this kind of interrupt specifier. It's my fault and
> will fix it. Feel free to let me know if any suggestions.
You probably mean the GIC_CPU_MASK_SIMPLE()?
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
The interrupts property will be used by KVM (or possibly Xen) for vGIC.
Please ensure that the Kconfig you use for testing has KVM enabled.
>>> + };
>>> +};
Cheers,
Andreas
--
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer
HRB 36809 (AG Nürnberg)
Hi Andreas
On Thu, 2021-08-12 at 19:42 +0200, Andreas Färber wrote:
> Hi Chester et al.,
>
> On 05.08.21 08:54, Chester Lin wrote:
> > Add serial/uart support for NXP S32G2.
>
> You might mention here that (following our initial stub) this commit
> is
> now apparently based on the CodeAurora BSP branch foo (and therefore
> adding its last-year copyright below and separate from 4/8).
>
> >
>
> @NXP: If there are downstream Signed-off-bys that you would like to
> see
> included for this portion here, please speak up.
Larisa signed-off should be added.
Signed-off-by: Larisa Grigore <[email protected]>
>
> > Signed-off-by: Chester Lin <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/s32g2.dtsi | 31
> > ++++++++++++++++++++++++
> > 1 file changed, 31 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > index 3321819c1a2d..0076eacad8a6 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > @@ -1,6 +1,7 @@
> > // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > /*
> > * Copyright (c) 2021 SUSE LLC
> > + * Copyright 2017-2020 NXP
>
> @NXP: Should this be updated to include 2021 from your latest BSP
> releases? Do you want it visually aligned by adding the ASCII-art?
Yes for both questions. The copyright year sould be updated to 2021 and
should be visually aligned.
>
> > */
> >
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -11,6 +12,12 @@ / {
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + aliases {
> > + serial0 = &uart0;
> > + serial1 = &uart1;
> > + serial2 = &uart2;
> > + };
>
> Note: In the past there had been controversies as to whether to
> define
> aliases globally for a SoC or in a .dts specific to a board's usage.
> In this case it does not seem to matter much, as uart0 is being used
> as
> console on the reference boards.
>
> > +
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -82,6 +89,30 @@ soc {
> >
> > ranges;
> >
> > + uart0: serial@401c8000 {
> > + compatible = "fsl,s32g2-linflexuart",
> > + "fsl,s32v234-linflexuart";
> > + reg = <0 0x401c8000 0 0x3000>;
> > + interrupts = <GIC_SPI 82
> > IRQ_TYPE_EDGE_RISING>;
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@401cc000 {
> > + compatible = "fsl,s32g2-linflexuart",
> > + "fsl,s32v234-linflexuart";
> > + reg = <0 0x401cc000 0 0x3000>;
> > + interrupts = <GIC_SPI 83
> > IRQ_TYPE_EDGE_RISING>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@402bc000 {
> > + compatible = "fsl,s32g2-linflexuart",
> > + "fsl,s32v234-linflexuart";
> > + reg = <0 0x402bc000 0 0x3000>;
> > + interrupts = <GIC_SPI 84
> > IRQ_TYPE_EDGE_RISING>;
> > + status = "disabled";
> > + };
> > +
> > gic: interrupt-controller@50800000 {
> > compatible = "arm,gic-v3";
> > #interrupt-cells = <3>;
>
> Regards,
> Andreas
>
On Thu, 12 Aug 2021 18:26:28 +0100,
Andreas Färber <[email protected]> wrote:
>
> Hi Chester et al.,
>
> On 05.08.21 08:54, Chester Lin wrote:
> > Add an initial dtsi file for generic SoC features of NXP S32G2.
> >
> > Signed-off-by: Chester Lin <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++
> > 1 file changed, 98 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > new file mode 100644
> > index 000000000000..3321819c1a2d
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
[...]
> > + gic: interrupt-controller@50800000 {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0 0x50800000 0 0x10000>,
> > + <0 0x50880000 0 0x200000>,
That's enough redistributor space for 16 CPUs. However, you only
describe 4. Either the number of CPUs is wrong, the size is wrong, or
the GIC has been configured for more cores than the SoC has.
> > + <0 0x50400000 0 0x2000>,
> > + <0 0x50410000 0 0x2000>,
> > + <0 0x50420000 0 0x2000>;
>
> Please order reg after compatible by convention, and sort
> interrupt-controller or at least #interrupt-cells (applying to
> consumers) last, after the below one applying to this device itself.
>
> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> > + IRQ_TYPE_LEVEL_HIGH)>;
> > + };
>
> CC'ing Marc for additional GIC scrutiny, often the sizes are wrong.
There is more than just sizes. The interrupt specifier for the
maintenance interrupt is also wrong.
M.
--
Without deviation from the norm, progress is not possible.
On Fri, Aug 20, 2021 at 02:12:13PM +0100, Marc Zyngier wrote:
> On Thu, 12 Aug 2021 18:26:28 +0100,
> Andreas F?rber <[email protected]> wrote:
> >
> > Hi Chester et al.,
> >
> > On 05.08.21 08:54, Chester Lin wrote:
> > > Add an initial dtsi file for generic SoC features of NXP S32G2.
> > >
> > > Signed-off-by: Chester Lin <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++
> > > 1 file changed, 98 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > > new file mode 100644
> > > index 000000000000..3321819c1a2d
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>
> [...]
>
> > > + gic: interrupt-controller@50800000 {
> > > + compatible = "arm,gic-v3";
> > > + #interrupt-cells = <3>;
> > > + interrupt-controller;
> > > + reg = <0 0x50800000 0 0x10000>,
> > > + <0 0x50880000 0 0x200000>,
>
> That's enough redistributor space for 16 CPUs. However, you only
> describe 4. Either the number of CPUs is wrong, the size is wrong, or
> the GIC has been configured for more cores than the SoC has.
Confirmed the SoC can only find 4 redistributors:
localhost:~ # dmesg | grep CPU
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: detected: GIC system register CPU interface
[ 0.000000] CPU features: detected: ARM erratum 845719
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=480 to nr_cpu_ids=4.
[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000
[ 0.063865] smp: Bringing up secondary CPUs ...
[ 0.068852] Detected VIPT I-cache on CPU1
[ 0.068894] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000
[ 0.068963] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 0.069809] Detected VIPT I-cache on CPU2
[ 0.069851] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000
[ 0.069903] CPU2: Booted secondary processor 0x0000000100 [0x410fd034]
[ 0.070698] Detected VIPT I-cache on CPU3
[ 0.070722] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000
[ 0.070749] CPU3: Booted secondary processor 0x0000000101 [0x410fd034]
[ 0.070847] smp: Brought up 1 node, 4 CPUs
<..snip..>
I will correct the size to 0x80000, thanks!
>
> > > + <0 0x50400000 0 0x2000>,
> > > + <0 0x50410000 0 0x2000>,
> > > + <0 0x50420000 0 0x2000>;
> >
> > Please order reg after compatible by convention, and sort
> > interrupt-controller or at least #interrupt-cells (applying to
> > consumers) last, after the below one applying to this device itself.
> >
> > > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> > > + IRQ_TYPE_LEVEL_HIGH)>;
> > > + };
> >
> > CC'ing Marc for additional GIC scrutiny, often the sizes are wrong.
>
> There is more than just sizes. The interrupt specifier for the
> maintenance interrupt is also wrong.
>
> M.
I will remove the wrong interrupt specifier. Thanks!
Chester.
>
> --
> Without deviation from the norm, progress is not possible.
>
On Fri, 20 Aug 2021 16:15:49 +0100,
Chester Lin <[email protected]> wrote:
>
> On Fri, Aug 20, 2021 at 02:12:13PM +0100, Marc Zyngier wrote:
> > On Thu, 12 Aug 2021 18:26:28 +0100,
> > Andreas Färber <[email protected]> wrote:
> > >
> > > Hi Chester et al.,
> > >
> > > On 05.08.21 08:54, Chester Lin wrote:
> > > > Add an initial dtsi file for generic SoC features of NXP S32G2.
> > > >
> > > > Signed-off-by: Chester Lin <[email protected]>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++
> > > > 1 file changed, 98 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > > > new file mode 100644
> > > > index 000000000000..3321819c1a2d
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> >
> > [...]
> >
> > > > + gic: interrupt-controller@50800000 {
> > > > + compatible = "arm,gic-v3";
> > > > + #interrupt-cells = <3>;
> > > > + interrupt-controller;
> > > > + reg = <0 0x50800000 0 0x10000>,
> > > > + <0 0x50880000 0 0x200000>,
> >
> > That's enough redistributor space for 16 CPUs. However, you only
> > describe 4. Either the number of CPUs is wrong, the size is wrong, or
> > the GIC has been configured for more cores than the SoC has.
>
> Confirmed the SoC can only find 4 redistributors:
>
> localhost:~ # dmesg | grep CPU
> [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
> [ 0.000000] Detected VIPT I-cache on CPU0
> [ 0.000000] CPU features: detected: GIC system register CPU interface
> [ 0.000000] CPU features: detected: ARM erratum 845719
> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=480 to nr_cpu_ids=4.
> [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000
> [ 0.063865] smp: Bringing up secondary CPUs ...
> [ 0.068852] Detected VIPT I-cache on CPU1
> [ 0.068894] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000
> [ 0.068963] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
> [ 0.069809] Detected VIPT I-cache on CPU2
> [ 0.069851] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000
> [ 0.069903] CPU2: Booted secondary processor 0x0000000100 [0x410fd034]
> [ 0.070698] Detected VIPT I-cache on CPU3
> [ 0.070722] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000
> [ 0.070749] CPU3: Booted secondary processor 0x0000000101 [0x410fd034]
> [ 0.070847] smp: Brought up 1 node, 4 CPUs
> <..snip..>
That's not the correct way to find out. Each CPU tries to find its
matching RD in the region. This doesn't mean there aren't more RDs
present in the GIC.
You need to iterate over all the RDs in the region until you find one
that has GICR_TYPER.Last == 1. This will give you the actual count.
Alternatively, you can check whether the RD at 508e0000 has that bit
set. If it doesn't, then you know there are more RDs than CPUs.
M.
--
Without deviation from the norm, progress is not possible.
Hi Marc,
On Fri, Aug 20, 2021 at 04:29:00PM +0100, Marc Zyngier wrote:
> On Fri, 20 Aug 2021 16:15:49 +0100,
> Chester Lin <[email protected]> wrote:
> >
> > On Fri, Aug 20, 2021 at 02:12:13PM +0100, Marc Zyngier wrote:
> > > On Thu, 12 Aug 2021 18:26:28 +0100,
> > > Andreas F?rber <[email protected]> wrote:
> > > >
> > > > Hi Chester et al.,
> > > >
> > > > On 05.08.21 08:54, Chester Lin wrote:
> > > > > Add an initial dtsi file for generic SoC features of NXP S32G2.
> > > > >
> > > > > Signed-off-by: Chester Lin <[email protected]>
> > > > > ---
> > > > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++
> > > > > 1 file changed, 98 insertions(+)
> > > > > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > > > > new file mode 100644
> > > > > index 000000000000..3321819c1a2d
> > > > > --- /dev/null
> > > > > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > >
> > > [...]
> > >
> > > > > + gic: interrupt-controller@50800000 {
> > > > > + compatible = "arm,gic-v3";
> > > > > + #interrupt-cells = <3>;
> > > > > + interrupt-controller;
> > > > > + reg = <0 0x50800000 0 0x10000>,
> > > > > + <0 0x50880000 0 0x200000>,
> > >
> > > That's enough redistributor space for 16 CPUs. However, you only
> > > describe 4. Either the number of CPUs is wrong, the size is wrong, or
> > > the GIC has been configured for more cores than the SoC has.
> >
> > Confirmed the SoC can only find 4 redistributors:
> >
> > localhost:~ # dmesg | grep CPU
> > [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
> > [ 0.000000] Detected VIPT I-cache on CPU0
> > [ 0.000000] CPU features: detected: GIC system register CPU interface
> > [ 0.000000] CPU features: detected: ARM erratum 845719
> > [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> > [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=480 to nr_cpu_ids=4.
> > [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000
> > [ 0.063865] smp: Bringing up secondary CPUs ...
> > [ 0.068852] Detected VIPT I-cache on CPU1
> > [ 0.068894] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000
> > [ 0.068963] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
> > [ 0.069809] Detected VIPT I-cache on CPU2
> > [ 0.069851] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000
> > [ 0.069903] CPU2: Booted secondary processor 0x0000000100 [0x410fd034]
> > [ 0.070698] Detected VIPT I-cache on CPU3
> > [ 0.070722] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000
> > [ 0.070749] CPU3: Booted secondary processor 0x0000000101 [0x410fd034]
> > [ 0.070847] smp: Brought up 1 node, 4 CPUs
> > <..snip..>
>
> That's not the correct way to find out. Each CPU tries to find its
> matching RD in the region. This doesn't mean there aren't more RDs
> present in the GIC.
>
> You need to iterate over all the RDs in the region until you find one
> that has GICR_TYPER.Last == 1. This will give you the actual count.
> Alternatively, you can check whether the RD at 508e0000 has that bit
> set. If it doesn't, then you know there are more RDs than CPUs.
>
> M.
>
Thanks for your guidance. Not sure if any debug log can be enabled for this
check so I temporarily add an ugly message as below:
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index e0f4debe64e1..5998306fff39 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -866,10 +866,11 @@ static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
gic_data_rdist_rd_base() = ptr;
gic_data_rdist()->phys_base = region->phys_base + offset;
- pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
+ pr_info("CPU%d: found redistributor %lx region %d:%pa last: %d\n",
smp_processor_id(), mpidr,
(int)(region - gic_data.redist_regions),
- &gic_data_rdist()->phys_base);
+ &gic_data_rdist()->phys_base,
+ (typer & GICR_TYPER_LAST) ? 1 : 0);
return 0;
}
The following log shows that the "Last" bit (GICR_TYPER[4]) of RD at
508e0000 has been set.
localhost:~ # dmesg | grep GIC
[ 0.000000] CPU features: detected: GIC system register CPU interface
[ 0.000000] GICv3: 544 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[ 0.000000] GICv3: Distributor has no Range Selector support
[ 0.000000] GICv3: 16 PPIs implemented
[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000 last: 0
[ 0.078745] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000 last: 0
[ 0.089598] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000 last: 0
[ 0.100395] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000 last: 1
On Sat, 21 Aug 2021 13:39:04 +0100,
Chester Lin <[email protected]> wrote:
>
> The following log shows that the "Last" bit (GICR_TYPER[4]) of RD at
> 508e0000 has been set.
>
> localhost:~ # dmesg | grep GIC
> [ 0.000000] CPU features: detected: GIC system register CPU interface
> [ 0.000000] GICv3: 544 SPIs implemented
> [ 0.000000] GICv3: 0 Extended SPIs implemented
> [ 0.000000] GICv3: Distributor has no Range Selector support
> [ 0.000000] GICv3: 16 PPIs implemented
> [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000 last: 0
> [ 0.078745] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000 last: 0
> [ 0.089598] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000 last: 0
> [ 0.100395] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000 last: 1
Looks convincing enough. Trimming the RD range to 512kB is then the
right thing to do.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.