On 10/10/18 6:51 AM, Thierry Reding wrote:
> On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote:
> [...]
>> +- interrupts: one interrupt per PWM channel (currently unused in the driver)
>
> This should probably say what the interrupt is used for. And once you
> have that, remove the comment about it being unused in the driver. DT
> is OS agnostic, so "driver" is very unspecific and your claim may
> actually be false.
>
> Thierry
>
As per my understanding, they are generated by hardware but no usage of
pwm interrupts as of now.

I am not sure if removing the entire entry is a good idea.
What would be the best way to represent that information ?

May be this ?

+-interrupts: one interrupt per PWM channel. No usage in HiFive
Unleashed SoC.

Regards,
Atish

2018-10-15 22:58:21

by Atish Patra

[permalink] [raw]

Subject: Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

On 10/10/18 6:49 AM, Thierry Reding wrote:
> On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote:
>> From: "Wesley W. Terpstra" <[email protected]>
>>
>> DT documentation for PWM controller added with updated compatible
>> string.
>>
>> Signed-off-by: Wesley W. Terpstra <[email protected]>
>> [Atish: Compatible string update]
>> Signed-off-by: Atish Patra <[email protected]>
>> ---
>> .../devicetree/bindings/pwm/pwm-sifive.txt | 32 ++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
>> new file mode 100644
>> index 00000000..532b10fc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
>> @@ -0,0 +1,32 @@
>> +SiFive PWM controller
>> +
>> +Unlike most other PWM controllers, the SiFive PWM controller currently only
>> +supports one period for all channels in the PWM. This is set globally in DTS.
>> +The period also has significant restrictions on the values it can achieve,
>> +which the driver rounds to the nearest achievable frequency.
>
> What restrictions are these? If "nearest achievable" is too far off the
> target period it might be preferable to error out.
>

@Wes: Any comments?

>> +Required properties:
>> +- compatible: should be one of
>> + "sifive,fu540-c000-pwm0","sifive,pwm0".
>
> What's the '0' in here? A version number?
>

I think yes. Since fu540 is the first Linux capable RISC-V core, SiFive
Guys decided mark it as version 0.

@Wesly: Please correct me if I am wrong.

>> + PWM controller is HiFive Unleashed specific chip which warrants a
>> + specific compatible string. The second string is kept for backward
>> + compatibility until a firmware update with latest compatible string.
>> +- reg: physical base address and length of the controller's registers
>> +- clocks: The frequency the controller runs at
>> +- #pwm-cells: Should be 2.
>> + The first cell is the PWM channel number
>> + The second cell is the PWM polarity
>> +- sifive,approx-period: the driver will get as close to this period as it can
>
> Given the above comment, maybe "sifive,period"?
>

ok.
In Unleashed board, the DT is loaded by FSBL (first stage boot loader).
Thus, changing device tree entries requires a FSBL update. If we update
this string, we need to update the driver to parse both properties so
that existing devices with older firmware continue to work.

This is probably ok as we anyways do that for compatible strings. Just
wanted to update that here for the record.

Regards,
Atish
> Thierry
>

2018-10-15 23:20:09

by Wesley Terpstra

[permalink] [raw]

Subject: Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

On Mon, Oct 15, 2018 at 3:57 PM Atish Patra <[email protected]> wrote:
> >> +SiFive PWM controller
> >> +
> >> +Unlike most other PWM controllers, the SiFive PWM controller currently only
> >> +supports one period for all channels in the PWM. This is set globally in DTS.
> >> +The period also has significant restrictions on the values it can achieve,
> >> +which the driver rounds to the nearest achievable frequency.
> >
> > What restrictions are these? If "nearest achievable" is too far off the
> > target period it might be preferable to error out.
> >
>
> @Wes: Any comments?

When I last looked at this driver and hardware, I briefly considered
throwing up my hands and pretending that this PWM device had no period
control at all, only duty-cycle. There are several examples of PWM
controllers in linux already that behave that way.

Most of the uses of this PWM are only going to care about the
duty-cycle, not the period. So failing when the period is unachievable
seems worse to me than just completely eliminating access to period
control.

> I think yes. Since fu540 is the first Linux capable RISC-V core, SiFive
> Guys decided mark it as version 0.
>
> @Wesly: Please correct me if I am wrong.

Correct.

2018-10-16 06:26:56

by Atish Patra

[permalink] [raw]

Subject: Re: [RFC 2/4] pwm: sifive: Add a driver for SiFive SoC PWM

On 10/10/18 7:13 AM, Thierry Reding wrote:
> On Tue, Oct 09, 2018 at 11:51:23AM -0700, Atish Patra wrote:
>> From: "Wesley W. Terpstra" <[email protected]>
>>
>> Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC.
>>
>> Signed-off-by: Wesley W. Terpstra <[email protected]>
>> [Atish: Various fixes and code cleanup]
>> Signed-off-by: Atish Patra <[email protected]>
>> ---
>> drivers/pwm/Kconfig | 10 ++
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-sifive.c | 240 +++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 251 insertions(+)
>> create mode 100644 drivers/pwm/pwm-sifive.c
>>
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index 504d2527..dd12144d 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -378,6 +378,16 @@ config PWM_SAMSUNG
>> To compile this driver as a module, choose M here: the module
>> will be called pwm-samsung.
>>
>> +config PWM_SIFIVE
>> + tristate "SiFive PWM support"
>> + depends on OF
>> + depends on COMMON_CLK
>> + help
>> + Generic PWM framework driver for SiFive SoCs.
>> +
>> + To compile this driver as a module, choose M here: the module
>> + will be called pwm-sifive.
>> +
>> config PWM_SPEAR
>> tristate "STMicroelectronics SPEAr PWM support"
>> depends on PLAT_SPEAR
>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>> index 9c676a0d..30089ca6 100644
>> --- a/drivers/pwm/Makefile
>> +++ b/drivers/pwm/Makefile
>> @@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
>> obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
>> obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
>> obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
>> +obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
>> obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
>> obj-$(CONFIG_PWM_STI) += pwm-sti.o
>> obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
>> diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
>> new file mode 100644
>> index 00000000..99580025
>> --- /dev/null
>> +++ b/drivers/pwm/pwm-sifive.c
>> @@ -0,0 +1,240 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2017 SiFive
>> + */
>> +#include <dt-bindings/pwm/pwm.h>
>
> What do you need this for? Your driver should only be dealing with enum
> pwm_polarity, not the defines from the above header. This works but only
> because PWM_POLARITY_INVERTED and PWM_POLARITY_INVERSED happen to be the
> same value.
>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pwm.h>
>> +#include <linux/slab.h>
>> +#include <linux/clk.h>
>> +#include <linux/io.h>
>
> Keep these in alphabetical order, please.
>
>> +
>> +#define MAX_PWM 4
>> +
>> +/* Register offsets */
>> +#define REG_PWMCFG 0x0
>> +#define REG_PWMCOUNT 0x8
>> +#define REG_PWMS 0x10
>> +#define REG_PWMCMP0 0x20
>> +
>> +/* PWMCFG fields */
>> +#define BIT_PWM_SCALE 0
>> +#define BIT_PWM_STICKY 8
>> +#define BIT_PWM_ZERO_ZMP 9
>> +#define BIT_PWM_DEGLITCH 10
>> +#define BIT_PWM_EN_ALWAYS 12
>> +#define BIT_PWM_EN_ONCE 13
>> +#define BIT_PWM0_CENTER 16
>> +#define BIT_PWM0_GANG 24
>> +#define BIT_PWM0_IP 28
>> +
>> +#define SIZE_PWMCMP 4
>> +#define MASK_PWM_SCALE 0xf
>> +
>> +struct sifive_pwm_device {
>> + struct pwm_chip chip;
>> + struct notifier_block notifier;
>> + struct clk *clk;
>> + void __iomem *regs;
>> + unsigned int approx_period;
>> + unsigned int real_period;
>> +};
>
> No need to align these. A single space is enough to separate variable
> type and name.
>
>> +
>> +static inline struct sifive_pwm_device *to_sifive_pwm_chip(struct pwm_chip *c)
>> +{
>> + return container_of(c, struct sifive_pwm_device, chip);
>> +}
>> +
>> +static int sifive_pwm_apply(struct pwm_chip *chip, struct pwm_device *dev,
>> + struct pwm_state *state)
>> +{
>> + struct sifive_pwm_device *pwm = to_sifive_pwm_chip(chip);
>> + unsigned int duty_cycle;
>> + u32 frac;
>> +
>> + duty_cycle = state->duty_cycle;
>> + if (!state->enabled)
>> + duty_cycle = 0;
>> + if (state->polarity == PWM_POLARITY_NORMAL)
>> + duty_cycle = state->period - duty_cycle;
>
> That's not actually polarity inversion. This is "lightweight" inversion
> which should be up to the consumer, not the PWM driver, to implement. If
> you don't actually have a knob in hardware to switch the polarity, don't
> support it.
>

I couldn't find anything about polarity support in the spec. Of course,
I might be complete idiot as well :). I will wait for Wesly's confirmation.

>> +
>> + frac = ((u64)duty_cycle << 16) / state->period;
>> + frac = min(frac, 0xFFFFU);
>> +
>> + iowrite32(frac, pwm->regs + REG_PWMCMP0 + (dev->hwpwm * SIZE_PWMCMP));
>
> writel()?
>

>> +
>> + if (state->enabled) {
>> + state->period = pwm->real_period;
>> + state->duty_cycle = ((u64)frac * pwm->real_period) >> 16;
>> + if (state->polarity == PWM_POLARITY_NORMAL)
>> + state->duty_cycle = state->period - state->duty_cycle;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void sifive_pwm_get_state(struct pwm_chip *chip, struct pwm_device *dev,
>> + struct pwm_state *state)
>> +{
>> + struct sifive_pwm_device *pwm = to_sifive_pwm_chip(chip);
>> + unsigned long duty;
>> +
>> + duty = ioread32(pwm->regs + REG_PWMCMP0 + (dev->hwpwm * SIZE_PWMCMP));
>
> readl()? Maybe also change duty to u32, which is what readl() returns.
>
Sure. I will convert all iowrite/read to readl/writel.

>> +
>> + state->period = pwm->real_period;
>> + state->duty_cycle = ((u64)duty * pwm->real_period) >> 16;
>> + state->polarity = PWM_POLARITY_INVERSED;
>> + state->enabled = duty > 0;
>> +}
>> +
>> +static const struct pwm_ops sifive_pwm_ops = {
>> + .get_state = sifive_pwm_get_state,
>> + .apply = sifive_pwm_apply,
>> + .owner = THIS_MODULE,
>
> Again, no need to artificially align these.
>

Sure. I will fix the other alignment comment as well.

>> +};
>> +
>> +static struct pwm_device *sifive_pwm_xlate(struct pwm_chip *chip,
>> + const struct of_phandle_args *args)
>> +{
>> + struct sifive_pwm_device *pwm = to_sifive_pwm_chip(chip);
>> + struct pwm_device *dev;
>> +
>> + if (args->args[0] >= chip->npwm)
>> + return ERR_PTR(-EINVAL);
>> +
>> + dev = pwm_request_from_chip(chip, args->args[0], NULL);
>> + if (IS_ERR(dev))
>> + return dev;
>> +
>> + /* The period cannot be changed on a per-PWM basis */
>> + dev->args.period = pwm->real_period;
>> + dev->args.polarity = PWM_POLARITY_NORMAL;
>> + if (args->args[1] & PWM_POLARITY_INVERTED)
>> + dev->args.polarity = PWM_POLARITY_INVERSED;
>> +
>> + return dev;
>> +}
>> +
>> +static void sifive_pwm_update_clock(struct sifive_pwm_device *pwm,
>> + unsigned long rate)
>> +{
>> + /* (1 << (16+scale)) * 10^9/rate = real_period */
>> + unsigned long scalePow = (pwm->approx_period * (u64)rate) / 1000000000;
>> + int scale = ilog2(scalePow) - 16;
>> +
>> + scale = clamp(scale, 0, 0xf);
>> + iowrite32((1 << BIT_PWM_EN_ALWAYS) | (scale << BIT_PWM_SCALE),
>> + pwm->regs + REG_PWMCFG);
>> +
>> + pwm->real_period = (1000000000ULL << (16 + scale)) / rate;
>> +}
>> +
>> +static int sifive_pwm_clock_notifier(struct notifier_block *nb,
>> + unsigned long event, void *data)
>> +{
>> + struct clk_notifier_data *ndata = data;
>> + struct sifive_pwm_device *pwm = container_of(nb,
>> + struct sifive_pwm_device,
>> + notifier);
>> +
>> + if (event == POST_RATE_CHANGE)
>> + sifive_pwm_update_clock(pwm, ndata->new_rate);
>> +
>> + return NOTIFY_OK;
>> +}
>
> Does this mean that the PWM source clock can be shared with other IP
> blocks?

PWM clock update is required to be reprogrammed because of single PLL.
It runs at bus clock rate which is half of the PLL rate.
In case of, cpu clock rate change, pwm settings need to be calculated
again to maintain the same rate.

What happens if some other user sets a frequency that we can't
> support? Or what if the clock rate change results in a real period that
> is out of the limits that are considered valid?
>

@Wesley: What should be the expected behavior in these cases ?

>> +static int sifive_pwm_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *node = pdev->dev.of_node;
>> + struct sifive_pwm_device *pwm;
>> + struct pwm_chip *chip;
>> + struct resource *res;
>> + int ret;
>> +
>> + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
>> + if (!pwm)
>> + return -ENOMEM;
>> +
>> + chip = &pwm->chip;
>> + chip->dev = dev;
>> + chip->ops = &sifive_pwm_ops;
>> + chip->of_xlate = sifive_pwm_xlate;
>> + chip->of_pwm_n_cells = 2;
>> + chip->base = -1;
>> +
>> + ret = of_property_read_u32(node, "sifive,npwm", &chip->npwm);
>> + if (ret < 0 || chip->npwm > MAX_PWM)
>> + chip->npwm = MAX_PWM;
>
> This property is not documented. Also, why is it necessary? Do you
> expect the number of PWMs to differ depending on the instance of the IP
> block? I would argue that the number of PWMs can be derived from the
> compatible string, so it's unnecessary here.
>

I think this is left over from old code. Sorry for that.
I will remove it.

> I think you can also remove the MAX_PWM macro, since that's only used in
> one location and it's meaning is very clear in the context, so the
> symbolic name isn't useful.
>

Sure.

>> +
>> + ret = of_property_read_u32(node, "sifive,approx-period",
>> + &pwm->approx_period);
>> + if (ret < 0) {
>> + dev_err(dev, "Unable to read sifive,approx-period from DTS\n");
>> + return -ENOENT;
>> + }
>
> Maybe propagate ret instead of always returning -ENOENT?
>
ok.

>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + pwm->regs = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(pwm->regs)) {
>> + dev_err(dev, "Unable to map IO resources\n");
>> + return PTR_ERR(pwm->regs);
>> + }
>> +
>> + pwm->clk = devm_clk_get(dev, NULL);
>> + if (IS_ERR(pwm->clk)) {
>> + dev_err(dev, "Unable to find controller clock\n");
>> + return PTR_ERR(pwm->clk);
>> + }
>> +
>> + /* Watch for changes to underlying clock frequency */
>> + pwm->notifier.notifier_call = sifive_pwm_clock_notifier;
>> + clk_notifier_register(pwm->clk, &pwm->notifier);
>
> Check for errors from this?
>
>> +
>> + /* Initialize PWM config */
>> + sifive_pwm_update_clock(pwm, clk_get_rate(pwm->clk));
>> +
>> + /* No interrupt handler needed yet */
>
> That's not a useful comment.
>
Will remove it.

>> +
>> + ret = pwmchip_add(chip);
>> + if (ret < 0) {
>> + dev_err(dev, "cannot register PWM: %d\n", ret);
>> + clk_notifier_unregister(pwm->clk, &pwm->notifier);
>
> Might be worth introducing a managed version of clk_notifier_register()
> so that we can avoid having to unregister it.
>

If I understand correctly, it should be defined in clk.c as a
devm_clk_notifier_register. I can add it as as a separate patch and
rebase this patch on top of it.

>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, pwm);
>> + dev_info(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
>
> Remove this, or at least make it dev_dbg(). This is not noteworthy news,
> so no need to bother the user with it.
>

Sure.

>> +
>> + return 0;
>> +}
>> +
>> +static int sifive_pwm_remove(struct platform_device *dev)
>> +{
>> + struct sifive_pwm_device *pwm = platform_get_drvdata(dev);
>> + struct pwm_chip *chip = &pwm->chip;
>
> Not sure that this intermediate variable is useful, might as well use
> &pwm->chip in the one location where you need it.
>

Correct. I will remove it.

>> +
>> + clk_notifier_unregister(pwm->clk, &pwm->notifier);
>> + return pwmchip_remove(chip);
>> +}
>> +
>> +static const struct of_device_id sifive_pwm_of_match[] = {
>> + { .compatible = "sifive,pwm0" },
>> + { .compatible = "sifive,fu540-c000-pwm0" },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, sifive_pwm_of_match);
>> +
>> +static struct platform_driver sifive_pwm_driver = {
>> + .probe = sifive_pwm_probe,
>> + .remove = sifive_pwm_remove,
>> + .driver = {
>> + .name = "pwm-sifivem",
>
> Why does this have the 'm' at the end? I don't see that anywhere else in
> the names.

My bad. It's a typo.

>
>> + .of_match_table = of_match_ptr(sifive_pwm_of_match),
>
> No need for of_match_ptr() here since you depend on OF, so this is
> always going to expand to sifive_pwm_of_match.
>

ok.

Thanks a lot for reviewing the patch.

Regards,
Atish
> Thierry
>

2018-10-16 06:30:39

by Atish Patra

[permalink] [raw]

Subject: Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller.

On 10/16/18 3:04 PM, Thierry Reding wrote:
> On Tue, Oct 16, 2018 at 10:31:42AM -0700, Paul Walmsley wrote:
>> On 10/16/18 4:01 AM, Thierry Reding wrote:
>>> On Mon, Oct 15, 2018 at 03:57:35PM -0700, Atish Patra wrote:
>>>> On 10/10/18 6:49 AM, Thierry Reding wrote:
>>>>> On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote:
>>>>>> +Required properties:
>>>>>> +- compatible: should be one of
>>>>>> + "sifive,fu540-c000-pwm0","sifive,pwm0".
>>>>> What's the '0' in here? A version number?
>>>>>
>>>> I think yes. Since fu540 is the first Linux capable RISC-V core, SiFive Guys
>>>> decided mark it as version 0.
>>>>
>>>> @Wesly: Please correct me if I am wrong.
>>> It seems fairly superfluous to me to have a version number in additon to
>>> the fu540-c000, which already seems to be the core plus some sort of
>>> part number. Do you really expect there to be any changes in the SoC
>>> that would require a different compatible string at this point? If the
>>> SoC has taped out, how will you ever get a different version of the PWM
>>> IP in it?
>>>
>>> I would expect any improvements or changes to the PWM IP to show up in a
>>> different SoC generation, at which point it would be something like
>>> "sifive,fu640-c000" maybe, or perhaps "sifive,fu540-d000", or whatever
>>> the numbering is.
>>
>> The "0" suffix refers to a revision number for the underlying PWM IP block.
>>
>> It's certainly important to keep that version number on the "sifive,pwm0"
>> compatible string that doesn't have the chip name associated with it.
> Isn't the hardware identified by "sifive,pwm0" and "sifive,fu540-c000"
> effectively identical?

The intention was that the "sifive,pwm0" compatible string specifies a
register interface and programming model that the IP block exposes to
the software, rather than a particular underlying hardware
implementation. That is in contrast to a string like
"sifive,fu540-c000-pwm" which might activate particular workarounds or
quirks that are specific to the integration of the IP block on a given SoC.

The idea is that, for this and similar open-source hardware IP blocks,
the driver code can just match on a generic "sifive,pwm0" compatible
string. The SoC DT data would include both the SoC-specific
"sifive,fu540-c000-pwm0" and the common interface "sifive,pwm0". But
the driver would only need the SoC-specific compatible string if the SoC
wound up needing some SoC-specific quirks.

In the past, some folks have had a problem with that idea, since for
closed-source IP blocks, it's been difficult to determine what changes
went into a specific version of the IP block. Thus folks generating
data for later SoCs usually specify a compatible string for another,
older, SoC that seems to have the desired behavior. But since this
particular IP block has open-source RTL, and contains a "sifive,pwmX"
version string in the RTL itself:

https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pwm/PWM.scala#L74

... it's straightforward to see what interface the hardware exposes to
the software for a given compatible string.

> Is there a need to have two compatible strings
> that refer to the exact same hardware?

There's no intention that "sifive,pwm0" and "sifive,fu540-c000-pwm0"
refer to the same hardware; just the same software interface and
programming model. Even now, it's usually pretty unlikely that two
different SoCs that refer to (say) "nvidia,tegra20-pwm" contain the same
hardware, since differences in synthesis, place and route, ECOs, and
integration change the actual realization of the hardware. Some folks
interpreted that compatible string reuse as implying the same "hardware"
is in use on both SoCs, but we're really just identifying a software
interface.

>> As to whether there could ever be a FU540-C000 part with different IP block
>> versions on it: FU540-C000 is ultimately a marketing name. While
>> theoretically we shouldn't have another "FU540-C000" chip with different
>> peripheral IP block versions on it, I don't think any engineer can guarantee
>> that it won't happen.
> I would argue that if at some point there was indeed a chip with the
> same name but a different IP block version in it, we can figure out what
> to call it. Sure there are no guarantees, but it's still fairly unlikely
> in my opinion, so I personally wouldn't worry about this up front.
>
> Anyway, I don't feel strongly either way, I'm just pointing out that
> this is somewhat unusual. If you want to keep it, feel free to.

Thanks for the review, Thierry -

- Paul

2019-09-18 11:50:43

by Bin Meng

[permalink] [raw]

Subject: Re: [RFC 4/4] gpio: sifive: Add GPIO driver for SiFive SoCs

Hi,

On Wed, Oct 17, 2018 at 9:01 AM Atish Patra <[email protected]> wrote:
>
> On 10/10/18 5:35 AM, Linus Walleij wrote:
> > Hi Atish,
> >
> > thanks for your patch!
> >
> > On Tue, Oct 9, 2018 at 8:51 PM Atish Patra <[email protected]> wrote:
> >
> >> From: "Wesley W. Terpstra" <[email protected]>
> >>
> >> Adds the GPIO driver for SiFive RISC-V SoCs.
> >>
> >> Signed-off-by: Wesley W. Terpstra <[email protected]>
> >> [Atish: Various fixes and code cleanup]
> >> Signed-off-by: Atish Patra <[email protected]>
> >
> > (...)
> >
> >> +config GPIO_SIFIVE
> >> + bool "SiFive GPIO support"
> >> + depends on OF_GPIO
> >> + select GPIOLIB_IRQCHIP
> >
> > I suggest to add
> > select GPIO_GENERIC as per below.
> >
> > Maybe select REGMAP_MMIO as well.
>
> ok.
>
> >
> >> + help
> >> + Say yes here to support the GPIO device on SiFive SoCs.
> >> +
> >
> >> +#include <linux/of_irq.h>
> >> +#include <linux/irqchip/chained_irq.h>
> >
> > Do you need these two? I think <linux/gpio/driver.h>
> > will bring them in for you.
> >
>
> driver.h only brings chained_irq.h. of_irq.h is still required. Right ?
>
> >> +#include <linux/pinctrl/consumer.h>
> >
> > Are you using this?
>
> My bad. Left over from the old code. I will remove it.
>
> >
> >> +struct sifive_gpio {
> >> + raw_spinlock_t lock;
> >> + void __iomem *base;
> >> + struct gpio_chip gc;
> >> + unsigned long enabled;
> >
> > Since max GPIO is 32 why not use an u32 for this?
> >
>
> Sure.
>
> >> + unsigned int trigger[MAX_GPIO];
> >> + unsigned int irq_parent[MAX_GPIO];
> >> + struct sifive_gpio *self_ptr[MAX_GPIO];
> >> +};
> >> +
> >> +static void sifive_assign_bit(void __iomem *ptr, unsigned int offset, int value)
> >> +{
> >> + /*
> >> + * It's frustrating that we are not allowed to use the device atomics
> >> + * which are GUARANTEED to be supported by this device on RISC-V
> >> + */
> >> + u32 bit = BIT(offset), old = ioread32(ptr);
> >> +
> >> + if (value)
> >> + iowrite32(old | bit, ptr);
> >> + else
> >> + iowrite32(old & ~bit, ptr);
> >> +}
> >
> > This looks like a mask and set implementation, you are
> > essentially reinventing regmap MMIO and the
> > regmap_update_bits() call. Could you look into
> > just using regmap MMIO in that case?
> >
> > If you need examples, look at gpio-mvebu.c that calls
> > devm_regmap_init_mmio() for example.
> >
>
> That's really cool. Sorry, for not checking that earlier.
> I am pretty new to this.
>
> >> +static int sifive_direction_input(struct gpio_chip *gc, unsigned int offset)
> >> +static int sifive_direction_output(struct gpio_chip *gc, unsigned int offset,
> >> +static int sifive_get_direction(struct gpio_chip *gc, unsigned int offset)
> >> +static int sifive_get_value(struct gpio_chip *gc, unsigned int offset)
> >> +static void sifive_set_value(struct gpio_chip *gc, unsigned int offset,
> >
> > These functions look like a typical hardware that can use
> >
> > GPIOLIB_GENERIC and bgpio_init() to set up the accessors.
> >
> > See gpio-ftgpio010.c for an example.
> >
> > As a bonus you will get .get/.set_multiple implemented by
> > the generic GPIO.
> >
>
> Great. This will reduce the driver a code by a big factor.
> Thanks for the pointer.
>
>
> >> +static void sifive_irq_enable(struct irq_data *d)
> >> +static void sifive_irq_disable(struct irq_data *d)
> > (...)
> >> +static struct irq_chip sifive_irqchip = {
> >> + .name = "sifive-gpio",
> >> + .irq_set_type = sifive_irq_set_type,
> >> + .irq_mask = sifive_irq_mask,
> >> + .irq_unmask = sifive_irq_unmask,
> >> + .irq_enable = sifive_irq_enable,
> >> + .irq_disable = sifive_irq_disable,
> >
> > The handling of .irq_enable and .irq_disable has
> > changed upstream. Please align with the new codebase
> > as changed by Hans Verkuil:
> >
> > commit 461c1a7d4733d1dfd5c47b040cf32a5e7eefbc6c
> > "gpiolib: override irq_enable/disable"
> > commit 4e9439ddacea06f35acce4d374bf6bd0acf99bc8
> > "gpiolib: add flag to indicate if the irq is disabled"
> >
> > You will need to rebase your work on the v4.20-rc1 once it is
> > out. Right now the changes are on linux-next or my devel
> > branch.
>
> Will do.
>
> >
> >> + ngpio = of_irq_count(node);
> >> + if (ngpio >= MAX_GPIO) {
> >> + dev_err(dev, "Too many GPIO interrupts (max=%d)\n", MAX_GPIO);
> >> + return -ENXIO;
> >> + }
> > (...)
> >> + for (gpio = 0; gpio < ngpio; ++gpio) {
> >> + irq = platform_get_irq(pdev, gpio);
> >> + if (irq < 0) {
> >> + dev_err(dev, "invalid IRQ\n");
> >> + gpiochip_remove(&chip->gc);
> >> + return -ENODEV;
> >> + }
> >
> > This is an hierarchical IRQ so it should use an hierarchical
> > irqdomain.
> >
> > I am discussing with Thierry to make more generic irq domains
> > for hierarchical IRQ GPIOs, until then you have to look at
> > gpio-thunderx.c, gpio-uniphier.c or gpio-xgene-sb.c that all
> > use hierarchical IRQs.
> >
>
> Thanks. I will convert them to hierarchical IRQ.
>

When will this series get respun and upstreamed?

Regards,
Bin