LinuxLists.cc - [PATCH v2 00/12] riscv: Allwinner D1/D1s platform support

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Subject: [PATCH v2 06/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

"D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
plus low-speed I/O from the SoC and a GPIO expander chip.

Reviewed-by: Heiko Stuebner <[email protected]>
Tested-by: Conor Dooley <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---

Changes in v2:
- Common regulators moved to MangoPi MQ patch, removed analog LDOs
- Removed LRADC (depends on analog LDOs)
- Added XR829 host-wake interrupt

arch/riscv/boot/dts/allwinner/Makefile | 1 +
.../boot/dts/allwinner/sun20i-d1-nezha.dts | 167 ++++++++++++++++++
2 files changed, 168 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index 2f2792594f7d..277e59d1c907 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
new file mode 100644
index 000000000000..9ea3648e64ea
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/dts-v1/;
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-common-regulators.dtsi"
+
+/ {
+ model = "Allwinner D1 Nezha";
+ compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &xr829;
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_usbvbus: usbvbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbvbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
+ enable-active-high;
+ vin-supply = <&reg_vcc>;
+ };
+
+ /*
+ * This regulator is PWM-controlled, but the PWM controller is not
+ * yet supported, so fix the regulator to its default voltage.
+ */
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&reg_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-0 = <&rgmii_pe_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&reg_vcc_3v3>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pb0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcf8574a: gpio@38 {
+ compatible = "nxp,pcf8574a";
+ reg = <0x38>;
+ interrupt-parent = <&pio>;
+ interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
+ interrupt-controller;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ xr829: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* XR829 bluetooth is connected here */
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ usb0_vbus-supply = <&reg_usbvbus>;
+ usb1_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
--
2.37.4

2022-11-25 23:51:32

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Subject: [PATCH v2 11/12] riscv: Add the Allwinner SoC family Kconfig option

Allwinner manufactures the sunxi family of application processors. This
includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.

The first SoC in the sun20i series is D1, containing a single T-HEAD
C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.

Most peripherals are shared across the entire chip family. In fact, the
ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
with the D1s.

This means many existing device drivers can be reused. To facilitate
this reuse, name the symbol ARCH_SUNXI, since that is what the existing
drivers have as their dependency.

Reviewed-by: Heiko Stuebner <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---

Changes in v2:
- Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing

arch/riscv/Kconfig.socs | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..4c1dc2ca11f9 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -26,6 +26,15 @@ config SOC_STARFIVE
help
This enables support for StarFive SoC platform hardware.

+config ARCH_SUNXI
+ bool "Allwinner sun20i SoCs"
+ select ERRATA_THEAD if MMU && !XIP_KERNEL
+ select SIFIVE_PLIC
+ select SUN4I_TIMER
+ help
+ This enables support for Allwinner sun20i platform hardware,
+ including boards based on the D1 and D1s SoCs.
+
config SOC_VIRT
bool "QEMU Virt Machine"
select CLINT_TIMER if RISCV_M_MODE
--
2.37.4

2022-11-26 00:12:03

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Subject: [PATCH v2 10/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees

Clockwork Tech manufactures several SoMs for their RasPi CM3-compatible
"ClockworkPi" mainboard. Their R-01 SoM features the Allwinner D1 SoC.
The R-01 contains only the CPU, DRAM, and always-on voltage regulation;
it does not merit a separate devicetree.

The ClockworkPi mainboard features analog audio, a MIPI-DSI panel, USB
host and peripheral ports, an Ampak AP6256 WiFi/Bluetooth module, and an
X-Powers AXP228 PMIC for managing a Li-ion battery.

The DevTerm is a complete system which extends the ClockworkPi mainboard
with a MIPI-DSI panel and a pair of expansion boards. These expansion
boards provide a fan, a USB keyboard, speakers, and a thermal printer.

Signed-off-by: Samuel Holland <[email protected]>
---

Changes in v2:
- Added PMIC GPIO controller node (binding merged for 6.2)

arch/riscv/boot/dts/allwinner/Makefile | 2 +
.../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 253 ++++++++++++++++++
.../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 36 +++
3 files changed, 291 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index 87f70b1af6b4..1c91be38ea16 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -1,4 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
new file mode 100644
index 000000000000..4289e724f948
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-common-regulators.dtsi"
+
+/ {
+ model = "ClockworkPi v3.14 (R-01)";
+ compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &ap6256;
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /*
+ * This regulator is PWM-controlled, but the PWM controller is not
+ * yet supported, so fix the regulator to its default voltage.
+ */
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&reg_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pb10_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ axp221: pmic@34 {
+ compatible = "x-powers,axp228", "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&pio>;
+ interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ ac_power_supply: ac-power {
+ compatible = "x-powers,axp221-ac-power-supply";
+ };
+
+ axp_adc: adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+
+ battery_power_supply: battery-power {
+ compatible = "x-powers,axp221-battery-power-supply";
+ };
+
+ axp_gpio: gpio {
+ compatible = "x-powers,axp221-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ regulators {
+ x-powers,dcdc-freq = <3000>;
+
+ reg_dcdc1: dcdc1 {
+ regulator-name = "sys-3v3";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = "sys-1v8";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_aldo1: aldo1 {
+ regulator-name = "aud-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-name = "disp-3v3";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-name = "vdd-wifi";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ /* DLDO1 and ELDO1-3 are connected in parallel. */
+ reg_dldo1: dldo1 {
+ regulator-name = "vbat-wifi-a";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* DLDO2-DLDO4 are connected in parallel. */
+ reg_dldo2: dldo2 {
+ regulator-name = "vcc-3v3-ext-a";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dldo3: dldo3 {
+ regulator-name = "vcc-3v3-ext-b";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dldo4: dldo4 {
+ regulator-name = "vcc-3v3-ext-c";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo1: eldo1 {
+ regulator-name = "vbat-wifi-b";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo2: eldo2 {
+ regulator-name = "vbat-wifi-c";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo3: eldo3 {
+ regulator-name = "vbat-wifi-d";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ usb_power_supply: usb-power {
+ compatible = "x-powers,axp221-usb-power-supply";
+ status = "disabled";
+ };
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <&reg_dcdc1>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_dldo1>;
+ vqmmc-supply = <&reg_aldo3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ap6256: wifi@1 {
+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pg-supply = <&reg_ldoa>;
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ interrupt-parent = <&pio>;
+ interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
+ device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
+ shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
+ max-speed = <1500000>;
+ vbat-supply = <&reg_dldo1>;
+ vddio-supply = <&reg_aldo3>;
+ };
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus_power-supply = <&ac_power_supply>;
+ usb1_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
new file mode 100644
index 000000000000..bc5c84f22762
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include "sun20i-d1-clockworkpi-v3.14.dts"
+
+/ {
+ model = "Clockwork DevTerm (R-01)";
+ compatible = "clockwork,r-01-devterm-v3.14",
+ "clockwork,r-01-clockworkpi-v3.14",
+ "allwinner,sun20i-d1";
+
+ fan {
+ compatible = "gpio-fan";
+ gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
+ gpio-fan,speed-map = <0 0>,
+ <6000 1>;
+ #cooling-cells = <2>;
+ };
+
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
+ scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@54 {
+ compatible = "ti,adc101c";
+ reg = <0x54>;
+ interrupt-parent = <&pio>;
+ interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
+ vref-supply = <&reg_dldo2>;
+ #io-channel-cells = <1>;
+ };
+ };
+};
--
2.37.4

2022-11-26 00:14:13

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Subject: [PATCH v2 08/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree

The MangoPi MQ Pro is a tiny SBC with a layout compatible to the
Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3,
and an RTL8723DS-based WiFi/Bluetooth module.

The board also exposes GPIO Port E via a connector on the end of the
board, which can support either a camera or an RMII Ethernet PHY. The
additional regulators supply that connector.

Signed-off-by: Samuel Holland <[email protected]>
---

Changes in v2:
- Added LED (GPIO shared between onboard LED and backlight regulator)

arch/riscv/boot/dts/allwinner/Makefile | 1 +
.../allwinner/sun20i-d1-mangopi-mq-pro.dts | 143 ++++++++++++++++++
2 files changed, 144 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index f1c70b9dc9bf..2ed586fafaea 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
new file mode 100644
index 000000000000..6d5897dc22e2
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/dts-v1/;
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-common-regulators.dtsi"
+
+/ {
+ model = "MangoPi MQ Pro";
+ compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &rtl8723ds;
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_BACKLIGHT;
+ gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
+ };
+ };
+
+ reg_avdd2v8: avdd2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <&reg_vcc_3v3>;
+ };
+
+ reg_dvdd: dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&reg_vcc_3v3>;
+ };
+
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&reg_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rtl8723ds: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pe-supply = <&reg_avdd2v8>;
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723ds-bt";
+ device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
+ enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
+ host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
+ };
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
--
2.37.4

2022-11-26 00:19:54

[permalink] [raw]

Subject: [PATCH v2 09/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree

The 100ask Dongshan Nezha STU is a system-on-module that can be used
standalone or with a carrier board. The SoM provides gigabit Ethernet,
HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.

The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
headers, but contains no digital circuitry, so it does not have its own
devicetree.

Signed-off-by: Samuel Holland <[email protected]>
---

(no changes since v1)

arch/riscv/boot/dts/allwinner/Makefile | 1 +
.../sun20i-d1-dongshan-nezha-stu.dts | 118 ++++++++++++++++++
2 files changed, 119 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index 2ed586fafaea..87f70b1af6b4 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
new file mode 100644
index 000000000000..c549a1c5fbf0
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/dts-v1/;
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-common-regulators.dtsi"
+
+/ {
+ model = "Dongshan Nezha STU";
+ compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &emac;
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
+ };
+ };
+
+ reg_usbvbus: usbvbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbvbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
+ enable-active-high;
+ vin-supply = <&reg_vcc>;
+ };
+
+ /*
+ * This regulator is PWM-controlled, but the PWM controller is not
+ * yet supported, so fix the regulator to its default voltage.
+ */
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&reg_vcc>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-0 = <&rgmii_pe_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&reg_vcc_3v3>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ usb0_vbus-supply = <&reg_usbvbus>;
+ status = "okay";
+};
--
2.37.4

2022-11-26 00:20:21

[permalink] [raw]

Subject: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
on a single die, or at a pair of dies derived from the same design.

D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
variants.

Because the original design supported both ARM and RISC-V CPUs, some
peripherals are duplicated. In addition, all variants except D1s contain
a HiFi 4 DSP with its own set of peripherals.

The devicetrees are organized to minimize duplication:
- Common perhiperals are described in sunxi-d1s-t113.dtsi
- DSP-related peripherals are described in sunxi-d1-t113.dtsi
- RISC-V specific hardware is described in sun20i-d1s.dtsi
- Functionality unique to the D1 variant is described in sun20i-d1.dtsi

The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.

Signed-off-by: Samuel Holland <[email protected]>
---

Changes in v2:
- Split into separate files for sharing with D1s/R528/T113
- Use SOC_PERIPHERAL_IRQ macro for interrupts
- Rename osc24M to dcxo and move the frequency to the board DTs
- Drop analog LDOs due to the missing binding
- Correct tcon_top DSI clock reference
- Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
- Add CPU OPP table

arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++
.../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 +
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 844 ++++++++++++++++++
4 files changed, 1001 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
new file mode 100644
index 000000000000..97e7cbb32597
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+#include "sun20i-d1s.dtsi"
+#include "sunxi-d1-t113.dtsi"
+
+/ {
+ soc {
+ lradc: keys@2009800 {
+ compatible = "allwinner,sun20i-d1-lradc",
+ "allwinner,sun50i-r329-lradc";
+ reg = <0x2009800 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(61) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LRADC>;
+ resets = <&ccu RST_BUS_LRADC>;
+ status = "disabled";
+ };
+
+ i2s0: i2s@2032000 {
+ compatible = "allwinner,sun20i-d1-i2s",
+ "allwinner,sun50i-r329-i2s";
+ reg = <0x2032000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(26) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>,
+ <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S0>;
+ dmas = <&dma 3>, <&dma 3>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+ };
+};
+
+&pio {
+ /omit-if-no-ref/
+ dmic_pb11_d0_pin: dmic-pb11-d0-pin {
+ pins = "PB11";
+ function = "dmic";
+ };
+
+ /omit-if-no-ref/
+ dmic_pe17_clk_pin: dmic-pe17-clk-pin {
+ pins = "PE17";
+ function = "dmic";
+ };
+
+ /omit-if-no-ref/
+ i2c0_pb10_pins: i2c0-pb10-pins {
+ pins = "PB10", "PB11";
+ function = "i2c0";
+ };
+
+ /omit-if-no-ref/
+ i2c2_pb0_pins: i2c2-pb0-pins {
+ pins = "PB0", "PB1";
+ function = "i2c2";
+ };
+
+ /omit-if-no-ref/
+ uart0_pb8_pins: uart0-pb8-pins {
+ pins = "PB8", "PB9";
+ function = "uart0";
+ };
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
new file mode 100644
index 000000000000..859509832d58
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
+
+#include "sunxi-d1s-t113.dtsi"
+
+/ {
+ cpus {
+ timebase-frequency = <24000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&ccu CLK_RISCV>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ operating-points-v2 = <&opp_table_cpu>;
+ riscv,isa = "rv64imafdc";
+ #cooling-cells = <2>;
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ opp_table_cpu: opp-table-cpu {
+ compatible = "operating-points-v2";
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ };
+
+ opp-1080000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ };
+ };
+
+ soc {
+ interrupt-parent = <&plic>;
+
+ riscv_wdt: watchdog@6011000 {
+ compatible = "allwinner,sun20i-d1-wdt";
+ reg = <0x6011000 0x20>;
+ interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ };
+
+ plic: interrupt-controller@10000000 {
+ compatible = "allwinner,sun20i-d1-plic",
+ "thead,c900-plic";
+ reg = <0x10000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu0_intc 9>;
+ interrupt-controller;
+ riscv,ndev = <176>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
new file mode 100644
index 000000000000..b7156123df54
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+/ {
+ soc {
+ dsp_wdt: watchdog@1700400 {
+ compatible = "allwinner,sun20i-d1-wdt";
+ reg = <0x1700400 0x20>;
+ interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ status = "reserved";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
new file mode 100644
index 000000000000..c8815cbf0b46
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -0,0 +1,844 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
+#include <dt-bindings/clock/sun20i-d1-ccu.h>
+#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun20i-d1-ccu.h>
+#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dcxo: dcxo-clk {
+ compatible = "fixed-clock";
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ clock-output-names = "dcxo";
+ #clock-cells = <0>;
+ };
+
+ de: display-engine {
+ compatible = "allwinner,sun20i-d1-display-engine";
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
+ status = "disabled";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ dma-noncoherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pio: pinctrl@2000000 {
+ compatible = "allwinner,sun20i-d1-pinctrl";
+ reg = <0x2000000 0x800>;
+ interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB0>,
+ <&dcxo>,
+ <&rtc CLK_OSC32K>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ interrupt-controller;
+ #gpio-cells = <3>;
+ #interrupt-cells = <3>;
+
+ /omit-if-no-ref/
+ clk_pg11_pin: clk-pg11-pin {
+ pins = "PG11";
+ function = "clk";
+ };
+
+ /omit-if-no-ref/
+ dsi_4lane_pins: dsi-4lane-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+ "PD6", "PD7", "PD8", "PD9";
+ drive-strength = <30>;
+ function = "dsi";
+ };
+
+ /omit-if-no-ref/
+ lcd_rgb666_pins: lcd-rgb666-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
+ "PD18", "PD19", "PD20", "PD21";
+ function = "lcd0";
+ };
+
+ /omit-if-no-ref/
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ function = "mmc0";
+ };
+
+ /omit-if-no-ref/
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+ function = "mmc1";
+ };
+
+ /omit-if-no-ref/
+ mmc2_pins: mmc2-pins {
+ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+ function = "mmc2";
+ };
+
+ /omit-if-no-ref/
+ rgmii_pe_pins: rgmii-pe-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9",
+ "PE11", "PE12", "PE13", "PE14", "PE15";
+ function = "emac";
+ };
+
+ /omit-if-no-ref/
+ rmii_pe_pins: rmii-pe-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9";
+ function = "emac";
+ };
+
+ /omit-if-no-ref/
+ uart1_pg6_pins: uart1-pg6-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart3_pb_pins: uart3-pb-pins {
+ pins = "PB6", "PB7";
+ function = "uart3";
+ };
+ };
+
+ ccu: clock-controller@2001000 {
+ compatible = "allwinner,sun20i-d1-ccu";
+ reg = <0x2001000 0x1000>;
+ clocks = <&dcxo>,
+ <&rtc CLK_OSC32K>,
+ <&rtc CLK_IOSC>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ dmic: dmic@2031000 {
+ compatible = "allwinner,sun20i-d1-dmic",
+ "allwinner,sun50i-h6-dmic";
+ reg = <0x2031000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMIC>,
+ <&ccu CLK_DMIC>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_DMIC>;
+ dmas = <&dma 8>;
+ dma-names = "rx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ i2s1: i2s@2033000 {
+ compatible = "allwinner,sun20i-d1-i2s",
+ "allwinner,sun50i-r329-i2s";
+ reg = <0x2033000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S1>,
+ <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S1>;
+ dmas = <&dma 4>, <&dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ i2s2: i2s@2034000 {
+ compatible = "allwinner,sun20i-d1-i2s",
+ "allwinner,sun50i-r329-i2s";
+ reg = <0x2034000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>,
+ <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dmas = <&dma 5>, <&dma 5>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ timer: timer@2050000 {
+ compatible = "allwinner,sun20i-d1-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x2050000 0xa0>;
+ interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcxo>;
+ };
+
+ wdt: watchdog@20500a0 {
+ compatible = "allwinner,sun20i-d1-wdt-reset",
+ "allwinner,sun20i-d1-wdt";
+ reg = <0x20500a0 0x20>;
+ interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ status = "reserved";
+ };
+
+ uart0: serial@2500000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500000 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ dmas = <&dma 14>, <&dma 14>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@2500400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500400 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@2500800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500800 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ dmas = <&dma 16>, <&dma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@2500c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500c00 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ dmas = <&dma 17>, <&dma 17>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@2501000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2501000 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ dmas = <&dma 18>, <&dma 18>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@2501400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2501400 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
+ dmas = <&dma 19>, <&dma 19>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c0: i2c@2502000 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ dmas = <&dma 43>, <&dma 43>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@2502400 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502400 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ dmas = <&dma 44>, <&dma 44>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@2502800 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502800 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ dmas = <&dma 45>, <&dma 45>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@2502c00 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502c00 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ dmas = <&dma 46>, <&dma 46>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ syscon: syscon@3000000 {
+ compatible = "allwinner,sun20i-d1-system-control";
+ reg = <0x3000000 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ regulators@3000150 {
+ compatible = "allwinner,sun20i-d1-system-ldos";
+ reg = <0x3000150 0x4>;
+
+ reg_ldoa: ldoa {
+ };
+
+ reg_ldob: ldob {
+ };
+ };
+ };
+
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun20i-d1-dma";
+ reg = <0x3002000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ resets = <&ccu RST_BUS_DMA>;
+ dma-channels = <16>;
+ dma-requests = <48>;
+ #dma-cells = <1>;
+ };
+
+ sid: efuse@3006000 {
+ compatible = "allwinner,sun20i-d1-sid";
+ reg = <0x3006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ mbus: dram-controller@3102000 {
+ compatible = "allwinner,sun20i-d1-mbus";
+ reg = <0x3102000 0x1000>,
+ <0x3103000 0x1000>;
+ reg-names = "mbus", "dram";
+ interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_MBUS>,
+ <&ccu CLK_DRAM>,
+ <&ccu CLK_BUS_DRAM>;
+ clock-names = "mbus", "dram", "bus";
+ dma-ranges = <0 0x40000000 0x80000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interconnect-cells = <1>;
+ };
+
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun20i-d1-mmc";
+ reg = <0x4020000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ cap-sd-highspeed;
+ max-frequency = <150000000>;
+ no-mmc;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun20i-d1-mmc";
+ reg = <0x4021000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ cap-sd-highspeed;
+ max-frequency = <150000000>;
+ no-mmc;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun20i-d1-emmc",
+ "allwinner,sun50i-a100-emmc";
+ reg = <0x4022000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-ddr-1_8v;
+ mmc-ddr-3_3v;
+ no-sd;
+ no-sdio;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb_otg: usb@4100000 {
+ compatible = "allwinner,sun20i-d1-musb",
+ "allwinner,sun8i-a33-musb";
+ reg = <0x4100000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ extcon = <&usbphy 0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: phy@4100400 {
+ compatible = "allwinner,sun20i-d1-usb-phy";
+ reg = <0x4100400 0x100>,
+ <0x4101800 0x100>,
+ <0x4200800 0x100>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1";
+ clocks = <&dcxo>,
+ <&dcxo>;
+ clock-names = "usb0_phy",
+ "usb1_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>;
+ reset-names = "usb0_reset",
+ "usb1_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@4101000 {
+ compatible = "allwinner,sun20i-d1-ehci",
+ "generic-ehci";
+ reg = <0x4101000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@4101400 {
+ compatible = "allwinner,sun20i-d1-ohci",
+ "generic-ohci";
+ reg = <0x4101400 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@4200000 {
+ compatible = "allwinner,sun20i-d1-ehci",
+ "generic-ehci";
+ reg = <0x4200000 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@4200400 {
+ compatible = "allwinner,sun20i-d1-ohci",
+ "generic-ohci";
+ reg = <0x4200400 0x100>;
+ interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ emac: ethernet@4500000 {
+ compatible = "allwinner,sun20i-d1-emac",
+ "allwinner,sun50i-a64-emac";
+ reg = <0x4500000 0x10000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ syscon = <&syscon>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ display_clocks: clock-controller@5000000 {
+ compatible = "allwinner,sun20i-d1-de2-clk",
+ "allwinner,sun50i-h5-de2-clk";
+ reg = <0x5000000 0x10000>;
+ clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@5100000 {
+ compatible = "allwinner,sun20i-d1-de2-mixer-0";
+ reg = <0x5100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus", "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@5200000 {
+ compatible = "allwinner,sun20i-d1-de2-mixer-1";
+ reg = <0x5200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus", "mod";
+ resets = <&display_clocks RST_MIXER1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+
+ mixer1_out_tcon_top_mixer1: endpoint {
+ remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+ };
+ };
+ };
+ };
+
+ dsi: dsi@5450000 {
+ compatible = "allwinner,sun20i-d1-mipi-dsi",
+ "allwinner,sun50i-a100-mipi-dsi";
+ reg = <0x5450000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&tcon_top CLK_TCON_TOP_DSI>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port {
+ dsi_in_tcon_lcd0: endpoint {
+ remote-endpoint = <&tcon_lcd0_out_dsi>;
+ };
+ };
+ };
+
+ dphy: phy@5451000 {
+ compatible = "allwinner,sun20i-d1-mipi-dphy",
+ "allwinner,sun50i-a100-mipi-dphy";
+ reg = <0x5451000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&ccu CLK_MIPI_DSI>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ #phy-cells = <0>;
+ };
+
+ tcon_top: tcon-top@5460000 {
+ compatible = "allwinner,sun20i-d1-tcon-top";
+ reg = <0x5460000 0x1000>;
+ clocks = <&ccu CLK_BUS_DPSS_TOP>,
+ <&ccu CLK_TCON_TV>,
+ <&ccu CLK_TVE>,
+ <&ccu CLK_TCON_LCD0>;
+ clock-names = "bus", "tcon-tv0", "tve0", "dsi";
+ clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
+ resets = <&ccu RST_BUS_DPSS_TOP>;
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer0_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+ };
+
+ tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer1_in: port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer1_in_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
+ };
+ };
+
+ tcon_top_mixer1_out: port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
+ };
+
+ tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+ };
+ };
+
+ tcon_top_hdmi_in: port@4 {
+ reg = <4>;
+
+ tcon_top_hdmi_in_tcon_tv0: endpoint {
+ remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
+ };
+ };
+
+ tcon_top_hdmi_out: port@5 {
+ reg = <5>;
+ };
+ };
+ };
+
+ tcon_lcd0: lcd-controller@5461000 {
+ compatible = "allwinner,sun20i-d1-tcon-lcd";
+ reg = <0x5461000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_LCD0>,
+ <&ccu CLK_TCON_LCD0>;
+ clock-names = "ahb", "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON_LCD0>,
+ <&ccu RST_BUS_LVDS0>;
+ reset-names = "lcd", "lvds";
+ #clock-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_lcd0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+ };
+
+ tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
+ };
+ };
+
+ tcon_lcd0_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_lcd0_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_tcon_lcd0>;
+ };
+ };
+ };
+ };
+
+ tcon_tv0: lcd-controller@5470000 {
+ compatible = "allwinner,sun20i-d1-tcon-tv";
+ reg = <0x5470000 0x1000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV>,
+ <&tcon_top CLK_TCON_TOP_TV0>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+ };
+
+ tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+ };
+ };
+
+ tcon_tv0_out: port@1 {
+ reg = <1>;
+
+ tcon_tv0_out_tcon_top_hdmi: endpoint {
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+ };
+ };
+ };
+ };
+
+ r_ccu: clock-controller@7010000 {
+ compatible = "allwinner,sun20i-d1-r-ccu";
+ reg = <0x7010000 0x400>;
+ clocks = <&dcxo>,
+ <&rtc CLK_OSC32K>,
+ <&rtc CLK_IOSC>,
+ <&ccu CLK_PLL_PERIPH0_DIV3>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ rtc: rtc@7090000 {
+ compatible = "allwinner,sun20i-d1-rtc",
+ "allwinner,sun50i-r329-rtc";
+ reg = <0x7090000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_BUS_R_RTC>,
+ <&dcxo>,
+ <&r_ccu CLK_R_AHB>;
+ clock-names = "bus", "hosc", "ahb";
+ #clock-cells = <1>;
+ };
+ };
+};
--
2.37.4

2022-11-26 00:21:04

[permalink] [raw]

Subject: [PATCH v2 02/12] dt-bindings: vendor-prefixes: Add Allwinner D1/D1s board vendors

Some boards using the Allwinner D1 or D1s SoC are made by vendors not
previously documented.

Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the
ClockworkPi and DevTerm boards.

Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures
the MangoPi family of boards.

Acked-by: Rob Herring <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---

(no changes since v1)

Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 592e43911a07..f2c67b7418e4 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -262,6 +262,8 @@ patternProperties:
description: Cirrus Logic, Inc.
"^cisco,.*":
description: Cisco Systems, Inc.
+ "^clockwork,.*":
+ description: Clockwork Tech LLC
"^cloudengines,.*":
description: Cloud Engines, Inc.
"^cnm,.*":
@@ -1430,6 +1432,8 @@ patternProperties:
description: Shenzhen whwave Electronics, Inc.
"^wi2wi,.*":
description: Wi2Wi, Inc.
+ "^widora,.*":
+ description: Beijing Widora Technology Co., Ltd.
"^wiligear,.*":
description: Wiligear, Ltd.
"^willsemi,.*":
--
2.37.4

2022-11-26 00:21:08

[permalink] [raw]

Subject: [PATCH v2 05/12] riscv: dts: allwinner: Add MangoPi MQ devicetree

The MangoPi MQ is a tiny SBC built around the Allwinner D1s. Its
onboard peripherals include two USB Type-C ports (1 device, 1 host)
and RTL8189FTV WLAN.

A MangoPi MQ-R variant of the board also exists. The MQ-R has a
different form factor, but the onboard peripherals are the same.

Most D1 and D1s boards use a similar power tree, with the 1.8V rail
powered by the SoC's internal LDOA, analog domains powered by ALDO,
and the rest of the board powered by always-on fixed regulators. To
avoid duplication, factor out the regulator information that is
common across boards.

The board also exposes GPIO Port E via a FPC connector, which can
support either a camera or an RMII Ethernet PHY. The additional
regulators supply that connector.

Signed-off-by: Samuel Holland <[email protected]>
---

Changes in v2:
- New patch for v2

arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/allwinner/Makefile | 2 +
.../allwinner/sun20i-common-regulators.dtsi | 35 +++++
.../dts/allwinner/sun20i-d1s-mangopi-mq.dts | 135 ++++++++++++++++++
4 files changed, 173 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..f292e31bdb2c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+subdir-y += allwinner
subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
new file mode 100644
index 000000000000..2f2792594f7d
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi
new file mode 100644
index 000000000000..de1adf2a2759
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+/ {
+ reg_vcc: vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vcc_3v3: vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&reg_vcc>;
+ };
+};
+
+&pio {
+ vcc-pb-supply = <&reg_vcc_3v3>;
+ vcc-pc-supply = <&reg_vcc_3v3>;
+ vcc-pd-supply = <&reg_vcc_3v3>;
+ vcc-pe-supply = <&reg_vcc_3v3>;
+ vcc-pf-supply = <&reg_vcc_3v3>;
+ vcc-pg-supply = <&reg_vcc_3v3>;
+};
+
+&reg_ldoa {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ ldo-in-supply = <&reg_vcc_3v3>;
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts
new file mode 100644
index 000000000000..11b150182490
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/dts-v1/;
+
+#include "sun20i-d1s.dtsi"
+#include "sun20i-common-regulators.dtsi"
+
+/ {
+ model = "MangoPi MQ";
+ compatible = "widora,mangopi-mq", "allwinner,sun20i-d1s";
+
+ aliases {
+ ethernet0 = &rtl8189ftv;
+ mmc0 = &mmc0;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_BACKLIGHT;
+ gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */
+ };
+ };
+
+ reg_avdd2v8: avdd2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <&reg_vcc_3v3>;
+ };
+
+ reg_dvdd: dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&reg_vcc_3v3>;
+ };
+
+ reg_vcc_core: vcc-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-core";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&reg_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vcc_core>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rtl8189ftv: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pe-supply = <&reg_avdd2v8>;
+};
+
+&reg_ldob {
+ regulator-name = "vcc-dram";
+ regulator-always-on;
+ ldo-in-supply = <&reg_vcc_3v3>;
+};
+
+&uart3 {
+ pinctrl-0 = <&uart3_pb_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
--
2.37.4

2022-11-26 00:21:14

[permalink] [raw]

Subject: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

Now that several D1-based boards are supported, enable the platform in
our defconfig. Build in the drivers which are necessary to boot, such as
the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
and watchdog (which may be left enabled by the bootloader). Other common
onboard peripherals are enabled as modules.

Signed-off-by: Samuel Holland <[email protected]>
---

(no changes since v1)

arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..8dfe0550c0e6 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_PROFILING=y
+CONFIG_ARCH_SUNXI=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
@@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_E1000E=y
CONFIG_R8169=y
+CONFIG_STMMAC_ETH=m
CONFIG_MICROSEMI_PHY=y
CONFIG_INPUT_MOUSEDEV=y
+CONFIG_KEYBOARD_SUN4I_LRADC=m
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_MV64XXX=m
CONFIG_SPI=y
CONFIG_SPI_SIFIVE=y
+CONFIG_SPI_SUN6I=y
# CONFIG_PTP_1588_CLOCK is not set
-CONFIG_GPIOLIB=y
CONFIG_GPIO_SIFIVE=y
+CONFIG_WATCHDOG=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DRM=m
CONFIG_DRM_RADEON=m
CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_SUN4I=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SUNXI=m
+CONFIG_NOP_USB_XCEIV=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SPI=y
+CONFIG_MMC_SUNXI=y
CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_SUN6I=m
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
+CONFIG_SUN8I_DE2_CCU=m
+CONFIG_SUN50I_IOMMU=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_VIRTIO=y
+CONFIG_PHY_SUN4I_USB=m
+CONFIG_NVMEM_SUNXI_SID=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
--
2.37.4

2022-11-26 00:22:00

[permalink] [raw]

Subject: [PATCH v2 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs

Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match
that pattern in addition to the designators for 32 and 64-bit ARM SoCs.

Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---

(no changes since v1)

MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index cd2cbb940f11..6a79f736fe35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1828,7 +1828,7 @@ F: drivers/pinctrl/sunxi/
F: drivers/soc/sunxi/
N: allwinner
N: sun[x456789]i
-N: sun50i
+N: sun[25]0i

ARM/Amlogic Meson SoC CLOCK FRAMEWORK
M: Neil Armstrong <[email protected]>
--
2.37.4

2022-11-26 00:22:24

[permalink] [raw]

Subject: [PATCH v2 07/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees

Sipeed manufactures a "Lichee RV" system-on-module, which provides a
minimal working system on its own, as well as a few carrier boards. The
"Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally
provides 100M Ethernet and a built-in display panel.

The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB
panel interface, since the USB OTG port is inaccessible inside the case.

Co-developed-by: Jisheng Zhang <[email protected]>
Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---

Changes in v2:
- Added DMIC sound card to Lichee RV dock and Lichee RV 86 Panel
- Removed LRADC (depends on analog LDOs)

arch/riscv/boot/dts/allwinner/Makefile | 4 +
.../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +++++
.../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 ++
.../sun20i-d1-lichee-rv-86-panel.dtsi | 118 ++++++++++++++++++
.../allwinner/sun20i-d1-lichee-rv-dock.dts | 96 ++++++++++++++
.../dts/allwinner/sun20i-d1-lichee-rv.dts | 88 +++++++++++++
6 files changed, 345 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index 277e59d1c907..f1c70b9dc9bf 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -1,3 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
new file mode 100644
index 000000000000..4df8ffb71561
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
+
+/ {
+ model = "Sipeed Lichee RV 86 Panel (480p)";
+ compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
+ "allwinner,sun20i-d1";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pb0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ touchscreen@48 {
+ compatible = "focaltech,ft6236";
+ reg = <0x48>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
+ iovcc-supply = <&reg_vcc_3v3>;
+ reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <480>;
+ vcc-supply = <&reg_vcc_3v3>;
+ wakeup-source;
+ };
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
new file mode 100644
index 000000000000..1874fc05359f
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
+
+/ {
+ model = "Sipeed Lichee RV 86 Panel (720p)";
+ compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
+ "allwinner,sun20i-d1";
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
new file mode 100644
index 000000000000..65408b7c66ab
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include "sun20i-d1-lichee-rv.dts"
+
+/ {
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &xr829;
+ };
+
+ dmic_codec: dmic-codec {
+ compatible = "dmic-codec";
+ num-channels = <2>;
+ #sound-dai-cells = <0>;
+ };
+
+ dmic-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DMIC";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ simple-audio-card,dai-link@0 {
+ format = "pdm";
+ frame-master = <&link0_cpu>;
+ bitclock-master = <&link0_cpu>;
+
+ link0_cpu: cpu {
+ sound-dai = <&dmic>;
+ };
+
+ link0_codec: codec {
+ sound-dai = <&dmic_codec>;
+ };
+ };
+ };
+
+ /* PC1 is repurposed as BT_WAKE_AP */
+ /delete-node/ leds;
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&ccu CLK_FANOUT1>;
+ clock-names = "ext_clock";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ assigned-clocks = <&ccu CLK_FANOUT1>;
+ assigned-clock-rates = <32768>;
+ pinctrl-0 = <&clk_pg11_pin>;
+ pinctrl-names = "default";
+ };
+};
+
+&dmic {
+ pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-0 = <&rmii_pe_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&ext_rmii_phy>;
+ phy-mode = "rmii";
+ phy-supply = <&reg_vcc_3v3>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
+ };
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ xr829: wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* XR829 bluetooth is connected here */
+};
+
+&usb_otg {
+ status = "disabled";
+};
+
+&usbphy {
+ /* PD20 and PD21 are repurposed for the LCD panel */
+ /delete-property/ usb0_id_det-gpios;
+ /delete-property/ usb0_vbus_det-gpios;
+ usb1_vbus-supply = <&reg_vcc>;
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
new file mode 100644
index 000000000000..57a1359193a8
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Jisheng Zhang <[email protected]>
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/input/input.h>
+
+#include "sun20i-d1-lichee-rv.dts"
+
+/ {
+ model = "Sipeed Lichee RV Dock";
+ compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
+ "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet1 = &rtl8723ds;
+ };
+
+ dmic_codec: dmic-codec {
+ compatible = "dmic-codec";
+ num-channels = <2>;
+ #sound-dai-cells = <0>;
+ };
+
+ dmic-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DMIC";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ simple-audio-card,dai-link@0 {
+ format = "pdm";
+ frame-master = <&link0_cpu>;
+ bitclock-master = <&link0_cpu>;
+
+ link0_cpu: cpu {
+ sound-dai = <&dmic>;
+ };
+
+ link0_codec: codec {
+ sound-dai = <&dmic_codec>;
+ };
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ };
+};
+
+&dmic {
+ pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rtl8723ds: wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723ds-bt";
+ device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
+ enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
+ host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
+ };
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc>;
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
new file mode 100644
index 000000000000..b1c458fae09e
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Jisheng Zhang <[email protected]>
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/dts-v1/;
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-common-regulators.dtsi"
+
+/ {
+ model = "Sipeed Lichee RV";
+ compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
+
+ aliases {
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
+ };
+ };
+
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&reg_vcc>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ usb0_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
--
2.37.4

2022-11-26 00:22:44

[permalink] [raw]

Subject: Re: [PATCH v2 02/12] dt-bindings: vendor-prefixes: Add Allwinner D1/D1s board vendors

Reviewed-by: Guo Ren <[email protected]>

On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]> wrote:
>
> Some boards using the Allwinner D1 or D1s SoC are made by vendors not
> previously documented.
>
> Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the
> ClockworkPi and DevTerm boards.
>
> Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures
> the MangoPi family of boards.
>
> Acked-by: Rob Herring <[email protected]>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> (no changes since v1)
>
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 592e43911a07..f2c67b7418e4 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -262,6 +262,8 @@ patternProperties:
> description: Cirrus Logic, Inc.
> "^cisco,.*":
> description: Cisco Systems, Inc.
> + "^clockwork,.*":
> + description: Clockwork Tech LLC
> "^cloudengines,.*":
> description: Cloud Engines, Inc.
> "^cnm,.*":
> @@ -1430,6 +1432,8 @@ patternProperties:
> description: Shenzhen whwave Electronics, Inc.
> "^wi2wi,.*":
> description: Wi2Wi, Inc.
> + "^widora,.*":
> + description: Beijing Widora Technology Co., Ltd.
> "^wiligear,.*":
> description: Wiligear, Ltd.
> "^willsemi,.*":
> --
> 2.37.4
>

--
Best Regards
Guo Ren

2022-11-26 00:31:09

[permalink] [raw]

Subject: Re: [PATCH v2 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs

On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]> wrote:
>
> Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match
> that pattern in addition to the designators for 32 and 64-bit ARM SoCs.
Reviewed-by: Guo Ren <[email protected]>

>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> (no changes since v1)
>
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cd2cbb940f11..6a79f736fe35 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1828,7 +1828,7 @@ F: drivers/pinctrl/sunxi/
> F: drivers/soc/sunxi/
> N: allwinner
> N: sun[x456789]i
> -N: sun50i
> +N: sun[25]0i
>
> ARM/Amlogic Meson SoC CLOCK FRAMEWORK
> M: Neil Armstrong <[email protected]>
> --
> 2.37.4
>

--
Best Regards
Guo Ren

2022-11-26 00:52:58

[permalink] [raw]

Subject: Re: [PATCH v2 09/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree

Reviewed-by: Guo Ren <[email protected]>

On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]> wrote:
>
> The 100ask Dongshan Nezha STU is a system-on-module that can be used
> standalone or with a carrier board. The SoM provides gigabit Ethernet,
> HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.
>
> The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
> headers, but contains no digital circuitry, so it does not have its own
> devicetree.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> (no changes since v1)
>
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> .../sun20i-d1-dongshan-nezha-stu.dts | 118 ++++++++++++++++++
> 2 files changed, 119 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
>
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> index 2ed586fafaea..87f70b1af6b4 100644
> --- a/arch/riscv/boot/dts/allwinner/Makefile
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
> new file mode 100644
> index 000000000000..c549a1c5fbf0
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/dts-v1/;
> +
> +#include "sun20i-d1.dtsi"
> +#include "sun20i-common-regulators.dtsi"
> +
> +/ {
> + model = "Dongshan Nezha STU";
> + compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
> +
> + aliases {
> + ethernet0 = &emac;
> + mmc0 = &mmc0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-0 {
> + color = <LED_COLOR_ID_GREEN>;
> + function = LED_FUNCTION_STATUS;
> + gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
> + };
> + };
> +
> + reg_usbvbus: usbvbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usbvbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
> + enable-active-high;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + /*
> + * This regulator is PWM-controlled, but the PWM controller is not
> + * yet supported, so fix the regulator to its default voltage.
> + */
> + reg_vdd_cpu: vdd-cpu {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-cpu";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + vin-supply = <&reg_vcc>;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&reg_vdd_cpu>;
> +};
> +
> +&dcxo {
> + clock-frequency = <24000000>;
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&emac {
> + pinctrl-0 = <&rgmii_pe_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&reg_vcc_3v3>;
> + status = "okay";
> +};
> +
> +&mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&mmc0 {
> + broken-cd;
> + bus-width = <4>;
> + disable-wp;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb8_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
> + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
> + usb0_vbus-supply = <&reg_usbvbus>;
> + status = "okay";
> +};
> --
> 2.37.4
>

--
Best Regards
Guo Ren

2022-11-26 00:53:24

[permalink] [raw]

Subject: Re: [PATCH v2 06/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

Reviewed-by: Guo Ren <[email protected]>

On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]> wrote:
>
> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
> plus low-speed I/O from the SoC and a GPIO expander chip.
>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Tested-by: Conor Dooley <[email protected]>
> Tested-by: Heiko Stuebner <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v2:
> - Common regulators moved to MangoPi MQ patch, removed analog LDOs
> - Removed LRADC (depends on analog LDOs)
> - Added XR829 host-wake interrupt
>
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 167 ++++++++++++++++++
> 2 files changed, 168 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
>
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> index 2f2792594f7d..277e59d1c907 100644
> --- a/arch/riscv/boot/dts/allwinner/Makefile
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> new file mode 100644
> index 000000000000..9ea3648e64ea
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/dts-v1/;
> +
> +#include "sun20i-d1.dtsi"
> +#include "sun20i-common-regulators.dtsi"
> +
> +/ {
> + model = "Allwinner D1 Nezha";
> + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
> +
> + aliases {
> + ethernet0 = &emac;
> + ethernet1 = &xr829;
> + mmc0 = &mmc0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reg_usbvbus: usbvbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usbvbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
> + enable-active-high;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + /*
> + * This regulator is PWM-controlled, but the PWM controller is not
> + * yet supported, so fix the regulator to its default voltage.
> + */
> + reg_vdd_cpu: vdd-cpu {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-cpu";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&reg_vdd_cpu>;
> +};
> +
> +&dcxo {
> + clock-frequency = <24000000>;
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&emac {
> + pinctrl-0 = <&rgmii_pe_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&reg_vcc_3v3>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-0 = <&i2c2_pb0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + pcf8574a: gpio@38 {
> + compatible = "nxp,pcf8574a";
> + reg = <0x38>;
> + interrupt-parent = <&pio>;
> + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
> + interrupt-controller;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&mmc0 {
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + disable-wp;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mmc1 {
> + bus-width = <4>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + non-removable;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + xr829: wifi@1 {
> + reg = <1>;
> + interrupt-parent = <&pio>;
> + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
> + interrupt-names = "host-wake";
> + };
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb8_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart1 {
> + uart-has-rtscts;
> + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + /* XR829 bluetooth is connected here */
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
> + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
> + usb0_vbus-supply = <&reg_usbvbus>;
> + usb1_vbus-supply = <&reg_vcc>;
> + status = "okay";
> +};
> --
> 2.37.4
>

--
Best Regards
Guo Ren

2022-11-26 00:55:29

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]> wrote:
>
> Now that several D1-based boards are supported, enable the platform in
> our defconfig. Build in the drivers which are necessary to boot, such as
> the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
> and watchdog (which may be left enabled by the bootloader). Other common
> onboard peripherals are enabled as modules.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> (no changes since v1)
>
> arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 05fd5fcf24f9..8dfe0550c0e6 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> CONFIG_PROFILING=y
> +CONFIG_ARCH_SUNXI=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> @@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
> CONFIG_MACB=y
> CONFIG_E1000E=y
> CONFIG_R8169=y
> +CONFIG_STMMAC_ETH=m
> CONFIG_MICROSEMI_PHY=y
> CONFIG_INPUT_MOUSEDEV=y
> +CONFIG_KEYBOARD_SUN4I_LRADC=m
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_DW=y
> CONFIG_SERIAL_OF_PLATFORM=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> +CONFIG_I2C_MV64XXX=m
> CONFIG_SPI=y
> CONFIG_SPI_SIFIVE=y
> +CONFIG_SPI_SUN6I=y
> # CONFIG_PTP_1588_CLOCK is not set
> -CONFIG_GPIOLIB=y
> CONFIG_GPIO_SIFIVE=y
> +CONFIG_WATCHDOG=y
> +CONFIG_SUNXI_WATCHDOG=y
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> CONFIG_DRM=m
> CONFIG_DRM_RADEON=m
> CONFIG_DRM_NOUVEAU=m
> +CONFIG_DRM_SUN4I=m
> CONFIG_DRM_VIRTIO_GPU=m
> CONFIG_FB=y
> CONFIG_FRAMEBUFFER_CONSOLE=y
> @@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_USB_MUSB_HDRC=m
> +CONFIG_USB_MUSB_SUNXI=m
> +CONFIG_NOP_USB_XCEIV=m
> CONFIG_MMC=y
> CONFIG_MMC_SDHCI=y
> CONFIG_MMC_SDHCI_PLTFM=y
> CONFIG_MMC_SDHCI_CADENCE=y
> CONFIG_MMC_SPI=y
> +CONFIG_MMC_SUNXI=y
> CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_SUN6I=y
> +CONFIG_DMADEVICES=y
> +CONFIG_DMA_SUN6I=m
> CONFIG_VIRTIO_PCI=y
> CONFIG_VIRTIO_BALLOON=y
> CONFIG_VIRTIO_INPUT=y
> CONFIG_VIRTIO_MMIO=y
> +CONFIG_SUN8I_DE2_CCU=m
> +CONFIG_SUN50I_IOMMU=y
Do we need IOMMU?

Others:
Reviewed-by: Guo Ren <[email protected]>

> CONFIG_RPMSG_CHAR=y
> CONFIG_RPMSG_CTRL=y
> CONFIG_RPMSG_VIRTIO=y
> +CONFIG_PHY_SUN4I_USB=m
> +CONFIG_NVMEM_SUNXI_SID=y
> CONFIG_EXT4_FS=y
> CONFIG_EXT4_FS_POSIX_ACL=y
> CONFIG_EXT4_FS_SECURITY=y
> --
> 2.37.4
>

--
Best Regards
Guo Ren

2022-11-26 00:55:41

[permalink] [raw]

Subject: Re: [PATCH v2 11/12] riscv: Add the Allwinner SoC family Kconfig option

Reviewed-by: Guo Ren <[email protected]>

On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]> wrote:
>
> Allwinner manufactures the sunxi family of application processors. This
> includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
> SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>
> The first SoC in the sun20i series is D1, containing a single T-HEAD
> C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>
> Most peripherals are shared across the entire chip family. In fact, the
> ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
> with the D1s.
>
> This means many existing device drivers can be reused. To facilitate
> this reuse, name the symbol ARCH_SUNXI, since that is what the existing
> drivers have as their dependency.
>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Tested-by: Heiko Stuebner <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v2:
> - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing
>
> arch/riscv/Kconfig.socs | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..4c1dc2ca11f9 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -26,6 +26,15 @@ config SOC_STARFIVE
> help
> This enables support for StarFive SoC platform hardware.
>
> +config ARCH_SUNXI
> + bool "Allwinner sun20i SoCs"
> + select ERRATA_THEAD if MMU && !XIP_KERNEL
> + select SIFIVE_PLIC
> + select SUN4I_TIMER
> + help
> + This enables support for Allwinner sun20i platform hardware,
> + including boards based on the D1 and D1s SoCs.
> +
> config SOC_VIRT
> bool "QEMU Virt Machine"
> select CLINT_TIMER if RISCV_M_MODE
> --
> 2.37.4
>

--
Best Regards
Guo Ren

2022-11-26 00:55:45

[permalink] [raw]

Subject: Re: [PATCH v2 05/12] riscv: dts: allwinner: Add MangoPi MQ devicetree

Reviewed-by: Guo Ren <[email protected]>

On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]> wrote:
>
> The MangoPi MQ is a tiny SBC built around the Allwinner D1s. Its
> onboard peripherals include two USB Type-C ports (1 device, 1 host)
> and RTL8189FTV WLAN.
>
> A MangoPi MQ-R variant of the board also exists. The MQ-R has a
> different form factor, but the onboard peripherals are the same.
>
> Most D1 and D1s boards use a similar power tree, with the 1.8V rail
> powered by the SoC's internal LDOA, analog domains powered by ALDO,
> and the rest of the board powered by always-on fixed regulators. To
> avoid duplication, factor out the regulator information that is
> common across boards.
>
> The board also exposes GPIO Port E via a FPC connector, which can
> support either a camera or an RMII Ethernet PHY. The additional
> regulators supply that connector.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v2:
> - New patch for v2
>
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/Makefile | 2 +
> .../allwinner/sun20i-common-regulators.dtsi | 35 +++++
> .../dts/allwinner/sun20i-d1s-mangopi-mq.dts | 135 ++++++++++++++++++
> 4 files changed, 173 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..f292e31bdb2c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> +subdir-y += allwinner
> subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> new file mode 100644
> index 000000000000..2f2792594f7d
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi
> new file mode 100644
> index 000000000000..de1adf2a2759
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +/ {
> + reg_vcc: vcc {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_vcc_3v3: vcc-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&reg_vcc>;
> + };
> +};
> +
> +&pio {
> + vcc-pb-supply = <&reg_vcc_3v3>;
> + vcc-pc-supply = <&reg_vcc_3v3>;
> + vcc-pd-supply = <&reg_vcc_3v3>;
> + vcc-pe-supply = <&reg_vcc_3v3>;
> + vcc-pf-supply = <&reg_vcc_3v3>;
> + vcc-pg-supply = <&reg_vcc_3v3>;
> +};
> +
> +&reg_ldoa {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + ldo-in-supply = <&reg_vcc_3v3>;
> +};
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts
> new file mode 100644
> index 000000000000..11b150182490
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts
> @@ -0,0 +1,135 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/dts-v1/;
> +
> +#include "sun20i-d1s.dtsi"
> +#include "sun20i-common-regulators.dtsi"
> +
> +/ {
> + model = "MangoPi MQ";
> + compatible = "widora,mangopi-mq", "allwinner,sun20i-d1s";
> +
> + aliases {
> + ethernet0 = &rtl8189ftv;
> + mmc0 = &mmc0;
> + serial3 = &uart3;
> + };
> +
> + chosen {
> + stdout-path = "serial3:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-0 {
> + color = <LED_COLOR_ID_BLUE>;
> + function = LED_FUNCTION_BACKLIGHT;
> + gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */
> + };
> + };
> +
> + reg_avdd2v8: avdd2v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "avdd2v8";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + vin-supply = <&reg_vcc_3v3>;
> + };
> +
> + reg_dvdd: dvdd {
> + compatible = "regulator-fixed";
> + regulator-name = "dvdd";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + vin-supply = <&reg_vcc_3v3>;
> + };
> +
> + reg_vcc_core: vcc-core {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-core";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&reg_vcc_core>;
> +};
> +
> +&dcxo {
> + clock-frequency = <24000000>;
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> + disable-wp;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mmc1 {
> + bus-width = <4>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + non-removable;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + rtl8189ftv: wifi@1 {
> + reg = <1>;
> + interrupt-parent = <&pio>;
> + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
> + interrupt-names = "host-wake";
> + };
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&pio {
> + vcc-pe-supply = <&reg_avdd2v8>;
> +};
> +
> +&reg_ldob {
> + regulator-name = "vcc-dram";
> + regulator-always-on;
> + ldo-in-supply = <&reg_vcc_3v3>;
> +};
> +
> +&uart3 {
> + pinctrl-0 = <&uart3_pb_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb1_vbus-supply = <&reg_vcc>;
> + status = "okay";
> +};
> --
> 2.37.4
>

--
Best Regards
Guo Ren

2022-11-26 01:14:31

[permalink] [raw]

Subject: Re: [PATCH v2 08/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree

Reviewed-by: Guo Ren <[email protected]>

On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]> wrote:
>
> The MangoPi MQ Pro is a tiny SBC with a layout compatible to the
> Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3,
> and an RTL8723DS-based WiFi/Bluetooth module.
>
> The board also exposes GPIO Port E via a connector on the end of the
> board, which can support either a camera or an RMII Ethernet PHY. The
> additional regulators supply that connector.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v2:
> - Added LED (GPIO shared between onboard LED and backlight regulator)
>
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 143 ++++++++++++++++++
> 2 files changed, 144 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
>
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> index f1c70b9dc9bf..2ed586fafaea 100644
> --- a/arch/riscv/boot/dts/allwinner/Makefile
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
> new file mode 100644
> index 000000000000..6d5897dc22e2
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/dts-v1/;
> +
> +#include "sun20i-d1.dtsi"
> +#include "sun20i-common-regulators.dtsi"
> +
> +/ {
> + model = "MangoPi MQ Pro";
> + compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
> +
> + aliases {
> + ethernet0 = &rtl8723ds;
> + mmc0 = &mmc0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-0 {
> + color = <LED_COLOR_ID_BLUE>;
> + function = LED_FUNCTION_BACKLIGHT;
> + gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
> + };
> + };
> +
> + reg_avdd2v8: avdd2v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "avdd2v8";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + vin-supply = <&reg_vcc_3v3>;
> + };
> +
> + reg_dvdd: dvdd {
> + compatible = "regulator-fixed";
> + regulator-name = "dvdd";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + vin-supply = <&reg_vcc_3v3>;
> + };
> +
> + reg_vdd_cpu: vdd-cpu {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-cpu";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&reg_vdd_cpu>;
> +};
> +
> +&dcxo {
> + clock-frequency = <24000000>;
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + disable-wp;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mmc1 {
> + bus-width = <4>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + non-removable;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + rtl8723ds: wifi@1 {
> + reg = <1>;
> + interrupt-parent = <&pio>;
> + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
> + interrupt-names = "host-wake";
> + };
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&pio {
> + vcc-pe-supply = <&reg_avdd2v8>;
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb8_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart1 {
> + uart-has-rtscts;
> + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + bluetooth {
> + compatible = "realtek,rtl8723ds-bt";
> + device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
> + enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
> + host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
> + };
> +};
> +
> +&usb_otg {
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb1_vbus-supply = <&reg_vcc>;
> + status = "okay";
> +};
> --
> 2.37.4
>

--
Best Regards
Guo Ren

2022-11-26 10:44:30

[permalink] [raw]

Subject: Re: [PATCH v2 00/12] riscv: Allwinner D1/D1s platform support

Hey Samuel,

On Fri, Nov 25, 2022 at 05:46:44PM -0600, Samuel Holland wrote:
> This series adds the Kconfig/defconfig plumbing and devicetrees for a
> range of Allwinner D1 and D1s-based boards. Many features are already
> enabled, including USB, Ethernet, and WiFi.
>
> The devicetrees use bindings from the following series which have not
> yet been merged:
> - In-package LDO regulators:
> https://lore.kernel.org/lkml/[email protected]/
> - Ethernet MAC binding fixes (not a new issue with D1):
> https://lore.kernel.org/lkml/[email protected]/
> - RTL8723DS Bluetooth (has driver support, missing documentation):
> https://lore.kernel.org/lkml/[email protected]/
> - TI ADC101C ADC (has driver support, missing documentation):
> https://lore.kernel.org/lkml/[email protected]/
>
> $ make ARCH=riscv CROSS_COMPILE=riscv64-linux-musl- dtbs_check
> SYNC include/config/auto.conf.cmd
> LINT Documentation/devicetree/bindings
> CHKDT Documentation/devicetree/bindings/processed-schema.json
> SCHEMA Documentation/devicetree/bindings/processed-schema.json
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dtb

Ran this last night, so before I go mess with your timer stuff & forget
there were a good few warnings about surplus-to-requirements address &
size cells. Other than that,

sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sun20i-d1-lichee-rv-86-panel.dtsi:24.32-36.5: Warning (unit_address_vs_reg): /dmic-sound/simple-audio-card,dai-link@0: node has a unit name, but no reg or ranges property
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sun20i-d1-lichee-rv-86-panel.dtsi:18.13-37.4: Warning (avoid_unnecessary_addr_size): /dmic-sound: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sun20i-d1-lichee-rv-dock.dts:30.32-42.5: Warning (unit_address_vs_reg): /dmic-sound/simple-audio-card,dai-link@0: node has a unit name, but no reg or ranges property
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sun20i-d1-lichee-rv-dock.dts:24.13-43.4: Warning (avoid_unnecessary_addr_size): /dmic-sound: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sun20i-d1-lichee-rv-86-panel.dtsi:24.32-36.5: Warning (unit_address_vs_reg): /dmic-sound/simple-audio-card,dai-link@0: node has a unit name, but no reg or ranges property
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sun20i-d1-lichee-rv-86-panel.dtsi:18.13-37.4: Warning (avoid_unnecessary_addr_size): /dmic-sound: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sunxi-d1s-t113.dtsi:616.20-636.5: Warning (avoid_unnecessary_addr_size): /soc/dsi@5450000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
sunxi-d1s-t113.dtsi:666.32-675.7: Warning (graph_child_address): /soc/tcon-top@5460000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary

> The only remaining DT validation issue is that gpio-fan is missing a
> YAML conversion, although one is on the list here:
> https://lore.kernel.org/lkml/[email protected]/
> arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dtb:0:0: /fan: failed to match any schema with compatible: ['gpio-fan']

Documentation/devicetree/bindings/hwmon/gpio-fan.yaml

I actually didn't see this error on next-20221122 :)

2022-11-26 16:25:37

[permalink] [raw]

Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

On Fri, Nov 25, 2022 at 05:46:48PM -0600, Samuel Holland wrote:
> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
>
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's.

Is this "additionally contain" or a case of the D1 is the R528 but with
s/arm/riscv/? It's the latter, right?

> D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
>
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
>
> The devicetrees are organized to minimize duplication:
> - Common perhiperals are described in sunxi-d1s-t113.dtsi
> - DSP-related peripherals are described in sunxi-d1-t113.dtsi
> - RISC-V specific hardware is described in sun20i-d1s.dtsi
> - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
>
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.

Modulo the warnings I replied to the cover with & one minor comment
below:
Reviewed-by: Conor Dooley <[email protected]>

> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v2:
> - Split into separate files for sharing with D1s/R528/T113
> - Use SOC_PERIPHERAL_IRQ macro for interrupts
> - Rename osc24M to dcxo and move the frequency to the board DTs
> - Drop analog LDOs due to the missing binding
> - Correct tcon_top DSI clock reference
> - Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
> - Add CPU OPP table
>
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++
> .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 +
> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 844 ++++++++++++++++++
> 4 files changed, 1001 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> new file mode 100644
> index 000000000000..c8815cbf0b46
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> @@ -0,0 +1,844 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/clock/sun6i-rtc.h>
> +#include <dt-bindings/clock/sun8i-de2.h>
> +#include <dt-bindings/clock/sun8i-tcon-top.h>
> +#include <dt-bindings/clock/sun20i-d1-ccu.h>
> +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset/sun8i-de2.h>
> +#include <dt-bindings/reset/sun20i-d1-ccu.h>
> +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + dcxo: dcxo-clk {
> + compatible = "fixed-clock";
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;

Since this is a "must", can you drop the clock-frequency = <0> here so
that if someone doesn't override it in their board dt-validate
complains?

Thanks,
Conor.

> + clock-output-names = "dcxo";
> + #clock-cells = <0>;
> + };
> +

2022-11-26 17:26:00

[permalink] [raw]

Subject: Re: [PATCH v2 11/12] riscv: Add the Allwinner SoC family Kconfig option

On Fri, Nov 25, 2022 at 05:46:55PM -0600, Samuel Holland wrote:
> Allwinner manufactures the sunxi family of application processors. This
> includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
> SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>
> The first SoC in the sun20i series is D1, containing a single T-HEAD
> C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>
> Most peripherals are shared across the entire chip family. In fact, the
> ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
> with the D1s.
>
> This means many existing device drivers can be reused. To facilitate
> this reuse, name the symbol ARCH_SUNXI, since that is what the existing
> drivers have as their dependency.
>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Tested-by: Heiko Stuebner <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v2:
> - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing
>
> arch/riscv/Kconfig.socs | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..4c1dc2ca11f9 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -26,6 +26,15 @@ config SOC_STARFIVE
> help
> This enables support for StarFive SoC platform hardware.
>
> +config ARCH_SUNXI
> + bool "Allwinner sun20i SoCs"
> + select ERRATA_THEAD if MMU && !XIP_KERNEL

Does this need to have the if MMU? I thought it only needed the
!XIP_KERNEL since the PMU errata does not depend on MMU.

Or have a missed some patch elsewhere that'll change that?

> + select SIFIVE_PLIC

This is v6.3 material right? One of the things that should be going for
v6.3 is all of these select SIFIVE_PLICs. Palmer suggested putting up an
immutable branch for any of that cleanup that intersects with new
platforms, so I'll probably send one out at some stage.

Thanks,
Conor.

> + select SUN4I_TIMER
> + help
> + This enables support for Allwinner sun20i platform hardware,
> + including boards based on the D1 and D1s SoCs.
> +
> config SOC_VIRT
> bool "QEMU Virt Machine"
> select CLINT_TIMER if RISCV_M_MODE
> --
> 2.37.4
>

2022-11-26 17:34:47

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

On Fri, Nov 25, 2022 at 05:46:56PM -0600, Samuel Holland wrote:
> Now that several D1-based boards are supported, enable the platform in
> our defconfig. Build in the drivers which are necessary to boot, such as
> the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
> and watchdog (which may be left enabled by the bootloader).

All of that looks good.

> Other common
> onboard peripherals are enabled as modules.

This I am not sure about though. I'll leave that to Palmer since I'm
pretty sure it was him that said it, but I thought the plan was only
turning on stuff required to boot to a console & things that are
generally useful rather than enabling modules for everyone's "random"
drivers. Palmer?

>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> (no changes since v1)
>
> arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 05fd5fcf24f9..8dfe0550c0e6 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> CONFIG_PROFILING=y
> +CONFIG_ARCH_SUNXI=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> @@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
> CONFIG_MACB=y
> CONFIG_E1000E=y
> CONFIG_R8169=y
> +CONFIG_STMMAC_ETH=m
> CONFIG_MICROSEMI_PHY=y
> CONFIG_INPUT_MOUSEDEV=y
> +CONFIG_KEYBOARD_SUN4I_LRADC=m
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_DW=y
> CONFIG_SERIAL_OF_PLATFORM=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> +CONFIG_I2C_MV64XXX=m
> CONFIG_SPI=y
> CONFIG_SPI_SIFIVE=y
> +CONFIG_SPI_SUN6I=y
> # CONFIG_PTP_1588_CLOCK is not set
> -CONFIG_GPIOLIB=y
> CONFIG_GPIO_SIFIVE=y
> +CONFIG_WATCHDOG=y
> +CONFIG_SUNXI_WATCHDOG=y
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> CONFIG_DRM=m
> CONFIG_DRM_RADEON=m
> CONFIG_DRM_NOUVEAU=m
> +CONFIG_DRM_SUN4I=m
> CONFIG_DRM_VIRTIO_GPU=m
> CONFIG_FB=y
> CONFIG_FRAMEBUFFER_CONSOLE=y
> @@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_USB_MUSB_HDRC=m
> +CONFIG_USB_MUSB_SUNXI=m
> +CONFIG_NOP_USB_XCEIV=m
> CONFIG_MMC=y
> CONFIG_MMC_SDHCI=y
> CONFIG_MMC_SDHCI_PLTFM=y
> CONFIG_MMC_SDHCI_CADENCE=y
> CONFIG_MMC_SPI=y
> +CONFIG_MMC_SUNXI=y
> CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_SUN6I=y
> +CONFIG_DMADEVICES=y
> +CONFIG_DMA_SUN6I=m
> CONFIG_VIRTIO_PCI=y
> CONFIG_VIRTIO_BALLOON=y
> CONFIG_VIRTIO_INPUT=y
> CONFIG_VIRTIO_MMIO=y
> +CONFIG_SUN8I_DE2_CCU=m
> +CONFIG_SUN50I_IOMMU=y
> CONFIG_RPMSG_CHAR=y
> CONFIG_RPMSG_CTRL=y
> CONFIG_RPMSG_VIRTIO=y
> +CONFIG_PHY_SUN4I_USB=m
> +CONFIG_NVMEM_SUNXI_SID=y
> CONFIG_EXT4_FS=y
> CONFIG_EXT4_FS_POSIX_ACL=y
> CONFIG_EXT4_FS_SECURITY=y
> --
> 2.37.4
>

2022-11-26 17:35:38

[permalink] [raw]

Subject: Re: [PATCH v2 06/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

Reviewed-by: Conor Dooley <[email protected]>

2022-11-27 17:53:50

by Andre Przywara

[permalink] [raw]

Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

On Fri, 25 Nov 2022 17:46:48 -0600
Samuel Holland <[email protected]> wrote:

> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
>
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
>
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
>
> The devicetrees are organized to minimize duplication:
> - Common perhiperals are described in sunxi-d1s-t113.dtsi

So I compared all the reg and interrupts properties against the T113
manual, they match, as far as they are described there. The undocumented
rest matches what we already have in other SoCs.

I noticed two things, though, mentioned inline below:

> - DSP-related peripherals are described in sunxi-d1-t113.dtsi
> - RISC-V specific hardware is described in sun20i-d1s.dtsi
> - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
>
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v2:
> - Split into separate files for sharing with D1s/R528/T113
> - Use SOC_PERIPHERAL_IRQ macro for interrupts
> - Rename osc24M to dcxo and move the frequency to the board DTs
> - Drop analog LDOs due to the missing binding
> - Correct tcon_top DSI clock reference
> - Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
> - Add CPU OPP table
>
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++
> .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 +
> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 844 ++++++++++++++++++
> 4 files changed, 1001 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> new file mode 100644
> index 000000000000..97e7cbb32597
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +#include "sun20i-d1s.dtsi"
> +#include "sunxi-d1-t113.dtsi"
> +
> +/ {
> + soc {
> + lradc: keys@2009800 {
> + compatible = "allwinner,sun20i-d1-lradc",
> + "allwinner,sun50i-r329-lradc";
> + reg = <0x2009800 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(61) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_LRADC>;
> + resets = <&ccu RST_BUS_LRADC>;
> + status = "disabled";
> + };
> +
> + i2s0: i2s@2032000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2032000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(26) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S0>,
> + <&ccu CLK_I2S0>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S0>;
> + dmas = <&dma 3>, <&dma 3>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> + };
> +};
> +
> +&pio {
> + /omit-if-no-ref/
> + dmic_pb11_d0_pin: dmic-pb11-d0-pin {
> + pins = "PB11";
> + function = "dmic";
> + };
> +
> + /omit-if-no-ref/
> + dmic_pe17_clk_pin: dmic-pe17-clk-pin {
> + pins = "PE17";
> + function = "dmic";
> + };
> +
> + /omit-if-no-ref/
> + i2c0_pb10_pins: i2c0-pb10-pins {
> + pins = "PB10", "PB11";
> + function = "i2c0";
> + };
> +
> + /omit-if-no-ref/
> + i2c2_pb0_pins: i2c2-pb0-pins {
> + pins = "PB0", "PB1";
> + function = "i2c2";
> + };
> +
> + /omit-if-no-ref/
> + uart0_pb8_pins: uart0-pb8-pins {
> + pins = "PB8", "PB9";
> + function = "uart0";
> + };
> +};
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> new file mode 100644
> index 000000000000..859509832d58
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
> +
> +#include "sunxi-d1s-t113.dtsi"
> +
> +/ {
> + cpus {
> + timebase-frequency = <24000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = <&ccu CLK_RISCV>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <256>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + operating-points-v2 = <&opp_table_cpu>;
> + riscv,isa = "rv64imafdc";
> + #cooling-cells = <2>;
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + opp_table_cpu: opp-table-cpu {
> + compatible = "operating-points-v2";
> +
> + opp-408000000 {
> + opp-hz = /bits/ 64 <408000000>;
> + opp-microvolt = <900000 900000 1100000>;
> + };
> +
> + opp-1080000000 {
> + opp-hz = /bits/ 64 <1008000000>;
> + opp-microvolt = <900000 900000 1100000>;
> + };
> + };
> +
> + soc {
> + interrupt-parent = <&plic>;
> +
> + riscv_wdt: watchdog@6011000 {
> + compatible = "allwinner,sun20i-d1-wdt";
> + reg = <0x6011000 0x20>;
> + interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + };
> +
> + plic: interrupt-controller@10000000 {
> + compatible = "allwinner,sun20i-d1-plic",
> + "thead,c900-plic";
> + reg = <0x10000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu0_intc 9>;
> + interrupt-controller;
> + riscv,ndev = <176>;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + };
> + };
> +};
> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> new file mode 100644
> index 000000000000..b7156123df54
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +/ {
> + soc {
> + dsp_wdt: watchdog@1700400 {
> + compatible = "allwinner,sun20i-d1-wdt";
> + reg = <0x1700400 0x20>;
> + interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + status = "reserved";
> + };
> + };
> +};
> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> new file mode 100644
> index 000000000000..c8815cbf0b46
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> @@ -0,0 +1,844 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/clock/sun6i-rtc.h>
> +#include <dt-bindings/clock/sun8i-de2.h>
> +#include <dt-bindings/clock/sun8i-tcon-top.h>
> +#include <dt-bindings/clock/sun20i-d1-ccu.h>
> +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset/sun8i-de2.h>
> +#include <dt-bindings/reset/sun20i-d1-ccu.h>
> +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + dcxo: dcxo-clk {
> + compatible = "fixed-clock";
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + clock-output-names = "dcxo";
> + #clock-cells = <0>;
> + };
> +
> + de: display-engine {
> + compatible = "allwinner,sun20i-d1-display-engine";
> + allwinner,pipelines = <&mixer0>, <&mixer1>;
> + status = "disabled";
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + ranges;
> + dma-noncoherent;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + pio: pinctrl@2000000 {
> + compatible = "allwinner,sun20i-d1-pinctrl";
> + reg = <0x2000000 0x800>;
> + interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
> + <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
> + <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
> + <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
> + <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
> + <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_APB0>,
> + <&dcxo>,
> + <&rtc CLK_OSC32K>;
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + interrupt-controller;
> + #gpio-cells = <3>;
> + #interrupt-cells = <3>;
> +
> + /omit-if-no-ref/
> + clk_pg11_pin: clk-pg11-pin {
> + pins = "PG11";
> + function = "clk";
> + };
> +
> + /omit-if-no-ref/
> + dsi_4lane_pins: dsi-4lane-pins {
> + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
> + "PD6", "PD7", "PD8", "PD9";
> + drive-strength = <30>;
> + function = "dsi";
> + };
> +
> + /omit-if-no-ref/
> + lcd_rgb666_pins: lcd-rgb666-pins {
> + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
> + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
> + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
> + "PD18", "PD19", "PD20", "PD21";
> + function = "lcd0";
> + };
> +
> + /omit-if-no-ref/
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> + function = "mmc0";
> + };
> +
> + /omit-if-no-ref/
> + mmc1_pins: mmc1-pins {
> + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
> + function = "mmc1";
> + };
> +
> + /omit-if-no-ref/
> + mmc2_pins: mmc2-pins {
> + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
> + function = "mmc2";
> + };
> +
> + /omit-if-no-ref/
> + rgmii_pe_pins: rgmii-pe-pins {
> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> + "PE5", "PE6", "PE7", "PE8", "PE9",
> + "PE11", "PE12", "PE13", "PE14", "PE15";
> + function = "emac";
> + };
> +
> + /omit-if-no-ref/
> + rmii_pe_pins: rmii-pe-pins {
> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> + "PE5", "PE6", "PE7", "PE8", "PE9";
> + function = "emac";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pg6_pins: uart1-pg6-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
> + pins = "PG8", "PG9";
> + function = "uart1";
> + };
> +
> + /omit-if-no-ref/
> + uart3_pb_pins: uart3-pb-pins {
> + pins = "PB6", "PB7";
> + function = "uart3";
> + };
> + };
> +
> + ccu: clock-controller@2001000 {
> + compatible = "allwinner,sun20i-d1-ccu";
> + reg = <0x2001000 0x1000>;
> + clocks = <&dcxo>,
> + <&rtc CLK_OSC32K>,
> + <&rtc CLK_IOSC>;
> + clock-names = "hosc", "losc", "iosc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + dmic: dmic@2031000 {
> + compatible = "allwinner,sun20i-d1-dmic",
> + "allwinner,sun50i-h6-dmic";
> + reg = <0x2031000 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_DMIC>,
> + <&ccu CLK_DMIC>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_DMIC>;
> + dmas = <&dma 8>;
> + dma-names = "rx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + i2s1: i2s@2033000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2033000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S1>,
> + <&ccu CLK_I2S1>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S1>;
> + dmas = <&dma 4>, <&dma 4>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + i2s2: i2s@2034000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2034000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S2>,
> + <&ccu CLK_I2S2>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S2>;
> + dmas = <&dma 5>, <&dma 5>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + timer: timer@2050000 {
> + compatible = "allwinner,sun20i-d1-timer",
> + "allwinner,sun8i-a23-timer";
> + reg = <0x2050000 0xa0>;
> + interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
> + <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dcxo>;
> + };
> +
> + wdt: watchdog@20500a0 {
> + compatible = "allwinner,sun20i-d1-wdt-reset",
> + "allwinner,sun20i-d1-wdt";
> + reg = <0x20500a0 0x20>;
> + interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + status = "reserved";
> + };
> +
> + uart0: serial@2500000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500000 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + dmas = <&dma 14>, <&dma 14>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart1: serial@2500400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500400 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + dmas = <&dma 15>, <&dma 15>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart2: serial@2500800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500800 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + dmas = <&dma 16>, <&dma 16>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart3: serial@2500c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500c00 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + dmas = <&dma 17>, <&dma 17>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart4: serial@2501000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2501000 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + dmas = <&dma 18>, <&dma 18>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart5: serial@2501400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2501400 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART5>;
> + resets = <&ccu RST_BUS_UART5>;
> + dmas = <&dma 19>, <&dma 19>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + i2c0: i2c@2502000 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502000 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + dmas = <&dma 43>, <&dma 43>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@2502400 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502400 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + dmas = <&dma 44>, <&dma 44>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@2502800 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502800 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + dmas = <&dma 45>, <&dma 45>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@2502c00 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502c00 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C3>;
> + resets = <&ccu RST_BUS_I2C3>;
> + dmas = <&dma 46>, <&dma 46>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + syscon: syscon@3000000 {
> + compatible = "allwinner,sun20i-d1-system-control";
> + reg = <0x3000000 0x1000>;
> + ranges;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + regulators@3000150 {
> + compatible = "allwinner,sun20i-d1-system-ldos";
> + reg = <0x3000150 0x4>;
> +
> + reg_ldoa: ldoa {
> + };
> +
> + reg_ldob: ldob {
> + };
> + };
> + };
> +
> + dma: dma-controller@3002000 {
> + compatible = "allwinner,sun20i-d1-dma";
> + reg = <0x3002000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
> + clock-names = "bus", "mbus";
> + resets = <&ccu RST_BUS_DMA>;
> + dma-channels = <16>;
> + dma-requests = <48>;
> + #dma-cells = <1>;
> + };
> +
> + sid: efuse@3006000 {
> + compatible = "allwinner,sun20i-d1-sid";
> + reg = <0x3006000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +
> + mbus: dram-controller@3102000 {
> + compatible = "allwinner,sun20i-d1-mbus";
> + reg = <0x3102000 0x1000>,
> + <0x3103000 0x1000>;
> + reg-names = "mbus", "dram";
> + interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_MBUS>,
> + <&ccu CLK_DRAM>,
> + <&ccu CLK_BUS_DRAM>;
> + clock-names = "mbus", "dram", "bus";
> + dma-ranges = <0 0x40000000 0x80000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interconnect-cells = <1>;
> + };
> +
> + mmc0: mmc@4020000 {
> + compatible = "allwinner,sun20i-d1-mmc";
> + reg = <0x4020000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + cap-sd-highspeed;
> + max-frequency = <150000000>;
> + no-mmc;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@4021000 {
> + compatible = "allwinner,sun20i-d1-mmc";
> + reg = <0x4021000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + cap-sd-highspeed;
> + max-frequency = <150000000>;
> + no-mmc;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@4022000 {
> + compatible = "allwinner,sun20i-d1-emmc",
> + "allwinner,sun50i-a100-emmc";
> + reg = <0x4022000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC2>;
> + reset-names = "ahb";
> + cap-mmc-highspeed;
> + max-frequency = <150000000>;
> + mmc-ddr-1_8v;
> + mmc-ddr-3_3v;
> + no-sd;
> + no-sdio;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + usb_otg: usb@4100000 {
> + compatible = "allwinner,sun20i-d1-musb",
> + "allwinner,sun8i-a33-musb";
> + reg = <0x4100000 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "mc";
> + clocks = <&ccu CLK_BUS_OTG>;
> + resets = <&ccu RST_BUS_OTG>;
> + extcon = <&usbphy 0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + usbphy: phy@4100400 {
> + compatible = "allwinner,sun20i-d1-usb-phy";
> + reg = <0x4100400 0x100>,
> + <0x4101800 0x100>,
> + <0x4200800 0x100>;
> + reg-names = "phy_ctrl",
> + "pmu0",
> + "pmu1";
> + clocks = <&dcxo>,
> + <&dcxo>;
> + clock-names = "usb0_phy",
> + "usb1_phy";
> + resets = <&ccu RST_USB_PHY0>,
> + <&ccu RST_USB_PHY1>;
> + reset-names = "usb0_reset",
> + "usb1_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ehci0: usb@4101000 {
> + compatible = "allwinner,sun20i-d1-ehci",
> + "generic-ehci";
> + reg = <0x4101000 0x100>;
> + interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_BUS_EHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_OHCI0>,
> + <&ccu RST_BUS_EHCI0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci0: usb@4101400 {
> + compatible = "allwinner,sun20i-d1-ohci",
> + "generic-ohci";
> + reg = <0x4101400 0x100>;
> + interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_OHCI0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb@4200000 {
> + compatible = "allwinner,sun20i-d1-ehci",
> + "generic-ehci";
> + reg = <0x4200000 0x100>;
> + interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_BUS_EHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>,
> + <&ccu RST_BUS_EHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci1: usb@4200400 {
> + compatible = "allwinner,sun20i-d1-ohci",
> + "generic-ohci";
> + reg = <0x4200400 0x100>;
> + interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + emac: ethernet@4500000 {
> + compatible = "allwinner,sun20i-d1-emac",
> + "allwinner,sun50i-a64-emac";
> + reg = <0x4500000 0x10000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&ccu CLK_BUS_EMAC>;
> + clock-names = "stmmaceth";
> + resets = <&ccu RST_BUS_EMAC>;
> + reset-names = "stmmaceth";
> + syscon = <&syscon>;
> + status = "disabled";
> +
> + mdio: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + display_clocks: clock-controller@5000000 {

The clocks and the two mixers are not children of a bus node anymore,
IIUC correctly this was to manage the SRAM control. Is that now handled
differently, or does the D1 generation not require this anymore?

> + compatible = "allwinner,sun20i-d1-de2-clk",
> + "allwinner,sun50i-h5-de2-clk";
> + reg = <0x5000000 0x10000>;
> + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + mixer0: mixer@5100000 {
> + compatible = "allwinner,sun20i-d1-de2-mixer-0";
> + reg = <0x5100000 0x100000>;
> + clocks = <&display_clocks CLK_BUS_MIXER0>,
> + <&display_clocks CLK_MIXER0>;
> + clock-names = "bus", "mod";
> + resets = <&display_clocks RST_MIXER0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer0_out: port@1 {
> + reg = <1>;
> +
> + mixer0_out_tcon_top_mixer0: endpoint {
> + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
> + };
> + };
> + };
> + };
> +
> + mixer1: mixer@5200000 {
> + compatible = "allwinner,sun20i-d1-de2-mixer-1";
> + reg = <0x5200000 0x100000>;
> + clocks = <&display_clocks CLK_BUS_MIXER1>,
> + <&display_clocks CLK_MIXER1>;
> + clock-names = "bus", "mod";
> + resets = <&display_clocks RST_MIXER1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer1_out: port@1 {
> + reg = <1>;
> +
> + mixer1_out_tcon_top_mixer1: endpoint {
> + remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
> + };
> + };
> + };
> + };
> +
> + dsi: dsi@5450000 {
> + compatible = "allwinner,sun20i-d1-mipi-dsi",
> + "allwinner,sun50i-a100-mipi-dsi";
> + reg = <0x5450000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MIPI_DSI>,
> + <&tcon_top CLK_TCON_TOP_DSI>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_MIPI_DSI>;
> + phys = <&dphy>;
> + phy-names = "dphy";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port {
> + dsi_in_tcon_lcd0: endpoint {
> + remote-endpoint = <&tcon_lcd0_out_dsi>;
> + };
> + };
> + };
> +
> + dphy: phy@5451000 {
> + compatible = "allwinner,sun20i-d1-mipi-dphy",
> + "allwinner,sun50i-a100-mipi-dphy";
> + reg = <0x5451000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;

This is the same interrupt number as for the DSI controller above. Is
that correct, and can the drivers handle that?

Cheers,
Andre

> + clocks = <&ccu CLK_BUS_MIPI_DSI>,
> + <&ccu CLK_MIPI_DSI>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_MIPI_DSI>;
> + #phy-cells = <0>;
> + };
> +
> + tcon_top: tcon-top@5460000 {
> + compatible = "allwinner,sun20i-d1-tcon-top";
> + reg = <0x5460000 0x1000>;
> + clocks = <&ccu CLK_BUS_DPSS_TOP>,
> + <&ccu CLK_TCON_TV>,
> + <&ccu CLK_TVE>,
> + <&ccu CLK_TCON_LCD0>;
> + clock-names = "bus", "tcon-tv0", "tve0", "dsi";
> + clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
> + resets = <&ccu RST_BUS_DPSS_TOP>;
> + #clock-cells = <1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_in_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
> + };
> + };
> +
> + tcon_top_mixer0_out: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
> + };
> +
> + tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
> + };
> + };
> +
> + tcon_top_mixer1_in: port@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer1_in_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
> + };
> + };
> +
> + tcon_top_mixer1_out: port@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
> + };
> +
> + tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
> + };
> + };
> +
> + tcon_top_hdmi_in: port@4 {
> + reg = <4>;
> +
> + tcon_top_hdmi_in_tcon_tv0: endpoint {
> + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
> + };
> + };
> +
> + tcon_top_hdmi_out: port@5 {
> + reg = <5>;
> + };
> + };
> + };
> +
> + tcon_lcd0: lcd-controller@5461000 {
> + compatible = "allwinner,sun20i-d1-tcon-lcd";
> + reg = <0x5461000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON_LCD0>,
> + <&ccu CLK_TCON_LCD0>;
> + clock-names = "ahb", "tcon-ch0";
> + clock-output-names = "tcon-pixel-clock";
> + resets = <&ccu RST_BUS_TCON_LCD0>,
> + <&ccu RST_BUS_LVDS0>;
> + reset-names = "lcd", "lvds";
> + #clock-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_lcd0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
> + };
> +
> + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
> + };
> + };
> +
> + tcon_lcd0_out: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_lcd0_out_dsi: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&dsi_in_tcon_lcd0>;
> + };
> + };
> + };
> + };
> +
> + tcon_tv0: lcd-controller@5470000 {
> + compatible = "allwinner,sun20i-d1-tcon-tv";
> + reg = <0x5470000 0x1000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON_TV>,
> + <&tcon_top CLK_TCON_TOP_TV0>;
> + clock-names = "ahb", "tcon-ch1";
> + resets = <&ccu RST_BUS_TCON_TV>;
> + reset-names = "lcd";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_tv0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
> + };
> +
> + tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
> + };
> + };
> +
> + tcon_tv0_out: port@1 {
> + reg = <1>;
> +
> + tcon_tv0_out_tcon_top_hdmi: endpoint {
> + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
> + };
> + };
> + };
> + };
> +
> + r_ccu: clock-controller@7010000 {
> + compatible = "allwinner,sun20i-d1-r-ccu";
> + reg = <0x7010000 0x400>;
> + clocks = <&dcxo>,
> + <&rtc CLK_OSC32K>,
> + <&rtc CLK_IOSC>,
> + <&ccu CLK_PLL_PERIPH0_DIV3>;
> + clock-names = "hosc", "losc", "iosc", "pll-periph";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + rtc: rtc@7090000 {
> + compatible = "allwinner,sun20i-d1-rtc",
> + "allwinner,sun50i-r329-rtc";
> + reg = <0x7090000 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_BUS_R_RTC>,
> + <&dcxo>,
> + <&r_ccu CLK_R_AHB>;
> + clock-names = "bus", "hosc", "ahb";
> + #clock-cells = <1>;
> + };
> + };
> +};

2022-11-27 19:55:13

[permalink] [raw]

Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

On 11/27/22 11:41, Andre Przywara wrote:
> On Fri, 25 Nov 2022 17:46:48 -0600
> Samuel Holland <[email protected]> wrote:
>
>> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
>> on a single die, or at a pair of dies derived from the same design.
>>
>> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
>> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
>> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
>> variants.
>>
>> Because the original design supported both ARM and RISC-V CPUs, some
>> peripherals are duplicated. In addition, all variants except D1s contain
>> a HiFi 4 DSP with its own set of peripherals.
>>
>> The devicetrees are organized to minimize duplication:
>> - Common perhiperals are described in sunxi-d1s-t113.dtsi
>
> So I compared all the reg and interrupts properties against the T113
> manual, they match, as far as they are described there. The undocumented
> rest matches what we already have in other SoCs.
>
> I noticed two things, though, mentioned inline below:
>
> [...]
>
>> + display_clocks: clock-controller@5000000 {
>
> The clocks and the two mixers are not children of a bus node anymore,
> IIUC correctly this was to manage the SRAM control. Is that now handled
> differently, or does the D1 generation not require this anymore?

The D1 family uses the DSP SRAM for extra space during early boot --
this applies even to D1s, where the DSP is fused off. Since the DE SRAM
is not used for this purpose, the "SRAM C" aka "boot mode" bit in the
SRAM controller is cleared by default, thus mapping the DE SRAM to the
peripheral. So the DE works without touching the syscon registers.

However, if I set the SRAM C bit, the DE stops working. So having the
bus node would make some sense. But I do not know any address for the
SRAM -- there is no "boot" address, and the "peripheral" address may not
even be accessible to the CPU. So it is not possible to represent this
with a mmio-sram node like the binding requires.

So I suppose we should either change the binding to allow a child
allwinner,sun50i-a64-sram-c node with no address (the driver should work
fine with this); or leave out the bus, and people who go poking around
in the syscon registers get to keep the pieces. :)

>> + compatible = "allwinner,sun20i-d1-de2-clk",
>> + "allwinner,sun50i-h5-de2-clk";
>> + reg = <0x5000000 0x10000>;
>> + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
>> + clock-names = "bus", "mod";
>> + resets = <&ccu RST_BUS_DE>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + mixer0: mixer@5100000 {
>> + compatible = "allwinner,sun20i-d1-de2-mixer-0";
>> + reg = <0x5100000 0x100000>;
>> + clocks = <&display_clocks CLK_BUS_MIXER0>,
>> + <&display_clocks CLK_MIXER0>;
>> + clock-names = "bus", "mod";
>> + resets = <&display_clocks RST_MIXER0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + mixer0_out: port@1 {
>> + reg = <1>;
>> +
>> + mixer0_out_tcon_top_mixer0: endpoint {
>> + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + mixer1: mixer@5200000 {
>> + compatible = "allwinner,sun20i-d1-de2-mixer-1";
>> + reg = <0x5200000 0x100000>;
>> + clocks = <&display_clocks CLK_BUS_MIXER1>,
>> + <&display_clocks CLK_MIXER1>;
>> + clock-names = "bus", "mod";
>> + resets = <&display_clocks RST_MIXER1>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + mixer1_out: port@1 {
>> + reg = <1>;
>> +
>> + mixer1_out_tcon_top_mixer1: endpoint {
>> + remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + dsi: dsi@5450000 {
>> + compatible = "allwinner,sun20i-d1-mipi-dsi",
>> + "allwinner,sun50i-a100-mipi-dsi";
>> + reg = <0x5450000 0x1000>;
>> + interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MIPI_DSI>,
>> + <&tcon_top CLK_TCON_TOP_DSI>;
>> + clock-names = "bus", "mod";
>> + resets = <&ccu RST_BUS_MIPI_DSI>;
>> + phys = <&dphy>;
>> + phy-names = "dphy";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port {
>> + dsi_in_tcon_lcd0: endpoint {
>> + remote-endpoint = <&tcon_lcd0_out_dsi>;
>> + };
>> + };
>> + };
>> +
>> + dphy: phy@5451000 {
>> + compatible = "allwinner,sun20i-d1-mipi-dphy",
>> + "allwinner,sun50i-a100-mipi-dphy";
>> + reg = <0x5451000 0x1000>;
>> + interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
>
> This is the same interrupt number as for the DSI controller above. Is
> that correct, and can the drivers handle that?

Yes, it is correct. Currently, neither driver uses the interrupt, so we
will just need to keep the sharing in mind if/when that happens.

Regards,
Samuel

2022-11-28 14:39:49

by Bin Meng

[permalink] [raw]

Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
>
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
>
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
>
> The devicetrees are organized to minimize duplication:
> - Common perhiperals are described in sunxi-d1s-t113.dtsi
> - DSP-related peripherals are described in sunxi-d1-t113.dtsi
> - RISC-V specific hardware is described in sun20i-d1s.dtsi
> - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
>
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v2:
> - Split into separate files for sharing with D1s/R528/T113
> - Use SOC_PERIPHERAL_IRQ macro for interrupts
> - Rename osc24M to dcxo and move the frequency to the board DTs
> - Drop analog LDOs due to the missing binding
> - Correct tcon_top DSI clock reference
> - Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
> - Add CPU OPP table
>
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++
> .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 +
> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 844 ++++++++++++++++++
> 4 files changed, 1001 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

<snip>

> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
> +
> +#include "sunxi-d1s-t113.dtsi"
> +
> +/ {
> + cpus {
> + timebase-frequency = <24000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = <&ccu CLK_RISCV>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <256>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + operating-points-v2 = <&opp_table_cpu>;
> + riscv,isa = "rv64imafdc";
> + #cooling-cells = <2>;
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + opp_table_cpu: opp-table-cpu {
> + compatible = "operating-points-v2";
> +
> + opp-408000000 {
> + opp-hz = /bits/ 64 <408000000>;
> + opp-microvolt = <900000 900000 1100000>;
> + };
> +
> + opp-1080000000 {
> + opp-hz = /bits/ 64 <1008000000>;
> + opp-microvolt = <900000 900000 1100000>;
> + };
> + };
> +
> + soc {
> + interrupt-parent = <&plic>;
> +
> + riscv_wdt: watchdog@6011000 {
> + compatible = "allwinner,sun20i-d1-wdt";
> + reg = <0x6011000 0x20>;
> + interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + };
> +
> + plic: interrupt-controller@10000000 {
> + compatible = "allwinner,sun20i-d1-plic",
> + "thead,c900-plic";
> + reg = <0x10000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu0_intc 9>;
> + interrupt-controller;
> + riscv,ndev = <176>;

The D1-H user manual says starting from interrupt number 176, interrupts are
CPUX related which I assume are CPU internal interrupts?

If yes, for external ones, valid interrupt source range is [1, 175]. And this
field should be 175, no?

> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + };
> + };
> +};

<snip>

Regards,
Bin

2022-11-28 21:26:56

[permalink] [raw]

Subject: Re: [PATCH v2 11/12] riscv: Add the Allwinner SoC family Kconfig option

Am Sonntag, 27. November 2022, 12:31:15 CET schrieb Guo Ren:
> On Sun, Nov 27, 2022 at 12:36 AM Conor Dooley <[email protected]> wrote:
> >
> > On Fri, Nov 25, 2022 at 05:46:55PM -0600, Samuel Holland wrote:
> > > Allwinner manufactures the sunxi family of application processors. This
> > > includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
> > > SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
> > >
> > > The first SoC in the sun20i series is D1, containing a single T-HEAD
> > > C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
> > >
> > > Most peripherals are shared across the entire chip family. In fact, the
> > > ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
> > > with the D1s.
> > >
> > > This means many existing device drivers can be reused. To facilitate
> > > this reuse, name the symbol ARCH_SUNXI, since that is what the existing
> > > drivers have as their dependency.
> > >
> > > Reviewed-by: Heiko Stuebner <[email protected]>
> > > Tested-by: Heiko Stuebner <[email protected]>
> > > Signed-off-by: Samuel Holland <[email protected]>
> > > ---
> > >
> > > Changes in v2:
> > > - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing
> > >
> > > arch/riscv/Kconfig.socs | 9 +++++++++
> > > 1 file changed, 9 insertions(+)
> > >
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index 69774bb362d6..4c1dc2ca11f9 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -26,6 +26,15 @@ config SOC_STARFIVE
> > > help
> > > This enables support for StarFive SoC platform hardware.
> > >
> > > +config ARCH_SUNXI
> > > + bool "Allwinner sun20i SoCs"
> > > + select ERRATA_THEAD if MMU && !XIP_KERNEL
>
> depend on MMU
> depend on !XIP_KERNEL
> select ERRATA_THEAD

That sounds like a better variant.

The D1 / C906 _needs_ the errata for the memory handling
and the other alternative constraints require the !XIP

With the select, a xip-kernel would not boot at all on a D1

Heiko

2022-11-28 21:27:46

[permalink] [raw]

Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

Am Samstag, 26. November 2022, 00:46:48 CET schrieb Samuel Holland:
> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
>
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
>
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
>
> The devicetrees are organized to minimize duplication:
> - Common perhiperals are described in sunxi-d1s-t113.dtsi
> - DSP-related peripherals are described in sunxi-d1-t113.dtsi
> - RISC-V specific hardware is described in sun20i-d1s.dtsi
> - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
>
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
>
> Signed-off-by: Samuel Holland <[email protected]>

While the overall dt looks good to me, it seems others did find
some minor issues. But I can at least provide a

Tested-by: Heiko Stuebner <[email protected]>

as it could sucessfully boot the Nezha variant of boards for me.

Heiko

2022-11-28 21:29:13

[permalink] [raw]

Subject: Re: [PATCH v2 06/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

Am Samstag, 26. November 2022, 00:46:50 CET schrieb Samuel Holland:
> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
> plus low-speed I/O from the SoC and a GPIO expander chip.
>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Tested-by: Conor Dooley <[email protected]>
> Tested-by: Heiko Stuebner <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>

just to confirm the tags above, the board still runs nicely.

Thanks
Heiko

2022-11-28 21:29:35

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

Am Samstag, 26. November 2022, 17:40:11 CET schrieb Conor Dooley:
> On Fri, Nov 25, 2022 at 05:46:56PM -0600, Samuel Holland wrote:
> > Now that several D1-based boards are supported, enable the platform in
> > our defconfig. Build in the drivers which are necessary to boot, such as
> > the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
> > and watchdog (which may be left enabled by the bootloader).
>
> All of that looks good.
>
> > Other common
> > onboard peripherals are enabled as modules.
>
> This I am not sure about though. I'll leave that to Palmer since I'm
> pretty sure it was him that said it, but I thought the plan was only
> turning on stuff required to boot to a console & things that are
> generally useful rather than enabling modules for everyone's "random"
> drivers. Palmer?

Isn't the defconfig meant as a starting point to get working systems
with minimal config effort? At least that was always the way to go on arm
so far :-) .

So having boot-required drivers built-in with the rest enabled as modules
for supported boards will allow people to boot theirs without headaches.

Disabling unneeded drivers if you're starved for storage space in a special
project is always easier than hunting down all the drivers to enable for a
specific board.

Heiko

> > Signed-off-by: Samuel Holland <[email protected]>
> > ---
> >
> > (no changes since v1)
> >
> > arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
> > 1 file changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index 05fd5fcf24f9..8dfe0550c0e6 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
> > CONFIG_EXPERT=y
> > # CONFIG_SYSFS_SYSCALL is not set
> > CONFIG_PROFILING=y
> > +CONFIG_ARCH_SUNXI=y
> > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_STARFIVE=y
> > @@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
> > CONFIG_MACB=y
> > CONFIG_E1000E=y
> > CONFIG_R8169=y
> > +CONFIG_STMMAC_ETH=m
> > CONFIG_MICROSEMI_PHY=y
> > CONFIG_INPUT_MOUSEDEV=y
> > +CONFIG_KEYBOARD_SUN4I_LRADC=m
> > CONFIG_SERIAL_8250=y
> > CONFIG_SERIAL_8250_CONSOLE=y
> > +CONFIG_SERIAL_8250_DW=y
> > CONFIG_SERIAL_OF_PLATFORM=y
> > CONFIG_VIRTIO_CONSOLE=y
> > CONFIG_HW_RANDOM=y
> > CONFIG_HW_RANDOM_VIRTIO=y
> > +CONFIG_I2C_MV64XXX=m
> > CONFIG_SPI=y
> > CONFIG_SPI_SIFIVE=y
> > +CONFIG_SPI_SUN6I=y
> > # CONFIG_PTP_1588_CLOCK is not set
> > -CONFIG_GPIOLIB=y
> > CONFIG_GPIO_SIFIVE=y
> > +CONFIG_WATCHDOG=y
> > +CONFIG_SUNXI_WATCHDOG=y
> > +CONFIG_REGULATOR=y
> > +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> > CONFIG_DRM=m
> > CONFIG_DRM_RADEON=m
> > CONFIG_DRM_NOUVEAU=m
> > +CONFIG_DRM_SUN4I=m
> > CONFIG_DRM_VIRTIO_GPU=m
> > CONFIG_FB=y
> > CONFIG_FRAMEBUFFER_CONSOLE=y
> > @@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
> > CONFIG_USB_OHCI_HCD_PLATFORM=y
> > CONFIG_USB_STORAGE=y
> > CONFIG_USB_UAS=y
> > +CONFIG_USB_MUSB_HDRC=m
> > +CONFIG_USB_MUSB_SUNXI=m
> > +CONFIG_NOP_USB_XCEIV=m
> > CONFIG_MMC=y
> > CONFIG_MMC_SDHCI=y
> > CONFIG_MMC_SDHCI_PLTFM=y
> > CONFIG_MMC_SDHCI_CADENCE=y
> > CONFIG_MMC_SPI=y
> > +CONFIG_MMC_SUNXI=y
> > CONFIG_RTC_CLASS=y
> > +CONFIG_RTC_DRV_SUN6I=y
> > +CONFIG_DMADEVICES=y
> > +CONFIG_DMA_SUN6I=m
> > CONFIG_VIRTIO_PCI=y
> > CONFIG_VIRTIO_BALLOON=y
> > CONFIG_VIRTIO_INPUT=y
> > CONFIG_VIRTIO_MMIO=y
> > +CONFIG_SUN8I_DE2_CCU=m
> > +CONFIG_SUN50I_IOMMU=y
> > CONFIG_RPMSG_CHAR=y
> > CONFIG_RPMSG_CTRL=y
> > CONFIG_RPMSG_VIRTIO=y
> > +CONFIG_PHY_SUN4I_USB=m
> > +CONFIG_NVMEM_SUNXI_SID=y
> > CONFIG_EXT4_FS=y
> > CONFIG_EXT4_FS_POSIX_ACL=y
> > CONFIG_EXT4_FS_SECURITY=y
>

2022-11-28 21:30:38

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

On 28/11/2022 21:11, Heiko Stübner wrote:
> Am Samstag, 26. November 2022, 17:40:11 CET schrieb Conor Dooley:
>> On Fri, Nov 25, 2022 at 05:46:56PM -0600, Samuel Holland wrote:
>>> Now that several D1-based boards are supported, enable the platform in
>>> our defconfig. Build in the drivers which are necessary to boot, such as
>>> the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
>>> and watchdog (which may be left enabled by the bootloader).
>>
>> All of that looks good.
>>
>>> Other common
>>> onboard peripherals are enabled as modules.
>>
>> This I am not sure about though. I'll leave that to Palmer since I'm
>> pretty sure it was him that said it, but I thought the plan was only
>> turning on stuff required to boot to a console & things that are
>> generally useful rather than enabling modules for everyone's "random"
>> drivers. Palmer?
>
> Isn't the defconfig meant as a starting point to get working systems
> with minimal config effort? At least that was always the way to go on arm
> so far :-) .
>
> So having boot-required drivers built-in with the rest enabled as modules
> for supported boards will allow people to boot theirs without headaches.
>
> Disabling unneeded drivers if you're starved for storage space in a special
> project is always easier than hunting down all the drivers to enable for a
> specific board.

I wouldn't mind being able to turn on all the PolarFire SoC stuff and
yeah, that would be the way that arm64 does it. But I do recall hearing
that I should not turn stuff on this way, when I initially tried to
turn stuff on via selects, got a nack and asked if I could do this instead.

But it may be that I misremember, which is why I appealed to the Higher
Powers for clarification :)

2022-11-29 07:04:39

by Andrew Jones

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

On Mon, Nov 28, 2022 at 09:17:38PM +0000, Conor Dooley wrote:
> On 28/11/2022 21:11, Heiko St?bner wrote:
> > Am Samstag, 26. November 2022, 17:40:11 CET schrieb Conor Dooley:
> >> On Fri, Nov 25, 2022 at 05:46:56PM -0600, Samuel Holland wrote:
> >>> Now that several D1-based boards are supported, enable the platform in
> >>> our defconfig. Build in the drivers which are necessary to boot, such as
> >>> the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
> >>> and watchdog (which may be left enabled by the bootloader).
> >>
> >> All of that looks good.
> >>
> >>> Other common
> >>> onboard peripherals are enabled as modules.
> >>
> >> This I am not sure about though. I'll leave that to Palmer since I'm
> >> pretty sure it was him that said it, but I thought the plan was only
> >> turning on stuff required to boot to a console & things that are
> >> generally useful rather than enabling modules for everyone's "random"
> >> drivers. Palmer?
> >
> > Isn't the defconfig meant as a starting point to get working systems
> > with minimal config effort? At least that was always the way to go on arm
> > so far :-) .
> >
> > So having boot-required drivers built-in with the rest enabled as modules
> > for supported boards will allow people to boot theirs without headaches.
> >
> > Disabling unneeded drivers if you're starved for storage space in a special
> > project is always easier than hunting down all the drivers to enable for a
> > specific board.
>
> I wouldn't mind being able to turn on all the PolarFire SoC stuff and
> yeah, that would be the way that arm64 does it. But I do recall hearing
> that I should not turn stuff on this way, when I initially tried to
> turn stuff on via selects, got a nack and asked if I could do this instead.
>
> But it may be that I misremember, which is why I appealed to the Higher
> Powers for clarification :)

FWIW, I don't worry too much about modules in defconfig because I always
immediately apply a 'LSMOD=$PWD/L localmodconfig' to it, where the L
file is an lsmod output which only includes modules I need.

Thanks,
drew

>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv

2022-11-29 07:05:12

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

On 29 November 2022 06:49:25 GMT, Andrew Jones <[email protected]> wrote:
>On Mon, Nov 28, 2022 at 09:17:38PM +0000, Conor Dooley wrote:
>> On 28/11/2022 21:11, Heiko Stübner wrote:
>> > Am Samstag, 26. November 2022, 17:40:11 CET schrieb Conor Dooley:
>> >> On Fri, Nov 25, 2022 at 05:46:56PM -0600, Samuel Holland wrote:
>> >>> Now that several D1-based boards are supported, enable the platform in
>> >>> our defconfig. Build in the drivers which are necessary to boot, such as
>> >>> the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
>> >>> and watchdog (which may be left enabled by the bootloader).
>> >>
>> >> All of that looks good.
>> >>
>> >>> Other common
>> >>> onboard peripherals are enabled as modules.
>> >>
>> >> This I am not sure about though. I'll leave that to Palmer since I'm
>> >> pretty sure it was him that said it, but I thought the plan was only
>> >> turning on stuff required to boot to a console & things that are
>> >> generally useful rather than enabling modules for everyone's "random"
>> >> drivers. Palmer?
>> >
>> > Isn't the defconfig meant as a starting point to get working systems
>> > with minimal config effort? At least that was always the way to go on arm
>> > so far :-) .
>> >
>> > So having boot-required drivers built-in with the rest enabled as modules
>> > for supported boards will allow people to boot theirs without headaches.
>> >
>> > Disabling unneeded drivers if you're starved for storage space in a special
>> > project is always easier than hunting down all the drivers to enable for a
>> > specific board.
>>
>> I wouldn't mind being able to turn on all the PolarFire SoC stuff and
>> yeah, that would be the way that arm64 does it. But I do recall hearing
>> that I should not turn stuff on this way, when I initially tried to
>> turn stuff on via selects, got a nack and asked if I could do this instead.
>>
>> But it may be that I misremember, which is why I appealed to the Higher
>> Powers for clarification :)
>
>FWIW, I don't worry too much about modules in defconfig because I always
>immediately apply a 'LSMOD=$PWD/L localmodconfig' to it, where the L
>file is an lsmod output which only includes modules I need.

idk, defconfig to me is not about you or I, it's about A Developer that gets an SBC or a devkit and their experience.
Or alternatively, someone's CI ;)
I'd like to put everything in, but I recall that being shot down, that's all.

2022-11-30 21:05:13

by Palmer Dabbelt

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

On Mon, 28 Nov 2022 22:54:18 PST (-0800), Conor Dooley wrote:
>
>
> On 29 November 2022 06:49:25 GMT, Andrew Jones <[email protected]> wrote:
>>On Mon, Nov 28, 2022 at 09:17:38PM +0000, Conor Dooley wrote:
>>> On 28/11/2022 21:11, Heiko Stübner wrote:
>>> > Am Samstag, 26. November 2022, 17:40:11 CET schrieb Conor Dooley:
>>> >> On Fri, Nov 25, 2022 at 05:46:56PM -0600, Samuel Holland wrote:
>>> >>> Now that several D1-based boards are supported, enable the platform in
>>> >>> our defconfig. Build in the drivers which are necessary to boot, such as
>>> >>> the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
>>> >>> and watchdog (which may be left enabled by the bootloader).
>>> >>
>>> >> All of that looks good.
>>> >>
>>> >>> Other common
>>> >>> onboard peripherals are enabled as modules.
>>> >>
>>> >> This I am not sure about though. I'll leave that to Palmer since I'm
>>> >> pretty sure it was him that said it, but I thought the plan was only
>>> >> turning on stuff required to boot to a console & things that are
>>> >> generally useful rather than enabling modules for everyone's "random"
>>> >> drivers. Palmer?
>>> >
>>> > Isn't the defconfig meant as a starting point to get working systems
>>> > with minimal config effort? At least that was always the way to go on arm
>>> > so far :-) .
>>> >
>>> > So having boot-required drivers built-in with the rest enabled as modules
>>> > for supported boards will allow people to boot theirs without headaches.
>>> >
>>> > Disabling unneeded drivers if you're starved for storage space in a special
>>> > project is always easier than hunting down all the drivers to enable for a
>>> > specific board.
>>>
>>> I wouldn't mind being able to turn on all the PolarFire SoC stuff and
>>> yeah, that would be the way that arm64 does it. But I do recall hearing
>>> that I should not turn stuff on this way, when I initially tried to
>>> turn stuff on via selects, got a nack and asked if I could do this instead.
>>>
>>> But it may be that I misremember, which is why I appealed to the Higher
>>> Powers for clarification :)
>>
>>FWIW, I don't worry too much about modules in defconfig because I always
>>immediately apply a 'LSMOD=$PWD/L localmodconfig' to it, where the L
>>file is an lsmod output which only includes modules I need.
>
> idk, defconfig to me is not about you or I, it's about A Developer that gets an SBC or a devkit and their experience.
> Or alternatively, someone's CI ;)
> I'd like to put everything in, but I recall that being shot down, that's all.

The whole "who is defconfig for" discussion always ends up kind of
vague, but IIUC it's generally aimed at kernel hackers as opposed to end
users -- so it's not meant to be a disto config, that's why we have
things like the debug options turned on. I tend to think of it as a "if
a patch submitter is going to test only one config, then what do I want
in it?" and let that determine what goes in defconfig.

IMO having defconfig contain the drivers necessary to boot every common
dev board as =y, and having =m for anything else on those boards also
seem reasonable. That will make the transition from vendor/distro
kernels to upstream a bit smoother, which is always good. I guess
there's some slight build time and image size issues, but aside from
some very small systems that shouldn't be too bad for kernel developers
-- and if we really end up with another popular system with 6MiB of RAM
we can just stick another tiny defconfig in there for it.

I actually don't use modules when doing kernel development because I
find it easier to track things when they're packed into a single binary,
but I don't think it's necessary to steer everyone that way.

Adding some of the Arm folks here, in case they have thoughts. The best
bet is probably to try and do something similar, though my worry is that
the answer is something like "target standard platforms" and we don't
have any.

2022-11-30 22:13:03

by Arnd Bergmann

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

On Wed, Nov 30, 2022, at 21:24, Palmer Dabbelt wrote:
> On Mon, 28 Nov 2022 22:54:18 PST (-0800), Conor Dooley wrote:
>>
>> idk, defconfig to me is not about you or I, it's about A Developer that gets an SBC or a devkit and their experience.
>> Or alternatively, someone's CI ;)
>> I'd like to put everything in, but I recall that being shot down, that's all.
>
> The whole "who is defconfig for" discussion always ends up kind of
> vague, but IIUC it's generally aimed at kernel hackers as opposed to end
> users -- so it's not meant to be a disto config, that's why we have
> things like the debug options turned on. I tend to think of it as a "if
> a patch submitter is going to test only one config, then what do I want
> in it?" and let that determine what goes in defconfig.
>
> IMO having defconfig contain the drivers necessary to boot every common
> dev board as =y, and having =m for anything else on those boards also
> seem reasonable. That will make the transition from vendor/distro
> kernels to upstream a bit smoother, which is always good. I guess
> there's some slight build time and image size issues, but aside from
> some very small systems that shouldn't be too bad for kernel developers
> -- and if we really end up with another popular system with 6MiB of RAM
> we can just stick another tiny defconfig in there for it.
>
> I actually don't use modules when doing kernel development because I
> find it easier to track things when they're packed into a single binary,
> but I don't think it's necessary to steer everyone that way.
>
> Adding some of the Arm folks here, in case they have thoughts. The best
> bet is probably to try and do something similar, though my worry is that
> the answer is something like "target standard platforms" and we don't
> have any.

I think this is handled very inconsistently across architectures. On
32-bit arm, we used to have a board specific defconfig for each machine,
but of course that never scaled to the number of supported machines.

The important defconfig files we have these days are the arm64
one, and on arm32 we have the ones that are mutually incompatible,
in particular one for armv7 and one for armv5, each enabling as
many machines as possible, plus usually one per SoC vendor that
is more specialized.

If you want to formalize it a bit more than this, I would recommend
having more fragments, e.g. one for typical debugging options,
one for things that are needed to boot both Fedora and Debian
userland, etc.

Arnd

2022-12-01 00:59:19

by Andre Przywara

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

On Wed, 30 Nov 2022 12:24:08 -0800 (PST)
Palmer Dabbelt <[email protected]> wrote:

Hi,

> On Mon, 28 Nov 2022 22:54:18 PST (-0800), Conor Dooley wrote:
> >
> >
> > On 29 November 2022 06:49:25 GMT, Andrew Jones <[email protected]> wrote:
> >>On Mon, Nov 28, 2022 at 09:17:38PM +0000, Conor Dooley wrote:
> >>> On 28/11/2022 21:11, Heiko Stübner wrote:
> >>> > Am Samstag, 26. November 2022, 17:40:11 CET schrieb Conor Dooley:
> >>> >> On Fri, Nov 25, 2022 at 05:46:56PM -0600, Samuel Holland wrote:
> >>> >>> Now that several D1-based boards are supported, enable the platform in
> >>> >>> our defconfig. Build in the drivers which are necessary to boot, such as
> >>> >>> the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
> >>> >>> and watchdog (which may be left enabled by the bootloader).
> >>> >>
> >>> >> All of that looks good.
> >>> >>
> >>> >>> Other common
> >>> >>> onboard peripherals are enabled as modules.
> >>> >>
> >>> >> This I am not sure about though. I'll leave that to Palmer since I'm
> >>> >> pretty sure it was him that said it, but I thought the plan was only
> >>> >> turning on stuff required to boot to a console & things that are
> >>> >> generally useful rather than enabling modules for everyone's "random"
> >>> >> drivers. Palmer?
> >>> >
> >>> > Isn't the defconfig meant as a starting point to get working systems
> >>> > with minimal config effort? At least that was always the way to go on arm
> >>> > so far :-) .
> >>> >
> >>> > So having boot-required drivers built-in with the rest enabled as modules
> >>> > for supported boards will allow people to boot theirs without headaches.
> >>> >
> >>> > Disabling unneeded drivers if you're starved for storage space in a special
> >>> > project is always easier than hunting down all the drivers to enable for a
> >>> > specific board.
> >>>
> >>> I wouldn't mind being able to turn on all the PolarFire SoC stuff and
> >>> yeah, that would be the way that arm64 does it. But I do recall hearing
> >>> that I should not turn stuff on this way, when I initially tried to
> >>> turn stuff on via selects, got a nack and asked if I could do this instead.
> >>>
> >>> But it may be that I misremember, which is why I appealed to the Higher
> >>> Powers for clarification :)
> >>
> >>FWIW, I don't worry too much about modules in defconfig because I always
> >>immediately apply a 'LSMOD=$PWD/L localmodconfig' to it, where the L
> >>file is an lsmod output which only includes modules I need.
> >
> > idk, defconfig to me is not about you or I, it's about A Developer that gets an SBC or a devkit and their experience.
> > Or alternatively, someone's CI ;)
> > I'd like to put everything in, but I recall that being shot down, that's all.
>
> The whole "who is defconfig for" discussion always ends up kind of
> vague, but IIUC it's generally aimed at kernel hackers as opposed to end
> users -- so it's not meant to be a disto config, that's why we have
> things like the debug options turned on. I tend to think of it as a "if
> a patch submitter is going to test only one config, then what do I want
> in it?" and let that determine what goes in defconfig.

Yes, this is also the guideline for arm64. On top of that it's supposed
to be a sane common config to be used to reproduce bugs. A common
question from maintainers is "Does it happen with defconfig?". If not,
what does it take on top of defconfig to get there?
The idea is that people can run the same config and thus the same image
on *their* boards, regardless of the particular platform.

> IMO having defconfig contain the drivers necessary to boot every common
> dev board as =y, and having =m for anything else on those boards also
> seem reasonable. That will make the transition from vendor/distro
> kernels to upstream a bit smoother, which is always good. I guess
> there's some slight build time and image size issues, but aside from
> some very small systems that shouldn't be too bad for kernel developers
> -- and if we really end up with another popular system with 6MiB of RAM
> we can just stick another tiny defconfig in there for it.
>
> I actually don't use modules when doing kernel development because I
> find it easier to track things when they're packed into a single binary,

Originally arm64 included most drivers as [=y], but this grew too big
quickly, so it was scaled back to be able to boot from the board's mass
storage (SD card, SATA, NVMe), with non-essential drivers included as
modules. And yes, most people just build and use the Image, which keeps
the build effort reasonable.
Also required features to make systemd happy, and to enable other core
distro features, were included, so that such kernels can boot distro
userland without losing significant functionality.

> but I don't think it's necessary to steer everyone that way.
>
> Adding some of the Arm folks here, in case they have thoughts. The best
> bet is probably to try and do something similar, though my worry is that
> the answer is something like "target standard platforms" and we don't
> have any.

No such thing on arm64 either :-(

Cheers,
Andre

2022-12-02 08:33:55

by Icenowy Zheng

[permalink] [raw]

Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

在 2022-11-26星期六的 16:03 +0000，Conor Dooley写道：
> On Fri, Nov 25, 2022 at 05:46:48PM -0600, Samuel Holland wrote:
> > D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs
> > based
> > on a single die, or at a pair of dies derived from the same design.
> >
> > D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528
> > and
> > T113 contain a pair of Cortex-A7's.
>
> Is this "additionally contain" or a case of the D1 is the R528 but
> with
> s/arm/riscv/? It's the latter, right?

Technically they're the same die, but the CPU cores are selectively
enabled, and at least what Allwinner says is that D1 contains only RV
and R528 contains only ARM.

>
> > D1 and R528 are the full version of
> > the chip with a BGA package, whereas D1s and T113 are low-pin-count
> > QFP
> > variants.
> >
> > Because the original design supported both ARM and RISC-V CPUs,
> > some
> > peripherals are duplicated. In addition, all variants except D1s
> > contain
> > a HiFi 4 DSP with its own set of peripherals.
> >
> > The devicetrees are organized to minimize duplication:
> > - Common perhiperals are described in sunxi-d1s-t113.dtsi
> > - DSP-related peripherals are described in sunxi-d1-t113.dtsi
> > - RISC-V specific hardware is described in sun20i-d1s.dtsi
> > - Functionality unique to the D1 variant is described in sun20i-
> > d1.dtsi
> >
> > The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> > values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
>
> Modulo the warnings I replied to the cover with & one minor comment
> below:
> Reviewed-by: Conor Dooley <[email protected]>
>
> > Signed-off-by: Samuel Holland <[email protected]>
> > ---
> >
> > Changes in v2:
> > - Split into separate files for sharing with D1s/R528/T113
> > - Use SOC_PERIPHERAL_IRQ macro for interrupts
> > - Rename osc24M to dcxo and move the frequency to the board DTs
> > - Drop analog LDOs due to the missing binding
> > - Correct tcon_top DSI clock reference
> > - Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
> > - Add CPU OPP table
> >
> > arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++
> > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++
> > .../boot/dts/allwinner/sunxi-d1-t113.dtsi     | 15 +
> > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 844
> > ++++++++++++++++++
> > 4 files changed, 1001 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-
> > t113.dtsi
> > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-
> > t113.dtsi
>
>
> > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > new file mode 100644
> > index 000000000000..c8815cbf0b46
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > @@ -0,0 +1,844 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> > +
> > +#include <dt-bindings/clock/sun6i-rtc.h>
> > +#include <dt-bindings/clock/sun8i-de2.h>
> > +#include <dt-bindings/clock/sun8i-tcon-top.h>
> > +#include <dt-bindings/clock/sun20i-d1-ccu.h>
> > +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/reset/sun8i-de2.h>
> > +#include <dt-bindings/reset/sun20i-d1-ccu.h>
> > +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
> > +
> > +/ {
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +
> > +       dcxo: dcxo-clk {
> > +               compatible = "fixed-clock";
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
>
> Since this is a "must", can you drop the clock-frequency = <0> here
> so
> that if someone doesn't override it in their board dt-validate
> complains?
>
> Thanks,
> Conor.
>
> > +               clock-output-names = "dcxo";
> > +               #clock-cells = <0>;
> > +       };
> > +
>
>

2022-12-02 08:47:37

by Icenowy Zheng

[permalink] [raw]

Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

在 2022-11-26星期六的 08:24 +0800，Guo Ren写道：
> On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <[email protected]>
> wrote:
> >
> > Now that several D1-based boards are supported, enable the platform
> > in
> > our defconfig. Build in the drivers which are necessary to boot,
> > such as
> > the pinctrl, MMC, RTC (which provides critical clocks), SPI (for
> > flash),
> > and watchdog (which may be left enabled by the bootloader). Other
> > common
> > onboard peripherals are enabled as modules.
> >
> > Signed-off-by: Samuel Holland <[email protected]>
> > ---
> >
> > (no changes since v1)
> >
> > arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
> > 1 file changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/configs/defconfig
> > b/arch/riscv/configs/defconfig
> > index 05fd5fcf24f9..8dfe0550c0e6 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
> > CONFIG_EXPERT=y
> > # CONFIG_SYSFS_SYSCALL is not set
> > CONFIG_PROFILING=y
> > +CONFIG_ARCH_SUNXI=y
> > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_STARFIVE=y
> > @@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
> > CONFIG_MACB=y
> > CONFIG_E1000E=y
> > CONFIG_R8169=y
> > +CONFIG_STMMAC_ETH=m
> > CONFIG_MICROSEMI_PHY=y
> > CONFIG_INPUT_MOUSEDEV=y
> > +CONFIG_KEYBOARD_SUN4I_LRADC=m
> > CONFIG_SERIAL_8250=y
> > CONFIG_SERIAL_8250_CONSOLE=y
> > +CONFIG_SERIAL_8250_DW=y
> > CONFIG_SERIAL_OF_PLATFORM=y
> > CONFIG_VIRTIO_CONSOLE=y
> > CONFIG_HW_RANDOM=y
> > CONFIG_HW_RANDOM_VIRTIO=y
> > +CONFIG_I2C_MV64XXX=m
> > CONFIG_SPI=y
> > CONFIG_SPI_SIFIVE=y
> > +CONFIG_SPI_SUN6I=y
> > # CONFIG_PTP_1588_CLOCK is not set
> > -CONFIG_GPIOLIB=y
> > CONFIG_GPIO_SIFIVE=y
> > +CONFIG_WATCHDOG=y
> > +CONFIG_SUNXI_WATCHDOG=y
> > +CONFIG_REGULATOR=y
> > +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> > CONFIG_DRM=m
> > CONFIG_DRM_RADEON=m
> > CONFIG_DRM_NOUVEAU=m
> > +CONFIG_DRM_SUN4I=m
> > CONFIG_DRM_VIRTIO_GPU=m
> > CONFIG_FB=y
> > CONFIG_FRAMEBUFFER_CONSOLE=y
> > @@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
> > CONFIG_USB_OHCI_HCD_PLATFORM=y
> > CONFIG_USB_STORAGE=y
> > CONFIG_USB_UAS=y
> > +CONFIG_USB_MUSB_HDRC=m
> > +CONFIG_USB_MUSB_SUNXI=m
> > +CONFIG_NOP_USB_XCEIV=m
> > CONFIG_MMC=y
> > CONFIG_MMC_SDHCI=y
> > CONFIG_MMC_SDHCI_PLTFM=y
> > CONFIG_MMC_SDHCI_CADENCE=y
> > CONFIG_MMC_SPI=y
> > +CONFIG_MMC_SUNXI=y
> > CONFIG_RTC_CLASS=y
> > +CONFIG_RTC_DRV_SUN6I=y
> > +CONFIG_DMADEVICES=y
> > +CONFIG_DMA_SUN6I=m
> > CONFIG_VIRTIO_PCI=y
> > CONFIG_VIRTIO_BALLOON=y
> > CONFIG_VIRTIO_INPUT=y
> > CONFIG_VIRTIO_MMIO=y
> > +CONFIG_SUN8I_DE2_CCU=m
> > +CONFIG_SUN50I_IOMMU=y
> Do we need IOMMU?

It's utilized by some peripherals, e.g. the display engine.

>
> Others:
> Reviewed-by: Guo Ren <[email protected]>
>
> > CONFIG_RPMSG_CHAR=y
> > CONFIG_RPMSG_CTRL=y
> > CONFIG_RPMSG_VIRTIO=y
> > +CONFIG_PHY_SUN4I_USB=m
> > +CONFIG_NVMEM_SUNXI_SID=y
> > CONFIG_EXT4_FS=y
> > CONFIG_EXT4_FS_POSIX_ACL=y
> > CONFIG_EXT4_FS_SECURITY=y
> > --
> > 2.37.4
> >
>
>

2022-12-02 09:23:53

by Icenowy Zheng

[permalink] [raw]

Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

在 2022-11-27星期日的 17:41 +0000，Andre Przywara写道：
> On Fri, 25 Nov 2022 17:46:48 -0600
> Samuel Holland <[email protected]> wrote:
>
> > D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs
> > based
> > on a single die, or at a pair of dies derived from the same design.
> >
> > D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528
> > and
> > T113 contain a pair of Cortex-A7's. D1 and R528 are the full
> > version of
> > the chip with a BGA package, whereas D1s and T113 are low-pin-count
> > QFP
> > variants.
> >
> > Because the original design supported both ARM and RISC-V CPUs,
> > some
> > peripherals are duplicated. In addition, all variants except D1s
> > contain
> > a HiFi 4 DSP with its own set of peripherals.
> >
> > The devicetrees are organized to minimize duplication:
> > - Common perhiperals are described in sunxi-d1s-t113.dtsi
>
> So I compared all the reg and interrupts properties against the T113
> manual, they match, as far as they are described there. The
> undocumented
> rest matches what we already have in other SoCs.
>
> I noticed two things, though, mentioned inline below:
>
> > - DSP-related peripherals are described in sunxi-d1-t113.dtsi
> > - RISC-V specific hardware is described in sun20i-d1s.dtsi
> > - Functionality unique to the D1 variant is described in sun20i-
> > d1.dtsi
> >
> > The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> > values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
> >
> > Signed-off-by: Samuel Holland <[email protected]>
> > ---
> >
> > Changes in v2:
> > - Split into separate files for sharing with D1s/R528/T113
> > - Use SOC_PERIPHERAL_IRQ macro for interrupts
> > - Rename osc24M to dcxo and move the frequency to the board DTs
> > - Drop analog LDOs due to the missing binding
> > - Correct tcon_top DSI clock reference
> > - Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
> > - Add CPU OPP table
> >
> > arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++
> > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++
> > .../boot/dts/allwinner/sunxi-d1-t113.dtsi     | 15 +
> > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 844
> > ++++++++++++++++++
> > 4 files changed, 1001 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-
> > t113.dtsi
> > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-
> > t113.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> > b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> > new file mode 100644
> > index 000000000000..97e7cbb32597
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> > @@ -0,0 +1,66 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> > +
> > +#include "sun20i-d1s.dtsi"
> > +#include "sunxi-d1-t113.dtsi"
> > +
> > +/ {
> > +       soc {
> > +               lradc: keys@2009800 {
> > +                       compatible = "allwinner,sun20i-d1-lradc",
> > +                                    "allwinner,sun50i-r329-lradc";
> > +                       reg = <0x2009800 0x400>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(61)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_LRADC>;
> > +                       resets = <&ccu RST_BUS_LRADC>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2s0: i2s@2032000 {
> > +                       compatible = "allwinner,sun20i-d1-i2s",
> > +                                    "allwinner,sun50i-r329-i2s";
> > +                       reg = <0x2032000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(26)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_I2S0>,
> > +                                <&ccu CLK_I2S0>;
> > +                       clock-names = "apb", "mod";
> > +                       resets = <&ccu RST_BUS_I2S0>;
> > +                       dmas = <&dma 3>, <&dma 3>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +                       #sound-dai-cells = <0>;
> > +               };
> > +       };
> > +};
> > +
> > +&pio {
> > +       /omit-if-no-ref/
> > +       dmic_pb11_d0_pin: dmic-pb11-d0-pin {
> > +               pins = "PB11";
> > +               function = "dmic";
> > +       };
> > +
> > +       /omit-if-no-ref/
> > +       dmic_pe17_clk_pin: dmic-pe17-clk-pin {
> > +               pins = "PE17";
> > +               function = "dmic";
> > +       };
> > +
> > +       /omit-if-no-ref/
> > +       i2c0_pb10_pins: i2c0-pb10-pins {
> > +               pins = "PB10", "PB11";
> > +               function = "i2c0";
> > +       };
> > +
> > +       /omit-if-no-ref/
> > +       i2c2_pb0_pins: i2c2-pb0-pins {
> > +               pins = "PB0", "PB1";
> > +               function = "i2c2";
> > +       };
> > +
> > +       /omit-if-no-ref/
> > +       uart0_pb8_pins: uart0-pb8-pins {
> > +               pins = "PB8", "PB9";
> > +               function = "uart0";
> > +       };
> > +};
> > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > new file mode 100644
> > index 000000000000..859509832d58
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > @@ -0,0 +1,76 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> > +
> > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
> > +
> > +#include "sunxi-d1s-t113.dtsi"
> > +
> > +/ {
> > +       cpus {
> > +               timebase-frequency = <24000000>;
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "thead,c906", "riscv";
> > +                       device_type = "cpu";
> > +                       reg = <0>;
> > +                       clocks = <&ccu CLK_RISCV>;
> > +                       d-cache-block-size = <64>;
> > +                       d-cache-sets = <256>;
> > +                       d-cache-size = <32768>;
> > +                       i-cache-block-size = <64>;
> > +                       i-cache-sets = <128>;
> > +                       i-cache-size = <32768>;
> > +                       mmu-type = "riscv,sv39";
> > +                       operating-points-v2 = <&opp_table_cpu>;
> > +                       riscv,isa = "rv64imafdc";
> > +                       #cooling-cells = <2>;
> > +
> > +                       cpu0_intc: interrupt-controller {
> > +                               compatible = "riscv,cpu-intc";
> > +                               interrupt-controller;
> > +                               #address-cells = <0>;
> > +                               #interrupt-cells = <1>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       opp_table_cpu: opp-table-cpu {
> > +               compatible = "operating-points-v2";
> > +
> > +               opp-408000000 {
> > +                       opp-hz = /bits/ 64 <408000000>;
> > +                       opp-microvolt = <900000 900000 1100000>;
> > +               };
> > +
> > +               opp-1080000000 {
> > +                       opp-hz = /bits/ 64 <1008000000>;
> > +                       opp-microvolt = <900000 900000 1100000>;
> > +               };
> > +       };
> > +
> > +       soc {
> > +               interrupt-parent = <&plic>;
> > +
> > +               riscv_wdt: watchdog@6011000 {
> > +                       compatible = "allwinner,sun20i-d1-wdt";
> > +                       reg = <0x6011000 0x20>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(131)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> > +                       clock-names = "hosc", "losc";
> > +               };
> > +
> > +               plic: interrupt-controller@10000000 {
> > +                       compatible = "allwinner,sun20i-d1-plic",
> > +                                    "thead,c900-plic";
> > +                       reg = <0x10000000 0x4000000>;
> > +                       interrupts-extended = <&cpu0_intc 11>,
> > +                                             <&cpu0_intc 9>;
> > +                       interrupt-controller;
> > +                       riscv,ndev = <176>;
> > +                       #address-cells = <0>;
> > +                       #interrupt-cells = <2>;
> > +               };
> > +       };
> > +};
> > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> > b/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> > new file mode 100644
> > index 000000000000..b7156123df54
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> > @@ -0,0 +1,15 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> > +
> > +/ {
> > +       soc {
> > +               dsp_wdt: watchdog@1700400 {
> > +                       compatible = "allwinner,sun20i-d1-wdt";
> > +                       reg = <0x1700400 0x20>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(122)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> > +                       clock-names = "hosc", "losc";
> > +                       status = "reserved";
> > +               };
> > +       };
> > +};
> > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > new file mode 100644
> > index 000000000000..c8815cbf0b46
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > @@ -0,0 +1,844 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> > +
> > +#include <dt-bindings/clock/sun6i-rtc.h>
> > +#include <dt-bindings/clock/sun8i-de2.h>
> > +#include <dt-bindings/clock/sun8i-tcon-top.h>
> > +#include <dt-bindings/clock/sun20i-d1-ccu.h>
> > +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/reset/sun8i-de2.h>
> > +#include <dt-bindings/reset/sun20i-d1-ccu.h>
> > +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
> > +
> > +/ {
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +
> > +       dcxo: dcxo-clk {
> > +               compatible = "fixed-clock";
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +               clock-output-names = "dcxo";
> > +               #clock-cells = <0>;
> > +       };
> > +
> > +       de: display-engine {
> > +               compatible = "allwinner,sun20i-d1-display-engine";
> > +               allwinner,pipelines = <&mixer0>, <&mixer1>;
> > +               status = "disabled";
> > +       };
> > +
> > +       soc {
> > +               compatible = "simple-bus";
> > +               ranges;
> > +               dma-noncoherent;
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +
> > +               pio: pinctrl@2000000 {
> > +                       compatible = "allwinner,sun20i-d1-pinctrl";
> > +                       reg = <0x2000000 0x800>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(69)
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <SOC_PERIPHERAL_IRQ(71)
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <SOC_PERIPHERAL_IRQ(73)
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <SOC_PERIPHERAL_IRQ(75)
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <SOC_PERIPHERAL_IRQ(77)
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <SOC_PERIPHERAL_IRQ(79)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_APB0>,
> > +                                <&dcxo>,
> > +                                <&rtc CLK_OSC32K>;
> > +                       clock-names = "apb", "hosc", "losc";
> > +                       gpio-controller;
> > +                       interrupt-controller;
> > +                       #gpio-cells = <3>;
> > +                       #interrupt-cells = <3>;
> > +
> > +                       /omit-if-no-ref/
> > +                       clk_pg11_pin: clk-pg11-pin {
> > +                               pins = "PG11";
> > +                               function = "clk";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       dsi_4lane_pins: dsi-4lane-pins {
> > +                               pins = "PD0", "PD1", "PD2", "PD3",
> > "PD4", "PD5",
> > +                                      "PD6", "PD7", "PD8", "PD9";
> > +                               drive-strength = <30>;
> > +                               function = "dsi";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       lcd_rgb666_pins: lcd-rgb666-pins {
> > +                               pins = "PD0", "PD1", "PD2", "PD3",
> > "PD4", "PD5",
> > +                                      "PD6", "PD7", "PD8", "PD9",
> > "PD10", "PD11",
> > +                                      "PD12", "PD13", "PD14",
> > "PD15", "PD16", "PD17",
> > +                                      "PD18", "PD19", "PD20",
> > "PD21";
> > +                               function = "lcd0";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       mmc0_pins: mmc0-pins {
> > +                               pins = "PF0", "PF1", "PF2", "PF3",
> > "PF4", "PF5";
> > +                               function = "mmc0";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       mmc1_pins: mmc1-pins {
> > +                               pins = "PG0", "PG1", "PG2", "PG3",
> > "PG4", "PG5";
> > +                               function = "mmc1";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       mmc2_pins: mmc2-pins {
> > +                               pins = "PC2", "PC3", "PC4", "PC5",
> > "PC6", "PC7";
> > +                               function = "mmc2";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       rgmii_pe_pins: rgmii-pe-pins {
> > +                               pins = "PE0", "PE1", "PE2", "PE3",
> > "PE4",
> > +                                      "PE5", "PE6", "PE7", "PE8",
> > "PE9",
> > +                                      "PE11", "PE12", "PE13",
> > "PE14", "PE15";
> > +                               function = "emac";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       rmii_pe_pins: rmii-pe-pins {
> > +                               pins = "PE0", "PE1", "PE2", "PE3",
> > "PE4",
> > +                                      "PE5", "PE6", "PE7", "PE8",
> > "PE9";
> > +                               function = "emac";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       uart1_pg6_pins: uart1-pg6-pins {
> > +                               pins = "PG6", "PG7";
> > +                               function = "uart1";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-
> > pins {
> > +                               pins = "PG8", "PG9";
> > +                               function = "uart1";
> > +                       };
> > +
> > +                       /omit-if-no-ref/
> > +                       uart3_pb_pins: uart3-pb-pins {
> > +                               pins = "PB6", "PB7";
> > +                               function = "uart3";
> > +                       };
> > +               };
> > +
> > +               ccu: clock-controller@2001000 {
> > +                       compatible = "allwinner,sun20i-d1-ccu";
> > +                       reg = <0x2001000 0x1000>;
> > +                       clocks = <&dcxo>,
> > +                                <&rtc CLK_OSC32K>,
> > +                                <&rtc CLK_IOSC>;
> > +                       clock-names = "hosc", "losc", "iosc";
> > +                       #clock-cells = <1>;
> > +                       #reset-cells = <1>;
> > +               };
> > +
> > +               dmic: dmic@2031000 {
> > +                       compatible = "allwinner,sun20i-d1-dmic",
> > +                                    "allwinner,sun50i-h6-dmic";
> > +                       reg = <0x2031000 0x400>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(24)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_DMIC>,
> > +                                <&ccu CLK_DMIC>;
> > +                       clock-names = "bus", "mod";
> > +                       resets = <&ccu RST_BUS_DMIC>;
> > +                       dmas = <&dma 8>;
> > +                       dma-names = "rx";
> > +                       status = "disabled";
> > +                       #sound-dai-cells = <0>;
> > +               };
> > +
> > +               i2s1: i2s@2033000 {
> > +                       compatible = "allwinner,sun20i-d1-i2s",
> > +                                    "allwinner,sun50i-r329-i2s";
> > +                       reg = <0x2033000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(27)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_I2S1>,
> > +                                <&ccu CLK_I2S1>;
> > +                       clock-names = "apb", "mod";
> > +                       resets = <&ccu RST_BUS_I2S1>;
> > +                       dmas = <&dma 4>, <&dma 4>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +                       #sound-dai-cells = <0>;
> > +               };
> > +
> > +               i2s2: i2s@2034000 {
> > +                       compatible = "allwinner,sun20i-d1-i2s",
> > +                                    "allwinner,sun50i-r329-i2s";
> > +                       reg = <0x2034000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(28)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_I2S2>,
> > +                                <&ccu CLK_I2S2>;
> > +                       clock-names = "apb", "mod";
> > +                       resets = <&ccu RST_BUS_I2S2>;
> > +                       dmas = <&dma 5>, <&dma 5>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +                       #sound-dai-cells = <0>;
> > +               };
> > +
> > +               timer: timer@2050000 {
> > +                       compatible = "allwinner,sun20i-d1-timer",
> > +                                    "allwinner,sun8i-a23-timer";
> > +                       reg = <0x2050000 0xa0>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(59)
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <SOC_PERIPHERAL_IRQ(60)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&dcxo>;
> > +               };
> > +
> > +               wdt: watchdog@20500a0 {
> > +                       compatible = "allwinner,sun20i-d1-wdt-
> > reset",
> > +                                    "allwinner,sun20i-d1-wdt";
> > +                       reg = <0x20500a0 0x20>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(63)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> > +                       clock-names = "hosc", "losc";
> > +                       status = "reserved";
> > +               };
> > +
> > +               uart0: serial@2500000 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x2500000 0x400>;
> > +                       reg-io-width = <4>;
> > +                       reg-shift = <2>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(2)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_UART0>;
> > +                       resets = <&ccu RST_BUS_UART0>;
> > +                       dmas = <&dma 14>, <&dma 14>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart1: serial@2500400 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x2500400 0x400>;
> > +                       reg-io-width = <4>;
> > +                       reg-shift = <2>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(3)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_UART1>;
> > +                       resets = <&ccu RST_BUS_UART1>;
> > +                       dmas = <&dma 15>, <&dma 15>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart2: serial@2500800 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x2500800 0x400>;
> > +                       reg-io-width = <4>;
> > +                       reg-shift = <2>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(4)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_UART2>;
> > +                       resets = <&ccu RST_BUS_UART2>;
> > +                       dmas = <&dma 16>, <&dma 16>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart3: serial@2500c00 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x2500c00 0x400>;
> > +                       reg-io-width = <4>;
> > +                       reg-shift = <2>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(5)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_UART3>;
> > +                       resets = <&ccu RST_BUS_UART3>;
> > +                       dmas = <&dma 17>, <&dma 17>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart4: serial@2501000 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x2501000 0x400>;
> > +                       reg-io-width = <4>;
> > +                       reg-shift = <2>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(6)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_UART4>;
> > +                       resets = <&ccu RST_BUS_UART4>;
> > +                       dmas = <&dma 18>, <&dma 18>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart5: serial@2501400 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x2501400 0x400>;
> > +                       reg-io-width = <4>;
> > +                       reg-shift = <2>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(7)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_UART5>;
> > +                       resets = <&ccu RST_BUS_UART5>;
> > +                       dmas = <&dma 19>, <&dma 19>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c0: i2c@2502000 {
> > +                       compatible = "allwinner,sun20i-d1-i2c",
> > +                                    "allwinner,sun8i-v536-i2c",
> > +                                    "allwinner,sun6i-a31-i2c";
> > +                       reg = <0x2502000 0x400>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(9)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_I2C0>;
> > +                       resets = <&ccu RST_BUS_I2C0>;
> > +                       dmas = <&dma 43>, <&dma 43>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +               };
> > +
> > +               i2c1: i2c@2502400 {
> > +                       compatible = "allwinner,sun20i-d1-i2c",
> > +                                    "allwinner,sun8i-v536-i2c",
> > +                                    "allwinner,sun6i-a31-i2c";
> > +                       reg = <0x2502400 0x400>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(10)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_I2C1>;
> > +                       resets = <&ccu RST_BUS_I2C1>;
> > +                       dmas = <&dma 44>, <&dma 44>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +               };
> > +
> > +               i2c2: i2c@2502800 {
> > +                       compatible = "allwinner,sun20i-d1-i2c",
> > +                                    "allwinner,sun8i-v536-i2c",
> > +                                    "allwinner,sun6i-a31-i2c";
> > +                       reg = <0x2502800 0x400>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(11)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_I2C2>;
> > +                       resets = <&ccu RST_BUS_I2C2>;
> > +                       dmas = <&dma 45>, <&dma 45>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +               };
> > +
> > +               i2c3: i2c@2502c00 {
> > +                       compatible = "allwinner,sun20i-d1-i2c",
> > +                                    "allwinner,sun8i-v536-i2c",
> > +                                    "allwinner,sun6i-a31-i2c";
> > +                       reg = <0x2502c00 0x400>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(12)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_I2C3>;
> > +                       resets = <&ccu RST_BUS_I2C3>;
> > +                       dmas = <&dma 46>, <&dma 46>;
> > +                       dma-names = "rx", "tx";
> > +                       status = "disabled";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +               };
> > +
> > +               syscon: syscon@3000000 {
> > +                       compatible = "allwinner,sun20i-d1-system-
> > control";
> > +                       reg = <0x3000000 0x1000>;
> > +                       ranges;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +
> > +                       regulators@3000150 {
> > +                               compatible = "allwinner,sun20i-d1-
> > system-ldos";
> > +                               reg = <0x3000150 0x4>;
> > +
> > +                               reg_ldoa: ldoa {
> > +                               };
> > +
> > +                               reg_ldob: ldob {
> > +                               };
> > +                       };
> > +               };
> > +
> > +               dma: dma-controller@3002000 {
> > +                       compatible = "allwinner,sun20i-d1-dma";
> > +                       reg = <0x3002000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(50)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_DMA>, <&ccu
> > CLK_MBUS_DMA>;
> > +                       clock-names = "bus", "mbus";
> > +                       resets = <&ccu RST_BUS_DMA>;
> > +                       dma-channels = <16>;
> > +                       dma-requests = <48>;
> > +                       #dma-cells = <1>;
> > +               };
> > +
> > +               sid: efuse@3006000 {
> > +                       compatible = "allwinner,sun20i-d1-sid";
> > +                       reg = <0x3006000 0x1000>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +               };
> > +
> > +               mbus: dram-controller@3102000 {
> > +                       compatible = "allwinner,sun20i-d1-mbus";
> > +                       reg = <0x3102000 0x1000>,
> > +                             <0x3103000 0x1000>;
> > +                       reg-names = "mbus", "dram";
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(43)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_MBUS>,
> > +                                <&ccu CLK_DRAM>,
> > +                                <&ccu CLK_BUS_DRAM>;
> > +                       clock-names = "mbus", "dram", "bus";
> > +                       dma-ranges = <0 0x40000000 0x80000000>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +                       #interconnect-cells = <1>;
> > +               };
> > +
> > +               mmc0: mmc@4020000 {
> > +                       compatible = "allwinner,sun20i-d1-mmc";
> > +                       reg = <0x4020000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(40)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_MMC0>, <&ccu
> > CLK_MMC0>;
> > +                       clock-names = "ahb", "mmc";
> > +                       resets = <&ccu RST_BUS_MMC0>;
> > +                       reset-names = "ahb";
> > +                       cap-sd-highspeed;
> > +                       max-frequency = <150000000>;
> > +                       no-mmc;
> > +                       status = "disabled";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +               };
> > +
> > +               mmc1: mmc@4021000 {
> > +                       compatible = "allwinner,sun20i-d1-mmc";
> > +                       reg = <0x4021000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(41)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_MMC1>, <&ccu
> > CLK_MMC1>;
> > +                       clock-names = "ahb", "mmc";
> > +                       resets = <&ccu RST_BUS_MMC1>;
> > +                       reset-names = "ahb";
> > +                       cap-sd-highspeed;
> > +                       max-frequency = <150000000>;
> > +                       no-mmc;
> > +                       status = "disabled";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +               };
> > +
> > +               mmc2: mmc@4022000 {
> > +                       compatible = "allwinner,sun20i-d1-emmc",
> > +                                    "allwinner,sun50i-a100-emmc";
> > +                       reg = <0x4022000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(42)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_MMC2>, <&ccu
> > CLK_MMC2>;
> > +                       clock-names = "ahb", "mmc";
> > +                       resets = <&ccu RST_BUS_MMC2>;
> > +                       reset-names = "ahb";
> > +                       cap-mmc-highspeed;
> > +                       max-frequency = <150000000>;
> > +                       mmc-ddr-1_8v;
> > +                       mmc-ddr-3_3v;
> > +                       no-sd;
> > +                       no-sdio;
> > +                       status = "disabled";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +               };
> > +
> > +               usb_otg: usb@4100000 {
> > +                       compatible = "allwinner,sun20i-d1-musb",
> > +                                    "allwinner,sun8i-a33-musb";
> > +                       reg = <0x4100000 0x400>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(29)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "mc";
> > +                       clocks = <&ccu CLK_BUS_OTG>;
> > +                       resets = <&ccu RST_BUS_OTG>;
> > +                       extcon = <&usbphy 0>;
> > +                       phys = <&usbphy 0>;
> > +                       phy-names = "usb";
> > +                       status = "disabled";
> > +               };
> > +
> > +               usbphy: phy@4100400 {
> > +                       compatible = "allwinner,sun20i-d1-usb-phy";
> > +                       reg = <0x4100400 0x100>,
> > +                             <0x4101800 0x100>,
> > +                             <0x4200800 0x100>;
> > +                       reg-names = "phy_ctrl",
> > +                                   "pmu0",
> > +                                   "pmu1";
> > +                       clocks = <&dcxo>,
> > +                                <&dcxo>;
> > +                       clock-names = "usb0_phy",
> > +                                     "usb1_phy";
> > +                       resets = <&ccu RST_USB_PHY0>,
> > +                                <&ccu RST_USB_PHY1>;
> > +                       reset-names = "usb0_reset",
> > +                                     "usb1_reset";
> > +                       status = "disabled";
> > +                       #phy-cells = <1>;
> > +               };
> > +
> > +               ehci0: usb@4101000 {
> > +                       compatible = "allwinner,sun20i-d1-ehci",
> > +                                    "generic-ehci";
> > +                       reg = <0x4101000 0x100>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(30)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_OHCI0>,
> > +                                <&ccu CLK_BUS_EHCI0>,
> > +                                <&ccu CLK_USB_OHCI0>;
> > +                       resets = <&ccu RST_BUS_OHCI0>,
> > +                                <&ccu RST_BUS_EHCI0>;
> > +                       phys = <&usbphy 0>;
> > +                       phy-names = "usb";
> > +                       status = "disabled";
> > +               };
> > +
> > +               ohci0: usb@4101400 {
> > +                       compatible = "allwinner,sun20i-d1-ohci",
> > +                                    "generic-ohci";
> > +                       reg = <0x4101400 0x100>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(31)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_OHCI0>,
> > +                                <&ccu CLK_USB_OHCI0>;
> > +                       resets = <&ccu RST_BUS_OHCI0>;
> > +                       phys = <&usbphy 0>;
> > +                       phy-names = "usb";
> > +                       status = "disabled";
> > +               };
> > +
> > +               ehci1: usb@4200000 {
> > +                       compatible = "allwinner,sun20i-d1-ehci",
> > +                                    "generic-ehci";
> > +                       reg = <0x4200000 0x100>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(33)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_OHCI1>,
> > +                                <&ccu CLK_BUS_EHCI1>,
> > +                                <&ccu CLK_USB_OHCI1>;
> > +                       resets = <&ccu RST_BUS_OHCI1>,
> > +                                <&ccu RST_BUS_EHCI1>;
> > +                       phys = <&usbphy 1>;
> > +                       phy-names = "usb";
> > +                       status = "disabled";
> > +               };
> > +
> > +               ohci1: usb@4200400 {
> > +                       compatible = "allwinner,sun20i-d1-ohci",
> > +                                    "generic-ohci";
> > +                       reg = <0x4200400 0x100>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(34)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_OHCI1>,
> > +                                <&ccu CLK_USB_OHCI1>;
> > +                       resets = <&ccu RST_BUS_OHCI1>;
> > +                       phys = <&usbphy 1>;
> > +                       phy-names = "usb";
> > +                       status = "disabled";
> > +               };
> > +
> > +               emac: ethernet@4500000 {
> > +                       compatible = "allwinner,sun20i-d1-emac",
> > +                                    "allwinner,sun50i-a64-emac";
> > +                       reg = <0x4500000 0x10000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(46)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "macirq";
> > +                       clocks = <&ccu CLK_BUS_EMAC>;
> > +                       clock-names = "stmmaceth";
> > +                       resets = <&ccu RST_BUS_EMAC>;
> > +                       reset-names = "stmmaceth";
> > +                       syscon = <&syscon>;
> > +                       status = "disabled";
> > +
> > +                       mdio: mdio {
> > +                               compatible = "snps,dwmac-mdio";
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +                       };
> > +               };
> > +
> > +               display_clocks: clock-controller@5000000 {
>
> The clocks and the two mixers are not children of a bus node anymore,
> IIUC correctly this was to manage the SRAM control. Is that now
> handled
> differently, or does the D1 generation not require this anymore?

I think D1 does not require SRAM control at all, only a few SoCs really
need the SRAM control to be active for DE to work.

>
> > +                       compatible = "allwinner,sun20i-d1-de2-clk",
> > +                                    "allwinner,sun50i-h5-de2-clk";
> > +                       reg = <0x5000000 0x10000>;
> > +                       clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
> > +                       clock-names = "bus", "mod";
> > +                       resets = <&ccu RST_BUS_DE>;
> > +                       #clock-cells = <1>;
> > +                       #reset-cells = <1>;
> > +               };
> > +
> > +               mixer0: mixer@5100000 {
> > +                       compatible = "allwinner,sun20i-d1-de2-
> > mixer-0";
> > +                       reg = <0x5100000 0x100000>;
> > +                       clocks = <&display_clocks CLK_BUS_MIXER0>,
> > +                                <&display_clocks CLK_MIXER0>;
> > +                       clock-names = "bus", "mod";
> > +                       resets = <&display_clocks RST_MIXER0>;
> > +
> > +                       ports {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +
> > +                               mixer0_out: port@1 {
> > +                                       reg = <1>;
> > +
> > +                                       mixer0_out_tcon_top_mixer0:
> > endpoint {
> > +                                               remote-endpoint =
> > <&tcon_top_mixer0_in_mixer0>;
> > +                                       };
> > +                               };
> > +                       };
> > +               };
> > +
> > +               mixer1: mixer@5200000 {
> > +                       compatible = "allwinner,sun20i-d1-de2-
> > mixer-1";
> > +                       reg = <0x5200000 0x100000>;
> > +                       clocks = <&display_clocks CLK_BUS_MIXER1>,
> > +                                <&display_clocks CLK_MIXER1>;
> > +                       clock-names = "bus", "mod";
> > +                       resets = <&display_clocks RST_MIXER1>;
> > +
> > +                       ports {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +
> > +                               mixer1_out: port@1 {
> > +                                       reg = <1>;
> > +
> > +                                       mixer1_out_tcon_top_mixer1:
> > endpoint {
> > +                                               remote-endpoint =
> > <&tcon_top_mixer1_in_mixer1>;
> > +                                       };
> > +                               };
> > +                       };
> > +               };
> > +
> > +               dsi: dsi@5450000 {
> > +                       compatible = "allwinner,sun20i-d1-mipi-
> > dsi",
> > +                                    "allwinner,sun50i-a100-mipi-
> > dsi";
> > +                       reg = <0x5450000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(92)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_MIPI_DSI>,
> > +                                <&tcon_top CLK_TCON_TOP_DSI>;
> > +                       clock-names = "bus", "mod";
> > +                       resets = <&ccu RST_BUS_MIPI_DSI>;
> > +                       phys = <&dphy>;
> > +                       phy-names = "dphy";
> > +                       status = "disabled";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +
> > +                       port {
> > +                               dsi_in_tcon_lcd0: endpoint {
> > +                                       remote-endpoint =
> > <&tcon_lcd0_out_dsi>;
> > +                               };
> > +                       };
> > +               };
> > +
> > +               dphy: phy@5451000 {
> > +                       compatible = "allwinner,sun20i-d1-mipi-
> > dphy",
> > +                                    "allwinner,sun50i-a100-mipi-
> > dphy";
> > +                       reg = <0x5451000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(92)
> > IRQ_TYPE_LEVEL_HIGH>;
>
> This is the same interrupt number as for the DSI controller above. Is
> that correct, and can the drivers handle that?

I think this should be correct, and only one driver acquires IRQ now.

>
> Cheers,
> Andre
>
>
> > +                       clocks = <&ccu CLK_BUS_MIPI_DSI>,
> > +                                <&ccu CLK_MIPI_DSI>;
> > +                       clock-names = "bus", "mod";
> > +                       resets = <&ccu RST_BUS_MIPI_DSI>;
> > +                       #phy-cells = <0>;
> > +               };
> > +
> > +               tcon_top: tcon-top@5460000 {
> > +                       compatible = "allwinner,sun20i-d1-tcon-
> > top";
> > +                       reg = <0x5460000 0x1000>;
> > +                       clocks = <&ccu CLK_BUS_DPSS_TOP>,
> > +                                <&ccu CLK_TCON_TV>,
> > +                                <&ccu CLK_TVE>,
> > +                                <&ccu CLK_TCON_LCD0>;
> > +                       clock-names = "bus", "tcon-tv0", "tve0",
> > "dsi";
> > +                       clock-output-names = "tcon-top-tv0", "tcon-
> > top-dsi";
> > +                       resets = <&ccu RST_BUS_DPSS_TOP>;
> > +                       #clock-cells = <1>;
> > +
> > +                       ports {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +
> > +                               tcon_top_mixer0_in: port@0 {
> > +                                       reg = <0>;
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       tcon_top_mixer0_in_mixer0:
> > endpoint@0 {
> > +                                               reg = <0>;
> > +                                               remote-endpoint =
> > <&mixer0_out_tcon_top_mixer0>;
> > +                                       };
> > +                               };
> > +
> > +                               tcon_top_mixer0_out: port@1 {
> > +                                       reg = <1>;
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       tcon_top_mixer0_out_tcon_lc
> > d0: endpoint@0 {
> > +                                               reg = <0>;
> > +                                               remote-endpoint =
> > <&tcon_lcd0_in_tcon_top_mixer0>;
> > +                                       };
> > +
> > +                                       tcon_top_mixer0_out_tcon_tv
> > 0: endpoint@2 {
> > +                                               reg = <2>;
> > +                                               remote-endpoint =
> > <&tcon_tv0_in_tcon_top_mixer0>;
> > +                                       };
> > +                               };
> > +
> > +                               tcon_top_mixer1_in: port@2 {
> > +                                       reg = <2>;
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       tcon_top_mixer1_in_mixer1:
> > endpoint@1 {
> > +                                               reg = <1>;
> > +                                               remote-endpoint =
> > <&mixer1_out_tcon_top_mixer1>;
> > +                                       };
> > +                               };
> > +
> > +                               tcon_top_mixer1_out: port@3 {
> > +                                       reg = <3>;
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       tcon_top_mixer1_out_tcon_lc
> > d0: endpoint@0 {
> > +                                               reg = <0>;
> > +                                               remote-endpoint =
> > <&tcon_lcd0_in_tcon_top_mixer1>;
> > +                                       };
> > +
> > +                                       tcon_top_mixer1_out_tcon_tv
> > 0: endpoint@2 {
> > +                                               reg = <2>;
> > +                                               remote-endpoint =
> > <&tcon_tv0_in_tcon_top_mixer1>;
> > +                                       };
> > +                               };
> > +
> > +                               tcon_top_hdmi_in: port@4 {
> > +                                       reg = <4>;
> > +
> > +                                       tcon_top_hdmi_in_tcon_tv0:
> > endpoint {
> > +                                               remote-endpoint =
> > <&tcon_tv0_out_tcon_top_hdmi>;
> > +                                       };
> > +                               };
> > +
> > +                               tcon_top_hdmi_out: port@5 {
> > +                                       reg = <5>;
> > +                               };
> > +                       };
> > +               };
> > +
> > +               tcon_lcd0: lcd-controller@5461000 {
> > +                       compatible = "allwinner,sun20i-d1-tcon-
> > lcd";
> > +                       reg = <0x5461000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(90)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_TCON_LCD0>,
> > +                                <&ccu CLK_TCON_LCD0>;
> > +                       clock-names = "ahb", "tcon-ch0";
> > +                       clock-output-names = "tcon-pixel-clock";
> > +                       resets = <&ccu RST_BUS_TCON_LCD0>,
> > +                                <&ccu RST_BUS_LVDS0>;
> > +                       reset-names = "lcd", "lvds";
> > +                       #clock-cells = <0>;
> > +
> > +                       ports {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +
> > +                               tcon_lcd0_in: port@0 {
> > +                                       reg = <0>;
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       tcon_lcd0_in_tcon_top_mixer
> > 0: endpoint@0 {
> > +                                               reg = <0>;
> > +                                               remote-endpoint =
> > <&tcon_top_mixer0_out_tcon_lcd0>;
> > +                                       };
> > +
> > +                                       tcon_lcd0_in_tcon_top_mixer
> > 1: endpoint@1 {
> > +                                               reg = <1>;
> > +                                               remote-endpoint =
> > <&tcon_top_mixer1_out_tcon_lcd0>;
> > +                                       };
> > +                               };
> > +
> > +                               tcon_lcd0_out: port@1 {
> > +                                       reg = <1>;
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       tcon_lcd0_out_dsi:
> > endpoint@1 {
> > +                                               reg = <1>;
> > +                                               remote-endpoint =
> > <&dsi_in_tcon_lcd0>;
> > +                                       };
> > +                               };
> > +                       };
> > +               };
> > +
> > +               tcon_tv0: lcd-controller@5470000 {
> > +                       compatible = "allwinner,sun20i-d1-tcon-tv";
> > +                       reg = <0x5470000 0x1000>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(91)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_TCON_TV>,
> > +                                <&tcon_top CLK_TCON_TOP_TV0>;
> > +                       clock-names = "ahb", "tcon-ch1";
> > +                       resets = <&ccu RST_BUS_TCON_TV>;
> > +                       reset-names = "lcd";
> > +
> > +                       ports {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +
> > +                               tcon_tv0_in: port@0 {
> > +                                       reg = <0>;
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       tcon_tv0_in_tcon_top_mixer0
> > : endpoint@0 {
> > +                                               reg = <0>;
> > +                                               remote-endpoint =
> > <&tcon_top_mixer0_out_tcon_tv0>;
> > +                                       };
> > +
> > +                                       tcon_tv0_in_tcon_top_mixer1
> > : endpoint@1 {
> > +                                               reg = <1>;
> > +                                               remote-endpoint =
> > <&tcon_top_mixer1_out_tcon_tv0>;
> > +                                       };
> > +                               };
> > +
> > +                               tcon_tv0_out: port@1 {
> > +                                       reg = <1>;
> > +
> > +                                       tcon_tv0_out_tcon_top_hdmi:
> > endpoint {
> > +                                               remote-endpoint =
> > <&tcon_top_hdmi_in_tcon_tv0>;
> > +                                       };
> > +                               };
> > +                       };
> > +               };
> > +
> > +               r_ccu: clock-controller@7010000 {
> > +                       compatible = "allwinner,sun20i-d1-r-ccu";
> > +                       reg = <0x7010000 0x400>;
> > +                       clocks = <&dcxo>,
> > +                                <&rtc CLK_OSC32K>,
> > +                                <&rtc CLK_IOSC>,
> > +                                <&ccu CLK_PLL_PERIPH0_DIV3>;
> > +                       clock-names = "hosc", "losc", "iosc", "pll-
> > periph";
> > +                       #clock-cells = <1>;
> > +                       #reset-cells = <1>;
> > +               };
> > +
> > +               rtc: rtc@7090000 {
> > +                       compatible = "allwinner,sun20i-d1-rtc",
> > +                                    "allwinner,sun50i-r329-rtc";
> > +                       reg = <0x7090000 0x400>;
> > +                       interrupts = <SOC_PERIPHERAL_IRQ(144)
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&r_ccu CLK_BUS_R_RTC>,
> > +                                <&dcxo>,
> > +                                <&r_ccu CLK_R_AHB>;
> > +                       clock-names = "bus", "hosc", "ahb";
> > +                       #clock-cells = <1>;
> > +               };
> > +       };
> > +};
>
>

2022-12-02 18:57:23

by Palmer Dabbelt

[permalink] [raw]

Subject: Re: [PATCH v2 00/12] riscv: Allwinner D1/D1s platform support

On Fri, 25 Nov 2022 15:46:44 PST (-0800), [email protected] wrote:
> This series adds the Kconfig/defconfig plumbing and devicetrees for a
> range of Allwinner D1 and D1s-based boards. Many features are already
> enabled, including USB, Ethernet, and WiFi.
>
> The devicetrees use bindings from the following series which have not
> yet been merged:
> - In-package LDO regulators:
> https://lore.kernel.org/lkml/[email protected]/
> - Ethernet MAC binding fixes (not a new issue with D1):
> https://lore.kernel.org/lkml/[email protected]/
> - RTL8723DS Bluetooth (has driver support, missing documentation):
> https://lore.kernel.org/lkml/[email protected]/
> - TI ADC101C ADC (has driver support, missing documentation):
> https://lore.kernel.org/lkml/[email protected]/
>
> The only remaining DT validation issue is that gpio-fan is missing a
> YAML conversion, although one is on the list here:
> https://lore.kernel.org/lkml/[email protected]/
>
> $ make ARCH=riscv CROSS_COMPILE=riscv64-linux-musl- dtbs_check
> SYNC include/config/auto.conf.cmd
> LINT Documentation/devicetree/bindings
> CHKDT Documentation/devicetree/bindings/processed-schema.json
> SCHEMA Documentation/devicetree/bindings/processed-schema.json
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dtb
> DTC_CHK arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dtb
> arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dtb:0:0: /fan: failed to match any schema with compatible: ['gpio-fan']
>
> I tested this series (DMIC, Ethernet, LEDs, MMC, PMIC, touch, and USB,
> all where available) on the following boards:
> - sun20i-d1-devterm-v3.14
> - sun20i-d1-dongshan-nezha-stu
> - sun20i-d1-lichee-rv-86-panel-480p
> - sun20i-d1-mangopi-mq-pro
> - sun20i-d1-nezha
> - sun20i-d1s-mangopi-mq
>
> Changes in v2:
> - Add MangoPi MQ (non-Pro) board
> - Split into separate files for sharing with D1s/R528/T113
> - Use SOC_PERIPHERAL_IRQ macro for interrupts
> - Rename osc24M to dcxo and move the frequency to the board DTs
> - Drop analog LDOs due to the missing binding
> - Correct tcon_top DSI clock reference
> - Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
> - Add CPU OPP table
> - Common regulators moved to MangoPi MQ patch, removed analog LDOs
> - Removed LRADC (depends on analog LDOs)
> - Added XR829 host-wake interrupt
> - Added DMIC sound card to Lichee RV dock and Lichee RV 86 Panel
> - Removed LRADC (depends on analog LDOs)
> - Added LED (GPIO shared between onboard LED and backlight regulator)
> - Added PMIC GPIO controller node (binding merged for 6.2)
> - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing
>
> Samuel Holland (12):
> MAINTAINERS: Match the sun20i family of Allwinner SoCs
> dt-bindings: vendor-prefixes: Add Allwinner D1/D1s board vendors
> dt-bindings: riscv: Add Allwinner D1/D1s board compatibles
> riscv: dts: allwinner: Add the D1/D1s SoC devicetree
> riscv: dts: allwinner: Add MangoPi MQ devicetree
> riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree
> riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees
> riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
> riscv: dts: allwinner: Add Dongshan Nezha STU devicetree
> riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees
> riscv: Add the Allwinner SoC family Kconfig option
> riscv: defconfig: Enable the Allwinner D1 platform and drivers
>
> .../devicetree/bindings/riscv/sunxi.yaml | 69 ++
> .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> MAINTAINERS | 2 +-
> arch/riscv/Kconfig.socs | 9 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/Makefile | 11 +
> .../allwinner/sun20i-common-regulators.dtsi | 35 +
> .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 253 ++++++
> .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 36 +
> .../sun20i-d1-dongshan-nezha-stu.dts | 118 +++
> .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
> .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
> .../sun20i-d1-lichee-rv-86-panel.dtsi | 118 +++
> .../allwinner/sun20i-d1-lichee-rv-dock.dts | 96 ++
> .../dts/allwinner/sun20i-d1-lichee-rv.dts | 88 ++
> .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 143 +++
> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 167 ++++
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++
> .../dts/allwinner/sun20i-d1s-mangopi-mq.dts | 135 +++
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++
> .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 +
> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 844 ++++++++++++++++++
> arch/riscv/configs/defconfig | 23 +-
> 23 files changed, 2346 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

Acked-by: Palmer Dabbelt <[email protected]>

2022-12-05 20:50:46

[permalink] [raw]

Subject: Re: [PATCH v2 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs

Dne sobota, 26. november 2022 ob 00:46:45 CET je Samuel Holland napisal(a):
> Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match
> that pattern in addition to the designators for 32 and 64-bit ARM SoCs.
>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>

Acked-by: Jernej Skrabec <[email protected]>

Best regards,
Jernej

2022-12-05 20:55:37

[permalink] [raw]

Subject: Re: [PATCH v2 09/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree

Hi Samuel,

Dne sobota, 26. november 2022 ob 00:46:53 CET je Samuel Holland napisal(a):
> The 100ask Dongshan Nezha STU is a system-on-module that can be used
> standalone or with a carrier board. The SoM provides gigabit Ethernet,
> HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.
>
> The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
> headers, but contains no digital circuitry, so it does not have its own
> devicetree.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> (no changes since v1)
>
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> .../sun20i-d1-dongshan-nezha-stu.dts | 118 ++++++++++++++++++
> 2 files changed, 119 insertions(+)
> create mode 100644
> arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
>
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile
> b/arch/riscv/boot/dts/allwinner/Makefile index 2ed586fafaea..87f70b1af6b4
> 100644
> --- a/arch/riscv/boot/dts/allwinner/Makefile
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
> b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts new file
> mode 100644
> index 000000000000..c549a1c5fbf0
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/dts-v1/;
> +
> +#include "sun20i-d1.dtsi"
> +#include "sun20i-common-regulators.dtsi"
> +
> +/ {
> + model = "Dongshan Nezha STU";
> + compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
> +
> + aliases {
> + ethernet0 = &emac;
> + mmc0 = &mmc0;

Sorry, I just noticed now, but why is there above alias? It's not sunxi
practice to add mmc aliases.

Best regards,
Jernej

> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-0 {
> + color = <LED_COLOR_ID_GREEN>;
> + function = LED_FUNCTION_STATUS;
> + gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1
*/
> + };
> + };
> +
> + reg_usbvbus: usbvbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usbvbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
> + enable-active-high;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + /*
> + * This regulator is PWM-controlled, but the PWM controller is not
> + * yet supported, so fix the regulator to its default voltage.
> + */
> + reg_vdd_cpu: vdd-cpu {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-cpu";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + vin-supply = <&reg_vcc>;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&reg_vdd_cpu>;
> +};
> +
> +&dcxo {
> + clock-frequency = <24000000>;
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&emac {
> + pinctrl-0 = <&rgmii_pe_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&reg_vcc_3v3>;
> + status = "okay";
> +};
> +
> +&mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&mmc0 {
> + broken-cd;
> + bus-width = <4>;
> + disable-wp;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb8_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
> + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
> + usb0_vbus-supply = <&reg_usbvbus>;
> + status = "okay";
> +};
> --
> 2.37.4

2022-12-05 21:07:21

[permalink] [raw]

Subject: Re: [PATCH v2 05/12] riscv: dts: allwinner: Add MangoPi MQ devicetree

Dne sobota, 26. november 2022 ob 00:46:49 CET je Samuel Holland napisal(a):
> The MangoPi MQ is a tiny SBC built around the Allwinner D1s. Its
> onboard peripherals include two USB Type-C ports (1 device, 1 host)
> and RTL8189FTV WLAN.
>
> A MangoPi MQ-R variant of the board also exists. The MQ-R has a
> different form factor, but the onboard peripherals are the same.
>
> Most D1 and D1s boards use a similar power tree, with the 1.8V rail
> powered by the SoC's internal LDOA, analog domains powered by ALDO,
> and the rest of the board powered by always-on fixed regulators. To
> avoid duplication, factor out the regulator information that is
> common across boards.
>
> The board also exposes GPIO Port E via a FPC connector, which can
> support either a camera or an RMII Ethernet PHY. The additional
> regulators supply that connector.
>
> Signed-off-by: Samuel Holland <[email protected]>

Acked-by: Jernej Skrabec <[email protected]>

Best regards,
Jernej

2022-12-05 21:41:54

[permalink] [raw]

Subject: Re: [PATCH v2 09/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree

Dne sobota, 26. november 2022 ob 00:46:53 CET je Samuel Holland napisal(a):
> The 100ask Dongshan Nezha STU is a system-on-module that can be used
> standalone or with a carrier board. The SoM provides gigabit Ethernet,
> HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.
>
> The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
> headers, but contains no digital circuitry, so it does not have its own
> devicetree.
>
> Signed-off-by: Samuel Holland <[email protected]>

Acked-by: Jernej Skrabec <[email protected]>

Best regards,
Jernej

2022-12-05 21:42:20

[permalink] [raw]

Subject: Re: [PATCH v2 08/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree

Dne sobota, 26. november 2022 ob 00:46:52 CET je Samuel Holland napisal(a):
> The MangoPi MQ Pro is a tiny SBC with a layout compatible to the
> Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3,
> and an RTL8723DS-based WiFi/Bluetooth module.
>
> The board also exposes GPIO Port E via a connector on the end of the
> board, which can support either a camera or an RMII Ethernet PHY. The
> additional regulators supply that connector.
>
> Signed-off-by: Samuel Holland <[email protected]>

Acked-by: Jernej Skrabec <[email protected]>

Best regards,
Jernej

2022-12-05 21:43:38

[permalink] [raw]

Subject: Re: [PATCH v2 06/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

Dne sobota, 26. november 2022 ob 00:46:50 CET je Samuel Holland napisal(a):
> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
> plus low-speed I/O from the SoC and a GPIO expander chip.
>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Tested-by: Conor Dooley <[email protected]>
> Tested-by: Heiko Stuebner <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>

Acked-by: Jernej Skrabec <[email protected]>

Best regards,
Jernej

2022-12-05 21:50:43

[permalink] [raw]

Subject: Re: [PATCH v2 07/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees

Dne sobota, 26. november 2022 ob 00:46:51 CET je Samuel Holland napisal(a):
> Sipeed manufactures a "Lichee RV" system-on-module, which provides a
> minimal working system on its own, as well as a few carrier boards. The
> "Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally
> provides 100M Ethernet and a built-in display panel.
>
> The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB
> panel interface, since the USB OTG port is inaccessible inside the case.
>
> Co-developed-by: Jisheng Zhang <[email protected]>
> Signed-off-by: Jisheng Zhang <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>

Acked-by: Jernej Skrabec <[email protected]>

Best regards,
Jernej

2022-12-05 21:54:02