This patchset enables CXL RCH error handling. This is necessary because RCH
downstream port protocol error handling is implemented uniquely and not
currently supported. These patches address the following:
* Discovery and mapping of RCH downstream port AER registers.
* AER portdrv changes to support CXL RCH protocol errors.
* Interrupt setup specific to RCH mode: enabling RCEC internal
errors and disabling root port interrupts.
* Logging RCH downstream port AER and RAS errors.
Changes in v11:
- Rebased onto cxl/fixes (c66650d29764)
- Added: cxl/port: Fix release of RCD endpoints
- Added: cxl/core/regs: Rename @dev to @host in struct cxl_register_map
- Added: cxl/port: Fix @host confusion in cxl_dport_setup_regs()
- Added: cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map
- Removed: cxl/regs: Prepare for multiple users of register mappings
- Modified: cxl/hdm: Use stored Component Register mappings to map
HDM decoder capability
- Dan: rework to drop cxl_port_get_comp_map()
- Added: cxl/pci: Introduce config option PCIEAER_CXL
- Modified: cxl/pci: Add RCH downstream port AER register discovery
- Moved AER discovery to devm_cxl_setup_parent_dport() called when
memdev is probed
- Fixed devm_cxl_iomap_block() release by fixing devm host
- Modified: cxl/pci: Map RCH downstream AER registers for logging
protocol errors
- Reworded description
- Moved register mappings to devm_cxl_setup_parent_dport() called
when memdev is probed
- Modified: cxl/pci: Disable root port interrupts in RCH mode
- Call cxl_disable_rch_root_ints() in devm_cxl_setup_parent_dport()
called when memdev is probed
- Fixed resource release by fixing devm host
- Reworded description of PCIEAER_CXL config option
- Added: cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for
devm
Changes in v10:
- Updated cxl_setup_comp_regs() in patch#1 to include
cxl_register_map::reg_type default value initialization.
Changes in v9:
- Added: cxl/regs: Prepare for multiple users of register mappings,
- Updated use of cxl_map_component_regs() and cxl_map_device_regs
Changes in V8:
- Rebased onto: commit
0c0df63177e3 ("Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl")
- cxl/port: Pre-initialize component register mappings
- Added patch to pre-initialize component register mappings.
- cxl/pci: Remove Component Register base address from
- Separated removal of Component Register base address in struct
cxl_dev_state to not break functionality.
- cxl/hdm: Use stored Component Register mappings to map HDM decoder
capability
- Implemented a less strict check in devm_cxl_setup_hdm(), be tolerant
if HDM decoder registers are not implemented.
- cxl/pci: Map RCH downstream AER registers for logging protocol errors
- Fixed uninitialized access of map->dev in cxl_dport_map_regs().
- PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem
dev handler
- Fix typo in patch description.
- cxl/pci: Update CXL error logging to use RAS register address
- Fix typo in patch description.
Changes in V7:
- cxl: Updates for CXL Test to work with RCH
- Removed Robert's DSO.
- cxl/core/regs: Add @dev to cxl_register_map
- Corrected typo in patch description.
- PCI/AER: Unmask RCEC internal errors to enable RCH downstream port
error handling.
- Changed int variable to bool.
- cxl/pci: Map RCH downstream AER registers for logging protocol errors
- Corrected patch description.
- cxl/pci: Add RCH downstream port AER register discovery
- Reverted empty line removal.
- cxl/port: Store the port's Component Register mappings in struct
cxl_port
- Update to use structure initialization in cxl_setup_comp_regs().
- Remove first patch (already in the tree) and added patch 27/27.
- Was a one-off error caused when merging branches during internal
review.
Changes in V6:
- Added patch for cxl test fixes: 'cxl: Update CXl Test to Work with
RCH'. Patch from Dan.
- Simplified: 'cxl/rch: Prepare for caching the MMIO mapped PCIe AER
capability'. Patch from Dan.
- Added patch: 'cxl: Rename 'uport' to 'uport_dev''
- Updated patch: 'cxl: Rename member @dport of struct cxl_dport to
@dport_dev'
- Updated *map assignment to use structure init in 'cxl/core/regs: Add
@dev to cxl_register_map'. Also fixed whitespace.
- Removed extra whitespace in 'cxl/core/regs: Add @dev to
cxl_register_map'
- Updated patch subject: 'cxl/acpi: Move add_host_bridge_uport() after
cxl_get_chbs()'
- Changes to work with CXL test. 'cxl/acpi: Directly bind the CEDT
detected CHBCR to the Host Bridge's port'
- 'cxl/pci: Early setup RCH dport component registers from RCRB'
- Removed parameter from cxl_rcrb_get_comp_regs().
- Changed return value to EPROBE_DEFER for retry during ACPI
initialization.
- Changed map to us struct initialization.
- Remove ENODEV check in 'cxl/port: Store the downstream port's
Component Register mappings in struct cxl_dport'
- 'cxl/port: Remove Component Register base address from struct
cxl_dport'
- Moved earlier with same removal for cxl_port.
- cxl/pci: Add RCH downstream port AER register discovery
- Flattened {request,release}_mem_region() and ioremap() into
cxl_rcrb_to_aer().
- Add check if OS is assigned AER handling before discovering AER.
- Added CXL namespace import to cxl_core (drivers/cxl/core/port.c).
Needed for using pci_print_aer(). In 'PCI/AER: Refactor
cper_print_aer() for use by CXL driver module'.
- cxl/pci: Map RCH downstream AER registers for logging protocol errors
- Changed dport device used in devm_cxl_iomap_block() call to be
port->dev.
- Removed ENODEV check.
- cxl/pci: Disable root port interrupts in RCH mode
- Removed unnecessary 'rch' check.
- Moved cxl_disable_rch_root_ints() into core/pci.c.
- Added OSC AER assignment check before accessing AER registers.
- cxl/pci: Update CXL error logging to use RAS register address
- Renamed function handlers.
- cxl/pci: Add RCH downstream port error logging
- Moved RCD check to caller.
- Added put_dev() after call to cxl_pci_find_port().
Changes in V5:
- Split 'cxl/rch: Prepare for logging RCH downstream port protocol
errors' patch into 2 patches.
- Added:
cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
cxl/mem: Prepare for early RCH dport component register setup
- Correct comments CXL3.0 to CXL 3.0.
- changed cxl_port_get_comp_map() to static.
Changes in V4:
- Made port RAS register discovery common and called from
__devm_cxl_add_dport().
- Changed RCH AER register discovery to be called from
__devm_cxl_add_dport().
- Changed RAS and RCH AER register mapping to be called from
__devm_cxl_add_dport().
- Changed component register mapping to support all CXL component
mapping, cxl_map_component_regs().
- Added cxl_regs to 'struct cxl_dport' for providing RCH downstream port
mapped registers USED in error handler.
- PCI/AER:
- Improved description of PCIEAER_CXL option in Kconfig.
- Renamed function to pci_aer_unmask_internal_errors(), added
pcie_aer_is_native() check.
- Improved comments and added spec refs.
- Renamed functions to cxl_rch_handle_error*().
- Modified cxl_rch_handle_error_iter() to only call the handler
callbacks, this also simplifies refcounting of the pdev.
- Refactored handle_error_source(), created pci_aer_handle_error().
- Changed printk messages to pci_*() variants.
- Added check for pcie_aer_is_native() to the RCEC.
- Introduced function cxl_rch_enable_rcec().
- Updated patch description ("PCI/AER: Forward RCH downstream
port-detected errors to the CXL.mem dev handler").
Changes in V3:
- Correct base commit in cover sheet.
- Change hardcoded return 0 to NULL in regs.c.
- Remove calls to pci_disable_pcie_error_reporting(pdev) and
pci_enable_pcie_error_reporting(pdev) in mem.c;
- Move RCEC interrupt unmask to PCIe port AER driver's probe.
- Fixes missing PCIEAER and PCIEPORTBUS config option error.
- Rename cxl_rcrb_setup() to cxl_setup_rcrb() in mem.c.
- Update cper_mem_err_unpack() patch subject and description.
Changes in V2:
- Refactor RCH initialization into cxl_mem driver.
- Includes RCH RAS and AER register discovery and mapping.
- Add RCEC protocol error interrupt forwarding to CXL endpoint
handler.
- Change AER and RAS logging to use existing trace routines.
- Enable RCEC AER internal errors.
Dan Williams (1):
cxl/port: Fix @host confusion in cxl_dport_setup_regs()
Robert Richter (13):
cxl/port: Fix release of RCD endpoints
cxl/core/regs: Rename @dev to @host in struct cxl_register_map
cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map
cxl/port: Pre-initialize component register mappings
cxl/pci: Store the endpoint's Component Register mappings in struct
cxl_dev_state
cxl/hdm: Use stored Component Register mappings to map HDM decoder
capability
cxl/pci: Remove Component Register base address from struct
cxl_dev_state
cxl/port: Remove Component Register base address from struct cxl_port
cxl/pci: Introduce config option PCIEAER_CXL
PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem
dev handler
PCI/AER: Unmask RCEC internal errors to enable RCH downstream port
error handling
cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm
Terry Bowman (6):
cxl/pci: Add RCH downstream port AER register discovery
PCI/AER: Refactor cper_print_aer() for use by CXL driver module
cxl/pci: Update CXL error logging to use RAS register address
cxl/pci: Map RCH downstream AER registers for logging protocol errors
cxl/pci: Add RCH downstream port error logging
cxl/pci: Disable root port interrupts in RCH mode
drivers/cxl/core/core.h | 1 +
drivers/cxl/core/hdm.c | 48 +++-----
drivers/cxl/core/mbox.c | 2 +
drivers/cxl/core/pci.c | 223 +++++++++++++++++++++++++++++++++--
drivers/cxl/core/port.c | 104 +++++++++++-----
drivers/cxl/core/regs.c | 72 ++++++++---
drivers/cxl/cxl.h | 34 ++++--
drivers/cxl/cxlmem.h | 4 +-
drivers/cxl/mem.c | 7 +-
drivers/cxl/pci.c | 14 +--
drivers/pci/pcie/Kconfig | 9 ++
drivers/pci/pcie/aer.c | 162 ++++++++++++++++++++++++-
include/linux/aer.h | 2 +-
tools/testing/cxl/test/mem.c | 1 -
14 files changed, 559 insertions(+), 124 deletions(-)
base-commit: c66650d29764e228eba40b7a59fdb70fa6567daa
--
2.30.2
Now, that the Component Register mappings are stored, use them to
enable and map the HDM decoder capabilities. The Component Registers
do not need to be probed again for this, remove probing code.
The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
Endpoint's component register mappings are located in the cxlds and
else in the port's structure. Duplicate the cxlds->reg_map in
port->reg_map for endpoint ports.
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
[rework to drop cxl_port_get_comp_map()]
Signed-off-by: Dan Williams <[email protected]>
---
drivers/cxl/core/hdm.c | 48 ++++++++++++++++-------------------------
drivers/cxl/core/port.c | 29 +++++++++++++++++++------
drivers/cxl/mem.c | 5 ++---
3 files changed, 43 insertions(+), 39 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 11d9971f3e8c..14a0d0017df3 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
cxlhdm->interleave_mask |= GENMASK(14, 12);
}
-static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
- struct cxl_component_regs *regs)
-{
- struct cxl_register_map map = {
- .host = &port->dev,
- .resource = port->component_reg_phys,
- .base = crb,
- .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
- };
-
- cxl_probe_component_regs(&port->dev, crb, &map.component_map);
- if (!map.component_map.hdm_decoder.valid) {
- dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
- /* unique error code to indicate no HDM decoder capability */
- return -ENODEV;
- }
-
- return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
-}
-
static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
{
struct cxl_hdm *cxlhdm;
@@ -155,7 +135,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
{
struct device *dev = &port->dev;
struct cxl_hdm *cxlhdm;
- void __iomem *crb;
+ struct cxl_register_map *reg_map;
int rc;
cxlhdm = devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL);
@@ -164,19 +144,29 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
cxlhdm->port = port;
dev_set_drvdata(dev, cxlhdm);
- crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
- if (!crb && info && info->mem_enabled) {
- cxlhdm->decoder_count = info->ranges;
- return cxlhdm;
- } else if (!crb) {
+ reg_map = &port->reg_map;
+ if (reg_map->resource == CXL_RESOURCE_NONE) {
+ if (info && info->mem_enabled) {
+ cxlhdm->decoder_count = info->ranges;
+ return cxlhdm;
+ }
+ WARN_ON(1);
dev_err(dev, "No component registers mapped\n");
return ERR_PTR(-ENXIO);
}
- rc = map_hdm_decoder_regs(port, crb, &cxlhdm->regs);
- iounmap(crb);
- if (rc)
+ if (!reg_map->component_map.hdm_decoder.valid) {
+ dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
+ /* unique error code to indicate no HDM decoder capability */
+ return ERR_PTR(-ENODEV);
+ }
+
+ rc = cxl_map_component_regs(reg_map, &cxlhdm->regs,
+ BIT(CXL_CM_CAP_CAP_ID_HDM));
+ if (rc) {
+ dev_dbg(dev, "Failed to map HDM capability.\n");
return ERR_PTR(rc);
+ }
parse_hdm_decoder_caps(cxlhdm);
if (cxlhdm->decoder_count == 0) {
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 28ba8922d0a4..f69484d3c93c 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -751,16 +751,31 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
return port;
dev = &port->dev;
- if (is_cxl_memdev(uport_dev))
+ if (is_cxl_memdev(uport_dev)) {
+ struct cxl_memdev *cxlmd = to_cxl_memdev(uport_dev);
+ struct cxl_dev_state *cxlds = cxlmd->cxlds;
+
rc = dev_set_name(dev, "endpoint%d", port->id);
- else if (parent_dport)
+ if (rc)
+ goto err;
+
+ /*
+ * The endpoint driver already enumerated the component and RAS
+ * registers. Reuse that enumeration while prepping them to be
+ * mapped by the cxl_port driver.
+ */
+ port->reg_map = cxlds->reg_map;
+ port->reg_map.host = &port->dev;
+ } else if (parent_dport) {
rc = dev_set_name(dev, "port%d", port->id);
- else
- rc = dev_set_name(dev, "root%d", port->id);
- if (rc)
- goto err;
+ if (rc)
+ goto err;
- rc = cxl_port_setup_regs(port, component_reg_phys);
+ rc = cxl_port_setup_regs(port, component_reg_phys);
+ if (rc)
+ goto err;
+ } else
+ rc = dev_set_name(dev, "root%d", port->id);
if (rc)
goto err;
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 317c7548e4e9..04107058739b 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
struct cxl_dport *parent_dport)
{
struct cxl_port *parent_port = parent_dport->port;
- struct cxl_dev_state *cxlds = cxlmd->cxlds;
struct cxl_port *endpoint, *iter, *down;
int rc;
@@ -65,8 +64,8 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
ep->next = down;
}
- endpoint = devm_cxl_add_port(host, &cxlmd->dev,
- cxlds->component_reg_phys,
+ /* Note: endpoint port component registers are derived from @cxlds */
+ endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE,
parent_dport);
if (IS_ERR(endpoint))
return PTR_ERR(endpoint);
--
2.30.2
Binding and unbindind RCD endpoints (e.g. mem0 device) caused the
corresponding endpoint not being released. Reason for that is the
wrong port discovered for RCD endpoints. See cxl_mem_probe() for
proper endpoint parent detection. Fix delete_endpoint() respectively.
Signed-off-by: Robert Richter <[email protected]>
---
drivers/cxl/core/port.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 7ca01a834e18..d4572a02989a 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1222,12 +1222,17 @@ static void delete_endpoint(void *data)
struct cxl_memdev *cxlmd = data;
struct cxl_port *endpoint = cxlmd->endpoint;
struct cxl_port *parent_port;
+ struct cxl_dport *dport;
struct device *parent;
- parent_port = cxl_mem_find_port(cxlmd, NULL);
+ parent_port = cxl_mem_find_port(cxlmd, &dport);
if (!parent_port)
goto out;
- parent = &parent_port->dev;
+
+ if (dport->rch)
+ parent = parent_port->uport_dev;
+ else
+ parent = &parent_port->dev;
device_lock(parent);
if (parent->driver && !endpoint->dead) {
--
2.30.2
struct cxl_register_map carries a @dev parameter for devm operations.
Simplify the function interface to use that instead of a separate @dev
argument.
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
---
drivers/cxl/core/regs.c | 5 ++---
drivers/cxl/cxl.h | 3 +--
drivers/cxl/pci.c | 2 +-
3 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 7b56f6f28ab1..b668be617fd7 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -386,10 +386,9 @@ int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
}
EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
-int cxl_map_pmu_regs(struct pci_dev *pdev, struct cxl_pmu_regs *regs,
- struct cxl_register_map *map)
+int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs)
{
- struct device *dev = &pdev->dev;
+ struct device *dev = map->host;
resource_size_t phys_addr;
phys_addr = map->resource;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 7c2c195592d6..ed90ca8ed79e 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -286,8 +286,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
unsigned long map_mask);
int cxl_map_device_regs(const struct cxl_register_map *map,
struct cxl_device_regs *regs);
-int cxl_map_pmu_regs(struct pci_dev *pdev, struct cxl_pmu_regs *regs,
- struct cxl_register_map *map);
+int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs);
enum cxl_regloc_type;
int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 037792e941f2..fa94bc61af25 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -898,7 +898,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
break;
}
- rc = cxl_map_pmu_regs(pdev, &pmu_regs, &map);
+ rc = cxl_map_pmu_regs(&map, &pmu_regs);
if (rc) {
dev_dbg(&pdev->dev, "Could not map PMU regs\n");
break;
--
2.30.2
From: Dan Williams <[email protected]>
commit 5d2ffbe4b81a ("cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport")
...moved the dport component registers from a raw component_reg_phys
passed in at dport instantiation time to a 'struct cxl_register_map'
populated with both the component register data *and* the "host" device
for mapping operations.
While typical CXL switch dports are mapped by their associated 'struct
cxl_port', an RCH host bridge dport registered by cxl_acpi needs to wait
until the cxl_mem driver makes the attachment to map the registers. This
is because there are no intervening 'struct cxl_port' instances between
the root cxl_port and the endpoint port in an RCH topology.
For now just mark the host as NULL in the RCH dport case until code that
needs to map the dport registers arrives. Name the field @reg_map,
because @reg_map->host will be used for mapping operations beyond
component registers (i.e. AER registers).
This patch is not flagged for -stable since nothing in the current
driver uses the dport->reg_map.
Now, I am slightly uneasy that cxl_setup_comp_regs() sets map->host to a
wrong value and then cxl_dport_setup_regs() fixes it up, but the
alternatives I came up with are more messy. For example, adding an
@logdev to 'struct cxl_register_map' that the dev_printk()s can fall
back to when @host is NULL. I settled on "post-fixup+comment" since it
is only RCH dports that have this special case where register probing is
split between a host-bridge RCRB lookup and when cxl_mem_probe() does
the association of the cxl_memdev and endpoint port.
Fixes: 5d2ffbe4b81a ("cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport")
Cc: Jonathan Cameron <[email protected]>
Signed-off-by: Dan Williams <[email protected]>
[kept dev_dbg() message]
Signed-off-by: Robert Richter <[email protected]>
---
drivers/cxl/core/port.c | 43 +++++++++++++++++++++++++++++------------
drivers/cxl/cxl.h | 4 ++--
2 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 033651a5da30..99df86d72dbc 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -716,13 +716,23 @@ static int cxl_port_setup_regs(struct cxl_port *port,
component_reg_phys);
}
-static int cxl_dport_setup_regs(struct cxl_dport *dport,
+static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport,
resource_size_t component_reg_phys)
{
+ int rc;
+
if (dev_is_platform(dport->dport_dev))
return 0;
- return cxl_setup_comp_regs(dport->dport_dev, &dport->comp_map,
- component_reg_phys);
+
+ /*
+ * use @dport->dport_dev for the context for error messages during
+ * register probing, and fixup @host after the fact, since @host may be
+ * NULL.
+ */
+ rc = cxl_setup_comp_regs(dport->dport_dev, &dport->reg_map,
+ component_reg_phys);
+ dport->reg_map.host = host;
+ return rc;
}
static struct cxl_port *__devm_cxl_add_port(struct device *host,
@@ -983,7 +993,16 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
if (!dport)
return ERR_PTR(-ENOMEM);
- if (rcrb != CXL_RESOURCE_NONE) {
+ dport->dport_dev = dport_dev;
+ dport->port_id = port_id;
+ dport->port = port;
+
+ if (rcrb == CXL_RESOURCE_NONE) {
+ rc = cxl_dport_setup_regs(&port->dev, dport,
+ component_reg_phys);
+ if (rc)
+ return ERR_PTR(rc);
+ } else {
dport->rcrb.base = rcrb;
component_reg_phys = __rcrb_to_component(dport_dev, &dport->rcrb,
CXL_RCRB_DOWNSTREAM);
@@ -992,6 +1011,14 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
return ERR_PTR(-ENXIO);
}
+ /*
+ * RCH @dport is not ready to map until associated with its
+ * memdev
+ */
+ rc = cxl_dport_setup_regs(NULL, dport, component_reg_phys);
+ if (rc)
+ return ERR_PTR(rc);
+
dport->rch = true;
}
@@ -999,14 +1026,6 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
dev_dbg(dport_dev, "Component Registers found for dport: %pa\n",
&component_reg_phys);
- dport->dport_dev = dport_dev;
- dport->port_id = port_id;
- dport->port = port;
-
- rc = cxl_dport_setup_regs(dport, component_reg_phys);
- if (rc)
- return ERR_PTR(rc);
-
cond_cxl_root_lock(port);
rc = add_dport(port, dport);
cond_cxl_root_unlock(port);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index b5b015b661ea..68abf9944383 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -620,7 +620,7 @@ struct cxl_rcrb_info {
/**
* struct cxl_dport - CXL downstream port
* @dport_dev: PCI bridge or firmware device representing the downstream link
- * @comp_map: component register capability mappings
+ * @reg_map: component and ras register mapping parameters
* @port_id: unique hardware identifier for dport in decoder target list
* @rcrb: Data about the Root Complex Register Block layout
* @rch: Indicate whether this dport was enumerated in RCH or VH mode
@@ -628,7 +628,7 @@ struct cxl_rcrb_info {
*/
struct cxl_dport {
struct device *dport_dev;
- struct cxl_register_map comp_map;
+ struct cxl_register_map reg_map;
int port_id;
struct cxl_rcrb_info rcrb;
bool rch;
--
2.30.2
From: Terry Bowman <[email protected]>
The CXL error handler currently only logs endpoint RAS status. The CXL
topology includes several components providing RAS details to be logged
during error handling.[1] Update the current handler's RAS logging to use a
RAS register address. Also, update the error handler function names to be
consistent with correctable and uncorrectable RAS. This will allow for
adding support to log other CXL component's RAS details in the future.
[1] CXL3.0 Table 8-22 CXL_Capability_ID Assignment
Co-developed-by: Robert Richter <[email protected]>
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/cxl/core/pci.c | 44 +++++++++++++++++++++++++++++-------------
1 file changed, 31 insertions(+), 13 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 4c6c5c7ba5a3..2b8883288539 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -646,32 +646,36 @@ void read_cdat_data(struct cxl_port *port)
}
EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
-void cxl_cor_error_detected(struct pci_dev *pdev)
+static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
+ void __iomem *ras_base)
{
- struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
void __iomem *addr;
u32 status;
- if (!cxlds->regs.ras)
+ if (!ras_base)
return;
- addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
+ addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
status = readl(addr);
if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
trace_cxl_aer_correctable_error(cxlds->cxlmd, status);
}
}
-EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL);
+
+static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds)
+{
+ return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras);
+}
/* CXL spec rev3.0 8.2.4.16.1 */
-static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log)
+static void header_log_copy(void __iomem *ras_base, u32 *log)
{
void __iomem *addr;
u32 *log_addr;
int i, log_u32_size = CXL_HEADERLOG_SIZE / sizeof(u32);
- addr = cxlds->regs.ras + CXL_RAS_HEADER_LOG_OFFSET;
+ addr = ras_base + CXL_RAS_HEADER_LOG_OFFSET;
log_addr = log;
for (i = 0; i < log_u32_size; i++) {
@@ -685,17 +689,18 @@ static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log)
* Log the state of the RAS status registers and prepare them to log the
* next error status. Return 1 if reset needed.
*/
-static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
+static bool __cxl_handle_ras(struct cxl_dev_state *cxlds,
+ void __iomem *ras_base)
{
u32 hl[CXL_HEADERLOG_SIZE_U32];
void __iomem *addr;
u32 status;
u32 fe;
- if (!cxlds->regs.ras)
+ if (!ras_base)
return false;
- addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
+ addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
status = readl(addr);
if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))
return false;
@@ -703,7 +708,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
/* If multiple errors, log header points to first error from ctrl reg */
if (hweight32(status) > 1) {
void __iomem *rcc_addr =
- cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
+ ras_base + CXL_RAS_CAP_CONTROL_OFFSET;
fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
readl(rcc_addr)));
@@ -711,13 +716,18 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
fe = status;
}
- header_log_copy(cxlds, hl);
+ header_log_copy(ras_base, hl);
trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl);
writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
return true;
}
+static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
+{
+ return __cxl_handle_ras(cxlds, cxlds->regs.ras);
+}
+
#ifdef CONFIG_PCIEAER_CXL
void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
@@ -733,6 +743,14 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
#endif
+void cxl_cor_error_detected(struct pci_dev *pdev)
+{
+ struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+
+ cxl_handle_endpoint_cor_ras(cxlds);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL);
+
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
@@ -747,7 +765,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
* chance the situation is recoverable dump the status of the RAS
* capability registers and bounce the active state of the memdev.
*/
- ue = cxl_report_and_clear(cxlds);
+ ue = cxl_handle_endpoint_ras(cxlds);
switch (state) {
case pci_channel_io_normal:
--
2.30.2
The primary role of @dev is to host the mappings for devm operations.
@dev is too ambiguous as a name. I.e. when does @dev refer to the
'struct device *' instance that the registers belong, and when does
@dev refer to the 'struct device *' instance hosting the mapping for
devm operations?
Clarify the role of @dev in cxl_register_map by renaming it to @host.
Also, rename local variables to 'host' where map->host is used.
Add Fixes: tag as the fix in the next patch depends on this change.
Fixes: 5d2ffbe4b81a ("cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport")
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
---
drivers/cxl/core/hdm.c | 2 +-
drivers/cxl/core/port.c | 4 ++--
drivers/cxl/core/regs.c | 28 ++++++++++++++--------------
drivers/cxl/cxl.h | 4 ++--
drivers/cxl/pci.c | 2 +-
5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 4449b34a80cc..11d9971f3e8c 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -85,7 +85,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
struct cxl_component_regs *regs)
{
struct cxl_register_map map = {
- .dev = &port->dev,
+ .host = &port->dev,
.resource = port->component_reg_phys,
.base = crb,
.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index d4572a02989a..033651a5da30 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -691,14 +691,14 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
return ERR_PTR(rc);
}
-static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
+static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,
resource_size_t component_reg_phys)
{
if (component_reg_phys == CXL_RESOURCE_NONE)
return 0;
*map = (struct cxl_register_map) {
- .dev = dev,
+ .host = host,
.reg_type = CXL_REGLOC_RBI_COMPONENT,
.resource = component_reg_phys,
.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 6281127b3e9d..e0fbe964f6f0 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -204,7 +204,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
struct cxl_component_regs *regs,
unsigned long map_mask)
{
- struct device *dev = map->dev;
+ struct device *host = map->host;
struct mapinfo {
const struct cxl_reg_map *rmap;
void __iomem **addr;
@@ -225,7 +225,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
continue;
phys_addr = map->resource + mi->rmap->offset;
length = mi->rmap->size;
- *(mi->addr) = devm_cxl_iomap_block(dev, phys_addr, length);
+ *(mi->addr) = devm_cxl_iomap_block(host, phys_addr, length);
if (!*(mi->addr))
return -ENOMEM;
}
@@ -237,7 +237,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
int cxl_map_device_regs(const struct cxl_register_map *map,
struct cxl_device_regs *regs)
{
- struct device *dev = map->dev;
+ struct device *host = map->host;
resource_size_t phys_addr = map->resource;
struct mapinfo {
const struct cxl_reg_map *rmap;
@@ -259,7 +259,7 @@ int cxl_map_device_regs(const struct cxl_register_map *map,
addr = phys_addr + mi->rmap->offset;
length = mi->rmap->size;
- *(mi->addr) = devm_cxl_iomap_block(dev, addr, length);
+ *(mi->addr) = devm_cxl_iomap_block(host, addr, length);
if (!*(mi->addr))
return -ENOMEM;
}
@@ -309,7 +309,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
int regloc, i;
*map = (struct cxl_register_map) {
- .dev = &pdev->dev,
+ .host = &pdev->dev,
.resource = CXL_RESOURCE_NONE,
};
@@ -403,15 +403,15 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_pmu_regs, CXL);
static int cxl_map_regblock(struct cxl_register_map *map)
{
- struct device *dev = map->dev;
+ struct device *host = map->host;
map->base = ioremap(map->resource, map->max_size);
if (!map->base) {
- dev_err(dev, "failed to map registers\n");
+ dev_err(host, "failed to map registers\n");
return -ENOMEM;
}
- dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource);
+ dev_dbg(host, "Mapped CXL Memory Device resource %pa\n", &map->resource);
return 0;
}
@@ -425,28 +425,28 @@ static int cxl_probe_regs(struct cxl_register_map *map)
{
struct cxl_component_reg_map *comp_map;
struct cxl_device_reg_map *dev_map;
- struct device *dev = map->dev;
+ struct device *host = map->host;
void __iomem *base = map->base;
switch (map->reg_type) {
case CXL_REGLOC_RBI_COMPONENT:
comp_map = &map->component_map;
- cxl_probe_component_regs(dev, base, comp_map);
- dev_dbg(dev, "Set up component registers\n");
+ cxl_probe_component_regs(host, base, comp_map);
+ dev_dbg(host, "Set up component registers\n");
break;
case CXL_REGLOC_RBI_MEMDEV:
dev_map = &map->device_map;
- cxl_probe_device_regs(dev, base, dev_map);
+ cxl_probe_device_regs(host, base, dev_map);
if (!dev_map->status.valid || !dev_map->mbox.valid ||
!dev_map->memdev.valid) {
- dev_err(dev, "registers not found: %s%s%s\n",
+ dev_err(host, "registers not found: %s%s%s\n",
!dev_map->status.valid ? "status " : "",
!dev_map->mbox.valid ? "mbox " : "",
!dev_map->memdev.valid ? "memdev " : "");
return -ENXIO;
}
- dev_dbg(dev, "Probing device registers...\n");
+ dev_dbg(host, "Probing device registers...\n");
break;
default:
break;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 76d92561af29..b5b015b661ea 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -247,7 +247,7 @@ struct cxl_pmu_reg_map {
/**
* struct cxl_register_map - DVSEC harvested register block mapping parameters
- * @dev: device for devm operations and logging
+ * @host: device for devm operations and logging
* @base: virtual base of the register-block-BAR + @block_offset
* @resource: physical resource base of the register block
* @max_size: maximum mapping size to perform register search
@@ -257,7 +257,7 @@ struct cxl_pmu_reg_map {
* @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
*/
struct cxl_register_map {
- struct device *dev;
+ struct device *host;
void __iomem *base;
resource_size_t resource;
resource_size_t max_size;
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 44a21ab7add5..f9d852957809 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -484,7 +484,7 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
resource_size_t component_reg_phys;
*map = (struct cxl_register_map) {
- .dev = &pdev->dev,
+ .host = &pdev->dev,
.resource = CXL_RESOURCE_NONE,
};
--
2.30.2
From: Terry Bowman <[email protected]>
RCH downstream port error logging is missing in the current CXL driver. The
missing AER and RAS error logging is needed for communicating driver error
details to userspace. Update the driver to include PCIe AER and CXL RAS
error logging.
Add RCH downstream port error handling into the existing RCiEP handler.
The downstream port error handler is added to the RCiEP error handler
because the downstream port is implemented in a RCRB, is not PCI
enumerable, and as a result is not directly accessible to the PCI AER
root port driver. The AER root port driver calls the RCiEP handler for
handling RCD errors and RCH downstream port protocol errors.
Update existing RCiEP correctable and uncorrectable handlers to also call
the RCH handler. The RCH handler will read the RCH AER registers, check for
error severity, and if an error exists will log using an existing kernel
AER trace routine. The RCH handler will also log downstream port RAS errors
if they exist.
Co-developed-by: Robert Richter <[email protected]>
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/cxl/core/pci.c | 96 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 2af7ad77b273..8d849c8bf8fb 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -777,12 +777,105 @@ void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
+static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds,
+ struct cxl_dport *dport)
+{
+ return __cxl_handle_cor_ras(cxlds, dport->regs.ras);
+}
+
+static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds,
+ struct cxl_dport *dport)
+{
+ return __cxl_handle_ras(cxlds, dport->regs.ras);
+}
+
+/*
+ * Copy the AER capability registers using 32 bit read accesses.
+ * This is necessary because RCRB AER capability is MMIO mapped. Clear the
+ * status after copying.
+ *
+ * @aer_base: base address of AER capability block in RCRB
+ * @aer_regs: destination for copying AER capability
+ */
+static bool cxl_rch_get_aer_info(void __iomem *aer_base,
+ struct aer_capability_regs *aer_regs)
+{
+ int read_cnt = sizeof(struct aer_capability_regs) / sizeof(u32);
+ u32 *aer_regs_buf = (u32 *)aer_regs;
+ int n;
+
+ if (!aer_base)
+ return false;
+
+ /* Use readl() to guarantee 32-bit accesses */
+ for (n = 0; n < read_cnt; n++)
+ aer_regs_buf[n] = readl(aer_base + n * sizeof(u32));
+
+ writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS);
+ writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS);
+
+ return true;
+}
+
+/* Get AER severity. Return false if there is no error. */
+static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs,
+ int *severity)
+{
+ if (aer_regs->uncor_status & ~aer_regs->uncor_mask) {
+ if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV)
+ *severity = AER_FATAL;
+ else
+ *severity = AER_NONFATAL;
+ return true;
+ }
+
+ if (aer_regs->cor_status & ~aer_regs->cor_mask) {
+ *severity = AER_CORRECTABLE;
+ return true;
+ }
+
+ return false;
+}
+
+static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
+{
+ struct pci_dev *pdev = to_pci_dev(cxlds->dev);
+ struct aer_capability_regs aer_regs;
+ struct cxl_dport *dport;
+ struct cxl_port *port;
+ int severity;
+
+ port = cxl_pci_find_port(pdev, &dport);
+ if (!port)
+ return;
+
+ put_device(&port->dev);
+
+ if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs))
+ return;
+
+ if (!cxl_rch_get_aer_severity(&aer_regs, &severity))
+ return;
+
+ pci_print_aer(pdev, severity, &aer_regs);
+
+ if (severity == AER_CORRECTABLE)
+ cxl_handle_rdport_cor_ras(cxlds, dport);
+ else
+ cxl_handle_rdport_ras(cxlds, dport);
+}
+
+#else
+static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }
#endif
void cxl_cor_error_detected(struct pci_dev *pdev)
{
struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+ if (cxlds->rcd)
+ cxl_handle_rdport_errors(cxlds);
+
cxl_handle_endpoint_cor_ras(cxlds);
}
EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL);
@@ -795,6 +888,9 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
struct device *dev = &cxlmd->dev;
bool ue;
+ if (cxlds->rcd)
+ cxl_handle_rdport_errors(cxlds);
+
/*
* A frozen channel indicates an impending reset which is fatal to
* CXL.mem operation, and will likely crash the system. On the off
--
2.30.2
Name the field @reg_map, because @reg_map->host will be used for
mapping operations beyond component registers (i.e. AER registers).
This is valid for all occurrences of @comp_map. Change them all.
Signed-off-by: Robert Richter <[email protected]>
---
drivers/cxl/core/port.c | 2 +-
drivers/cxl/cxl.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 99df86d72dbc..b993dea61436 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -712,7 +712,7 @@ static int cxl_port_setup_regs(struct cxl_port *port,
{
if (dev_is_platform(port->uport_dev))
return 0;
- return cxl_setup_comp_regs(&port->dev, &port->comp_map,
+ return cxl_setup_comp_regs(&port->dev, &port->reg_map,
component_reg_phys);
}
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 68abf9944383..3a51b58a66d0 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -572,7 +572,7 @@ struct cxl_dax_region {
* @regions: cxl_region_ref instances, regions mapped by this port
* @parent_dport: dport that points to this port in the parent
* @decoder_ida: allocator for decoder ids
- * @comp_map: component register capability mappings
+ * @reg_map: component and ras register mapping parameters
* @nr_dports: number of entries in @dports
* @hdm_end: track last allocated HDM decoder instance for allocation ordering
* @commit_end: cursor to track highest committed decoder for commit ordering
@@ -592,7 +592,7 @@ struct cxl_port {
struct xarray regions;
struct cxl_dport *parent_dport;
struct ida decoder_ida;
- struct cxl_register_map comp_map;
+ struct cxl_register_map reg_map;
int nr_dports;
int hdm_end;
int commit_end;
--
2.30.2
From: Terry Bowman <[email protected]>
The restricted CXL host (RCH) error handler will log protocol errors
using AER and RAS status registers. The AER and RAS registers need to
be virtually memory mapped before enabling interrupts. Create the
initializer function devm_cxl_setup_parent_dport() for this when the
endpoint is connected with the dport. The initialization sets up the
RCH RAS and AER mappings.
Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
the RCH downstream port's AER and RAS registers.
Co-developed-by: Robert Richter <[email protected]>
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
---
drivers/cxl/core/pci.c | 36 ++++++++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 10 ++++++++++
2 files changed, 46 insertions(+)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 2b8883288539..2af7ad77b273 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -5,6 +5,7 @@
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/pci-doe.h>
+#include <linux/aer.h>
#include <cxlpci.h>
#include <cxlmem.h>
#include <cxl.h>
@@ -730,6 +731,38 @@ static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
#ifdef CONFIG_PCIEAER_CXL
+static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
+{
+ struct cxl_rcrb_info *ri = &dport->rcrb;
+ void __iomem *dport_aer = NULL;
+ resource_size_t aer_phys;
+ struct device *host;
+
+ if (dport->rch && ri->aer_cap) {
+ host = dport->reg_map.host;
+ aer_phys = ri->aer_cap + ri->base;
+ dport_aer = devm_cxl_iomap_block(host, aer_phys,
+ sizeof(struct aer_capability_regs));
+ }
+
+ dport->regs.dport_aer = dport_aer;
+}
+
+static void cxl_dport_map_regs(struct cxl_dport *dport)
+{
+ struct cxl_register_map *map = &dport->reg_map;
+ struct device *dev = dport->dport_dev;
+
+ if (!map->component_map.ras.valid)
+ dev_dbg(dev, "RAS registers not found\n");
+ else if (cxl_map_component_regs(map, &dport->regs.component,
+ BIT(CXL_CM_CAP_CAP_ID_RAS)))
+ dev_dbg(dev, "Failed to map RAS capability.\n");
+
+ if (dport->rch)
+ cxl_dport_map_rch_aer(dport);
+}
+
void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
{
struct device *dport_dev = dport->dport_dev;
@@ -738,6 +771,9 @@ void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
host_bridge = to_pci_host_bridge(dport_dev);
if (host_bridge->native_cxl_error)
dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);
+
+ dport->reg_map.host = host;
+ cxl_dport_map_regs(dport);
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index cfa2f6bede41..7c2c195592d6 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -221,6 +221,14 @@ struct cxl_regs {
struct_group_tagged(cxl_pmu_regs, pmu_regs,
void __iomem *pmu;
);
+
+ /*
+ * RCH downstream port specific RAS register
+ * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
+ */
+ struct_group_tagged(cxl_rch_regs, rch_regs,
+ void __iomem *dport_aer;
+ );
};
struct cxl_reg_map {
@@ -623,6 +631,7 @@ struct cxl_rcrb_info {
* @rcrb: Data about the Root Complex Register Block layout
* @rch: Indicate whether this dport was enumerated in RCH or VH mode
* @port: reference to cxl_port that contains this downstream port
+ * @regs: Dport parsed register blocks
*/
struct cxl_dport {
struct device *dport_dev;
@@ -631,6 +640,7 @@ struct cxl_dport {
struct cxl_rcrb_info rcrb;
bool rch;
struct cxl_port *port;
+ struct cxl_regs regs;
};
/**
--
2.30.2
From: Terry Bowman <[email protected]>
Restricted CXL host (RCH) downstream port AER information is not currently
logged while in the error state. One problem preventing the error logging
is the AER and RAS registers are not accessible. The CXL driver requires
changes to find RCH downstream port AER and RAS registers for purpose of
error logging.
RCH downstream ports are not enumerated during a PCI bus scan and are
instead discovered using system firmware, ACPI in this case.[1] The
downstream port is implemented as a Root Complex Register Block (RCRB).
The RCRB is a 4k memory block containing PCIe registers based on the PCIe
root port.[2] The RCRB includes AER extended capability registers used for
reporting errors. Note, the RCH's AER Capability is located in the RCRB
memory space instead of PCI configuration space, thus its register access
is different. Existing kernel PCIe AER functions can not be used to manage
the downstream port AER capabilities and RAS registers because the port was
not enumerated during PCI scan and the registers are not PCI config
accessible.
Discover RCH downstream port AER extended capability registers. Use MMIO
accesses to search for extended AER capability in RCRB register space.
[1] CXL 3.0 Spec, 9.11.2 - System Firmware View of CXL 1.1 Hierarchy
[2] CXL 3.0 Spec, 8.2.1.1 - RCH Downstream Port RCRB
Co-developed-by: Robert Richter <[email protected]>
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/cxl/core/core.h | 1 +
drivers/cxl/core/pci.c | 6 ++++++
drivers/cxl/core/regs.c | 35 +++++++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 45e7e044cf4a..f470ef5c0a6a 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -73,6 +73,7 @@ struct cxl_rcrb_info;
resource_size_t __rcrb_to_component(struct device *dev,
struct cxl_rcrb_info *ri,
enum cxl_rcrb which);
+u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
extern struct rw_semaphore cxl_dpa_rwsem;
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 6ba3b7370816..4c6c5c7ba5a3 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -722,6 +722,12 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
{
+ struct device *dport_dev = dport->dport_dev;
+ struct pci_host_bridge *host_bridge;
+
+ host_bridge = to_pci_host_bridge(dport_dev);
+ if (host_bridge->native_cxl_error)
+ dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index e0fbe964f6f0..6e502f02899b 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -470,6 +470,41 @@ int cxl_setup_regs(struct cxl_register_map *map)
}
EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
+u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb)
+{
+ void __iomem *addr;
+ u16 offset = 0;
+ u32 cap_hdr;
+
+ if (WARN_ON_ONCE(rcrb == CXL_RESOURCE_NONE))
+ return 0;
+
+ if (!request_mem_region(rcrb, SZ_4K, dev_name(dev)))
+ return 0;
+
+ addr = ioremap(rcrb, SZ_4K);
+ if (!addr) {
+ release_mem_region(rcrb, SZ_4K);
+ return 0;
+ }
+
+ cap_hdr = readl(addr + offset);
+ while (PCI_EXT_CAP_ID(cap_hdr) != PCI_EXT_CAP_ID_ERR) {
+ offset = PCI_EXT_CAP_NEXT(cap_hdr);
+ if (!offset)
+ break;
+ cap_hdr = readl(addr + offset);
+ }
+
+ if (offset)
+ dev_dbg(dev, "found AER extended capability (0x%x)\n", offset);
+
+ iounmap(addr);
+ release_mem_region(rcrb, SZ_4K);
+
+ return offset;
+}
+
resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri,
enum cxl_rcrb which)
{
--
2.30.2
From: Terry Bowman <[email protected]>
The RCH root port contains root command AER registers that should not be
enabled.[1] Disable these to prevent root port interrupts.
[1] CXL 3.0 - 12.2.1.1 RCH Downstream Port-detected Errors
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/cxl/core/pci.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 8d849c8bf8fb..61e443aff0eb 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -763,6 +763,35 @@ static void cxl_dport_map_regs(struct cxl_dport *dport)
cxl_dport_map_rch_aer(dport);
}
+static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
+{
+ void __iomem *aer_base = dport->regs.dport_aer;
+ struct pci_host_bridge *bridge;
+ u32 aer_cmd_mask, aer_cmd;
+
+ if (!aer_base)
+ return;
+
+ bridge = to_pci_host_bridge(dport->dport_dev);
+
+ /*
+ * Disable RCH root port command interrupts.
+ * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
+ *
+ * This sequence may not be necessary. CXL spec states disabling
+ * the root cmd register's interrupts is required. But, PCI spec
+ * shows these are disabled by default on reset.
+ */
+ if (bridge->native_cxl_error) {
+ aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
+ PCI_ERR_ROOT_CMD_NONFATAL_EN |
+ PCI_ERR_ROOT_CMD_FATAL_EN);
+ aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
+ aer_cmd &= ~aer_cmd_mask;
+ writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
+ }
+}
+
void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
{
struct device *dport_dev = dport->dport_dev;
@@ -774,6 +803,9 @@ void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
dport->reg_map.host = host;
cxl_dport_map_regs(dport);
+
+ if (dport->rch)
+ cxl_disable_rch_root_ints(dport);
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
--
2.30.2
The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @reg_map instead. Remove the base address.
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/cxl/cxlmem.h | 2 --
drivers/cxl/pci.c | 3 ---
tools/testing/cxl/test/mem.c | 1 -
3 files changed, 6 deletions(-)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 8fb8db47c3b7..cfd287466fa8 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -405,7 +405,6 @@ enum cxl_devtype {
* @dpa_res: Overall DPA resource tree for the device
* @pmem_res: Active Persistent memory capacity configuration
* @ram_res: Active Volatile memory capacity configuration
- * @component_reg_phys: register base of component registers
* @serial: PCIe Device Serial Number
* @type: Generic Memory Class device or Vendor Specific Memory device
*/
@@ -420,7 +419,6 @@ struct cxl_dev_state {
struct resource dpa_res;
struct resource pmem_res;
struct resource ram_res;
- resource_size_t component_reg_phys;
u64 serial;
enum cxl_devtype type;
};
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index a6ad9bcb96b4..037792e941f2 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -834,7 +834,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
* If the component registers can't be found, the cxl_pci driver may
* still be useful for management functions so don't return an error.
*/
- cxlds->component_reg_phys = CXL_RESOURCE_NONE;
rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
&cxlds->reg_map);
if (rc)
@@ -842,8 +841,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
else if (!cxlds->reg_map.component_map.ras.valid)
dev_dbg(&pdev->dev, "RAS registers not found\n");
- cxlds->component_reg_phys = cxlds->reg_map.resource;
-
rc = cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component,
BIT(CXL_CM_CAP_CAP_ID_RAS));
if (rc)
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 464fc39ed277..aa44d111fd28 100644
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -1423,7 +1423,6 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
cxlds->serial = pdev->id;
if (is_rcd(pdev)) {
cxlds->rcd = true;
- cxlds->component_reg_phys = CXL_RESOURCE_NONE;
}
rc = cxl_enumerate_cmds(mds);
--
2.30.2
Trivial change that renames variable phys_addr in
cxl_map_component_regs() to shorten its length to keep the 80 char
size limit for the line and also for consistency between the different
paths.
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
---
drivers/cxl/core/regs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 6e502f02899b..7b56f6f28ab1 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -216,16 +216,16 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
for (i = 0; i < ARRAY_SIZE(mapinfo); i++) {
struct mapinfo *mi = &mapinfo[i];
- resource_size_t phys_addr;
+ resource_size_t addr;
resource_size_t length;
if (!mi->rmap->valid)
continue;
if (!test_bit(mi->rmap->id, &map_mask))
continue;
- phys_addr = map->resource + mi->rmap->offset;
+ addr = map->resource + mi->rmap->offset;
length = mi->rmap->size;
- *(mi->addr) = devm_cxl_iomap_block(host, phys_addr, length);
+ *(mi->addr) = devm_cxl_iomap_block(host, addr, length);
if (!*(mi->addr))
return -ENOMEM;
}
--
2.30.2
In Restricted CXL Device (RCD) mode a CXL device is exposed as an
RCiEP, but CXL downstream and upstream ports are not enumerated and
not visible in the PCIe hierarchy. [1] Protocol and link errors from
these non-enumerated ports are signaled as internal AER errors, either
Uncorrectable Internal Error (UIE) or Corrected Internal Errors (CIE)
via an RCEC.
Restricted CXL host (RCH) downstream port-detected errors have the
Requester ID of the RCEC set in the RCEC's AER Error Source ID
register. A CXL handler must then inspect the error status in various
CXL registers residing in the dport's component register space (CXL
RAS capability) or the dport's RCRB (PCIe AER extended
capability). [2]
Errors showing up in the RCEC's error handler must be handled and
connected to the CXL subsystem. Implement this by forwarding the error
to all CXL devices below the RCEC. Since the entire CXL device is
controlled only using PCIe Configuration Space of device 0, function
0, only pass it there [3]. The error handling is limited to currently
supported devices with the Memory Device class code set (CXL Type 3
Device, PCI_CLASS_MEMORY_CXL, 502h), handle downstream port errors in
the device's cxl_pci driver. Support for other CXL Device Types
(e.g. a CXL.cache Device) can be added later.
To handle downstream port errors in addition to errors directed to the
CXL endpoint device, a handler must also inspect the CXL RAS and PCIe
AER capabilities of the CXL downstream port the device is connected
to.
Since CXL downstream port errors are signaled using internal errors,
the handler requires those errors to be unmasked. This is subject of a
follow-on patch.
The reason for choosing this implementation is that the AER service
driver claims the RCEC device, but does not allow it to register a
custom specific handler to support CXL. Connecting the RCEC hard-wired
with a CXL handler does not work, as the CXL subsystem might not be
present all the time. The alternative to add an implementation to the
portdrv to allow the registration of a custom RCEC error handler isn't
worth doing it as CXL would be its only user. Instead, just check for
an CXL RCEC and pass it down to the connected CXL device's error
handler. With this approach the code can entirely be implemented in
the PCIe AER driver and is independent of the CXL subsystem. The CXL
driver only provides the handler.
[1] CXL 3.0 spec: 9.11.8 CXL Devices Attached to an RCH
[2] CXL 3.0 spec, 12.2.1.1 RCH Downstream Port-detected Errors
[3] CXL 3.0 spec, 8.1.3 PCIe DVSEC for CXL Devices
Co-developed-by: Terry Bowman <[email protected]>
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Cc: "Oliver O'Halloran" <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: [email protected]
Cc: [email protected]
Acked-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/pci/pcie/Kconfig | 9 ++++
drivers/pci/pcie/aer.c | 96 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 103 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 228652a59f27..8999fcebde6a 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -49,6 +49,15 @@ config PCIEAER_INJECT
gotten from:
https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
+config PCIEAER_CXL
+ bool "PCI Express CXL RAS support"
+ default y
+ depends on PCIEAER && CXL_PCI
+ help
+ Enables CXL error handling.
+
+ If unsure, say Y.
+
#
# PCI Express ECRC
#
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 6593fe3fc555..9f420733996b 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -934,14 +934,100 @@ static bool find_source_device(struct pci_dev *parent,
return true;
}
+#ifdef CONFIG_PCIEAER_CXL
+
+static bool is_cxl_mem_dev(struct pci_dev *dev)
+{
+ /*
+ * The capability, status, and control fields in Device 0,
+ * Function 0 DVSEC control the CXL functionality of the
+ * entire device (CXL 3.0, 8.1.3).
+ */
+ if (dev->devfn != PCI_DEVFN(0, 0))
+ return false;
+
+ /*
+ * CXL Memory Devices must have the 502h class code set (CXL
+ * 3.0, 8.1.12.1).
+ */
+ if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL)
+ return false;
+
+ return true;
+}
+
+static bool cxl_error_is_native(struct pci_dev *dev)
+{
+ struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
+
+ if (pcie_ports_native)
+ return true;
+
+ return host->native_aer && host->native_cxl_error;
+}
+
+static bool is_internal_error(struct aer_err_info *info)
+{
+ if (info->severity == AER_CORRECTABLE)
+ return info->status & PCI_ERR_COR_INTERNAL;
+
+ return info->status & PCI_ERR_UNC_INTN;
+}
+
+static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
+{
+ struct aer_err_info *info = (struct aer_err_info *)data;
+ const struct pci_error_handlers *err_handler;
+
+ if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
+ return 0;
+
+ /* protect dev->driver */
+ device_lock(&dev->dev);
+
+ err_handler = dev->driver ? dev->driver->err_handler : NULL;
+ if (!err_handler)
+ goto out;
+
+ if (info->severity == AER_CORRECTABLE) {
+ if (err_handler->cor_error_detected)
+ err_handler->cor_error_detected(dev);
+ } else if (err_handler->error_detected) {
+ if (info->severity == AER_NONFATAL)
+ err_handler->error_detected(dev, pci_channel_io_normal);
+ else if (info->severity == AER_FATAL)
+ err_handler->error_detected(dev, pci_channel_io_frozen);
+ }
+out:
+ device_unlock(&dev->dev);
+ return 0;
+}
+
+static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
+{
+ /*
+ * Internal errors of an RCEC indicate an AER error in an
+ * RCH's downstream port. Check and handle them in the CXL.mem
+ * device driver.
+ */
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC &&
+ is_internal_error(info))
+ pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
+}
+
+#else
+static inline void cxl_rch_handle_error(struct pci_dev *dev,
+ struct aer_err_info *info) { }
+#endif
+
/**
- * handle_error_source - handle logging error into an event log
+ * pci_aer_handle_error - handle logging error into an event log
* @dev: pointer to pci_dev data structure of error source device
* @info: comprehensive error information
*
* Invoked when an error being detected by Root Port.
*/
-static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
+static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info)
{
int aer = dev->aer_cap;
@@ -965,6 +1051,12 @@ static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
else if (info->severity == AER_FATAL)
pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
+}
+
+static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
+{
+ cxl_rch_handle_error(dev, info);
+ pci_aer_handle_error(dev, info);
pci_dev_put(dev);
}
--
2.30.2
CXL error handling depends on AER.
Introduce config option PCIEAER_CXL in preparation of the AER dport
error handling. Also, introduce the stub function
devm_cxl_setup_parent_dport() to setup dports.
This is in preparation of follow on patches.
Note the Kconfg part of the option is added in a later patch to enable
it once coding of the feature is complete.
Signed-off-by: Robert Richter <[email protected]>
---
drivers/cxl/core/pci.c | 9 +++++++++
drivers/cxl/cxl.h | 7 +++++++
drivers/cxl/mem.c | 2 ++
3 files changed, 18 insertions(+)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index c7a7887ebdcf..6ba3b7370816 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -718,6 +718,15 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
return true;
}
+#ifdef CONFIG_PCIEAER_CXL
+
+void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
+{
+}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
+
+#endif
+
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index c07064e0c136..cfa2f6bede41 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -704,6 +704,13 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
struct device *dport_dev, int port_id,
resource_size_t rcrb);
+#ifdef CONFIG_PCIEAER_CXL
+void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
+#else
+static inline void devm_cxl_setup_parent_dport(struct device *host,
+ struct cxl_dport *dport) { }
+#endif
+
struct cxl_decoder *to_cxl_decoder(struct device *dev);
struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 04107058739b..61ca21c020fa 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -157,6 +157,8 @@ static int cxl_mem_probe(struct device *dev)
else
endpoint_parent = &parent_port->dev;
+ devm_cxl_setup_parent_dport(dev, dport);
+
device_lock(endpoint_parent);
if (!endpoint_parent->driver) {
dev_err(dev, "CXL port topology %s not enabled\n",
--
2.30.2
AER corrected and uncorrectable internal errors (CIE/UIE) are masked
in their corresponding mask registers per default once in power-up
state. [1][2] Enable internal errors for RCECs to receive CXL
downstream port errors of Restricted CXL Hosts (RCHs).
[1] CXL 3.0 Spec, 12.2.1.1 - RCH Downstream Port Detected Errors
[2] PCIe Base Spec r6.0, 7.8.4.3 Uncorrectable Error Mask Register,
7.8.4.6 Correctable Error Mask Register
Co-developed-by: Terry Bowman <[email protected]>
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/pci/pcie/aer.c | 57 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 9f420733996b..de63cda8f453 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -936,6 +936,30 @@ static bool find_source_device(struct pci_dev *parent,
#ifdef CONFIG_PCIEAER_CXL
+/**
+ * pci_aer_unmask_internal_errors - unmask internal errors
+ * @dev: pointer to the pcie_dev data structure
+ *
+ * Unmasks internal errors in the Uncorrectable and Correctable Error
+ * Mask registers.
+ *
+ * Note: AER must be enabled and supported by the device which must be
+ * checked in advance, e.g. with pcie_aer_is_native().
+ */
+static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
+{
+ int aer = dev->aer_cap;
+ u32 mask;
+
+ pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
+ mask &= ~PCI_ERR_UNC_INTN;
+ pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);
+
+ pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
+ mask &= ~PCI_ERR_COR_INTERNAL;
+ pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
+}
+
static bool is_cxl_mem_dev(struct pci_dev *dev)
{
/*
@@ -1015,7 +1039,39 @@ static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
}
+static int handles_cxl_error_iter(struct pci_dev *dev, void *data)
+{
+ bool *handles_cxl = data;
+
+ if (!*handles_cxl)
+ *handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev);
+
+ /* Non-zero terminates iteration */
+ return *handles_cxl;
+}
+
+static bool handles_cxl_errors(struct pci_dev *rcec)
+{
+ bool handles_cxl = false;
+
+ if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC &&
+ pcie_aer_is_native(rcec))
+ pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl);
+
+ return handles_cxl;
+}
+
+static void cxl_rch_enable_rcec(struct pci_dev *rcec)
+{
+ if (!handles_cxl_errors(rcec))
+ return;
+
+ pci_aer_unmask_internal_errors(rcec);
+ pci_info(rcec, "CXL: Internal errors unmasked");
+}
+
#else
+static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { }
static inline void cxl_rch_handle_error(struct pci_dev *dev,
struct aer_err_info *info) { }
#endif
@@ -1415,6 +1471,7 @@ static int aer_probe(struct pcie_device *dev)
return status;
}
+ cxl_rch_enable_rcec(port);
aer_enable_rootport(rpc);
pci_info(port, "enabled with IRQ %d\n", dev->irq);
return 0;
--
2.30.2
From: Terry Bowman <[email protected]>
The CXL driver plans to use cper_print_aer() for logging restricted CXL
host (RCH) AER errors. cper_print_aer() is not currently exported and
therefore not usable by the CXL drivers built as loadable modules. Export
the cper_print_aer() function. Use the EXPORT_SYMBOL_NS_GPL() variant
to restrict the export to CXL drivers.
The CONFIG_ACPI_APEI_PCIEAER kernel config is currently used to enable
cper_print_aer(). cper_print_aer() logs the AER registers and is
useful in PCIE AER logging outside of APEI. Remove the
CONFIG_ACPI_APEI_PCIEAER dependency to enable cper_print_aer().
The cper_print_aer() function name implies CPER specific use but is useful
in non-CPER cases as well. Rename cper_print_aer() to pci_print_aer().
Also, update cxl_core to import CXL namespace imports.
Co-developed-by: Robert Richter <[email protected]>
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Cc: Mahesh J Salgaonkar <[email protected]>
Cc: "Oliver O'Halloran" <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: [email protected]
Reviewed-by: Jonathan Cameron <[email protected]>
Acked-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/cxl/core/port.c | 1 +
drivers/pci/pcie/aer.c | 9 +++++----
include/linux/aer.h | 2 +-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 41a8aa56cffd..802e85321a63 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -2101,3 +2101,4 @@ static void cxl_core_exit(void)
subsys_initcall(cxl_core_init);
module_exit(cxl_core_exit);
MODULE_LICENSE("GPL v2");
+MODULE_IMPORT_NS(CXL);
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 9c8fd69ae5ad..6593fe3fc555 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -759,9 +759,10 @@ int cper_severity_to_aer(int cper_severity)
}
}
EXPORT_SYMBOL_GPL(cper_severity_to_aer);
+#endif
-void cper_print_aer(struct pci_dev *dev, int aer_severity,
- struct aer_capability_regs *aer)
+void pci_print_aer(struct pci_dev *dev, int aer_severity,
+ struct aer_capability_regs *aer)
{
int layer, agent, tlp_header_valid = 0;
u32 status, mask;
@@ -800,7 +801,7 @@ void cper_print_aer(struct pci_dev *dev, int aer_severity,
trace_aer_event(dev_name(&dev->dev), (status & ~mask),
aer_severity, tlp_header_valid, &aer->header_log);
}
-#endif
+EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL);
/**
* add_error_device - list device to be handled
@@ -996,7 +997,7 @@ static void aer_recover_work_func(struct work_struct *work)
PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
continue;
}
- cper_print_aer(pdev, entry.severity, entry.regs);
+ pci_print_aer(pdev, entry.severity, entry.regs);
if (entry.severity == AER_NONFATAL)
pcie_do_recovery(pdev, pci_channel_io_normal,
aer_root_reset);
diff --git a/include/linux/aer.h b/include/linux/aer.h
index 29cc10220952..f6ea2f57d808 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -51,7 +51,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
#endif
-void cper_print_aer(struct pci_dev *dev, int aer_severity,
+void pci_print_aer(struct pci_dev *dev, int aer_severity,
struct aer_capability_regs *aer);
int cper_severity_to_aer(int cper_severity);
void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
--
2.30.2
The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @reg_map instead. Remove the base address.
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/cxl/core/port.c | 4 +---
drivers/cxl/cxl.h | 2 --
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index f69484d3c93c..41a8aa56cffd 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -619,7 +619,6 @@ static int devm_cxl_link_parent_dport(struct device *host,
static struct lock_class_key cxl_port_key;
static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
- resource_size_t component_reg_phys,
struct cxl_dport *parent_dport)
{
struct cxl_port *port;
@@ -670,7 +669,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
} else
dev->parent = uport_dev;
- port->component_reg_phys = component_reg_phys;
ida_init(&port->decoder_ida);
port->hdm_end = -1;
port->commit_end = -1;
@@ -746,7 +744,7 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
struct device *dev;
int rc;
- port = cxl_port_alloc(uport_dev, component_reg_phys, parent_dport);
+ port = cxl_port_alloc(uport_dev, parent_dport);
if (IS_ERR(port))
return port;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 3a51b58a66d0..c07064e0c136 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -576,7 +576,6 @@ struct cxl_dax_region {
* @nr_dports: number of entries in @dports
* @hdm_end: track last allocated HDM decoder instance for allocation ordering
* @commit_end: cursor to track highest committed decoder for commit ordering
- * @component_reg_phys: component register capability base address (optional)
* @dead: last ep has been removed, force port re-creation
* @depth: How deep this port is relative to the root. depth 0 is the root.
* @cdat: Cached CDAT data
@@ -596,7 +595,6 @@ struct cxl_port {
int nr_dports;
int hdm_end;
int commit_end;
- resource_size_t component_reg_phys;
bool dead;
unsigned int depth;
struct cxl_cdat {
--
2.30.2
Same as for ports and dports, also store the endpoint's Component
Register mappings, use struct cxl_dev_state for that.
Keep the Component Register base address @component_reg_phys a bit to
not break functionality. It will be removed after the transition in a
later patch.
Signed-off-by: Terry Bowman <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
---
drivers/cxl/core/mbox.c | 2 ++
drivers/cxl/cxlmem.h | 2 ++
drivers/cxl/pci.c | 9 +++++----
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 4df4f614f490..7e1c4d6f2e39 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1377,6 +1377,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)
mutex_init(&mds->mbox_mutex);
mutex_init(&mds->event.log_lock);
mds->cxlds.dev = dev;
+ mds->cxlds.reg_map.host = dev;
+ mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
return mds;
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 706f8a6d1ef4..8fb8db47c3b7 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -397,6 +397,7 @@ enum cxl_devtype {
*
* @dev: The device associated with this CXL state
* @cxlmd: The device representing the CXL.mem capabilities of @dev
+ * @reg_map: component and ras register mapping parameters
* @regs: Parsed register blocks
* @cxl_dvsec: Offset to the PCIe device DVSEC
* @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
@@ -411,6 +412,7 @@ enum cxl_devtype {
struct cxl_dev_state {
struct device *dev;
struct cxl_memdev *cxlmd;
+ struct cxl_register_map reg_map;
struct cxl_regs regs;
int cxl_dvsec;
bool rcd;
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index f9d852957809..a6ad9bcb96b4 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -835,15 +835,16 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
* still be useful for management functions so don't return an error.
*/
cxlds->component_reg_phys = CXL_RESOURCE_NONE;
- rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
+ &cxlds->reg_map);
if (rc)
dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
- else if (!map.component_map.ras.valid)
+ else if (!cxlds->reg_map.component_map.ras.valid)
dev_dbg(&pdev->dev, "RAS registers not found\n");
- cxlds->component_reg_phys = map.resource;
+ cxlds->component_reg_phys = cxlds->reg_map.resource;
- rc = cxl_map_component_regs(&map, &cxlds->regs.component,
+ rc = cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component,
BIT(CXL_CM_CAP_CAP_ID_RAS));
if (rc)
dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
--
2.30.2
Dan,
On 27.09.23 17:43:19, Robert Richter wrote:
> Changes in v11:
> - Rebased onto cxl/fixes (c66650d29764)
> - Added: cxl/port: Fix release of RCD endpoints
> - Added: cxl/core/regs: Rename @dev to @host in struct cxl_register_map
> - Added: cxl/port: Fix @host confusion in cxl_dport_setup_regs()
> - Added: cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map
> - Removed: cxl/regs: Prepare for multiple users of register mappings
> - Modified: cxl/hdm: Use stored Component Register mappings to map
> HDM decoder capability
> - Dan: rework to drop cxl_port_get_comp_map()
> - Added: cxl/pci: Introduce config option PCIEAER_CXL
> - Modified: cxl/pci: Add RCH downstream port AER register discovery
> - Moved AER discovery to devm_cxl_setup_parent_dport() called when
> memdev is probed
> - Fixed devm_cxl_iomap_block() release by fixing devm host
> - Modified: cxl/pci: Map RCH downstream AER registers for logging
> protocol errors
> - Reworded description
> - Moved register mappings to devm_cxl_setup_parent_dport() called
> when memdev is probed
> - Modified: cxl/pci: Disable root port interrupts in RCH mode
> - Call cxl_disable_rch_root_ints() in devm_cxl_setup_parent_dport()
> called when memdev is probed
> - Fixed resource release by fixing devm host
> - Reworded description of PCIEAER_CXL config option
> - Added: cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for
> devm
for a v11 this is a major rework. Most of the dport setup is now in
devm_cxl_setup_parent_dport() which is called very late from
cxl_mem_probe(). Also, additional patches with fixes and more
reworks. I saw one failure in the ndctl cxl test suite with qemu, but
decided to send the patches out anyway as a new baseline for review,
testing and debugging. Bear with it as due to its changes the code
need to mature a little.
Thanks,
-Robert
On Wed, 27 Sep 2023 17:43:22 +0200
Robert Richter <[email protected]> wrote:
> From: Dan Williams <[email protected]>
>
> commit 5d2ffbe4b81a ("cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport")
>
> ...moved the dport component registers from a raw component_reg_phys
> passed in at dport instantiation time to a 'struct cxl_register_map'
> populated with both the component register data *and* the "host" device
> for mapping operations.
>
> While typical CXL switch dports are mapped by their associated 'struct
> cxl_port', an RCH host bridge dport registered by cxl_acpi needs to wait
> until the cxl_mem driver makes the attachment to map the registers. This
> is because there are no intervening 'struct cxl_port' instances between
> the root cxl_port and the endpoint port in an RCH topology.
>
> For now just mark the host as NULL in the RCH dport case until code that
> needs to map the dport registers arrives. Name the field @reg_map,
> because @reg_map->host will be used for mapping operations beyond
> component registers (i.e. AER registers).
I'm not keen on a rename buried in here. Its fine in general but as
far as I can see little to do with the rest of what is going on here.
>
> This patch is not flagged for -stable since nothing in the current
> driver uses the dport->reg_map.
>
> Now, I am slightly uneasy that cxl_setup_comp_regs() sets map->host to a
> wrong value and then cxl_dport_setup_regs() fixes it up, but the
> alternatives I came up with are more messy. For example, adding an
> @logdev to 'struct cxl_register_map' that the dev_printk()s can fall
> back to when @host is NULL. I settled on "post-fixup+comment" since it
> is only RCH dports that have this special case where register probing is
> split between a host-bridge RCRB lookup and when cxl_mem_probe() does
> the association of the cxl_memdev and endpoint port.
>
> Fixes: 5d2ffbe4b81a ("cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport")
> Cc: Jonathan Cameron <[email protected]>
> Signed-off-by: Dan Williams <[email protected]>
> [kept dev_dbg() message]
> Signed-off-by: Robert Richter <[email protected]>
Seems right to me otherwise, though I've lost track a little of what was
going on with this... Hence a tentative
Reviewed-by: Jonathan Cameron <[email protected]>
> ---
> drivers/cxl/core/port.c | 43 +++++++++++++++++++++++++++++------------
> drivers/cxl/cxl.h | 4 ++--
> 2 files changed, 33 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 033651a5da30..99df86d72dbc 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -716,13 +716,23 @@ static int cxl_port_setup_regs(struct cxl_port *port,
> component_reg_phys);
> }
>
> -static int cxl_dport_setup_regs(struct cxl_dport *dport,
> +static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport,
> resource_size_t component_reg_phys)
> {
> + int rc;
> +
> if (dev_is_platform(dport->dport_dev))
> return 0;
> - return cxl_setup_comp_regs(dport->dport_dev, &dport->comp_map,
> - component_reg_phys);
> +
> + /*
> + * use @dport->dport_dev for the context for error messages during
> + * register probing, and fixup @host after the fact, since @host may be
> + * NULL.
> + */
> + rc = cxl_setup_comp_regs(dport->dport_dev, &dport->reg_map,
> + component_reg_phys);
> + dport->reg_map.host = host;
> + return rc;
> }
>
> static struct cxl_port *__devm_cxl_add_port(struct device *host,
> @@ -983,7 +993,16 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
> if (!dport)
> return ERR_PTR(-ENOMEM);
>
> - if (rcrb != CXL_RESOURCE_NONE) {
> + dport->dport_dev = dport_dev;
> + dport->port_id = port_id;
> + dport->port = port;
> +
> + if (rcrb == CXL_RESOURCE_NONE) {
> + rc = cxl_dport_setup_regs(&port->dev, dport,
> + component_reg_phys);
> + if (rc)
> + return ERR_PTR(rc);
> + } else {
> dport->rcrb.base = rcrb;
> component_reg_phys = __rcrb_to_component(dport_dev, &dport->rcrb,
> CXL_RCRB_DOWNSTREAM);
> @@ -992,6 +1011,14 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
> return ERR_PTR(-ENXIO);
> }
>
> + /*
> + * RCH @dport is not ready to map until associated with its
> + * memdev
> + */
> + rc = cxl_dport_setup_regs(NULL, dport, component_reg_phys);
> + if (rc)
> + return ERR_PTR(rc);
> +
> dport->rch = true;
> }
>
> @@ -999,14 +1026,6 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
> dev_dbg(dport_dev, "Component Registers found for dport: %pa\n",
> &component_reg_phys);
>
> - dport->dport_dev = dport_dev;
> - dport->port_id = port_id;
> - dport->port = port;
> -
> - rc = cxl_dport_setup_regs(dport, component_reg_phys);
> - if (rc)
> - return ERR_PTR(rc);
> -
> cond_cxl_root_lock(port);
> rc = add_dport(port, dport);
> cond_cxl_root_unlock(port);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index b5b015b661ea..68abf9944383 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -620,7 +620,7 @@ struct cxl_rcrb_info {
> /**
> * struct cxl_dport - CXL downstream port
> * @dport_dev: PCI bridge or firmware device representing the downstream link
> - * @comp_map: component register capability mappings
> + * @reg_map: component and ras register mapping parameters
> * @port_id: unique hardware identifier for dport in decoder target list
> * @rcrb: Data about the Root Complex Register Block layout
> * @rch: Indicate whether this dport was enumerated in RCH or VH mode
> @@ -628,7 +628,7 @@ struct cxl_rcrb_info {
> */
> struct cxl_dport {
> struct device *dport_dev;
> - struct cxl_register_map comp_map;
> + struct cxl_register_map reg_map;
> int port_id;
> struct cxl_rcrb_info rcrb;
> bool rch;
On Wed, 27 Sep 2023 17:43:26 +0200
Robert Richter <[email protected]> wrote:
> Now, that the Component Register mappings are stored, use them to
> enable and map the HDM decoder capabilities. The Component Registers
> do not need to be probed again for this, remove probing code.
>
> The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
> Endpoint's component register mappings are located in the cxlds and
> else in the port's structure. Duplicate the cxlds->reg_map in
> port->reg_map for endpoint ports.
>
> Signed-off-by: Terry Bowman <[email protected]>
> Signed-off-by: Robert Richter <[email protected]>
> Reviewed-by: Dave Jiang <[email protected]>
> [rework to drop cxl_port_get_comp_map()]
> Signed-off-by: Dan Williams <[email protected]>
A few comments inline.
Also, Dan's SoB doesn't make sense if you are the Author and he's not
the one sending the email. The fun of patches bounced back and forwards
is sometimes you have to tweak this stuff on each posting... :(
> ---
> drivers/cxl/core/hdm.c | 48 ++++++++++++++++-------------------------
> drivers/cxl/core/port.c | 29 +++++++++++++++++++------
> drivers/cxl/mem.c | 5 ++---
> 3 files changed, 43 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 11d9971f3e8c..14a0d0017df3 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
> cxlhdm->interleave_mask |= GENMASK(14, 12);
> }
>
> -static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> - struct cxl_component_regs *regs)
> -{
> - struct cxl_register_map map = {
> - .host = &port->dev,
> - .resource = port->component_reg_phys,
> - .base = crb,
> - .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> - };
> -
> - cxl_probe_component_regs(&port->dev, crb, &map.component_map);
> - if (!map.component_map.hdm_decoder.valid) {
> - dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
> - /* unique error code to indicate no HDM decoder capability */
> - return -ENODEV;
> - }
> -
> - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
> -}
> -
> static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> {
> struct cxl_hdm *cxlhdm;
> @@ -155,7 +135,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
> {
> struct device *dev = &port->dev;
> struct cxl_hdm *cxlhdm;
> - void __iomem *crb;
> + struct cxl_register_map *reg_map;
> int rc;
>
> cxlhdm = devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL);
> @@ -164,19 +144,29 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
> cxlhdm->port = port;
> dev_set_drvdata(dev, cxlhdm);
>
> - crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
> - if (!crb && info && info->mem_enabled) {
> - cxlhdm->decoder_count = info->ranges;
> - return cxlhdm;
> - } else if (!crb) {
> + reg_map = &port->reg_map;
Could you set this where it's defined above?
> + if (reg_map->resource == CXL_RESOURCE_NONE) {
A reminder comment on why/when this happens might be a good addition.
> + if (info && info->mem_enabled) {
> + cxlhdm->decoder_count = info->ranges;
> + return cxlhdm;
> + }
Trivial (and true before this patch) but I'd rather see the error path out of line
if (!info || !info->mem_enabled) {
WARN_ON(1);
dev_err(dev, "No ...
...
}
cxlhdm->decoder_count = info->ranges;
return cxlhdm;
}
> + WARN_ON(1);
> dev_err(dev, "No component registers mapped\n");
> return ERR_PTR(-ENXIO);
> }
>
> - rc = map_hdm_decoder_regs(port, crb, &cxlhdm->regs);
> - iounmap(crb);
> - if (rc)
> + if (!reg_map->component_map.hdm_decoder.valid) {
> + dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
> + /* unique error code to indicate no HDM decoder capability */
> + return ERR_PTR(-ENODEV);
> + }
> +
> + rc = cxl_map_component_regs(reg_map, &cxlhdm->regs,
> + BIT(CXL_CM_CAP_CAP_ID_HDM));
> + if (rc) {
> + dev_dbg(dev, "Failed to map HDM capability.\n");
dev_err() seems appropriate here.
> return ERR_PTR(rc);
> + }
>
> parse_hdm_decoder_caps(cxlhdm);
> if (cxlhdm->decoder_count == 0) {
On Wed, 27 Sep 2023 17:43:30 +0200
Robert Richter <[email protected]> wrote:
> From: Terry Bowman <[email protected]>
>
> Restricted CXL host (RCH) downstream port AER information is not currently
> logged while in the error state. One problem preventing the error logging
> is the AER and RAS registers are not accessible. The CXL driver requires
> changes to find RCH downstream port AER and RAS registers for purpose of
> error logging.
>
> RCH downstream ports are not enumerated during a PCI bus scan and are
> instead discovered using system firmware, ACPI in this case.[1] The
> downstream port is implemented as a Root Complex Register Block (RCRB).
> The RCRB is a 4k memory block containing PCIe registers based on the PCIe
> root port.[2] The RCRB includes AER extended capability registers used for
> reporting errors. Note, the RCH's AER Capability is located in the RCRB
> memory space instead of PCI configuration space, thus its register access
> is different. Existing kernel PCIe AER functions can not be used to manage
> the downstream port AER capabilities and RAS registers because the port was
> not enumerated during PCI scan and the registers are not PCI config
> accessible.
>
> Discover RCH downstream port AER extended capability registers. Use MMIO
> accesses to search for extended AER capability in RCRB register space.
>
> [1] CXL 3.0 Spec, 9.11.2 - System Firmware View of CXL 1.1 Hierarchy
> [2] CXL 3.0 Spec, 8.2.1.1 - RCH Downstream Port RCRB
>
> Co-developed-by: Robert Richter <[email protected]>
> Signed-off-by: Terry Bowman <[email protected]>
> Signed-off-by: Robert Richter <[email protected]>
This doesn't look right. IIRC Co-dev tag should be just
before the SoB.
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Dave Jiang <[email protected]>
New day, fresh questions....
> ---
> drivers/cxl/core/core.h | 1 +
> drivers/cxl/core/pci.c | 6 ++++++
> drivers/cxl/core/regs.c | 35 +++++++++++++++++++++++++++++++++++
> 3 files changed, 42 insertions(+)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 45e7e044cf4a..f470ef5c0a6a 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -73,6 +73,7 @@ struct cxl_rcrb_info;
> resource_size_t __rcrb_to_component(struct device *dev,
> struct cxl_rcrb_info *ri,
> enum cxl_rcrb which);
> +u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
>
> extern struct rw_semaphore cxl_dpa_rwsem;
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 6ba3b7370816..4c6c5c7ba5a3 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -722,6 +722,12 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
>
> void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
> {
> + struct device *dport_dev = dport->dport_dev;
> + struct pci_host_bridge *host_bridge;
> +
> + host_bridge = to_pci_host_bridge(dport_dev);
> + if (host_bridge->native_cxl_error)
> + dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);
> }
> EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
>
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index e0fbe964f6f0..6e502f02899b 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -470,6 +470,41 @@ int cxl_setup_regs(struct cxl_register_map *map)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
>
> +u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb)
> +{
> + void __iomem *addr;
> + u16 offset = 0;
> + u32 cap_hdr;
> +
> + if (WARN_ON_ONCE(rcrb == CXL_RESOURCE_NONE))
> + return 0;
> +
> + if (!request_mem_region(rcrb, SZ_4K, dev_name(dev)))
> + return 0;
> +
> + addr = ioremap(rcrb, SZ_4K);
> + if (!addr) {
Given this handling exists, below, perhaps a goto?
Also, why isn't this an error? A comment would be good for that.
> + release_mem_region(rcrb, SZ_4K);
> + return 0;
> + }
> +
> + cap_hdr = readl(addr + offset);
> + while (PCI_EXT_CAP_ID(cap_hdr) != PCI_EXT_CAP_ID_ERR) {
> + offset = PCI_EXT_CAP_NEXT(cap_hdr);
> + if (!offset)
> + break;
> + cap_hdr = readl(addr + offset);
> + }
> +
> + if (offset)
Add a comment / specification reference for why an offset of 0 is not valid.
Of the top of my head I'm not sure though there may be a requirement for
something else coming first...
> + dev_dbg(dev, "found AER extended capability (0x%x)\n", offset);
> +
> + iounmap(addr);
> + release_mem_region(rcrb, SZ_4K);
> +
> + return offset;
> +}
> +
> resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri,
> enum cxl_rcrb which)
> {
On Wed, 27 Sep 2023 17:43:20 +0200
Robert Richter <[email protected]> wrote:
> Binding and unbindind RCD endpoints (e.g. mem0 device) caused the
> corresponding endpoint not being released. Reason for that is the
> wrong port discovered for RCD endpoints. See cxl_mem_probe() for
> proper endpoint parent detection. Fix delete_endpoint() respectively.
>
> Signed-off-by: Robert Richter <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
I wondered briefly if an access function of some type could be
used to hide this detail away. However it's messy enough that
that is a little tricky so I think we should just keep it
explicit in each location. So as you have it here.
> ---
> drivers/cxl/core/port.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 7ca01a834e18..d4572a02989a 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1222,12 +1222,17 @@ static void delete_endpoint(void *data)
> struct cxl_memdev *cxlmd = data;
> struct cxl_port *endpoint = cxlmd->endpoint;
> struct cxl_port *parent_port;
> + struct cxl_dport *dport;
> struct device *parent;
>
> - parent_port = cxl_mem_find_port(cxlmd, NULL);
> + parent_port = cxl_mem_find_port(cxlmd, &dport);
> if (!parent_port)
> goto out;
> - parent = &parent_port->dev;
> +
> + if (dport->rch)
> + parent = parent_port->uport_dev;
> + else
> + parent = &parent_port->dev;
>
> device_lock(parent);
> if (parent->driver && !endpoint->dead) {
On Wed, 27 Sep 2023 17:43:33 +0200
Robert Richter <[email protected]> wrote:
> From: Terry Bowman <[email protected]>
>
> The restricted CXL host (RCH) error handler will log protocol errors
> using AER and RAS status registers. The AER and RAS registers need to
> be virtually memory mapped before enabling interrupts. Create the
> initializer function devm_cxl_setup_parent_dport() for this when the
> endpoint is connected with the dport. The initialization sets up the
> RCH RAS and AER mappings.
>
> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
> the RCH downstream port's AER and RAS registers.
>
> Co-developed-by: Robert Richter <[email protected]>
> Signed-off-by: Terry Bowman <[email protected]>
As before. Co-dev just before SoB.
https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L521
This example looks like what you have here.
> Signed-off-by: Robert Richter <[email protected]>
Otherwise, LGTM
Reviewed-by: Jonathan Cameron <[email protected]>
> ---
> drivers/cxl/core/pci.c | 36 ++++++++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 10 ++++++++++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 2b8883288539..2af7ad77b273 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -5,6 +5,7 @@
> #include <linux/delay.h>
> #include <linux/pci.h>
> #include <linux/pci-doe.h>
> +#include <linux/aer.h>
> #include <cxlpci.h>
> #include <cxlmem.h>
> #include <cxl.h>
> @@ -730,6 +731,38 @@ static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
>
> #ifdef CONFIG_PCIEAER_CXL
>
> +static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
> +{
> + struct cxl_rcrb_info *ri = &dport->rcrb;
> + void __iomem *dport_aer = NULL;
> + resource_size_t aer_phys;
> + struct device *host;
> +
> + if (dport->rch && ri->aer_cap) {
> + host = dport->reg_map.host;
> + aer_phys = ri->aer_cap + ri->base;
> + dport_aer = devm_cxl_iomap_block(host, aer_phys,
> + sizeof(struct aer_capability_regs));
> + }
> +
> + dport->regs.dport_aer = dport_aer;
> +}
> +
> +static void cxl_dport_map_regs(struct cxl_dport *dport)
> +{
> + struct cxl_register_map *map = &dport->reg_map;
> + struct device *dev = dport->dport_dev;
> +
> + if (!map->component_map.ras.valid)
> + dev_dbg(dev, "RAS registers not found\n");
> + else if (cxl_map_component_regs(map, &dport->regs.component,
> + BIT(CXL_CM_CAP_CAP_ID_RAS)))
> + dev_dbg(dev, "Failed to map RAS capability.\n");
> +
> + if (dport->rch)
> + cxl_dport_map_rch_aer(dport);
> +}
> +
> void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
> {
> struct device *dport_dev = dport->dport_dev;
> @@ -738,6 +771,9 @@ void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
> host_bridge = to_pci_host_bridge(dport_dev);
> if (host_bridge->native_cxl_error)
> dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);
> +
> + dport->reg_map.host = host;
> + cxl_dport_map_regs(dport);
> }
> EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index cfa2f6bede41..7c2c195592d6 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -221,6 +221,14 @@ struct cxl_regs {
> struct_group_tagged(cxl_pmu_regs, pmu_regs,
> void __iomem *pmu;
> );
> +
> + /*
> + * RCH downstream port specific RAS register
> + * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
> + */
> + struct_group_tagged(cxl_rch_regs, rch_regs,
> + void __iomem *dport_aer;
> + );
> };
>
> struct cxl_reg_map {
> @@ -623,6 +631,7 @@ struct cxl_rcrb_info {
> * @rcrb: Data about the Root Complex Register Block layout
> * @rch: Indicate whether this dport was enumerated in RCH or VH mode
> * @port: reference to cxl_port that contains this downstream port
> + * @regs: Dport parsed register blocks
> */
> struct cxl_dport {
> struct device *dport_dev;
> @@ -631,6 +640,7 @@ struct cxl_dport {
> struct cxl_rcrb_info rcrb;
> bool rch;
> struct cxl_port *port;
> + struct cxl_regs regs;
> };
>
> /**
On Wed, 27 Sep 2023 17:43:23 +0200
Robert Richter <[email protected]> wrote:
> Name the field @reg_map, because @reg_map->host will be used for
> mapping operations beyond component registers (i.e. AER registers).
> This is valid for all occurrences of @comp_map. Change them all.
>
> Signed-off-by: Robert Richter <[email protected]>
Makes sense. Can we pull the one I moaned about in the previous
patch into this one?
That way the renames are all together.
If not, I'm fine with just moaning :) Whichever patch split
you go with across this and previous...
Reviewed-by: Jonathan Cameron <[email protected]>
> ---
> drivers/cxl/core/port.c | 2 +-
> drivers/cxl/cxl.h | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 99df86d72dbc..b993dea61436 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -712,7 +712,7 @@ static int cxl_port_setup_regs(struct cxl_port *port,
> {
> if (dev_is_platform(port->uport_dev))
> return 0;
> - return cxl_setup_comp_regs(&port->dev, &port->comp_map,
> + return cxl_setup_comp_regs(&port->dev, &port->reg_map,
> component_reg_phys);
> }
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 68abf9944383..3a51b58a66d0 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -572,7 +572,7 @@ struct cxl_dax_region {
> * @regions: cxl_region_ref instances, regions mapped by this port
> * @parent_dport: dport that points to this port in the parent
> * @decoder_ida: allocator for decoder ids
> - * @comp_map: component register capability mappings
> + * @reg_map: component and ras register mapping parameters
> * @nr_dports: number of entries in @dports
> * @hdm_end: track last allocated HDM decoder instance for allocation ordering
> * @commit_end: cursor to track highest committed decoder for commit ordering
> @@ -592,7 +592,7 @@ struct cxl_port {
> struct xarray regions;
> struct cxl_dport *parent_dport;
> struct ida decoder_ida;
> - struct cxl_register_map comp_map;
> + struct cxl_register_map reg_map;
> int nr_dports;
> int hdm_end;
> int commit_end;
On Wed, 27 Sep 2023 17:43:29 +0200
Robert Richter <[email protected]> wrote:
> CXL error handling depends on AER.
>
> Introduce config option PCIEAER_CXL in preparation of the AER dport
> error handling. Also, introduce the stub function
> devm_cxl_setup_parent_dport() to setup dports.
>
> This is in preparation of follow on patches.
>
> Note the Kconfg part of the option is added in a later patch to enable
> it once coding of the feature is complete.
>
> Signed-off-by: Robert Richter <[email protected]>
Feels like it should just be combined with a later patch that fills
some of this in as on it's own it's just a weird snippet of code :)
Still, one comment inline anyway.
> ---
> drivers/cxl/core/pci.c | 9 +++++++++
> drivers/cxl/cxl.h | 7 +++++++
> drivers/cxl/mem.c | 2 ++
> 3 files changed, 18 insertions(+)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index c7a7887ebdcf..6ba3b7370816 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -718,6 +718,15 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> return true;
> }
>
> +#ifdef CONFIG_PCIEAER_CXL
> +
> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
> +{
> +}
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
> +
> +#endif
> +
> pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
> pci_channel_state_t state)
> {
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index c07064e0c136..cfa2f6bede41 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -704,6 +704,13 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
> struct device *dport_dev, int port_id,
> resource_size_t rcrb);
>
> +#ifdef CONFIG_PCIEAER_CXL
> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
> +#else
> +static inline void devm_cxl_setup_parent_dport(struct device *host,
> + struct cxl_dport *dport) { }
> +#endif
> +
> struct cxl_decoder *to_cxl_decoder(struct device *dev);
> struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
> struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 04107058739b..61ca21c020fa 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -157,6 +157,8 @@ static int cxl_mem_probe(struct device *dev)
> else
> endpoint_parent = &parent_port->dev;
>
> + devm_cxl_setup_parent_dport(dev, dport);
devm calls can always fail (because if nothing else you have to register
some cleanup and that involves an allocation. If you want to ignore
that I'd expect a comment here.
> +
> device_lock(endpoint_parent);
> if (!endpoint_parent->driver) {
> dev_err(dev, "CXL port topology %s not enabled\n",
On Wed, 27 Sep 2023 17:43:39 +0200
Robert Richter <[email protected]> wrote:
> struct cxl_register_map carries a @dev parameter for devm operations.
> Simplify the function interface to use that instead of a separate @dev
> argument.
>
> Signed-off-by: Terry Bowman <[email protected]>
> Signed-off-by: Robert Richter <[email protected]>
Seems reasonable.
Reviewed-by: Jonathan Cameron <[email protected]>
> ---
> drivers/cxl/core/regs.c | 5 ++---
> drivers/cxl/cxl.h | 3 +--
> drivers/cxl/pci.c | 2 +-
> 3 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 7b56f6f28ab1..b668be617fd7 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -386,10 +386,9 @@ int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
>
> -int cxl_map_pmu_regs(struct pci_dev *pdev, struct cxl_pmu_regs *regs,
> - struct cxl_register_map *map)
> +int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs)
> {
> - struct device *dev = &pdev->dev;
> + struct device *dev = map->host;
> resource_size_t phys_addr;
>
> phys_addr = map->resource;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 7c2c195592d6..ed90ca8ed79e 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -286,8 +286,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
> unsigned long map_mask);
> int cxl_map_device_regs(const struct cxl_register_map *map,
> struct cxl_device_regs *regs);
> -int cxl_map_pmu_regs(struct pci_dev *pdev, struct cxl_pmu_regs *regs,
> - struct cxl_register_map *map);
> +int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs);
>
> enum cxl_regloc_type;
> int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 037792e941f2..fa94bc61af25 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -898,7 +898,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> break;
> }
>
> - rc = cxl_map_pmu_regs(pdev, &pmu_regs, &map);
> + rc = cxl_map_pmu_regs(&map, &pmu_regs);
> if (rc) {
> dev_dbg(&pdev->dev, "Could not map PMU regs\n");
> break;
On Wed, 27 Sep 2023 17:43:21 +0200
Robert Richter <[email protected]> wrote:
> The primary role of @dev is to host the mappings for devm operations.
> @dev is too ambiguous as a name. I.e. when does @dev refer to the
> 'struct device *' instance that the registers belong, and when does
> @dev refer to the 'struct device *' instance hosting the mapping for
> devm operations?
>
> Clarify the role of @dev in cxl_register_map by renaming it to @host.
> Also, rename local variables to 'host' where map->host is used.
>
> Add Fixes: tag as the fix in the next patch depends on this change.
>
> Fixes: 5d2ffbe4b81a ("cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport")
> Signed-off-by: Terry Bowman <[email protected]>
> Signed-off-by: Robert Richter <[email protected]>
Good cleanup.
Reviewed-by: Jonathan Cameron <[email protected]>
> ---
> drivers/cxl/core/hdm.c | 2 +-
> drivers/cxl/core/port.c | 4 ++--
> drivers/cxl/core/regs.c | 28 ++++++++++++++--------------
> drivers/cxl/cxl.h | 4 ++--
> drivers/cxl/pci.c | 2 +-
> 5 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 4449b34a80cc..11d9971f3e8c 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -85,7 +85,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> struct cxl_component_regs *regs)
> {
> struct cxl_register_map map = {
> - .dev = &port->dev,
> + .host = &port->dev,
> .resource = port->component_reg_phys,
> .base = crb,
> .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index d4572a02989a..033651a5da30 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -691,14 +691,14 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
> return ERR_PTR(rc);
> }
>
> -static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
> +static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,
> resource_size_t component_reg_phys)
> {
> if (component_reg_phys == CXL_RESOURCE_NONE)
> return 0;
>
> *map = (struct cxl_register_map) {
> - .dev = dev,
> + .host = host,
> .reg_type = CXL_REGLOC_RBI_COMPONENT,
> .resource = component_reg_phys,
> .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 6281127b3e9d..e0fbe964f6f0 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -204,7 +204,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
> struct cxl_component_regs *regs,
> unsigned long map_mask)
> {
> - struct device *dev = map->dev;
> + struct device *host = map->host;
> struct mapinfo {
> const struct cxl_reg_map *rmap;
> void __iomem **addr;
> @@ -225,7 +225,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
> continue;
> phys_addr = map->resource + mi->rmap->offset;
> length = mi->rmap->size;
> - *(mi->addr) = devm_cxl_iomap_block(dev, phys_addr, length);
> + *(mi->addr) = devm_cxl_iomap_block(host, phys_addr, length);
> if (!*(mi->addr))
> return -ENOMEM;
> }
> @@ -237,7 +237,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
> int cxl_map_device_regs(const struct cxl_register_map *map,
> struct cxl_device_regs *regs)
> {
> - struct device *dev = map->dev;
> + struct device *host = map->host;
> resource_size_t phys_addr = map->resource;
> struct mapinfo {
> const struct cxl_reg_map *rmap;
> @@ -259,7 +259,7 @@ int cxl_map_device_regs(const struct cxl_register_map *map,
>
> addr = phys_addr + mi->rmap->offset;
> length = mi->rmap->size;
> - *(mi->addr) = devm_cxl_iomap_block(dev, addr, length);
> + *(mi->addr) = devm_cxl_iomap_block(host, addr, length);
> if (!*(mi->addr))
> return -ENOMEM;
> }
> @@ -309,7 +309,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
> int regloc, i;
>
> *map = (struct cxl_register_map) {
> - .dev = &pdev->dev,
> + .host = &pdev->dev,
> .resource = CXL_RESOURCE_NONE,
> };
>
> @@ -403,15 +403,15 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_pmu_regs, CXL);
>
> static int cxl_map_regblock(struct cxl_register_map *map)
> {
> - struct device *dev = map->dev;
> + struct device *host = map->host;
>
> map->base = ioremap(map->resource, map->max_size);
> if (!map->base) {
> - dev_err(dev, "failed to map registers\n");
> + dev_err(host, "failed to map registers\n");
> return -ENOMEM;
> }
>
> - dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource);
> + dev_dbg(host, "Mapped CXL Memory Device resource %pa\n", &map->resource);
> return 0;
> }
>
> @@ -425,28 +425,28 @@ static int cxl_probe_regs(struct cxl_register_map *map)
> {
> struct cxl_component_reg_map *comp_map;
> struct cxl_device_reg_map *dev_map;
> - struct device *dev = map->dev;
> + struct device *host = map->host;
> void __iomem *base = map->base;
>
> switch (map->reg_type) {
> case CXL_REGLOC_RBI_COMPONENT:
> comp_map = &map->component_map;
> - cxl_probe_component_regs(dev, base, comp_map);
> - dev_dbg(dev, "Set up component registers\n");
> + cxl_probe_component_regs(host, base, comp_map);
> + dev_dbg(host, "Set up component registers\n");
> break;
> case CXL_REGLOC_RBI_MEMDEV:
> dev_map = &map->device_map;
> - cxl_probe_device_regs(dev, base, dev_map);
> + cxl_probe_device_regs(host, base, dev_map);
> if (!dev_map->status.valid || !dev_map->mbox.valid ||
> !dev_map->memdev.valid) {
> - dev_err(dev, "registers not found: %s%s%s\n",
> + dev_err(host, "registers not found: %s%s%s\n",
> !dev_map->status.valid ? "status " : "",
> !dev_map->mbox.valid ? "mbox " : "",
> !dev_map->memdev.valid ? "memdev " : "");
> return -ENXIO;
> }
>
> - dev_dbg(dev, "Probing device registers...\n");
> + dev_dbg(host, "Probing device registers...\n");
> break;
> default:
> break;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 76d92561af29..b5b015b661ea 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -247,7 +247,7 @@ struct cxl_pmu_reg_map {
>
> /**
> * struct cxl_register_map - DVSEC harvested register block mapping parameters
> - * @dev: device for devm operations and logging
> + * @host: device for devm operations and logging
> * @base: virtual base of the register-block-BAR + @block_offset
> * @resource: physical resource base of the register block
> * @max_size: maximum mapping size to perform register search
> @@ -257,7 +257,7 @@ struct cxl_pmu_reg_map {
> * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
> */
> struct cxl_register_map {
> - struct device *dev;
> + struct device *host;
> void __iomem *base;
> resource_size_t resource;
> resource_size_t max_size;
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 44a21ab7add5..f9d852957809 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -484,7 +484,7 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
> resource_size_t component_reg_phys;
>
> *map = (struct cxl_register_map) {
> - .dev = &pdev->dev,
> + .host = &pdev->dev,
> .resource = CXL_RESOURCE_NONE,
> };
>
Hi Johnathan,
Thanks for the review comments.
On 10/2/23 09:34, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:23 +0200
> Robert Richter <[email protected]> wrote:
>
>> Name the field @reg_map, because @reg_map->host will be used for
>> mapping operations beyond component registers (i.e. AER registers).
>> This is valid for all occurrences of @comp_map. Change them all.
>>
>> Signed-off-by: Robert Richter <[email protected]>
> Makes sense. Can we pull the one I moaned about in the previous
> patch into this one?
>
> That way the renames are all together.
>
Yes, we will move the previous patch's variable rename into this patch
Regards,
Terry
> If not, I'm fine with just moaning :) Whichever patch split
> you go with across this and previous...
>
> Reviewed-by: Jonathan Cameron <[email protected]>
>> ---
>> drivers/cxl/core/port.c | 2 +-
>> drivers/cxl/cxl.h | 4 ++--
>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
>> index 99df86d72dbc..b993dea61436 100644
>> --- a/drivers/cxl/core/port.c
>> +++ b/drivers/cxl/core/port.c
>> @@ -712,7 +712,7 @@ static int cxl_port_setup_regs(struct cxl_port *port,
>> {
>> if (dev_is_platform(port->uport_dev))
>> return 0;
>> - return cxl_setup_comp_regs(&port->dev, &port->comp_map,
>> + return cxl_setup_comp_regs(&port->dev, &port->reg_map,
>> component_reg_phys);
>> }
>>
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index 68abf9944383..3a51b58a66d0 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -572,7 +572,7 @@ struct cxl_dax_region {
>> * @regions: cxl_region_ref instances, regions mapped by this port
>> * @parent_dport: dport that points to this port in the parent
>> * @decoder_ida: allocator for decoder ids
>> - * @comp_map: component register capability mappings
>> + * @reg_map: component and ras register mapping parameters
>> * @nr_dports: number of entries in @dports
>> * @hdm_end: track last allocated HDM decoder instance for allocation ordering
>> * @commit_end: cursor to track highest committed decoder for commit ordering
>> @@ -592,7 +592,7 @@ struct cxl_port {
>> struct xarray regions;
>> struct cxl_dport *parent_dport;
>> struct ida decoder_ida;
>> - struct cxl_register_map comp_map;
>> + struct cxl_register_map reg_map;
>> int nr_dports;
>> int hdm_end;
>> int commit_end;
>
Hi Jonathan,
I added responses below.
On 10/2/23 09:43, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:26 +0200
> Robert Richter <[email protected]> wrote:
>
>> Now, that the Component Register mappings are stored, use them to
>> enable and map the HDM decoder capabilities. The Component Registers
>> do not need to be probed again for this, remove probing code.
>>
>> The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
>> Endpoint's component register mappings are located in the cxlds and
>> else in the port's structure. Duplicate the cxlds->reg_map in
>> port->reg_map for endpoint ports.
>>
>> Signed-off-by: Terry Bowman <[email protected]>
>> Signed-off-by: Robert Richter <[email protected]>
>> Reviewed-by: Dave Jiang <[email protected]>
>> [rework to drop cxl_port_get_comp_map()]
>> Signed-off-by: Dan Williams <[email protected]>
> A few comments inline.
>
> Also, Dan's SoB doesn't make sense if you are the Author and he's not
> the one sending the email. The fun of patches bounced back and forwards
> is sometimes you have to tweak this stuff on each posting... :(
>
>> ---
>> drivers/cxl/core/hdm.c | 48 ++++++++++++++++-------------------------
>> drivers/cxl/core/port.c | 29 +++++++++++++++++++------
>> drivers/cxl/mem.c | 5 ++---
>> 3 files changed, 43 insertions(+), 39 deletions(-)
>>
>> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
>> index 11d9971f3e8c..14a0d0017df3 100644
>> --- a/drivers/cxl/core/hdm.c
>> +++ b/drivers/cxl/core/hdm.c
>> @@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
>> cxlhdm->interleave_mask |= GENMASK(14, 12);
>> }
>>
>> -static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
>> - struct cxl_component_regs *regs)
>> -{
>> - struct cxl_register_map map = {
>> - .host = &port->dev,
>> - .resource = port->component_reg_phys,
>> - .base = crb,
>> - .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
>> - };
>> -
>> - cxl_probe_component_regs(&port->dev, crb, &map.component_map);
>> - if (!map.component_map.hdm_decoder.valid) {
>> - dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
>> - /* unique error code to indicate no HDM decoder capability */
>> - return -ENODEV;
>> - }
>> -
>> - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
>> -}
>> -
>> static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
>> {
>> struct cxl_hdm *cxlhdm;
>> @@ -155,7 +135,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
>> {
>> struct device *dev = &port->dev;
>> struct cxl_hdm *cxlhdm;
>> - void __iomem *crb;
>> + struct cxl_register_map *reg_map;
>> int rc;
>>
>> cxlhdm = devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL);
>> @@ -164,19 +144,29 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
>> cxlhdm->port = port;
>> dev_set_drvdata(dev, cxlhdm);
>>
>> - crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
>> - if (!crb && info && info->mem_enabled) {
>> - cxlhdm->decoder_count = info->ranges;
>> - return cxlhdm;
>> - } else if (!crb) {
>> + reg_map = &port->reg_map;
>
> Could you set this where it's defined above?
>
Yes.
>> + if (reg_map->resource == CXL_RESOURCE_NONE) {
>
> A reminder comment on why/when this happens might be a good addition.
>
Yes, we will add.
>> + if (info && info->mem_enabled) {
>> + cxlhdm->decoder_count = info->ranges;
>> + return cxlhdm;
>> + }
>
> Trivial (and true before this patch) but I'd rather see the error path out of line
>
Ok, we will change the conditional check to be for the error case and the default path
for success.
>
> if (!info || !info->mem_enabled) {
> WARN_ON(1);
> dev_err(dev, "No ...
> ...
> }
>
> cxlhdm->decoder_count = info->ranges;
> return cxlhdm;
> }
>
>
>> + WARN_ON(1);
>> dev_err(dev, "No component registers mapped\n");
>> return ERR_PTR(-ENXIO);
>> }
>>
>> - rc = map_hdm_decoder_regs(port, crb, &cxlhdm->regs);
>> - iounmap(crb);
>> - if (rc)
>> + if (!reg_map->component_map.hdm_decoder.valid) {
>> + dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
>> + /* unique error code to indicate no HDM decoder capability */
>> + return ERR_PTR(-ENODEV);
>> + }
>> +
>> + rc = cxl_map_component_regs(reg_map, &cxlhdm->regs,
>> + BIT(CXL_CM_CAP_CAP_ID_HDM));
>> + if (rc) {
>> + dev_dbg(dev, "Failed to map HDM capability.\n");
> dev_err() seems appropriate here.
>
Yes, we will change dev_dbg() here to use dev_err().
Regards,
Terry
>> return ERR_PTR(rc);
>> + }
>>
>> parse_hdm_decoder_caps(cxlhdm);
>> if (cxlhdm->decoder_count == 0) {
>
Hi Jonathan,
I added responses inline below.
On 10/2/23 09:46, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:29 +0200
> Robert Richter <[email protected]> wrote:
>
>> CXL error handling depends on AER.
>>
>> Introduce config option PCIEAER_CXL in preparation of the AER dport
>> error handling. Also, introduce the stub function
>> devm_cxl_setup_parent_dport() to setup dports.
>>
>> This is in preparation of follow on patches.
>>
>> Note the Kconfg part of the option is added in a later patch to enable
>> it once coding of the feature is complete.
>>
>> Signed-off-by: Robert Richter <[email protected]>
>
> Feels like it should just be combined with a later patch that fills
> some of this in as on it's own it's just a weird snippet of code :)
>
We will look to merge with the following patch.
> Still, one comment inline anyway.
>
>
>> ---
>> drivers/cxl/core/pci.c | 9 +++++++++
>> drivers/cxl/cxl.h | 7 +++++++
>> drivers/cxl/mem.c | 2 ++
>> 3 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index c7a7887ebdcf..6ba3b7370816 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -718,6 +718,15 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
>> return true;
>> }
>>
>> +#ifdef CONFIG_PCIEAER_CXL
>> +
>> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
>> +{
>> +}
>> +EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
>> +
>> +#endif
>> +
>> pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
>> pci_channel_state_t state)
>> {
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index c07064e0c136..cfa2f6bede41 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -704,6 +704,13 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
>> struct device *dport_dev, int port_id,
>> resource_size_t rcrb);
>>
>> +#ifdef CONFIG_PCIEAER_CXL
>> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
>> +#else
>> +static inline void devm_cxl_setup_parent_dport(struct device *host,
>> + struct cxl_dport *dport) { }
>> +#endif
>> +
>> struct cxl_decoder *to_cxl_decoder(struct device *dev);
>> struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
>> struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
>> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
>> index 04107058739b..61ca21c020fa 100644
>> --- a/drivers/cxl/mem.c
>> +++ b/drivers/cxl/mem.c
>> @@ -157,6 +157,8 @@ static int cxl_mem_probe(struct device *dev)
>> else
>> endpoint_parent = &parent_port->dev;
>>
>> + devm_cxl_setup_parent_dport(dev, dport);
>
> devm calls can always fail (because if nothing else you have to register
> some cleanup and that involves an allocation. If you want to ignore
> that I'd expect a comment here.
>
We will add error handling here.
Regards,
Terry
>> +
>> device_lock(endpoint_parent);
>> if (!endpoint_parent->driver) {
>> dev_err(dev, "CXL port topology %s not enabled\n",
>
Hi Jonathan,
I added responses inline below.
On 10/2/23 09:53, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:30 +0200
> Robert Richter <[email protected]> wrote:
>
>> From: Terry Bowman <[email protected]>
>>
>> Restricted CXL host (RCH) downstream port AER information is not currently
>> logged while in the error state. One problem preventing the error logging
>> is the AER and RAS registers are not accessible. The CXL driver requires
>> changes to find RCH downstream port AER and RAS registers for purpose of
>> error logging.
>>
>> RCH downstream ports are not enumerated during a PCI bus scan and are
>> instead discovered using system firmware, ACPI in this case.[1] The
>> downstream port is implemented as a Root Complex Register Block (RCRB).
>> The RCRB is a 4k memory block containing PCIe registers based on the PCIe
>> root port.[2] The RCRB includes AER extended capability registers used for
>> reporting errors. Note, the RCH's AER Capability is located in the RCRB
>> memory space instead of PCI configuration space, thus its register access
>> is different. Existing kernel PCIe AER functions can not be used to manage
>> the downstream port AER capabilities and RAS registers because the port was
>> not enumerated during PCI scan and the registers are not PCI config
>> accessible.
>>
>> Discover RCH downstream port AER extended capability registers. Use MMIO
>> accesses to search for extended AER capability in RCRB register space.
>>
>> [1] CXL 3.0 Spec, 9.11.2 - System Firmware View of CXL 1.1 Hierarchy
>> [2] CXL 3.0 Spec, 8.2.1.1 - RCH Downstream Port RCRB
>>
>> Co-developed-by: Robert Richter <[email protected]>
>> Signed-off-by: Terry Bowman <[email protected]>
>> Signed-off-by: Robert Richter <[email protected]>
>
> This doesn't look right. IIRC Co-dev tag should be just
> before the SoB.
>
Yes, that needs to be swapped.
>> Reviewed-by: Jonathan Cameron <[email protected]>
>> Reviewed-by: Dave Jiang <[email protected]>
>
> New day, fresh questions....
>
>
>> ---
>> drivers/cxl/core/core.h | 1 +
>> drivers/cxl/core/pci.c | 6 ++++++
>> drivers/cxl/core/regs.c | 35 +++++++++++++++++++++++++++++++++++
>> 3 files changed, 42 insertions(+)
>>
>> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
>> index 45e7e044cf4a..f470ef5c0a6a 100644
>> --- a/drivers/cxl/core/core.h
>> +++ b/drivers/cxl/core/core.h
>> @@ -73,6 +73,7 @@ struct cxl_rcrb_info;
>> resource_size_t __rcrb_to_component(struct device *dev,
>> struct cxl_rcrb_info *ri,
>> enum cxl_rcrb which);
>> +u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
>>
>> extern struct rw_semaphore cxl_dpa_rwsem;
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 6ba3b7370816..4c6c5c7ba5a3 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -722,6 +722,12 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
>>
>> void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
>> {
>> + struct device *dport_dev = dport->dport_dev;
>> + struct pci_host_bridge *host_bridge;
>> +
>> + host_bridge = to_pci_host_bridge(dport_dev);
>> + if (host_bridge->native_cxl_error)
>> + dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);
>> }
>> EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
>>
>> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
>> index e0fbe964f6f0..6e502f02899b 100644
>> --- a/drivers/cxl/core/regs.c
>> +++ b/drivers/cxl/core/regs.c
>> @@ -470,6 +470,41 @@ int cxl_setup_regs(struct cxl_register_map *map)
>> }
>> EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
>>
>> +u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb)
>> +{
>> + void __iomem *addr;
>> + u16 offset = 0;
>> + u32 cap_hdr;
>> +
>> + if (WARN_ON_ONCE(rcrb == CXL_RESOURCE_NONE))
>> + return 0;
>> +
>> + if (!request_mem_region(rcrb, SZ_4K, dev_name(dev)))
>> + return 0;
>> +
>> + addr = ioremap(rcrb, SZ_4K);
>> + if (!addr) {
>
> Given this handling exists, below, perhaps a goto?
Yes, will make that change.
> Also, why isn't this an error? A comment would be good for that.
>
The intent is to avoid failing the driver probe in the case of missing RCH
error handling.
>> + release_mem_region(rcrb, SZ_4K);
>> + return 0;
>> + }
>> +
>> + cap_hdr = readl(addr + offset);
>> + while (PCI_EXT_CAP_ID(cap_hdr) != PCI_EXT_CAP_ID_ERR) {
>> + offset = PCI_EXT_CAP_NEXT(cap_hdr);
>> + if (!offset)
>> + break;
>> + cap_hdr = readl(addr + offset);
>> + }
>> +
>> + if (offset)
>
> Add a comment / specification reference for why an offset of 0 is not valid.
> Of the top of my head I'm not sure though there may be a requirement for
> something else coming first...
>
I can add spec documentation:
'For Extended Capabilities implemented in Configuration Space, this offset is
relative to the beginning of PCI-compatible Configuration Space and thus must
always be either 000h (for terminating list of Capabilities) or greater than 0FFh.' [1]
[1] - PCI 6.0 - 7.9.7.1 RCRB Header Extended Capability Header (Offset 00h)
Regards,
Terry
>> + dev_dbg(dev, "found AER extended capability (0x%x)\n", offset);
>> +
>> + iounmap(addr);
>> + release_mem_region(rcrb, SZ_4K);
>> +
>> + return offset;
>> +}
>> +
>> resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri,
>> enum cxl_rcrb which)
>> {
>
On 10/2/23 09:56, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:33 +0200
> Robert Richter <[email protected]> wrote:
>
>> From: Terry Bowman <[email protected]>
>>
>> The restricted CXL host (RCH) error handler will log protocol errors
>> using AER and RAS status registers. The AER and RAS registers need to
>> be virtually memory mapped before enabling interrupts. Create the
>> initializer function devm_cxl_setup_parent_dport() for this when the
>> endpoint is connected with the dport. The initialization sets up the
>> RCH RAS and AER mappings.
>>
>> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
>> the RCH downstream port's AER and RAS registers.
>>
>> Co-developed-by: Robert Richter <[email protected]>
>> Signed-off-by: Terry Bowman <[email protected]>
> As before. Co-dev just before SoB.
>
> https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L521
> This example looks like what you have here.
>
>> Signed-off-by: Robert Richter <[email protected]>
> Otherwise, LGTM
>
> Reviewed-by: Jonathan Cameron <[email protected]>
Yes, we will fix.
Regards,
Terry
Hi Jonathan,
I added a response below.
On 10/9/23 09:44, Terry Bowman wrote:
> Hi Jonathan,
>
> I added responses inline below.
>
> On 10/2/23 09:46, Jonathan Cameron wrote:
>> On Wed, 27 Sep 2023 17:43:29 +0200
>> Robert Richter <[email protected]> wrote:
>>
>>> CXL error handling depends on AER.
>>>
>>> Introduce config option PCIEAER_CXL in preparation of the AER dport
>>> error handling. Also, introduce the stub function
>>> devm_cxl_setup_parent_dport() to setup dports.
>>>
>>> This is in preparation of follow on patches.
>>>
>>> Note the Kconfg part of the option is added in a later patch to enable
>>> it once coding of the feature is complete.
>>>
>>> Signed-off-by: Robert Richter <[email protected]>
>>
>> Feels like it should just be combined with a later patch that fills
>> some of this in as on it's own it's just a weird snippet of code :)
>>
>
> We will look to merge with the following patch.
>
>> Still, one comment inline anyway.
>>
>>
>>> ---
>>> drivers/cxl/core/pci.c | 9 +++++++++
>>> drivers/cxl/cxl.h | 7 +++++++
>>> drivers/cxl/mem.c | 2 ++
>>> 3 files changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>>> index c7a7887ebdcf..6ba3b7370816 100644
>>> --- a/drivers/cxl/core/pci.c
>>> +++ b/drivers/cxl/core/pci.c
>>> @@ -718,6 +718,15 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
>>> return true;
>>> }
>>>
>>> +#ifdef CONFIG_PCIEAER_CXL
>>> +
>>> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
>>> +{
>>> +}
>>> +EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
>>> +
>>> +#endif
>>> +
>>> pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
>>> pci_channel_state_t state)
>>> {
>>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>>> index c07064e0c136..cfa2f6bede41 100644
>>> --- a/drivers/cxl/cxl.h
>>> +++ b/drivers/cxl/cxl.h
>>> @@ -704,6 +704,13 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
>>> struct device *dport_dev, int port_id,
>>> resource_size_t rcrb);
>>>
>>> +#ifdef CONFIG_PCIEAER_CXL
>>> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
>>> +#else
>>> +static inline void devm_cxl_setup_parent_dport(struct device *host,
>>> + struct cxl_dport *dport) { }
>>> +#endif
>>> +
>>> struct cxl_decoder *to_cxl_decoder(struct device *dev);
>>> struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
>>> struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
>>> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
>>> index 04107058739b..61ca21c020fa 100644
>>> --- a/drivers/cxl/mem.c
>>> +++ b/drivers/cxl/mem.c
>>> @@ -157,6 +157,8 @@ static int cxl_mem_probe(struct device *dev)
>>> else
>>> endpoint_parent = &parent_port->dev;
>>>
>>> + devm_cxl_setup_parent_dport(dev, dport);
>>
>> devm calls can always fail (because if nothing else you have to register
>> some cleanup and that involves an allocation. If you want to ignore
>> that I'd expect a comment here.
>>
>
> We will add error handling here.
>
> Regards,
> Terry
>
Found devm_cxl_setup_parent_dport() is a NULL function without return value.
Regards,
Terry
> >>> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> >>> index 04107058739b..61ca21c020fa 100644
> >>> --- a/drivers/cxl/mem.c
> >>> +++ b/drivers/cxl/mem.c
> >>> @@ -157,6 +157,8 @@ static int cxl_mem_probe(struct device *dev)
> >>> else
> >>> endpoint_parent = &parent_port->dev;
> >>>
> >>> + devm_cxl_setup_parent_dport(dev, dport);
> >>
> >> devm calls can always fail (because if nothing else you have to register
> >> some cleanup and that involves an allocation. If you want to ignore
> >> that I'd expect a comment here.
> >>
> >
> > We will add error handling here.
> >
> > Regards,
> > Terry
> >
>
> Found devm_cxl_setup_parent_dport() is a NULL function without return value.
Hmm. Then it's not a devm function.
I went looking and can't find it registering any cleanup so
just rename it to cxl_setup_parent_dport()
>
> Regards,
> Terry
On 02.10.23 15:43:51, Jonathan Cameron wrote:
> On Wed, 27 Sep 2023 17:43:26 +0200
> Robert Richter <[email protected]> wrote:
>
> > Now, that the Component Register mappings are stored, use them to
> > enable and map the HDM decoder capabilities. The Component Registers
> > do not need to be probed again for this, remove probing code.
> >
> > The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
> > Endpoint's component register mappings are located in the cxlds and
> > else in the port's structure. Duplicate the cxlds->reg_map in
> > port->reg_map for endpoint ports.
> >
> > Signed-off-by: Terry Bowman <[email protected]>
> > Signed-off-by: Robert Richter <[email protected]>
> > Reviewed-by: Dave Jiang <[email protected]>
> > [rework to drop cxl_port_get_comp_map()]
> > Signed-off-by: Dan Williams <[email protected]>
> A few comments inline.
>
> Also, Dan's SoB doesn't make sense if you are the Author and he's not
> the one sending the email. The fun of patches bounced back and forwards
> is sometimes you have to tweak this stuff on each posting... :(
Yeah, there was some back and forth with the code going on: Terry
changed a little, Dan was taking it and reposting, Terry was also
submitting the previous series, Dave reviewed it. So I decided here to
just swap Terry and my SOBs as I was posting the series now and left
the remaining to Dan the way as it will look like when he will apply
the patch, which means updating the SOB chain again. This keeps the
comment for the change he made to the patch.
-Robert
>
> > ---
> > drivers/cxl/core/hdm.c | 48 ++++++++++++++++-------------------------
> > drivers/cxl/core/port.c | 29 +++++++++++++++++++------
> > drivers/cxl/mem.c | 5 ++---
> > 3 files changed, 43 insertions(+), 39 deletions(-)