Hi,
This series adds SATA controller support for the Texas Instruments
OMAP5 and DRA7 platforms.
As the SATA controller is compatible with AHCI, we use the ahci_platform
driver and just provide the glue logic.
The AHCI controller is enclosed within a TI specific Wrapper that controls
the controller power mode. Patch 9 adds a driver for this wrapper.
The controller is linked to a SATA (PIPE3) PHY, which needs to be clocked
and powered up before it can be used. We do that with the help of the
generic PHY framework [2] in Patch 8.
Patches 1 to 7 adapt the the PHY driver to the Generic PHY framework.
Patches 9 to 15 provide platform adaptation code for OMAP5 and DRA7.
Patches are based on v3.12-rc1 with the following patches on top
[1] - omap control usb multiple instance support
http://article.gmane.org/gmane.linux.ports.arm.kernel/267587
git://github.com/rogerq/linux.git usb-control-module
[2] - Generic PHY framework
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git testing
[3] - Clock DT support
git://gitorious.org/~kristo/omap-pm/omap-pm-work.git mainline-3.11-rc3-omap-dt-clks-v5
[4] - PHY framework mis cleanup
https://lkml.org/lkml/2013/9/2/313
NOTE: [2], [3] and [4] will cause merge conflicts and need to be resolved manually.
A merged tree is available for reference/testing at
git://github.com/rogerq/linux.git ti-3.12-sata
Tested on omap5-uevm and dra7-evm with Gen2 SATA hard drive.
Known issues:
- Gen3 SATA SSD does not work due to some issue with PHY speed negotiation.
cheers,
-roger
---
Balaji T K (3):
ata: ahci_platform: Manage SATA PHY
arm: dts: omap5: add sata node
arm: dts: dra7: add sata node
Benoit Cousson (1):
arm: omap5: hwmod: add missing ocp2scp hwmod data
Keshava Munegowda (1):
ARM: omap5: hwmod: Add ocp2scp3 and sata hwmods
Kishon Vijay Abraham I (2):
phy: rename struct omap_control_usb to struct omap_control_phy
phy: omap-pipe3: use generic clock names
Nikhil Devshatwar (1):
ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods
Roger Quadros (7):
phy: omap-control: Update DT binding information
ARM: dts: omap5: Add clocks to usb3_phy node
phy: omap-pipe3: Add SATA DPLL support
phy: omap-pipe3: update compatibility string and DT binding
ARM: dts: omap5: Update usb3phy node
ata: ti_sata: Add Texas Instruments SATA Wrapper driver
ARM: dts: omap5: add ocp2scp1 address resource
.../devicetree/bindings/ata/ahci-platform.txt | 2 +-
Documentation/devicetree/bindings/ata/ti-sata.txt | 31 ++
Documentation/devicetree/bindings/phy/omap-phy.txt | 26 ++-
Documentation/devicetree/bindings/usb/omap-usb.txt | 23 --
arch/arm/boot/dts/dra7.dtsi | 49 ++++
arch/arm/boot/dts/omap5.dtsi | 56 ++++-
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 117 ++++++++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 40 +++-
drivers/ata/Kconfig | 8 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci.h | 2 +
drivers/ata/ahci_platform.c | 31 ++-
drivers/ata/sata_ti.c | 160 +++++++++++
drivers/phy/Kconfig | 14 +-
drivers/phy/Makefile | 1 +
drivers/phy/phy-omap-control.c | 300 ++++++++++++++++++++
drivers/phy/phy-omap-pipe3.c | 157 ++++++-----
drivers/phy/phy-omap-usb2.c | 9 +-
drivers/usb/musb/omap2430.c | 2 +-
drivers/usb/phy/Kconfig | 10 -
drivers/usb/phy/Makefile | 1 -
drivers/usb/phy/phy-omap-control.c | 300 --------------------
include/linux/phy/omap_control_phy.h | 83 ++++++
include/linux/phy/omap_pipe3.h | 6 +
include/linux/usb/omap_control_usb.h | 83 ------
25 files changed, 1013 insertions(+), 499 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/ti-sata.txt
create mode 100644 drivers/ata/sata_ti.c
create mode 100644 drivers/phy/phy-omap-control.c
delete mode 100644 drivers/usb/phy/phy-omap-control.c
create mode 100644 include/linux/phy/omap_control_phy.h
delete mode 100644 include/linux/usb/omap_control_usb.h
--
1.7.4.1
Update compatibility string and DT binding document.
Signed-off-by: Roger Quadros <[email protected]>
---
Documentation/devicetree/bindings/phy/omap-phy.txt | 23 ++++++++++++++++++++
Documentation/devicetree/bindings/usb/omap-usb.txt | 23 --------------------
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/omap-phy.txt b/Documentation/devicetree/bindings/phy/omap-phy.txt
index 2c485ee..cf45b01 100644
--- a/Documentation/devicetree/bindings/phy/omap-phy.txt
+++ b/Documentation/devicetree/bindings/phy/omap-phy.txt
@@ -1,5 +1,28 @@
OMAP PHY: DT DOCUMENTATION FOR PHYs in OMAP PLATFORM
+OMAP CONTROL PHY
+
+Required properties:
+ - compatible: Should be one of
+ "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
+ "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
+ e.g. USB2_PHY on OMAP5.
+ "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
+ e.g. USB3 PHY and SATA PHY on OMAP5.
+ "ti,control-phy-dra7usb2" - if it has power down register like USB2 PHY on
+ DRA7 platform.
+ - reg : Address and length of the register set for the device. It contains
+ the address of "otghs_control" for control-phy-otghs or "power" register
+ for other types.
+ - reg-names: should be "otghs_control" control-phy-otghs and "power" for
+ other types.
+
+omap_control_otghs: omap-control-phy@4a002300 {
+ compatible = "ti,control-phy-otghs";
+ reg = <0x4a00233c 0x4>;
+ reg-names = "otghs_control";
+};
+
OMAP USB2 PHY
Required properties:
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
index b2bf7b3..4aa8eab 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -79,26 +79,3 @@ omap_dwc3 {
clock-names = "usb_otg_ss_refclk960m";
ranges;
};
-
-OMAP CONTROL USB
-
-Required properties:
- - compatible: Should be one of
- "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
- "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
- e.g. USB2_PHY on OMAP5.
- "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
- e.g. USB3 PHY and SATA PHY on OMAP5.
- "ti,control-phy-dra7usb2" - if it has power down register like USB2 PHY on
- DRA7 platform.
- - reg : Address and length of the register set for the device. It contains
- the address of "otghs_control" for control-phy-otghs or "power" register
- for other types.
- - reg-names: should be "otghs_control" control-phy-otghs and "power" for
- other types.
-
-omap_control_usb: omap-control-usb@4a002300 {
- compatible = "ti,control-phy-otghs";
- reg = <0x4a00233c 0x4>;
- reg-names = "otghs_control";
-};
--
1.7.4.1
The pipe3-phy driver expects certain named clocks.
Provide the necessary clocks.
CC: Benoit Cousson <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/boot/dts/omap5.dtsi | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 576b06a..97f361a 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -677,6 +677,8 @@
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_usb3phy>;
+ clocks = <&usb_phy_cm_clk32k>, <&sys_clkin>;
+ clock-names = "wkupclk", "sysclk";
#phy-cells = <0>;
};
};
--
1.7.4.1
From: Kishon Vijay Abraham I <[email protected]>
As this driver is no longer USB specific use generic clock names.
[Roger Q]
- Fix PLL_SD_SHIFT from 9 to 10
- As optclk and wkupclk may not be always required, don't bail out
if they aren't available.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
drivers/phy/phy-omap-pipe3.c | 71 +++++++++++++++++++++++-------------------
1 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/drivers/phy/phy-omap-pipe3.c b/drivers/phy/phy-omap-pipe3.c
index 63de0f8..807ab8a 100644
--- a/drivers/phy/phy-omap-pipe3.c
+++ b/drivers/phy/phy-omap-pipe3.c
@@ -37,15 +37,15 @@
#define PLL_CONFIGURATION4 0x00000020
#define PLL_REGM_MASK 0x001FFE00
-#define PLL_REGM_SHIFT 0x9
+#define PLL_REGM_SHIFT 9
#define PLL_REGM_F_MASK 0x0003FFFF
-#define PLL_REGM_F_SHIFT 0x0
+#define PLL_REGM_F_SHIFT 0
#define PLL_REGN_MASK 0x000001FE
-#define PLL_REGN_SHIFT 0x1
+#define PLL_REGN_SHIFT 1
#define PLL_SELFREQDCO_MASK 0x0000000E
-#define PLL_SELFREQDCO_SHIFT 0x1
+#define PLL_SELFREQDCO_SHIFT 1
#define PLL_SD_MASK 0x0003FC00
-#define PLL_SD_SHIFT 0x9
+#define PLL_SD_SHIFT 10
#define SET_PLL_GO 0x1
#define PLL_TICOPWDN 0x10000
#define PLL_LOCK 0x2
@@ -232,23 +232,21 @@ static int omap_pipe3_probe(struct platform_device *pdev)
phy->dev = &pdev->dev;
- phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
- if (IS_ERR(phy->wkupclk)) {
- dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
- return PTR_ERR(phy->wkupclk);
- }
- clk_prepare(phy->wkupclk);
+ phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
+ if (IS_ERR(phy->wkupclk))
+ dev_dbg(&pdev->dev, "unable to get wkupclk\n");
+ else
+ clk_prepare(phy->wkupclk);
- phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
- if (IS_ERR(phy->optclk)) {
- dev_err(&pdev->dev, "unable to get usb_otg_ss_refclk960m\n");
- return PTR_ERR(phy->optclk);
- }
- clk_prepare(phy->optclk);
+ phy->optclk = devm_clk_get(phy->dev, "optclk");
+ if (IS_ERR(phy->optclk))
+ dev_dbg(&pdev->dev, "unable to get optclk\n");
+ else
+ clk_prepare(phy->optclk);
- phy->sys_clk = devm_clk_get(phy->dev, "sys_clkin");
+ phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
if (IS_ERR(phy->sys_clk)) {
- pr_err("%s: unable to get sys_clkin\n", __func__);
+ dev_err(&pdev->dev, "unable to get sysclk\n");
return -EINVAL;
}
@@ -290,8 +288,10 @@ static int omap_pipe3_remove(struct platform_device *pdev)
{
struct omap_pipe3 *phy = platform_get_drvdata(pdev);
- clk_unprepare(phy->wkupclk);
- clk_unprepare(phy->optclk);
+ if (!IS_ERR(phy->wkupclk))
+ clk_unprepare(phy->wkupclk);
+ if (!IS_ERR(phy->optclk))
+ clk_unprepare(phy->optclk);
if (!pm_runtime_suspended(&pdev->dev))
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
@@ -305,8 +305,10 @@ static int omap_pipe3_runtime_suspend(struct device *dev)
{
struct omap_pipe3 *phy = dev_get_drvdata(dev);
- clk_disable(phy->wkupclk);
- clk_disable(phy->optclk);
+ if (!IS_ERR(phy->wkupclk))
+ clk_disable(phy->wkupclk);
+ if (!IS_ERR(phy->optclk))
+ clk_disable(phy->optclk);
return 0;
}
@@ -316,22 +318,27 @@ static int omap_pipe3_runtime_resume(struct device *dev)
u32 ret = 0;
struct omap_pipe3 *phy = dev_get_drvdata(dev);
- ret = clk_enable(phy->optclk);
- if (ret) {
- dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
- goto err1;
+ if (!IS_ERR(phy->optclk)) {
+ ret = clk_enable(phy->optclk);
+ if (ret) {
+ dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
+ goto err1;
+ }
}
- ret = clk_enable(phy->wkupclk);
- if (ret) {
- dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
- goto err2;
+ if (!IS_ERR(phy->wkupclk)) {
+ ret = clk_enable(phy->wkupclk);
+ if (ret) {
+ dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
+ goto err2;
+ }
}
return 0;
err2:
- clk_disable(phy->optclk);
+ if (!IS_ERR(phy->optclk))
+ clk_disable(phy->optclk);
err1:
return ret;
--
1.7.4.1
From: Balaji T K <[email protected]>
Some platforms have a PHY hooked up to the
SATA controller. The PHY needs to be initialized
and powered up for SATA to work. We do that
using the PHY framework.
[Roger Q] Cleaned up.
CC: Tejun Heo <[email protected]>
Signed-off-by: Balaji T K <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
.../devicetree/bindings/ata/ahci-platform.txt | 2 +-
drivers/ata/Kconfig | 1 +
drivers/ata/ahci.h | 2 +
drivers/ata/ahci_platform.c | 31 +++++++++++++++++++-
4 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 89de156..c6c549a 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -4,7 +4,7 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
-- compatible : compatible list, contains "snps,spear-ahci"
+- compatible : compatible list, contains "snps,spear-ahci" or "snps,dwc-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 4e73772..a53ef27 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -91,6 +91,7 @@ config SATA_AHCI
config SATA_AHCI_PLATFORM
tristate "Platform AHCI SATA support"
+ select GENERIC_PHY
help
This option enables support for Platform AHCI Serial ATA
controllers.
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 1145637..94484cb 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -37,6 +37,7 @@
#include <linux/clk.h>
#include <linux/libata.h>
+#include <linux/phy/phy.h>
/* Enclosure Management Control */
#define EM_CTRL_MSG_TYPE 0x000f0000
@@ -322,6 +323,7 @@ struct ahci_host_priv {
u32 em_buf_sz; /* EM buffer size in byte */
u32 em_msg_type; /* EM message type */
struct clk *clk; /* Only for platforms supporting clk */
+ struct phy *phy; /* If platforms use phy */
void *plat_data; /* Other platform data */
};
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 2daaee0..f812ffa 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -23,6 +23,7 @@
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/ahci_platform.h>
+#include <linux/phy/phy.h>
#include "ahci.h"
static void ahci_host_stop(struct ata_host *host);
@@ -141,16 +142,32 @@ static int ahci_probe(struct platform_device *pdev)
}
}
+ hpriv->phy = devm_phy_get(dev, "sata-phy");
+ if (IS_ERR(hpriv->phy)) {
+ dev_err(dev, "can't get phy\n");
+ /* return only if -EPROBE_DEFER */
+ if (PTR_ERR(hpriv->phy) == -EPROBE_DEFER) {
+ rc = -EPROBE_DEFER;
+ goto disable_unprepare_clk;
+ }
+ }
+
/*
* Some platforms might need to prepare for mmio region access,
* which could be done in the following init call. So, the mmio
* region shouldn't be accessed before init (if provided) has
* returned successfully.
*/
+
+ if (!(IS_ERR(hpriv->phy))) {
+ phy_init(hpriv->phy);
+ phy_power_on(hpriv->phy);
+ }
+
if (pdata && pdata->init) {
rc = pdata->init(dev, hpriv->mmio);
if (rc)
- goto disable_unprepare_clk;
+ goto disable_phy;
}
ahci_save_initial_config(dev, hpriv,
@@ -220,6 +237,12 @@ static int ahci_probe(struct platform_device *pdev)
pdata_exit:
if (pdata && pdata->exit)
pdata->exit(dev);
+disable_phy:
+ if (!IS_ERR(hpriv->phy)) {
+ phy_power_off(hpriv->phy);
+ phy_exit(hpriv->phy);
+ }
+
disable_unprepare_clk:
if (!IS_ERR(hpriv->clk))
clk_disable_unprepare(hpriv->clk);
@@ -238,6 +261,11 @@ static void ahci_host_stop(struct ata_host *host)
if (pdata && pdata->exit)
pdata->exit(dev);
+ if (!IS_ERR(hpriv->phy)) {
+ phy_power_off(hpriv->phy);
+ phy_exit(hpriv->phy);
+ }
+
if (!IS_ERR(hpriv->clk)) {
clk_disable_unprepare(hpriv->clk);
clk_put(hpriv->clk);
@@ -328,6 +356,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
static const struct of_device_id ahci_of_match[] = {
{ .compatible = "snps,spear-ahci", },
{ .compatible = "snps,exynos5440-ahci", },
+ { .compatible = "snps,dwc-ahci", },
{},
};
MODULE_DEVICE_TABLE(of, ahci_of_match);
--
1.7.4.1
Improve compatibility string format to "ti,phy-pipe3-<type>"
where <type> can be "usb3" or "sata". Remove "pcie" type
as it is not yet supported due to missing DPLL data.
Signed-off-by: Roger Quadros <[email protected]>
---
Documentation/devicetree/bindings/phy/omap-phy.txt | 3 +--
drivers/phy/phy-omap-pipe3.c | 8 ++------
2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/omap-phy.txt b/Documentation/devicetree/bindings/phy/omap-phy.txt
index cf45b01..8e09ad3 100644
--- a/Documentation/devicetree/bindings/phy/omap-phy.txt
+++ b/Documentation/devicetree/bindings/phy/omap-phy.txt
@@ -47,8 +47,7 @@ usb2phy@4a0ad080 {
OMAP PIPE3 PHY
Required properties:
- - compatible: Should be "ti,omap-usb3", "ti,omap-pipe3", "ti,omap-sata"
- or "ti,omap-pcie"
+ - compatible: Should be "ti,phy-pipe3-usb3" or "ti,phy-pipe3-sata"
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the registers
filled in "reg".
diff --git a/drivers/phy/phy-omap-pipe3.c b/drivers/phy/phy-omap-pipe3.c
index 19d1664..67eeaeb 100644
--- a/drivers/phy/phy-omap-pipe3.c
+++ b/drivers/phy/phy-omap-pipe3.c
@@ -219,17 +219,13 @@ static struct phy_ops ops = {
#ifdef CONFIG_OF
static const struct of_device_id omap_pipe3_id_table[] = {
{
- .compatible = "ti,omap-pipe3",
+ .compatible = "ti,phy-pipe3-usb3",
.data = dpll_map_usb,
},
{
- .compatible = "ti,omap-sata",
+ .compatible = "ti,phy-pipe3-sata",
.data = dpll_map_sata,
},
- {
- .compatible = "ti,omap-usb3",
- .data = dpll_map_usb,
- },
{},
};
MODULE_DEVICE_TABLE(of, omap_pipe3_id_table);
--
1.7.4.1
Texas Instruments SoCs like OMAP5 and DRA7 contain a SATA wrapper
around the AHCI SATA core. This driver will manage that.
CC: Tejun Heo <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
Documentation/devicetree/bindings/ata/ti-sata.txt | 31 ++++
drivers/ata/Kconfig | 7 +
drivers/ata/Makefile | 1 +
drivers/ata/sata_ti.c | 160 +++++++++++++++++++++
4 files changed, 199 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/ti-sata.txt
create mode 100644 drivers/ata/sata_ti.c
diff --git a/Documentation/devicetree/bindings/ata/ti-sata.txt b/Documentation/devicetree/bindings/ata/ti-sata.txt
new file mode 100644
index 0000000..bf0ea3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ti-sata.txt
@@ -0,0 +1,31 @@
+* Texas Instruments SATA Controller Wrapper
+
+Required properties:
+- compatible : "ti,sata"
+- ti,hwmods : "sata"
+- reg : Register mapping
+- #address-cells: <1>
+- #size-cells : <1>
+- ranges : allows valid translation between child's address space and parent's
+ address space.
+- Must contain at least one child node for the SATA controller core
+
+Example:
+
+ sata: sata@4a141100 {
+ compatible = "ti,sata";
+ ti,hwmods = "sata";
+ reg = <0x4a141100 0x7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dwc-ahci@4a140000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x4a140000 0x1100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ clocks = <&sata_ref_clk>;
+ clock-names = "optclk";
+ };
+ };
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index a53ef27..a3de4d2 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -138,6 +138,13 @@ config SATA_SIL24
If unsure, say N.
+config SATA_TI
+ tristate "Texas Instruments SATA Wrapper driver"
+ depends on ARCH_OMAP
+ help
+ This options enables SATA Wrapper driver for Texas Instruments SoCs.
+ It is found on OMAP5 and DRA7.
+
config ATA_SFF
bool "ATA SFF support (for legacy IDE and PATA)"
default y
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 46518c6..673ba5e 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
+obj-$(CONFIG_SATA_TI) += sata_ti.o
# SFF w/ custom DMA
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
diff --git a/drivers/ata/sata_ti.c b/drivers/ata/sata_ti.c
new file mode 100644
index 0000000..0b9093d
--- /dev/null
+++ b/drivers/ata/sata_ti.c
@@ -0,0 +1,160 @@
+/**
+ * sata-ti.c - Texas Instruments Specific SATA Glue layer
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Authors: Roger Quadros <[email protected]>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+/*
+ * All these registers belong to OMAP's Wrapper around the
+ * DesignWare SATA Core.
+ */
+
+#define SATA_SYSCONFIG 0x0000
+#define SATA_CDRLOCK 0x0004
+
+struct ti_sata {
+ struct device *dev;
+ void __iomem *base;
+};
+
+static int ti_sata_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct ti_sata *sata;
+ struct resource *res;
+ void __iomem *base;
+ int ret;
+
+ if (!np) {
+ dev_err(dev, "device node not found\n");
+ return -EINVAL;
+ }
+
+ sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
+ if (!sata)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, sata);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "missing memory base resource\n");
+ return -EINVAL;
+ }
+
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ sata->dev = dev;
+ sata->base = base;
+
+ pm_runtime_enable(dev);
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ dev_err(dev, "pm_runtime_get_sync failed with err %d\n",
+ ret);
+ goto runtime_disable;
+ }
+
+ ret = of_platform_populate(np, NULL, NULL, dev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to create TI SATA children\n");
+ goto runtime_put;
+ }
+
+ return 0;
+
+runtime_put:
+ pm_runtime_put_sync(dev);
+
+runtime_disable:
+ pm_runtime_disable(dev);
+
+ return ret;
+}
+
+static int ti_sata_remove_child(struct device *dev, void *c)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+
+ platform_device_unregister(pdev);
+
+ return 0;
+}
+
+static int ti_sata_remove(struct platform_device *pdev)
+{
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ device_for_each_child(&pdev->dev, NULL, ti_sata_remove_child);
+
+ return 0;
+}
+
+static const struct of_device_id of_ti_sata_match[] = {
+ {
+ .compatible = "ti,sata"
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, of_ti_sata_match);
+
+#ifdef CONFIG_PM
+
+static int ti_sata_resume(struct device *dev)
+{
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ return 0;
+}
+
+static const struct dev_pm_ops ti_sata_dev_pm_ops = {
+ .resume = ti_sata_resume,
+};
+
+#define DEV_PM_OPS (&ti_sata_dev_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver ti_sata_driver = {
+ .probe = ti_sata_probe,
+ .remove = ti_sata_remove,
+ .driver = {
+ .name = "ti-sata",
+ .of_match_table = of_ti_sata_match,
+ .pm = DEV_PM_OPS,
+ },
+};
+
+module_platform_driver(ti_sata_driver);
+
+MODULE_ALIAS("platform:ti-sata");
+MODULE_AUTHOR("Roger Quadros <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("TI SATA Glue Layer");
--
1.7.4.1
Update compatible property for usb3phy node.
CC: Benoit Cousson <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/boot/dts/omap5.dtsi | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 97f361a..06aa665 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -671,7 +671,7 @@
};
usb3_phy: usb3phy@4a084400 {
- compatible = "ti,omap-usb3";
+ compatible = "ti,phy-pipe3-usb3";
reg = <0x4a084400 0x80>,
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
--
1.7.4.1
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree compatible_id.
Signed-off-by: Roger Quadros <[email protected]>
---
drivers/phy/phy-omap-pipe3.c | 82 ++++++++++++++++++++++++++--------------
include/linux/phy/omap_pipe3.h | 6 +++
2 files changed, 60 insertions(+), 28 deletions(-)
diff --git a/drivers/phy/phy-omap-pipe3.c b/drivers/phy/phy-omap-pipe3.c
index 807ab8a..19d1664 100644
--- a/drivers/phy/phy-omap-pipe3.c
+++ b/drivers/phy/phy-omap-pipe3.c
@@ -58,29 +58,41 @@
*/
# define PLL_IDLE_TIME 100;
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { }, /* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
+ {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { }, /* Terminator */
};
-static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
+ *pipe3)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
- for (i = 0; i < ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return &dpll_map[i].params;
+ rate = clk_get_rate(pipe3->sys_clk);
+
+ for (; dpll_map->rate; dpll_map++) {
+ if (rate == dpll_map->rate)
+ return &dpll_map->params;
}
+ dev_err(pipe3->dev,
+ "No DPLL configuration for %lu Hz SYS CLK\n", rate);
return 0;
}
@@ -148,10 +160,8 @@ static int omap_pipe3_dpll_lock(struct omap_pipe3 *phy)
struct pipe3_dpll_params *dpll_params;
rate = clk_get_rate(phy->sys_clk);
- dpll_params = omap_pipe3_get_dpll_params(rate);
+ dpll_params = omap_pipe3_get_dpll_params(phy);
if (!dpll_params) {
- dev_err(phy->dev,
- "No DPLL configuration for %lu Hz SYS CLK\n", rate);
return -EINVAL;
}
@@ -206,6 +216,25 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id omap_pipe3_id_table[] = {
+ {
+ .compatible = "ti,omap-pipe3",
+ .data = dpll_map_usb,
+ },
+ {
+ .compatible = "ti,omap-sata",
+ .data = dpll_map_sata,
+ },
+ {
+ .compatible = "ti,omap-usb3",
+ .data = dpll_map_usb,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, omap_pipe3_id_table);
+#endif
+
static int omap_pipe3_probe(struct platform_device *pdev)
{
struct omap_pipe3 *phy;
@@ -215,9 +244,7 @@ static int omap_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
-
- if (!node)
- return -EINVAL;
+ const struct of_device_id *match;
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
@@ -225,6 +252,16 @@ static int omap_pipe3_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ match = of_match_device(of_match_ptr(omap_pipe3_id_table), &pdev->dev);
+ if (!match)
+ return -EINVAL;
+
+ phy->dpll_map = (struct pipe3_dpll_map *)match->data;
+ if (!phy->dpll_map) {
+ dev_err(&pdev->dev, "no dpll data\n");
+ return -EINVAL;
+ }
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(phy->pll_ctrl_base))
@@ -354,17 +391,6 @@ static const struct dev_pm_ops omap_pipe3_pm_ops = {
#define DEV_PM_OPS NULL
#endif
-#ifdef CONFIG_OF
-static const struct of_device_id omap_pipe3_id_table[] = {
- { .compatible = "ti,omap-pipe3" },
- { .compatible = "ti,omap-sata" },
- { .compatible = "ti,omap-pcie" },
- { .compatible = "ti,omap-usb3" },
- {}
-};
-MODULE_DEVICE_TABLE(of, omap_pipe3_id_table);
-#endif
-
static struct platform_driver omap_pipe3_driver = {
.probe = omap_pipe3_probe,
.remove = omap_pipe3_remove,
diff --git a/include/linux/phy/omap_pipe3.h b/include/linux/phy/omap_pipe3.h
index 7329056..86825ca 100644
--- a/include/linux/phy/omap_pipe3.h
+++ b/include/linux/phy/omap_pipe3.h
@@ -29,6 +29,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct omap_pipe3 {
void __iomem *pll_ctrl_base;
struct device *dev;
@@ -36,6 +41,7 @@ struct omap_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *optclk;
+ struct pipe3_dpll_map *dpll_map;
};
static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
--
1.7.4.1
From: Kishon Vijay Abraham I <[email protected]>
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
drivers/phy/Kconfig | 14 ++-
drivers/phy/Makefile | 1 +
drivers/phy/phy-omap-control.c | 300 ++++++++++++++++++++++++++++++++++
drivers/phy/phy-omap-pipe3.c | 8 +-
drivers/phy/phy-omap-usb2.c | 9 +-
drivers/usb/musb/omap2430.c | 2 +-
drivers/usb/phy/Kconfig | 10 -
drivers/usb/phy/Makefile | 1 -
drivers/usb/phy/phy-omap-control.c | 300 ----------------------------------
include/linux/phy/omap_control_phy.h | 83 ++++++++++
include/linux/usb/omap_control_usb.h | 83 ----------
11 files changed, 406 insertions(+), 405 deletions(-)
create mode 100644 drivers/phy/phy-omap-control.c
delete mode 100644 drivers/usb/phy/phy-omap-control.c
create mode 100644 include/linux/phy/omap_control_phy.h
delete mode 100644 include/linux/usb/omap_control_usb.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5c2e7a0..7155f56 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -15,12 +15,22 @@ config GENERIC_PHY
phy users can obtain reference to the PHY. All the users of this
framework should select this config.
+config OMAP_CONTROL_PHY
+ tristate "OMAP CONTROL PHY Driver"
+ help
+ Enable this to add support for the PHY part present in the control
+ module. This driver has API to power on the USB2 PHY and to write to
+ the mailbox. The mailbox is present only in omap4 and the register to
+ power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
+ additional register to power on USB3 PHY/SATA PHY/PCIE PHY
+ (PIPE3 PHY).
+
config OMAP_USB2
tristate "OMAP USB2 PHY Driver"
depends on ARCH_OMAP2PLUS
select GENERIC_PHY
select USB_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the transceiver that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator.
@@ -30,7 +40,7 @@ config OMAP_USB2
config OMAP_PIPE3
tristate "OMAP PIPE3 PHY Driver"
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the PIPE3 PHY that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator.
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 48bf9f2..f0127f6 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
+obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_OMAP_PIPE3) += phy-omap-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
new file mode 100644
index 0000000..5b85478
--- /dev/null
+++ b/drivers/phy/phy-omap-control.c
@@ -0,0 +1,300 @@
+/*
+ * omap-control-phy.c - The PHY part of control module.
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I <[email protected]>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/phy/omap_control_phy.h>
+
+/**
+ * omap_control_phy_power - power on/off the phy using control module reg
+ * @dev: the control module device
+ * @on: 0 or 1, based on powering on or off the PHY
+ */
+void omap_control_phy_power(struct device *dev, int on)
+{
+ u32 val;
+ unsigned long rate;
+ struct omap_control_phy *control_phy;
+
+ if (IS_ERR(dev) || !dev) {
+ pr_err("%s: invalid device\n", __func__);
+ return;
+ }
+
+ control_phy = dev_get_drvdata(dev);
+ if (!control_phy) {
+ dev_err(dev, "%s: invalid control phy device\n", __func__);
+ return;
+ }
+
+ if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
+ return;
+
+ val = readl(control_phy->power);
+
+ switch (control_phy->type) {
+ case OMAP_CTRL_TYPE_USB2:
+ if (on)
+ val &= ~OMAP_CTRL_DEV_PHY_PD;
+ else
+ val |= OMAP_CTRL_DEV_PHY_PD;
+ break;
+
+ case OMAP_CTRL_TYPE_PIPE3:
+ rate = clk_get_rate(control_phy->sys_clk);
+ rate = rate/1000000;
+
+ if (on) {
+ val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+ val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ val |= rate <<
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+ } else {
+ val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+ val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ }
+ break;
+
+ case OMAP_CTRL_TYPE_DRA7USB2:
+ if (on)
+ val &= ~OMAP_CTRL_USB2_PHY_PD;
+ else
+ val |= OMAP_CTRL_USB2_PHY_PD;
+ break;
+ default:
+ dev_err(dev, "%s: type %d not recognized\n",
+ __func__, control_phy->type);
+ break;
+ }
+
+ writel(val, control_phy->power);
+}
+EXPORT_SYMBOL_GPL(omap_control_phy_power);
+
+/**
+ * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
+ * @ctrl_phy: struct omap_control_phy *
+ *
+ * Writes to the mailbox register to notify the usb core that a usb
+ * device has been connected.
+ */
+static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
+{
+ u32 val;
+
+ val = readl(ctrl_phy->otghs_control);
+ val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
+ val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
+ writel(val, ctrl_phy->otghs_control);
+}
+
+/**
+ * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
+ * impedance
+ * @ctrl_phy: struct omap_control_phy *
+ *
+ * Writes to the mailbox register to notify the usb core that it has been
+ * connected to a usb host.
+ */
+static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
+{
+ u32 val;
+
+ val = readl(ctrl_phy->otghs_control);
+ val &= ~OMAP_CTRL_DEV_SESSEND;
+ val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
+ OMAP_CTRL_DEV_VBUSVALID;
+ writel(val, ctrl_phy->otghs_control);
+}
+
+/**
+ * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
+ * impedance
+ * @ctrl_phy: struct omap_control_phy *
+ *
+ * Writes to the mailbox register to notify the usb core it's now in
+ * disconnected state.
+ */
+static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
+{
+ u32 val;
+
+ val = readl(ctrl_phy->otghs_control);
+ val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
+ val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
+ writel(val, ctrl_phy->otghs_control);
+}
+
+/**
+ * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
+ * or device mode or to denote disconnected state
+ * @dev: the control module device
+ * @mode: The mode to which usb should be configured
+ *
+ * This is an API to write to the mailbox register to notify the usb core that
+ * a usb device has been connected.
+ */
+void omap_control_usb_set_mode(struct device *dev,
+ enum omap_control_usb_mode mode)
+{
+ struct omap_control_phy *ctrl_phy;
+
+ if (IS_ERR(dev) || !dev)
+ return;
+
+ ctrl_phy = dev_get_drvdata(dev);
+
+ if (!ctrl_phy) {
+ dev_err(dev, "Invalid control phy device\n");
+ return;
+ }
+
+ if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
+ return;
+
+ switch (mode) {
+ case USB_MODE_HOST:
+ omap_control_usb_host_mode(ctrl_phy);
+ break;
+ case USB_MODE_DEVICE:
+ omap_control_usb_device_mode(ctrl_phy);
+ break;
+ case USB_MODE_DISCONNECT:
+ omap_control_usb_set_sessionend(ctrl_phy);
+ break;
+ default:
+ dev_vdbg(dev, "invalid omap control usb mode\n");
+ }
+}
+EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
+
+#ifdef CONFIG_OF
+
+static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
+static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
+static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
+static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
+
+static const struct of_device_id omap_control_phy_id_table[] = {
+ {
+ .compatible = "ti,control-phy-otghs",
+ .data = &otghs_data,
+ },
+ {
+ .compatible = "ti,control-phy-usb2",
+ .data = &usb2_data,
+ },
+ {
+ .compatible = "ti,control-phy-pipe3",
+ .data = &pipe3_data,
+ },
+ {
+ .compatible = "ti,control-phy-dra7usb2",
+ .data = &dra7usb2_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
+#endif
+
+static int omap_control_phy_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ const struct of_device_id *of_id;
+ struct omap_control_phy *control_phy;
+
+ of_id = of_match_device(of_match_ptr(omap_control_phy_id_table),
+ &pdev->dev);
+ if (!of_id)
+ return -EINVAL;
+
+ control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
+ GFP_KERNEL);
+ if (!control_phy) {
+ dev_err(&pdev->dev, "unable to alloc memory for control phy\n");
+ return -ENOMEM;
+ }
+
+ control_phy->dev = &pdev->dev;
+ control_phy->type = *(enum omap_control_phy_type *)of_id->data;
+
+ if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "otghs_control");
+ control_phy->otghs_control = devm_ioremap_resource(
+ &pdev->dev, res);
+ if (IS_ERR(control_phy->otghs_control))
+ return PTR_ERR(control_phy->otghs_control);
+ } else {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "power");
+ control_phy->power = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(control_phy->power)) {
+ dev_err(&pdev->dev, "Couldn't get power register\n");
+ return PTR_ERR(control_phy->power);
+ }
+ }
+
+ if (control_phy->type == OMAP_CTRL_TYPE_PIPE3) {
+ control_phy->sys_clk = devm_clk_get(control_phy->dev,
+ "sys_clkin");
+ if (IS_ERR(control_phy->sys_clk)) {
+ pr_err("%s: unable to get sys_clkin\n", __func__);
+ return -EINVAL;
+ }
+ }
+
+ dev_set_drvdata(control_phy->dev, control_phy);
+
+ return 0;
+}
+
+static struct platform_driver omap_control_phy_driver = {
+ .probe = omap_control_phy_probe,
+ .driver = {
+ .name = "omap-control-phy",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(omap_control_phy_id_table),
+ },
+};
+
+static int __init omap_control_phy_init(void)
+{
+ return platform_driver_register(&omap_control_phy_driver);
+}
+subsys_initcall(omap_control_phy_init);
+
+static void __exit omap_control_phy_exit(void)
+{
+ platform_driver_unregister(&omap_control_phy_driver);
+}
+module_exit(omap_control_phy_exit);
+
+MODULE_ALIAS("platform: omap_control_phy");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-omap-pipe3.c b/drivers/phy/phy-omap-pipe3.c
index ee9a901..63de0f8 100644
--- a/drivers/phy/phy-omap-pipe3.c
+++ b/drivers/phy/phy-omap-pipe3.c
@@ -26,7 +26,7 @@
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
-#include <linux/usb/omap_control_usb.h>
+#include <linux/phy/omap_control_phy.h>
#include <linux/of_platform.h>
#define PLL_STATUS 0x00000004
@@ -101,7 +101,7 @@ static int omap_pipe3_power_off(struct phy *x)
udelay(1);
} while (--timeout);
- omap_control_usb_phy_power(phy->control_dev, 0);
+ omap_control_phy_power(phy->control_dev, 0);
return 0;
}
@@ -194,7 +194,7 @@ static int omap_pipe3_init(struct phy *x)
if (ret)
return ret;
- omap_control_usb_phy_power(phy->control_dev, 1);
+ omap_control_phy_power(phy->control_dev, 1);
return 0;
}
@@ -270,7 +270,7 @@ static int omap_pipe3_probe(struct platform_device *pdev)
phy->control_dev = &control_pdev->dev;
- omap_control_usb_phy_power(phy->control_dev, 0);
+ omap_control_phy_power(phy->control_dev, 0);
platform_set_drvdata(pdev, phy);
pm_runtime_enable(phy->dev);
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 332178d..9c231b8 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -27,7 +27,8 @@
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
-#include <linux/usb/omap_control_usb.h>
+#include <linux/phy/omap_control_phy.h>
+#include <linux/phy/phy.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
@@ -102,7 +103,7 @@ static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
- omap_control_usb_phy_power(phy->control_dev, 0);
+ omap_control_phy_power(phy->control_dev, 0);
return 0;
}
@@ -111,7 +112,7 @@ static int omap_usb_power_on(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
- omap_control_usb_phy_power(phy->control_dev, 1);
+ omap_control_phy_power(phy->control_dev, 1);
return 0;
}
@@ -172,7 +173,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy->control_dev = &control_pdev->dev;
- omap_control_usb_phy_power(phy->control_dev, 0);
+ omap_control_phy_power(phy->control_dev, 0);
otg->set_host = omap_usb_set_host;
otg->set_peripheral = omap_usb_set_peripheral;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 9eab645..4f5ef0b 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -37,7 +37,7 @@
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/usb/musb-omap.h>
-#include <linux/usb/omap_control_usb.h>
+#include <linux/phy/omap_control_phy.h>
#include <linux/of_platform.h>
#include "musb_core.h"
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 0210e03..f517d49 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -56,16 +56,6 @@ config NOP_USB_XCEIV
built-in with usb ip or which are autonomous and doesn't require any
phy programming such as ISP1x04 etc.
-config OMAP_CONTROL_USB
- tristate "OMAP CONTROL USB Driver"
- depends on ARCH_OMAP2PLUS || COMPILE_TEST
- help
- Enable this to add support for the USB part present in the control
- module. This driver has API to power on the USB2 PHY and to write to
- the mailbox. The mailbox is present only in omap4 and the register to
- power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
- additional register to power on USB3 PHY.
-
config AM335X_CONTROL_USB
tristate
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index fa80661..b356953 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_FSL_USB2_OTG) += phy-fsl-usb2.o
obj-$(CONFIG_ISP1301_OMAP) += phy-isp1301-omap.o
obj-$(CONFIG_MV_U3D_PHY) += phy-mv-u3d-usb.o
obj-$(CONFIG_NOP_USB_XCEIV) += phy-generic.o
-obj-$(CONFIG_OMAP_CONTROL_USB) += phy-omap-control.o
obj-$(CONFIG_AM335X_CONTROL_USB) += phy-am335x-control.o
obj-$(CONFIG_AM335X_PHY_USB) += phy-am335x.o
obj-$(CONFIG_SAMSUNG_USBPHY) += phy-samsung-usb.o
diff --git a/drivers/usb/phy/phy-omap-control.c b/drivers/usb/phy/phy-omap-control.c
deleted file mode 100644
index 09c5ace..0000000
--- a/drivers/usb/phy/phy-omap-control.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * omap-control-usb.c - The USB part of control module.
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Author: Kishon Vijay Abraham I <[email protected]>
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/usb/omap_control_usb.h>
-
-/**
- * omap_control_usb_phy_power - power on/off the phy using control module reg
- * @dev: the control module device
- * @on: 0 or 1, based on powering on or off the PHY
- */
-void omap_control_usb_phy_power(struct device *dev, int on)
-{
- u32 val;
- unsigned long rate;
- struct omap_control_usb *control_usb;
-
- if (IS_ERR(dev) || !dev) {
- pr_err("%s: invalid device\n", __func__);
- return;
- }
-
- control_usb = dev_get_drvdata(dev);
- if (!control_usb) {
- dev_err(dev, "%s: invalid control usb device\n", __func__);
- return;
- }
-
- if (control_usb->type == OMAP_CTRL_TYPE_OTGHS)
- return;
-
- val = readl(control_usb->power);
-
- switch (control_usb->type) {
- case OMAP_CTRL_TYPE_USB2:
- if (on)
- val &= ~OMAP_CTRL_DEV_PHY_PD;
- else
- val |= OMAP_CTRL_DEV_PHY_PD;
- break;
-
- case OMAP_CTRL_TYPE_PIPE3:
- rate = clk_get_rate(control_usb->sys_clk);
- rate = rate/1000000;
-
- if (on) {
- val &= ~(OMAP_CTRL_USB_PWRCTL_CLK_CMD_MASK |
- OMAP_CTRL_USB_PWRCTL_CLK_FREQ_MASK);
- val |= OMAP_CTRL_USB3_PHY_TX_RX_POWERON <<
- OMAP_CTRL_USB_PWRCTL_CLK_CMD_SHIFT;
- val |= rate << OMAP_CTRL_USB_PWRCTL_CLK_FREQ_SHIFT;
- } else {
- val &= ~OMAP_CTRL_USB_PWRCTL_CLK_CMD_MASK;
- val |= OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF <<
- OMAP_CTRL_USB_PWRCTL_CLK_CMD_SHIFT;
- }
- break;
-
- case OMAP_CTRL_TYPE_DRA7USB2:
- if (on)
- val &= ~OMAP_CTRL_USB2_PHY_PD;
- else
- val |= OMAP_CTRL_USB2_PHY_PD;
- break;
- default:
- dev_err(dev, "%s: type %d not recognized\n",
- __func__, control_usb->type);
- break;
- }
-
- writel(val, control_usb->power);
-}
-EXPORT_SYMBOL_GPL(omap_control_usb_phy_power);
-
-/**
- * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
- * @ctrl_usb: struct omap_control_usb *
- *
- * Writes to the mailbox register to notify the usb core that a usb
- * device has been connected.
- */
-static void omap_control_usb_host_mode(struct omap_control_usb *ctrl_usb)
-{
- u32 val;
-
- val = readl(ctrl_usb->otghs_control);
- val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
- val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
- writel(val, ctrl_usb->otghs_control);
-}
-
-/**
- * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
- * impedance
- * @ctrl_usb: struct omap_control_usb *
- *
- * Writes to the mailbox register to notify the usb core that it has been
- * connected to a usb host.
- */
-static void omap_control_usb_device_mode(struct omap_control_usb *ctrl_usb)
-{
- u32 val;
-
- val = readl(ctrl_usb->otghs_control);
- val &= ~OMAP_CTRL_DEV_SESSEND;
- val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
- OMAP_CTRL_DEV_VBUSVALID;
- writel(val, ctrl_usb->otghs_control);
-}
-
-/**
- * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
- * impedance
- * @ctrl_usb: struct omap_control_usb *
- *
- * Writes to the mailbox register to notify the usb core it's now in
- * disconnected state.
- */
-static void omap_control_usb_set_sessionend(struct omap_control_usb *ctrl_usb)
-{
- u32 val;
-
- val = readl(ctrl_usb->otghs_control);
- val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
- val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
- writel(val, ctrl_usb->otghs_control);
-}
-
-/**
- * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
- * or device mode or to denote disconnected state
- * @dev: the control module device
- * @mode: The mode to which usb should be configured
- *
- * This is an API to write to the mailbox register to notify the usb core that
- * a usb device has been connected.
- */
-void omap_control_usb_set_mode(struct device *dev,
- enum omap_control_usb_mode mode)
-{
- struct omap_control_usb *ctrl_usb;
-
- if (IS_ERR(dev) || !dev)
- return;
-
- ctrl_usb = dev_get_drvdata(dev);
-
- if (!ctrl_usb) {
- dev_err(dev, "Invalid control usb device\n");
- return;
- }
-
- if (ctrl_usb->type != OMAP_CTRL_TYPE_OTGHS)
- return;
-
- switch (mode) {
- case USB_MODE_HOST:
- omap_control_usb_host_mode(ctrl_usb);
- break;
- case USB_MODE_DEVICE:
- omap_control_usb_device_mode(ctrl_usb);
- break;
- case USB_MODE_DISCONNECT:
- omap_control_usb_set_sessionend(ctrl_usb);
- break;
- default:
- dev_vdbg(dev, "invalid omap control usb mode\n");
- }
-}
-EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
-
-#ifdef CONFIG_OF
-
-static const enum omap_control_usb_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
-static const enum omap_control_usb_type usb2_data = OMAP_CTRL_TYPE_USB2;
-static const enum omap_control_usb_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
-static const enum omap_control_usb_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
-
-static const struct of_device_id omap_control_usb_id_table[] = {
- {
- .compatible = "ti,control-phy-otghs",
- .data = &otghs_data,
- },
- {
- .compatible = "ti,control-phy-usb2",
- .data = &usb2_data,
- },
- {
- .compatible = "ti,control-phy-pipe3",
- .data = &pipe3_data,
- },
- {
- .compatible = "ti,control-phy-dra7usb2",
- .data = &dra7usb2_data,
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, omap_control_usb_id_table);
-#endif
-
-
-static int omap_control_usb_probe(struct platform_device *pdev)
-{
- struct resource *res;
- const struct of_device_id *of_id;
- struct omap_control_usb *control_usb;
-
- of_id = of_match_device(of_match_ptr(omap_control_usb_id_table),
- &pdev->dev);
- if (!of_id)
- return -EINVAL;
-
- control_usb = devm_kzalloc(&pdev->dev, sizeof(*control_usb),
- GFP_KERNEL);
- if (!control_usb) {
- dev_err(&pdev->dev, "unable to alloc memory for control usb\n");
- return -ENOMEM;
- }
-
- control_usb->dev = &pdev->dev;
- control_usb->type = *(enum omap_control_usb_type *)of_id->data;
-
- if (control_usb->type == OMAP_CTRL_TYPE_OTGHS) {
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "otghs_control");
- control_usb->otghs_control = devm_ioremap_resource(
- &pdev->dev, res);
- if (IS_ERR(control_usb->otghs_control))
- return PTR_ERR(control_usb->otghs_control);
- } else {
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "power");
- control_usb->power = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(control_usb->power)) {
- dev_err(&pdev->dev, "Couldn't get power register\n");
- return PTR_ERR(control_usb->power);
- }
- }
-
- if (control_usb->type == OMAP_CTRL_TYPE_PIPE3) {
- control_usb->sys_clk = devm_clk_get(control_usb->dev,
- "sys_clkin");
- if (IS_ERR(control_usb->sys_clk)) {
- pr_err("%s: unable to get sys_clkin\n", __func__);
- return -EINVAL;
- }
- }
-
- dev_set_drvdata(control_usb->dev, control_usb);
-
- return 0;
-}
-
-static struct platform_driver omap_control_usb_driver = {
- .probe = omap_control_usb_probe,
- .driver = {
- .name = "omap-control-usb",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(omap_control_usb_id_table),
- },
-};
-
-static int __init omap_control_usb_init(void)
-{
- return platform_driver_register(&omap_control_usb_driver);
-}
-subsys_initcall(omap_control_usb_init);
-
-static void __exit omap_control_usb_exit(void)
-{
- platform_driver_unregister(&omap_control_usb_driver);
-}
-module_exit(omap_control_usb_exit);
-
-MODULE_ALIAS("platform: omap_control_usb");
-MODULE_AUTHOR("Texas Instruments Inc.");
-MODULE_DESCRIPTION("OMAP Control Module USB Driver");
-MODULE_LICENSE("GPL v2");
diff --git a/include/linux/phy/omap_control_phy.h b/include/linux/phy/omap_control_phy.h
new file mode 100644
index 0000000..44ad1fc
--- /dev/null
+++ b/include/linux/phy/omap_control_phy.h
@@ -0,0 +1,83 @@
+/*
+ * omap_control_phy.h - Header file for the PHY part of control module.
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I <[email protected]>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __OMAP_CONTROL_PHY_H__
+#define __OMAP_CONTROL_PHY_H__
+
+enum omap_control_phy_type {
+ OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */
+ OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */
+ OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
+ OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
+};
+
+struct omap_control_phy {
+ struct device *dev;
+
+ u32 __iomem *otghs_control;
+ u32 __iomem *power;
+ u32 __iomem *power_aux;
+
+ struct clk *sys_clk;
+
+ enum omap_control_phy_type type;
+};
+
+enum omap_control_usb_mode {
+ USB_MODE_UNDEFINED = 0,
+ USB_MODE_HOST,
+ USB_MODE_DEVICE,
+ USB_MODE_DISCONNECT,
+};
+
+#define OMAP_CTRL_DEV_PHY_PD BIT(0)
+
+#define OMAP_CTRL_DEV_AVALID BIT(0)
+#define OMAP_CTRL_DEV_BVALID BIT(1)
+#define OMAP_CTRL_DEV_VBUSVALID BIT(2)
+#define OMAP_CTRL_DEV_SESSEND BIT(3)
+#define OMAP_CTRL_DEV_IDDIG BIT(4)
+
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
+
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
+
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
+
+#define OMAP_CTRL_USB2_PHY_PD BIT(28)
+
+#if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
+extern void omap_control_phy_power(struct device *dev, int on);
+extern void omap_control_usb_set_mode(struct device *dev,
+ enum omap_control_usb_mode mode);
+#else
+
+static inline void omap_control_phy_power(struct device *dev, int on)
+{
+}
+
+static inline void omap_control_usb_set_mode(struct device *dev,
+ enum omap_control_usb_mode mode)
+{
+}
+#endif
+
+#endif /* __OMAP_CONTROL_PHY_H__ */
diff --git a/include/linux/usb/omap_control_usb.h b/include/linux/usb/omap_control_usb.h
deleted file mode 100644
index 596b019..0000000
--- a/include/linux/usb/omap_control_usb.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * omap_control_usb.h - Header file for the USB part of control module.
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Author: Kishon Vijay Abraham I <[email protected]>
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __OMAP_CONTROL_USB_H__
-#define __OMAP_CONTROL_USB_H__
-
-enum omap_control_usb_type {
- OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */
- OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */
- OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
- OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
-};
-
-struct omap_control_usb {
- struct device *dev;
-
- u32 __iomem *otghs_control;
- u32 __iomem *power;
- u32 __iomem *power_aux;
-
- struct clk *sys_clk;
-
- enum omap_control_usb_type type;
-};
-
-enum omap_control_usb_mode {
- USB_MODE_UNDEFINED = 0,
- USB_MODE_HOST,
- USB_MODE_DEVICE,
- USB_MODE_DISCONNECT,
-};
-
-#define OMAP_CTRL_DEV_PHY_PD BIT(0)
-
-#define OMAP_CTRL_DEV_AVALID BIT(0)
-#define OMAP_CTRL_DEV_BVALID BIT(1)
-#define OMAP_CTRL_DEV_VBUSVALID BIT(2)
-#define OMAP_CTRL_DEV_SESSEND BIT(3)
-#define OMAP_CTRL_DEV_IDDIG BIT(4)
-
-#define OMAP_CTRL_USB_PWRCTL_CLK_CMD_MASK 0x003FC000
-#define OMAP_CTRL_USB_PWRCTL_CLK_CMD_SHIFT 0xE
-
-#define OMAP_CTRL_USB_PWRCTL_CLK_FREQ_MASK 0xFFC00000
-#define OMAP_CTRL_USB_PWRCTL_CLK_FREQ_SHIFT 0x16
-
-#define OMAP_CTRL_USB3_PHY_TX_RX_POWERON 0x3
-#define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF 0x0
-
-#define OMAP_CTRL_USB2_PHY_PD BIT(28)
-
-#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
-extern void omap_control_usb_phy_power(struct device *dev, int on);
-extern void omap_control_usb_set_mode(struct device *dev,
- enum omap_control_usb_mode mode);
-#else
-
-static inline void omap_control_usb_phy_power(struct device *dev, int on)
-{
-}
-
-static inline void omap_control_usb_set_mode(struct device *dev,
- enum omap_control_usb_mode mode)
-{
-}
-#endif
-
-#endif /* __OMAP_CONTROL_USB_H__ */
--
1.7.4.1
From: Keshava Munegowda <[email protected]>
Create hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson <[email protected]>
Signed-off-by: Balaji T K <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 72 ++++++++++++++++++++++++++++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 3dae6b9..2b698b8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -1545,6 +1545,76 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
},
};
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+/* ocp2scp3 */
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_ocp2scp3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
+ .name = "ocp2scp3",
+ .class = &omap54xx_ocp2scp_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'sata' class
+ * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
+ .sysc_offs = 0x0000,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
+ .name = "sata",
+ .sysc = &omap54xx_sata_sysc,
+};
+
+/* sata */
+static struct omap_hwmod omap54xx_sata_hwmod = {
+ .name = "sata",
+ .class = &omap54xx_sata_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* l4_cfg -> sata */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_sata_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
/*
* Interfaces
@@ -2192,6 +2262,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l4_per__uart6,
&omap54xx_l4_cfg__usb_otg_ss,
&omap54xx_l4_wkup__wd_timer2,
+ &omap54xx_l4_cfg__ocp2scp3,
+ &omap54xx_l4_cfg__sata,
NULL,
};
--
1.7.4.1
From: Benoit Cousson <[email protected]>
without that hwmod data, USB3 will not in OMAP5 boards.
Signed-off-by: Benoit Cousson <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
---
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 45 ++++++++++++++++++++++++++++
1 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 2b698b8..e7d4fcb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -1146,6 +1146,42 @@ static struct omap_hwmod omap54xx_mpu_hwmod = {
};
/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
+ .name = "ocp2scp",
+ .sysc = &omap54xx_ocp2scp_sysc,
+};
+
+/* ocp2scp1 */
+static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
+ .name = "ocp2scp1",
+ .class = &omap54xx_ocp2scp_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
+ .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
* 'timer' class
* general purpose timer module with accurate 1ms tick
* This class contains several variants: ['timer_1ms', 'timer']
@@ -2040,6 +2076,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> ocp2scp1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
+ .master = &omap54xx_l4_cfg_hwmod,
+ .slave = &omap54xx_ocp2scp1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
.master = &omap54xx_l4_wkup_hwmod,
@@ -2243,6 +2287,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l4_per__mmc4,
&omap54xx_l4_per__mmc5,
&omap54xx_l4_cfg__mpu,
+ &omap54xx_l4_cfg__ocp2scp1,
&omap54xx_l4_wkup__timer1,
&omap54xx_l4_per__timer2,
&omap54xx_l4_per__timer3,
--
1.7.4.1
Add OCP2SCP1 module address space.
CC: Benoit Cousson <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/boot/dts/omap5.dtsi | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 06aa665..8a88a94 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -663,6 +663,7 @@
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp1";
+ reg = <0x4a080000 0x1f>;
usb2_phy: usb2phy@4a084000 {
compatible = "ti,omap-usb2";
reg = <0x4a084000 0x7c>;
--
1.7.4.1
From: Balaji T K <[email protected]>
Add support for sata.
[Roger Q] Clean up.
CC: Benoit Cousson <[email protected]>
Signed-off-by: Balaji T K <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/boot/dts/omap5.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++-
1 files changed, 50 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 8a88a94..a79ccb7 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -434,6 +434,53 @@
dma-names = "tx", "rx";
};
+ omap_control_sata: control-phy@4a002374 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a002374 0x4>;
+ reg-names = "power";
+ clocks = <&sys_clkin>;
+ clock-names = "sysclk";
+ };
+
+ ocp2scp3: ocp2scp3@4a090000 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "ocp2scp3";
+ reg = <0x4a090000 0x1f>; /* ocp2scp3 */
+ reg-names = "ocp2scp3";
+ sata_phy: sataphy@4A096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4A096000 0x80>, /* phy_rx */
+ <0x4A096400 0x64>, /* phy_tx */
+ <0x4A096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_sata>;
+ clocks = <&sys_clkin>;
+ clock-names = "sysclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ sata: sata@4a141100 {
+ compatible = "ti,sata";
+ ti,hwmods = "sata";
+ reg = <0x4a141100 0x7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dwc-ahci@4a140000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x4a140000 0x1100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ clocks = <&sata_ref_clk>;
+ clock-names = "optclk";
+ };
+ };
+
keypad: keypad@4ae1c000 {
compatible = "ti,omap4-keypad";
reg = <0x4ae1c000 0x400>;
@@ -636,6 +683,8 @@
compatible = "ti,control-phy-pipe3";
reg = <0x4a002370 0x4>;
reg-names = "power";
+ clocks = <&sys_clkin>;
+ clock-names = "sysclk";
};
omap_dwc3@4a020000 {
@@ -657,7 +706,7 @@
};
};
- ocp2scp {
+ ocp2scp1: ocp2scp1@4a080000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
--
1.7.4.1
From: Nikhil Devshatwar <[email protected]>
Add hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson <[email protected]>
Signed-off-by: Balaji T K <[email protected]>
Signed-off-by: Nikhil Devshatwar <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 40 +++++++++++++++++++++++++---
1 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index f647998b..4d7d70f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1215,6 +1215,40 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
},
};
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
+static struct omap_hwmod_addr_space dra7xx_ocp2scp3_addrs[] = {
+ {
+ .name = "ocp2scp3",
+ .pa_start = 0x4a090000,
+ .pa_end = 0x4a09001f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_ocp2scp3_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_ocp2scp3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+ .name = "ocp2scp3",
+ .class = &dra7xx_ocp2scp_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
/*
* 'qspi' class
*
@@ -1268,9 +1302,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
};
/* sata */
-static struct omap_hwmod_opt_clk sata_opt_clks[] = {
- { .role = "ref_clk", .clk = "sata_ref_clk" },
-};
static struct omap_hwmod dra7xx_sata_hwmod = {
.name = "sata",
@@ -1285,8 +1316,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .opt_clks = sata_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
};
/*
@@ -2683,6 +2712,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per1__mmc4,
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
+ &dra7xx_l4_cfg__ocp2scp3,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
--
1.7.4.1
From: Balaji T K <[email protected]>
Add support for sata controller.
[Roger Q] Clean up.
CC: Benoit Cousson <[email protected]>
Signed-off-by: Balaji T K <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/boot/dts/dra7.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 49 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ce9a0f0..545545d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -426,6 +426,55 @@
dma-names = "tx", "rx";
};
+ omap_control_sata: control-phy@4a002374 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a002374 0x4>;
+ reg-names = "power";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
+ ocp2scp3: ocp2scp3@4a090000 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "ocp2scp3";
+ reg = <0x4a090000 0x1f>; /* ocp2scp3 */
+ reg-names = "ocp2scp3";
+ sata_phy: sataphy@4A096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4A096000 0x80>, /* phy_rx */
+ <0x4A096400 0x64>, /* phy_tx */
+ <0x4A096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_sata>;
+ clocks = <&sata_ref_clk>,
+ <&sys_clkin1>;
+ clock-names = "optclk", "sysclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ sata: sata@4a141100 {
+ compatible = "ti,sata";
+ ti,hwmods = "sata";
+ reg = <0x4a141100 0x7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dwc-ahci@4a140000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x4a140000 0x1100>;
+ interrupts = <0 54 0x4>;
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ clocks = <&sata_ref_clk>;
+ clock-names = "optclk";
+ };
+ };
+
+
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
reg = <0x48098000 0x200>;
--
1.7.4.1
Hello.
On 09/19/2013 05:24 PM, Roger Quadros wrote:
> From: Balaji T K <[email protected]>
> Add support for sata controller.
> [Roger Q] Clean up.
> CC: Benoit Cousson <[email protected]>
> Signed-off-by: Balaji T K <[email protected]>
> Signed-off-by: Roger Quadros <[email protected]>
> ---
> arch/arm/boot/dts/dra7.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 49 insertions(+), 0 deletions(-)
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index ce9a0f0..545545d 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -426,6 +426,55 @@
> dma-names = "tx", "rx";
> };
>
> + omap_control_sata: control-phy@4a002374 {
> + compatible = "ti,control-phy-pipe3";
> + reg = <0x4a002374 0x4>;
> + reg-names = "power";
> + clocks = <&sys_clkin1>;
> + clock-names = "sysclk";
> + };
> +
> + ocp2scp3: ocp2scp3@4a090000 {
> + compatible = "ti,omap-ocp2scp";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + ti,hwmods = "ocp2scp3";
> + reg = <0x4a090000 0x1f>; /* ocp2scp3 */
> + reg-names = "ocp2scp3";
> + sata_phy: sataphy@4A096000 {
It's better to name the PHY nodes uniformly after already standard
"ethernet-phy" and your "control-phy".
> + compatible = "ti,phy-pipe3-sata";
> + reg = <0x4A096000 0x80>, /* phy_rx */
> + <0x4A096400 0x64>, /* phy_tx */
> + <0x4A096800 0x40>; /* pll_ctrl */
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + ctrl-module = <&omap_control_sata>;
> + clocks = <&sata_ref_clk>,
> + <&sys_clkin1>;
> + clock-names = "optclk", "sysclk";
> + #phy-cells = <0>;
> + };
> + };
> +
> + sata: sata@4a141100 {
> + compatible = "ti,sata";
> + ti,hwmods = "sata";
> + reg = <0x4a141100 0x7>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + dwc-ahci@4a140000 {
Hm, ePAPR spec. [1] says that "the name of a node should be somewhat
generic, reflecting the function of the device and not its precise programming
model", so it looks like the name should be "sata" as well. I'm a bit at a
loss here, not sure why you had to use the nested device nodes.
> + compatible = "snps,dwc-ahci";
> + reg = <0x4a140000 0x1100>;
> + interrupts = <0 54 0x4>;
> + phys = <&sata_phy>;
Hm, it's the third PHY related generic property I'm encountering. First,
there was "phy-handle", then "phy", now "phys"... Seems like a bit too much. :-)
> + phy-names = "sata-phy";
> + clocks = <&sata_ref_clk>;
> + clock-names = "optclk";
> + };
> + };
[1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf
On 09/19/2013 05:23 PM, Roger Quadros wrote:
> Add OCP2SCP1 module address space.
> CC: Benoit Cousson <[email protected]>
> Signed-off-by: Roger Quadros <[email protected]>
> ---
> arch/arm/boot/dts/omap5.dtsi | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index 06aa665..8a88a94 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -663,6 +663,7 @@
> #size-cells = <1>;
> ranges;
> ti,hwmods = "ocp2scp1";
> + reg = <0x4a080000 0x1f>;
Are you sure length is not 0x20?
WBR, Sergei
On 19.09.2013 15:05, Roger Quadros wrote:
> From: Kishon Vijay Abraham I <[email protected]>
>
> Rename struct omap_control_usb to struct omap_control_phy since it can
> be used to control PHY of USB, SATA and PCIE. Also move the driver and
> include files under *phy* and made the corresponding changes in the users
> of phy-omap-control.
>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> Signed-off-by: Roger Quadros <[email protected]>
> ---
> drivers/phy/Kconfig | 14 ++-
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-omap-control.c | 300 ++++++++++++++++++++++++++++++++++
> drivers/phy/phy-omap-pipe3.c | 8 +-
> drivers/phy/phy-omap-usb2.c | 9 +-
> drivers/usb/musb/omap2430.c | 2 +-
> drivers/usb/phy/Kconfig | 10 -
> drivers/usb/phy/Makefile | 1 -
> drivers/usb/phy/phy-omap-control.c | 300 ----------------------------------
> include/linux/phy/omap_control_phy.h | 83 ++++++++++
> include/linux/usb/omap_control_usb.h | 83 ----------
> 11 files changed, 406 insertions(+), 405 deletions(-)
> create mode 100644 drivers/phy/phy-omap-control.c
> delete mode 100644 drivers/usb/phy/phy-omap-control.c
> create mode 100644 include/linux/phy/omap_control_phy.h
> delete mode 100644 include/linux/usb/omap_control_usb.h
In case you do another version of this set, please use "git format-patch
-M", which will detect renames and hence make the review much easier.
Daniel
Hi,
On 09/19/2013 05:17 PM, Sergei Shtylyov wrote:
> On 09/19/2013 05:23 PM, Roger Quadros wrote:
>
>> Add OCP2SCP1 module address space.
>
>> CC: Benoit Cousson <[email protected]>
>> Signed-off-by: Roger Quadros <[email protected]>
>> ---
>> arch/arm/boot/dts/omap5.dtsi | 1 +
>> 1 files changed, 1 insertions(+), 0 deletions(-)
>
>> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
>> index 06aa665..8a88a94 100644
>> --- a/arch/arm/boot/dts/omap5.dtsi
>> +++ b/arch/arm/boot/dts/omap5.dtsi
>> @@ -663,6 +663,7 @@
>> #size-cells = <1>;
>> ranges;
>> ti,hwmods = "ocp2scp1";
>> + reg = <0x4a080000 0x1f>;
>
> Are you sure length is not 0x20?
Actually there are just 4 of 32-bit registers with the last one
starting at 0x18, so I think length should be 0x1c.
I copied 0x1f from omap4.dtsi. Looks like that is wrong as well.
But it is harmless as nobody else is using that address.
I'll fix this to 0x1c in next rev.
cheers,
-roger
Hi,
On 09/19/2013 05:11 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 09/19/2013 05:24 PM, Roger Quadros wrote:
>
>> From: Balaji T K <[email protected]>
>
>> Add support for sata controller.
>
>> [Roger Q] Clean up.
>
>> CC: Benoit Cousson <[email protected]>
>> Signed-off-by: Balaji T K <[email protected]>
>> Signed-off-by: Roger Quadros <[email protected]>
>> ---
>> arch/arm/boot/dts/dra7.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
>> 1 files changed, 49 insertions(+), 0 deletions(-)
>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index ce9a0f0..545545d 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -426,6 +426,55 @@
>> dma-names = "tx", "rx";
>> };
>>
>> + omap_control_sata: control-phy@4a002374 {
>> + compatible = "ti,control-phy-pipe3";
>> + reg = <0x4a002374 0x4>;
>> + reg-names = "power";
>> + clocks = <&sys_clkin1>;
>> + clock-names = "sysclk";
>> + };
>> +
>> + ocp2scp3: ocp2scp3@4a090000 {
>> + compatible = "ti,omap-ocp2scp";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + ti,hwmods = "ocp2scp3";
>> + reg = <0x4a090000 0x1f>; /* ocp2scp3 */
>> + reg-names = "ocp2scp3";
>> + sata_phy: sataphy@4A096000 {
>
> It's better to name the PHY nodes uniformly after already standard "ethernet-phy" and your "control-phy".
OK. will fix it to sata-phy.
>
>> + compatible = "ti,phy-pipe3-sata";
>> + reg = <0x4A096000 0x80>, /* phy_rx */
>> + <0x4A096400 0x64>, /* phy_tx */
>> + <0x4A096800 0x40>; /* pll_ctrl */
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + ctrl-module = <&omap_control_sata>;
>> + clocks = <&sata_ref_clk>,
>> + <&sys_clkin1>;
>> + clock-names = "optclk", "sysclk";
>> + #phy-cells = <0>;
>> + };
>> + };
>> +
>> + sata: sata@4a141100 {
>> + compatible = "ti,sata";
>> + ti,hwmods = "sata";
>> + reg = <0x4a141100 0x7>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + dwc-ahci@4a140000 {
>
> Hm, ePAPR spec. [1] says that "the name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model", so it looks like the name should be "sata" as well. I'm a bit at a loss here, not sure why you had to use the nested device nodes.
>
ok. will fix it to sata.
I've nested it because the wrapper registers are not part of the AHCI sata controller.
They are TI specific registers for power management.
Similar setup is on the USB controller. Please see omap_dwc3 node.
But if you have better idea, please let me know.
>> + compatible = "snps,dwc-ahci";
>> + reg = <0x4a140000 0x1100>;
>> + interrupts = <0 54 0x4>;
>> + phys = <&sata_phy>;
>
> Hm, it's the third PHY related generic property I'm encountering. First, there was "phy-handle", then "phy", now "phys"... Seems like a bit too much. :-)
I'm afraid but this is how the designers have made it.
1) control-phy-pipe3 is that part of the PHY which sits in control module space and is different
from the sata-phy space and hence needs a different node. If it were to me, I would just put this
resource in sata-phy node, but there was a discussion about this earlier to do it otherwise [1].
2) sata-phy (sataphy) is the actual SATA PHY device.
3) phys is just a reference to the sata_phy and is used via the generic PHY framework.
It is upto the sata driver to power up/down the phy.
>
>> + phy-names = "sata-phy";
>> + clocks = <&sata_ref_clk>;
>> + clock-names = "optclk";
>> + };
>> + };
>
> [1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf
>
cheers,
-roger
[1] - https://lkml.org/lkml/2012/9/10/399
On Thu, Sep 19, 2013 at 04:05:36PM +0300, Roger Quadros wrote:
> From: Balaji T K <[email protected]>
>
> Some platforms have a PHY hooked up to the
> SATA controller. The PHY needs to be initialized
> and powered up for SATA to work. We do that
> using the PHY framework.
>
> [Roger Q] Cleaned up.
>
> CC: Tejun Heo <[email protected]>
> Signed-off-by: Balaji T K <[email protected]>
> Signed-off-by: Roger Quadros <[email protected]>
Looks okay to me although I don't know whether everyone using
ahci_platform would be happy with requiring phy. Sergei, does this
look good to you?
Thanks.
--
tejun
Hello.
On 09/19/2013 05:05 PM, Roger Quadros wrote:
> From: Balaji T K <[email protected]>
> Some platforms have a PHY hooked up to the
> SATA controller. The PHY needs to be initialized
> and powered up for SATA to work. We do that
> using the PHY framework.
> [Roger Q] Cleaned up.
> CC: Tejun Heo <[email protected]>
> Signed-off-by: Balaji T K <[email protected]>
> Signed-off-by: Roger Quadros <[email protected]>
[...]
> diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
> index 1145637..94484cb 100644
> --- a/drivers/ata/ahci.h
> +++ b/drivers/ata/ahci.h
> @@ -37,6 +37,7 @@
>
> #include <linux/clk.h>
> #include <linux/libata.h>
> +#include <linux/phy/phy.h>
struct phy;
should suffice.
> @@ -322,6 +323,7 @@ struct ahci_host_priv {
> u32 em_buf_sz; /* EM buffer size in byte */
> u32 em_msg_type; /* EM message type */
> struct clk *clk; /* Only for platforms supporting clk */
> + struct phy *phy; /* If platforms use phy */
> void *plat_data; /* Other platform data */
> };
>
> diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
> index 2daaee0..f812ffa 100644
> --- a/drivers/ata/ahci_platform.c
> +++ b/drivers/ata/ahci_platform.c
> @@ -23,6 +23,7 @@
> #include <linux/platform_device.h>
> #include <linux/libata.h>
> #include <linux/ahci_platform.h>
> +#include <linux/phy/phy.h>
Why include it from both ahci.h and here?
> #include "ahci.h"
>
> static void ahci_host_stop(struct ata_host *host);
> @@ -141,16 +142,32 @@ static int ahci_probe(struct platform_device *pdev)
> }
> }
>
> + hpriv->phy = devm_phy_get(dev, "sata-phy");
> + if (IS_ERR(hpriv->phy)) {
> + dev_err(dev, "can't get phy\n");
Don't think it's a good idea to complain about missing PHY when the driver
doesn't even use it.
> + /* return only if -EPROBE_DEFER */
> + if (PTR_ERR(hpriv->phy) == -EPROBE_DEFER) {
> + rc = -EPROBE_DEFER;
> + goto disable_unprepare_clk;
> + }
> + }
> +
> /*
> * Some platforms might need to prepare for mmio region access,
> * which could be done in the following init call. So, the mmio
> * region shouldn't be accessed before init (if provided) has
> * returned successfully.
> */
> +
> + if (!(IS_ERR(hpriv->phy))) {
() not needed around IS_ERR() invocation.
> + phy_init(hpriv->phy);
> + phy_power_on(hpriv->phy);
> + }
> +
I think this is misplaced, i.e. it should precede the comment.
> if (pdata && pdata->init) {
> rc = pdata->init(dev, hpriv->mmio);
> if (rc)
> - goto disable_unprepare_clk;
> + goto disable_phy;
> }
>
> ahci_save_initial_config(dev, hpriv,
[...]
> @@ -328,6 +356,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
> static const struct of_device_id ahci_of_match[] = {
> { .compatible = "snps,spear-ahci", },
> { .compatible = "snps,exynos5440-ahci", },
> + { .compatible = "snps,dwc-ahci", },
Looks like the binding documentation is incomplete -- it doesn't list
"snps,exynos5440-ahci"...
WBR, Sergei
Hello.
On 09/22/2013 08:58 PM, Tejun Heo wrote:
>> From: Balaji T K <[email protected]>
>> Some platforms have a PHY hooked up to the
>> SATA controller. The PHY needs to be initialized
>> and powered up for SATA to work. We do that
>> using the PHY framework.
>> [Roger Q] Cleaned up.
>> CC: Tejun Heo <[email protected]>
>> Signed-off-by: Balaji T K <[email protected]>
>> Signed-off-by: Roger Quadros <[email protected]>
> Looks okay to me although I don't know whether everyone using
> ahci_platform would be happy with requiring phy. Sergei, does this
> look good to you?
Not sure why you asked -- I'm not using this driver, neither I'm the
author of it (former MV's Anton Vorontsov is IIRC). I've commented on the
patch anyway though...
> Thanks.
WBR, Sergei
On 09/20/2013 02:19 PM, Roger Quadros wrote:
>>> From: Balaji T K <[email protected]>
>>> Add support for sata controller.
>>> [Roger Q] Clean up.
>>> CC: Benoit Cousson <[email protected]>
>>> Signed-off-by: Balaji T K <[email protected]>
>>> Signed-off-by: Roger Quadros <[email protected]>
>>> ---
>>> arch/arm/boot/dts/dra7.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
>>> 1 files changed, 49 insertions(+), 0 deletions(-)
>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>>> index ce9a0f0..545545d 100644
>>> --- a/arch/arm/boot/dts/dra7.dtsi
>>> +++ b/arch/arm/boot/dts/dra7.dtsi
>>> @@ -426,6 +426,55 @@
[...]
>>> + sata: sata@4a141100 {
>>> + compatible = "ti,sata";
>>> + ti,hwmods = "sata";
>>> + reg = <0x4a141100 0x7>;
Not 0x8 BTW?
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
>>> + dwc-ahci@4a140000 {
>> Hm, ePAPR spec. [1] says that "the name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model", so it looks like the name should be "sata" as well. I'm a bit at a loss here, not sure why you had to use the nested device nodes.
> ok. will fix it to sata.
> I've nested it because the wrapper registers are not part of the AHCI sata controller.
> They are TI specific registers for power management.
> Similar setup is on the USB controller. Please see omap_dwc3 node.
> But if you have better idea, please let me know.
Don't know, it seems to me that you're over-complicating it by using the
nested nodes. You could just have AHCI regs as a first tuple of the "regs"
prop, and PM regs as a second tuple.
>>> + compatible = "snps,dwc-ahci";
>>> + reg = <0x4a140000 0x1100>;
>>> + interrupts = <0 54 0x4>;
>>> + phys = <&sata_phy>;
>> Hm, it's the third PHY related generic property I'm encountering. First, there was "phy-handle", then "phy", now "phys"... Seems like a bit too much. :-)
> I'm afraid but this is how the designers have made it.
> 1) control-phy-pipe3 is that part of the PHY which sits in control module space and is different
> from the sata-phy space and hence needs a different node. If it were to me, I would just put this
> resource in sata-phy node, but there was a discussion about this earlier to do it otherwise [1].
> 2) sata-phy (sataphy) is the actual SATA PHY device.
> 3) phys is just a reference to the sata_phy and is used via the generic PHY framework.
> It is upto the sata driver to power up/down the phy.
I understand that it's a reference but why have 3 variants of such phandle
containing prop? Is it really possible for a device to have multiple PHYs?
Well, remembering our customer's USB, it's indeed possible, however, there 2
PHYs out of 3 are not software controllable...
>>> + phy-names = "sata-phy";
>>> + clocks = <&sata_ref_clk>;
>>> + clock-names = "optclk";
>>> + };
>>> + };
>> [1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf
> cheers,
> -roger
> [1] - https://lkml.org/lkml/2012/9/10/399
WBR, Sergei
Hello,
On Sun, Sep 22, 2013 at 10:22:31PM +0400, Sergei Shtylyov wrote:
> >@@ -37,6 +37,7 @@
> >
> > #include <linux/clk.h>
> > #include <linux/libata.h>
> >+#include <linux/phy/phy.h>
>
> struct phy;
>
> should suffice.
Unless it's actually likely to cause inclusion loop, I think it's
better to include the header than adding explicit declarations.
Thanks.
--
tejun
Hello,
On Sun, Sep 22, 2013 at 10:24:36PM +0400, Sergei Shtylyov wrote:
> Not sure why you asked -- I'm not using this driver, neither I'm
Well, you have better grip of what's going on in the embedded world
than me. I'm mostly curious whether adding dependency on PHY is okay.
Thanks.
--
tejun
Hi Tejun,
On 09/23/2013 12:51 AM, Tejun Heo wrote:
> Hello,
>
> On Sun, Sep 22, 2013 at 10:24:36PM +0400, Sergei Shtylyov wrote:
>> Not sure why you asked -- I'm not using this driver, neither I'm
>
> Well, you have better grip of what's going on in the embedded world
> than me. I'm mostly curious whether adding dependency on PHY is okay.
>
There is no hard dependency on presence of PHY. The driver will continue
as usual if devm_phy_get() fails.
I hope selecting GENERIC_PHY in Kconfig is not an issue.
cheers,
-roger
Hi,
On 09/22/2013 09:22 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 09/19/2013 05:05 PM, Roger Quadros wrote:
>
>> From: Balaji T K <[email protected]>
>
>> Some platforms have a PHY hooked up to the
>> SATA controller. The PHY needs to be initialized
>> and powered up for SATA to work. We do that
>> using the PHY framework.
>
>> [Roger Q] Cleaned up.
>
>> CC: Tejun Heo <[email protected]>
>> Signed-off-by: Balaji T K <[email protected]>
>> Signed-off-by: Roger Quadros <[email protected]>
> [...]
>
>> diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
>> index 1145637..94484cb 100644
>> --- a/drivers/ata/ahci.h
>> +++ b/drivers/ata/ahci.h
>> @@ -37,6 +37,7 @@
>>
>> #include <linux/clk.h>
>> #include <linux/libata.h>
>> +#include <linux/phy/phy.h>
>
> struct phy;
>
> should suffice.
>
>> @@ -322,6 +323,7 @@ struct ahci_host_priv {
>> u32 em_buf_sz; /* EM buffer size in byte */
>> u32 em_msg_type; /* EM message type */
>> struct clk *clk; /* Only for platforms supporting clk */
>> + struct phy *phy; /* If platforms use phy */
>> void *plat_data; /* Other platform data */
>> };
>>
>> diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
>> index 2daaee0..f812ffa 100644
>> --- a/drivers/ata/ahci_platform.c
>> +++ b/drivers/ata/ahci_platform.c
>> @@ -23,6 +23,7 @@
>> #include <linux/platform_device.h>
>> #include <linux/libata.h>
>> #include <linux/ahci_platform.h>
>> +#include <linux/phy/phy.h>
>
> Why include it from both ahci.h and here?
>
OK. will move it to just .c file.
>> #include "ahci.h"
>>
>> static void ahci_host_stop(struct ata_host *host);
>> @@ -141,16 +142,32 @@ static int ahci_probe(struct platform_device *pdev)
>> }
>> }
>>
>> + hpriv->phy = devm_phy_get(dev, "sata-phy");
>> + if (IS_ERR(hpriv->phy)) {
>> + dev_err(dev, "can't get phy\n");
>
> Don't think it's a good idea to complain about missing PHY when the driver doesn't even use it.
OK. will change it to dev_dbg() instead.
>
>> + /* return only if -EPROBE_DEFER */
>> + if (PTR_ERR(hpriv->phy) == -EPROBE_DEFER) {
>> + rc = -EPROBE_DEFER;
>> + goto disable_unprepare_clk;
>> + }
>> + }
>> +
>> /*
>> * Some platforms might need to prepare for mmio region access,
>> * which could be done in the following init call. So, the mmio
>> * region shouldn't be accessed before init (if provided) has
>> * returned successfully.
>> */
>> +
>> + if (!(IS_ERR(hpriv->phy))) {
>
> () not needed around IS_ERR() invocation.
OK.
>
>> + phy_init(hpriv->phy);
>> + phy_power_on(hpriv->phy);
>> + }
>> +
>
> I think this is misplaced, i.e. it should precede the comment.
>
OK.
>> if (pdata && pdata->init) {
>> rc = pdata->init(dev, hpriv->mmio);
>> if (rc)
>> - goto disable_unprepare_clk;
>> + goto disable_phy;
>> }
>>
>> ahci_save_initial_config(dev, hpriv,
> [...]
>> @@ -328,6 +356,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
>> static const struct of_device_id ahci_of_match[] = {
>> { .compatible = "snps,spear-ahci", },
>> { .compatible = "snps,exynos5440-ahci", },
>> + { .compatible = "snps,dwc-ahci", },
>
> Looks like the binding documentation is incomplete -- it doesn't list "snps,exynos5440-ahci"...
OK, I'll update it. Thanks for review.
cheers,
-roger
On 09/22/2013 09:45 PM, Sergei Shtylyov wrote:
> On 09/20/2013 02:19 PM, Roger Quadros wrote:
>
>>>> From: Balaji T K <[email protected]>
>
>>>> Add support for sata controller.
>
>>>> [Roger Q] Clean up.
>
>>>> CC: Benoit Cousson <[email protected]>
>>>> Signed-off-by: Balaji T K <[email protected]>
>>>> Signed-off-by: Roger Quadros <[email protected]>
>>>> ---
>>>> arch/arm/boot/dts/dra7.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
>>>> 1 files changed, 49 insertions(+), 0 deletions(-)
>
>>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>>>> index ce9a0f0..545545d 100644
>>>> --- a/arch/arm/boot/dts/dra7.dtsi
>>>> +++ b/arch/arm/boot/dts/dra7.dtsi
>>>> @@ -426,6 +426,55 @@
> [...]
>
>>>> + sata: sata@4a141100 {
>>>> + compatible = "ti,sata";
>>>> + ti,hwmods = "sata";
>>>> + reg = <0x4a141100 0x7>;
>
> Not 0x8 BTW?
You are right. Two 32 bit registers are used.
However, in the instance summary, the reference manual says 256 bytes.
So I think we should use 0x100.
>
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges;
>>>> + dwc-ahci@4a140000 {
>
>>> Hm, ePAPR spec. [1] says that "the name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model", so it looks like the name should be "sata" as well. I'm a bit at a loss here, not sure why you had to use the nested device nodes.
>
>> ok. will fix it to sata.
>> I've nested it because the wrapper registers are not part of the AHCI sata controller.
>> They are TI specific registers for power management.
>> Similar setup is on the USB controller. Please see omap_dwc3 node.
>
>> But if you have better idea, please let me know.
>
> Don't know, it seems to me that you're over-complicating it by using the nested nodes. You could just have AHCI regs as a first tuple of the "regs" prop, and PM regs as a second tuple.
>
Yes that is possible, and in fact it was that way in Balaji's original code.
However in that case, won't TI specific handling be need to be done in the ahci_platform driver?
As of now, that is limited to using pm_runtime to enable/disable the hardware module so it is generic enough.
However in the future it would mean reading/writing to the TI wrapper register. If this can be done in ahci_platform
driver then I don't see any issue and can combine the 2 nodes.
>>>> + compatible = "snps,dwc-ahci";
>>>> + reg = <0x4a140000 0x1100>;
>>>> + interrupts = <0 54 0x4>;
>>>> + phys = <&sata_phy>;
>
>>> Hm, it's the third PHY related generic property I'm encountering. First, there was "phy-handle", then "phy", now "phys"... Seems like a bit too much. :-)
>
>> I'm afraid but this is how the designers have made it.
>
>> 1) control-phy-pipe3 is that part of the PHY which sits in control module space and is different
>> from the sata-phy space and hence needs a different node. If it were to me, I would just put this
>> resource in sata-phy node, but there was a discussion about this earlier to do it otherwise [1].
>
>> 2) sata-phy (sataphy) is the actual SATA PHY device.
>
>> 3) phys is just a reference to the sata_phy and is used via the generic PHY framework.
>> It is upto the sata driver to power up/down the phy.
>
> I understand that it's a reference but why have 3 variants of such phandle containing prop? Is it really possible for a device to have multiple PHYs? Well, remembering our customer's USB, it's indeed possible, however, there 2 PHYs out of 3 are not software controllable...
>
If I understand right, are you asking that we don't need "phy-names" property if there can be only one PHY?
I too think it is redundant. Maybe the PHY framework should be modified to allow users to use phy_get() whithout
any phy name string. In such case it should return the first PHY.
Kishon, any thoughts?
>>>> + phy-names = "sata-phy";
>>>> + clocks = <&sata_ref_clk>;
>>>> + clock-names = "optclk";
>>>> + };
>>>> + };
>
>>> [1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf
>
cheers,
-roger
Hello.
On 23-09-2013 1:51, Tejun Heo wrote:
>> Not sure why you asked -- I'm not using this driver, neither I'm
> Well, you have better grip of what's going on in the embedded world
> than me. I'm mostly curious whether adding dependency on PHY is okay.
This driver already supports optional clock, the optional PHY support
seems analogous.
> Thanks.
WBR, Sergei
Hello.
On 23-09-2013 11:37, Roger Quadros wrote:
>>> Not sure why you asked -- I'm not using this driver, neither I'm
>> Well, you have better grip of what's going on in the embedded world
>> than me. I'm mostly curious whether adding dependency on PHY is okay.
> There is no hard dependency on presence of PHY. The driver will continue
> as usual if devm_phy_get() fails.
> I hope selecting GENERIC_PHY in Kconfig is not an issue.
Selecting in the AHCI_PLATFORM section? It seems I have overlooked it. No,
I don't think it's a good idea. The generic PHY functions seem to be stubbed
when GENERIC_PHY=n.
> cheers,
> -roger
WBR, Sergei
On 09/23/2013 03:59 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 23-09-2013 11:37, Roger Quadros wrote:
>
>>>> Not sure why you asked -- I'm not using this driver, neither I'm
>
>>> Well, you have better grip of what's going on in the embedded world
>>> than me. I'm mostly curious whether adding dependency on PHY is okay.
>
>> There is no hard dependency on presence of PHY. The driver will continue
>> as usual if devm_phy_get() fails.
>> I hope selecting GENERIC_PHY in Kconfig is not an issue.
>
> Selecting in the AHCI_PLATFORM section? It seems I have overlooked it. No, I don't think it's a good idea. The generic PHY functions seem to be stubbed when GENERIC_PHY=n.
>
OK I will remove the select then.
cheers,
-roger
Hello.
On 09/23/2013 01:48 AM, Tejun Heo wrote:
>>> @@ -37,6 +37,7 @@
>>> #include <linux/clk.h>
>>> #include <linux/libata.h>
>>> +#include <linux/phy/phy.h>
>> struct phy;
>> should suffice.
> Unless it's actually likely to cause inclusion loop, I think it's
> better to include the header than adding explicit declarations.
Apparently, tastes differ here. E.g. Greg KH would have also told Roger to
use forward declaration in such case. :-)
> Thanks.
WBR, Sergei
On Mon, Sep 23, 2013 at 06:10:30PM +0400, Sergei Shtylyov wrote:
> >Unless it's actually likely to cause inclusion loop, I think it's
> >better to include the header than adding explicit declarations.
>
> Apparently, tastes differ here. E.g. Greg KH would have also told
> Roger to use forward declaration in such case. :-)
Yes, it's a matter of taste, but, of course mine is better than
Greg's. :P
--
tejun
Hi,
On Monday, September 23, 2013 04:53:52 PM Sergei Shtylyov wrote:
> Hello.
>
> On 23-09-2013 1:51, Tejun Heo wrote:
>
> >> Not sure why you asked -- I'm not using this driver, neither I'm
>
> > Well, you have better grip of what's going on in the embedded world
> > than me. I'm mostly curious whether adding dependency on PHY is okay.
>
> This driver already supports optional clock, the optional PHY support
> seems analogous.
Right, this reminds me that PHY support should probably also be added to
ahci_suspend() and ahci_resume().
Also please note the generic PHY framework is not yet merged in Linus'
tree so this patch should probably be merged only after the generic PHY
framework is in.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
Hi,
On Thursday, September 19, 2013 04:05:37 PM Roger Quadros wrote:
> Texas Instruments SoCs like OMAP5 and DRA7 contain a SATA wrapper
> around the AHCI SATA core. This driver will manage that.
>
> CC: Tejun Heo <[email protected]>
> Signed-off-by: Roger Quadros <[email protected]>
> ---
> Documentation/devicetree/bindings/ata/ti-sata.txt | 31 ++++
> drivers/ata/Kconfig | 7 +
> drivers/ata/Makefile | 1 +
> drivers/ata/sata_ti.c | 160 +++++++++++++++++++++
> 4 files changed, 199 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ata/ti-sata.txt
> create mode 100644 drivers/ata/sata_ti.c
>
> diff --git a/Documentation/devicetree/bindings/ata/ti-sata.txt b/Documentation/devicetree/bindings/ata/ti-sata.txt
> new file mode 100644
> index 0000000..bf0ea3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/ti-sata.txt
> @@ -0,0 +1,31 @@
> +* Texas Instruments SATA Controller Wrapper
> +
> +Required properties:
> +- compatible : "ti,sata"
> +- ti,hwmods : "sata"
> +- reg : Register mapping
> +- #address-cells: <1>
> +- #size-cells : <1>
> +- ranges : allows valid translation between child's address space and parent's
> + address space.
> +- Must contain at least one child node for the SATA controller core
> +
> +Example:
> +
> + sata: sata@4a141100 {
> + compatible = "ti,sata";
> + ti,hwmods = "sata";
> + reg = <0x4a141100 0x7>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + dwc-ahci@4a140000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0x4a140000 0x1100>;
> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&sata_phy>;
> + phy-names = "sata-phy";
> + clocks = <&sata_ref_clk>;
> + clock-names = "optclk";
> + };
> + };
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index a53ef27..a3de4d2 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -138,6 +138,13 @@ config SATA_SIL24
>
> If unsure, say N.
>
> +config SATA_TI
> + tristate "Texas Instruments SATA Wrapper driver"
> + depends on ARCH_OMAP
> + help
> + This options enables SATA Wrapper driver for Texas Instruments SoCs.
> + It is found on OMAP5 and DRA7.
> +
> config ATA_SFF
> bool "ATA SFF support (for legacy IDE and PATA)"
> default y
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 46518c6..673ba5e 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
> obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
> obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
> obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
> +obj-$(CONFIG_SATA_TI) += sata_ti.o
>
> # SFF w/ custom DMA
> obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
> diff --git a/drivers/ata/sata_ti.c b/drivers/ata/sata_ti.c
> new file mode 100644
> index 0000000..0b9093d
> --- /dev/null
> +++ b/drivers/ata/sata_ti.c
> @@ -0,0 +1,160 @@
> +/**
> + * sata-ti.c - Texas Instruments Specific SATA Glue layer
s/sata-ti/sata_ti/
> + *
> + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
> + *
> + * Authors: Roger Quadros <[email protected]>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/slab.h>
> +#include <linux/platform_device.h>
> +#include <linux/ioport.h>
> +#include <linux/io.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +
> +/*
> + * All these registers belong to OMAP's Wrapper around the
> + * DesignWare SATA Core.
> + */
> +
> +#define SATA_SYSCONFIG 0x0000
> +#define SATA_CDRLOCK 0x0004
These defines are not used anywhere.
> +struct ti_sata {
> + struct device *dev;
> + void __iomem *base;
> +};
> +
> +static int ti_sata_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct ti_sata *sata;
> + struct resource *res;
> + void __iomem *base;
> + int ret;
> +
> + if (!np) {
> + dev_err(dev, "device node not found\n");
> + return -EINVAL;
> + }
> +
> + sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
> + if (!sata)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, sata);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "missing memory base resource\n");
> + return -EINVAL;
> + }
> +
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + sata->dev = dev;
> + sata->base = base;
sata structure is just setup and it is not used later anywhere.
> + pm_runtime_enable(dev);
> + ret = pm_runtime_get_sync(dev);
> + if (ret < 0) {
> + dev_err(dev, "pm_runtime_get_sync failed with err %d\n",
> + ret);
> + goto runtime_disable;
> + }
> +
> + ret = of_platform_populate(np, NULL, NULL, dev);
Shouldn't this driver depend on CONFIG_OF?
> + if (ret) {
> + dev_err(&pdev->dev, "failed to create TI SATA children\n");
> + goto runtime_put;
> + }
> +
> + return 0;
> +
> +runtime_put:
> + pm_runtime_put_sync(dev);
> +
> +runtime_disable:
> + pm_runtime_disable(dev);
> +
> + return ret;
> +}
> +
> +static int ti_sata_remove_child(struct device *dev, void *c)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> +
> + platform_device_unregister(pdev);
> +
> + return 0;
> +}
> +
> +static int ti_sata_remove(struct platform_device *pdev)
> +{
> + pm_runtime_put_sync(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> + device_for_each_child(&pdev->dev, NULL, ti_sata_remove_child);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id of_ti_sata_match[] = {
> + {
> + .compatible = "ti,sata"
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, of_ti_sata_match);
> +
> +#ifdef CONFIG_PM
> +
> +static int ti_sata_resume(struct device *dev)
> +{
> + pm_runtime_disable(dev);
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
This doesn't look like a correct ->resume method:
* it shouldn't touch runtime PM at all
* for each ->resume method there should be a corresponding ->suspend method
Moreover this whole wrapper driver seems strange, why not just add a proper
runtime PM support to ahci_platform driver instead?
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops ti_sata_dev_pm_ops = {
> + .resume = ti_sata_resume,
> +};
> +
> +#define DEV_PM_OPS (&ti_sata_dev_pm_ops)
> +#else
> +#define DEV_PM_OPS NULL
> +#endif /* CONFIG_PM */
> +
> +static struct platform_driver ti_sata_driver = {
> + .probe = ti_sata_probe,
> + .remove = ti_sata_remove,
> + .driver = {
> + .name = "ti-sata",
> + .of_match_table = of_ti_sata_match,
> + .pm = DEV_PM_OPS,
> + },
> +};
> +
> +module_platform_driver(ti_sata_driver);
> +
> +MODULE_ALIAS("platform:ti-sata");
> +MODULE_AUTHOR("Roger Quadros <[email protected]>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("TI SATA Glue Layer");
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
On Wednesday, September 25, 2013 02:37:19 PM Bartlomiej Zolnierkiewicz wrote:
[...]
> > +#ifdef CONFIG_PM
> > +
> > +static int ti_sata_resume(struct device *dev)
> > +{
> > + pm_runtime_disable(dev);
> > + pm_runtime_set_active(dev);
> > + pm_runtime_enable(dev);
>
> This doesn't look like a correct ->resume method:
> * it shouldn't touch runtime PM at all
> * for each ->resume method there should be a corresponding ->suspend method
>
> Moreover this whole wrapper driver seems strange, why not just add a proper
> runtime PM support to ahci_platform driver instead?
Hmm, even this shouldn't be needed as this wrapper driver doesn't have
->runtime_suspend and ->runtime resume methods.
What exactly is the purpose of the existence of this wrapper driver?
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
Hi,
On 09/25/2013 03:49 PM, Bartlomiej Zolnierkiewicz wrote:
> On Wednesday, September 25, 2013 02:37:19 PM Bartlomiej Zolnierkiewicz wrote:
>
> [...]
>
>>> +#ifdef CONFIG_PM
>>> +
>>> +static int ti_sata_resume(struct device *dev)
>>> +{
>>> + pm_runtime_disable(dev);
>>> + pm_runtime_set_active(dev);
>>> + pm_runtime_enable(dev);
>>
>> This doesn't look like a correct ->resume method:
>> * it shouldn't touch runtime PM at all
>> * for each ->resume method there should be a corresponding ->suspend method
>>
>> Moreover this whole wrapper driver seems strange, why not just add a proper
>> runtime PM support to ahci_platform driver instead?
>
> Hmm, even this shouldn't be needed as this wrapper driver doesn't have
> ->runtime_suspend and ->runtime resume methods.
>
> What exactly is the purpose of the existence of this wrapper driver?
This is the weirdness of OMAP hwmod framework :).
The OMAP hwmod framework tries to manage the module clocks by itself and needs
a runtime_resume to enable the relevant clocks.
hwmod framework will be deprecated in the near future and this is the place where
we need to handle the resources.
But since we are not yet there, I can get rid of this wrapper driver for now
and add the necessary pm_runtime calls in the ahci_platform driver.
cheers,
-roger
Hi,
On 09/23/2013 04:59 PM, Roger Quadros wrote:
> On 09/23/2013 03:59 PM, Sergei Shtylyov wrote:
>> Hello.
>>
>> On 23-09-2013 11:37, Roger Quadros wrote:
>>
>>>>> Not sure why you asked -- I'm not using this driver, neither I'm
>>
>>>> Well, you have better grip of what's going on in the embedded world
>>>> than me. I'm mostly curious whether adding dependency on PHY is okay.
>>
>>> There is no hard dependency on presence of PHY. The driver will continue
>>> as usual if devm_phy_get() fails.
>>> I hope selecting GENERIC_PHY in Kconfig is not an issue.
>>
>> Selecting in the AHCI_PLATFORM section? It seems I have overlooked it. No, I don't think it's a good idea. The generic PHY functions seem to be stubbed when GENERIC_PHY=n.
>>
> OK I will remove the select then.
If I remove the select then build fails like so if we set CONFIG_GENERIC_PHY to 'm' and CONFIG_SATA_AHCI_PLATFORM to 'y'
drivers/built-in.o: In function `ahci_platform_enable_resources':
(.text+0x162647): undefined reference to `phy_init'
drivers/built-in.o: In function `ahci_platform_enable_resources':
(.text+0x16267c): undefined reference to `phy_power_on'
drivers/built-in.o: In function `ahci_platform_enable_resources':
(.text+0x162694): undefined reference to `phy_exit'
drivers/built-in.o: In function `ahci_platform_disable_resources':
(.text+0x1626af): undefined reference to `phy_power_off'
drivers/built-in.o: In function `ahci_platform_disable_resources':
(.text+0x1626b7): undefined reference to `phy_exit'
drivers/built-in.o: In function `ahci_platform_get_resources':
(.text+0x162768): undefined reference to `devm_phy_get'
make: *** [vmlinux] Error 1
This means we need to make CONFIG_SATA_AHCI_PLATFORM depend on CONFIG_GENERIC_PHY or
select it.
OR
Generic PHY layer must be fixed so that the API's are always built in.
What is the better option? I believe making the PHY API's always built in is the better option.
cheers,
-roger
On Friday 07 February 2014 12:33:38 Roger Quadros wrote:
>
> This means we need to make CONFIG_SATA_AHCI_PLATFORM depend on CONFIG_GENERIC_PHY or
> select it.
>
> OR
>
> Generic PHY layer must be fixed so that the API's are always built in.
>
> What is the better option? I believe making the PHY API's always built in is the better option.
>
CONFIG_SATA_AHCI_PLATFORM should do
"depends on CONFIG_GENERIC_PHY || !CONFIG_GENERIC_PHY"
which is the Kconfig way of saying that if CONFIG_GENERIC_PHY is a module,
CONFIG_SATA_AHCI_PLATFORM needs to be a module as well.
Arnd
On 02/07/2014 12:39 PM, Arnd Bergmann wrote:
> On Friday 07 February 2014 12:33:38 Roger Quadros wrote:
>>
>> This means we need to make CONFIG_SATA_AHCI_PLATFORM depend on CONFIG_GENERIC_PHY or
>> select it.
>>
>> OR
>>
>> Generic PHY layer must be fixed so that the API's are always built in.
>>
>> What is the better option? I believe making the PHY API's always built in is the better option.
>>
>
> CONFIG_SATA_AHCI_PLATFORM should do
>
> "depends on CONFIG_GENERIC_PHY || !CONFIG_GENERIC_PHY"
>
> which is the Kconfig way of saying that if CONFIG_GENERIC_PHY is a module,
> CONFIG_SATA_AHCI_PLATFORM needs to be a module as well.
>
Ah, that's neat. Thanks :).
cheers,
-roger