2022-08-29 06:47:21

by Zong Li

Subject: [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE

Since composible cache may be L3 cache if private L2 cache exists, we
should use its original name "composible cache" to prevent confusion.

This patchset contains the modification which is related to ccache, such
as DT binding and EDAC driver.

Greentime Hu (1):
soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

Zong Li (2):
dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache
EDAC/sifive: use sifive_ccache instead of sifive_l2

...ifive-l2-cache.yaml => sifive-ccache.yaml} | 6 +-
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 12 +-
drivers/soc/sifive/Kconfig | 7 +-
drivers/soc/sifive/Makefile | 2 +-
drivers/soc/sifive/sifive_ccache.c | 221 ++++++++++++++++
drivers/soc/sifive/sifive_l2_cache.c | 237 ------------------
include/soc/sifive/sifive_ccache.h | 16 ++
include/soc/sifive/sifive_l2_cache.h | 16 --
9 files changed, 253 insertions(+), 266 deletions(-)
rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
create mode 100644 drivers/soc/sifive/sifive_ccache.c
delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
create mode 100644 include/soc/sifive/sifive_ccache.h
delete mode 100644 include/soc/sifive/sifive_l2_cache.h

--
2.17.1

2022-08-29 06:48:22

by Zong Li

Subject: [PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2

The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
apply the change as well

Signed-off-by: Zong Li <[email protected]>
---
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 17562cf1fe97..456602d373b7 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC

config EDAC_SIFIVE
bool "Sifive platform EDAC driver"
- depends on EDAC=y && SIFIVE_L2
+ depends on EDAC=y && SIFIVE_CCACHE
help
Support for error detection and correction on the SiFive SoCs.

diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
index ee800aec7d47..b844e2626fd5 100644
--- a/drivers/edac/sifive_edac.c
+++ b/drivers/edac/sifive_edac.c
@@ -2,7 +2,7 @@
/*
* SiFive Platform EDAC Driver
*
- * Copyright (C) 2018-2019 SiFive, Inc.
+ * Copyright (C) 2018-2022 SiFive, Inc.
*
* This driver is partially based on octeon_edac-pc.c
*
@@ -10,7 +10,7 @@
#include <linux/edac.h>
#include <linux/platform_device.h>
#include "edac_module.h"
-#include <soc/sifive/sifive_l2_cache.h>
+#include <soc/sifive/sifive_ccache.h>

#define DRVNAME "sifive_edac"

@@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr)

p = container_of(this, struct sifive_edac_priv, notifier);

- if (event == SIFIVE_L2_ERR_TYPE_UE)
+ if (event == SIFIVE_CCACHE_ERR_TYPE_UE)
edac_device_handle_ue(p->dci, 0, 0, msg);
- else if (event == SIFIVE_L2_ERR_TYPE_CE)
+ else if (event == SIFIVE_CCACHE_ERR_TYPE_CE)
edac_device_handle_ce(p->dci, 0, 0, msg);

return NOTIFY_OK;
@@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev)
goto err;
}

- register_sifive_l2_error_notifier(&p->notifier);
+ register_sifive_ccache_error_notifier(&p->notifier);

return 0;

@@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev)
{
struct sifive_edac_priv *p = platform_get_drvdata(pdev);

- unregister_sifive_l2_error_notifier(&p->notifier);
+ unregister_sifive_ccache_error_notifier(&p->notifier);
edac_device_del_device(&pdev->dev);
edac_device_free_ctl_info(p->dci);

--
2.17.1

2022-08-29 06:53:58

by Zong Li

Subject: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

From: Greentime Hu <[email protected]>

Since composible cache may be L3 cache if pL2 cache exists, we should use
its original name composible cache to prevent confusion.

Signed-off-by: Greentime Hu <[email protected]>
Signed-off-by: Zong Li <[email protected]>
---
drivers/soc/sifive/Kconfig | 7 +-
drivers/soc/sifive/Makefile | 2 +-
drivers/soc/sifive/sifive_ccache.c | 221 +++++++++++++++++++++++++
drivers/soc/sifive/sifive_l2_cache.c | 237 ---------------------------
include/soc/sifive/sifive_ccache.h | 16 ++
include/soc/sifive/sifive_l2_cache.h | 16 --
6 files changed, 242 insertions(+), 257 deletions(-)
create mode 100644 drivers/soc/sifive/sifive_ccache.c
delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
create mode 100644 include/soc/sifive/sifive_ccache.h
delete mode 100644 include/soc/sifive/sifive_l2_cache.h

diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c40d08d..3d65d2771f9a 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -2,9 +2,10 @@

if SOC_SIFIVE

-config SIFIVE_L2
- bool "Sifive L2 Cache controller"
+config SIFIVE_CCACHE
+ bool "Sifive composable Cache controller"
+ default y
help
- Support for the L2 cache controller on SiFive platforms.
+ Support for the composable cache controller on SiFive platforms.

endif
diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
index b5caff77938f..1f5dc339bf82 100644
--- a/drivers/soc/sifive/Makefile
+++ b/drivers/soc/sifive/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0

-obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
new file mode 100644
index 000000000000..46ce33db7d30
--- /dev/null
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SiFive composable cache controller Driver
+ *
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ *
+ */
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/device.h>
+#include <asm/cacheinfo.h>
+#include <soc/sifive/sifive_ccache.h>
+
+#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
+#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
+#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
+
+#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
+#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
+#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
+
+#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
+#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
+#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
+
+#define SIFIVE_CCACHE_CONFIG 0x00
+#define SIFIVE_CCACHE_WAYENABLE 0x08
+#define SIFIVE_CCACHE_ECCINJECTERR 0x40
+
+#define SIFIVE_CCACHE_MAX_ECCINTR 3
+
+static void __iomem *ccache_base;
+static int level;
+static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
+static struct riscv_cacheinfo_ops ccache_cache_ops;
+
+enum {
+ DIR_CORR = 0,
+ DATA_CORR,
+ DATA_UNCORR,
+};
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *sifive_test;
+
+static ssize_t ccache_write(struct file *file, const char __user *data,
+ size_t count, loff_t *ppos)
+{
+ unsigned int val;
+
+ if (kstrtouint_from_user(data, count, 0, &val))
+ return -EINVAL;
+ if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
+ writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
+ else
+ return -EINVAL;
+ return count;
+}
+
+static const struct file_operations ccache_fops = {
+ .owner = THIS_MODULE,
+ .open = simple_open,
+ .write = ccache_write
+};
+
+static void setup_sifive_debug(void)
+{
+ sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL);
+
+ debugfs_create_file("sifive_debug_inject_error", 0200,
+ sifive_test, NULL, &ccache_fops);
+}
+#endif
+
+static void ccache_config_read(void)
+{
+ u32 regval, val;
+
+ regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
+ val = regval & 0xFF;
+ pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
+ val = (regval & 0xFF00) >> 8;
+ pr_info("CCACHE: No. of ways per bank: %d\n", val);
+ val = (regval & 0xFF0000) >> 16;
+ pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
+ val = (regval & 0xFF000000) >> 24;
+ pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
+
+ regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
+ pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
+}
+
+static const struct of_device_id sifive_ccache_ids[] = {
+ { .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "sifive,ccache0" },
+ { /* end of table */ },
+};
+
+static ATOMIC_NOTIFIER_HEAD(ccache_err_chain);
+
+int register_sifive_ccache_error_notifier(struct notifier_block *nb)
+{
+ return atomic_notifier_chain_register(&ccache_err_chain, nb);
+}
+EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier);
+
+int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
+{
+ return atomic_notifier_chain_unregister(&ccache_err_chain, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
+
+static int ccache_largest_wayenabled(void)
+{
+ return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
+}
+
+static ssize_t number_of_ways_enabled_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%u\n", ccache_largest_wayenabled());
+}
+
+static DEVICE_ATTR_RO(number_of_ways_enabled);
+
+static struct attribute *priv_attrs[] = {
+ &dev_attr_number_of_ways_enabled.attr,
+ NULL,
+};
+
+static const struct attribute_group priv_attr_group = {
+ .attrs = priv_attrs,
+};
+
+static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
+{
+ /* We want to use private group for composable cache only */
+ if (this_leaf->level == level)
+ return &priv_attr_group;
+ else
+ return NULL;
+}
+
+static irqreturn_t ccache_int_handler(int irq, void *device)
+{
+ unsigned int add_h, add_l;
+
+ if (irq == g_irq[DIR_CORR]) {
+ add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
+ add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
+ pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
+ /* Reading this register clears the DirError interrupt sig */
+ readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
+ atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
+ "DirECCFix");
+ }
+ if (irq == g_irq[DATA_CORR]) {
+ add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
+ add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
+ pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
+ /* Reading this register clears the DataError interrupt sig */
+ readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
+ atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
+ "DatECCFix");
+ }
+ if (irq == g_irq[DATA_UNCORR]) {
+ add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
+ add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
+ pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
+ /* Reading this register clears the DataFail interrupt sig */
+ readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
+ atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
+ "DatECCFail");
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int __init sifive_ccache_init(void)
+{
+ struct device_node *np;
+ struct resource res;
+ int i, rc;
+
+ np = of_find_matching_node(NULL, sifive_ccache_ids);
+ if (!np)
+ return -ENODEV;
+
+ if (of_address_to_resource(np, 0, &res))
+ return -ENODEV;
+
+ if (of_property_read_u32(np, "cache-level", &level))
+ return -ENODEV;
+
+ ccache_base = ioremap(res.start, resource_size(&res));
+ if (!ccache_base)
+ return -ENOMEM;
+
+ for (i = 0; i < SIFIVE_CCACHE_MAX_ECCINTR; i++) {
+ g_irq[i] = irq_of_parse_and_map(np, i);
+ rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
+ if (rc) {
+ pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
+ return rc;
+ }
+ }
+
+ ccache_config_read();
+
+ ccache_cache_ops.get_priv_group = ccache_get_priv_group;
+ riscv_set_cacheinfo_ops(&ccache_cache_ops);
+
+#ifdef CONFIG_DEBUG_FS
+ setup_sifive_debug();
+#endif
+ return 0;
+}
+device_initcall(sifive_ccache_init);
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
deleted file mode 100644
index 59640a1d0b28..000000000000
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ /dev/null
@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SiFive L2 cache controller Driver
- *
- * Copyright (C) 2018-2019 SiFive, Inc.
- *
- */
-#include <linux/debugfs.h>
-#include <linux/interrupt.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/device.h>
-#include <asm/cacheinfo.h>
-#include <soc/sifive/sifive_l2_cache.h>
-
-#define SIFIVE_L2_DIRECCFIX_LOW 0x100
-#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
-#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
-
-#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
-#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
-#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
-
-#define SIFIVE_L2_DATECCFIX_LOW 0x140
-#define SIFIVE_L2_DATECCFIX_HIGH 0x144
-#define SIFIVE_L2_DATECCFIX_COUNT 0x148
-
-#define SIFIVE_L2_DATECCFAIL_LOW 0x160
-#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
-#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
-
-#define SIFIVE_L2_CONFIG 0x00
-#define SIFIVE_L2_WAYENABLE 0x08
-#define SIFIVE_L2_ECCINJECTERR 0x40
-
-#define SIFIVE_L2_MAX_ECCINTR 4
-
-static void __iomem *l2_base;
-static int g_irq[SIFIVE_L2_MAX_ECCINTR];
-static struct riscv_cacheinfo_ops l2_cache_ops;
-
-enum {
- DIR_CORR = 0,
- DATA_CORR,
- DATA_UNCORR,
- DIR_UNCORR,
-};
-
-#ifdef CONFIG_DEBUG_FS
-static struct dentry *sifive_test;
-
-static ssize_t l2_write(struct file *file, const char __user *data,
- size_t count, loff_t *ppos)
-{
- unsigned int val;
-
- if (kstrtouint_from_user(data, count, 0, &val))
- return -EINVAL;
- if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
- writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
- else
- return -EINVAL;
- return count;
-}
-
-static const struct file_operations l2_fops = {
- .owner = THIS_MODULE,
- .open = simple_open,
- .write = l2_write
-};
-
-static void setup_sifive_debug(void)
-{
- sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
-
- debugfs_create_file("sifive_debug_inject_error", 0200,
- sifive_test, NULL, &l2_fops);
-}
-#endif
-
-static void l2_config_read(void)
-{
- u32 regval, val;
-
- regval = readl(l2_base + SIFIVE_L2_CONFIG);
- val = regval & 0xFF;
- pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
- val = (regval & 0xFF00) >> 8;
- pr_info("L2CACHE: No. of ways per bank: %d\n", val);
- val = (regval & 0xFF0000) >> 16;
- pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
- val = (regval & 0xFF000000) >> 24;
- pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
-
- regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
- pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
-}
-
-static const struct of_device_id sifive_l2_ids[] = {
- { .compatible = "sifive,fu540-c000-ccache" },
- { .compatible = "sifive,fu740-c000-ccache" },
- { /* end of table */ },
-};
-
-static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
-
-int register_sifive_l2_error_notifier(struct notifier_block *nb)
-{
- return atomic_notifier_chain_register(&l2_err_chain, nb);
-}
-EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
-
-int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
-{
- return atomic_notifier_chain_unregister(&l2_err_chain, nb);
-}
-EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
-
-static int l2_largest_wayenabled(void)
-{
- return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
-}
-
-static ssize_t number_of_ways_enabled_show(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return sprintf(buf, "%u\n", l2_largest_wayenabled());
-}
-
-static DEVICE_ATTR_RO(number_of_ways_enabled);
-
-static struct attribute *priv_attrs[] = {
- &dev_attr_number_of_ways_enabled.attr,
- NULL,
-};
-
-static const struct attribute_group priv_attr_group = {
- .attrs = priv_attrs,
-};
-
-static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
-{
- /* We want to use private group for L2 cache only */
- if (this_leaf->level == 2)
- return &priv_attr_group;
- else
- return NULL;
-}
-
-static irqreturn_t l2_int_handler(int irq, void *device)
-{
- unsigned int add_h, add_l;
-
- if (irq == g_irq[DIR_CORR]) {
- add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
- add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
- pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
- /* Reading this register clears the DirError interrupt sig */
- readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
- atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
- "DirECCFix");
- }
- if (irq == g_irq[DIR_UNCORR]) {
- add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
- add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
- /* Reading this register clears the DirFail interrupt sig */
- readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
- atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
- "DirECCFail");
- panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
- }
- if (irq == g_irq[DATA_CORR]) {
- add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
- add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
- pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
- /* Reading this register clears the DataError interrupt sig */
- readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
- atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
- "DatECCFix");
- }
- if (irq == g_irq[DATA_UNCORR]) {
- add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
- add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
- pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
- /* Reading this register clears the DataFail interrupt sig */
- readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
- atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
- "DatECCFail");
- }
-
- return IRQ_HANDLED;
-}
-
-static int __init sifive_l2_init(void)
-{
- struct device_node *np;
- struct resource res;
- int i, rc, intr_num;
-
- np = of_find_matching_node(NULL, sifive_l2_ids);
- if (!np)
- return -ENODEV;
-
- if (of_address_to_resource(np, 0, &res))
- return -ENODEV;
-
- l2_base = ioremap(res.start, resource_size(&res));
- if (!l2_base)
- return -ENOMEM;
-
- intr_num = of_property_count_u32_elems(np, "interrupts");
- if (!intr_num) {
- pr_err("L2CACHE: no interrupts property\n");
- return -ENODEV;
- }
-
- for (i = 0; i < intr_num; i++) {
- g_irq[i] = irq_of_parse_and_map(np, i);
- rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
- if (rc) {
- pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
- return rc;
- }
- }
-
- l2_config_read();
-
- l2_cache_ops.get_priv_group = l2_get_priv_group;
- riscv_set_cacheinfo_ops(&l2_cache_ops);
-
-#ifdef CONFIG_DEBUG_FS
- setup_sifive_debug();
-#endif
- return 0;
-}
-device_initcall(sifive_l2_init);
diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h
new file mode 100644
index 000000000000..16576d678ea8
--- /dev/null
+++ b/include/soc/sifive/sifive_ccache.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * SiFive composable Cache Controller header file
+ *
+ */
+
+#ifndef __SOC_SIFIVE_CCACHE_H
+#define __SOC_SIFIVE_CCACHE_H
+
+extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);
+extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
+
+#define SIFIVE_CCACHE_ERR_TYPE_CE 0
+#define SIFIVE_CCACHE_ERR_TYPE_UE 1
+
+#endif /* __SOC_SIFIVE_CCACHE_H */
diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h
deleted file mode 100644
index 92ade10ed67e..000000000000
--- a/include/soc/sifive/sifive_l2_cache.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * SiFive L2 Cache Controller header file
- *
- */
-
-#ifndef __SOC_SIFIVE_L2_CACHE_H
-#define __SOC_SIFIVE_L2_CACHE_H
-
-extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
-extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
-
-#define SIFIVE_L2_ERR_TYPE_CE 0
-#define SIFIVE_L2_ERR_TYPE_UE 1
-
-#endif /* __SOC_SIFIVE_L2_CACHE_H */
--
2.17.1

2022-08-29 07:35:36

by Conor Dooley

Subject: Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

Hey Zong,

On 29/08/2022 07:22, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Greentime Hu <[email protected]>
>
> Since composible cache may be L3 cache if pL2 cache exists, we should use
> its original name composible cache to prevent confusion.
>
> Signed-off-by: Greentime Hu <[email protected]>
> Signed-off-by: Zong Li <[email protected]>
> ---
> drivers/soc/sifive/Kconfig | 7 +-
> drivers/soc/sifive/Makefile | 2 +-
> drivers/soc/sifive/sifive_ccache.c | 221 +++++++++++++++++++++++++
> drivers/soc/sifive/sifive_l2_cache.c | 237 ---------------------------

Where did the 16 lines go? Could you please split renames off from any
other changes so that it is easier to see what has changed?

> include/soc/sifive/sifive_ccache.h | 16 ++
> include/soc/sifive/sifive_l2_cache.h | 16 --
> 6 files changed, 242 insertions(+), 257 deletions(-)
> create mode 100644 drivers/soc/sifive/sifive_ccache.c
> delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
> create mode 100644 include/soc/sifive/sifive_ccache.h
> delete mode 100644 include/soc/sifive/sifive_l2_cache.h
>
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index 58cf8c40d08d..3d65d2771f9a 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -2,9 +2,10 @@
>
> if SOC_SIFIVE
>
> -config SIFIVE_L2
> - bool "Sifive L2 Cache controller"
> +config SIFIVE_CCACHE
> + bool "Sifive composable Cache controller"
> + default y

Changing this to default on is not a rename of the file..
This should be in a different patch.

> help
> - Support for the L2 cache controller on SiFive platforms.
> + Support for the composable cache controller on SiFive platforms.
>
> endif
> diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
> index b5caff77938f..1f5dc339bf82 100644
> --- a/drivers/soc/sifive/Makefile
> +++ b/drivers/soc/sifive/Makefile
> @@ -1,3 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o
> +obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> new file mode 100644
> index 000000000000..46ce33db7d30
> --- /dev/null
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SiFive composable cache controller Driver
> + *
> + * Copyright (C) 2018-2019 SiFive, Inc.
> + *
> + */
> +#include <linux/debugfs.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/device.h>
> +#include <asm/cacheinfo.h>
> +#include <soc/sifive/sifive_ccache.h>
> +
> +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
> +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
> +
> +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
> +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
> +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
> +
> +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
> +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
> +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> +
> +#define SIFIVE_CCACHE_CONFIG 0x00
> +#define SIFIVE_CCACHE_WAYENABLE 0x08
> +#define SIFIVE_CCACHE_ECCINJECTERR 0x40

From what I can see, you've also changed these around too?
Please generate the patch's diff so that the rename is detected & the
diff shows only what changed in the file. The -M option is what you
are looking for.

I have a couple other comments to make about what's changed here other,
thatn the rename but I will do so against a v2 where the diff is usable.

Thanks,
Conor.

> +
> +#define SIFIVE_CCACHE_MAX_ECCINTR 3

2022-08-29 08:59:48

by Zong Li

Subject: Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

On Mon, Aug 29, 2022 at 3:05 PM <[email protected]> wrote:
>
> Hey Zong,
>
> On 29/08/2022 07:22, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Greentime Hu <[email protected]>
> >
> > Since composible cache may be L3 cache if pL2 cache exists, we should use
> > its original name composible cache to prevent confusion.
> >
> > Signed-off-by: Greentime Hu <[email protected]>
> > Signed-off-by: Zong Li <[email protected]>
> > ---
> > drivers/soc/sifive/Kconfig | 7 +-
> > drivers/soc/sifive/Makefile | 2 +-
> > drivers/soc/sifive/sifive_ccache.c | 221 +++++++++++++++++++++++++
> > drivers/soc/sifive/sifive_l2_cache.c | 237 ---------------------------
>
> Where did the 16 lines go? Could you please split renames off from any
> other changes so that it is easier to see what has changed?

As your suggestion, we should separate the difference from this patch

>
> > include/soc/sifive/sifive_ccache.h | 16 ++
> > include/soc/sifive/sifive_l2_cache.h | 16 --
> > 6 files changed, 242 insertions(+), 257 deletions(-)
> > create mode 100644 drivers/soc/sifive/sifive_ccache.c
> > delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
> > create mode 100644 include/soc/sifive/sifive_ccache.h
> > delete mode 100644 include/soc/sifive/sifive_l2_cache.h
> >
> > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> > index 58cf8c40d08d..3d65d2771f9a 100644
> > --- a/drivers/soc/sifive/Kconfig
> > +++ b/drivers/soc/sifive/Kconfig
> > @@ -2,9 +2,10 @@
> >
> > if SOC_SIFIVE
> >
> > -config SIFIVE_L2
> > - bool "Sifive L2 Cache controller"
> > +config SIFIVE_CCACHE
> > + bool "Sifive composable Cache controller"
> > + default y
>
> Changing this to default on is not a rename of the file..
> This should be in a different patch.

Okay, let me separate it to another patch, but I guess we could remove
it, and enable it by user. What is your perspective on it?

>
> > help
> > - Support for the L2 cache controller on SiFive platforms.
> > + Support for the composable cache controller on SiFive platforms.
> >
> > endif
> > diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
> > index b5caff77938f..1f5dc339bf82 100644
> > --- a/drivers/soc/sifive/Makefile
> > +++ b/drivers/soc/sifive/Makefile
> > @@ -1,3 +1,3 @@
> > # SPDX-License-Identifier: GPL-2.0
> >
> > -obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o
> > +obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > new file mode 100644
> > index 000000000000..46ce33db7d30
> > --- /dev/null
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -0,0 +1,221 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * SiFive composable cache controller Driver
> > + *
> > + * Copyright (C) 2018-2019 SiFive, Inc.
> > + *
> > + */
> > +#include <linux/debugfs.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_address.h>
> > +#include <linux/device.h>
> > +#include <asm/cacheinfo.h>
> > +#include <soc/sifive/sifive_ccache.h>
> > +
> > +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> > +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
> > +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
> > +
> > +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
> > +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
> > +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
> > +
> > +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
> > +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
> > +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> > +
> > +#define SIFIVE_CCACHE_CONFIG 0x00
> > +#define SIFIVE_CCACHE_WAYENABLE 0x08
> > +#define SIFIVE_CCACHE_ECCINJECTERR 0x40
>
> From what I can see, you've also changed these around too?
> Please generate the patch's diff so that the rename is detected & the
> diff shows only what changed in the file. The -M option is what you
> are looking for.
>
> I have a couple other comments to make about what's changed here other,
> thatn the rename but I will do so against a v2 where the diff is usable.
>

Let me sent the v2 patch, and separate the rename and diff part

> Thanks,
> Conor.
>
> > +
> > +#define SIFIVE_CCACHE_MAX_ECCINTR 3

2022-08-30 08:51:06

by Ben Dooks

Subject: [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

With newer cores such as the p550, the SiFive composable cache can be
a level 3 cache. Update the cache level to be one of 2 or 3.

Signed-off-by: Ben Dooks <[email protected]>
---
Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 1a64a5384e36..6190deb65455 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -45,7 +45,7 @@ properties:
const: 64

cache-level:
- const: 2
+ enum: [2, 3]

cache-sets:
enum: [1024, 2048]
--
2.35.1

2022-08-30 09:03:51

by Ben Dooks

Subject: [PATCH] soc: sifive: ccache: reduce printing on init

The driver prints out 6 lines on startup, which can easily be redcued
to two lines without losing any information.

Note, to make the types work better, uint64_t has been replaced with
ULL to make the unsigned long long match the format in the print
statement.

Signed-off-by: Ben Dooks <[email protected]>
---
drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 46ce33db7d30..65a10a6ee211 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -76,20 +76,17 @@ static void setup_sifive_debug(void)

static void ccache_config_read(void)
{
- u32 regval, val;
-
- regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
- val = regval & 0xFF;
- pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
- val = (regval & 0xFF00) >> 8;
- pr_info("CCACHE: No. of ways per bank: %d\n", val);
- val = (regval & 0xFF0000) >> 16;
- pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
- val = (regval & 0xFF000000) >> 24;
- pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
-
- regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
- pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
+ u32 cfg;
+
+ cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
+
+ pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
+ (cfg & 0xff), (cfg >> 8) & 0xff,
+ 1ULL << ((cfg >> 16) & 0xff),
+ 1ULL << ((cfg >> 24) & 0xff));
+
+ cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
+ pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
}

static const struct of_device_id sifive_ccache_ids[] = {
--
2.35.1

2022-08-30 09:30:30

by Ben Dooks

Subject: Re: [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE

On 29/08/2022 07:21, Zong Li wrote:
> Since composible cache may be L3 cache if private L2 cache exists, we
> should use its original name "composible cache" to prevent confusion.
>
> This patchset contains the modification which is related to ccache, such
> as DT binding and EDAC driver.
>
> Greentime Hu (1):
> soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.
>
> Zong Li (2):
> dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache
> EDAC/sifive: use sifive_ccache instead of sifive_l2
>
> ...ifive-l2-cache.yaml => sifive-ccache.yaml} | 6 +-
> drivers/edac/Kconfig | 2 +-
> drivers/edac/sifive_edac.c | 12 +-
> drivers/soc/sifive/Kconfig | 7 +-
> drivers/soc/sifive/Makefile | 2 +-
> drivers/soc/sifive/sifive_ccache.c | 221 ++++++++++++++++
> drivers/soc/sifive/sifive_l2_cache.c | 237 ------------------
> include/soc/sifive/sifive_ccache.h | 16 ++
> include/soc/sifive/sifive_l2_cache.h | 16 --
> 9 files changed, 253 insertions(+), 266 deletions(-)
> rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> create mode 100644 drivers/soc/sifive/sifive_ccache.c
> delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
> create mode 100644 include/soc/sifive/sifive_ccache.h
> delete mode 100644 include/soc/sifive/sifive_l2_cache.h

Is this series available on a git branch anywhere, I have at least
one other cleanup I was doing in a similar move to rename and make
it usable as the l3 cache.

I gave the series a quick review and did not find any issues so far.

--
Ben

2022-08-30 09:34:00

by Conor Dooley

Subject: Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

On 29/08/2022 09:40, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, Aug 29, 2022 at 3:05 PM <[email protected]> wrote:
>>
>> Hey Zong,
>>
>> On 29/08/2022 07:22, Zong Li wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Greentime Hu <[email protected]>
>>>
>>> Since composible cache may be L3 cache if pL2 cache exists, we should use
>>> its original name composible cache to prevent confusion.
>>>
>>> Signed-off-by: Greentime Hu <[email protected]>
>>> Signed-off-by: Zong Li <[email protected]>

>>>
>>> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
>>> index 58cf8c40d08d..3d65d2771f9a 100644
>>> --- a/drivers/soc/sifive/Kconfig
>>> +++ b/drivers/soc/sifive/Kconfig
>>> @@ -2,9 +2,10 @@
>>>
>>> if SOC_SIFIVE
>>>
>>> -config SIFIVE_L2
>>> - bool "Sifive L2 Cache controller"
>>> +config SIFIVE_CCACHE
>>> + bool "Sifive composable Cache controller"
>>> + default y
>>
>> Changing this to default on is not a rename of the file..
>> This should be in a different patch.
>
> Okay, let me separate it to another patch, but I guess we could remove
> it, and enable it by user. What is your perspective on it?

Personally I would like to leave the default y out & leave it up
to the user - the driver is more informational than anything else
so I don't think making it default to on makes sense.



>>> +
>>> +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
>>> +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
>>> +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
>>> +
>>> +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
>>> +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
>>> +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
>>> +
>>> +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
>>> +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
>>> +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
>>> +
>>> +#define SIFIVE_CCACHE_CONFIG 0x00
>>> +#define SIFIVE_CCACHE_WAYENABLE 0x08
>>> +#define SIFIVE_CCACHE_ECCINJECTERR 0x40
>>
>> From what I can see, you've also changed these around too?
>> Please generate the patch's diff so that the rename is detected & the
>> diff shows only what changed in the file. The -M option is what you
>> are looking for.
>>
>> I have a couple other comments to make about what's changed here other,
>> thatn the rename but I will do so against a v2 where the diff is usable.
>>
>
> Let me sent the v2 patch, and separate the rename and diff part

Great, thanks. I'll take another look at it then.

Conor.

2022-08-30 09:57:28

by Ben Dooks

Subject: Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

On 29/08/2022 07:22, Zong Li wrote:
> From: Greentime Hu <[email protected]>
>
> Since composible cache may be L3 cache if pL2 cache exists, we should use
> its original name composible cache to prevent confusion.

You probably should have noted in this that you also read the cache
level property to work out if this is an l2 or l3 cache.

>
> Signed-off-by: Greentime Hu <[email protected]>
> Signed-off-by: Zong Li <[email protected]>
> ---
> drivers/soc/sifive/Kconfig | 7 +-
> drivers/soc/sifive/Makefile | 2 +-
> drivers/soc/sifive/sifive_ccache.c | 221 +++++++++++++++++++++++++
> drivers/soc/sifive/sifive_l2_cache.c | 237 ---------------------------
> include/soc/sifive/sifive_ccache.h | 16 ++
> include/soc/sifive/sifive_l2_cache.h | 16 --
> 6 files changed, 242 insertions(+), 257 deletions(-)
> create mode 100644 drivers/soc/sifive/sifive_ccache.c
> delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
> create mode 100644 include/soc/sifive/sifive_ccache.h
> delete mode 100644 include/soc/sifive/sifive_l2_cache.h
>
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index 58cf8c40d08d..3d65d2771f9a 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -2,9 +2,10 @@
>
> if SOC_SIFIVE
>
> -config SIFIVE_L2
> - bool "Sifive L2 Cache controller"
> +config SIFIVE_CCACHE
> + bool "Sifive composable Cache controller"
> + default y
> help
> - Support for the L2 cache controller on SiFive platforms.
> + Support for the composable cache controller on SiFive platforms.
>
> endif
> diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
> index b5caff77938f..1f5dc339bf82 100644
> --- a/drivers/soc/sifive/Makefile
> +++ b/drivers/soc/sifive/Makefile
> @@ -1,3 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o
> +obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> new file mode 100644
> index 000000000000..46ce33db7d30
> --- /dev/null
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SiFive composable cache controller Driver
> + *
> + * Copyright (C) 2018-2019 SiFive, Inc.
> + *
> + */
> +#include <linux/debugfs.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/device.h>
> +#include <asm/cacheinfo.h>
> +#include <soc/sifive/sifive_ccache.h>
> +
> +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
> +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
> +
> +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
> +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
> +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
> +
> +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
> +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
> +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> +
> +#define SIFIVE_CCACHE_CONFIG 0x00
> +#define SIFIVE_CCACHE_WAYENABLE 0x08
> +#define SIFIVE_CCACHE_ECCINJECTERR 0x40
> +
> +#define SIFIVE_CCACHE_MAX_ECCINTR 3
> +
> +static void __iomem *ccache_base;
> +static int level;
> +static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> +static struct riscv_cacheinfo_ops ccache_cache_ops;
> +
> +enum {
> + DIR_CORR = 0,
> + DATA_CORR,
> + DATA_UNCORR,
> +};
> +
> +#ifdef CONFIG_DEBUG_FS
> +static struct dentry *sifive_test;
> +
> +static ssize_t ccache_write(struct file *file, const char __user *data,
> + size_t count, loff_t *ppos)
> +{
> + unsigned int val;
> +
> + if (kstrtouint_from_user(data, count, 0, &val))
> + return -EINVAL;
> + if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> + writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
> + else
> + return -EINVAL;
> + return count;
> +}
> +
> +static const struct file_operations ccache_fops = {
> + .owner = THIS_MODULE,
> + .open = simple_open,
> + .write = ccache_write
> +};
> +
> +static void setup_sifive_debug(void)
> +{
> + sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL);
> +
> + debugfs_create_file("sifive_debug_inject_error", 0200,
> + sifive_test, NULL, &ccache_fops);
> +}
> +#endif
> +
> +static void ccache_config_read(void)
> +{
> + u32 regval, val;
> +
> + regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> + val = regval & 0xFF;
> + pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> + val = (regval & 0xFF00) >> 8;
> + pr_info("CCACHE: No. of ways per bank: %d\n", val);
> + val = (regval & 0xFF0000) >> 16;
> + pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> + val = (regval & 0xFF000000) >> 24;
> + pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> +
> + regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> + pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> +}
> +
> +static const struct of_device_id sifive_ccache_ids[] = {
> + { .compatible = "sifive,fu540-c000-ccache" },
> + { .compatible = "sifive,ccache0" },
> + { /* end of table */ },
> +};
> +
> +static ATOMIC_NOTIFIER_HEAD(ccache_err_chain);
> +
> +int register_sifive_ccache_error_notifier(struct notifier_block *nb)
> +{
> + return atomic_notifier_chain_register(&ccache_err_chain, nb);
> +}
> +EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier);
> +
> +int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
> +{
> + return atomic_notifier_chain_unregister(&ccache_err_chain, nb);
> +}
> +EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
> +
> +static int ccache_largest_wayenabled(void)
> +{
> + return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
> +}
> +
> +static ssize_t number_of_ways_enabled_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + return sprintf(buf, "%u\n", ccache_largest_wayenabled());
> +}
> +
> +static DEVICE_ATTR_RO(number_of_ways_enabled);
> +
> +static struct attribute *priv_attrs[] = {
> + &dev_attr_number_of_ways_enabled.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group priv_attr_group = {
> + .attrs = priv_attrs,
> +};
> +
> +static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
> +{
> + /* We want to use private group for composable cache only */
> + if (this_leaf->level == level)
> + return &priv_attr_group;
> + else
> + return NULL;
> +}
> +
> +static irqreturn_t ccache_int_handler(int irq, void *device)
> +{
> + unsigned int add_h, add_l;
> +
> + if (irq == g_irq[DIR_CORR]) {
> + add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
> + add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
> + pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
> + /* Reading this register clears the DirError interrupt sig */
> + readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
> + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> + "DirECCFix");
> + }
> + if (irq == g_irq[DATA_CORR]) {
> + add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
> + add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
> + pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
> + /* Reading this register clears the DataError interrupt sig */
> + readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
> + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> + "DatECCFix");
> + }
> + if (irq == g_irq[DATA_UNCORR]) {
> + add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
> + add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
> + pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
> + /* Reading this register clears the DataFail interrupt sig */
> + readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
> + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
> + "DatECCFail");
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int __init sifive_ccache_init(void)
> +{
> + struct device_node *np;
> + struct resource res;
> + int i, rc;
> +
> + np = of_find_matching_node(NULL, sifive_ccache_ids);
> + if (!np)
> + return -ENODEV;
> +
> + if (of_address_to_resource(np, 0, &res))
> + return -ENODEV;
> +
> + if (of_property_read_u32(np, "cache-level", &level))
> + return -ENODEV;
> +
> + ccache_base = ioremap(res.start, resource_size(&res));
> + if (!ccache_base)
> + return -ENOMEM;
> +
> + for (i = 0; i < SIFIVE_CCACHE_MAX_ECCINTR; i++) {
> + g_irq[i] = irq_of_parse_and_map(np, i);
> + rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
> + if (rc) {
> + pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
> + return rc;
> + }
> + }
> +
> + ccache_config_read();
> +
> + ccache_cache_ops.get_priv_group = ccache_get_priv_group;
> + riscv_set_cacheinfo_ops(&ccache_cache_ops);
> +
> +#ifdef CONFIG_DEBUG_FS
> + setup_sifive_debug();
> +#endif
> + return 0;
> +}
> +device_initcall(sifive_ccache_init);
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> deleted file mode 100644
> index 59640a1d0b28..000000000000
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ /dev/null
> @@ -1,237 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * SiFive L2 cache controller Driver
> - *
> - * Copyright (C) 2018-2019 SiFive, Inc.
> - *
> - */
> -#include <linux/debugfs.h>
> -#include <linux/interrupt.h>
> -#include <linux/of_irq.h>
> -#include <linux/of_address.h>
> -#include <linux/device.h>
> -#include <asm/cacheinfo.h>
> -#include <soc/sifive/sifive_l2_cache.h>
> -
> -#define SIFIVE_L2_DIRECCFIX_LOW 0x100
> -#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
> -#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
> -
> -#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
> -#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
> -#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
> -
> -#define SIFIVE_L2_DATECCFIX_LOW 0x140
> -#define SIFIVE_L2_DATECCFIX_HIGH 0x144
> -#define SIFIVE_L2_DATECCFIX_COUNT 0x148
> -
> -#define SIFIVE_L2_DATECCFAIL_LOW 0x160
> -#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
> -#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
> -
> -#define SIFIVE_L2_CONFIG 0x00
> -#define SIFIVE_L2_WAYENABLE 0x08
> -#define SIFIVE_L2_ECCINJECTERR 0x40
> -
> -#define SIFIVE_L2_MAX_ECCINTR 4
> -
> -static void __iomem *l2_base;
> -static int g_irq[SIFIVE_L2_MAX_ECCINTR];
> -static struct riscv_cacheinfo_ops l2_cache_ops;
> -
> -enum {
> - DIR_CORR = 0,
> - DATA_CORR,
> - DATA_UNCORR,
> - DIR_UNCORR,
> -};
> -
> -#ifdef CONFIG_DEBUG_FS
> -static struct dentry *sifive_test;
> -
> -static ssize_t l2_write(struct file *file, const char __user *data,
> - size_t count, loff_t *ppos)
> -{
> - unsigned int val;
> -
> - if (kstrtouint_from_user(data, count, 0, &val))
> - return -EINVAL;
> - if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> - writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
> - else
> - return -EINVAL;
> - return count;
> -}
> -
> -static const struct file_operations l2_fops = {
> - .owner = THIS_MODULE,
> - .open = simple_open,
> - .write = l2_write
> -};
> -
> -static void setup_sifive_debug(void)
> -{
> - sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
> -
> - debugfs_create_file("sifive_debug_inject_error", 0200,
> - sifive_test, NULL, &l2_fops);
> -}
> -#endif
> -
> -static void l2_config_read(void)
> -{
> - u32 regval, val;
> -
> - regval = readl(l2_base + SIFIVE_L2_CONFIG);
> - val = regval & 0xFF;
> - pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
> - val = (regval & 0xFF00) >> 8;
> - pr_info("L2CACHE: No. of ways per bank: %d\n", val);
> - val = (regval & 0xFF0000) >> 16;
> - pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> - val = (regval & 0xFF000000) >> 24;
> - pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> -
> - regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
> - pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> -}
> -
> -static const struct of_device_id sifive_l2_ids[] = {
> - { .compatible = "sifive,fu540-c000-ccache" },
> - { .compatible = "sifive,fu740-c000-ccache" },
> - { /* end of table */ },
> -};
> -
> -static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
> -
> -int register_sifive_l2_error_notifier(struct notifier_block *nb)
> -{
> - return atomic_notifier_chain_register(&l2_err_chain, nb);
> -}
> -EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
> -
> -int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
> -{
> - return atomic_notifier_chain_unregister(&l2_err_chain, nb);
> -}
> -EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
> -
> -static int l2_largest_wayenabled(void)
> -{
> - return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
> -}
> -
> -static ssize_t number_of_ways_enabled_show(struct device *dev,
> - struct device_attribute *attr,
> - char *buf)
> -{
> - return sprintf(buf, "%u\n", l2_largest_wayenabled());
> -}
> -
> -static DEVICE_ATTR_RO(number_of_ways_enabled);
> -
> -static struct attribute *priv_attrs[] = {
> - &dev_attr_number_of_ways_enabled.attr,
> - NULL,
> -};
> -
> -static const struct attribute_group priv_attr_group = {
> - .attrs = priv_attrs,
> -};
> -
> -static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
> -{
> - /* We want to use private group for L2 cache only */
> - if (this_leaf->level == 2)
> - return &priv_attr_group;
> - else
> - return NULL;
> -}
> -
> -static irqreturn_t l2_int_handler(int irq, void *device)
> -{
> - unsigned int add_h, add_l;
> -
> - if (irq == g_irq[DIR_CORR]) {
> - add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
> - add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
> - pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
> - /* Reading this register clears the DirError interrupt sig */
> - readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
> - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
> - "DirECCFix");
> - }
> - if (irq == g_irq[DIR_UNCORR]) {
> - add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
> - add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
> - /* Reading this register clears the DirFail interrupt sig */
> - readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
> - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
> - "DirECCFail");
> - panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
> - }
> - if (irq == g_irq[DATA_CORR]) {
> - add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
> - add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
> - pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
> - /* Reading this register clears the DataError interrupt sig */
> - readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
> - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
> - "DatECCFix");
> - }
> - if (irq == g_irq[DATA_UNCORR]) {
> - add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
> - add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
> - pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
> - /* Reading this register clears the DataFail interrupt sig */
> - readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
> - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
> - "DatECCFail");
> - }
> -
> - return IRQ_HANDLED;
> -}
> -
> -static int __init sifive_l2_init(void)
> -{
> - struct device_node *np;
> - struct resource res;
> - int i, rc, intr_num;
> -
> - np = of_find_matching_node(NULL, sifive_l2_ids);
> - if (!np)
> - return -ENODEV;
> -
> - if (of_address_to_resource(np, 0, &res))
> - return -ENODEV;
> -
> - l2_base = ioremap(res.start, resource_size(&res));
> - if (!l2_base)
> - return -ENOMEM;
> -
> - intr_num = of_property_count_u32_elems(np, "interrupts");
> - if (!intr_num) {
> - pr_err("L2CACHE: no interrupts property\n");
> - return -ENODEV;
> - }
> -
> - for (i = 0; i < intr_num; i++) {
> - g_irq[i] = irq_of_parse_and_map(np, i);
> - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> - if (rc) {
> - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> - return rc;
> - }
> - }
> -
> - l2_config_read();
> -
> - l2_cache_ops.get_priv_group = l2_get_priv_group;
> - riscv_set_cacheinfo_ops(&l2_cache_ops);
> -
> -#ifdef CONFIG_DEBUG_FS
> - setup_sifive_debug();
> -#endif
> - return 0;
> -}
> -device_initcall(sifive_l2_init);
> diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h
> new file mode 100644
> index 000000000000..16576d678ea8
> --- /dev/null
> +++ b/include/soc/sifive/sifive_ccache.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * SiFive composable Cache Controller header file
> + *
> + */
> +
> +#ifndef __SOC_SIFIVE_CCACHE_H
> +#define __SOC_SIFIVE_CCACHE_H
> +
> +extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);
> +extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
> +
> +#define SIFIVE_CCACHE_ERR_TYPE_CE 0
> +#define SIFIVE_CCACHE_ERR_TYPE_UE 1
> +
> +#endif /* __SOC_SIFIVE_CCACHE_H */
> diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h
> deleted file mode 100644
> index 92ade10ed67e..000000000000
> --- a/include/soc/sifive/sifive_l2_cache.h
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * SiFive L2 Cache Controller header file
> - *
> - */
> -
> -#ifndef __SOC_SIFIVE_L2_CACHE_H
> -#define __SOC_SIFIVE_L2_CACHE_H
> -
> -extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
> -extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
> -
> -#define SIFIVE_L2_ERR_TYPE_CE 0
> -#define SIFIVE_L2_ERR_TYPE_UE 1
> -
> -#endif /* __SOC_SIFIVE_L2_CACHE_H */

--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

2022-08-30 13:07:16

by Rob Herring

Subject: Re: [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

On Tue, Aug 30, 2022 at 3:36 AM Ben Dooks <[email protected]> wrote:
>
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
>
> Signed-off-by: Ben Dooks <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

Please send DT patches to the DT list. Resend so checks run.

Rob

2022-08-30 13:38:54

by Ben Dooks

Subject: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

With newer cores such as the p550, the SiFive composable cache can be
a level 3 cache. Update the cache level to be one of 2 or 3.

Signed-off-by: Ben Dooks <[email protected]>
---
Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 1a64a5384e36..6190deb65455 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -45,7 +45,7 @@ properties:
const: 64

cache-level:
- const: 2
+ enum: [2, 3]

cache-sets:
enum: [1024, 2048]
--
2.35.1

2022-08-30 17:05:56

by Ben Dooks

Subject: Re: [PATCH] soc: sifive: ccache: reduce printing on init

On 30/08/2022 17:30, [email protected] wrote:
> On 30/08/2022 09:26, Ben Dooks wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The driver prints out 6 lines on startup, which can easily be redcued
>> to two lines without losing any information.
>>
>> Note, to make the types work better, uint64_t has been replaced with
>> ULL to make the unsigned long long match the format in the print
>> statement.
>>
>> Signed-off-by: Ben Dooks <[email protected]>
>> ---
>> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
>> 1 file changed, 11 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
>> index 46ce33db7d30..65a10a6ee211 100644
>> --- a/drivers/soc/sifive/sifive_ccache.c
>> +++ b/drivers/soc/sifive/sifive_ccache.c
>> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
>>
>> static void ccache_config_read(void)
>> {
>> - u32 regval, val;
>> -
>> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
>> - val = regval & 0xFF;
>> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
>> - val = (regval & 0xFF00) >> 8;
>> - pr_info("CCACHE: No. of ways per bank: %d\n", val);
>> - val = (regval & 0xFF0000) >> 16;
>> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
>> - val = (regval & 0xFF000000) >> 24;
>> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
>> -
>> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
>> + u32 cfg;
>> +
>> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
>> +
>> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
>> + (cfg & 0xff), (cfg >> 8) & 0xff,
>> + 1ULL << ((cfg >> 16) & 0xff),
>
> This is just BIT_ULL((cfg >> 16) & 0xff), no?
> Would be nice too if these were defined, so you'd have something
> like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
>
> I do like the cleanup of the uint64_t & cutting down on the prints
> though :) Again, it'd be nice if you and Zong could collaborate on
> a combined v2.

I think even BIT_UL() would do here, if someone is going to make a
cache bigger than 2GiB we'll probably be quite old by then, so v2
might have the last two values down as %lu.

> Thanks,
> Conor.
>
>> + 1ULL << ((cfg >> 24) & 0xff));
>> +
>> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
>> }
>>
>> static const struct of_device_id sifive_ccache_ids[] = {
>> --
>> 2.35.1
>>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>

--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

2022-08-30 17:14:34

by Conor Dooley

Subject: Re: [PATCH] soc: sifive: ccache: reduce printing on init

On 30/08/2022 09:26, Ben Dooks wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The driver prints out 6 lines on startup, which can easily be redcued
> to two lines without losing any information.
>
> Note, to make the types work better, uint64_t has been replaced with
> ULL to make the unsigned long long match the format in the print
> statement.
>
> Signed-off-by: Ben Dooks <[email protected]>
> ---
> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> 1 file changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 46ce33db7d30..65a10a6ee211 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
>
> static void ccache_config_read(void)
> {
> - u32 regval, val;
> -
> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> - val = regval & 0xFF;
> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> - val = (regval & 0xFF00) >> 8;
> - pr_info("CCACHE: No. of ways per bank: %d\n", val);
> - val = (regval & 0xFF0000) >> 16;
> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> - val = (regval & 0xFF000000) >> 24;
> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> -
> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> + u32 cfg;
> +
> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> +
> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> + (cfg & 0xff), (cfg >> 8) & 0xff,
> + 1ULL << ((cfg >> 16) & 0xff),

This is just BIT_ULL((cfg >> 16) & 0xff), no?
Would be nice too if these were defined, so you'd have something
like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)

I do like the cleanup of the uint64_t & cutting down on the prints
though :) Again, it'd be nice if you and Zong could collaborate on
a combined v2.

Thanks,
Conor.

> + 1ULL << ((cfg >> 24) & 0xff));
> +
> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
> }
>
> static const struct of_device_id sifive_ccache_ids[] = {
> --
> 2.35.1
>

2022-08-31 05:33:37

by Zong Li

Subject: Re: [PATCH] soc: sifive: ccache: reduce printing on init

Ben Dooks <[email protected]> 於 2022年8月31日 週三 凌晨1:04寫道：
>
> On 30/08/2022 17:30, [email protected] wrote:
> > On 30/08/2022 09:26, Ben Dooks wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> The driver prints out 6 lines on startup, which can easily be redcued
> >> to two lines without losing any information.
> >>
> >> Note, to make the types work better, uint64_t has been replaced with
> >> ULL to make the unsigned long long match the format in the print
> >> statement.
> >>
> >> Signed-off-by: Ben Dooks <[email protected]>
> >> ---
> >> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> >> 1 file changed, 11 insertions(+), 14 deletions(-)
> >>
> >> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> >> index 46ce33db7d30..65a10a6ee211 100644
> >> --- a/drivers/soc/sifive/sifive_ccache.c
> >> +++ b/drivers/soc/sifive/sifive_ccache.c
> >> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
> >>
> >> static void ccache_config_read(void)
> >> {
> >> - u32 regval, val;
> >> -
> >> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >> - val = regval & 0xFF;
> >> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> >> - val = (regval & 0xFF00) >> 8;
> >> - pr_info("CCACHE: No. of ways per bank: %d\n", val);
> >> - val = (regval & 0xFF0000) >> 16;
> >> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> >> - val = (regval & 0xFF000000) >> 24;
> >> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> >> -
> >> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> >> + u32 cfg;
> >> +
> >> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >> +
> >> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> >> + (cfg & 0xff), (cfg >> 8) & 0xff,
> >> + 1ULL << ((cfg >> 16) & 0xff),
> >
> > This is just BIT_ULL((cfg >> 16) & 0xff), no?
> > Would be nice too if these were defined, so you'd have something
> > like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
> >
> > I do like the cleanup of the uint64_t & cutting down on the prints
> > though :) Again, it'd be nice if you and Zong could collaborate on
> > a combined v2.
>
> I think even BIT_UL() would do here, if someone is going to make a
> cache bigger than 2GiB we'll probably be quite old by then, so v2
> might have the last two values down as %lu.
>

Hi Ben,
Thanks for your suggestion, If you don't mind, I will take this into
my V2 patchset.

> > Thanks,
> > Conor.
> >
> >> + 1ULL << ((cfg >> 24) & 0xff));
> >> +
> >> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
> >> }
> >>
> >> static const struct of_device_id sifive_ccache_ids[] = {
> >> --
> >> 2.35.1
> >>
> >
> > _______________________________________________
> > linux-riscv mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv

2022-08-31 05:36:40

by Zong Li

Subject: Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

<[email protected]> 於 2022年8月30日 週二 下午4:42寫道：
>
> On 29/08/2022 09:40, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Mon, Aug 29, 2022 at 3:05 PM <[email protected]> wrote:
> >>
> >> Hey Zong,
> >>
> >> On 29/08/2022 07:22, Zong Li wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> From: Greentime Hu <[email protected]>
> >>>
> >>> Since composible cache may be L3 cache if pL2 cache exists, we should use
> >>> its original name composible cache to prevent confusion.
> >>>
> >>> Signed-off-by: Greentime Hu <[email protected]>
> >>> Signed-off-by: Zong Li <[email protected]>
>
> >>>
> >>> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> >>> index 58cf8c40d08d..3d65d2771f9a 100644
> >>> --- a/drivers/soc/sifive/Kconfig
> >>> +++ b/drivers/soc/sifive/Kconfig
> >>> @@ -2,9 +2,10 @@
> >>>
> >>> if SOC_SIFIVE
> >>>
> >>> -config SIFIVE_L2
> >>> - bool "Sifive L2 Cache controller"
> >>> +config SIFIVE_CCACHE
> >>> + bool "Sifive composable Cache controller"
> >>> + default y
> >>
> >> Changing this to default on is not a rename of the file..
> >> This should be in a different patch.
> >
> > Okay, let me separate it to another patch, but I guess we could remove
> > it, and enable it by user. What is your perspective on it?
>
> Personally I would like to leave the default y out & leave it up
> to the user - the driver is more informational than anything else
> so I don't think making it default to on makes sense.
>

Agree, let me remove it in the next version. Thanks

>
>
> >>> +
> >>> +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> >>> +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
> >>> +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
> >>> +
> >>> +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
> >>> +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
> >>> +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
> >>> +
> >>> +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
> >>> +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
> >>> +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> >>> +
> >>> +#define SIFIVE_CCACHE_CONFIG 0x00
> >>> +#define SIFIVE_CCACHE_WAYENABLE 0x08
> >>> +#define SIFIVE_CCACHE_ECCINJECTERR 0x40
> >>
> >> From what I can see, you've also changed these around too?
> >> Please generate the patch's diff so that the rename is detected & the
> >> diff shows only what changed in the file. The -M option is what you
> >> are looking for.
> >>
> >> I have a couple other comments to make about what's changed here other,
> >> thatn the rename but I will do so against a v2 where the diff is usable.
> >>
> >
> > Let me sent the v2 patch, and separate the rename and diff part
>
> Great, thanks. I'll take another look at it then.
>
> Conor.
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv

2022-08-31 08:38:13

by Zong Li

Subject: Re: [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE

On Tue, Aug 30, 2022 at 3:59 PM Ben Dooks <[email protected]> wrote:
>
> On 29/08/2022 07:21, Zong Li wrote:
> > Since composible cache may be L3 cache if private L2 cache exists, we
> > should use its original name "composible cache" to prevent confusion.
> >
> > This patchset contains the modification which is related to ccache, such
> > as DT binding and EDAC driver.
> >
> > Greentime Hu (1):
> > soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.
> >
> > Zong Li (2):
> > dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache
> > EDAC/sifive: use sifive_ccache instead of sifive_l2
> >
> > ...ifive-l2-cache.yaml => sifive-ccache.yaml} | 6 +-
> > drivers/edac/Kconfig | 2 +-
> > drivers/edac/sifive_edac.c | 12 +-
> > drivers/soc/sifive/Kconfig | 7 +-
> > drivers/soc/sifive/Makefile | 2 +-
> > drivers/soc/sifive/sifive_ccache.c | 221 ++++++++++++++++
> > drivers/soc/sifive/sifive_l2_cache.c | 237 ------------------
> > include/soc/sifive/sifive_ccache.h | 16 ++
> > include/soc/sifive/sifive_l2_cache.h | 16 --
> > 9 files changed, 253 insertions(+), 266 deletions(-)
> > rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> > create mode 100644 drivers/soc/sifive/sifive_ccache.c
> > delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
> > create mode 100644 include/soc/sifive/sifive_ccache.h
> > delete mode 100644 include/soc/sifive/sifive_l2_cache.h
>
> Is this series available on a git branch anywhere, I have at least
> one other cleanup I was doing in a similar move to rename and make
> it usable as the l3 cache.
>
> I gave the series a quick review and did not find any issues so far.
>

Thanks for your review, I don't push the series to a public
repository, if you needed, I can push it to somewhere.

> --
> Ben
>
>

2022-08-31 16:05:52

by Ben Dooks

Subject: Re: [PATCH] soc: sifive: ccache: reduce printing on init

On 31/08/2022 06:22, Zong Li wrote:
> Ben Dooks <[email protected]> 於 2022年8月31日 週三 凌晨1:04寫道：
>>
>> On 30/08/2022 17:30, [email protected] wrote:
>>> On 30/08/2022 09:26, Ben Dooks wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> The driver prints out 6 lines on startup, which can easily be redcued
>>>> to two lines without losing any information.
>>>>
>>>> Note, to make the types work better, uint64_t has been replaced with
>>>> ULL to make the unsigned long long match the format in the print
>>>> statement.
>>>>
>>>> Signed-off-by: Ben Dooks <[email protected]>
>>>> ---
>>>> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
>>>> 1 file changed, 11 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
>>>> index 46ce33db7d30..65a10a6ee211 100644
>>>> --- a/drivers/soc/sifive/sifive_ccache.c
>>>> +++ b/drivers/soc/sifive/sifive_ccache.c
>>>> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
>>>>
>>>> static void ccache_config_read(void)
>>>> {
>>>> - u32 regval, val;
>>>> -
>>>> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
>>>> - val = regval & 0xFF;
>>>> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
>>>> - val = (regval & 0xFF00) >> 8;
>>>> - pr_info("CCACHE: No. of ways per bank: %d\n", val);
>>>> - val = (regval & 0xFF0000) >> 16;
>>>> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
>>>> - val = (regval & 0xFF000000) >> 24;
>>>> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
>>>> -
>>>> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>>>> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
>>>> + u32 cfg;
>>>> +
>>>> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
>>>> +
>>>> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
>>>> + (cfg & 0xff), (cfg >> 8) & 0xff,
>>>> + 1ULL << ((cfg >> 16) & 0xff),
>>>
>>> This is just BIT_ULL((cfg >> 16) & 0xff), no?
>>> Would be nice too if these were defined, so you'd have something
>>> like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
>>>
>>> I do like the cleanup of the uint64_t & cutting down on the prints
>>> though :) Again, it'd be nice if you and Zong could collaborate on
>>> a combined v2.
>>
>> I think even BIT_UL() would do here, if someone is going to make a
>> cache bigger than 2GiB we'll probably be quite old by then, so v2
>> might have the last two values down as %lu.
>>
>
> Hi Ben,
> Thanks for your suggestion, If you don't mind, I will take this into
> my V2 patchset.

Thanks.

I may well post v2 of this tomorrow with the BIT_ULL() suggestions
from Conor, or even down to BIT_UL() and use %lu as noted.

>
>>> Thanks,
>>> Conor.
>>>
>>>> + 1ULL << ((cfg >> 24) & 0xff));
>>>> +
>>>> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>>>> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
>>>> }
>>>>
>>>> static const struct of_device_id sifive_ccache_ids[] = {
>>>> --
>>>> 2.35.1
>>>>
>>>
>>> _______________________________________________
>>> linux-riscv mailing list
>>> [email protected]
>>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>>
>>
>> --
>> Ben Dooks http://www.codethink.co.uk/
>> Senior Engineer Codethink - Providing Genius
>>
>> https://www.codethink.co.uk/privacy.html
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-riscv

2022-09-01 09:34:20

by Zong Li

Subject: Re: [PATCH] soc: sifive: ccache: reduce printing on init

On Wed, Aug 31, 2022 at 11:55 PM Ben Dooks <[email protected]> wrote:
>
> On 31/08/2022 06:22, Zong Li wrote:
> > Ben Dooks <[email protected]> 於 2022年8月31日 週三 凌晨1:04寫道：
> >>
> >> On 30/08/2022 17:30, [email protected] wrote:
> >>> On 30/08/2022 09:26, Ben Dooks wrote:
> >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>>
> >>>> The driver prints out 6 lines on startup, which can easily be redcued
> >>>> to two lines without losing any information.
> >>>>
> >>>> Note, to make the types work better, uint64_t has been replaced with
> >>>> ULL to make the unsigned long long match the format in the print
> >>>> statement.
> >>>>
> >>>> Signed-off-by: Ben Dooks <[email protected]>
> >>>> ---
> >>>> drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> >>>> 1 file changed, 11 insertions(+), 14 deletions(-)
> >>>>
> >>>> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> >>>> index 46ce33db7d30..65a10a6ee211 100644
> >>>> --- a/drivers/soc/sifive/sifive_ccache.c
> >>>> +++ b/drivers/soc/sifive/sifive_ccache.c
> >>>> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
> >>>>
> >>>> static void ccache_config_read(void)
> >>>> {
> >>>> - u32 regval, val;
> >>>> -
> >>>> - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >>>> - val = regval & 0xFF;
> >>>> - pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> >>>> - val = (regval & 0xFF00) >> 8;
> >>>> - pr_info("CCACHE: No. of ways per bank: %d\n", val);
> >>>> - val = (regval & 0xFF0000) >> 16;
> >>>> - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> >>>> - val = (regval & 0xFF000000) >> 24;
> >>>> - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> >>>> -
> >>>> - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >>>> - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> >>>> + u32 cfg;
> >>>> +
> >>>> + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >>>> +
> >>>> + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> >>>> + (cfg & 0xff), (cfg >> 8) & 0xff,
> >>>> + 1ULL << ((cfg >> 16) & 0xff),
> >>>
> >>> This is just BIT_ULL((cfg >> 16) & 0xff), no?
> >>> Would be nice too if these were defined, so you'd have something
> >>> like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
> >>>
> >>> I do like the cleanup of the uint64_t & cutting down on the prints
> >>> though :) Again, it'd be nice if you and Zong could collaborate on
> >>> a combined v2.
> >>
> >> I think even BIT_UL() would do here, if someone is going to make a
> >> cache bigger than 2GiB we'll probably be quite old by then, so v2
> >> might have the last two values down as %lu.
> >>
> >
> > Hi Ben,
> > Thanks for your suggestion, If you don't mind, I will take this into
> > my V2 patchset.
>
> Thanks.
>
> I may well post v2 of this tomorrow with the BIT_ULL() suggestions
> from Conor, or even down to BIT_UL() and use %lu as noted.
>

No problem Ben. Could you please also add me in the thread of your v2,
then I can take it and send out my v2 patchset. Thanks.

> >
> >>> Thanks,
> >>> Conor.
> >>>
> >>>> + 1ULL << ((cfg >> 24) & 0xff));
> >>>> +
> >>>> + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >>>> + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
> >>>> }
> >>>>
> >>>> static const struct of_device_id sifive_ccache_ids[] = {
> >>>> --
> >>>> 2.35.1
> >>>>
> >>>
> >>> _______________________________________________
> >>> linux-riscv mailing list
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> >>>
> >>
> >> --
> >> Ben Dooks http://www.codethink.co.uk/
> >> Senior Engineer Codethink - Providing Genius
> >>
> >> https://www.codethink.co.uk/privacy.html
> >>
> >>
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>

2022-09-02 20:13:07

by Rob Herring (Arm)

Subject: Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

On Tue, 30 Aug 2022 13:51:33 +0100, Ben Dooks wrote:
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
>
> Signed-off-by: Ben Dooks <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>

Acked-by: Rob Herring <[email protected]>

2022-10-07 03:14:31

by Palmer Dabbelt

Subject: Re: [PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2

On Sun, 28 Aug 2022 23:22:02 PDT (-0700), [email protected] wrote:
> The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
> apply the change as well

That means the build would be broken before this patch, which we
generally try to avoid as it breaks things like bisecting.

>
> Signed-off-by: Zong Li <[email protected]>
> ---
> drivers/edac/Kconfig | 2 +-
> drivers/edac/sifive_edac.c | 12 ++++++------
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 17562cf1fe97..456602d373b7 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC
>
> config EDAC_SIFIVE
> bool "Sifive platform EDAC driver"
> - depends on EDAC=y && SIFIVE_L2
> + depends on EDAC=y && SIFIVE_CCACHE
> help
> Support for error detection and correction on the SiFive SoCs.
>
> diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
> index ee800aec7d47..b844e2626fd5 100644
> --- a/drivers/edac/sifive_edac.c
> +++ b/drivers/edac/sifive_edac.c
> @@ -2,7 +2,7 @@
> /*
> * SiFive Platform EDAC Driver
> *
> - * Copyright (C) 2018-2019 SiFive, Inc.
> + * Copyright (C) 2018-2022 SiFive, Inc.
> *
> * This driver is partially based on octeon_edac-pc.c
> *
> @@ -10,7 +10,7 @@
> #include <linux/edac.h>
> #include <linux/platform_device.h>
> #include "edac_module.h"
> -#include <soc/sifive/sifive_l2_cache.h>
> +#include <soc/sifive/sifive_ccache.h>
>
> #define DRVNAME "sifive_edac"
>
> @@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr)
>
> p = container_of(this, struct sifive_edac_priv, notifier);
>
> - if (event == SIFIVE_L2_ERR_TYPE_UE)
> + if (event == SIFIVE_CCACHE_ERR_TYPE_UE)
> edac_device_handle_ue(p->dci, 0, 0, msg);
> - else if (event == SIFIVE_L2_ERR_TYPE_CE)
> + else if (event == SIFIVE_CCACHE_ERR_TYPE_CE)
> edac_device_handle_ce(p->dci, 0, 0, msg);
>
> return NOTIFY_OK;
> @@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev)
> goto err;
> }
>
> - register_sifive_l2_error_notifier(&p->notifier);
> + register_sifive_ccache_error_notifier(&p->notifier);
>
> return 0;
>
> @@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev)
> {
> struct sifive_edac_priv *p = platform_get_drvdata(pdev);
>
> - unregister_sifive_l2_error_notifier(&p->notifier);
> + unregister_sifive_ccache_error_notifier(&p->notifier);
> edac_device_del_device(&pdev->dev);
> edac_device_free_ctl_info(p->dci);