v2:
1. Addressed the review comments given in v1
2. Removed the DMA coherent buffer for register read and used
streaming DMA API’s
3. Reorganized the NAND read and write functions
4. Separated patch for driver and documentation changes
5. Changed the compatible string for EBI2
v1:
http://www.spinics.net/lists/devicetree/msg183706.html
Abhishek Sahu (25):
mtd: nand: qcom: fix config error for BCH
mtd: nand: qcom: program NAND_DEV_CMD_VLD register
mtd: nand: qcom: change compatible string for EBI2 NANDC
dt-bindings: qcom_nandc: change compatible string for EBI2 NANDC
mtd: nand: qcom: remove redundant chip select compatible string
dt-bindings: qcom_nandc: remove chip select compatible string
mtd: nand: qcom: reorganize nand page read
mtd: nand: qcom: reorganize nand page write
mtd: nand: qcom: remove memset for clearing read register buffer
mtd: nand: qcom: reorganize nand devices probing
mtd: nand: qcom: support for NAND controller properties
dt-bindings: qcom_nandc: QPIC NAND documentation
mtd: nand: qcom: add QPIC NAND compatible string
mtd: nand: qcom: add and initialize QPIC DMA resources
mtd: nand: qcom: DMA mapping support for register read buffer
mtd: nand: qcom: allocate BAM transaction
mtd: nand: qcom: add BAM DMA descriptor handling
mtd: nand: qcom: support for passing flags in transfer functions
mtd: nand: qcom: support for read location registers
mtd: nand: qcom: erased codeword detection configuration
mtd: nand: qcom: support for QPIC page read/write
mtd: nand: qcom: QPIC raw write support
mtd: nand: qcom: change register offset defines with enums
dt-bindings: qcom_nandc: compatible string for version 1.5.0
mtd: nand: qcom: support for QPIC version 1.5.0
.../devicetree/bindings/mtd/qcom_nandc.txt | 56 +-
drivers/mtd/nand/qcom_nandc.c | 1157 ++++++++++++++++----
2 files changed, 1010 insertions(+), 203 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The configuration for BCH is not correct in the current driver.
The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the
BCH ECC in which
0x1 : BCH_DISABLED
0x0 : BCH_ENABLED
But currently host->bch_enabled is being assined to BCH_DISABLED.
Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
Cc: [email protected]
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 57d483a..bc0408c 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -1893,7 +1893,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
| wide_bus << WIDE_FLASH
| 1 << DEV0_CFG1_ECC_DISABLE;
- host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
+ host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
| 0 << ECC_SW_RESET
| host->cw_data << ECC_NUM_DATA_BYTES
| 1 << ECC_FORCE_CLK_OPEN
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The current driver is failing without complete bootchain since
NAND_DEV_CMD_VLD value is not valid.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index bc0408c..f3b995d 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -148,6 +148,9 @@
#define FETCH_ID 0xb
#define RESET_DEVICE 0xd
+/* Value for NAND_DEV_CMD_VLD */
+#define NAND_DEV_CMD_VLD_VAL 0x1d
+
/*
* the NAND controller performs reads/writes with ECC in 516 byte chunks.
* the driver calls the chunks 'step' or 'codeword' interchangeably
@@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
{
/* kill onenand */
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
+ nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
/* enable ADM DMA */
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The current compatible string “qcom,ipq806x-nand" implies that
the driver is specific to IPQ806x. This driver can be used by
any chip which uses EBI2 NAND controller so changed the
compatible string to “qcom,ebi2-nandc” to give it more generic
name.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f3b995d..8fa2f0c 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -2190,7 +2190,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
* more controller variants
*/
static const struct of_device_id qcom_nandc_of_match[] = {
- { .compatible = "qcom,ipq806x-nand",
+ { .compatible = "qcom,ebi2-nandc",
.data = (void *)EBI2_NANDC_ECC_MODES,
},
{}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The current compatible string “qcom,ipq806x-nand" implies that
the driver is specific to IPQ806x. This driver can be used by
any chip which uses EBI2 NAND controller so changed the
compatible string to “qcom,ebi2-nandc” to give it more generic
name.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <[email protected]>
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 70dd511..4511918 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -1,7 +1,9 @@
* Qualcomm NAND controller
Required properties:
-- compatible: should be "qcom,ipq806x-nand"
+- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
+ DMA like IPQ8064.
+
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Currently the compatible “qcom,nandcs” is being used for each
connected NAND device to support for multiple NAND devices in the
same bus. The same thing can be achieved by looking reg property
for each sub nodes which contains the chip select number so this
patch removes the use of “qcom,nandcs” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8fa2f0c..110a26a 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -2129,22 +2129,20 @@ static int qcom_nandc_probe(struct platform_device *pdev)
goto err_setup;
for_each_available_child_of_node(dn, child) {
- if (of_device_is_compatible(child, "qcom,nandcs")) {
- host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
- if (!host) {
- of_node_put(child);
- ret = -ENOMEM;
- goto err_cs_init;
- }
-
- ret = qcom_nand_host_init(nandc, host, child);
- if (ret) {
- devm_kfree(dev, host);
- continue;
- }
+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+ if (!host) {
+ of_node_put(child);
+ ret = -ENOMEM;
+ goto err_cs_init;
+ }
- list_add_tail(&host->node, &nandc->host_list);
+ ret = qcom_nand_host_init(nandc, host, child);
+ if (ret) {
+ devm_kfree(dev, host);
+ continue;
}
+
+ list_add_tail(&host->node, &nandc->host_list);
}
if (list_empty(&nandc->host_list)) {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Currently the compatible “qcom,nandcs” is being used for each
connected NAND device to support for multiple NAND devices in the
same bus. The same thing can be achieved by looking reg property
for each sub nodes which contains the chip select number so this
patch removes the use of “qcom,nandcs” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <[email protected]>
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 4511918..b24adfe 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -28,7 +28,6 @@ chip-selects which (may) contain NAND flash chips. Their properties are as
follows.
Required properties:
-- compatible: should contain "qcom,nandcs"
- reg: a single integer representing the chip-select
number (e.g., 0, 1, 2, etc.)
- #address-cells: see partition.txt
@@ -62,7 +61,6 @@ nand@1ac00000 {
#size-cells = <0>;
nandcs@0 {
- compatible = "qcom,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Each NAND page consist of multiple codewords. Following is
sequence for NAND page read according to hardware guide.
1. Program Power-up configuration, page row, page column
address and flash configuration registers.
2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
codeword.
3. Read NAND_FLASH_STATUS for each codeword.
The step 1 should be done once for each page and step 2,3 should
be done for each codeword.
Currently, all the 3 steps are being done for each codeword which
is wrong. Now this patch reorganizes read page functions to
configure page specific register once and per codeword specific
registers for each NAND ECC step.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 37 +++++++++++++++++++++++++++----------
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 110a26a..27ea594 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -605,15 +605,23 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
}
/*
- * helper to prepare dma descriptors to configure registers needed for reading a
- * codeword/step in a page
+ * Helper to prepare DMA descriptors for configuring registers
+ * before reading a NAND page.
*/
-static void config_cw_read(struct qcom_nand_controller *nandc)
+static void config_nand_page_read(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
+ write_reg_dma(nandc, NAND_ADDR0, 2);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
+}
+/*
+ * Helper to prepare DMA descriptors for configuring registers
+ * before reading each codeword in NAND page.
+ */
+static void config_nand_cw_read(struct qcom_nand_controller *nandc)
+{
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1);
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
@@ -621,9 +629,15 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
}
/*
- * helpers to prepare dma descriptors used to configure registers needed for
- * writing a codeword/step in a page
+ * Helper to prepare dma descriptors to configure registers needed for reading a
+ * single codeword in page
*/
+static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
+{
+ config_nand_page_read(nandc);
+ config_nand_cw_read(nandc);
+}
+
static void config_cw_write_pre(struct qcom_nand_controller *nandc)
{
write_reg_dma(nandc, NAND_FLASH_CMD, 3);
@@ -692,7 +706,7 @@ static int nandc_param(struct qcom_nand_host *host)
nandc->buf_count = 512;
memset(nandc->data_buffer, 0xff, nandc->buf_count);
- config_cw_read(nandc);
+ config_nand_single_cw_page_read(nandc);
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
nandc->buf_count);
@@ -1105,6 +1119,8 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
struct nand_ecc_ctrl *ecc = &chip->ecc;
int i, ret;
+ config_nand_page_read(nandc);
+
/* queue cmd descs for each codeword */
for (i = 0; i < ecc->steps; i++) {
int data_size, oob_size;
@@ -1118,7 +1134,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
oob_size = host->ecc_bytes_hw + host->spare_bytes;
}
- config_cw_read(nandc);
+ config_nand_cw_read(nandc);
if (data_buf)
read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
@@ -1178,7 +1194,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, true);
- config_cw_read(nandc);
+ config_nand_single_cw_page_read(nandc);
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
@@ -1228,6 +1244,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
host->use_ecc = false;
update_rw_regs(host, ecc->steps, true);
+ config_nand_page_read(nandc);
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
@@ -1246,7 +1263,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
- config_cw_read(nandc);
+ config_nand_cw_read(nandc);
read_data_dma(nandc, reg_off, data_buf, data_size1);
reg_off += data_size1;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Each NAND page consist of multiple codewords. Following is
sequence for NAND page write according to hardware guide.
1. Program Power-up configuration, page row, page column
address and flash configuration registers.
2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
codeword.
3. Read NAND_FLASH_STATUS for each codeword.
The step 1 should be done once for each page and step 2,3 should
be done for each codeword.
Currently, all the 3 steps are being done for each codeword which
is wrong. Now this patch reorganizes page write functions to
configure page specific register once and per codeword specific
registers for each NAND ECC step.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 27ea594..5b71478 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -638,15 +638,24 @@ static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
config_nand_cw_read(nandc);
}
-static void config_cw_write_pre(struct qcom_nand_controller *nandc)
+/*
+ * Helper to prepare DMA descriptors used to configure registers needed for
+ * before writing a NAND page.
+ */
+static void config_nand_page_write(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
+ write_reg_dma(nandc, NAND_ADDR0, 2);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
}
-static void config_cw_write_post(struct qcom_nand_controller *nandc)
+/*
+ * Helper to prepare DMA descriptors for configuring registers
+ * before writing each codeword in NAND page.
+ */
+static void config_nand_cw_write(struct qcom_nand_controller *nandc)
{
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1);
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
@@ -1329,6 +1338,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
host->use_ecc = true;
update_rw_regs(host, ecc->steps, false);
+ config_nand_page_write(nandc);
for (i = 0; i < ecc->steps; i++) {
int data_size, oob_size;
@@ -1342,7 +1352,6 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
oob_size = ecc->bytes;
}
- config_cw_write_pre(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
@@ -1360,7 +1369,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
oob_buf, oob_size);
}
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
data_buf += data_size;
oob_buf += oob_size;
@@ -1393,6 +1402,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
host->use_ecc = false;
update_rw_regs(host, ecc->steps, false);
+ config_nand_page_write(nandc);
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
@@ -1411,8 +1421,6 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
- config_cw_write_pre(nandc);
-
write_data_dma(nandc, reg_off, data_buf, data_size1);
reg_off += data_size1;
data_buf += data_size1;
@@ -1428,7 +1436,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
write_data_dma(nandc, reg_off, oob_buf, oob_size2);
oob_buf += oob_size2;
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
}
ret = submit_descs(nandc);
@@ -1478,10 +1486,10 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, false);
- config_cw_write_pre(nandc);
+ config_nand_page_write(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
data_size + oob_size);
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
ret = submit_descs(nandc);
@@ -1563,9 +1571,9 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, false);
- config_cw_write_pre(nandc);
+ config_nand_page_write(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
ret = submit_descs(nandc);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The memset in clear_read_regs is overhead. All the register data
will be filled by DMA during NAND operation so making these
register variables zero is not required.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 5b71478..7ecd0f8 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -826,8 +826,6 @@ static void free_descs(struct qcom_nand_controller *nandc)
static void clear_read_regs(struct qcom_nand_controller *nandc)
{
nandc->reg_read_pos = 0;
- memset(nandc->reg_read_buf, 0,
- MAX_REG_RD * sizeof(*nandc->reg_read_buf));
}
static void pre_command(struct qcom_nand_host *host, int command)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
This is reorganization of exiting code and will not change any
functionality. The NAND controller supports multiple NAND device
with different page size. The subsequent patch allocate memory
which depends upon the maximum number of codewords so this patch
reorganizes the NAND device probing. First the ONFI parameter
page will be read from each connected device followed by MTD
device registration.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 88 +++++++++++++++++++++++++++++--------------
1 file changed, 59 insertions(+), 29 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 7ecd0f8..8f9e86c 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -2059,14 +2059,67 @@ static int qcom_nand_host_init(struct qcom_nand_controller *nandc,
return ret;
ret = qcom_nand_host_setup(host);
- if (ret)
- return ret;
+
+ return ret;
+}
+
+static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
+ struct qcom_nand_host *host,
+ struct device_node *dn)
+{
+ struct nand_chip *chip = &host->chip;
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret;
ret = nand_scan_tail(mtd);
if (ret)
return ret;
- return mtd_device_register(mtd, NULL, 0);
+ ret = mtd_device_register(mtd, NULL, 0);
+ if (ret)
+ nand_cleanup(mtd_to_nand(mtd));
+
+ return ret;
+}
+
+static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
+{
+ struct device *dev = nandc->dev;
+ struct device_node *dn = dev->of_node, *child;
+ struct qcom_nand_host *host, *tmp;
+ int ret;
+
+ for_each_available_child_of_node(dn, child) {
+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+ if (!host) {
+ of_node_put(child);
+ return -ENOMEM;
+ }
+
+ ret = qcom_nand_host_init(nandc, host, child);
+ if (ret) {
+ devm_kfree(dev, host);
+ continue;
+ }
+
+ list_add_tail(&host->node, &nandc->host_list);
+ }
+
+ if (list_empty(&nandc->host_list))
+ return -ENODEV;
+
+ list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
+ ret = qcom_nand_mtd_register(nandc, host, child);
+ if (ret) {
+ list_del(&host->node);
+ devm_kfree(dev, host);
+ }
+ }
+
+ if (list_empty(&nandc->host_list))
+ return -ENODEV;
+
+ return 0;
}
/* parse custom DT properties here */
@@ -2094,10 +2147,8 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
static int qcom_nandc_probe(struct platform_device *pdev)
{
struct qcom_nand_controller *nandc;
- struct qcom_nand_host *host;
const void *dev_data;
struct device *dev = &pdev->dev;
- struct device_node *dn = dev->of_node, *child;
struct resource *res;
int ret;
@@ -2151,33 +2202,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
if (ret)
goto err_setup;
- for_each_available_child_of_node(dn, child) {
- host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
- if (!host) {
- of_node_put(child);
- ret = -ENOMEM;
- goto err_cs_init;
- }
-
- ret = qcom_nand_host_init(nandc, host, child);
- if (ret) {
- devm_kfree(dev, host);
- continue;
- }
-
- list_add_tail(&host->node, &nandc->host_list);
- }
-
- if (list_empty(&nandc->host_list)) {
- ret = -ENODEV;
- goto err_cs_init;
- }
+ ret = qcom_probe_nand_devices(nandc);
+ if (ret)
+ goto err_setup;
return 0;
-err_cs_init:
- list_for_each_entry(host, &nandc->host_list, node)
- nand_release(nand_to_mtd(&host->chip));
err_setup:
clk_disable_unprepare(nandc->aon_clk);
err_aon_clk:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Currently driver data is being assigned directly with ECC modes.
Now, the plan is to add more NAND controller versions, so
reorganized the current driver data assignment by creating NAND
controller properties structure. This will contain all
properties specific to NAND controller.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8f9e86c..3b0ae91 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -235,7 +235,7 @@ struct nandc_regs {
* writes. contains the register values to be
* written to controller
* @cmd1/vld: some fixed controller register values
- * @ecc_modes: supported ECC modes by the current controller,
+ * @props: properties of current NAND controller IP,
* initialized via DT match data
*/
struct qcom_nand_controller {
@@ -266,7 +266,7 @@ struct qcom_nand_controller {
struct nandc_regs *regs;
u32 cmd1, vld;
- u32 ecc_modes;
+ const struct qcom_props *props;
};
/*
@@ -319,6 +319,15 @@ struct qcom_nand_host {
u32 clrreadstatus;
};
+/*
+ * This data type corresponds to the nand controller properties which varies
+ * among different NAND controller IP's.
+ * @ecc_modes - ecc mode for NAND
+ */
+struct qcom_props {
+ u32 ecc_modes;
+};
+
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
{
return container_of(chip, struct qcom_nand_host, chip);
@@ -1820,7 +1829,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
* uses lesser bytes for ECC. If RS is used, the ECC bytes is
* always 10 bytes
*/
- if (nandc->ecc_modes & ECC_BCH_4BIT) {
+ if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
/* BCH */
host->bch_enabled = true;
ecc_mode = 0;
@@ -2165,7 +2174,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
return -ENODEV;
}
- nandc->ecc_modes = (unsigned long)dev_data;
+ nandc->props = dev_data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
nandc->base = devm_ioremap_resource(dev, res);
@@ -2234,7 +2243,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
return 0;
}
-#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
+static const struct qcom_props ebi2_nandc_data = {
+ .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
+};
/*
* data will hold a struct pointer containing more differences once we support
@@ -2242,7 +2253,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
*/
static const struct of_device_id qcom_nandc_of_match[] = {
{ .compatible = "qcom,ebi2-nandc",
- .data = (void *)EBI2_NANDC_ECC_MODES,
+ .data = &ebi2_nandc_data,
},
{}
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses only single ADM channel.
3. CRCI is only required for ADM DMA and its not required for
QPIC NAND.
Signed-off-by: Abhishek Sahu <[email protected]>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 54 ++++++++++++++++++++--
1 file changed, 51 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index b24adfe..8efaeb0 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -1,13 +1,15 @@
* Qualcomm NAND controller
Required properties:
-- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
- DMA like IPQ8064.
-
+- compatible: must be one of the following:
+ * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
+ * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
always on clock
+
+EBI2 specific properties:
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
controller node and the channel number to be used for
NAND. Refer to dma.txt and qcom_adm.txt for more details
@@ -18,6 +20,12 @@ Required properties:
- qcom,data-crci: must contain the ADM data type CRCI block instance
number specified for the NAND controller on the given
platform
+
+QPIC specific properties:
+- dmas: DMA specifier, consisting of a phandle to the BAM DMA
+ and the channel number to be used for NAND. Refer to
+ dma.txt, qcom_bam_dma.txt for more details
+- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
- #address-cells: <1> - subnodes give the chip-select number
- #size-cells: <0>
@@ -84,3 +92,43 @@ nand@1ac00000 {
};
};
};
+
+nand@79b0000 {
+ compatible = "qcom,qpic-nandc-v1.4.0";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nandcs@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The current driver only support EBI2 NAND which uses ADM DMA. The
latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
registers and programming sequence are same for EBI2 and QPIC
NAND so the same driver can support QPIC NAND also by adding the
BAM DMA support. This patch adds the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 3b0ae91..6d24630 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -323,9 +323,11 @@ struct qcom_nand_host {
* This data type corresponds to the nand controller properties which varies
* among different NAND controller IP's.
* @ecc_modes - ecc mode for NAND
+ * @is_bam - whether NAND controller is using bam
*/
struct qcom_props {
u32 ecc_modes;
+ bool is_bam;
};
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
@@ -2245,6 +2247,12 @@ static int qcom_nandc_remove(struct platform_device *pdev)
static const struct qcom_props ebi2_nandc_data = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
+ .is_bam = false,
+};
+
+static const struct qcom_props qpic_nandc_v1_4_0_data = {
+ .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+ .is_bam = true,
};
/*
@@ -2255,6 +2263,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
{ .compatible = "qcom,ebi2-nandc",
.data = &ebi2_nandc_data,
},
+ { .compatible = "qcom,qpic-nandc-v1.4.0",
+ .data = &qpic_nandc_v1_4_0_data,
+ },
{}
};
MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
1. QPIC NAND uses 3 BAM channels: command, data tx and data
rx while EBI2 NAND uses only single ADM channel.
2. CRCI is only required for ADM DMA and its not required for
QPIC NAND.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 83 +++++++++++++++++++++++++++++++++----------
1 file changed, 65 insertions(+), 18 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 6d24630..cb2b245 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -250,9 +250,19 @@ struct qcom_nand_controller {
struct clk *core_clk;
struct clk *aon_clk;
- struct dma_chan *chan;
- unsigned int cmd_crci;
- unsigned int data_crci;
+ union {
+ struct {
+ struct dma_chan *tx_chan;
+ struct dma_chan *rx_chan;
+ struct dma_chan *cmd_chan;
+ };
+ struct {
+ struct dma_chan *chan;
+ unsigned int cmd_crci;
+ unsigned int data_crci;
+ };
+ };
+
struct list_head desc_list;
u8 *data_buffer;
@@ -1985,10 +1995,31 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
if (!nandc->reg_read_buf)
return -ENOMEM;
- nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
- if (!nandc->chan) {
- dev_err(nandc->dev, "failed to request slave channel\n");
- return -ENODEV;
+ if (nandc->props->is_bam) {
+ nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
+ if (!nandc->tx_chan) {
+ dev_err(nandc->dev, "failed to request tx channel\n");
+ return -ENODEV;
+ }
+
+ nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
+ if (!nandc->rx_chan) {
+ dev_err(nandc->dev, "failed to request rx channel\n");
+ return -ENODEV;
+ }
+
+ nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
+ if (!nandc->cmd_chan) {
+ dev_err(nandc->dev, "failed to request cmd channel\n");
+ return -ENODEV;
+ }
+ } else {
+ nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
+ if (!nandc->chan) {
+ dev_err(nandc->dev,
+ "failed to request slave channel\n");
+ return -ENODEV;
+ }
}
INIT_LIST_HEAD(&nandc->desc_list);
@@ -2001,7 +2032,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
{
- dma_release_channel(nandc->chan);
+ if (nandc->props->is_bam) {
+ if (nandc->tx_chan)
+ dma_release_channel(nandc->tx_chan);
+
+ if (nandc->rx_chan)
+ dma_release_channel(nandc->rx_chan);
+
+ if (nandc->cmd_chan)
+ dma_release_channel(nandc->cmd_chan);
+ } else {
+ if (nandc->chan)
+ dma_release_channel(nandc->chan);
+ }
}
/* one time setup of a few nand controller registers */
@@ -2140,16 +2183,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
struct device_node *np = nandc->dev->of_node;
int ret;
- ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
- if (ret) {
- dev_err(nandc->dev, "command CRCI unspecified\n");
- return ret;
- }
+ if (!nandc->props->is_bam) {
+ ret = of_property_read_u32(np, "qcom,cmd-crci",
+ &nandc->cmd_crci);
+ if (ret) {
+ dev_err(nandc->dev, "command CRCI unspecified\n");
+ return ret;
+ }
- ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
- if (ret) {
- dev_err(nandc->dev, "data CRCI unspecified\n");
- return ret;
+ ret = of_property_read_u32(np, "qcom,data-crci",
+ &nandc->data_crci);
+ if (ret) {
+ dev_err(nandc->dev, "data CRCI unspecified\n");
+ return ret;
+ }
}
return 0;
@@ -2199,7 +2246,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
ret = qcom_nandc_alloc(nandc);
if (ret)
- return ret;
+ goto err_core_clk;
ret = clk_prepare_enable(nandc->core_clk);
if (ret)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The EBI2 NAND directly remaps register read buffer with
dma_map_sg. The QPIC NAND will give register read buffer in its
command descriptor and the command descriptor will be mapped with
dma_map_sg instead of register read buffer. This command
descriptor will contain the dma address of the register read
buffer.
This patch adds the DMA mapping support for register read buffer.
This buffer will be DMA mapped during allocation time. Before
starting of any operation, this buffer will be synced for device
operation and after operation completion, it will be synced for
CPU.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index cb2b245..f49c3da 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -229,6 +229,7 @@ struct nandc_regs {
* by upper layers directly
* @buf_size/count/start: markers for chip->read_buf/write_buf functions
* @reg_read_buf: local buffer for reading back registers via DMA
+ * @reg_read_buf_phys: contains dma address for register read buffer
* @reg_read_pos: marker for data read in reg_read_buf
*
* @regs: a contiguous chunk of memory for DMA register
@@ -271,6 +272,7 @@ struct qcom_nand_controller {
int buf_start;
__le32 *reg_read_buf;
+ dma_addr_t reg_read_buf_phys;
int reg_read_pos;
struct nandc_regs *regs;
@@ -363,6 +365,24 @@ static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
iowrite32(val, nandc->base + offset);
}
+static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
+ bool is_cpu)
+{
+ if (!nandc->props->is_bam)
+ return;
+
+ if (is_cpu)
+ dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_buf_phys,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+ else
+ dma_sync_single_for_device(nandc->dev, nandc->reg_read_buf_phys,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+}
+
static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
{
switch (offset) {
@@ -847,6 +867,7 @@ static void free_descs(struct qcom_nand_controller *nandc)
static void clear_read_regs(struct qcom_nand_controller *nandc)
{
nandc->reg_read_pos = 0;
+ nandc_read_buffer_sync(nandc, false);
}
static void pre_command(struct qcom_nand_host *host, int command)
@@ -876,6 +897,7 @@ static void parse_erase_write_errors(struct qcom_nand_host *host, int command)
int i;
num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
+ nandc_read_buffer_sync(nandc, true);
for (i = 0; i < num_cw; i++) {
u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
@@ -897,6 +919,7 @@ static void post_command(struct qcom_nand_host *host, int command)
switch (command) {
case NAND_CMD_READID:
+ nandc_read_buffer_sync(nandc, true);
memcpy(nandc->data_buffer, nandc->reg_read_buf,
nandc->buf_count);
break;
@@ -1060,6 +1083,7 @@ static int parse_read_errors(struct qcom_nand_host *host, u8 *data_buf,
int i;
buf = (struct read_stats *)nandc->reg_read_buf;
+ nandc_read_buffer_sync(nandc, true);
for (i = 0; i < ecc->steps; i++, buf++) {
u32 flash, buffer, erased_cw;
@@ -1996,6 +2020,16 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
return -ENOMEM;
if (nandc->props->is_bam) {
+ nandc->reg_read_buf_phys =
+ dma_map_single(nandc->dev, nandc->reg_read_buf,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(nandc->dev, nandc->reg_read_buf_phys)) {
+ dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
+ return -EIO;
+ }
+
nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
if (!nandc->tx_chan) {
dev_err(nandc->dev, "failed to request tx channel\n");
@@ -2033,6 +2067,12 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
{
if (nandc->props->is_bam) {
+ if (!dma_mapping_error(nandc->dev, nandc->reg_read_buf_phys))
+ dma_unmap_single(nandc->dev, nandc->reg_read_buf_phys,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+
if (nandc->tx_chan)
dma_release_channel(nandc->tx_chan);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The BAM transaction is the core data structure which will be used
for all the data transfers in QPIC NAND. Since the base layer is
serializing all the NAND requests so allocating BAM transaction
before every transfer will be overhead. The memory for it be
allocated during probe time and before every transfer, it will be
cleared. The BAM transaction contains the array of command
elements, command and data scatter gather list and indexes. For
every transfer, all the resource will be taken from BAM
transaction.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 114 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 114 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f49c3da..fc29c97 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -22,6 +22,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/delay.h>
+#include <linux/dma/qcom_bam_dma.h>
/* NANDc reg offsets */
#define NAND_FLASH_CMD 0x00
@@ -172,6 +173,45 @@
#define ECC_BCH_4BIT BIT(2)
#define ECC_BCH_8BIT BIT(3)
+#define QPIC_PER_CW_CMD_ELEMENTS 32
+#define QPIC_PER_CW_CMD_SGL 32
+#define QPIC_PER_CW_DATA_SGL 8
+
+/*
+ * This data type corresponds to the BAM transaction which will be used for all
+ * NAND transfers.
+ * @bam_ce - the array of bam command elements
+ * @cmd_sgl - sgl for nand bam command pipe
+ * @data_sgl - sgl for nand bam consumer/producer pipe
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl request
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ * for current sgl. It will be used for size calculation
+ * for current sgl
+ * @cmd_sgl_pos - current index in command sgl.
+ * @tx_sgl_pos - current index in data sgl for tx.
+ * @rx_sgl_pos - current index in data sgl for rx.
+ */
+struct bam_transaction {
+ struct bam_cmd_element *bam_ce;
+ struct scatterlist *cmd_sgl;
+ struct scatterlist *data_sgl;
+ u32 bam_ce_pos;
+ u32 bam_ce_start;
+ u32 cmd_sgl_pos;
+ u32 cmd_sgl_start;
+ u32 tx_sgl_pos;
+ u32 tx_sgl_start;
+ u32 rx_sgl_pos;
+ u32 rx_sgl_start;
+};
+
+/*
+ * This data type corresponds to the nand dma descriptor
+ * @list - list for desc_info
+ * @dir - DMA transfer direction
+ * @sgl - sgl which will be used for single sgl dma descriptor
+ * @dma_desc - low level dma engine descriptor
+ */
struct desc_info {
struct list_head node;
@@ -238,6 +278,8 @@ struct nandc_regs {
* @cmd1/vld: some fixed controller register values
* @props: properties of current NAND controller IP,
* initialized via DT match data
+ * @max_cwperpage: maximum qpic codeword required. calcualted
+ * from all nand device pagesize
*/
struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -265,11 +307,13 @@ struct qcom_nand_controller {
};
struct list_head desc_list;
+ struct bam_transaction *bam_txn;
u8 *data_buffer;
int buf_size;
int buf_count;
int buf_start;
+ unsigned int max_cwperpage;
__le32 *reg_read_buf;
dma_addr_t reg_read_buf_phys;
@@ -342,6 +386,50 @@ struct qcom_props {
bool is_bam;
};
+/* Frees the BAM transaction memory */
+static void free_bam_transaction(struct qcom_nand_controller *nandc)
+{
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ devm_kfree(nandc->dev, bam_txn);
+}
+
+/* Allocates and Initializes the BAM transaction */
+static struct bam_transaction *
+alloc_bam_transaction(struct qcom_nand_controller *nandc)
+{
+ struct bam_transaction *bam_txn;
+ size_t bam_txn_size;
+ unsigned int num_cw = nandc->max_cwperpage;
+ void *bam_txn_buf;
+
+ bam_txn_size =
+ sizeof(*bam_txn) + num_cw *
+ ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
+ (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+ (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
+
+ bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
+ if (!bam_txn_buf)
+ return NULL;
+
+ bam_txn = bam_txn_buf;
+ bam_txn_buf += sizeof(*bam_txn);
+
+ bam_txn->bam_ce = bam_txn_buf;
+ bam_txn_buf +=
+ sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
+
+ bam_txn->cmd_sgl = bam_txn_buf;
+ bam_txn_buf +=
+ sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_SGL * num_cw;
+
+ bam_txn->data_sgl = bam_txn_buf;
+ nandc->max_cwperpage = num_cw;
+
+ return bam_txn;
+}
+
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
{
return container_of(chip, struct qcom_nand_host, chip);
@@ -1913,6 +2001,8 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
cwperpage = mtd->writesize / ecc->size;
+ nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
+ cwperpage);
/*
* DATA_UD_BYTES varies based on whether the read/write command protects
@@ -2047,6 +2137,20 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
dev_err(nandc->dev, "failed to request cmd channel\n");
return -ENODEV;
}
+
+ /*
+ * Initially allocate BAM transaction to read ONFI param page.
+ * After detecting all the devices, this BAM transaction will
+ * be freed and the next BAM tranasction will be allocated with
+ * maximum codeword size
+ */
+ nandc->max_cwperpage = 1;
+ nandc->bam_txn = alloc_bam_transaction(nandc);
+ if (!nandc->bam_txn) {
+ dev_err(nandc->dev,
+ "failed to allocate bam transaction\n");
+ return -ENOMEM;
+ }
} else {
nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
if (!nandc->chan) {
@@ -2202,6 +2306,16 @@ static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
if (list_empty(&nandc->host_list))
return -ENODEV;
+ if (nandc->props->is_bam) {
+ free_bam_transaction(nandc);
+ nandc->bam_txn = alloc_bam_transaction(nandc);
+ if (!nandc->bam_txn) {
+ dev_err(nandc->dev,
+ "failed to allocate bam transaction\n");
+ return -ENOMEM;
+ }
+ }
+
list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
ret = qcom_nand_mtd_register(nandc, host, child);
if (ret) {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
1. prepare_bam_async_desc is the function which will call
all the DMA API’s. It will fetch the outstanding scatter gather
list for passed channel and will do the DMA descriptor formation.
The DMA flag is dependent upon the type of channel.
2. For ADM DMA, the descriptor is being formed for every DMA
request so its sgl count will be always 1 while in BAM DMA, the
clubbing of descriptor is being done to increase throughput.
3. ADM uses only one channel while in BAM, data descriptors
will be submitted to tx channel (for write) or rx channel
(for read) and all the registers read/write descriptors in
command channel.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 143 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 130 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index fc29c97..589108b 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -209,14 +209,23 @@ struct bam_transaction {
* This data type corresponds to the nand dma descriptor
* @list - list for desc_info
* @dir - DMA transfer direction
- * @sgl - sgl which will be used for single sgl dma descriptor
+ * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
+ * ADM
+ * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
+ * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
* @dma_desc - low level dma engine descriptor
*/
struct desc_info {
struct list_head node;
enum dma_data_direction dir;
- struct scatterlist sgl;
+ union {
+ struct scatterlist adm_sgl;
+ struct {
+ struct scatterlist *bam_sgl;
+ int sgl_cnt;
+ };
+ };
struct dma_async_tx_descriptor *dma_desc;
};
@@ -580,9 +589,77 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
}
-static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
- int reg_off, const void *vaddr, int size,
- bool flow_control)
+/*
+ * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
+ * for BAM. This descriptor will be added in the NAND DMA descriptor queue
+ * which will be submitted to DMA engine.
+ */
+static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
+ struct dma_chan *chan,
+ unsigned long flags)
+{
+ struct desc_info *desc;
+ struct scatterlist *sgl;
+ unsigned int sgl_cnt;
+ int ret;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+ enum dma_transfer_direction dir_eng;
+ struct dma_async_tx_descriptor *dma_desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ if (chan == nandc->cmd_chan) {
+ sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
+ sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
+ bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
+ dir_eng = DMA_MEM_TO_DEV;
+ desc->dir = DMA_TO_DEVICE;
+ } else if (chan == nandc->tx_chan) {
+ sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
+ sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
+ bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
+ dir_eng = DMA_MEM_TO_DEV;
+ desc->dir = DMA_TO_DEVICE;
+ } else {
+ sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
+ sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
+ bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
+ desc->dir = DMA_FROM_DEVICE;
+ dir_eng = DMA_DEV_TO_MEM;
+ }
+
+ sg_mark_end(sgl + sgl_cnt - 1);
+ ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
+ if (ret == 0) {
+ dev_err(nandc->dev, "failure in mapping desc\n");
+ kfree(desc);
+ return -ENOMEM;
+ }
+
+ desc->sgl_cnt = sgl_cnt;
+ desc->bam_sgl = sgl;
+
+ dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
+ flags);
+
+ if (!dma_desc) {
+ dev_err(nandc->dev, "failure in prep desc\n");
+ kfree(desc);
+ return -EINVAL;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ list_add_tail(&desc->node, &nandc->desc_list);
+
+ return 0;
+}
+
+static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
+ int reg_off, const void *vaddr, int size,
+ bool flow_control)
{
struct desc_info *desc;
struct dma_async_tx_descriptor *dma_desc;
@@ -595,7 +672,7 @@ static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
if (!desc)
return -ENOMEM;
- sgl = &desc->sgl;
+ sgl = &desc->adm_sgl;
sg_init_one(sgl, vaddr, size);
@@ -671,7 +748,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
nandc->reg_read_pos += num_regs;
- return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
+ return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
}
/*
@@ -702,7 +779,8 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
size = num_regs * sizeof(u32);
- return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
+ return prep_adm_dma_desc(nandc, false, first, vaddr, size,
+ flow_control);
}
/*
@@ -716,7 +794,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
const u8 *vaddr, int size)
{
- return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
+ return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
}
/*
@@ -730,7 +808,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
const u8 *vaddr, int size)
{
- return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
+ return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
}
/*
@@ -930,12 +1008,44 @@ static int submit_descs(struct qcom_nand_controller *nandc)
{
struct desc_info *desc;
dma_cookie_t cookie = 0;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+ int r;
+
+ if (nandc->props->is_bam) {
+ if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
+ r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
+ if (r)
+ return r;
+ }
+
+ if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
+ r = prepare_bam_async_desc(nandc, nandc->tx_chan,
+ DMA_PREP_INTERRUPT);
+ if (r)
+ return r;
+ }
+
+ if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
+ r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
+ DMA_PREP_CMD);
+ if (r)
+ return r;
+ }
+ }
list_for_each_entry(desc, &nandc->desc_list, node)
cookie = dmaengine_submit(desc->dma_desc);
- if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
- return -ETIMEDOUT;
+ if (nandc->props->is_bam) {
+ dma_async_issue_pending(nandc->tx_chan);
+ dma_async_issue_pending(nandc->rx_chan);
+
+ if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
+ return -ETIMEDOUT;
+ } else {
+ if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
+ return -ETIMEDOUT;
+ }
return 0;
}
@@ -946,7 +1056,14 @@ static void free_descs(struct qcom_nand_controller *nandc)
list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
list_del(&desc->node);
- dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
+
+ if (nandc->props->is_bam)
+ dma_unmap_sg(nandc->dev, desc->bam_sgl,
+ desc->sgl_cnt, desc->dir);
+ else
+ dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
+ desc->dir);
+
kfree(desc);
}
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 120 ++++++++++++++++++++++++------------------
1 file changed, 68 insertions(+), 52 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 589108b..8a6034f 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -177,6 +177,14 @@
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
+/* Flags used for BAM DMA desc preparation*/
+/* Don't set the EOT in current tx sgl */
+#define NAND_BAM_NO_EOT BIT(0)
+/* Set the NWD flag in current sgl */
+#define NAND_BAM_NWD BIT(1)
+/* Finish writing in the current sgl and start writing in another sgl */
+#define NAND_BAM_NEXT_SGL BIT(2)
+
/*
* This data type corresponds to the BAM transaction which will be used for all
* NAND transfers.
@@ -735,7 +743,7 @@ static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
* @num_regs: number of registers to read
*/
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs)
+ int num_regs, unsigned int flags)
{
bool flow_control = false;
void *vaddr;
@@ -759,7 +767,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
* @num_regs: number of registers to write
*/
static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs)
+ int num_regs, unsigned int flags)
{
bool flow_control = false;
struct nandc_regs *regs = nandc->regs;
@@ -771,6 +779,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
if (first == NAND_FLASH_CMD)
flow_control = true;
+ if (first == NAND_EXEC_CMD)
+ flags |= NAND_BAM_NWD;
+
if (first == NAND_DEV_CMD1_RESTORE)
first = NAND_DEV_CMD1;
@@ -792,7 +803,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
* @size: DMA transaction size in bytes
*/
static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
- const u8 *vaddr, int size)
+ const u8 *vaddr, int size, unsigned int flags)
{
return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
}
@@ -806,7 +817,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
* @size: DMA transaction size in bytes
*/
static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
- const u8 *vaddr, int size)
+ const u8 *vaddr, int size, unsigned int flags)
{
return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
}
@@ -817,9 +828,9 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
*/
static void config_nand_page_read(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_ADDR0, 2);
- write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
+ write_reg_dma(nandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
}
/*
@@ -828,11 +839,12 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
*/
static void config_nand_cw_read(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_FLASH_CMD, 1);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
- read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
+ read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
+ NAND_BAM_NEXT_SGL);
}
/*
@@ -851,9 +863,10 @@ static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
*/
static void config_nand_page_write(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_ADDR0, 2);
- write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
+ write_reg_dma(nandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
+ NAND_BAM_NEXT_SGL);
}
/*
@@ -862,13 +875,13 @@ static void config_nand_page_write(struct qcom_nand_controller *nandc)
*/
static void config_nand_cw_write(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_FLASH_CMD, 1);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
- write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
- write_reg_dma(nandc, NAND_READ_STATUS, 1);
+ write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
+ write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
}
/*
@@ -916,8 +929,8 @@ static int nandc_param(struct qcom_nand_host *host)
nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
- write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
- write_reg_dma(nandc, NAND_DEV_CMD1, 1);
+ write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
+ write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
nandc->buf_count = 512;
memset(nandc->data_buffer, 0xff, nandc->buf_count);
@@ -925,11 +938,11 @@ static int nandc_param(struct qcom_nand_host *host)
config_nand_single_cw_page_read(nandc);
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
- nandc->buf_count);
+ nandc->buf_count, 0);
/* restore CMD1 and VLD regs */
- write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
- write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
+ write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
+ write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
return 0;
}
@@ -951,14 +964,14 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
- write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
- write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
- write_reg_dma(nandc, NAND_READ_STATUS, 1);
+ write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
+ write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
return 0;
}
@@ -978,10 +991,10 @@ static int read_id(struct qcom_nand_host *host, int column)
nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
- write_reg_dma(nandc, NAND_FLASH_CMD, 4);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_READ_ID, 1);
+ read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
return 0;
}
@@ -995,10 +1008,10 @@ static int reset(struct qcom_nand_host *host)
nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
- write_reg_dma(nandc, NAND_FLASH_CMD, 1);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
return 0;
}
@@ -1395,7 +1408,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
if (data_buf)
read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
- data_size);
+ data_size, 0);
/*
* when ecc is enabled, the controller doesn't read the real
@@ -1411,7 +1424,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
*oob_buf++ = 0xff;
read_data_dma(nandc, FLASH_BUF_ACC + data_size,
- oob_buf, oob_size);
+ oob_buf, oob_size, 0);
}
if (data_buf)
@@ -1453,7 +1466,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
config_nand_single_cw_page_read(nandc);
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
+ read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
ret = submit_descs(nandc);
if (ret)
@@ -1522,19 +1535,19 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
config_nand_cw_read(nandc);
- read_data_dma(nandc, reg_off, data_buf, data_size1);
+ read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
reg_off += data_size1;
data_buf += data_size1;
- read_data_dma(nandc, reg_off, oob_buf, oob_size1);
+ read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
reg_off += oob_size1;
oob_buf += oob_size1;
- read_data_dma(nandc, reg_off, data_buf, data_size2);
+ read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
reg_off += data_size2;
data_buf += data_size2;
- read_data_dma(nandc, reg_off, oob_buf, oob_size2);
+ read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
oob_buf += oob_size2;
}
@@ -1601,7 +1614,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
}
- write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
+ write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
+ i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
/*
* when ECC is enabled, we don't really need to write anything
@@ -1614,7 +1628,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
oob_buf += host->bbm_size;
write_data_dma(nandc, FLASH_BUF_ACC + data_size,
- oob_buf, oob_size);
+ oob_buf, oob_size, 0);
}
config_nand_cw_write(nandc);
@@ -1669,19 +1683,20 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
- write_data_dma(nandc, reg_off, data_buf, data_size1);
+ write_data_dma(nandc, reg_off, data_buf, data_size1,
+ NAND_BAM_NO_EOT);
reg_off += data_size1;
data_buf += data_size1;
- write_data_dma(nandc, reg_off, oob_buf, oob_size1);
+ write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
reg_off += oob_size1;
oob_buf += oob_size1;
- write_data_dma(nandc, reg_off, data_buf, data_size2);
+ write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
reg_off += data_size2;
data_buf += data_size2;
- write_data_dma(nandc, reg_off, oob_buf, oob_size2);
+ write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
oob_buf += oob_size2;
config_nand_cw_write(nandc);
@@ -1735,8 +1750,8 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
- write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
- data_size + oob_size);
+ write_data_dma(nandc, FLASH_BUF_ACC,
+ nandc->data_buffer, data_size + oob_size, 0);
config_nand_cw_write(nandc);
ret = submit_descs(nandc);
@@ -1820,7 +1835,8 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
- write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
+ write_data_dma(nandc, FLASH_BUF_ACC,
+ nandc->data_buffer, host->cw_size, 0);
config_nand_cw_write(nandc);
ret = submit_descs(nandc);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The NAND controller returns ECC failure during read of completely
erased codeword. The NAND controller has hardware functionality
to detect erased codeword in case of BCH ECC algorithm. The
NAND_ERASED_CW_DETECT_CFG register controls the Erased
Codeword/Page detection controller. This register should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index b9e0eec..89f6a89 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -196,6 +196,11 @@
#define NAND_BAM_NWD BIT(1)
/* Finish writing in the current sgl and start writing in another sgl */
#define NAND_BAM_NEXT_SGL BIT(2)
+/*
+ * Erased codeword status is being used two times in single transfer so this
+ * flag will determine the current value of erased codeword status register
+ */
+#define NAND_ERASED_CW_SET BIT(4)
/*
* This data type corresponds to the BAM transaction which will be used for all
@@ -279,6 +284,8 @@ struct nandc_regs {
__le32 read_location2;
__le32 read_location3;
+ __le32 erased_cw_detect_cfg_clr;
+ __le32 erased_cw_detect_cfg_set;
};
/*
@@ -815,6 +822,13 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
if (first == NAND_FLASH_CMD)
flow_control = true;
+ if (first == NAND_ERASED_CW_DETECT_CFG) {
+ if (flags & NAND_ERASED_CW_SET)
+ vaddr = ®s->erased_cw_detect_cfg_set;
+ else
+ vaddr = ®s->erased_cw_detect_cfg_clr;
+ }
+
if (first == NAND_EXEC_CMD)
flags |= NAND_BAM_NWD;
@@ -867,6 +881,9 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
}
/*
@@ -2268,9 +2285,13 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
host->clrflashstatus = FS_READY_BSY_N;
host->clrreadstatus = 0xc0;
+ nandc->regs->erased_cw_detect_cfg_clr =
+ cpu_to_le32(CLR_ERASED_PAGE_DET);
+ nandc->regs->erased_cw_detect_cfg_set =
+ cpu_to_le32(SET_ERASED_PAGE_DET);
dev_dbg(nandc->dev,
- "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
+ "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg,
host->cw_size, host->cw_data, ecc->strength, ecc->bytes,
cwperpage);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation function which will be used
only by BAM DMA for forming the data SGL’s.
3. Add clear BAM transaction and call it before every new request
4. Check DMA mode for ADM or BAM and call the appropriate
descriptor formation function.
5. Enable the BAM in NAND_CTRL.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 197 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 180 insertions(+), 17 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 89f6a89..d0e7b9f 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -156,6 +156,9 @@
#define FETCH_ID 0xb
#define RESET_DEVICE 0xd
+/* NAND_CTRL bits */
+#define BAM_MODE_EN BIT(0)
+
/* Value for NAND_DEV_CMD_VLD */
#define NAND_DEV_CMD_VLD_VAL 0x1d
@@ -185,6 +188,14 @@
(offset << READ_LOCATION_OFFSET) | (size << READ_LOCATION_SIZE) |\
(is_last << READ_LOCATION_LAST))
+/* Returns the dma address for reg read buffer */
+#define REG_BUF_DMA_ADDR(chip, vaddr) \
+ ((chip)->reg_read_buf_phys + \
+ ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
+
+/* Returns the NAND register physical address */
+#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
+
#define QPIC_PER_CW_CMD_ELEMENTS 32
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
@@ -296,7 +307,8 @@ struct nandc_regs {
* controller
* @dev: parent device
* @base: MMIO base
- * @base_dma: physical base address of controller registers
+ * @base_phys: physical base address of controller registers
+ * @base_dma: dma base address of controller registers
* @core_clk: controller clock
* @aon_clk: another controller clock
*
@@ -329,6 +341,7 @@ struct qcom_nand_controller {
struct device *dev;
void __iomem *base;
+ phys_addr_t base_phys;
dma_addr_t base_dma;
struct clk *core_clk;
@@ -471,6 +484,29 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
return bam_txn;
}
+/* Clears the BAM transaction indexes */
+static void clear_bam_transaction(struct qcom_nand_controller *nandc)
+{
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ if (!nandc->props->is_bam)
+ return;
+
+ bam_txn->bam_ce_pos = 0;
+ bam_txn->bam_ce_start = 0;
+ bam_txn->cmd_sgl_pos = 0;
+ bam_txn->cmd_sgl_start = 0;
+ bam_txn->tx_sgl_pos = 0;
+ bam_txn->tx_sgl_start = 0;
+ bam_txn->rx_sgl_pos = 0;
+ bam_txn->rx_sgl_start = 0;
+
+ sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_CMD_SGL);
+ sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_DATA_SGL);
+}
+
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
{
return container_of(chip, struct qcom_nand_host, chip);
@@ -708,6 +744,101 @@ static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
return 0;
}
+/*
+ * Prepares the command descriptor for BAM DMA which will be used for NAND
+ * register reads and writes. The command descriptor requires the command
+ * to be formed in command element type so this function uses the command
+ * element from bam transaction ce array and fills the same with required
+ * data. A single SGL can contain multiple command elements so
+ * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
+ * after the current command element.
+ */
+static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
+ int reg_off, const void *vaddr,
+ int size, unsigned int flags)
+{
+ int bam_ce_size;
+ int i, ret;
+ struct bam_cmd_element *bam_ce_buffer;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
+
+ /* fill the command desc */
+ for (i = 0; i < size; i++) {
+ if (read)
+ bam_prep_ce(&bam_ce_buffer[i],
+ NAND_REG_PHYS(nandc, reg_off + 4 * i),
+ BAM_READ_COMMAND,
+ REG_BUF_DMA_ADDR(nandc,
+ (__le32 *)vaddr + i));
+ else
+ bam_prep_ce_le32(&bam_ce_buffer[i],
+ NAND_REG_PHYS(nandc, reg_off + 4 * i),
+ BAM_WRITE_COMMAND,
+ *((__le32 *)vaddr + i));
+ }
+
+ bam_txn->bam_ce_pos += size;
+
+ /* use the separate sgl after this command */
+ if (flags & NAND_BAM_NEXT_SGL) {
+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
+ bam_ce_size = (bam_txn->bam_ce_pos -
+ bam_txn->bam_ce_start) *
+ sizeof(struct bam_cmd_element);
+ sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
+ bam_ce_buffer, bam_ce_size);
+ bam_txn->cmd_sgl_pos++;
+ bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
+
+ if (flags & NAND_BAM_NWD) {
+ ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
+ DMA_PREP_FENCE |
+ DMA_PREP_CMD);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * Prepares the data descriptor for BAM DMA which will be used for NAND
+ * data reads and writes.
+ */
+static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
+ const void *vaddr,
+ int size, unsigned int flags)
+{
+ int ret;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ if (read) {
+ sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
+ vaddr, size);
+ bam_txn->rx_sgl_pos++;
+ } else {
+ sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
+ vaddr, size);
+ bam_txn->tx_sgl_pos++;
+
+ /*
+ * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
+ * is not set, form the DMA descriptor
+ */
+ if (!(flags & NAND_BAM_NO_EOT)) {
+ ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
+ DMA_PREP_INTERRUPT);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
int reg_off, const void *vaddr, int size,
bool flow_control)
@@ -790,16 +921,19 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
{
bool flow_control = false;
void *vaddr;
- int size;
- if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
- flow_control = true;
-
- size = num_regs * sizeof(u32);
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
nandc->reg_read_pos += num_regs;
- return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
+ num_regs, flags);
+
+ if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
+ flow_control = true;
+
+ return prep_adm_dma_desc(nandc, true, first, vaddr,
+ num_regs * sizeof(u32), flow_control);
}
/*
@@ -815,13 +949,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
bool flow_control = false;
struct nandc_regs *regs = nandc->regs;
void *vaddr;
- int size;
vaddr = offset_to_nandc_reg(regs, first);
- if (first == NAND_FLASH_CMD)
- flow_control = true;
-
if (first == NAND_ERASED_CW_DETECT_CFG) {
if (flags & NAND_ERASED_CW_SET)
vaddr = ®s->erased_cw_detect_cfg_set;
@@ -838,10 +968,15 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
if (first == NAND_DEV_CMD_VLD_RESTORE)
first = NAND_DEV_CMD_VLD;
- size = num_regs * sizeof(u32);
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
+ num_regs, flags);
- return prep_adm_dma_desc(nandc, false, first, vaddr, size,
- flow_control);
+ if (first == NAND_FLASH_CMD)
+ flow_control = true;
+
+ return prep_adm_dma_desc(nandc, false, first, vaddr,
+ num_regs * sizeof(u32), flow_control);
}
/*
@@ -855,6 +990,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
const u8 *vaddr, int size, unsigned int flags)
{
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
+
return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
}
@@ -869,6 +1007,9 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
const u8 *vaddr, int size, unsigned int flags)
{
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
+
return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
}
@@ -1046,7 +1187,8 @@ static int read_id(struct qcom_nand_host *host, int column)
nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
nandc_set_reg(nandc, NAND_ADDR0, column);
nandc_set_reg(nandc, NAND_ADDR1, 0);
- nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+ nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
+ nandc->props->is_bam ? 0 : DM_EN);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
@@ -1157,6 +1299,9 @@ static void pre_command(struct qcom_nand_host *host, int command)
host->last_command = command;
clear_read_regs(nandc);
+ if (command == NAND_CMD_RESET || command == NAND_CMD_READID ||
+ command == NAND_CMD_PARAM || command == NAND_CMD_ERASE1)
+ clear_bam_transaction(nandc);
}
/*
@@ -1561,6 +1706,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
data_buf = buf;
oob_buf = oob_required ? chip->oob_poi : NULL;
+ clear_bam_transaction(nandc);
ret = read_page_ecc(host, data_buf, oob_buf);
if (ret) {
dev_err(nandc->dev, "failure to read page\n");
@@ -1586,6 +1732,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
oob_buf = chip->oob_poi;
host->use_ecc = false;
+
+ clear_bam_transaction(nandc);
update_rw_regs(host, ecc->steps, true);
config_nand_page_read(nandc);
@@ -1657,6 +1805,7 @@ static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
int ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
host->use_ecc = true;
set_address(host, 0, page);
@@ -1680,6 +1829,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
int i, ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
data_buf = (u8 *)buf;
oob_buf = chip->oob_poi;
@@ -1745,6 +1895,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
int i, ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
data_buf = (u8 *)buf;
oob_buf = chip->oob_poi;
@@ -1819,11 +1970,13 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
host->use_ecc = true;
+ clear_bam_transaction(nandc);
ret = copy_last_cw(host, page);
if (ret)
return ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
/* calculate the data and oob size for the last codeword/step */
data_size = ecc->size - ((ecc->steps - 1) << 2);
@@ -1876,6 +2029,7 @@ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
*/
host->use_ecc = false;
+ clear_bam_transaction(nandc);
ret = copy_last_cw(host, page);
if (ret)
goto err;
@@ -1906,6 +2060,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
int page, ret, status = 0;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
/*
* to mark the BBM as bad, we flash the entire last codeword with 0s.
@@ -2418,12 +2573,19 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
/* one time setup of a few nand controller registers */
static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
{
+ u32 nand_ctrl;
+
/* kill onenand */
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
- /* enable ADM DMA */
- nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+ /* enable ADM or BAM DMA */
+ if (nandc->props->is_bam) {
+ nand_ctrl = nandc_read(nandc, NAND_CTRL);
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ } else {
+ nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+ }
/* save the original values of these registers */
nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
@@ -2608,6 +2770,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
if (IS_ERR(nandc->base))
return PTR_ERR(nandc->base);
+ nandc->base_phys = res->start;
nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
nandc->core_clk = devm_clk_get(dev, "core");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
BAM requires EOT flag should be set only for the
last data write in a codeword.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index d0e7b9f..7a7db6b 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1926,11 +1926,13 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
reg_off += data_size1;
data_buf += data_size1;
- write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
+ write_data_dma(nandc, reg_off, oob_buf, oob_size1,
+ NAND_BAM_NO_EOT);
reg_off += oob_size1;
oob_buf += oob_size1;
- write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
+ write_data_dma(nandc, reg_off, data_buf, data_size2,
+ NAND_BAM_NO_EOT);
reg_off += data_size2;
data_buf += data_size2;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 154 +++++++++++++++++++++++++++---------------
1 file changed, 100 insertions(+), 54 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 7a7db6b..0896e56 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
#include <linux/delay.h>
#include <linux/dma/qcom_bam_dma.h>
-/* NANDc reg offsets */
-#define NAND_FLASH_CMD 0x00
-#define NAND_ADDR0 0x04
-#define NAND_ADDR1 0x08
-#define NAND_FLASH_CHIP_SELECT 0x0c
-#define NAND_EXEC_CMD 0x10
-#define NAND_FLASH_STATUS 0x14
-#define NAND_BUFFER_STATUS 0x18
-#define NAND_DEV0_CFG0 0x20
-#define NAND_DEV0_CFG1 0x24
-#define NAND_DEV0_ECC_CFG 0x28
-#define NAND_DEV1_ECC_CFG 0x2c
-#define NAND_DEV1_CFG0 0x30
-#define NAND_DEV1_CFG1 0x34
-#define NAND_READ_ID 0x40
-#define NAND_READ_STATUS 0x44
-#define NAND_DEV_CMD0 0xa0
-#define NAND_DEV_CMD1 0xa4
-#define NAND_DEV_CMD2 0xa8
-#define NAND_DEV_CMD_VLD 0xac
-#define SFLASHC_BURST_CFG 0xe0
-#define NAND_ERASED_CW_DETECT_CFG 0xe8
-#define NAND_ERASED_CW_DETECT_STATUS 0xec
-#define NAND_EBI2_ECC_BUF_CFG 0xf0
-#define FLASH_BUF_ACC 0x100
-
-#define NAND_CTRL 0xf00
-#define NAND_VERSION 0xf08
-#define NAND_READ_LOCATION_0 0xf20
-#define NAND_READ_LOCATION_1 0xf24
-#define NAND_READ_LOCATION_2 0xf28
-#define NAND_READ_LOCATION_3 0xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#define NAND_DEV_CMD1_RESTORE 0xdead
-#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
-
/* NAND_FLASH_CMD bits */
#define PAGE_ACC BIT(4)
#define LAST_PAGE BIT(5)
@@ -196,6 +159,8 @@
/* Returns the NAND register physical address */
#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
+#define NANDC_FLASH_BUF(nandc) nandc->props->reg_offsets[FLASH_BUF_ACC]
+
#define QPIC_PER_CW_CMD_ELEMENTS 32
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
@@ -213,6 +178,44 @@
*/
#define NAND_ERASED_CW_SET BIT(4)
+/* NANDc reg offsets enumeration */
+enum {
+ NAND_FLASH_CMD,
+ NAND_ADDR0,
+ NAND_ADDR1,
+ NAND_FLASH_CHIP_SELECT,
+ NAND_EXEC_CMD,
+ NAND_FLASH_STATUS,
+ NAND_BUFFER_STATUS,
+ NAND_DEV0_CFG0,
+ NAND_DEV0_CFG1,
+ NAND_DEV0_ECC_CFG,
+ NAND_DEV1_ECC_CFG,
+ NAND_DEV1_CFG0,
+ NAND_DEV1_CFG1,
+ NAND_READ_ID,
+ NAND_READ_STATUS,
+ NAND_DEV_CMD0,
+ NAND_DEV_CMD1,
+ NAND_DEV_CMD2,
+ NAND_DEV_CMD_VLD,
+ SFLASHC_BURST_CFG,
+ NAND_ERASED_CW_DETECT_CFG,
+ NAND_ERASED_CW_DETECT_STATUS,
+ NAND_EBI2_ECC_BUF_CFG,
+ FLASH_BUF_ACC,
+ NAND_CTRL,
+ NAND_VERSION,
+ NAND_READ_LOCATION_0,
+ NAND_READ_LOCATION_1,
+ NAND_READ_LOCATION_2,
+ NAND_READ_LOCATION_3,
+
+ /* dummy register offsets, used by write_reg_dma */
+ NAND_DEV_CMD1_RESTORE,
+ NAND_DEV_CMD_VLD_RESTORE,
+};
+
/*
* This data type corresponds to the BAM transaction which will be used for all
* NAND transfers.
@@ -434,10 +437,46 @@ struct qcom_nand_host {
* among different NAND controller IP's.
* @ecc_modes - ecc mode for NAND
* @is_bam - whether NAND controller is using bam
+ * @reg_offsets: register offset mapping array
*/
struct qcom_props {
u32 ecc_modes;
bool is_bam;
+ const u32 *reg_offsets;
+};
+
+/* Mapping table which contains the actual register offsets */
+static const u32 nandc_reg_offsets[] = {
+ [NAND_FLASH_CMD] = 0x00,
+ [NAND_ADDR0] = 0x04,
+ [NAND_ADDR1] = 0x08,
+ [NAND_FLASH_CHIP_SELECT] = 0x0c,
+ [NAND_EXEC_CMD] = 0x10,
+ [NAND_FLASH_STATUS] = 0x14,
+ [NAND_BUFFER_STATUS] = 0x18,
+ [NAND_DEV0_CFG0] = 0x20,
+ [NAND_DEV0_CFG1] = 0x24,
+ [NAND_DEV0_ECC_CFG] = 0x28,
+ [NAND_DEV1_ECC_CFG] = 0x2c,
+ [NAND_DEV1_CFG0] = 0x30,
+ [NAND_DEV1_CFG1] = 0x34,
+ [NAND_READ_ID] = 0x40,
+ [NAND_READ_STATUS] = 0x44,
+ [NAND_DEV_CMD0] = 0xa0,
+ [NAND_DEV_CMD1] = 0xa4,
+ [NAND_DEV_CMD2] = 0xa8,
+ [NAND_DEV_CMD_VLD] = 0xac,
+ [SFLASHC_BURST_CFG] = 0xe0,
+ [NAND_ERASED_CW_DETECT_CFG] = 0xe8,
+ [NAND_ERASED_CW_DETECT_STATUS] = 0xec,
+ [NAND_EBI2_ECC_BUF_CFG] = 0xf0,
+ [FLASH_BUF_ACC] = 0x100,
+ [NAND_CTRL] = 0xf00,
+ [NAND_VERSION] = 0xf08,
+ [NAND_READ_LOCATION_0] = 0xf20,
+ [NAND_READ_LOCATION_1] = 0xf24,
+ [NAND_READ_LOCATION_2] = 0xf28,
+ [NAND_READ_LOCATION_3] = 0xf2c,
};
/* Frees the BAM transaction memory */
@@ -521,13 +560,13 @@ static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
{
- return ioread32(nandc->base + offset);
+ return ioread32(nandc->base + nandc->props->reg_offsets[offset]);
}
static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
u32 val)
{
- iowrite32(val, nandc->base + offset);
+ iowrite32(val, nandc->base + nandc->props->reg_offsets[offset]);
}
static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
@@ -920,19 +959,20 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
int num_regs, unsigned int flags)
{
bool flow_control = false;
+ u32 reg_offset = nandc->props->reg_offsets[first];
void *vaddr;
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
nandc->reg_read_pos += num_regs;
if (nandc->props->is_bam)
- return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
+ return prep_bam_dma_desc_cmd(nandc, true, reg_offset, vaddr,
num_regs, flags);
if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
flow_control = true;
- return prep_adm_dma_desc(nandc, true, first, vaddr,
+ return prep_adm_dma_desc(nandc, true, reg_offset, vaddr,
num_regs * sizeof(u32), flow_control);
}
@@ -948,6 +988,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
{
bool flow_control = false;
struct nandc_regs *regs = nandc->regs;
+ u32 reg_offset;
void *vaddr;
vaddr = offset_to_nandc_reg(regs, first);
@@ -968,14 +1009,15 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
if (first == NAND_DEV_CMD_VLD_RESTORE)
first = NAND_DEV_CMD_VLD;
+ reg_offset = nandc->props->reg_offsets[first];
if (nandc->props->is_bam)
- return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
+ return prep_bam_dma_desc_cmd(nandc, false, reg_offset, vaddr,
num_regs, flags);
if (first == NAND_FLASH_CMD)
flow_control = true;
- return prep_adm_dma_desc(nandc, false, first, vaddr,
+ return prep_adm_dma_desc(nandc, false, reg_offset, vaddr,
num_regs * sizeof(u32), flow_control);
}
@@ -1136,7 +1178,7 @@ static int nandc_param(struct qcom_nand_host *host)
config_nand_single_cw_page_read(nandc);
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
+ read_data_dma(nandc, NANDC_FLASH_BUF(nandc), nandc->data_buffer,
nandc->buf_count, 0);
/* restore CMD1 and VLD regs */
@@ -1623,7 +1665,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
config_nand_cw_read(nandc);
if (data_buf)
- read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
+ read_data_dma(nandc, NANDC_FLASH_BUF(nandc), data_buf,
data_size, 0);
/*
@@ -1639,7 +1681,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
for (j = 0; j < host->bbm_size; j++)
*oob_buf++ = 0xff;
- read_data_dma(nandc, FLASH_BUF_ACC + data_size,
+ read_data_dma(nandc, NANDC_FLASH_BUF(nandc) + data_size,
oob_buf, oob_size, 0);
}
@@ -1683,7 +1725,8 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
config_nand_single_cw_page_read(nandc);
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
+ read_data_dma(nandc, NANDC_FLASH_BUF(nandc), nandc->data_buffer,
+ size, 0);
ret = submit_descs(nandc);
if (ret)
@@ -1739,7 +1782,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
- int reg_off = FLASH_BUF_ACC;
+ int reg_off = NANDC_FLASH_BUF(nandc);
data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
oob_size1 = host->bbm_size;
@@ -1851,7 +1894,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
}
- write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
+ write_data_dma(nandc, NANDC_FLASH_BUF(nandc), data_buf,
+ data_size,
i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
/*
@@ -1864,8 +1908,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
if (i == (ecc->steps - 1)) {
oob_buf += host->bbm_size;
- write_data_dma(nandc, FLASH_BUF_ACC + data_size,
- oob_buf, oob_size, 0);
+ write_data_dma(nandc, NANDC_FLASH_BUF(nandc) +
+ data_size, oob_buf, oob_size, 0);
}
config_nand_cw_write(nandc);
@@ -1906,7 +1950,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
- int reg_off = FLASH_BUF_ACC;
+ int reg_off = NANDC_FLASH_BUF(nandc);
data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
oob_size1 = host->bbm_size;
@@ -1992,7 +2036,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
- write_data_dma(nandc, FLASH_BUF_ACC,
+ write_data_dma(nandc, NANDC_FLASH_BUF(nandc),
nandc->data_buffer, data_size + oob_size, 0);
config_nand_cw_write(nandc);
@@ -2079,7 +2123,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
- write_data_dma(nandc, FLASH_BUF_ACC,
+ write_data_dma(nandc, NANDC_FLASH_BUF(nandc),
nandc->data_buffer, host->cw_size, 0);
config_nand_cw_write(nandc);
@@ -2838,11 +2882,13 @@ static int qcom_nandc_remove(struct platform_device *pdev)
static const struct qcom_props ebi2_nandc_data = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
+ .reg_offsets = nandc_reg_offsets,
};
static const struct qcom_props qpic_nandc_v1_4_0_data = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
+ .reg_offsets = nandc_reg_offsets,
};
/*
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
A new compatible string has been added for QPIC NAND version 1.5.0.
Since only register offsets are diffferent in version 1.5.0 so no
new dts property is required for QPIC NAND version 1.5.0.
Signed-off-by: Abhishek Sahu <[email protected]>
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 8efaeb0..23bbb79 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -4,6 +4,8 @@ Required properties:
- compatible: must be one of the following:
* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
+ * "qcom,qpic-nandc-v1.5.0" - QPIC NAND v1.5.0 which uses BAM DMA like IPQ8074.
+
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
@@ -94,7 +96,7 @@ nand@1ac00000 {
};
nand@79b0000 {
- compatible = "qcom,qpic-nandc-v1.4.0";
+ compatible = "qcom,qpic-nandc-v1.4.0", "qcom,qpic-nandc-v1.5.0";
reg = <0x79b0000 0x1000>;
clocks = <&gcc GCC_QPIC_CLK>,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data contains the register offset
field which is being initialized with its corresponding register
offsets array. A new compatible string has been added for
version 1.5.0 in BAM mode which uses version 1.5.0 register
offsets.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 52 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 0896e56..52173f1 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -445,8 +445,9 @@ struct qcom_props {
const u32 *reg_offsets;
};
-/* Mapping table which contains the actual register offsets */
-static const u32 nandc_reg_offsets[] = {
+/* Mapping tables which contains the actual register offsets */
+/* NAND controller Version 1.4.0 mapping table */
+static const u32 reg_offsets_v1_4_0[] = {
[NAND_FLASH_CMD] = 0x00,
[NAND_ADDR0] = 0x04,
[NAND_ADDR1] = 0x08,
@@ -479,6 +480,40 @@ struct qcom_props {
[NAND_READ_LOCATION_3] = 0xf2c,
};
+/* NAND controller Version 1.5.0 mapping table */
+static const u32 reg_offsets_v1_5_0[] = {
+ [NAND_FLASH_CMD] = 0x00,
+ [NAND_ADDR0] = 0x04,
+ [NAND_ADDR1] = 0x08,
+ [NAND_FLASH_CHIP_SELECT] = 0x0c,
+ [NAND_EXEC_CMD] = 0x10,
+ [NAND_FLASH_STATUS] = 0x14,
+ [NAND_BUFFER_STATUS] = 0x18,
+ [NAND_DEV0_CFG0] = 0x20,
+ [NAND_DEV0_CFG1] = 0x24,
+ [NAND_DEV0_ECC_CFG] = 0x28,
+ [NAND_DEV1_ECC_CFG] = 0x2c,
+ [NAND_DEV1_CFG0] = 0x30,
+ [NAND_DEV1_CFG1] = 0x34,
+ [NAND_READ_ID] = 0x40,
+ [NAND_READ_STATUS] = 0x44,
+ [NAND_DEV_CMD0] = 0x70a0,
+ [NAND_DEV_CMD1] = 0x70a4,
+ [NAND_DEV_CMD2] = 0x70a8,
+ [NAND_DEV_CMD_VLD] = 0x70ac,
+ [SFLASHC_BURST_CFG] = 0xe0,
+ [NAND_ERASED_CW_DETECT_CFG] = 0xe8,
+ [NAND_ERASED_CW_DETECT_STATUS] = 0xec,
+ [NAND_EBI2_ECC_BUF_CFG] = 0xf0,
+ [FLASH_BUF_ACC] = 0x100,
+ [NAND_CTRL] = 0xf00,
+ [NAND_VERSION] = 0x4f08,
+ [NAND_READ_LOCATION_0] = 0xf20,
+ [NAND_READ_LOCATION_1] = 0xf24,
+ [NAND_READ_LOCATION_2] = 0xf28,
+ [NAND_READ_LOCATION_3] = 0xf2c,
+};
+
/* Frees the BAM transaction memory */
static void free_bam_transaction(struct qcom_nand_controller *nandc)
{
@@ -2882,13 +2917,19 @@ static int qcom_nandc_remove(struct platform_device *pdev)
static const struct qcom_props ebi2_nandc_data = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
- .reg_offsets = nandc_reg_offsets,
+ .reg_offsets = reg_offsets_v1_4_0,
};
static const struct qcom_props qpic_nandc_v1_4_0_data = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
- .reg_offsets = nandc_reg_offsets,
+ .reg_offsets = reg_offsets_v1_4_0,
+};
+
+static const struct qcom_props qpic_nandc_v1_5_0_data = {
+ .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+ .is_bam = true,
+ .reg_offsets = reg_offsets_v1_5_0,
};
/*
@@ -2902,6 +2943,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
{ .compatible = "qcom,qpic-nandc-v1.4.0",
.data = &qpic_nandc_v1_4_0_data,
},
+ { .compatible = "qcom,qpic-nandc-v1.5.0",
+ .data = (void *)&qpic_nandc_v1_5_0_data,
+ },
{}
};
MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
In EBI2, all codeword data will be read in FLASH_BUF_ACC buffer
and ADM will copy the data from source (FLASH_BUF_ACC) to
destination (memory for data read).
In QPIC, there is no FLASH_BUF_ACC and all the codeword data will
held in QPIC BAM FIFO buffers. It provides multiple READ_LOCATION
registers which will be used for copying the data from FIFO to
memory. The READ_LOCATION register will be used to read a
specific amount of data from a specific offset within the flash
buffer. It supports sequential offset requests. Each request is
composed of the following fields:
a. Offset within the flash buffer from which data should be
read
b. Amount of data to be read
c. Flag bit specifying the last read request from the flash
buffer. Following the last read request the NANDc refers to the
buffer as empty.
Signed-off-by: Abhishek Sahu <[email protected]>
---
drivers/mtd/nand/qcom_nandc.c | 72 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8a6034f..b9e0eec 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -54,6 +54,8 @@
#define NAND_VERSION 0xf08
#define NAND_READ_LOCATION_0 0xf20
#define NAND_READ_LOCATION_1 0xf24
+#define NAND_READ_LOCATION_2 0xf28
+#define NAND_READ_LOCATION_3 0xf2c
/* dummy register offsets, used by write_reg_dma */
#define NAND_DEV_CMD1_RESTORE 0xdead
@@ -132,6 +134,11 @@
#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
+/* NAND_READ_LOCATION_n bits */
+#define READ_LOCATION_OFFSET 0
+#define READ_LOCATION_SIZE 16
+#define READ_LOCATION_LAST 31
+
/* Version Mask */
#define NAND_VERSION_MAJOR_MASK 0xf0000000
#define NAND_VERSION_MAJOR_SHIFT 28
@@ -173,6 +180,11 @@
#define ECC_BCH_4BIT BIT(2)
#define ECC_BCH_8BIT BIT(3)
+#define NANDC_SET_READL(nandc, reg, offset, size, is_last) \
+nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
+ (offset << READ_LOCATION_OFFSET) | (size << READ_LOCATION_SIZE) |\
+ (is_last << READ_LOCATION_LAST))
+
#define QPIC_PER_CW_CMD_ELEMENTS 32
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
@@ -262,6 +274,11 @@ struct nandc_regs {
__le32 orig_vld;
__le32 ecc_buf_cfg;
+ __le32 read_location0;
+ __le32 read_location1;
+ __le32 read_location2;
+ __le32 read_location3;
+
};
/*
@@ -521,6 +538,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
return ®s->orig_vld;
case NAND_EBI2_ECC_BUF_CFG:
return ®s->ecc_buf_cfg;
+ case NAND_READ_LOCATION_0:
+ return ®s->read_location0;
+ case NAND_READ_LOCATION_1:
+ return ®s->read_location1;
+ case NAND_READ_LOCATION_2:
+ return ®s->read_location2;
+ case NAND_READ_LOCATION_3:
+ return ®s->read_location3;
default:
return NULL;
}
@@ -562,7 +587,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
{
struct nand_chip *chip = &host->chip;
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
- u32 cmd, cfg0, cfg1, ecc_bch_cfg;
+ u32 cmd, cfg0, cfg1, ecc_bch_cfg, read_location0;
if (read) {
if (host->use_ecc)
@@ -579,12 +604,20 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
cfg1 = host->cfg1;
ecc_bch_cfg = host->ecc_bch_cfg;
+ if (read)
+ read_location0 = (0 << READ_LOCATION_OFFSET) |
+ (host->cw_data << READ_LOCATION_SIZE) |
+ (1 << READ_LOCATION_LAST);
} else {
cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
(num_cw - 1) << CW_PER_PAGE;
cfg1 = host->cfg1_raw;
ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+ if (read)
+ read_location0 = (0 << READ_LOCATION_OFFSET) |
+ (host->cw_size << READ_LOCATION_SIZE) |
+ (1 << READ_LOCATION_LAST);
}
nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
@@ -595,6 +628,9 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
+
+ if (read)
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0, read_location0);
}
/*
@@ -839,6 +875,10 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
*/
static void config_nand_cw_read(struct qcom_nand_controller *nandc)
{
+ if (nandc->props->is_bam)
+ write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
+ NAND_BAM_NEXT_SGL);
+
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
@@ -928,6 +968,7 @@ static int nandc_param(struct qcom_nand_host *host)
nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
+ NANDC_SET_READL(nandc, 0, 0, 512, 1);
write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
@@ -1404,6 +1445,19 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
oob_size = host->ecc_bytes_hw + host->spare_bytes;
}
+ if (nandc->props->is_bam) {
+ if (data_buf && oob_buf) {
+ NANDC_SET_READL(nandc, 0, 0, data_size, 0);
+ NANDC_SET_READL(nandc, 1, data_size,
+ oob_size, 1);
+ } else if (data_buf) {
+ NANDC_SET_READL(nandc, 0, 0, data_size, 1);
+ } else {
+ NANDC_SET_READL(nandc, 0, data_size,
+ oob_size, 1);
+ }
+ }
+
config_nand_cw_read(nandc);
if (data_buf)
@@ -1463,6 +1517,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, true);
+ NANDC_SET_READL(nandc, 0, 0, size, 1);
config_nand_single_cw_page_read(nandc);
@@ -1508,6 +1563,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
u8 *data_buf, *oob_buf;
struct nand_ecc_ctrl *ecc = &chip->ecc;
int i, ret;
+ int read_loc;
data_buf = buf;
oob_buf = chip->oob_poi;
@@ -1533,6 +1589,20 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
+ if (nandc->props->is_bam) {
+ read_loc = 0;
+ NANDC_SET_READL(nandc, 0, read_loc, data_size1, 0);
+ read_loc += data_size1;
+
+ NANDC_SET_READL(nandc, 1, read_loc, oob_size1, 0);
+ read_loc += oob_size1;
+
+ NANDC_SET_READL(nandc, 2, read_loc, data_size2, 0);
+ read_loc += data_size2;
+
+ NANDC_SET_READL(nandc, 3, read_loc, oob_size2, 1);
+ }
+
config_nand_cw_read(nandc);
read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On Wed, 19 Jul 2017 17:18:00 +0530
Abhishek Sahu <[email protected]> wrote:
> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
> while EBI2 NAND uses only single ADM channel.
> 3. CRCI is only required for ADM DMA and its not required for
> QPIC NAND.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> .../devicetree/bindings/mtd/qcom_nandc.txt | 54 ++++++++++++++++++++--
> 1 file changed, 51 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index b24adfe..8efaeb0 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,13 +1,15 @@
> * Qualcomm NAND controller
>
> Required properties:
> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
> - DMA like IPQ8064.
> -
> +- compatible: must be one of the following:
> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
> - reg: MMIO address range
> - clocks: must contain core clock and always on clock
> - clock-names: must contain "core" for the core clock and "aon" for the
> always on clock
> +
> +EBI2 specific properties:
> - dmas: DMA specifier, consisting of a phandle to the ADM DMA
> controller node and the channel number to be used for
> NAND. Refer to dma.txt and qcom_adm.txt for more details
> @@ -18,6 +20,12 @@ Required properties:
> - qcom,data-crci: must contain the ADM data type CRCI block instance
> number specified for the NAND controller on the given
> platform
> +
> +QPIC specific properties:
> +- dmas: DMA specifier, consisting of a phandle to the BAM DMA
> + and the channel number to be used for NAND. Refer to
> + dma.txt, qcom_bam_dma.txt for more details
> +- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
> - #address-cells: <1> - subnodes give the chip-select number
> - #size-cells: <0>
>
> @@ -84,3 +92,43 @@ nand@1ac00000 {
> };
> };
> };
> +
> +nand@79b0000 {
I think I already mentioned I'd prefer to have
nand-controller@xxxx {
> + compatible = "qcom,qpic-nandc-v1.4.0";
> + reg = <0x79b0000 0x1000>;
> +
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>;
> + clock-names = "core", "aon";
> +
> + dmas = <&qpicbam 0>,
> + <&qpicbam 1>,
> + <&qpicbam 2>;
> + dma-names = "tx", "rx", "cmd";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + nandcs@0 {
and
nand@x {
here.
> + reg = <0>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + nand-bus-width = <8>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "boot-nand";
> + reg = <0 0x58a0000>;
> + };
> +
> + partition@58a0000 {
> + label = "fs-nand";
> + reg = <0x58a0000 0x4000000>;
> + };
> + };
> + };
> +};
On 2017-07-20 01:09, Boris Brezillon wrote:
> On Wed, 19 Jul 2017 17:18:00 +0530
> Abhishek Sahu <[email protected]> wrote:
>
>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>> while EBI2 NAND uses only single ADM channel.
>> 3. CRCI is only required for ADM DMA and its not required for
>> QPIC NAND.
>>
>> Signed-off-by: Abhishek Sahu <[email protected]>
>> ---
>> .../devicetree/bindings/mtd/qcom_nandc.txt | 54
>> ++++++++++++++++++++--
>> 1 file changed, 51 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index b24adfe..8efaeb0 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -1,13 +1,15 @@
>> * Qualcomm NAND controller
>>
>> Required properties:
>> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
>> - DMA like IPQ8064.
>> -
>> +- compatible: must be one of the following:
>> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
>> like IPQ4019.
>> - reg: MMIO address range
>> - clocks: must contain core clock and always on clock
>> - clock-names: must contain "core" for the core clock and "aon" for
>> the
>> always on clock
>> +
>> +EBI2 specific properties:
>> - dmas: DMA specifier, consisting of a phandle to the ADM DMA
>> controller node and the channel number to be used for
>> NAND. Refer to dma.txt and qcom_adm.txt for more details
>> @@ -18,6 +20,12 @@ Required properties:
>> - qcom,data-crci: must contain the ADM data type CRCI block instance
>> number specified for the NAND controller on the given
>> platform
>> +
>> +QPIC specific properties:
>> +- dmas: DMA specifier, consisting of a phandle to the BAM DMA
>> + and the channel number to be used for NAND. Refer to
>> + dma.txt, qcom_bam_dma.txt for more details
>> +- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
>> - #address-cells: <1> - subnodes give the chip-select number
>> - #size-cells: <0>
>>
>> @@ -84,3 +92,43 @@ nand@1ac00000 {
>> };
>> };
>> };
>> +
>> +nand@79b0000 {
>
> I think I already mentioned I'd prefer to have
>
> nand-controller@xxxx {
>
Sorry. I Missed that part. I will change it in v3.
>> + compatible = "qcom,qpic-nandc-v1.4.0";
>> + reg = <0x79b0000 0x1000>;
>> +
>> + clocks = <&gcc GCC_QPIC_CLK>,
>> + <&gcc GCC_QPIC_AHB_CLK>;
>> + clock-names = "core", "aon";
>> +
>> + dmas = <&qpicbam 0>,
>> + <&qpicbam 1>,
>> + <&qpicbam 2>;
>> + dma-names = "tx", "rx", "cmd";
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + nandcs@0 {
>
> and
> nand@x {
>
> here.
>
Will change this also.
>> + reg = <0>;
>> + nand-ecc-strength = <4>;
>> + nand-ecc-step-size = <512>;
>> + nand-bus-width = <8>;
>> +
>> + partitions {
>> + compatible = "fixed-partitions";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + partition@0 {
>> + label = "boot-nand";
>> + reg = <0 0x58a0000>;
>> + };
>> +
>> + partition@58a0000 {
>> + label = "fs-nand";
>> + reg = <0x58a0000 0x4000000>;
>> + };
>> + };
>> + };
>> +};
--
Abhishek Sahu
Hi Abhishek,
[auto build test ERROR on mtd/nand/fixes]
[also build test ERROR on v4.13-rc1 next-20170721]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Abhishek-Sahu/Add-QCOM-QPIC-NAND-support/20170721-103138
base: git://git.infradead.org/linux-mtd.git nand/fixes
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
>> drivers/mtd//nand/qcom_nandc.c:25:36: fatal error: linux/dma/qcom_bam_dma.h: No such file or directory
#include <linux/dma/qcom_bam_dma.h>
^
compilation terminated.
vim +25 drivers/mtd//nand/qcom_nandc.c
> 25 #include <linux/dma/qcom_bam_dma.h>
26
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
On Wed, Jul 19, 2017 at 05:17:54PM +0530, Abhishek Sahu wrote:
> Currently the compatible “qcom,nandcs” is being used for each
> connected NAND device to support for multiple NAND devices in the
> same bus. The same thing can be achieved by looking reg property
> for each sub nodes which contains the chip select number so this
> patch removes the use of “qcom,nandcs” for specifying NAND device
> sub nodes.
>
> Since there is no user for this driver currently in so
> changing compatible string is safe.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 --
> 1 file changed, 2 deletions(-)
Acked-by: Rob Herring <[email protected]>
On Wed, Jul 19, 2017 at 05:17:52PM +0530, Abhishek Sahu wrote:
> The current compatible string “qcom,ipq806x-nand" implies that
> the driver is specific to IPQ806x. This driver can be used by
> any chip which uses EBI2 NAND controller so changed the
> compatible string to “qcom,ebi2-nandc” to give it more generic
> name.
>
> Since there is no user for this driver currently in so
> changing compatible string is safe.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 70dd511..4511918 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,7 +1,9 @@
> * Qualcomm NAND controller
>
> Required properties:
> -- compatible: should be "qcom,ipq806x-nand"
> +- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
> + DMA like IPQ8064.
Compatible strings are supposed to be specific to the SoC. The old one
wasn't quite and the new one moves in the wrong direction.
Rob
On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
> while EBI2 NAND uses only single ADM channel.
> 3. CRCI is only required for ADM DMA and its not required for
> QPIC NAND.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> .../devicetree/bindings/mtd/qcom_nandc.txt | 54 ++++++++++++++++++++--
> 1 file changed, 51 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index b24adfe..8efaeb0 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,13 +1,15 @@
> * Qualcomm NAND controller
>
> Required properties:
> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
> - DMA like IPQ8064.
> -
> +- compatible: must be one of the following:
> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
compatible strings.
Rob
On 2017-07-25 00:47, Rob Herring wrote:
> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>> while EBI2 NAND uses only single ADM channel.
>> 3. CRCI is only required for ADM DMA and its not required for
>> QPIC NAND.
>>
>> Signed-off-by: Abhishek Sahu <[email protected]>
>> ---
>> .../devicetree/bindings/mtd/qcom_nandc.txt | 54
>> ++++++++++++++++++++--
>> 1 file changed, 51 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index b24adfe..8efaeb0 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -1,13 +1,15 @@
>> * Qualcomm NAND controller
>>
>> Required properties:
>> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
>> - DMA like IPQ8064.
>> -
>> +- compatible: must be one of the following:
>> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
>> like IPQ4019.
>
> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
> compatible strings.
We have 3 versions of NAND HW currently.
EBI2,
QPIC version 1.4.0
QPIC version 1.5.0
and multiple Qualcomm SoCs which use any one of these.
The original plan was to have compatible string for NAND version since
same NAND hardware is being in different SoC and SoC dtsi will simply
use its NAND version compatible string like other Qualcomm hardwares
http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
>
> Rob
--
Abhishek Sahu
On 2017-07-26 00:13, Abhishek Sahu wrote:
> On 2017-07-25 00:47, Rob Herring wrote:
>> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
>>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>>> while EBI2 NAND uses only single ADM channel.
>>> 3. CRCI is only required for ADM DMA and its not required for
>>> QPIC NAND.
>>>
>>> Signed-off-by: Abhishek Sahu <[email protected]>
>>> ---
>>> .../devicetree/bindings/mtd/qcom_nandc.txt | 54
>>> ++++++++++++++++++++--
>>> 1 file changed, 51 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>>> index b24adfe..8efaeb0 100644
>>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>>> @@ -1,13 +1,15 @@
>>> * Qualcomm NAND controller
>>>
>>> Required properties:
>>> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses
>>> ADM
>>> - DMA like IPQ8064.
>>> -
>>> +- compatible: must be one of the following:
>>> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>>> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
>>> like IPQ4019.
>>
>> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
>> compatible strings.
>
> We have 3 versions of NAND HW currently.
> EBI2,
> QPIC version 1.4.0
> QPIC version 1.5.0
>
> and multiple Qualcomm SoCs which use any one of these.
>
> The original plan was to have compatible string for NAND version since
> same NAND hardware is being in different SoC and SoC dtsi will simply
> use its NAND version compatible string like other Qualcomm hardwares
>
>
> http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
>
> http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
>
Following are the partial list for NAND controller and supported
SoC
EBI2: IPQ8064, APQ8064, MSM7xx, MDM9x15
QPIC v1.4.0 MDM9x25, MDM9x35, MDM9x45, IPQ4019
QPIC v1.5.0 MDM9x55, IPQ8074
so could we use NAND controller specific compatible strings instead of
SoC
since it will easy to maintain?
>>
>> Rob
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> The configuration for BCH is not correct in the current driver.
> The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the
> BCH ECC in which
>
> 0x1 : BCH_DISABLED
> 0x0 : BCH_ENABLED
>
> But currently host->bch_enabled is being assined to BCH_DISABLED.
s/assined/assigned
Thanks for fixing this up.
Reviewed-by: Archit Taneja <[email protected]>
>
> Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
> Cc: [email protected]
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..bc0408c 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
> *
> * This software is licensed under the terms of the GNU General Public
> * License version 2, as published by the Free Software Foundation, and
> @@ -1893,7 +1893,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> | wide_bus << WIDE_FLASH
> | 1 << DEV0_CFG1_ECC_DISABLE;
>
> - host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
> + host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
> | 0 << ECC_SW_RESET
> | host->cw_data << ECC_NUM_DATA_BYTES
> | 1 << ECC_FORCE_CLK_OPEN
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> The current driver is failing without complete bootchain since
> NAND_DEV_CMD_VLD value is not valid.
>
Reviewed-by: Archit Taneja <[email protected]>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index bc0408c..f3b995d 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -148,6 +148,9 @@
> #define FETCH_ID 0xb
> #define RESET_DEVICE 0xd
>
> +/* Value for NAND_DEV_CMD_VLD */
> +#define NAND_DEV_CMD_VLD_VAL 0x1d
> +
> /*
> * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
> {
> /* kill onenand */
> nandc_write(nandc, SFLASHC_BURST_CFG, 0);
> + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>
> /* enable ADM DMA */
> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> Currently the compatible “qcom,nandcs” is being used for each
> connected NAND device to support for multiple NAND devices in the
> same bus. The same thing can be achieved by looking reg property
> for each sub nodes which contains the chip select number so this
> patch removes the use of “qcom,nandcs” for specifying NAND device
> sub nodes.
>
> Since there is no user for this driver currently in so
> changing compatible string is safe.
Reviewed-by: Archit Taneja <[email protected]>
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 26 ++++++++++++--------------
> 1 file changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 8fa2f0c..110a26a 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -2129,22 +2129,20 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> goto err_setup;
>
> for_each_available_child_of_node(dn, child) {
> - if (of_device_is_compatible(child, "qcom,nandcs")) {
> - host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> - if (!host) {
> - of_node_put(child);
> - ret = -ENOMEM;
> - goto err_cs_init;
> - }
> -
> - ret = qcom_nand_host_init(nandc, host, child);
> - if (ret) {
> - devm_kfree(dev, host);
> - continue;
> - }
> + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> + if (!host) {
> + of_node_put(child);
> + ret = -ENOMEM;
> + goto err_cs_init;
> + }
>
> - list_add_tail(&host->node, &nandc->host_list);
> + ret = qcom_nand_host_init(nandc, host, child);
> + if (ret) {
> + devm_kfree(dev, host);
> + continue;
> }
> +
> + list_add_tail(&host->node, &nandc->host_list);
> }
>
> if (list_empty(&nandc->host_list)) {
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> Each NAND page consist of multiple codewords. Following is
> sequence for NAND page read according to hardware guide.
>
> 1. Program Power-up configuration, page row, page column
> address and flash configuration registers.
> 2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
> codeword.
> 3. Read NAND_FLASH_STATUS for each codeword.
>
> The step 1 should be done once for each page and step 2,3 should
> be done for each codeword.
>
> Currently, all the 3 steps are being done for each codeword which
> is wrong. Now this patch reorganizes read page functions to
> configure page specific register once and per codeword specific
> registers for each NAND ECC step.
Looks good to me.
Reviewed-by: Archit Taneja <[email protected]>
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 37 +++++++++++++++++++++++++++----------
> 1 file changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 110a26a..27ea594 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -605,15 +605,23 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> }
>
> /*
> - * helper to prepare dma descriptors to configure registers needed for reading a
> - * codeword/step in a page
> + * Helper to prepare DMA descriptors for configuring registers
> + * before reading a NAND page.
> */
> -static void config_cw_read(struct qcom_nand_controller *nandc)
> +static void config_nand_page_read(struct qcom_nand_controller *nandc)
> {
> - write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> + write_reg_dma(nandc, NAND_ADDR0, 2);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> +}
>
> +/*
> + * Helper to prepare DMA descriptors for configuring registers
> + * before reading each codeword in NAND page.
> + */
> +static void config_nand_cw_read(struct qcom_nand_controller *nandc)
> +{
> + write_reg_dma(nandc, NAND_FLASH_CMD, 1);
> write_reg_dma(nandc, NAND_EXEC_CMD, 1);
>
> read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
> @@ -621,9 +629,15 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
> }
>
> /*
> - * helpers to prepare dma descriptors used to configure registers needed for
> - * writing a codeword/step in a page
> + * Helper to prepare dma descriptors to configure registers needed for reading a
> + * single codeword in page
> */
> +static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
> +{
> + config_nand_page_read(nandc);
> + config_nand_cw_read(nandc);
> +}
> +
> static void config_cw_write_pre(struct qcom_nand_controller *nandc)
> {
> write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> @@ -692,7 +706,7 @@ static int nandc_param(struct qcom_nand_host *host)
> nandc->buf_count = 512;
> memset(nandc->data_buffer, 0xff, nandc->buf_count);
>
> - config_cw_read(nandc);
> + config_nand_single_cw_page_read(nandc);
>
> read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> nandc->buf_count);
> @@ -1105,6 +1119,8 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
> struct nand_ecc_ctrl *ecc = &chip->ecc;
> int i, ret;
>
> + config_nand_page_read(nandc);
> +
> /* queue cmd descs for each codeword */
> for (i = 0; i < ecc->steps; i++) {
> int data_size, oob_size;
> @@ -1118,7 +1134,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
> oob_size = host->ecc_bytes_hw + host->spare_bytes;
> }
>
> - config_cw_read(nandc);
> + config_nand_cw_read(nandc);
>
> if (data_buf)
> read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> @@ -1178,7 +1194,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
> set_address(host, host->cw_size * (ecc->steps - 1), page);
> update_rw_regs(host, 1, true);
>
> - config_cw_read(nandc);
> + config_nand_single_cw_page_read(nandc);
>
> read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
>
> @@ -1228,6 +1244,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>
> host->use_ecc = false;
> update_rw_regs(host, ecc->steps, true);
> + config_nand_page_read(nandc);
>
> for (i = 0; i < ecc->steps; i++) {
> int data_size1, data_size2, oob_size1, oob_size2;
> @@ -1246,7 +1263,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
> oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
> }
>
> - config_cw_read(nandc);
> + config_nand_cw_read(nandc);
>
> read_data_dma(nandc, reg_off, data_buf, data_size1);
> reg_off += data_size1;
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> Each NAND page consist of multiple codewords. Following is
> sequence for NAND page write according to hardware guide.
>
> 1. Program Power-up configuration, page row, page column
> address and flash configuration registers.
> 2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
> codeword.
> 3. Read NAND_FLASH_STATUS for each codeword.
>
> The step 1 should be done once for each page and step 2,3 should
> be done for each codeword.
>
> Currently, all the 3 steps are being done for each codeword which
> is wrong. Now this patch reorganizes page write functions to
> configure page specific register once and per codeword specific
> registers for each NAND ECC step.
Thanks for fixing this. I'm assuming this has been tested on IPQ806x
too.
Reviewed-by: Archit Taneja <[email protected]>
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 32 ++++++++++++++++++++------------
> 1 file changed, 20 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 27ea594..5b71478 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -638,15 +638,24 @@ static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
> config_nand_cw_read(nandc);
> }
>
> -static void config_cw_write_pre(struct qcom_nand_controller *nandc)
> +/*
> + * Helper to prepare DMA descriptors used to configure registers needed for
> + * before writing a NAND page.
> + */
> +static void config_nand_page_write(struct qcom_nand_controller *nandc)
> {
> - write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> + write_reg_dma(nandc, NAND_ADDR0, 2);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> }
>
> -static void config_cw_write_post(struct qcom_nand_controller *nandc)
> +/*
> + * Helper to prepare DMA descriptors for configuring registers
> + * before writing each codeword in NAND page.
> + */
> +static void config_nand_cw_write(struct qcom_nand_controller *nandc)
> {
> + write_reg_dma(nandc, NAND_FLASH_CMD, 1);
> write_reg_dma(nandc, NAND_EXEC_CMD, 1);
>
> read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> @@ -1329,6 +1338,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>
> host->use_ecc = true;
> update_rw_regs(host, ecc->steps, false);
> + config_nand_page_write(nandc);
>
> for (i = 0; i < ecc->steps; i++) {
> int data_size, oob_size;
> @@ -1342,7 +1352,6 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> oob_size = ecc->bytes;
> }
>
> - config_cw_write_pre(nandc);
>
> write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
>
> @@ -1360,7 +1369,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> oob_buf, oob_size);
> }
>
> - config_cw_write_post(nandc);
> + config_nand_cw_write(nandc);
>
> data_buf += data_size;
> oob_buf += oob_size;
> @@ -1393,6 +1402,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>
> host->use_ecc = false;
> update_rw_regs(host, ecc->steps, false);
> + config_nand_page_write(nandc);
>
> for (i = 0; i < ecc->steps; i++) {
> int data_size1, data_size2, oob_size1, oob_size2;
> @@ -1411,8 +1421,6 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
> oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
> }
>
> - config_cw_write_pre(nandc);
> -
> write_data_dma(nandc, reg_off, data_buf, data_size1);
> reg_off += data_size1;
> data_buf += data_size1;
> @@ -1428,7 +1436,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
> write_data_dma(nandc, reg_off, oob_buf, oob_size2);
> oob_buf += oob_size2;
>
> - config_cw_write_post(nandc);
> + config_nand_cw_write(nandc);
> }
>
> ret = submit_descs(nandc);
> @@ -1478,10 +1486,10 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
> set_address(host, host->cw_size * (ecc->steps - 1), page);
> update_rw_regs(host, 1, false);
>
> - config_cw_write_pre(nandc);
> + config_nand_page_write(nandc);
> write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> data_size + oob_size);
> - config_cw_write_post(nandc);
> + config_nand_cw_write(nandc);
>
> ret = submit_descs(nandc);
>
> @@ -1563,9 +1571,9 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
> set_address(host, host->cw_size * (ecc->steps - 1), page);
> update_rw_regs(host, 1, false);
>
> - config_cw_write_pre(nandc);
> + config_nand_page_write(nandc);
> write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
> - config_cw_write_post(nandc);
> + config_nand_cw_write(nandc);
>
> ret = submit_descs(nandc);
>
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> The memset in clear_read_regs is overhead. All the register data
> will be filled by DMA during NAND operation so making these
> register variables zero is not required.
Yeah, that's a good point.
Reviewed-by: Archit Taneja <[email protected]>
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 5b71478..7ecd0f8 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -826,8 +826,6 @@ static void free_descs(struct qcom_nand_controller *nandc)
> static void clear_read_regs(struct qcom_nand_controller *nandc)
> {
> nandc->reg_read_pos = 0;
> - memset(nandc->reg_read_buf, 0,
> - MAX_REG_RD * sizeof(*nandc->reg_read_buf));
> }
>
> static void pre_command(struct qcom_nand_host *host, int command)
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> This is reorganization of exiting code and will not change any
> functionality. The NAND controller supports multiple NAND device
> with different page size. The subsequent patch allocate memory
> which depends upon the maximum number of codewords so this patch
> reorganizes the NAND device probing. First the ONFI parameter
> page will be read from each connected device followed by MTD
> device registration.
>
Modified the commit message slightly so that it's more clear.
Looks good otherwise.
"The NAND controller can support multiple NAND devices having different
page sizes. Future code will require us to allocate memory based on the
maximum number of codewords among all the devices. We reorganize the NAND
device probing such that the ONFI parameters are first read for each
connected device to identify the maximum number of codewords possible,
and only then proceed with MTD device registration (i.e, call nand_scan_tail
and mtd_device_register).
This is a reorganization of the existing code and will not change
any functionality."
Thanks,
Archit
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 88 +++++++++++++++++++++++++++++--------------
> 1 file changed, 59 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 7ecd0f8..8f9e86c 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -2059,14 +2059,67 @@ static int qcom_nand_host_init(struct qcom_nand_controller *nandc,
> return ret;
>
> ret = qcom_nand_host_setup(host);
> - if (ret)
> - return ret;
> +
> + return ret;
> +}
> +
> +static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
> + struct qcom_nand_host *host,
> + struct device_node *dn)
> +{
> + struct nand_chip *chip = &host->chip;
> + struct mtd_info *mtd = nand_to_mtd(chip);
> + int ret;
>
> ret = nand_scan_tail(mtd);
> if (ret)
> return ret;
>
> - return mtd_device_register(mtd, NULL, 0);
> + ret = mtd_device_register(mtd, NULL, 0);
> + if (ret)
> + nand_cleanup(mtd_to_nand(mtd));
> +
> + return ret;
> +}
> +
> +static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
> +{
> + struct device *dev = nandc->dev;
> + struct device_node *dn = dev->of_node, *child;
> + struct qcom_nand_host *host, *tmp;
> + int ret;
> +
> + for_each_available_child_of_node(dn, child) {
> + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> + if (!host) {
> + of_node_put(child);
> + return -ENOMEM;
> + }
> +
> + ret = qcom_nand_host_init(nandc, host, child);
> + if (ret) {
> + devm_kfree(dev, host);
> + continue;
> + }
> +
> + list_add_tail(&host->node, &nandc->host_list);
> + }
> +
> + if (list_empty(&nandc->host_list))
> + return -ENODEV;
> +
> + list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
> + ret = qcom_nand_mtd_register(nandc, host, child);
> + if (ret) {
> + list_del(&host->node);
> + devm_kfree(dev, host);
> + }
> + }
> +
> + if (list_empty(&nandc->host_list))
> + return -ENODEV;
> +
> + return 0;
> }
>
> /* parse custom DT properties here */
> @@ -2094,10 +2147,8 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
> static int qcom_nandc_probe(struct platform_device *pdev)
> {
> struct qcom_nand_controller *nandc;
> - struct qcom_nand_host *host;
> const void *dev_data;
> struct device *dev = &pdev->dev;
> - struct device_node *dn = dev->of_node, *child;
> struct resource *res;
> int ret;
>
> @@ -2151,33 +2202,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> if (ret)
> goto err_setup;
>
> - for_each_available_child_of_node(dn, child) {
> - host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> - if (!host) {
> - of_node_put(child);
> - ret = -ENOMEM;
> - goto err_cs_init;
> - }
> -
> - ret = qcom_nand_host_init(nandc, host, child);
> - if (ret) {
> - devm_kfree(dev, host);
> - continue;
> - }
> -
> - list_add_tail(&host->node, &nandc->host_list);
> - }
> -
> - if (list_empty(&nandc->host_list)) {
> - ret = -ENODEV;
> - goto err_cs_init;
> - }
> + ret = qcom_probe_nand_devices(nandc);
> + if (ret)
> + goto err_setup;
>
> return 0;
>
> -err_cs_init:
> - list_for_each_entry(host, &nandc->host_list, node)
> - nand_release(nand_to_mtd(&host->chip));
> err_setup:
> clk_disable_unprepare(nandc->aon_clk);
> err_aon_clk:
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> Currently driver data is being assigned directly with ECC modes.
> Now, the plan is to add more NAND controller versions, so
> reorganized the current driver data assignment by creating NAND
> controller properties structure. This will contain all
> properties specific to NAND controller.
>
Reviewed-by: Archit Taneja <[email protected]>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 23 +++++++++++++++++------
> 1 file changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 8f9e86c..3b0ae91 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -235,7 +235,7 @@ struct nandc_regs {
> * writes. contains the register values to be
> * written to controller
> * @cmd1/vld: some fixed controller register values
> - * @ecc_modes: supported ECC modes by the current controller,
> + * @props: properties of current NAND controller IP,
> * initialized via DT match data
> */
> struct qcom_nand_controller {
> @@ -266,7 +266,7 @@ struct qcom_nand_controller {
> struct nandc_regs *regs;
>
> u32 cmd1, vld;
> - u32 ecc_modes;
> + const struct qcom_props *props;
> };
>
> /*
> @@ -319,6 +319,15 @@ struct qcom_nand_host {
> u32 clrreadstatus;
> };
>
> +/*
> + * This data type corresponds to the nand controller properties which varies
> + * among different NAND controller IP's.
> + * @ecc_modes - ecc mode for NAND
> + */
> +struct qcom_props {
> + u32 ecc_modes;
> +};
> +
> static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> {
> return container_of(chip, struct qcom_nand_host, chip);
> @@ -1820,7 +1829,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> * always 10 bytes
> */
> - if (nandc->ecc_modes & ECC_BCH_4BIT) {
> + if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
> /* BCH */
> host->bch_enabled = true;
> ecc_mode = 0;
> @@ -2165,7 +2174,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> return -ENODEV;
> }
>
> - nandc->ecc_modes = (unsigned long)dev_data;
> + nandc->props = dev_data;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> nandc->base = devm_ioremap_resource(dev, res);
> @@ -2234,7 +2243,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> return 0;
> }
>
> -#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
> +static const struct qcom_props ebi2_nandc_data = {
> + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> +};
>
> /*
> * data will hold a struct pointer containing more differences once we support
> @@ -2242,7 +2253,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> */
> static const struct of_device_id qcom_nandc_of_match[] = {
> { .compatible = "qcom,ebi2-nandc",
> - .data = (void *)EBI2_NANDC_ECC_MODES,
> + .data = &ebi2_nandc_data,
> },
> {}
> };
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
s/support/supports
> latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
> registers and programming sequence are same for EBI2 and QPIC
> NAND so the same driver can support QPIC NAND also by adding the
> BAM DMA support. This patch adds the QPIC NAND support in current
> NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
> maps it with different configuration parameter in driver data.
>
Reviewed-by: Archit Taneja <[email protected]>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 3b0ae91..6d24630 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -323,9 +323,11 @@ struct qcom_nand_host {
> * This data type corresponds to the nand controller properties which varies
> * among different NAND controller IP's.
> * @ecc_modes - ecc mode for NAND
> + * @is_bam - whether NAND controller is using bam
> */
> struct qcom_props {
> u32 ecc_modes;
> + bool is_bam;
> };
>
> static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> @@ -2245,6 +2247,12 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>
> static const struct qcom_props ebi2_nandc_data = {
> .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> + .is_bam = false,
> +};
> +
> +static const struct qcom_props qpic_nandc_v1_4_0_data = {
> + .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> + .is_bam = true,
> };
>
> /*
> @@ -2255,6 +2263,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> { .compatible = "qcom,ebi2-nandc",
> .data = &ebi2_nandc_data,
> },
> + { .compatible = "qcom,qpic-nandc-v1.4.0",
> + .data = &qpic_nandc_v1_4_0_data,
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
> 1. QPIC NAND uses 3 BAM channels: command, data tx and data
> rx while EBI2 NAND uses only single ADM channel.
> 2. CRCI is only required for ADM DMA and its not required for
s/its/it's
> QPIC NAND.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 83 +++++++++++++++++++++++++++++++++----------
> 1 file changed, 65 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 6d24630..cb2b245 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -250,9 +250,19 @@ struct qcom_nand_controller {
> struct clk *core_clk;
> struct clk *aon_clk;
>
> - struct dma_chan *chan;
> - unsigned int cmd_crci;
> - unsigned int data_crci;
> + union {
> + struct {
> + struct dma_chan *tx_chan;
> + struct dma_chan *rx_chan;
> + struct dma_chan *cmd_chan;
> + };
> + struct {
> + struct dma_chan *chan;
> + unsigned int cmd_crci;
> + unsigned int data_crci;
> + };
> + };
Could you put comments here explaining one is for EBI2/ADM
and other is for QPIC/BAM? It'll improve the readability a
bit. Otherwise:
Reviewed-by: Archit Taneja <[email protected]>
Thanks,
Archit
> +
> struct list_head desc_list;
>
> u8 *data_buffer;
> @@ -1985,10 +1995,31 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
> if (!nandc->reg_read_buf)
> return -ENOMEM;
>
> - nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> - if (!nandc->chan) {
> - dev_err(nandc->dev, "failed to request slave channel\n");
> - return -ENODEV;
> + if (nandc->props->is_bam) {
> + nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
> + if (!nandc->tx_chan) {
> + dev_err(nandc->dev, "failed to request tx channel\n");
> + return -ENODEV;
> + }
> +
> + nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
> + if (!nandc->rx_chan) {
> + dev_err(nandc->dev, "failed to request rx channel\n");
> + return -ENODEV;
> + }
> +
> + nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
> + if (!nandc->cmd_chan) {
> + dev_err(nandc->dev, "failed to request cmd channel\n");
> + return -ENODEV;
> + }
> + } else {
> + nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> + if (!nandc->chan) {
> + dev_err(nandc->dev,
> + "failed to request slave channel\n");
> + return -ENODEV;
> + }
> }
>
> INIT_LIST_HEAD(&nandc->desc_list);
> @@ -2001,7 +2032,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>
> static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
> {
> - dma_release_channel(nandc->chan);
> + if (nandc->props->is_bam) {
> + if (nandc->tx_chan)
> + dma_release_channel(nandc->tx_chan);
> +
> + if (nandc->rx_chan)
> + dma_release_channel(nandc->rx_chan);
> +
> + if (nandc->cmd_chan)
> + dma_release_channel(nandc->cmd_chan);
> + } else {
> + if (nandc->chan)
> + dma_release_channel(nandc->chan);
> + }
> }
>
> /* one time setup of a few nand controller registers */
> @@ -2140,16 +2183,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
> struct device_node *np = nandc->dev->of_node;
> int ret;
>
> - ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
> - if (ret) {
> - dev_err(nandc->dev, "command CRCI unspecified\n");
> - return ret;
> - }
> + if (!nandc->props->is_bam) {
> + ret = of_property_read_u32(np, "qcom,cmd-crci",
> + &nandc->cmd_crci);
> + if (ret) {
> + dev_err(nandc->dev, "command CRCI unspecified\n");
> + return ret;
> + }
>
> - ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
> - if (ret) {
> - dev_err(nandc->dev, "data CRCI unspecified\n");
> - return ret;
> + ret = of_property_read_u32(np, "qcom,data-crci",
> + &nandc->data_crci);
> + if (ret) {
> + dev_err(nandc->dev, "data CRCI unspecified\n");
> + return ret;
> + }
> }
>
> return 0;
> @@ -2199,7 +2246,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>
> ret = qcom_nandc_alloc(nandc);
> if (ret)
> - return ret;
> + goto err_core_clk;
>
> ret = clk_prepare_enable(nandc->core_clk);
> if (ret)
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 2017-08-02 11:31, Archit Taneja wrote:
> On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
>> Each NAND page consist of multiple codewords. Following is
>> sequence for NAND page write according to hardware guide.
>>
>> 1. Program Power-up configuration, page row, page column
>> address and flash configuration registers.
>> 2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
>> codeword.
>> 3. Read NAND_FLASH_STATUS for each codeword.
>>
>> The step 1 should be done once for each page and step 2,3 should
>> be done for each codeword.
>>
>> Currently, all the 3 steps are being done for each codeword which
>> is wrong. Now this patch reorganizes page write functions to
>> configure page specific register once and per codeword specific
>> registers for each NAND ECC step.
>
> Thanks for fixing this. I'm assuming this has been tested on IPQ806x
> too.
Thanks Archit for reviewing the patches.
Yes. I have tested this in IPQ8064 AP148 board with mtd tests after
applying the ADM DMA patch from list.
>
> Reviewed-by: Archit Taneja <[email protected]>
>
>>
>> Signed-off-by: Abhishek Sahu <[email protected]>
>> ---
>> drivers/mtd/nand/qcom_nandc.c | 32 ++++++++++++++++++++------------
>> 1 file changed, 20 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 27ea594..5b71478 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -638,15 +638,24 @@ static void
>> config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
>> config_nand_cw_read(nandc);
>> }
On 2017-08-02 13:51, Archit Taneja wrote:
> On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
>> This is reorganization of exiting code and will not change any
>> functionality. The NAND controller supports multiple NAND device
>> with different page size. The subsequent patch allocate memory
>> which depends upon the maximum number of codewords so this patch
>> reorganizes the NAND device probing. First the ONFI parameter
>> page will be read from each connected device followed by MTD
>> device registration.
>>
>
> Modified the commit message slightly so that it's more clear.
> Looks good otherwise.
>
> "The NAND controller can support multiple NAND devices having different
> page sizes. Future code will require us to allocate memory based on the
> maximum number of codewords among all the devices. We reorganize the
> NAND
> device probing such that the ONFI parameters are first read for each
> connected device to identify the maximum number of codewords possible,
> and only then proceed with MTD device registration (i.e, call
> nand_scan_tail
> and mtd_device_register).
>
> This is a reorganization of the existing code and will not change
> any functionality."
>
> Thanks,
> Archit
Thanks for making it more clear.
I will amend the commit message in v3.
>
>> Signed-off-by: Abhishek Sahu <[email protected]>
>> ---
>> drivers/mtd/nand/qcom_nandc.c | 88
>> +++++++++++++++++++++++++++++--------------
>> 1 file changed, 59 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 7ecd0f8..8f9e86c 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -2059,14 +2059,67 @@ static int qcom_nand_host_init(struct
>> qcom_nand_controller *nandc,
>> return ret;
>> ret = qcom_nand_host_setup(host);
>> - if (ret)
>> - return ret;
>> +
>> + return ret;
>> +}
>> +
>> +static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
>> + struct qcom_nand_host *host,
>> + struct device_node *dn)
>> +{
>> + struct nand_chip *chip = &host->chip;
>> + struct mtd_info *mtd = nand_to_mtd(chip);
>> + int ret;
>> ret = nand_scan_tail(mtd);
>> if (ret)
>> return ret;
>> - return mtd_device_register(mtd, NULL, 0);
>> + ret = mtd_device_register(mtd, NULL, 0);
>> + if (ret)
>> + nand_cleanup(mtd_to_nand(mtd));
>> +
>> + return ret;
>> +}
>> +
>> +static int qcom_probe_nand_devices(struct qcom_nand_controller
>> *nandc)
>> +{
>> + struct device *dev = nandc->dev;
>> + struct device_node *dn = dev->of_node, *child;
>> + struct qcom_nand_host *host, *tmp;
>> + int ret;
>> +
>> + for_each_available_child_of_node(dn, child) {
>> + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
>> + if (!host) {
>> + of_node_put(child);
>> + return -ENOMEM;
>> + }
>> +
>> + ret = qcom_nand_host_init(nandc, host, child);
>> + if (ret) {
>> + devm_kfree(dev, host);
>> + continue;
>> + }
>> +
>> + list_add_tail(&host->node, &nandc->host_list);
>> + }
>> +
>> + if (list_empty(&nandc->host_list))
>> + return -ENODEV;
>> +
>> + list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
>> + ret = qcom_nand_mtd_register(nandc, host, child);
>> + if (ret) {
>> + list_del(&host->node);
>> + devm_kfree(dev, host);
>> + }
>> + }
>> +
>> + if (list_empty(&nandc->host_list))
>> + return -ENODEV;
>> +
>> + return 0;
>> }
>> /* parse custom DT properties here */
>> @@ -2094,10 +2147,8 @@ static int qcom_nandc_parse_dt(struct
>> platform_device *pdev)
>> static int qcom_nandc_probe(struct platform_device *pdev)
>> {
>> struct qcom_nand_controller *nandc;
>> - struct qcom_nand_host *host;
>> const void *dev_data;
>> struct device *dev = &pdev->dev;
>> - struct device_node *dn = dev->of_node, *child;
>> struct resource *res;
>> int ret;
>> @@ -2151,33 +2202,12 @@ static int qcom_nandc_probe(struct
>> platform_device *pdev)
>> if (ret)
>> goto err_setup;
>> - for_each_available_child_of_node(dn, child) {
>> - host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
>> - if (!host) {
>> - of_node_put(child);
>> - ret = -ENOMEM;
>> - goto err_cs_init;
>> - }
>> -
>> - ret = qcom_nand_host_init(nandc, host, child);
>> - if (ret) {
>> - devm_kfree(dev, host);
>> - continue;
>> - }
>> -
>> - list_add_tail(&host->node, &nandc->host_list);
>> - }
>> -
>> - if (list_empty(&nandc->host_list)) {
>> - ret = -ENODEV;
>> - goto err_cs_init;
>> - }
>> + ret = qcom_probe_nand_devices(nandc);
>> + if (ret)
>> + goto err_setup;
>> return 0;
>> -err_cs_init:
>> - list_for_each_entry(host, &nandc->host_list, node)
>> - nand_release(nand_to_mtd(&host->chip));
>> err_setup:
>> clk_disable_unprepare(nandc->aon_clk);
>> err_aon_clk:
>>
--
Abhishek Sahu
On 2017-08-02 14:11, Archit Taneja wrote:
> On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
>> 1. QPIC NAND uses 3 BAM channels: command, data tx and data
>> rx while EBI2 NAND uses only single ADM channel.
>> 2. CRCI is only required for ADM DMA and its not required for
>
> s/its/it's
I Will fix this.
>
>> QPIC NAND.
>>
>> Signed-off-by: Abhishek Sahu <[email protected]>
>> ---
>> drivers/mtd/nand/qcom_nandc.c | 83
>> +++++++++++++++++++++++++++++++++----------
>> 1 file changed, 65 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 6d24630..cb2b245 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -250,9 +250,19 @@ struct qcom_nand_controller {
>> struct clk *core_clk;
>> struct clk *aon_clk;
>> - struct dma_chan *chan;
>> - unsigned int cmd_crci;
>> - unsigned int data_crci;
>> + union {
>> + struct {
>> + struct dma_chan *tx_chan;
>> + struct dma_chan *rx_chan;
>> + struct dma_chan *cmd_chan;
>> + };
>> + struct {
>> + struct dma_chan *chan;
>> + unsigned int cmd_crci;
>> + unsigned int data_crci;
>> + };
>> + };
>
> Could you put comments here explaining one is for EBI2/ADM
> and other is for QPIC/BAM? It'll improve the readability a
> bit. Otherwise:
Yes that would be better. I will put the comment.
>
> Reviewed-by: Archit Taneja <[email protected]>
>
> Thanks,
> Archit
>
>> +
>> struct list_head desc_list;
>> u8 *data_buffer;
>> @@ -1985,10 +1995,31 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>> if (!nandc->reg_read_buf)
>> return -ENOMEM;
>> - nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
>> - if (!nandc->chan) {
>> - dev_err(nandc->dev, "failed to request slave channel\n");
>> - return -ENODEV;
>> + if (nandc->props->is_bam) {
>> + nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
>> + if (!nandc->tx_chan) {
>> + dev_err(nandc->dev, "failed to request tx channel\n");
>> + return -ENODEV;
>> + }
>> +
>> + nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
>> + if (!nandc->rx_chan) {
>> + dev_err(nandc->dev, "failed to request rx channel\n");
>> + return -ENODEV;
>> + }
>> +
>> + nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
>> + if (!nandc->cmd_chan) {
>> + dev_err(nandc->dev, "failed to request cmd channel\n");
>> + return -ENODEV;
>> + }
>> + } else {
>> + nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
>> + if (!nandc->chan) {
>> + dev_err(nandc->dev,
>> + "failed to request slave channel\n");
>> + return -ENODEV;
>> + }
>> }
>> INIT_LIST_HEAD(&nandc->desc_list);
>> @@ -2001,7 +2032,19 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>> static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>> {
>> - dma_release_channel(nandc->chan);
>> + if (nandc->props->is_bam) {
>> + if (nandc->tx_chan)
>> + dma_release_channel(nandc->tx_chan);
>> +
>> + if (nandc->rx_chan)
>> + dma_release_channel(nandc->rx_chan);
>> +
>> + if (nandc->cmd_chan)
>> + dma_release_channel(nandc->cmd_chan);
>> + } else {
>> + if (nandc->chan)
>> + dma_release_channel(nandc->chan);
>> + }
>> }
>> /* one time setup of a few nand controller registers */
>> @@ -2140,16 +2183,20 @@ static int qcom_nandc_parse_dt(struct
>> platform_device *pdev)
>> struct device_node *np = nandc->dev->of_node;
>> int ret;
>> - ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
>> - if (ret) {
>> - dev_err(nandc->dev, "command CRCI unspecified\n");
>> - return ret;
>> - }
>> + if (!nandc->props->is_bam) {
>> + ret = of_property_read_u32(np, "qcom,cmd-crci",
>> + &nandc->cmd_crci);
>> + if (ret) {
>> + dev_err(nandc->dev, "command CRCI unspecified\n");
>> + return ret;
>> + }
>> - ret = of_property_read_u32(np, "qcom,data-crci",
>> &nandc->data_crci);
>> - if (ret) {
>> - dev_err(nandc->dev, "data CRCI unspecified\n");
>> - return ret;
>> + ret = of_property_read_u32(np, "qcom,data-crci",
>> + &nandc->data_crci);
>> + if (ret) {
>> + dev_err(nandc->dev, "data CRCI unspecified\n");
>> + return ret;
>> + }
>> }
>> return 0;
>> @@ -2199,7 +2246,7 @@ static int qcom_nandc_probe(struct
>> platform_device *pdev)
>> ret = qcom_nandc_alloc(nandc);
>> if (ret)
>> - return ret;
>> + goto err_core_clk;
>> ret = clk_prepare_enable(nandc->core_clk);
>> if (ret)
>>
On Wed, 19 Jul 2017 17:17:50 +0530
Abhishek Sahu <[email protected]> wrote:
> The current driver is failing without complete bootchain since
> NAND_DEV_CMD_VLD value is not valid.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index bc0408c..f3b995d 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -148,6 +148,9 @@
> #define FETCH_ID 0xb
> #define RESET_DEVICE 0xd
>
> +/* Value for NAND_DEV_CMD_VLD */
> +#define NAND_DEV_CMD_VLD_VAL 0x1d
Where does this 0x1d value comes from? Defining a macro instead of
passing 0x1d does not change the fact that this is a magic value :-).
> +
> /*
> * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
> {
> /* kill onenand */
> nandc_write(nandc, SFLASHC_BURST_CFG, 0);
> + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>
> /* enable ADM DMA */
> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
On Wed, 19 Jul 2017 17:17:50 +0530
Abhishek Sahu <[email protected]> wrote:
> The current driver is failing without complete bootchain since
> NAND_DEV_CMD_VLD value is not valid.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
BTW, do you want to backport this fix? Maybe you add Fixes and
Cc-stable tags...
> ---
> drivers/mtd/nand/qcom_nandc.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index bc0408c..f3b995d 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -148,6 +148,9 @@
> #define FETCH_ID 0xb
> #define RESET_DEVICE 0xd
>
> +/* Value for NAND_DEV_CMD_VLD */
> +#define NAND_DEV_CMD_VLD_VAL 0x1d
> +
> /*
> * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
> {
> /* kill onenand */
> nandc_write(nandc, SFLASHC_BURST_CFG, 0);
> + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>
> /* enable ADM DMA */
> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
On Wed, 19 Jul 2017 17:17:49 +0530
Abhishek Sahu <[email protected]> wrote:
> The configuration for BCH is not correct in the current driver.
> The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the
> BCH ECC in which
>
> 0x1 : BCH_DISABLED
> 0x0 : BCH_ENABLED
>
> But currently host->bch_enabled is being assined to BCH_DISABLED.
>
> Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
> Cc: [email protected]
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..bc0408c 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Hm, this copyright update is not really related to the changes you're
describing in the commit message. I'll drop this line from the commit
(no need to resend it) and ask you to send a separate patch updating the
copyright. Is that ok?
> *
> * This software is licensed under the terms of the GNU General Public
> * License version 2, as published by the Free Software Foundation, and
> @@ -1893,7 +1893,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> | wide_bus << WIDE_FLASH
> | 1 << DEV0_CFG1_ECC_DISABLE;
>
> - host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
> + host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
> | 0 << ECC_SW_RESET
> | host->cw_data << ECC_NUM_DATA_BYTES
> | 1 << ECC_FORCE_CLK_OPEN
On 2017-08-03 21:26, Boris Brezillon wrote:
> On Wed, 19 Jul 2017 17:17:49 +0530
> Abhishek Sahu <[email protected]> wrote:
>
>> The configuration for BCH is not correct in the current driver.
>> The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the
>> BCH ECC in which
>>
>> 0x1 : BCH_DISABLED
>> 0x0 : BCH_ENABLED
>>
>> But currently host->bch_enabled is being assined to BCH_DISABLED.
>>
>> Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
>> Cc: [email protected]
>> Signed-off-by: Abhishek Sahu <[email protected]>
>> ---
>> drivers/mtd/nand/qcom_nandc.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 57d483a..bc0408c 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -1,5 +1,5 @@
>> /*
>> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2016-2017, The Linux Foundation. All rights
>> reserved.
>
> Hm, this copyright update is not really related to the changes you're
> describing in the commit message. I'll drop this line from the commit
> (no need to resend it) and ask you to send a separate patch updating
> the
> copyright. Is that ok?
>
The idea was to change the copyright year since we are making
the changes in this file. If it requires separate patch, then I
will do the same.
Also I need to change 'assined' -> assigned in commit text. I can
update the patch and fix this. I am planning to send the v3 patches
tomorrow which incorporates all the review comments.
>> *
>> * This software is licensed under the terms of the GNU General
>> Public
>> * License version 2, as published by the Free Software Foundation,
>> and
>> @@ -1893,7 +1893,7 @@ static int qcom_nand_host_setup(struct
>> qcom_nand_host *host)
>> | wide_bus << WIDE_FLASH
>> | 1 << DEV0_CFG1_ECC_DISABLE;
>>
>> - host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
>> + host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
>> | 0 << ECC_SW_RESET
>> | host->cw_data << ECC_NUM_DATA_BYTES
>> | 1 << ECC_FORCE_CLK_OPEN
--
Abhishek Sahu
On 2017-08-03 21:18, Boris Brezillon wrote:
> On Wed, 19 Jul 2017 17:17:50 +0530
> Abhishek Sahu <[email protected]> wrote:
>
>> The current driver is failing without complete bootchain since
>> NAND_DEV_CMD_VLD value is not valid.
>>
>> Signed-off-by: Abhishek Sahu <[email protected]>
>
> BTW, do you want to backport this fix? Maybe you add Fixes and
> Cc-stable tags...
>
It was not a critical fix but its better to backport this.
I will add these tags in v3.
>> ---
>> drivers/mtd/nand/qcom_nandc.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>> b/drivers/mtd/nand/qcom_nandc.c
>> index bc0408c..f3b995d 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -148,6 +148,9 @@
>> #define FETCH_ID 0xb
>> #define RESET_DEVICE 0xd
>>
>> +/* Value for NAND_DEV_CMD_VLD */
>> +#define NAND_DEV_CMD_VLD_VAL 0x1d
>> +
>> /*
>> * the NAND controller performs reads/writes with ECC in 516 byte
>> chunks.
>> * the driver calls the chunks 'step' or 'codeword' interchangeably
>> @@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct
>> qcom_nand_controller *nandc)
>> {
>> /* kill onenand */
>> nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>> + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>>
>> /* enable ADM DMA */
>> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
On 2017-08-03 21:17, Boris Brezillon wrote:
> On Wed, 19 Jul 2017 17:17:50 +0530
> Abhishek Sahu <[email protected]> wrote:
>
>> The current driver is failing without complete bootchain since
>> NAND_DEV_CMD_VLD value is not valid.
>>
>> Signed-off-by: Abhishek Sahu <[email protected]>
>> ---
>> drivers/mtd/nand/qcom_nandc.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>> b/drivers/mtd/nand/qcom_nandc.c
>> index bc0408c..f3b995d 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -148,6 +148,9 @@
>> #define FETCH_ID 0xb
>> #define RESET_DEVICE 0xd
>>
>> +/* Value for NAND_DEV_CMD_VLD */
>> +#define NAND_DEV_CMD_VLD_VAL 0x1d
>
> Where does this 0x1d value comes from? Defining a macro instead of
> passing 0x1d does not change the fact that this is a magic value :-).
>
This register tells the NAND controller which commands are valid
Bits Meaning
0 READ_START_VALID
1 READ_STOP_VALID
2 WRITE_START_VALID
3 ERASE_START_VALID
4 SEQ_READ_START_VLD
The default power on value is
0xe - ERASE_START_VALID | WRITE_START_VALID | READ_STOP_VALID
It need to be programmed for
0x1d - READ_START_VALID | WRITE_START_VALID | ERASE_START_VALID |
SEQ_READ_START_VLD
Read STOP command is not required in normal NAND reads so it need to be
disabled.
I will define the individual bits and will make this value with bits
which will
make this more clear.
>> +
>> /*
>> * the NAND controller performs reads/writes with ECC in 516 byte
>> chunks.
>> * the driver calls the chunks 'step' or 'codeword' interchangeably
>> @@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct
>> qcom_nand_controller *nandc)
>> {
>> /* kill onenand */
>> nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>> + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>>
>> /* enable ADM DMA */
>> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
--
Abhishek Sahu
On Thu, 03 Aug 2017 23:22:37 +0530
Abhishek Sahu <[email protected]> wrote:
> On 2017-08-03 21:26, Boris Brezillon wrote:
> > On Wed, 19 Jul 2017 17:17:49 +0530
> > Abhishek Sahu <[email protected]> wrote:
> >
> >> The configuration for BCH is not correct in the current driver.
> >> The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the
> >> BCH ECC in which
> >>
> >> 0x1 : BCH_DISABLED
> >> 0x0 : BCH_ENABLED
> >>
> >> But currently host->bch_enabled is being assined to BCH_DISABLED.
> >>
> >> Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
> >> Cc: [email protected]
> >> Signed-off-by: Abhishek Sahu <[email protected]>
> >> ---
> >> drivers/mtd/nand/qcom_nandc.c | 4 ++--
> >> 1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/mtd/nand/qcom_nandc.c
> >> b/drivers/mtd/nand/qcom_nandc.c
> >> index 57d483a..bc0408c 100644
> >> --- a/drivers/mtd/nand/qcom_nandc.c
> >> +++ b/drivers/mtd/nand/qcom_nandc.c
> >> @@ -1,5 +1,5 @@
> >> /*
> >> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> >> + * Copyright (c) 2016-2017, The Linux Foundation. All rights
> >> reserved.
> >
> > Hm, this copyright update is not really related to the changes you're
> > describing in the commit message. I'll drop this line from the commit
> > (no need to resend it) and ask you to send a separate patch updating
> > the
> > copyright. Is that ok?
> >
>
> The idea was to change the copyright year since we are making
> the changes in this file. If it requires separate patch, then I
> will do the same.
Yes, I'd prefer a separate patch.
>
> Also I need to change 'assined' -> assigned in commit text.
Yep, already fixed that one.
> I can
> update the patch and fix this. I am planning to send the v3 patches
> tomorrow which incorporates all the review comments.
Can you wait a bit. I already applied some of your patches [1] and would
like to finish my review.
Thanks,
Boris
[1]https://github.com/bbrezillon/linux-0day/commits/nand/next
On 2017-08-04 00:17, Boris Brezillon wrote:
> On Thu, 03 Aug 2017 23:22:37 +0530
> Abhishek Sahu <[email protected]> wrote:
>
>> On 2017-08-03 21:26, Boris Brezillon wrote:
>> > On Wed, 19 Jul 2017 17:17:49 +0530
>> > Abhishek Sahu <[email protected]> wrote:
>> >
>> >> The configuration for BCH is not correct in the current driver.
>> >> The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the
>> >> BCH ECC in which
>> >>
>> >> 0x1 : BCH_DISABLED
>> >> 0x0 : BCH_ENABLED
>> >>
>> >> But currently host->bch_enabled is being assined to BCH_DISABLED.
>> >>
>> >> Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
>> >> Cc: [email protected]
>> >> Signed-off-by: Abhishek Sahu <[email protected]>
>> >> ---
>> >> drivers/mtd/nand/qcom_nandc.c | 4 ++--
>> >> 1 file changed, 2 insertions(+), 2 deletions(-)
>> >>
>> >> diff --git a/drivers/mtd/nand/qcom_nandc.c
>> >> b/drivers/mtd/nand/qcom_nandc.c
>> >> index 57d483a..bc0408c 100644
>> >> --- a/drivers/mtd/nand/qcom_nandc.c
>> >> +++ b/drivers/mtd/nand/qcom_nandc.c
>> >> @@ -1,5 +1,5 @@
>> >> /*
>> >> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> >> + * Copyright (c) 2016-2017, The Linux Foundation. All rights
>> >> reserved.
>> >
>> > Hm, this copyright update is not really related to the changes you're
>> > describing in the commit message. I'll drop this line from the commit
>> > (no need to resend it) and ask you to send a separate patch updating
>> > the
>> > copyright. Is that ok?
>> >
>>
>> The idea was to change the copyright year since we are making
>> the changes in this file. If it requires separate patch, then I
>> will do the same.
>
> Yes, I'd prefer a separate patch.
Sure. will raise a separate patch
>
>>
>> Also I need to change 'assined' -> assigned in commit text.
>
> Yep, already fixed that one.
>
>> I can
>> update the patch and fix this. I am planning to send the v3 patches
>> tomorrow which incorporates all the review comments.
>
> Can you wait a bit. I already applied some of your patches [1] and
> would
> like to finish my review.
Thanks Boris. I will wait for it and will update my patch series
accordingly.
>
> Thanks,
>
> Boris
>
> [1]https://github.com/bbrezillon/linux-0day/commits/nand/next
Hi,
On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
> The EBI2 NAND directly remaps register read buffer with
> dma_map_sg. The QPIC NAND will give register read buffer in its
> command descriptor and the command descriptor will be mapped with
> dma_map_sg instead of register read buffer. This command
> descriptor will contain the dma address of the register read
> buffer.
It isn't entirely clear from the commit message why we can't use
the existing code with QPIC NAND. A bit of background would help.
Can you consider adding something like this:
"On QPIC NAND, which uses BAM DMA, we read the controller registers
by preparing a BAM command descriptor. This descriptor requires the
the a) controller register address and b) the DMA address in which we
want to store the value read back from the controller register. Therefore,
it's required that we also map our register read buffer for DMA (using
dma_map_single). We use the returned DMA address for preparing
entries in our command descriptor."
>
> This patch adds the DMA mapping support for register read buffer.
> This buffer will be DMA mapped during allocation time. Before
> starting of any operation, this buffer will be synced for device
> operation and after operation completion, it will be synced for
> CPU.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index cb2b245..f49c3da 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -229,6 +229,7 @@ struct nandc_regs {
> * by upper layers directly
> * @buf_size/count/start: markers for chip->read_buf/write_buf functions
> * @reg_read_buf: local buffer for reading back registers via DMA
> + * @reg_read_buf_phys: contains dma address for register read buffer
Maybe we should rename this as reg_read_dma since it is dma_addr_t ?
Looks good otherwise.
Thanks,
Archit
> * @reg_read_pos: marker for data read in reg_read_buf
> *
> * @regs: a contiguous chunk of memory for DMA register
> @@ -271,6 +272,7 @@ struct qcom_nand_controller {
> int buf_start;
>
> __le32 *reg_read_buf;
> + dma_addr_t reg_read_buf_phys;
> int reg_read_pos;
>
> struct nandc_regs *regs;
> @@ -363,6 +365,24 @@ static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
> iowrite32(val, nandc->base + offset);
> }
>
> +static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
> + bool is_cpu)
> +{
> + if (!nandc->props->is_bam)
> + return;
> +
> + if (is_cpu)
> + dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_buf_phys,
> + MAX_REG_RD *
> + sizeof(*nandc->reg_read_buf),
> + DMA_FROM_DEVICE);
> + else
> + dma_sync_single_for_device(nandc->dev, nandc->reg_read_buf_phys,
> + MAX_REG_RD *
> + sizeof(*nandc->reg_read_buf),
> + DMA_FROM_DEVICE);
> +}
> +
> static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
> {
> switch (offset) {
> @@ -847,6 +867,7 @@ static void free_descs(struct qcom_nand_controller *nandc)
> static void clear_read_regs(struct qcom_nand_controller *nandc)
> {
> nandc->reg_read_pos = 0;
> + nandc_read_buffer_sync(nandc, false);
> }
>
> static void pre_command(struct qcom_nand_host *host, int command)
> @@ -876,6 +897,7 @@ static void parse_erase_write_errors(struct qcom_nand_host *host, int command)
> int i;
>
> num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
> + nandc_read_buffer_sync(nandc, true);
>
> for (i = 0; i < num_cw; i++) {
> u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
> @@ -897,6 +919,7 @@ static void post_command(struct qcom_nand_host *host, int command)
>
> switch (command) {
> case NAND_CMD_READID:
> + nandc_read_buffer_sync(nandc, true);
> memcpy(nandc->data_buffer, nandc->reg_read_buf,
> nandc->buf_count);
> break;
> @@ -1060,6 +1083,7 @@ static int parse_read_errors(struct qcom_nand_host *host, u8 *data_buf,
> int i;
>
> buf = (struct read_stats *)nandc->reg_read_buf;
> + nandc_read_buffer_sync(nandc, true);
>
> for (i = 0; i < ecc->steps; i++, buf++) {
> u32 flash, buffer, erased_cw;
> @@ -1996,6 +2020,16 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
> return -ENOMEM;
>
> if (nandc->props->is_bam) {
> + nandc->reg_read_buf_phys =
> + dma_map_single(nandc->dev, nandc->reg_read_buf,
> + MAX_REG_RD *
> + sizeof(*nandc->reg_read_buf),
> + DMA_FROM_DEVICE);
> + if (dma_mapping_error(nandc->dev, nandc->reg_read_buf_phys)) {
> + dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
> + return -EIO;
> + }
> +
> nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
> if (!nandc->tx_chan) {
> dev_err(nandc->dev, "failed to request tx channel\n");
> @@ -2033,6 +2067,12 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
> static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
> {
> if (nandc->props->is_bam) {
> + if (!dma_mapping_error(nandc->dev, nandc->reg_read_buf_phys))
> + dma_unmap_single(nandc->dev, nandc->reg_read_buf_phys,
> + MAX_REG_RD *
> + sizeof(*nandc->reg_read_buf),
> + DMA_FROM_DEVICE);
> +
> if (nandc->tx_chan)
> dma_release_channel(nandc->tx_chan);
>
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
> The BAM transaction is the core data structure which will be used
> for all the data transfers in QPIC NAND. Since the base layer is
> serializing all the NAND requests so allocating BAM transaction
> before every transfer will be overhead. The memory for it be
What does 'base layer' here mean?
> allocated during probe time and before every transfer, it will be
> cleared. The BAM transaction contains the array of command
> elements, command and data scatter gather list and indexes. For
> every transfer, all the resource will be taken from BAM
> transaction.
Could you also mention in the commit message that the size of the
buffer used for BAM transactions is calculated based on the NAND device
with the maximum page size, among all the devices connected to the
controller.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 114 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 114 insertions(+)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f49c3da..fc29c97 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -22,6 +22,7 @@
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <linux/delay.h>
> +#include <linux/dma/qcom_bam_dma.h>
>
> /* NANDc reg offsets */
> #define NAND_FLASH_CMD 0x00
> @@ -172,6 +173,45 @@
> #define ECC_BCH_4BIT BIT(2)
> #define ECC_BCH_8BIT BIT(3)
>
> +#define QPIC_PER_CW_CMD_ELEMENTS 32
> +#define QPIC_PER_CW_CMD_SGL 32
> +#define QPIC_PER_CW_DATA_SGL 8
> +
> +/*
> + * This data type corresponds to the BAM transaction which will be used for all
> + * NAND transfers.
> + * @bam_ce - the array of bam command elements
> + * @cmd_sgl - sgl for nand bam command pipe
> + * @data_sgl - sgl for nand bam consumer/producer pipe
> + * @bam_ce_pos - the index in bam_ce which is available for next sgl request
> + * @bam_ce_start - the index in bam_ce which marks the start position ce
> + * for current sgl. It will be used for size calculation
> + * for current sgl
> + * @cmd_sgl_pos - current index in command sgl.
> + * @tx_sgl_pos - current index in data sgl for tx.
> + * @rx_sgl_pos - current index in data sgl for rx.
> + */
> +struct bam_transaction {
> + struct bam_cmd_element *bam_ce;
> + struct scatterlist *cmd_sgl;
> + struct scatterlist *data_sgl;
> + u32 bam_ce_pos;
> + u32 bam_ce_start;
> + u32 cmd_sgl_pos;
> + u32 cmd_sgl_start;
> + u32 tx_sgl_pos;
> + u32 tx_sgl_start;
> + u32 rx_sgl_pos;
> + u32 rx_sgl_start;
> +};
> +
> +/*
> + * This data type corresponds to the nand dma descriptor
> + * @list - list for desc_info
> + * @dir - DMA transfer direction
> + * @sgl - sgl which will be used for single sgl dma descriptor
> + * @dma_desc - low level dma engine descriptor
> + */
> struct desc_info {
> struct list_head node;
>
> @@ -238,6 +278,8 @@ struct nandc_regs {
> * @cmd1/vld: some fixed controller register values
> * @props: properties of current NAND controller IP,
> * initialized via DT match data
> + * @max_cwperpage: maximum qpic codeword required. calcualted
s/calcualted/calculated
Thanks,
Archit
> + * from all nand device pagesize
> */
> struct qcom_nand_controller {
> struct nand_hw_control controller;
> @@ -265,11 +307,13 @@ struct qcom_nand_controller {
> };
>
> struct list_head desc_list;
> + struct bam_transaction *bam_txn;
>
> u8 *data_buffer;
> int buf_size;
> int buf_count;
> int buf_start;
> + unsigned int max_cwperpage;
>
> __le32 *reg_read_buf;
> dma_addr_t reg_read_buf_phys;
> @@ -342,6 +386,50 @@ struct qcom_props {
> bool is_bam;
> };
>
> +/* Frees the BAM transaction memory */
> +static void free_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> + devm_kfree(nandc->dev, bam_txn);
> +}
> +
> +/* Allocates and Initializes the BAM transaction */
> +static struct bam_transaction *
> +alloc_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> + struct bam_transaction *bam_txn;
> + size_t bam_txn_size;
> + unsigned int num_cw = nandc->max_cwperpage;
> + void *bam_txn_buf;
> +
> + bam_txn_size =
> + sizeof(*bam_txn) + num_cw *
> + ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
> + (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
> + (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
> +
> + bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
> + if (!bam_txn_buf)
> + return NULL;
> +
> + bam_txn = bam_txn_buf;
> + bam_txn_buf += sizeof(*bam_txn);
> +
> + bam_txn->bam_ce = bam_txn_buf;
> + bam_txn_buf +=
> + sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
> +
> + bam_txn->cmd_sgl = bam_txn_buf;
> + bam_txn_buf +=
> + sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_SGL * num_cw;
> +
> + bam_txn->data_sgl = bam_txn_buf;
> + nandc->max_cwperpage = num_cw;
> +
> + return bam_txn;
> +}
> +
> static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> {
> return container_of(chip, struct qcom_nand_host, chip);
> @@ -1913,6 +2001,8 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
>
> cwperpage = mtd->writesize / ecc->size;
> + nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
> + cwperpage);
>
> /*
> * DATA_UD_BYTES varies based on whether the read/write command protects
> @@ -2047,6 +2137,20 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
> dev_err(nandc->dev, "failed to request cmd channel\n");
> return -ENODEV;
> }
> +
> + /*
> + * Initially allocate BAM transaction to read ONFI param page.
> + * After detecting all the devices, this BAM transaction will
> + * be freed and the next BAM tranasction will be allocated with
> + * maximum codeword size
> + */
> + nandc->max_cwperpage = 1;
> + nandc->bam_txn = alloc_bam_transaction(nandc);
> + if (!nandc->bam_txn) {
> + dev_err(nandc->dev,
> + "failed to allocate bam transaction\n");
> + return -ENOMEM;
> + }
> } else {
> nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> if (!nandc->chan) {
> @@ -2202,6 +2306,16 @@ static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
> if (list_empty(&nandc->host_list))
> return -ENODEV;
>
> + if (nandc->props->is_bam) {
> + free_bam_transaction(nandc);
> + nandc->bam_txn = alloc_bam_transaction(nandc);
> + if (!nandc->bam_txn) {
> + dev_err(nandc->dev,
> + "failed to allocate bam transaction\n");
> + return -ENOMEM;
> + }
> + }
> +
> list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
> ret = qcom_nand_mtd_register(nandc, host, child);
> if (ret) {
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
> 1. prepare_bam_async_desc is the function which will call
> all the DMA API’s. It will fetch the outstanding scatter gather
> list for passed channel and will do the DMA descriptor formation.
> The DMA flag is dependent upon the type of channel.
>
> 2. For ADM DMA, the descriptor is being formed for every DMA
> request so its sgl count will be always 1 while in BAM DMA, the
> clubbing of descriptor is being done to increase throughput.
>
> 3. ADM uses only one channel while in BAM, data descriptors
> will be submitted to tx channel (for write) or rx channel
> (for read) and all the registers read/write descriptors in
> command channel.
Reviewed-by: Archit Taneja <[email protected]>
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 143 ++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 130 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index fc29c97..589108b 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -209,14 +209,23 @@ struct bam_transaction {
> * This data type corresponds to the nand dma descriptor
> * @list - list for desc_info
> * @dir - DMA transfer direction
> - * @sgl - sgl which will be used for single sgl dma descriptor
> + * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
> + * ADM
> + * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
> + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
> * @dma_desc - low level dma engine descriptor
> */
> struct desc_info {
> struct list_head node;
>
> enum dma_data_direction dir;
> - struct scatterlist sgl;
> + union {
> + struct scatterlist adm_sgl;
> + struct {
> + struct scatterlist *bam_sgl;
> + int sgl_cnt;
> + };
> + };
> struct dma_async_tx_descriptor *dma_desc;
> };
>
> @@ -580,9 +589,77 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
> nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
> }
>
> -static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
> - int reg_off, const void *vaddr, int size,
> - bool flow_control)
> +/*
> + * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
> + * for BAM. This descriptor will be added in the NAND DMA descriptor queue
> + * which will be submitted to DMA engine.
> + */
> +static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
> + struct dma_chan *chan,
> + unsigned long flags)
> +{
> + struct desc_info *desc;
> + struct scatterlist *sgl;
> + unsigned int sgl_cnt;
> + int ret;
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> + enum dma_transfer_direction dir_eng;
> + struct dma_async_tx_descriptor *dma_desc;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + if (chan == nandc->cmd_chan) {
> + sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
> + sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
> + bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
> + dir_eng = DMA_MEM_TO_DEV;
> + desc->dir = DMA_TO_DEVICE;
> + } else if (chan == nandc->tx_chan) {
> + sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
> + sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
> + bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
> + dir_eng = DMA_MEM_TO_DEV;
> + desc->dir = DMA_TO_DEVICE;
> + } else {
> + sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
> + sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
> + bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
> + desc->dir = DMA_FROM_DEVICE;
> + dir_eng = DMA_DEV_TO_MEM;
> + }
> +
> + sg_mark_end(sgl + sgl_cnt - 1);
> + ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
> + if (ret == 0) {
> + dev_err(nandc->dev, "failure in mapping desc\n");
> + kfree(desc);
> + return -ENOMEM;
> + }
> +
> + desc->sgl_cnt = sgl_cnt;
> + desc->bam_sgl = sgl;
> +
> + dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
> + flags);
> +
> + if (!dma_desc) {
> + dev_err(nandc->dev, "failure in prep desc\n");
> + kfree(desc);
> + return -EINVAL;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + list_add_tail(&desc->node, &nandc->desc_list);
> +
> + return 0;
> +}
> +
> +static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
> + int reg_off, const void *vaddr, int size,
> + bool flow_control)
> {
> struct desc_info *desc;
> struct dma_async_tx_descriptor *dma_desc;
> @@ -595,7 +672,7 @@ static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
> if (!desc)
> return -ENOMEM;
>
> - sgl = &desc->sgl;
> + sgl = &desc->adm_sgl;
>
> sg_init_one(sgl, vaddr, size);
>
> @@ -671,7 +748,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
> vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
> nandc->reg_read_pos += num_regs;
>
> - return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
> + return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
> }
>
> /*
> @@ -702,7 +779,8 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>
> size = num_regs * sizeof(u32);
>
> - return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
> + return prep_adm_dma_desc(nandc, false, first, vaddr, size,
> + flow_control);
> }
>
> /*
> @@ -716,7 +794,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
> static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> const u8 *vaddr, int size)
> {
> - return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
> + return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
> }
>
> /*
> @@ -730,7 +808,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> const u8 *vaddr, int size)
> {
> - return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
> + return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
> }
>
> /*
> @@ -930,12 +1008,44 @@ static int submit_descs(struct qcom_nand_controller *nandc)
> {
> struct desc_info *desc;
> dma_cookie_t cookie = 0;
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> + int r;
> +
> + if (nandc->props->is_bam) {
> + if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
> + r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
> + if (r)
> + return r;
> + }
> +
> + if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
> + r = prepare_bam_async_desc(nandc, nandc->tx_chan,
> + DMA_PREP_INTERRUPT);
> + if (r)
> + return r;
> + }
> +
> + if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
> + r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> + DMA_PREP_CMD);
> + if (r)
> + return r;
> + }
> + }
>
> list_for_each_entry(desc, &nandc->desc_list, node)
> cookie = dmaengine_submit(desc->dma_desc);
>
> - if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
> - return -ETIMEDOUT;
> + if (nandc->props->is_bam) {
> + dma_async_issue_pending(nandc->tx_chan);
> + dma_async_issue_pending(nandc->rx_chan);
> +
> + if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
> + return -ETIMEDOUT;
> + } else {
> + if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
> + return -ETIMEDOUT;
> + }
>
> return 0;
> }
> @@ -946,7 +1056,14 @@ static void free_descs(struct qcom_nand_controller *nandc)
>
> list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
> list_del(&desc->node);
> - dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
> +
> + if (nandc->props->is_bam)
> + dma_unmap_sg(nandc->dev, desc->bam_sgl,
> + desc->sgl_cnt, desc->dir);
> + else
> + dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
> + desc->dir);
> +
> kfree(desc);
> }
> }
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On Wed, 19 Jul 2017 17:17:49 +0530
Abhishek Sahu <[email protected]> wrote:
> The configuration for BCH is not correct in the current driver.
> The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the
> BCH ECC in which
>
> 0x1 : BCH_DISABLED
> 0x0 : BCH_ENABLED
>
> But currently host->bch_enabled is being assined to BCH_DISABLED.
>
> Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
> Cc: [email protected]
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..bc0408c 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Applied to nand/next after removing the above line.
> *
> * This software is licensed under the terms of the GNU General Public
> * License version 2, as published by the Free Software Foundation, and
> @@ -1893,7 +1893,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> | wide_bus << WIDE_FLASH
> | 1 << DEV0_CFG1_ECC_DISABLE;
>
> - host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
> + host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
> | 0 << ECC_SW_RESET
> | host->cw_data << ECC_NUM_DATA_BYTES
> | 1 << ECC_FORCE_CLK_OPEN
On Wed, 19 Jul 2017 17:17:53 +0530
Abhishek Sahu <[email protected]> wrote:
> Currently the compatible “qcom,nandcs” is being used for each
> connected NAND device to support for multiple NAND devices in the
> same bus. The same thing can be achieved by looking reg property
> for each sub nodes which contains the chip select number so this
> patch removes the use of “qcom,nandcs” for specifying NAND device
> sub nodes.
>
> Since there is no user for this driver currently in so
> changing compatible string is safe.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
Applied to nand/next.
Thanks,
Boris
> ---
> drivers/mtd/nand/qcom_nandc.c | 26 ++++++++++++--------------
> 1 file changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 8fa2f0c..110a26a 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -2129,22 +2129,20 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> goto err_setup;
>
> for_each_available_child_of_node(dn, child) {
> - if (of_device_is_compatible(child, "qcom,nandcs")) {
> - host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> - if (!host) {
> - of_node_put(child);
> - ret = -ENOMEM;
> - goto err_cs_init;
> - }
> -
> - ret = qcom_nand_host_init(nandc, host, child);
> - if (ret) {
> - devm_kfree(dev, host);
> - continue;
> - }
> + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> + if (!host) {
> + of_node_put(child);
> + ret = -ENOMEM;
> + goto err_cs_init;
> + }
>
> - list_add_tail(&host->node, &nandc->host_list);
> + ret = qcom_nand_host_init(nandc, host, child);
> + if (ret) {
> + devm_kfree(dev, host);
> + continue;
> }
> +
> + list_add_tail(&host->node, &nandc->host_list);
> }
>
> if (list_empty(&nandc->host_list)) {
On Wed, 19 Jul 2017 17:17:54 +0530
Abhishek Sahu <[email protected]> wrote:
> Currently the compatible “qcom,nandcs” is being used for each
> connected NAND device to support for multiple NAND devices in the
> same bus. The same thing can be achieved by looking reg property
> for each sub nodes which contains the chip select number so this
> patch removes the use of “qcom,nandcs” for specifying NAND device
> sub nodes.
>
> Since there is no user for this driver currently in so
> changing compatible string is safe.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
Applied to nand/next.
Thanks,
Boris
> ---
> Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 4511918..b24adfe 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -28,7 +28,6 @@ chip-selects which (may) contain NAND flash chips. Their properties are as
> follows.
>
> Required properties:
> -- compatible: should contain "qcom,nandcs"
> - reg: a single integer representing the chip-select
> number (e.g., 0, 1, 2, etc.)
> - #address-cells: see partition.txt
> @@ -62,7 +61,6 @@ nand@1ac00000 {
> #size-cells = <0>;
>
> nandcs@0 {
> - compatible = "qcom,nandcs";
> reg = <0>;
>
> nand-ecc-strength = <4>;
On Wed, 19 Jul 2017 17:17:55 +0530
Abhishek Sahu <[email protected]> wrote:
> Each NAND page consist of multiple codewords. Following is
> sequence for NAND page read according to hardware guide.
>
> 1. Program Power-up configuration, page row, page column
> address and flash configuration registers.
> 2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
> codeword.
> 3. Read NAND_FLASH_STATUS for each codeword.
>
> The step 1 should be done once for each page and step 2,3 should
> be done for each codeword.
>
> Currently, all the 3 steps are being done for each codeword which
> is wrong. Now this patch reorganizes read page functions to
> configure page specific register once and per codeword specific
> registers for each NAND ECC step.
Applied.
Thanks,
Boris
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 37 +++++++++++++++++++++++++++----------
> 1 file changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 110a26a..27ea594 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -605,15 +605,23 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> }
>
> /*
> - * helper to prepare dma descriptors to configure registers needed for reading a
> - * codeword/step in a page
> + * Helper to prepare DMA descriptors for configuring registers
> + * before reading a NAND page.
> */
> -static void config_cw_read(struct qcom_nand_controller *nandc)
> +static void config_nand_page_read(struct qcom_nand_controller *nandc)
> {
> - write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> + write_reg_dma(nandc, NAND_ADDR0, 2);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> +}
>
> +/*
> + * Helper to prepare DMA descriptors for configuring registers
> + * before reading each codeword in NAND page.
> + */
> +static void config_nand_cw_read(struct qcom_nand_controller *nandc)
> +{
> + write_reg_dma(nandc, NAND_FLASH_CMD, 1);
> write_reg_dma(nandc, NAND_EXEC_CMD, 1);
>
> read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
> @@ -621,9 +629,15 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
> }
>
> /*
> - * helpers to prepare dma descriptors used to configure registers needed for
> - * writing a codeword/step in a page
> + * Helper to prepare dma descriptors to configure registers needed for reading a
> + * single codeword in page
> */
> +static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
> +{
> + config_nand_page_read(nandc);
> + config_nand_cw_read(nandc);
> +}
> +
> static void config_cw_write_pre(struct qcom_nand_controller *nandc)
> {
> write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> @@ -692,7 +706,7 @@ static int nandc_param(struct qcom_nand_host *host)
> nandc->buf_count = 512;
> memset(nandc->data_buffer, 0xff, nandc->buf_count);
>
> - config_cw_read(nandc);
> + config_nand_single_cw_page_read(nandc);
>
> read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> nandc->buf_count);
> @@ -1105,6 +1119,8 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
> struct nand_ecc_ctrl *ecc = &chip->ecc;
> int i, ret;
>
> + config_nand_page_read(nandc);
> +
> /* queue cmd descs for each codeword */
> for (i = 0; i < ecc->steps; i++) {
> int data_size, oob_size;
> @@ -1118,7 +1134,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
> oob_size = host->ecc_bytes_hw + host->spare_bytes;
> }
>
> - config_cw_read(nandc);
> + config_nand_cw_read(nandc);
>
> if (data_buf)
> read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> @@ -1178,7 +1194,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
> set_address(host, host->cw_size * (ecc->steps - 1), page);
> update_rw_regs(host, 1, true);
>
> - config_cw_read(nandc);
> + config_nand_single_cw_page_read(nandc);
>
> read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
>
> @@ -1228,6 +1244,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>
> host->use_ecc = false;
> update_rw_regs(host, ecc->steps, true);
> + config_nand_page_read(nandc);
>
> for (i = 0; i < ecc->steps; i++) {
> int data_size1, data_size2, oob_size1, oob_size2;
> @@ -1246,7 +1263,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
> oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
> }
>
> - config_cw_read(nandc);
> + config_nand_cw_read(nandc);
>
> read_data_dma(nandc, reg_off, data_buf, data_size1);
> reg_off += data_size1;
On Wed, 19 Jul 2017 17:17:56 +0530
Abhishek Sahu <[email protected]> wrote:
> Each NAND page consist of multiple codewords. Following is
> sequence for NAND page write according to hardware guide.
>
> 1. Program Power-up configuration, page row, page column
> address and flash configuration registers.
> 2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
> codeword.
> 3. Read NAND_FLASH_STATUS for each codeword.
>
> The step 1 should be done once for each page and step 2,3 should
> be done for each codeword.
>
> Currently, all the 3 steps are being done for each codeword which
> is wrong. Now this patch reorganizes page write functions to
> configure page specific register once and per codeword specific
> registers for each NAND ECC step.
Applied.
Thanks,
Boris
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 32 ++++++++++++++++++++------------
> 1 file changed, 20 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 27ea594..5b71478 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -638,15 +638,24 @@ static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
> config_nand_cw_read(nandc);
> }
>
> -static void config_cw_write_pre(struct qcom_nand_controller *nandc)
> +/*
> + * Helper to prepare DMA descriptors used to configure registers needed for
> + * before writing a NAND page.
> + */
> +static void config_nand_page_write(struct qcom_nand_controller *nandc)
> {
> - write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> + write_reg_dma(nandc, NAND_ADDR0, 2);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> }
>
> -static void config_cw_write_post(struct qcom_nand_controller *nandc)
> +/*
> + * Helper to prepare DMA descriptors for configuring registers
> + * before writing each codeword in NAND page.
> + */
> +static void config_nand_cw_write(struct qcom_nand_controller *nandc)
> {
> + write_reg_dma(nandc, NAND_FLASH_CMD, 1);
> write_reg_dma(nandc, NAND_EXEC_CMD, 1);
>
> read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> @@ -1329,6 +1338,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>
> host->use_ecc = true;
> update_rw_regs(host, ecc->steps, false);
> + config_nand_page_write(nandc);
>
> for (i = 0; i < ecc->steps; i++) {
> int data_size, oob_size;
> @@ -1342,7 +1352,6 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> oob_size = ecc->bytes;
> }
>
> - config_cw_write_pre(nandc);
>
> write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
>
> @@ -1360,7 +1369,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> oob_buf, oob_size);
> }
>
> - config_cw_write_post(nandc);
> + config_nand_cw_write(nandc);
>
> data_buf += data_size;
> oob_buf += oob_size;
> @@ -1393,6 +1402,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>
> host->use_ecc = false;
> update_rw_regs(host, ecc->steps, false);
> + config_nand_page_write(nandc);
>
> for (i = 0; i < ecc->steps; i++) {
> int data_size1, data_size2, oob_size1, oob_size2;
> @@ -1411,8 +1421,6 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
> oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
> }
>
> - config_cw_write_pre(nandc);
> -
> write_data_dma(nandc, reg_off, data_buf, data_size1);
> reg_off += data_size1;
> data_buf += data_size1;
> @@ -1428,7 +1436,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
> write_data_dma(nandc, reg_off, oob_buf, oob_size2);
> oob_buf += oob_size2;
>
> - config_cw_write_post(nandc);
> + config_nand_cw_write(nandc);
> }
>
> ret = submit_descs(nandc);
> @@ -1478,10 +1486,10 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
> set_address(host, host->cw_size * (ecc->steps - 1), page);
> update_rw_regs(host, 1, false);
>
> - config_cw_write_pre(nandc);
> + config_nand_page_write(nandc);
> write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> data_size + oob_size);
> - config_cw_write_post(nandc);
> + config_nand_cw_write(nandc);
>
> ret = submit_descs(nandc);
>
> @@ -1563,9 +1571,9 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
> set_address(host, host->cw_size * (ecc->steps - 1), page);
> update_rw_regs(host, 1, false);
>
> - config_cw_write_pre(nandc);
> + config_nand_page_write(nandc);
> write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
> - config_cw_write_post(nandc);
> + config_nand_cw_write(nandc);
>
> ret = submit_descs(nandc);
>
On Wed, 19 Jul 2017 17:17:57 +0530
Abhishek Sahu <[email protected]> wrote:
> The memset in clear_read_regs is overhead. All the register data
> will be filled by DMA during NAND operation so making these
> register variables zero is not required.
>
Applied.
Thanks,
Boris
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 5b71478..7ecd0f8 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -826,8 +826,6 @@ static void free_descs(struct qcom_nand_controller *nandc)
> static void clear_read_regs(struct qcom_nand_controller *nandc)
> {
> nandc->reg_read_pos = 0;
> - memset(nandc->reg_read_buf, 0,
> - MAX_REG_RD * sizeof(*nandc->reg_read_buf));
> }
>
> static void pre_command(struct qcom_nand_host *host, int command)
On Wed, 2 Aug 2017 13:51:45 +0530
Archit Taneja <[email protected]> wrote:
> On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
> > This is reorganization of exiting code and will not change any
> > functionality. The NAND controller supports multiple NAND device
> > with different page size. The subsequent patch allocate memory
> > which depends upon the maximum number of codewords so this patch
> > reorganizes the NAND device probing. First the ONFI parameter
> > page will be read from each connected device followed by MTD
> > device registration.
> >
>
> Modified the commit message slightly so that it's more clear.
> Looks good otherwise.
>
> "The NAND controller can support multiple NAND devices having different
> page sizes. Future code will require us to allocate memory based on the
> maximum number of codewords among all the devices. We reorganize the NAND
> device probing such that the ONFI parameters are first read for each
> connected device to identify the maximum number of codewords possible,
> and only then proceed with MTD device registration (i.e, call nand_scan_tail
> and mtd_device_register).
>
> This is a reorganization of the existing code and will not change
> any functionality."
Applied after modifying the commit message as suggested by Archit.
Thanks,
Boris
>
> Thanks,
> Archit
>
> > Signed-off-by: Abhishek Sahu <[email protected]>
> > ---
> > drivers/mtd/nand/qcom_nandc.c | 88 +++++++++++++++++++++++++++++--------------
> > 1 file changed, 59 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> > index 7ecd0f8..8f9e86c 100644
> > --- a/drivers/mtd/nand/qcom_nandc.c
> > +++ b/drivers/mtd/nand/qcom_nandc.c
> > @@ -2059,14 +2059,67 @@ static int qcom_nand_host_init(struct qcom_nand_controller *nandc,
> > return ret;
> >
> > ret = qcom_nand_host_setup(host);
> > - if (ret)
> > - return ret;
> > +
> > + return ret;
> > +}
> > +
> > +static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
> > + struct qcom_nand_host *host,
> > + struct device_node *dn)
> > +{
> > + struct nand_chip *chip = &host->chip;
> > + struct mtd_info *mtd = nand_to_mtd(chip);
> > + int ret;
> >
> > ret = nand_scan_tail(mtd);
> > if (ret)
> > return ret;
> >
> > - return mtd_device_register(mtd, NULL, 0);
> > + ret = mtd_device_register(mtd, NULL, 0);
> > + if (ret)
> > + nand_cleanup(mtd_to_nand(mtd));
> > +
> > + return ret;
> > +}
> > +
> > +static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
> > +{
> > + struct device *dev = nandc->dev;
> > + struct device_node *dn = dev->of_node, *child;
> > + struct qcom_nand_host *host, *tmp;
> > + int ret;
> > +
> > + for_each_available_child_of_node(dn, child) {
> > + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> > + if (!host) {
> > + of_node_put(child);
> > + return -ENOMEM;
> > + }
> > +
> > + ret = qcom_nand_host_init(nandc, host, child);
> > + if (ret) {
> > + devm_kfree(dev, host);
> > + continue;
> > + }
> > +
> > + list_add_tail(&host->node, &nandc->host_list);
> > + }
> > +
> > + if (list_empty(&nandc->host_list))
> > + return -ENODEV;
> > +
> > + list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
> > + ret = qcom_nand_mtd_register(nandc, host, child);
> > + if (ret) {
> > + list_del(&host->node);
> > + devm_kfree(dev, host);
> > + }
> > + }
> > +
> > + if (list_empty(&nandc->host_list))
> > + return -ENODEV;
> > +
> > + return 0;
> > }
> >
> > /* parse custom DT properties here */
> > @@ -2094,10 +2147,8 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
> > static int qcom_nandc_probe(struct platform_device *pdev)
> > {
> > struct qcom_nand_controller *nandc;
> > - struct qcom_nand_host *host;
> > const void *dev_data;
> > struct device *dev = &pdev->dev;
> > - struct device_node *dn = dev->of_node, *child;
> > struct resource *res;
> > int ret;
> >
> > @@ -2151,33 +2202,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> > if (ret)
> > goto err_setup;
> >
> > - for_each_available_child_of_node(dn, child) {
> > - host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> > - if (!host) {
> > - of_node_put(child);
> > - ret = -ENOMEM;
> > - goto err_cs_init;
> > - }
> > -
> > - ret = qcom_nand_host_init(nandc, host, child);
> > - if (ret) {
> > - devm_kfree(dev, host);
> > - continue;
> > - }
> > -
> > - list_add_tail(&host->node, &nandc->host_list);
> > - }
> > -
> > - if (list_empty(&nandc->host_list)) {
> > - ret = -ENODEV;
> > - goto err_cs_init;
> > - }
> > + ret = qcom_probe_nand_devices(nandc);
> > + if (ret)
> > + goto err_setup;
> >
> > return 0;
> >
> > -err_cs_init:
> > - list_for_each_entry(host, &nandc->host_list, node)
> > - nand_release(nand_to_mtd(&host->chip));
> > err_setup:
> > clk_disable_unprepare(nandc->aon_clk);
> > err_aon_clk:
> >
>
On Wed, 19 Jul 2017 17:17:59 +0530
Abhishek Sahu <[email protected]> wrote:
> Currently driver data is being assigned directly with ECC modes.
> Now, the plan is to add more NAND controller versions, so
> reorganized the current driver data assignment by creating NAND
> controller properties structure. This will contain all
> properties specific to NAND controller.
>
Applied.
Thanks,
Boris
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 23 +++++++++++++++++------
> 1 file changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 8f9e86c..3b0ae91 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -235,7 +235,7 @@ struct nandc_regs {
> * writes. contains the register values to be
> * written to controller
> * @cmd1/vld: some fixed controller register values
> - * @ecc_modes: supported ECC modes by the current controller,
> + * @props: properties of current NAND controller IP,
> * initialized via DT match data
> */
> struct qcom_nand_controller {
> @@ -266,7 +266,7 @@ struct qcom_nand_controller {
> struct nandc_regs *regs;
>
> u32 cmd1, vld;
> - u32 ecc_modes;
> + const struct qcom_props *props;
> };
>
> /*
> @@ -319,6 +319,15 @@ struct qcom_nand_host {
> u32 clrreadstatus;
> };
>
> +/*
> + * This data type corresponds to the nand controller properties which varies
> + * among different NAND controller IP's.
> + * @ecc_modes - ecc mode for NAND
> + */
> +struct qcom_props {
> + u32 ecc_modes;
> +};
> +
> static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> {
> return container_of(chip, struct qcom_nand_host, chip);
> @@ -1820,7 +1829,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> * always 10 bytes
> */
> - if (nandc->ecc_modes & ECC_BCH_4BIT) {
> + if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
> /* BCH */
> host->bch_enabled = true;
> ecc_mode = 0;
> @@ -2165,7 +2174,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> return -ENODEV;
> }
>
> - nandc->ecc_modes = (unsigned long)dev_data;
> + nandc->props = dev_data;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> nandc->base = devm_ioremap_resource(dev, res);
> @@ -2234,7 +2243,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> return 0;
> }
>
> -#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
> +static const struct qcom_props ebi2_nandc_data = {
> + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> +};
>
> /*
> * data will hold a struct pointer containing more differences once we support
> @@ -2242,7 +2253,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> */
> static const struct of_device_id qcom_nandc_of_match[] = {
> { .compatible = "qcom,ebi2-nandc",
> - .data = (void *)EBI2_NANDC_ECC_MODES,
> + .data = &ebi2_nandc_data,
> },
> {}
> };
Hi Abhishek,
On Wed, 19 Jul 2017 17:17:48 +0530
Abhishek Sahu <[email protected]> wrote:
> v2:
>
> 1. Addressed the review comments given in v1
> 2. Removed the DMA coherent buffer for register read and used
> streaming DMA API’s
> 3. Reorganized the NAND read and write functions
> 4. Separated patch for driver and documentation changes
> 5. Changed the compatible string for EBI2
>
> v1:
>
> http://www.spinics.net/lists/devicetree/msg183706.html
>
> Abhishek Sahu (25):
> mtd: nand: qcom: fix config error for BCH
> mtd: nand: qcom: program NAND_DEV_CMD_VLD register
> mtd: nand: qcom: change compatible string for EBI2 NANDC
> dt-bindings: qcom_nandc: change compatible string for EBI2 NANDC
> mtd: nand: qcom: remove redundant chip select compatible string
> dt-bindings: qcom_nandc: remove chip select compatible string
> mtd: nand: qcom: reorganize nand page read
> mtd: nand: qcom: reorganize nand page write
> mtd: nand: qcom: remove memset for clearing read register buffer
> mtd: nand: qcom: reorganize nand devices probing
> mtd: nand: qcom: support for NAND controller properties
> dt-bindings: qcom_nandc: QPIC NAND documentation
> mtd: nand: qcom: add QPIC NAND compatible string
> mtd: nand: qcom: add and initialize QPIC DMA resources
> mtd: nand: qcom: DMA mapping support for register read buffer
> mtd: nand: qcom: allocate BAM transaction
> mtd: nand: qcom: add BAM DMA descriptor handling
> mtd: nand: qcom: support for passing flags in transfer functions
> mtd: nand: qcom: support for read location registers
> mtd: nand: qcom: erased codeword detection configuration
> mtd: nand: qcom: support for QPIC page read/write
> mtd: nand: qcom: QPIC raw write support
> mtd: nand: qcom: change register offset defines with enums
> dt-bindings: qcom_nandc: compatible string for version 1.5.0
> mtd: nand: qcom: support for QPIC version 1.5.0
Applied patch 1 and 5 to 11 to nand/next [1].
>
> .../devicetree/bindings/mtd/qcom_nandc.txt | 56 +-
> drivers/mtd/nand/qcom_nandc.c | 1157 ++++++++++++++++----
> 2 files changed, 1010 insertions(+), 203 deletions(-)
>
On Fri, 4 Aug 2017 09:53:05 +0200
Boris Brezillon <[email protected]> wrote:
> Hi Abhishek,
>
> On Wed, 19 Jul 2017 17:17:48 +0530
> Abhishek Sahu <[email protected]> wrote:
>
> > v2:
> >
> > 1. Addressed the review comments given in v1
> > 2. Removed the DMA coherent buffer for register read and used
> > streaming DMA API’s
> > 3. Reorganized the NAND read and write functions
> > 4. Separated patch for driver and documentation changes
> > 5. Changed the compatible string for EBI2
> >
> > v1:
> >
> > http://www.spinics.net/lists/devicetree/msg183706.html
> >
> > Abhishek Sahu (25):
> > mtd: nand: qcom: fix config error for BCH
> > mtd: nand: qcom: program NAND_DEV_CMD_VLD register
> > mtd: nand: qcom: change compatible string for EBI2 NANDC
> > dt-bindings: qcom_nandc: change compatible string for EBI2 NANDC
> > mtd: nand: qcom: remove redundant chip select compatible string
> > dt-bindings: qcom_nandc: remove chip select compatible string
> > mtd: nand: qcom: reorganize nand page read
> > mtd: nand: qcom: reorganize nand page write
> > mtd: nand: qcom: remove memset for clearing read register buffer
> > mtd: nand: qcom: reorganize nand devices probing
> > mtd: nand: qcom: support for NAND controller properties
> > dt-bindings: qcom_nandc: QPIC NAND documentation
> > mtd: nand: qcom: add QPIC NAND compatible string
> > mtd: nand: qcom: add and initialize QPIC DMA resources
> > mtd: nand: qcom: DMA mapping support for register read buffer
> > mtd: nand: qcom: allocate BAM transaction
> > mtd: nand: qcom: add BAM DMA descriptor handling
> > mtd: nand: qcom: support for passing flags in transfer functions
> > mtd: nand: qcom: support for read location registers
> > mtd: nand: qcom: erased codeword detection configuration
> > mtd: nand: qcom: support for QPIC page read/write
> > mtd: nand: qcom: QPIC raw write support
> > mtd: nand: qcom: change register offset defines with enums
> > dt-bindings: qcom_nandc: compatible string for version 1.5.0
> > mtd: nand: qcom: support for QPIC version 1.5.0
>
> Applied patch 1 and 5 to 11 to nand/next [1].
>
My bad, it's 5 to 10, patch 11 did not apply cleanly. And I also forgot
the link. Please rebase on this branch before sending your v3.
Thanks,
Boris
[1]http://git.infradead.org/l2-mtd.git/shortlog/refs/heads/nand/next
> >
> > .../devicetree/bindings/mtd/qcom_nandc.txt | 56 +-
> > drivers/mtd/nand/qcom_nandc.c | 1157 ++++++++++++++++----
> > 2 files changed, 1010 insertions(+), 203 deletions(-)
> >
>
On Fri, 4 Aug 2017 09:49:52 +0200
Boris Brezillon <[email protected]> wrote:
> On Wed, 19 Jul 2017 17:17:59 +0530
> Abhishek Sahu <[email protected]> wrote:
>
> > Currently driver data is being assigned directly with ECC modes.
> > Now, the plan is to add more NAND controller versions, so
> > reorganized the current driver data assignment by creating NAND
> > controller properties structure. This will contain all
> > properties specific to NAND controller.
> >
>
> Applied.
My bad, this one has not been applied.
>
> Thanks,
>
> Boris
>
> > Signed-off-by: Abhishek Sahu <[email protected]>
> > ---
> > drivers/mtd/nand/qcom_nandc.c | 23 +++++++++++++++++------
> > 1 file changed, 17 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> > index 8f9e86c..3b0ae91 100644
> > --- a/drivers/mtd/nand/qcom_nandc.c
> > +++ b/drivers/mtd/nand/qcom_nandc.c
> > @@ -235,7 +235,7 @@ struct nandc_regs {
> > * writes. contains the register values to be
> > * written to controller
> > * @cmd1/vld: some fixed controller register values
> > - * @ecc_modes: supported ECC modes by the current controller,
> > + * @props: properties of current NAND controller IP,
> > * initialized via DT match data
> > */
> > struct qcom_nand_controller {
> > @@ -266,7 +266,7 @@ struct qcom_nand_controller {
> > struct nandc_regs *regs;
> >
> > u32 cmd1, vld;
> > - u32 ecc_modes;
> > + const struct qcom_props *props;
> > };
> >
> > /*
> > @@ -319,6 +319,15 @@ struct qcom_nand_host {
> > u32 clrreadstatus;
> > };
> >
> > +/*
> > + * This data type corresponds to the nand controller properties which varies
> > + * among different NAND controller IP's.
> > + * @ecc_modes - ecc mode for NAND
> > + */
> > +struct qcom_props {
> > + u32 ecc_modes;
> > +};
> > +
> > static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> > {
> > return container_of(chip, struct qcom_nand_host, chip);
> > @@ -1820,7 +1829,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> > * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> > * always 10 bytes
> > */
> > - if (nandc->ecc_modes & ECC_BCH_4BIT) {
> > + if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
> > /* BCH */
> > host->bch_enabled = true;
> > ecc_mode = 0;
> > @@ -2165,7 +2174,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> > return -ENODEV;
> > }
> >
> > - nandc->ecc_modes = (unsigned long)dev_data;
> > + nandc->props = dev_data;
> >
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > nandc->base = devm_ioremap_resource(dev, res);
> > @@ -2234,7 +2243,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> > return 0;
> > }
> >
> > -#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
> > +static const struct qcom_props ebi2_nandc_data = {
> > + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> > +};
> >
> > /*
> > * data will hold a struct pointer containing more differences once we support
> > @@ -2242,7 +2253,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> > */
> > static const struct of_device_id qcom_nandc_of_match[] = {
> > { .compatible = "qcom,ebi2-nandc",
> > - .data = (void *)EBI2_NANDC_ECC_MODES,
> > + .data = &ebi2_nandc_data,
> > },
> > {}
> > };
>
On 2017-08-04 13:25, Boris Brezillon wrote:
> On Fri, 4 Aug 2017 09:53:05 +0200
> Boris Brezillon <[email protected]> wrote:
>
>> Hi Abhishek,
>>
>> On Wed, 19 Jul 2017 17:17:48 +0530
>> Abhishek Sahu <[email protected]> wrote:
>>
>> > v2:
>> >
>> > 1. Addressed the review comments given in v1
>> > 2. Removed the DMA coherent buffer for register read and used
>> > streaming DMA API’s
>> > 3. Reorganized the NAND read and write functions
>> > 4. Separated patch for driver and documentation changes
>> > 5. Changed the compatible string for EBI2
>> >
>> > v1:
>> >
>> > http://www.spinics.net/lists/devicetree/msg183706.html
>> >
>> > Abhishek Sahu (25):
>> > mtd: nand: qcom: fix config error for BCH
>> > mtd: nand: qcom: program NAND_DEV_CMD_VLD register
>> > mtd: nand: qcom: change compatible string for EBI2 NANDC
>> > dt-bindings: qcom_nandc: change compatible string for EBI2 NANDC
>> > mtd: nand: qcom: remove redundant chip select compatible string
>> > dt-bindings: qcom_nandc: remove chip select compatible string
>> > mtd: nand: qcom: reorganize nand page read
>> > mtd: nand: qcom: reorganize nand page write
>> > mtd: nand: qcom: remove memset for clearing read register buffer
>> > mtd: nand: qcom: reorganize nand devices probing
>> > mtd: nand: qcom: support for NAND controller properties
>> > dt-bindings: qcom_nandc: QPIC NAND documentation
>> > mtd: nand: qcom: add QPIC NAND compatible string
>> > mtd: nand: qcom: add and initialize QPIC DMA resources
>> > mtd: nand: qcom: DMA mapping support for register read buffer
>> > mtd: nand: qcom: allocate BAM transaction
>> > mtd: nand: qcom: add BAM DMA descriptor handling
>> > mtd: nand: qcom: support for passing flags in transfer functions
>> > mtd: nand: qcom: support for read location registers
>> > mtd: nand: qcom: erased codeword detection configuration
>> > mtd: nand: qcom: support for QPIC page read/write
>> > mtd: nand: qcom: QPIC raw write support
>> > mtd: nand: qcom: change register offset defines with enums
>> > dt-bindings: qcom_nandc: compatible string for version 1.5.0
>> > mtd: nand: qcom: support for QPIC version 1.5.0
>>
>> Applied patch 1 and 5 to 11 to nand/next [1].
>>
>
> My bad, it's 5 to 10, patch 11 did not apply cleanly. And I also forgot
> the link. Please rebase on this branch before sending your v3.
>
Thanks Boris.
I will rebase remaining patches on this branch.
> Thanks,
>
> Boris
>
> [1]http://git.infradead.org/l2-mtd.git/shortlog/refs/heads/nand/next
>
>> >
>> > .../devicetree/bindings/mtd/qcom_nandc.txt | 56 +-
>> > drivers/mtd/nand/qcom_nandc.c | 1157 ++++++++++++++++----
>> > 2 files changed, 1010 insertions(+), 203 deletions(-)
>> >
On Wed, 19 Jul 2017 17:17:59 +0530
Abhishek Sahu <[email protected]> wrote:
> Currently driver data is being assigned directly with ECC modes.
> Now, the plan is to add more NAND controller versions, so
> reorganized the current driver data assignment by creating NAND
> controller properties structure. This will contain all
> properties specific to NAND controller.
>
> Signed-off-by: Abhishek Sahu <[email protected]>
> ---
> drivers/mtd/nand/qcom_nandc.c | 23 +++++++++++++++++------
> 1 file changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 8f9e86c..3b0ae91 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -235,7 +235,7 @@ struct nandc_regs {
> * writes. contains the register values to be
> * written to controller
> * @cmd1/vld: some fixed controller register values
> - * @ecc_modes: supported ECC modes by the current controller,
> + * @props: properties of current NAND controller IP,
> * initialized via DT match data
> */
> struct qcom_nand_controller {
> @@ -266,7 +266,7 @@ struct qcom_nand_controller {
> struct nandc_regs *regs;
>
> u32 cmd1, vld;
> - u32 ecc_modes;
> + const struct qcom_props *props;
> };
>
> /*
> @@ -319,6 +319,15 @@ struct qcom_nand_host {
> u32 clrreadstatus;
> };
>
> +/*
> + * This data type corresponds to the nand controller properties which varies
> + * among different NAND controller IP's.
> + * @ecc_modes - ecc mode for NAND
> + */
> +struct qcom_props {
> + u32 ecc_modes;
> +};
> +
> static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> {
> return container_of(chip, struct qcom_nand_host, chip);
> @@ -1820,7 +1829,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> * always 10 bytes
> */
> - if (nandc->ecc_modes & ECC_BCH_4BIT) {
> + if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
> /* BCH */
> host->bch_enabled = true;
> ecc_mode = 0;
> @@ -2165,7 +2174,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> return -ENODEV;
> }
>
> - nandc->ecc_modes = (unsigned long)dev_data;
> + nandc->props = dev_data;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> nandc->base = devm_ioremap_resource(dev, res);
> @@ -2234,7 +2243,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> return 0;
> }
>
> -#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
> +static const struct qcom_props ebi2_nandc_data = {
> + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
Just a nit: parenthesis are unneeded here.
> +};
>
> /*
> * data will hold a struct pointer containing more differences once we support
> @@ -2242,7 +2253,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> */
> static const struct of_device_id qcom_nandc_of_match[] = {
> { .compatible = "qcom,ebi2-nandc",
> - .data = (void *)EBI2_NANDC_ECC_MODES,
> + .data = &ebi2_nandc_data,
> },
> {}
> };
On Mon, 31 Jul 2017 21:35:57 +0530
Abhishek Sahu <[email protected]> wrote:
> On 2017-07-26 00:13, Abhishek Sahu wrote:
> > On 2017-07-25 00:47, Rob Herring wrote:
> >> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
> >>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> >>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
> >>> while EBI2 NAND uses only single ADM channel.
> >>> 3. CRCI is only required for ADM DMA and its not required for
> >>> QPIC NAND.
> >>>
> >>> Signed-off-by: Abhishek Sahu <[email protected]>
> >>> ---
> >>> .../devicetree/bindings/mtd/qcom_nandc.txt | 54
> >>> ++++++++++++++++++++--
> >>> 1 file changed, 51 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >>> index b24adfe..8efaeb0 100644
> >>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >>> @@ -1,13 +1,15 @@
> >>> * Qualcomm NAND controller
> >>>
> >>> Required properties:
> >>> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses
> >>> ADM
> >>> - DMA like IPQ8064.
> >>> -
> >>> +- compatible: must be one of the following:
> >>> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> >>> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
> >>> like IPQ4019.
> >>
> >> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
> >> compatible strings.
> >
> > We have 3 versions of NAND HW currently.
> > EBI2,
> > QPIC version 1.4.0
> > QPIC version 1.5.0
> >
> > and multiple Qualcomm SoCs which use any one of these.
> >
> > The original plan was to have compatible string for NAND version since
> > same NAND hardware is being in different SoC and SoC dtsi will simply
> > use its NAND version compatible string like other Qualcomm hardwares
> >
> >
> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> >
> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
> >
>
> Following are the partial list for NAND controller and supported
> SoC
>
> EBI2: IPQ8064, APQ8064, MSM7xx, MDM9x15
> QPIC v1.4.0 MDM9x25, MDM9x35, MDM9x45, IPQ4019
> QPIC v1.5.0 MDM9x55, IPQ8074
>
> so could we use NAND controller specific compatible strings instead of
> SoC
> since it will easy to maintain?
Nope, though you can re-use the compatible of an old SoC for new SoCs
if the IP did not change.
For example:
- EBI2: compatible = "qcom,ipq8064"
- QPIC 1.4: compatible = "qcom,mdm9x25"
- QPIC 1.5: compatible = "qcom,mdm9x55"
Note that we usually pick the oldest SoC that started embedding an IP
when choosing the compatible. So my suggestion assumes IPQ8064 is older
than APQ8064, MSM7xx and MDM9x15.
On 2017-08-04 18:15, Boris Brezillon wrote:
> On Mon, 31 Jul 2017 21:35:57 +0530
> Abhishek Sahu <[email protected]> wrote:
>
>> On 2017-07-26 00:13, Abhishek Sahu wrote:
>> > On 2017-07-25 00:47, Rob Herring wrote:
>> >> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
>> >>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>> >>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>> >>> while EBI2 NAND uses only single ADM channel.
>> >>> 3. CRCI is only required for ADM DMA and its not required for
>> >>> QPIC NAND.
>> >>>
>> >>> Signed-off-by: Abhishek Sahu <[email protected]>
>> >>> ---
>> >>> .../devicetree/bindings/mtd/qcom_nandc.txt | 54
>> >>> ++++++++++++++++++++--
>> >>> 1 file changed, 51 insertions(+), 3 deletions(-)
>> >>>
>> >>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> >>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> >>> index b24adfe..8efaeb0 100644
>> >>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> >>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> >>> @@ -1,13 +1,15 @@
>> >>> * Qualcomm NAND controller
>> >>>
>> >>> Required properties:
>> >>> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses
>> >>> ADM
>> >>> - DMA like IPQ8064.
>> >>> -
>> >>> +- compatible: must be one of the following:
>> >>> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>> >>> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
>> >>> like IPQ4019.
>> >>
>> >> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
>> >> compatible strings.
>> >
>> > We have 3 versions of NAND HW currently.
>> > EBI2,
>> > QPIC version 1.4.0
>> > QPIC version 1.5.0
>> >
>> > and multiple Qualcomm SoCs which use any one of these.
>> >
>> > The original plan was to have compatible string for NAND version since
>> > same NAND hardware is being in different SoC and SoC dtsi will simply
>> > use its NAND version compatible string like other Qualcomm hardwares
>> >
>> >
>> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
>> >
>> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
>> >
>>
>> Following are the partial list for NAND controller and supported
>> SoC
>>
>> EBI2: IPQ8064, APQ8064, MSM7xx, MDM9x15
>> QPIC v1.4.0 MDM9x25, MDM9x35, MDM9x45, IPQ4019
>> QPIC v1.5.0 MDM9x55, IPQ8074
>>
>> so could we use NAND controller specific compatible strings instead
>> of
>> SoC
>> since it will easy to maintain?
>
> Nope, though you can re-use the compatible of an old SoC for new SoCs
> if the IP did not change.
>
> For example:
>
> - EBI2: compatible = "qcom,ipq8064"
> - QPIC 1.4: compatible = "qcom,mdm9x25"
> - QPIC 1.5: compatible = "qcom,mdm9x55"
>
> Note that we usually pick the oldest SoC that started embedding an IP
> when choosing the compatible. So my suggestion assumes IPQ8064 is older
> than APQ8064, MSM7xx and MDM9x15.
Thanks Boris for detailed clarification.
Then I will change the patch to use SoC specific compatible string.
Its better to use qcom,ipq4019 for 1.4.0 and qcom,ipq8074 for 1.5.0
since we don't have other SoC in upstream and I have tested the
NAND driver on these IPQ SoC's.
On Fri, 04 Aug 2017 18:41:20 +0530
Abhishek Sahu <[email protected]> wrote:
> On 2017-08-04 18:15, Boris Brezillon wrote:
> > On Mon, 31 Jul 2017 21:35:57 +0530
> > Abhishek Sahu <[email protected]> wrote:
> >
> >> On 2017-07-26 00:13, Abhishek Sahu wrote:
> >> > On 2017-07-25 00:47, Rob Herring wrote:
> >> >> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
> >> >>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> >> >>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
> >> >>> while EBI2 NAND uses only single ADM channel.
> >> >>> 3. CRCI is only required for ADM DMA and its not required for
> >> >>> QPIC NAND.
> >> >>>
> >> >>> Signed-off-by: Abhishek Sahu <[email protected]>
> >> >>> ---
> >> >>> .../devicetree/bindings/mtd/qcom_nandc.txt | 54
> >> >>> ++++++++++++++++++++--
> >> >>> 1 file changed, 51 insertions(+), 3 deletions(-)
> >> >>>
> >> >>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >> >>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >> >>> index b24adfe..8efaeb0 100644
> >> >>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >> >>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >> >>> @@ -1,13 +1,15 @@
> >> >>> * Qualcomm NAND controller
> >> >>>
> >> >>> Required properties:
> >> >>> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses
> >> >>> ADM
> >> >>> - DMA like IPQ8064.
> >> >>> -
> >> >>> +- compatible: must be one of the following:
> >> >>> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> >> >>> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
> >> >>> like IPQ4019.
> >> >>
> >> >> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
> >> >> compatible strings.
> >> >
> >> > We have 3 versions of NAND HW currently.
> >> > EBI2,
> >> > QPIC version 1.4.0
> >> > QPIC version 1.5.0
> >> >
> >> > and multiple Qualcomm SoCs which use any one of these.
> >> >
> >> > The original plan was to have compatible string for NAND version since
> >> > same NAND hardware is being in different SoC and SoC dtsi will simply
> >> > use its NAND version compatible string like other Qualcomm hardwares
> >> >
> >> >
> >> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> >> >
> >> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
> >> >
> >>
> >> Following are the partial list for NAND controller and supported
> >> SoC
> >>
> >> EBI2: IPQ8064, APQ8064, MSM7xx, MDM9x15
> >> QPIC v1.4.0 MDM9x25, MDM9x35, MDM9x45, IPQ4019
> >> QPIC v1.5.0 MDM9x55, IPQ8074
> >>
> >> so could we use NAND controller specific compatible strings instead
> >> of
> >> SoC
> >> since it will easy to maintain?
> >
> > Nope, though you can re-use the compatible of an old SoC for new SoCs
> > if the IP did not change.
> >
> > For example:
> >
> > - EBI2: compatible = "qcom,ipq8064"
> > - QPIC 1.4: compatible = "qcom,mdm9x25"
> > - QPIC 1.5: compatible = "qcom,mdm9x55"
> >
> > Note that we usually pick the oldest SoC that started embedding an IP
> > when choosing the compatible. So my suggestion assumes IPQ8064 is older
> > than APQ8064, MSM7xx and MDM9x15.
>
> Thanks Boris for detailed clarification.
> Then I will change the patch to use SoC specific compatible string.
>
> Its better to use qcom,ipq4019 for 1.4.0 and qcom,ipq8074 for 1.5.0
> since we don't have other SoC in upstream and I have tested the
> NAND driver on these IPQ SoC's.
Sounds good, but I'll let Rob confirm.