by Prabhakar

[permalink] [raw]

Subject: Re: [PATCH v2 02/13] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC

Hi Geert,

Thank you for the review.

On Wed, Apr 24, 2024 at 10:06 AM Geert Uytterhoeven
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Tue, Apr 23, 2024 at 7:59 PM Prabhakar <prabhakar.csengg@gmailcom> wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > Add documentation for the pin controller found on the Renesas RZ/V2H(P)
> > (R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L
> > family:
> > - Additional bits need to be set during pinmuxing.
> > - The GPIO pin count is different.
> >
> > Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is
> > added for the RZ/V2H(P) SoC.
> >
> > Also, add the 'renesas,output-impedance' property. The drive strength
> > setting on RZ/V2H(P) depends on the different power rails coming out from
> > the PMIC (connected via I2C). These power rails (required for drive
> > strength) can be 1.2V, 1.8V, or 3.3V.
> >
> > Pins are grouped into 4 groups:
> >
> > Group 1: Impedance
> > - 150/75/38/25 ohms (at 3.3V)
> > - 130/65/33/22 ohms (at 1.8V)
> >
> > Group 2: Impedance
> > - 50/40/33/25 ohms (at 1.8V)
> >
> > Group 3: Impedance
> > - 150/75/37.5/25 ohms (at 3.3V)
> > - 130/65/33/22 ohms (at 1.8V)
> >
> > Group 4: Impedance
> > - 110/55/30/20 ohms (at 1.8V)
> > - 150/75/38/25 ohms (at 1.2V)
> >
> > The 'renesas,output-impedance' property, as documented, can be
> > [0, 1, 2, 3], indicating x1/x2/x3/x4 drive strength.
>
> The documentation says "x1/x2/x4/x6" for all but Group 4 (P20/P21).
> Still, the actual values don't seem to match the magnification factors...
>
> > As power rail information may not be available very early in the boot
> > process, the 'renesas,output-impedance' property is added instead of
> > reusing the 'output-impedance-ohms' property.
> >
> > Also, allow bias-disable, bias-pull-down and bias-pull-up properties
> > as these can be used to configure the pins.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
>
> > --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > @@ -111,6 +116,18 @@ additionalProperties:
> > output-high: true
> > output-low: true
> > line-name: true
> > + bias-disable: true
> > + bias-pull-down: true
> > + bias-pull-up: true
> > + renesas,output-impedance:
> > + description: |
> > + Output impedance for pins on RZ/V2H(P) SoC.
> > + 0: Corresponds to x1
> > + 1: Corresponds to x2
> > + 2: Corresponds to x3
> > + 3: Corresponds to x4
>
> Hence I'd drop the multiplication factors, and just say the meaning
> of the value is pin-dependent?
>
Agreed, I will update the description "Output impedance for pins on
RZ/V2H(P) SoC. 0/1/2/3 corresponds to register bit values that can be
set in PFC_IOLH_mn register which adjusts the drive strength value and
is pin-dependent"

Cheers,
Prabhakar

> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1, 2, 3]
> >
> > - type: object
> > additionalProperties:
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds

2024-04-25 11:41:07

by Prabhakar

[permalink] [raw]

Subject: Re: [PATCH v2 06/13] pinctrl: renesas: pinctrl-rzg2l: Add function pointers for locking/unlocking the PFC register

Hi Biju,

Thank you for the review.

On Tue, Apr 23, 2024 at 7:12 PM Biju Das <[email protected]> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <[email protected]>
> > Sent: Tuesday, April 23, 2024 6:59 PM
> > Subject: [PATCH v2 06/13] pinctrl: renesas: pinctrl-rzg2l: Add function pointers for
> > locking/unlocking the PFC register
> >
> > From: Lad Prabhakar <[email protected]>
> >
> > On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers.
> > However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls writing to both PFC and
> > PMC registers. Additionally, BIT(7) B0WI is undocumented for the PWPR register on RZ/V2H(P) SoC. To
> > accommodate these differences across SoC variants, introduce the set_pfc_mode() and
> > pm_set_pfc() function pointers.
> >
> > Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_unlock() call is now called before PMC
> > read/write and pwpr_pfc_lock() call is now called after PMC read/write this is to keep changes
> > minimal for RZ/V2H(P).
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > RFC->v2
> > - Introduced function pointer for (un)lock
> > ---
> > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 51 ++++++++++++++++---------
> > 1 file changed, 34 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > index bec4685b4681..0840fda7ca69 100644
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -246,6 +246,8 @@ struct rzg2l_variable_pin_cfg {
> > u64 pin:3;
> > };
> >
> > +struct rzg2l_pinctrl;
> > +
> > struct rzg2l_pinctrl_data {
> > const char * const *port_pins;
> > const u64 *port_pin_configs;
> > @@ -256,6 +258,8 @@ struct rzg2l_pinctrl_data {
> > const struct rzg2l_hwcfg *hwcfg;
> > const struct rzg2l_variable_pin_cfg *variable_pin_cfg;
> > unsigned int n_variable_pin_cfg;
> > + void (*pwpr_pfc_unlock)(struct rzg2l_pinctrl *pctrl);
> > + void (*pwpr_pfc_lock)(struct rzg2l_pinctrl *pctrl);
> > };
> >
> > /**
> > @@ -462,7 +466,6 @@ static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] =
> > { static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> > u8 pin, u8 off, u8 func)
> > {
> > - const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
> > unsigned long flags;
> > u32 reg;
> >
> > @@ -473,27 +476,23 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> > reg &= ~(PM_MASK << (pin * 2));
> > writew(reg, pctrl->base + PM(off));
> >
> > + pctrl->data->pwpr_pfc_unlock(pctrl);
> > +
> > /* Temporarily switch to GPIO mode with PMC register */
> > reg = readb(pctrl->base + PMC(off));
> > writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
> >
> > - /* Set the PWPR register to allow PFC register to write */
> > - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> > - writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
> > -
> > /* Select Pin function mode with PFC register */
> > reg = readl(pctrl->base + PFC(off));
> > reg &= ~(PFC_MASK << (pin * 4));
> > writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
> >
> > - /* Set the PWPR register to be write-protected */
> > - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> > - writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
> > -
> > /* Switch to Peripheral pin function with PMC register */
> > reg = readb(pctrl->base + PMC(off));
> > writeb(reg | BIT(pin), pctrl->base + PMC(off));
> >
> > + pctrl->data->pwpr_pfc_lock(pctrl);
> > +
> > spin_unlock_irqrestore(&pctrl->lock, flags); };
> >
> > @@ -2519,12 +2518,8 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl
> > *pctrl, b static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) {
> > u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
> > - const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
> > - const struct rzg2l_register_offsets *regs = &hwcfg->regs;
> >
> > - /* Set the PWPR register to allow PFC register to write. */
> > - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> > - writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
> > + pctrl->data->pwpr_pfc_unlock(pctrl);
> >
> > /* Restore port registers. */
> > for (u32 port = 0; port < nports; port++) { @@ -2567,9 +2562,7 @@ static void
> > rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
> > }
> > }
> >
> > - /* Set the PWPR register to be write-protected. */
> > - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> > - writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
> > + pctrl->data->pwpr_pfc_lock(pctrl);
> > }
> >
> > static int rzg2l_pinctrl_suspend_noirq(struct device *dev) @@ -2631,6 +2624,24 @@ static int
> > rzg2l_pinctrl_resume_noirq(struct device *dev)
> > return 0;
> > }
> >
> > +static void rzg2l_pwpr_pfc_unlock(struct rzg2l_pinctrl *pctrl) {
> > + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
> > +
> > + /* Set the PWPR register to allow PFC register to write */
> > + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> > + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
> > +}
> > +
> > +static void rzg2l_pwpr_pfc_lock(struct rzg2l_pinctrl *pctrl) {
> > + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
> > +
> > + /* Set the PWPR register to be write-protected */
> > + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> > + writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
> > +}
> > +
> > static const struct rzg2l_hwcfg rzg2l_hwcfg = {
> > .regs = {
> > .pwpr = 0x3014,
> > @@ -2688,6 +2699,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
> > .variable_pin_cfg = r9a07g043f_variable_pin_cfg,
> > .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
> > #endif
> > + .pwpr_pfc_unlock = &rzg2l_pwpr_pfc_unlock,
> > + .pwpr_pfc_lock = &rzg2l_pwpr_pfc_lock,
> > };
> >
> > static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -2699,6 +2712,8 @@ static struct
> > rzg2l_pinctrl_data r9a07g044_data = {
> > .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
> > ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
> > .hwcfg = &rzg2l_hwcfg,
> > + .pwpr_pfc_unlock = &rzg2l_pwpr_pfc_unlock,
> > + .pwpr_pfc_lock = &rzg2l_pwpr_pfc_lock,
> > };
> >
> > static struct rzg2l_pinctrl_data r9a08g045_data = { @@ -2709,6 +2724,8 @@ static struct
> > rzg2l_pinctrl_data r9a08g045_data = {
> > .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
> > .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
> > .hwcfg = &rzg3s_hwcfg,
> > + .pwpr_pfc_unlock = &rzg2l_pwpr_pfc_unlock,
> > + .pwpr_pfc_lock = &rzg2l_pwpr_pfc_lock,
>
> Some memory can be saved by avoiding duplication of data by using
> a single pointer for structure containing function pointers??
>
> struct rzg2l_pinctrl_fns {
> void (*pwpr_pfc_unlock)(struct rzg2l_pinctrl *pctrl);
> void (*pwpr_pfc_lock)(struct rzg2l_pinctrl *pctrl);
> }
>
Ok makes sense, I will do that in the next version.

Cheers,
Prabhakar