Adds PCIe PF driver for OcteonTx3 DPI PF device which initializes DPI
DMA hardware's global configuration and enables PF-VF mbox channels
which can be used by it's VF devices. This DPI PF driver handles only
the resource configuration requests from VFs and it does not have any
data movement functionality.
Signed-off-by: Vamsi Attunuru <[email protected]>
---
MAINTAINERS | 5 +
drivers/misc/Kconfig | 10 +
drivers/misc/Makefile | 1 +
drivers/misc/mrvl-dpi/Makefile | 9 +
drivers/misc/mrvl-dpi/dpi.c | 559 +++++++++++++++++++++++++++++++++
drivers/misc/mrvl-dpi/dpi.h | 232 ++++++++++++++
6 files changed, 816 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 960512bec428..73029199716d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13104,6 +13104,11 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
+MARVELL OCTEONTX3 DPI DRIVER
+M: Vamsi Attunuru <[email protected]>
+S: Maintained
+F: drivers/misc/mrvl-dpi
+
MATROX FRAMEBUFFER DRIVER
L: [email protected]
S: Orphan
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4fb291f0bf7c..3142fdb1b4c0 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -574,6 +574,16 @@ config NSM
To compile this driver as a module, choose M here.
The module will be called nsm.
+config MARVELL_OCTEONTX3_DPI
+ tristate "OcteonTX3 DPI driver"
+ depends on ARM64 && PCI
+ default m
+ help
+ Enables OCTEONTX3 DPI driver which intializes DPI PF device's global configuration
+ and it's VFs resource configuration to enable DMA transfers. DPI PF device
+ does not have any data movement functionality, it only serves VF's resource
+ configuration requests.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ea6ea5bbbc9c..86229072166c 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
obj-$(CONFIG_NSM) += nsm.o
+obj-$(CONFIG_MARVELL_OCTEONTX3_DPI) += mrvl-dpi/
diff --git a/drivers/misc/mrvl-dpi/Makefile b/drivers/misc/mrvl-dpi/Makefile
new file mode 100644
index 000000000000..c938ea459483
--- /dev/null
+++ b/drivers/misc/mrvl-dpi/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for Marvell's OcteonTX3 DPI driver
+#
+
+obj-$(CONFIG_MARVELL_OCTEONTX3_DPI) += octeontx3_dpi.o
+
+octeontx3_dpi-y := dpi.o
+
diff --git a/drivers/misc/mrvl-dpi/dpi.c b/drivers/misc/mrvl-dpi/dpi.c
new file mode 100644
index 000000000000..fe0b3ee469c8
--- /dev/null
+++ b/drivers/misc/mrvl-dpi/dpi.c
@@ -0,0 +1,559 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell OcteonTx3 DPI driver
+ *
+ * Copyright (C) 2024 Marvell International Ltd.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include "dpi.h"
+
+#define DPI_DRV_NAME "OcteonTx3-dpi"
+#define DPI_DRV_STRING "Marvell OcteonTx3 DPI Driver"
+#define DPI_DRV_VERSION "1.0"
+
+static int mps = 128;
+module_param(mps, int, 0644);
+MODULE_PARM_DESC(mps, "Maximum payload size, Supported sizes are 128, 256, 512 and 1024 bytes");
+
+static int mrrs = 128;
+module_param(mrrs, int, 0644);
+MODULE_PARM_DESC(mrrs, "Maximum read request size, Supported sizes are 128, 256, 512 and 1024 bytes");
+
+static unsigned long eng_fifo_buf = 0x101008080808;
+module_param(eng_fifo_buf, ulong, 0644);
+MODULE_PARM_DESC(eng_fifo_buf, "Per engine buffer size. Each byte corresponds to engine number");
+
+static void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
+{
+ writeq(val, dpi->reg_base + offset);
+}
+
+static u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
+{
+ return readq(dpi->reg_base + offset);
+}
+
+static int dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
+{
+ u64 reg = 0ULL;
+
+ spin_lock(&dpi->vf_lock);
+ reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
+ reg &= ~DPI_DMA_CONTROL_WQECSDIS;
+ reg |= DPI_DMA_CONTROL_ZBWCSEN;
+ reg |= DPI_DMA_CONTROL_WQECSMODE1;
+ reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ spin_unlock(&dpi->vf_lock);
+
+ return 0;
+}
+
+static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
+ u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
+ u16 csize = dpivf->vf_config.csize;
+ u32 aura = dpivf->vf_config.aura;
+ int cnt = 0xFFFFF, queue = vf;
+ u64 reg = 0ULL;
+
+ spin_lock(&dpi->vf_lock);
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(queue), 0x1ULL);
+
+ while (cnt) {
+ reg = dpi_reg_read(dpi, DPI_DMAX_QRST(queue));
+ --cnt;
+ if (!(reg & 0x1))
+ break;
+ }
+
+ if (reg & 0x1)
+ dev_err(&dpi->pdev->dev, "Queue reset failed\n");
+
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), 0ULL);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(queue), 0ULL);
+
+ reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
+ dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(queue), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(queue));
+ reg |= DPI_DMA_IDS2_INST_AURA(aura);
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS(queue));
+ reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
+ reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
+ reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
+ reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(queue), reg);
+
+ spin_unlock(&dpi->vf_lock);
+
+ return 0;
+}
+
+static int dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ int queue = vf;
+
+ spin_lock(&dpi->vf_lock);
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(queue), 0x1ULL);
+
+ /* Reset IDS and IDS2 registers */
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), 0ULL);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(queue), 0ULL);
+
+ spin_unlock(&dpi->vf_lock);
+
+ return 0;
+}
+
+static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
+{
+ u64 reg;
+ u32 vf;
+
+ reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
+ if (reg) {
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ if (!(reg & (0x1UL << vf)))
+ continue;
+
+ if (!dpi->mbox[vf]) {
+ dev_err(&dpi->pdev->dev, "bad mbox vf %d\n", vf);
+ continue;
+ }
+
+ schedule_work(&dpi->mbox[vf]->wk.work);
+ }
+
+ if (reg)
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
+ }
+}
+
+static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
+{
+ struct dpipf *dpi = data;
+
+ dpi_poll_pfvf_mbox(dpi);
+
+ return IRQ_HANDLED;
+}
+
+static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
+{
+ switch (msg->s.cmd) {
+ case DPI_QUEUE_OPEN:
+ dpivf->vf_config.aura = msg->s.aura;
+ dpivf->vf_config.csize = msg->s.csize / 8;
+ dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
+ dpi_queue_init(dpi, dpivf, msg->s.vfid);
+ if (msg->s.wqecs)
+ dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
+ dpivf->setup_done = true;
+ break;
+ case DPI_QUEUE_OPEN_V2:
+ dpivf->vf_config.aura = msg->s.aura;
+ dpivf->vf_config.csize = msg->s.csize;
+ dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
+ dpi_queue_init(dpi, dpivf, msg->s.vfid);
+ if (msg->s.wqecs)
+ dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
+ dpivf->setup_done = true;
+ break;
+ case DPI_QUEUE_CLOSE:
+ dpivf->vf_config.aura = 0;
+ dpivf->vf_config.csize = 0;
+ dpivf->vf_config.sso_pf_func = 0;
+ dpivf->vf_config.npa_pf_func = 0;
+ dpi_queue_fini(dpi, dpivf, msg->s.vfid);
+ dpivf->setup_done = false;
+ break;
+ default:
+ return -1;
+ }
+ return 0;
+}
+
+static void dpi_pfvf_mbox_work(struct work_struct *work)
+{
+ struct dpi_pfvf_mbox_wk *wk = container_of(work, struct dpi_pfvf_mbox_wk, work);
+ union dpi_mbox_message_t msg = { 0 };
+ struct dpi_mbox *mbox = NULL;
+ struct dpipf_vf *dpivf;
+ struct dpipf *dpi;
+ int vf_id;
+
+ mbox = (struct dpi_mbox *)wk->ctxptr;
+ dpi = (struct dpipf *)mbox->pf;
+ vf_id = mbox->vf_id;
+
+ mutex_lock(&mbox->lock);
+ msg.u[0] = readq(mbox->vf_pf_data_reg);
+ if (unlikely(msg.u[0] == 0xFFFFFFFFFFFFFFFFU))
+ goto exit;
+
+ if (msg.s.vfid > dpi->total_vfs) {
+ dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
+ goto exit;
+ }
+
+ dpivf = &dpi->vf[msg.s.vfid];
+ msg.u[1] = readq(mbox->pf_vf_data_reg);
+ queue_config(dpi, dpivf, &msg);
+
+ writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
+exit:
+ mutex_unlock(&mbox->lock);
+}
+
+/* Setup registers for a PF mailbox */
+static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf_id)
+{
+ struct dpi_mbox *mbox = dpi->mbox[vf_id];
+
+ mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf_id);
+ mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf_id);
+}
+
+static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
+{
+ int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ dpi->mbox[vf] = vzalloc(sizeof(*dpi->mbox[vf]));
+
+ if (!dpi->mbox[vf])
+ goto free_mbox;
+
+ memset(dpi->mbox[vf], 0, sizeof(struct dpi_mbox));
+ mutex_init(&dpi->mbox[vf]->lock);
+ INIT_WORK(&dpi->mbox[vf]->wk.work, dpi_pfvf_mbox_work);
+ dpi->mbox[vf]->wk.ctxptr = dpi->mbox[vf];
+ dpi->mbox[vf]->pf = dpi;
+ dpi->mbox[vf]->vf_id = vf;
+ dpi_setup_mbox_regs(dpi, vf);
+ }
+
+ return 0;
+
+free_mbox:
+ while (vf) {
+ vf--;
+ cancel_work_sync(&dpi->mbox[vf]->wk.work);
+ mutex_destroy(&dpi->mbox[vf]->lock);
+ vfree(dpi->mbox[vf]);
+ dpi->mbox[vf] = NULL;
+ }
+
+ return -ENOMEM;
+}
+
+static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
+{
+ int vf_id;
+
+ for (vf_id = 0; vf_id < DPI_MAX_VFS; vf_id++) {
+ if (!dpi->mbox[vf_id])
+ continue;
+
+ if (work_pending(&dpi->mbox[vf_id]->wk.work))
+ cancel_work_sync(&dpi->mbox[vf_id]->wk.work);
+
+ mutex_destroy(&dpi->mbox[vf_id]->lock);
+ vfree(dpi->mbox[vf_id]);
+ dpi->mbox[vf_id] = NULL;
+ }
+}
+
+/**
+ * Global initialization of DPI
+ *
+ * @dpi: DPI device context structure
+ * @return Zero on success, negative on failure
+ */
+static int dpi_init(struct dpipf *dpi)
+{
+ uint8_t *eng_buf = (uint8_t *)&eng_fifo_buf;
+ int engine, port = 0;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ reg = DPI_ENG_BUF_BLKS(eng_buf[engine & 0x7]);
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+ }
+
+ reg = 0ULL;
+ reg = (DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
+ DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB(0x3fULL));
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
+
+ /* Configure MPS and MRRS for DPI */
+ if (mrrs < DPI_EBUS_MRRS_MIN || mrrs > DPI_EBUS_MRRS_MAX || !is_power_of_2(mrrs)) {
+ dev_info(&dpi->pdev->dev, "Invalid MRRS size:%d, Using default size(128B)\n", mrrs);
+ mrrs = 128;
+ }
+ mrrs_val = fls(mrrs) - 8;
+
+ if (mps < DPI_EBUS_MPS_MIN || mps > DPI_EBUS_MPS_MAX || !is_power_of_2(mps)) {
+ dev_info(&dpi->pdev->dev, "Invalid MPS size:%d, Using default size(128B)\n", mps);
+ mps = 128;
+ }
+ mps_val = fls(mps) - 8;
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ reg |= (DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val));
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ /* Set the write control FIFO threshold as per HW recommendation */
+ dpi_reg_write(dpi, DPI_WCTL_FIF_THR, 0x30);
+
+ return 0;
+}
+
+static int dpi_fini(struct dpipf *dpi)
+{
+ int engine = 0, port;
+ u64 reg = 0ULL;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES ; engine++)
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, reg);
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ return 0;
+}
+
+static int dpi_irq_init(struct dpipf *dpi)
+{
+ int i, num_msix = 1, msix_allocated;
+ int ret = 0;
+
+ /* Clear all RAS interrupts */
+ dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
+
+ /* Clear all RAS interrupt enable bits */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ dpi->msix_entries = kcalloc(num_msix, sizeof(struct msix_entry), GFP_KERNEL);
+ if (!dpi->msix_entries)
+ goto msix_alloc_err;
+
+ for (i = 0; i < num_msix; i++)
+ dpi->msix_entries[i].entry = DPI_MBOX_PF_VF_INT_IDX;
+
+ msix_allocated = pci_enable_msix_range(dpi->pdev, dpi->msix_entries, num_msix, num_msix);
+ if (msix_allocated != num_msix) {
+ dev_err(&dpi->pdev->dev, "DPI: Failed to enable %d msix irqs; got only %d\n",
+ num_msix, msix_allocated);
+ goto enable_msix_err;
+ }
+
+ dpi->num_irqs = msix_allocated;
+ dev_info(&dpi->pdev->dev, "DPI: MSI-X enabled successfully\n");
+
+ ret = request_irq(dpi->msix_entries[0].vector, dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
+ if (ret) {
+ dev_err(&dpi->pdev->dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
+ goto enable_msix_err;
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, 0xFFFFFFFF);
+
+ return 0;
+
+enable_msix_err:
+ if (msix_allocated > 0)
+ pci_disable_msix(dpi->pdev);
+ kfree(dpi->msix_entries);
+ dpi->msix_entries = NULL;
+msix_alloc_err:
+ return -1;
+}
+
+static void dpi_irq_free(struct dpipf *dpi)
+{
+ int i = 0;
+
+ /* Clear All Enables */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ for (i = 0; i < dpi->num_irqs; i++)
+ free_irq(pci_irq_vector(dpi->pdev, DPI_MBOX_PF_VF_INT_IDX), dpi);
+
+ pci_free_irq_vectors(dpi->pdev);
+ kfree(dpi->msix_entries);
+ dpi->msix_entries = NULL;
+ dpi->num_irqs = 0;
+}
+
+static int dpi_sriov_configure(struct pci_dev *pdev, int numvfs)
+{
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+ int ret = 0;
+
+ if (numvfs == 0) {
+ pci_disable_sriov(pdev);
+ dpi->total_vfs = 0;
+ } else {
+ ret = pci_enable_sriov(pdev, numvfs);
+ if (ret == 0) {
+ dpi->total_vfs = numvfs;
+ ret = numvfs;
+ }
+ }
+
+ return ret;
+}
+
+static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi->pdev = pdev;
+
+ ret = pcim_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to enable PCI device\n");
+ goto err_dpi_free;
+ }
+
+ ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to request MMIO region\n");
+ goto err_dpi_free;
+ }
+
+ dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
+
+ /* Initialize global PF registers */
+ ret = dpi_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize dpi\n");
+ goto err_dpi_free;
+ }
+
+ /* Setup PF-VF mailbox */
+ ret = dpi_pfvf_mbox_setup(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
+ goto err_dpi_fini;
+ }
+
+ /* Register interrupts */
+ ret = dpi_irq_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize irq vectors\n");
+ goto err_dpi_mbox_free;
+ }
+
+ pci_set_drvdata(pdev, dpi);
+ spin_lock_init(&dpi->vf_lock);
+
+ return 0;
+
+err_dpi_mbox_free:
+ dpi_pfvf_mbox_destroy(dpi);
+err_dpi_fini:
+ dpi_fini(dpi);
+err_dpi_free:
+ devm_kfree(dev, dpi);
+ return ret;
+}
+
+static void dpi_remove(struct pci_dev *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+
+ dpi_irq_free(dpi);
+ dpi_pfvf_mbox_destroy(dpi);
+ dpi_fini(dpi);
+ dpi_sriov_configure(pdev, 0);
+ pci_set_drvdata(pdev, NULL);
+ devm_kfree(dev, dpi);
+}
+
+static const struct pci_device_id dpi_id_table[] = {
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX3_DPI_PF,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_OCTEONTX3_DPI_PF) },
+ { 0, } /* end of table */
+};
+
+static struct pci_driver dpi_driver = {
+ .name = DPI_DRV_NAME,
+ .id_table = dpi_id_table,
+ .probe = dpi_probe,
+ .remove = dpi_remove,
+ .sriov_configure = dpi_sriov_configure,
+};
+
+static int __init dpi_init_module(void)
+{
+ pr_info("%s: %s\n", DPI_DRV_NAME, DPI_DRV_STRING);
+
+ return pci_register_driver(&dpi_driver);
+}
+
+static void __exit dpi_cleanup_module(void)
+{
+ pci_unregister_driver(&dpi_driver);
+}
+
+module_init(dpi_init_module);
+module_exit(dpi_cleanup_module);
+MODULE_DEVICE_TABLE(pci, dpi_id_table);
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_DESCRIPTION(DPI_DRV_STRING);
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DPI_DRV_VERSION);
diff --git a/drivers/misc/mrvl-dpi/dpi.h b/drivers/misc/mrvl-dpi/dpi.h
new file mode 100644
index 000000000000..99ebe6bbe577
--- /dev/null
+++ b/drivers/misc/mrvl-dpi/dpi.h
@@ -0,0 +1,232 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Marvell OcteonTx3 DPI driver
+ *
+ * Copyright (C) 2024 Marvell International Ltd.
+ */
+
+#ifndef __DPI_H__
+#define __DPI_H__
+
+ /* PCI device IDs */
+#define PCI_DEVID_OCTEONTX3_DPI_PF 0xA080
+#define PCI_SUBDEVID_OCTEONTX3_DPI_PF 0xBA00
+
+/* PCI BAR nos */
+#define PCI_DPI_CFG_BAR 0
+
+/* MSI-X interrupts */
+#define DPI_MAX_REQQ_INT 32
+#define DPI_MAX_CC_INT 64
+
+/* MBOX MSI-X interrupt vector index */
+#define DPI_MBOX_PF_VF_INT_IDX 0x75
+
+#define DPI_MAX_ENGINES 6
+#define DPI_MAX_VFS 32
+
+#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & 0x3fff)
+#define DPI_DMA_IBUFF_CSIZE_GET_CSIZE(x) ((x) & 0x3fff)
+
+#define DPI_DMA_IBUFF_CSIZE_NPA_FREE (1 << 16)
+
+#define DPI_DMA_IDS_INST_STRM(x) ((uint64_t)((x) & 0xff) << 40)
+#define DPI_DMA_IDS_GET_INST_STRM(x) (((x) >> 40) & 0xff)
+
+#define DPI_DMA_IDS_DMA_STRM(x) ((uint64_t)((x) & 0xff) << 32)
+#define DPI_DMA_IDS_GET_DMA_STRM(x) (((x) >> 32) & 0xff)
+
+#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) ((uint64_t)((x) & 0xffff) << 16)
+#define DPI_DMA_IDS_GET_DMA_NPA_PF_FUNC(x) (((x) >> 16) & 0xffff)
+
+#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((uint64_t)((x) & 0xffff))
+#define DPI_DMA_IDS_GET_DMA_SSO_PF_FUNC(x) ((x) & 0xffff)
+
+#define DPI_DMA_IDS2_INST_AURA(x) ((uint64_t)((x) & 0xfffff))
+#define DPI_DMA_IDS2_GET_INST_AURA(x) ((x) & 0xfffff)
+
+#define DPI_ENG_BUF_BLKS(x) ((x) & 0x1fULL)
+#define DPI_ENG_BUF_GET_BLKS(x) ((x) & 0x1fULL)
+
+#define DPI_ENG_BUF_BASE(x) (((x) & 0x3fULL) << 16)
+#define DPI_ENG_BUF_GET_BASE(x) (((x) >> 16) & 0x3fULL)
+
+#define DPI_DMA_ENG_EN_QEN(x) ((x) & 0xffULL)
+#define DPI_DMA_ENG_EN_GET_QEN(x) ((x) & 0xffULL)
+
+#define DPI_DMA_ENG_EN_MOLR(x) (((x) & 0x3ffULL) << 32)
+#define DPI_DMA_ENG_EN_GET_MOLR(x) (((x) >> 32) & 0x3ffULL)
+
+#define DPI_DMA_CONTROL_DMA_ENB(x) (((x) & 0x3fULL) << 48)
+#define DPI_DMA_CONTROL_GET_DMA_ENB(x) (((x) >> 48) & 0x3fULL)
+
+#define DPI_DMA_CONTROL_O_ES(x) (((x) & 0x3ULL) << 15)
+#define DPI_DMA_CONTROL_GET_O_ES(x) (((x) >> 15) & 0x3ULL)
+
+#define DPI_DMA_CONTROL_O_MODE (0x1ULL << 14)
+#define DPI_DMA_CONTROL_O_NS (0x1ULL << 17)
+#define DPI_DMA_CONTROL_O_RO (0x1ULL << 18)
+#define DPI_DMA_CONTROL_O_ADD1 (0x1ULL << 19)
+#define DPI_DMA_CONTROL_LDWB (0x1ULL << 32)
+#define DPI_DMA_CONTROL_NCB_TAG_DIS (0x1ULL << 34)
+#define DPI_DMA_CONTROL_WQECSMODE1 (0x1ULL << 37)
+#define DPI_DMA_CONTROL_ZBWCSEN (0x1ULL << 39)
+#define DPI_DMA_CONTROL_WQECSOFF(offset) (((uint64_t)offset) << 40)
+#define DPI_DMA_CONTROL_WQECSDIS (0x1ULL << 47)
+#define DPI_DMA_CONTROL_UIO_DIS (0x1ULL << 55)
+#define DPI_DMA_CONTROL_PKT_EN (0x1ULL << 56)
+#define DPI_DMA_CONTROL_FFP_DIS (0x1ULL << 59)
+
+#define DPI_CTL_EN (0x1ULL)
+
+#define DPI_DMA_CC_INT (0x1ULL)
+
+#define DPI_REQQ_INT_INSTRFLT (0x1ULL)
+#define DPI_REQQ_INT_RDFLT (0x1ULL << 1)
+#define DPI_REQQ_INT_WRFLT (0x1ULL << 2)
+#define DPI_REQQ_INT_CSFLT (0x1ULL << 3)
+#define DPI_REQQ_INT_INST_DBO (0x1ULL << 4)
+#define DPI_REQQ_INT_INST_ADDR_NULL (0x1ULL << 5)
+#define DPI_REQQ_INT_INST_FILL_INVAL (0x1ULL << 6)
+#define DPI_REQQ_INT_INSTR_PSN (0x1ULL << 7)
+
+#define DPI_REQQ_INT \
+ (DPI_REQQ_INT_INSTRFLT | \
+ DPI_REQQ_INT_RDFLT | \
+ DPI_REQQ_INT_WRFLT | \
+ DPI_REQQ_INT_CSFLT | \
+ DPI_REQQ_INT_INST_DBO | \
+ DPI_REQQ_INT_INST_ADDR_NULL | \
+ DPI_REQQ_INT_INST_FILL_INVAL | \
+ DPI_REQQ_INT_INSTR_PSN)
+
+#define DPI_PF_RAS_EBI_DAT_PSN (0x1ULL)
+#define DPI_PF_RAS_NCB_DAT_PSN (0x1ULL << 1)
+#define DPI_PF_RAS_NCB_CMD_PSN (0x1ULL << 2)
+#define DPI_PF_RAS_INT \
+ (DPI_PF_RAS_EBI_DAT_PSN | \
+ DPI_PF_RAS_NCB_DAT_PSN | \
+ DPI_PF_RAS_NCB_CMD_PSN)
+
+#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
+#define DPI_DMAX_REQBANK0(x) (0x8ULL | ((x) << 11))
+#define DPI_DMAX_REQBANK1(x) (0x10ULL | ((x) << 11))
+#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
+#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
+#define DPI_DMAX_IFLIGHT(x) (0x28ULL | ((x) << 11))
+#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
+#define DPI_DMAX_ERR_RSP_STATUS(x) (0x38ULL | ((x) << 11))
+
+#define DPI_CSCLK_ACTIVE_PC 0x10000ULL
+#define DPI_CTL 0x10010ULL
+#define DPI_DMA_CONTROL (0x10018ULL)
+#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
+#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
+#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
+#define DPI_EBUS_PORTX_ERR_INFO(x) (0x10200ULL | ((x) << 3))
+#define DPI_EBUS_PORTX_ERR(x) (0x10280ULL | ((x) << 3))
+
+#define DPI_PF_RAS (0x10308ULL)
+#define DPI_PF_RAS_ENA_W1C (0x10318ULL)
+
+#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
+
+#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
+#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
+
+#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
+#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
+
+#define DPI_MBOX_VF_PF_INT (0x16300ULL)
+#define DPI_MBOX_VF_PF_INT_W1S (0x16308ULL)
+#define DPI_MBOX_VF_PF_INT_ENA_W1C (0x16310ULL)
+#define DPI_MBOX_VF_PF_INT_ENA_W1S (0x16318ULL)
+
+#define DPI_WCTL_FIF_THR (0x17008ULL)
+
+#define DPI_EBUS_MRRS_MIN 128
+#define DPI_EBUS_MRRS_MAX 1024
+#define DPI_EBUS_MPS_MIN 128
+#define DPI_EBUS_MPS_MAX 1024
+#define DPI_EBUS_MAX_PORTS 2
+#define DPI_EBUS_PORTX_CFG_MRRS(x) (((x) & 0x7) << 0)
+#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & 0x7) << 4)
+
+enum dpi_mbox_word_type {
+ DPI_MBOX_TYPE_CMD,
+ DPI_MBOX_TYPE_RSP_ACK,
+ DPI_MBOX_TYPE_RSP_NACK,
+};
+
+struct dpivf_config {
+ uint16_t csize;
+ uint32_t aura;
+ uint16_t sso_pf_func;
+ uint16_t npa_pf_func;
+};
+
+struct dpipf_vf {
+ uint8_t this_vfid;
+ bool setup_done;
+ struct dpivf_config vf_config;
+};
+
+/* Wrappers around work structs */
+struct dpi_pfvf_mbox_wk {
+ struct work_struct work;
+ void *ctxptr;
+};
+
+/* DPI device mailbox */
+struct dpi_mbox {
+ /* A mutex to protect access to mbox. */
+ struct mutex lock;
+ u32 vf_id;
+ u8 __iomem *pf_vf_data_reg;
+ u8 __iomem *vf_pf_data_reg;
+ struct dpi_pfvf_mbox_wk wk;
+ struct dpipf *pf;
+};
+
+struct dpipf {
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ int num_irqs;
+ int total_vfs;
+ struct dpipf_vf vf[DPI_MAX_VFS];
+ struct msix_entry *msix_entries;
+ /* Mailbox to talk to VFs */
+ struct dpi_mbox *mbox[DPI_MAX_VFS];
+ /* lock to serialize queue access */
+ spinlock_t vf_lock;
+};
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+#define DPI_QUEUE_OPEN_V2 0x5
+
+union dpi_mbox_message_t {
+ uint64_t u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ uint64_t vfid :8;
+ /* Command code */
+ uint64_t cmd :4;
+ /* Command buffer size in 8-byte words */
+ uint64_t csize :14;
+ /* aura of the command buffer */
+ uint64_t aura :20;
+ /* SSO PF function */
+ uint64_t sso_pf_func :16;
+ /* NPA PF function */
+ uint64_t npa_pf_func :16;
+ /* Work queue completion status enable */
+ uint64_t wqecs :1;
+ /* Work queue completion status byte offset */
+ uint64_t wqecsoff :7;
+ } s __packed;
+};
+
+#endif
--
2.25.1
On Tue, Feb 13, 2024 at 07:55:24PM -0800, Vamsi Attunuru wrote:
> Adds PCIe PF driver for OcteonTx3 DPI PF device which initializes DPI
What is a "PF"?
WHat is "DPI"?
> DMA hardware's global configuration and enables PF-VF mbox channels
What is "PF-VF"?
> which can be used by it's VF devices. This DPI PF driver handles only
What is "VF"?
> the resource configuration requests from VFs and it does not have any
> data movement functionality.
What do you mean by "data movement functionality"?
Please provide a bit more dummed down description please, for those of
us who don't understand any of this.
And if this is a pci driver, why is it in misc?
>
> Signed-off-by: Vamsi Attunuru <[email protected]>
> ---
> MAINTAINERS | 5 +
> drivers/misc/Kconfig | 10 +
> drivers/misc/Makefile | 1 +
> drivers/misc/mrvl-dpi/Makefile | 9 +
> drivers/misc/mrvl-dpi/dpi.c | 559 +++++++++++++++++++++++++++++++++
> drivers/misc/mrvl-dpi/dpi.h | 232 ++++++++++++++
> 6 files changed, 816 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 960512bec428..73029199716d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -13104,6 +13104,11 @@ S: Supported
> F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
> F: drivers/mmc/host/sdhci-xenon*
>
> +MARVELL OCTEONTX3 DPI DRIVER
> +M: Vamsi Attunuru <[email protected]>
> +S: Maintained
> +F: drivers/misc/mrvl-dpi
> +
> MATROX FRAMEBUFFER DRIVER
> L: [email protected]
> S: Orphan
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 4fb291f0bf7c..3142fdb1b4c0 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -574,6 +574,16 @@ config NSM
> To compile this driver as a module, choose M here.
> The module will be called nsm.
>
> +config MARVELL_OCTEONTX3_DPI
> + tristate "OcteonTX3 DPI driver"
> + depends on ARM64 && PCI
> + default m
Don't set a default unless you can not boot the box without it.
> + help
> + Enables OCTEONTX3 DPI driver which intializes DPI PF device's global configuration
> + and it's VFs resource configuration to enable DMA transfers. DPI PF device
> + does not have any data movement functionality, it only serves VF's resource
> + configuration requests.
module name?
> +
> source "drivers/misc/c2port/Kconfig"
> source "drivers/misc/eeprom/Kconfig"
> source "drivers/misc/cb710/Kconfig"
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index ea6ea5bbbc9c..86229072166c 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
> obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
> obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
> obj-$(CONFIG_NSM) += nsm.o
> +obj-$(CONFIG_MARVELL_OCTEONTX3_DPI) += mrvl-dpi/
> diff --git a/drivers/misc/mrvl-dpi/Makefile b/drivers/misc/mrvl-dpi/Makefile
> new file mode 100644
> index 000000000000..c938ea459483
> --- /dev/null
> +++ b/drivers/misc/mrvl-dpi/Makefile
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Makefile for Marvell's OcteonTX3 DPI driver
> +#
> +
> +obj-$(CONFIG_MARVELL_OCTEONTX3_DPI) += octeontx3_dpi.o
> +
> +octeontx3_dpi-y := dpi.o
Why the two steps? Why not just name the file the module name?
And because of that, why do you need a subdirectory?
And if you do have a subdirectory, why not move the Kconfig entry into
it? You can't have it both ways here, sorry.
> +
> diff --git a/drivers/misc/mrvl-dpi/dpi.c b/drivers/misc/mrvl-dpi/dpi.c
> new file mode 100644
> index 000000000000..fe0b3ee469c8
> --- /dev/null
> +++ b/drivers/misc/mrvl-dpi/dpi.c
> @@ -0,0 +1,559 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Marvell OcteonTx3 DPI driver
> + *
> + * Copyright (C) 2024 Marvell International Ltd.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/pci.h>
> +#include <linux/irq.h>
> +#include <linux/interrupt.h>
> +
> +#include "dpi.h"
Why do you need a .h file for a single .c file?
> +
> +#define DPI_DRV_NAME "OcteonTx3-dpi"
> +#define DPI_DRV_STRING "Marvell OcteonTx3 DPI Driver"
> +#define DPI_DRV_VERSION "1.0"
Driver versions do not make sense once they are in the kernel tree,
please remove.
> +static int mps = 128;
> +module_param(mps, int, 0644);
> +MODULE_PARM_DESC(mps, "Maximum payload size, Supported sizes are 128, 256, 512 and 1024 bytes");
> +
> +static int mrrs = 128;
> +module_param(mrrs, int, 0644);
> +MODULE_PARM_DESC(mrrs, "Maximum read request size, Supported sizes are 128, 256, 512 and 1024 bytes");
> +
> +static unsigned long eng_fifo_buf = 0x101008080808;
> +module_param(eng_fifo_buf, ulong, 0644);
> +MODULE_PARM_DESC(eng_fifo_buf, "Per engine buffer size. Each byte corresponds to engine number");
This is not the 1990's, no module parameters should be needed, and they
don't work at all when you have multiple devices. Please make this
"just work" and if you have to tune it, make them proper dynamic options
at runtime.
> + while (cnt) {
> + reg = dpi_reg_read(dpi, DPI_DMAX_QRST(queue));
> + --cnt;
> + if (!(reg & 0x1))
> + break;
> + }
That's a long busy-wait loop, one that will take a variable amount of
time given different processor speeds. Shouldn't you be using a real
timeout instead?
> +
> + if (reg & 0x1)
> + dev_err(&dpi->pdev->dev, "Queue reset failed\n");
What can userspace do with this message? And why not return an error if
an error happened? Why are you ignoring it here?
> +
> + dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), 0ULL);
> + dpi_reg_write(dpi, DPI_DMAX_IDS(queue), 0ULL);
> +
> + reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
> + dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(queue), reg);
> +
> + reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(queue));
> + reg |= DPI_DMA_IDS2_INST_AURA(aura);
> + dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), reg);
> +
> + reg = dpi_reg_read(dpi, DPI_DMAX_IDS(queue));
> + reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
> + reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
> + reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
> + reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
> + dpi_reg_write(dpi, DPI_DMAX_IDS(queue), reg);
> +
> + spin_unlock(&dpi->vf_lock);
> +
> + return 0;
Shouldn't you have returned an error if one happened?
> +static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
> +{
> + switch (msg->s.cmd) {
> + case DPI_QUEUE_OPEN:
> + dpivf->vf_config.aura = msg->s.aura;
> + dpivf->vf_config.csize = msg->s.csize / 8;
> + dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
> + dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
> + dpi_queue_init(dpi, dpivf, msg->s.vfid);
> + if (msg->s.wqecs)
> + dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
> + dpivf->setup_done = true;
> + break;
> + case DPI_QUEUE_OPEN_V2:
> + dpivf->vf_config.aura = msg->s.aura;
> + dpivf->vf_config.csize = msg->s.csize;
> + dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
> + dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
> + dpi_queue_init(dpi, dpivf, msg->s.vfid);
> + if (msg->s.wqecs)
> + dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
> + dpivf->setup_done = true;
> + break;
> + case DPI_QUEUE_CLOSE:
> + dpivf->vf_config.aura = 0;
> + dpivf->vf_config.csize = 0;
> + dpivf->vf_config.sso_pf_func = 0;
> + dpivf->vf_config.npa_pf_func = 0;
> + dpi_queue_fini(dpi, dpivf, msg->s.vfid);
> + dpivf->setup_done = false;
> + break;
> + default:
> + return -1;
That is not a valid error number :(
> +static int __init dpi_init_module(void)
> +{
> + pr_info("%s: %s\n", DPI_DRV_NAME, DPI_DRV_STRING);
When drivers work properly, they are quiet. No need for this.
> +
> + return pci_register_driver(&dpi_driver);
> +}
> +
> +static void __exit dpi_cleanup_module(void)
> +{
> + pci_unregister_driver(&dpi_driver);
> +}
> +
> +module_init(dpi_init_module);
> +module_exit(dpi_cleanup_module);
module_pci_driver() instead? That will automatically get rid of the
pr_info() spam above :)
thanks,
greg k-h
On Wed, Feb 14, 2024, at 04:55, Vamsi Attunuru wrote:
> Adds PCIe PF driver for OcteonTx3 DPI PF device which initializes DPI
> DMA hardware's global configuration and enables PF-VF mbox channels
> which can be used by it's VF devices. This DPI PF driver handles only
> the resource configuration requests from VFs and it does not have any
> data movement functionality.
>
> Signed-off-by: Vamsi Attunuru <[email protected]>
This looks incomplete, as there is no apparent interface to
actually use the driver from either userspace or kernel. I
understand that you want to merge this one step at a time,
but please try to at least point out how this is intended
to be used, or post it together with an (in-kernel) user
if you plan to upstream that.
Is this used for anything other than networking? If not,
maybe it should be part of drivers/net/ instead of
drivers/misc.
A few more things that Greg hasn't already commented on:
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 4fb291f0bf7c..3142fdb1b4c0 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -574,6 +574,16 @@ config NSM
> To compile this driver as a module, choose M here.
> The module will be called nsm.
>
> +config MARVELL_OCTEONTX3_DPI
> + tristate "OcteonTX3 DPI driver"
Is OcteonTX3 an actual product name? I thought the follow-up
to OcteonTX2 (cn9[268]xx) was the OCTEON 10 line. Or is
this a follow-up to the Marvell Armada (cn91xx) line?
> +static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
> +{
> + u64 reg;
> + u32 vf;
> +
> + reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
> + if (reg) {
> + for (vf = 0; vf < DPI_MAX_VFS; vf++) {
> + if (!(reg & (0x1UL << vf)))
> + continue;
> +
> + if (!dpi->mbox[vf]) {
> + dev_err(&dpi->pdev->dev, "bad mbox vf %d\n", vf);
> + continue;
> + }
> +
> + schedule_work(&dpi->mbox[vf]->wk.work);
> + }
> +
> + if (reg)
> + dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
> + }
> +}
> +
> +static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
> +{
> + struct dpipf *dpi = data;
> +
> + dpi_poll_pfvf_mbox(dpi);
> +
> + return IRQ_HANDLED;
> +}
Have you considered using the drivers/mailbox framework for
the mailbox portion?
> +static void dpi_pfvf_mbox_work(struct work_struct *work)
> +{
> + struct dpi_pfvf_mbox_wk *wk = container_of(work, struct
> dpi_pfvf_mbox_wk, work);
> + union dpi_mbox_message_t msg = { 0 };
> + struct dpi_mbox *mbox = NULL;
> + struct dpipf_vf *dpivf;
> + struct dpipf *dpi;
> + int vf_id;
> +
> + mbox = (struct dpi_mbox *)wk->ctxptr;
> + dpi = (struct dpipf *)mbox->pf;
Can these pointers be strictly typed instead of casting
from a void*?
> +static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
> +{
> + int vf;
> +
> + for (vf = 0; vf < DPI_MAX_VFS; vf++) {
> + dpi->mbox[vf] = vzalloc(sizeof(*dpi->mbox[vf]));
> +
dpi->mbox[vf] does not look excessively large, so I think
kzalloc() is better than vzalloc() here.
> +module_init(dpi_init_module);
> +module_exit(dpi_cleanup_module);
> +MODULE_DEVICE_TABLE(pci, dpi_id_table);
> +MODULE_AUTHOR("Marvell International Ltd.");
> +MODULE_DESCRIPTION(DPI_DRV_STRING);
> +MODULE_LICENSE("GPL");
> +MODULE_VERSION(DPI_DRV_VERSION);
Please remove the DPI_DRV_STRING and DPI_DRV_VERSION macros,
they prevent grepping for the strings.
> diff --git a/drivers/misc/mrvl-dpi/dpi.h b/drivers/misc/mrvl-dpi/dpi.h
> new file mode 100644
> index 000000000000..99ebe6bbe577
> --- /dev/null
> +++ b/drivers/misc/mrvl-dpi/dpi.h
> @@ -0,0 +1,232 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Marvell OcteonTx3 DPI driver
> + *
> + * Copyright (C) 2024 Marvell International Ltd.
> + */
> +
> +#ifndef __DPI_H__
> +#define __DPI_H__
I see no need for a separate header file if there is no other
driver including it, so just merge this all into the .c file.
> +union dpi_mbox_message_t {
> + uint64_t u[2];
> + struct dpi_mbox_message_s {
> + /* VF ID to configure */
> + uint64_t vfid :8;
> + /* Command code */
> + uint64_t cmd :4;
> + /* Command buffer size in 8-byte words */
> + uint64_t csize :14;
> + /* aura of the command buffer */
> + uint64_t aura :20;
> + /* SSO PF function */
> + uint64_t sso_pf_func :16;
> + /* NPA PF function */
> + uint64_t npa_pf_func :16;
> + /* Work queue completion status enable */
> + uint64_t wqecs :1;
> + /* Work queue completion status byte offset */
> + uint64_t wqecsoff :7;
> + } s __packed;
> +};
Is this a hardware structure? If it is, you probably don't
want to use bit fields here, even in the best case that
is a bug that prevents you from using the driver in
big-endian mode.
I also see that there are only 86 bits defined, and one
field crosses a 64-bit boundary, which feels odd.
Arnd
-----Original Message-----
From: Greg KH <[email protected]>
Sent: Wednesday, February 14, 2024 4:21 PM
To: Vamsi Krishna Attunuru <[email protected]>
Cc: [email protected]; [email protected]
Subject: [EXT] Re: [PATCH 1/1] misc: mrvl-dpi: add octeontx3 dpi driver
External Email
----------------------------------------------------------------------
On Tue, Feb 13, 2024 at 07:55:24PM -0800, Vamsi Attunuru wrote:
> Adds PCIe PF driver for OcteonTx3 DPI PF device which initializes DPI
What is a "PF"?
PF refers to physical function
WHat is "DPI"?
DPI means DMA offload unit
> DMA hardware's global configuration and enables PF-VF mbox channels
What is "PF-VF"?
It's a mailbox communication hardware between PF & VF
> which can be used by it's VF devices. This DPI PF driver handles only
What is "VF"?
VF refers to virtual function
> the resource configuration requests from VFs and it does not have any
> data movement functionality.
What do you mean by "data movement functionality"?
DPI HW has DMA offload engines which can be used from VFs for data transfer functionality.
PF function is just a management interface which mainly does global register configuration
and any per VF specific register configuration.
Please provide a bit more dummed down description please, for those of us who don't understand any of this.
Sure, I will add more description. sorry for the poor documentation.
And if this is a pci driver, why is it in misc?
DPI HW device is probed as a PCIe device, and it's PF device is more of management interface for it's VFs. It only does required hardware registration configurations and more suitable as misc device/driver. I will register it as miscdev and add required ops in next version.
Thanks, Greg, for the review comments, I will address all the below review comments in next version.
>
> Signed-off-by: Vamsi Attunuru <[email protected]>
> ---
> MAINTAINERS | 5 +
> drivers/misc/Kconfig | 10 +
> drivers/misc/Makefile | 1 +
> drivers/misc/mrvl-dpi/Makefile | 9 +
> drivers/misc/mrvl-dpi/dpi.c | 559 +++++++++++++++++++++++++++++++++
> drivers/misc/mrvl-dpi/dpi.h | 232 ++++++++++++++
> 6 files changed, 816 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS index
> 960512bec428..73029199716d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -13104,6 +13104,11 @@ S: Supported
> F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
> F: drivers/mmc/host/sdhci-xenon*
>
> +MARVELL OCTEONTX3 DPI DRIVER
> +M: Vamsi Attunuru <[email protected]>
> +S: Maintained
> +F: drivers/misc/mrvl-dpi
> +
> MATROX FRAMEBUFFER DRIVER
> L: [email protected]
> S: Orphan
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> 4fb291f0bf7c..3142fdb1b4c0 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -574,6 +574,16 @@ config NSM
> To compile this driver as a module, choose M here.
> The module will be called nsm.
>
> +config MARVELL_OCTEONTX3_DPI
> + tristate "OcteonTX3 DPI driver"
> + depends on ARM64 && PCI
> + default m
Don't set a default unless you can not boot the box without it.
> + help
> + Enables OCTEONTX3 DPI driver which intializes DPI PF device's global configuration
> + and it's VFs resource configuration to enable DMA transfers. DPI PF device
> + does not have any data movement functionality, it only serves VF's resource
> + configuration requests.
module name?
> +
> source "drivers/misc/c2port/Kconfig"
> source "drivers/misc/eeprom/Kconfig"
> source "drivers/misc/cb710/Kconfig"
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> ea6ea5bbbc9c..86229072166c 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
> obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
> obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
> obj-$(CONFIG_NSM) += nsm.o
> +obj-$(CONFIG_MARVELL_OCTEONTX3_DPI) += mrvl-dpi/
> diff --git a/drivers/misc/mrvl-dpi/Makefile
> b/drivers/misc/mrvl-dpi/Makefile new file mode 100644 index
> 000000000000..c938ea459483
> --- /dev/null
> +++ b/drivers/misc/mrvl-dpi/Makefile
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Makefile for Marvell's OcteonTX3 DPI driver #
> +
> +obj-$(CONFIG_MARVELL_OCTEONTX3_DPI) += octeontx3_dpi.o
> +
> +octeontx3_dpi-y := dpi.o
Why the two steps? Why not just name the file the module name?
And because of that, why do you need a subdirectory?
And if you do have a subdirectory, why not move the Kconfig entry into it? You can't have it both ways here, sorry.
> +
> diff --git a/drivers/misc/mrvl-dpi/dpi.c b/drivers/misc/mrvl-dpi/dpi.c
> new file mode 100644 index 000000000000..fe0b3ee469c8
> --- /dev/null
> +++ b/drivers/misc/mrvl-dpi/dpi.c
> @@ -0,0 +1,559 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Marvell OcteonTx3 DPI driver
> + *
> + * Copyright (C) 2024 Marvell International Ltd.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/pci.h>
> +#include <linux/irq.h>
> +#include <linux/interrupt.h>
> +
> +#include "dpi.h"
Why do you need a .h file for a single .c file?
> +
> +#define DPI_DRV_NAME "OcteonTx3-dpi"
> +#define DPI_DRV_STRING "Marvell OcteonTx3 DPI Driver"
> +#define DPI_DRV_VERSION "1.0"
Driver versions do not make sense once they are in the kernel tree, please remove.
> +static int mps = 128;
> +module_param(mps, int, 0644);
> +MODULE_PARM_DESC(mps, "Maximum payload size, Supported sizes are 128,
> +256, 512 and 1024 bytes");
> +
> +static int mrrs = 128;
> +module_param(mrrs, int, 0644);
> +MODULE_PARM_DESC(mrrs, "Maximum read request size, Supported sizes
> +are 128, 256, 512 and 1024 bytes");
> +
> +static unsigned long eng_fifo_buf = 0x101008080808;
> +module_param(eng_fifo_buf, ulong, 0644);
> +MODULE_PARM_DESC(eng_fifo_buf, "Per engine buffer size. Each byte
> +corresponds to engine number");
This is not the 1990's, no module parameters should be needed, and they don't work at all when you have multiple devices. Please make this "just work" and if you have to tune it, make them proper dynamic options at runtime.
> + while (cnt) {
> + reg = dpi_reg_read(dpi, DPI_DMAX_QRST(queue));
> + --cnt;
> + if (!(reg & 0x1))
> + break;
> + }
That's a long busy-wait loop, one that will take a variable amount of time given different processor speeds. Shouldn't you be using a real timeout instead?
> +
> + if (reg & 0x1)
> + dev_err(&dpi->pdev->dev, "Queue reset failed\n");
What can userspace do with this message? And why not return an error if an error happened? Why are you ignoring it here?
> +
> + dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), 0ULL);
> + dpi_reg_write(dpi, DPI_DMAX_IDS(queue), 0ULL);
> +
> + reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
> + dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(queue), reg);
> +
> + reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(queue));
> + reg |= DPI_DMA_IDS2_INST_AURA(aura);
> + dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), reg);
> +
> + reg = dpi_reg_read(dpi, DPI_DMAX_IDS(queue));
> + reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
> + reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
> + reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
> + reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
> + dpi_reg_write(dpi, DPI_DMAX_IDS(queue), reg);
> +
> + spin_unlock(&dpi->vf_lock);
> +
> + return 0;
Shouldn't you have returned an error if one happened?
> +static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf,
> +union dpi_mbox_message_t *msg) {
> + switch (msg->s.cmd) {
> + case DPI_QUEUE_OPEN:
> + dpivf->vf_config.aura = msg->s.aura;
> + dpivf->vf_config.csize = msg->s.csize / 8;
> + dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
> + dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
> + dpi_queue_init(dpi, dpivf, msg->s.vfid);
> + if (msg->s.wqecs)
> + dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
> + dpivf->setup_done = true;
> + break;
> + case DPI_QUEUE_OPEN_V2:
> + dpivf->vf_config.aura = msg->s.aura;
> + dpivf->vf_config.csize = msg->s.csize;
> + dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
> + dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
> + dpi_queue_init(dpi, dpivf, msg->s.vfid);
> + if (msg->s.wqecs)
> + dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
> + dpivf->setup_done = true;
> + break;
> + case DPI_QUEUE_CLOSE:
> + dpivf->vf_config.aura = 0;
> + dpivf->vf_config.csize = 0;
> + dpivf->vf_config.sso_pf_func = 0;
> + dpivf->vf_config.npa_pf_func = 0;
> + dpi_queue_fini(dpi, dpivf, msg->s.vfid);
> + dpivf->setup_done = false;
> + break;
> + default:
> + return -1;
That is not a valid error number :(
> +static int __init dpi_init_module(void) {
> + pr_info("%s: %s\n", DPI_DRV_NAME, DPI_DRV_STRING);
When drivers work properly, they are quiet. No need for this.
> +
> + return pci_register_driver(&dpi_driver); }
> +
> +static void __exit dpi_cleanup_module(void) {
> + pci_unregister_driver(&dpi_driver);
> +}
> +
> +module_init(dpi_init_module);
> +module_exit(dpi_cleanup_module);
module_pci_driver() instead? That will automatically get rid of the
pr_info() spam above :)
thanks,
greg k-h
> -----Original Message-----
> From: Arnd Bergmann <[email protected]>
> Sent: Wednesday, February 14, 2024 4:53 PM
> To: Vamsi Krishna Attunuru <[email protected]>; Greg Kroah-Hartman
> <[email protected]>
> Cc: [email protected]
> Subject: [EXT] Re: [PATCH 1/1] misc: mrvl-dpi: add octeontx3 dpi driver
>
> External Email
>
> ----------------------------------------------------------------------
> On Wed, Feb 14, 2024, at 04:55, Vamsi Attunuru wrote:
> > Adds PCIe PF driver for OcteonTx3 DPI PF device which initializes DPI
> > DMA hardware's global configuration and enables PF-VF mbox channels
> > which can be used by it's VF devices. This DPI PF driver handles only
> > the resource configuration requests from VFs and it does not have any
> > data movement functionality.
> >
> > Signed-off-by: Vamsi Attunuru <[email protected]>
>
> This looks incomplete, as there is no apparent interface to actually use the
> driver from either userspace or kernel. I understand that you want to merge
> this one step at a time, but please try to at least point out how this is
> intended to be used, or post it together with an (in-kernel) user if you plan to
> upstream that.
>
Sure, I will address this in next version. Thanks for the feedback.
> Is this used for anything other than networking? If not, maybe it should be
> part of drivers/net/ instead of drivers/misc.
>
It's DMA offload hardware, not used for networking. The DPI PF function is a simple management interface for global & per VF configurations.
> A few more things that Greg hasn't already commented on:
>
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > 4fb291f0bf7c..3142fdb1b4c0 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -574,6 +574,16 @@ config NSM
> > To compile this driver as a module, choose M here.
> > The module will be called nsm.
> >
> > +config MARVELL_OCTEONTX3_DPI
> > + tristate "OcteonTX3 DPI driver"
>
> Is OcteonTX3 an actual product name? I thought the follow-up to OcteonTX2
> (cn9[268]xx) was the OCTEON 10 line. Or is this a follow-up to the Marvell
> Armada (cn91xx) line?
>
Yes, it's OCTEON10/OcteonTX3.
> > +static void dpi_poll_pfvf_mbox(struct dpipf *dpi) {
> > + u64 reg;
> > + u32 vf;
> > +
> > + reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
> > + if (reg) {
> > + for (vf = 0; vf < DPI_MAX_VFS; vf++) {
> > + if (!(reg & (0x1UL << vf)))
> > + continue;
> > +
> > + if (!dpi->mbox[vf]) {
> > + dev_err(&dpi->pdev->dev, "bad mbox vf
> %d\n", vf);
> > + continue;
> > + }
> > +
> > + schedule_work(&dpi->mbox[vf]->wk.work);
> > + }
> > +
> > + if (reg)
> > + dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
> > + }
> > +}
> > +
> > +static irqreturn_t dpi_mbox_intr_handler(int irq, void *data) {
> > + struct dpipf *dpi = data;
> > +
> > + dpi_poll_pfvf_mbox(dpi);
> > +
> > + return IRQ_HANDLED;
> > +}
>
> Have you considered using the drivers/mailbox framework for the mailbox
> portion?
>
DPI HW mailbox might not fit fully into the drivers/mailbox framework. I will double check once.
>
> > +static void dpi_pfvf_mbox_work(struct work_struct *work) {
> > + struct dpi_pfvf_mbox_wk *wk = container_of(work, struct
> > dpi_pfvf_mbox_wk, work);
> > + union dpi_mbox_message_t msg = { 0 };
> > + struct dpi_mbox *mbox = NULL;
> > + struct dpipf_vf *dpivf;
> > + struct dpipf *dpi;
> > + int vf_id;
> > +
> > + mbox = (struct dpi_mbox *)wk->ctxptr;
> > + dpi = (struct dpipf *)mbox->pf;
>
> Can these pointers be strictly typed instead of casting from a void*?
>
Yes
> > +static int dpi_pfvf_mbox_setup(struct dpipf *dpi) {
> > + int vf;
> > +
> > + for (vf = 0; vf < DPI_MAX_VFS; vf++) {
> > + dpi->mbox[vf] = vzalloc(sizeof(*dpi->mbox[vf]));
> > +
>
> dpi->mbox[vf] does not look excessively large, so I think
> kzalloc() is better than vzalloc() here.
>
ack
> > +module_init(dpi_init_module);
> > +module_exit(dpi_cleanup_module);
> > +MODULE_DEVICE_TABLE(pci, dpi_id_table); MODULE_AUTHOR("Marvell
> > +International Ltd."); MODULE_DESCRIPTION(DPI_DRV_STRING);
> > +MODULE_LICENSE("GPL");
> > +MODULE_VERSION(DPI_DRV_VERSION);
>
> Please remove the DPI_DRV_STRING and DPI_DRV_VERSION macros, they
> prevent grepping for the strings.
>
ack
> > diff --git a/drivers/misc/mrvl-dpi/dpi.h b/drivers/misc/mrvl-dpi/dpi.h
> > new file mode 100644 index 000000000000..99ebe6bbe577
> > --- /dev/null
> > +++ b/drivers/misc/mrvl-dpi/dpi.h
> > @@ -0,0 +1,232 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/* Marvell OcteonTx3 DPI driver
> > + *
> > + * Copyright (C) 2024 Marvell International Ltd.
> > + */
> > +
> > +#ifndef __DPI_H__
> > +#define __DPI_H__
>
> I see no need for a separate header file if there is no other driver including it,
> so just merge this all into the .c file.
>
Sure, will merge into .c file.
> > +union dpi_mbox_message_t {
> > + uint64_t u[2];
> > + struct dpi_mbox_message_s {
> > + /* VF ID to configure */
> > + uint64_t vfid :8;
> > + /* Command code */
> > + uint64_t cmd :4;
> > + /* Command buffer size in 8-byte words */
> > + uint64_t csize :14;
> > + /* aura of the command buffer */
> > + uint64_t aura :20;
> > + /* SSO PF function */
> > + uint64_t sso_pf_func :16;
> > + /* NPA PF function */
> > + uint64_t npa_pf_func :16;
> > + /* Work queue completion status enable */
> > + uint64_t wqecs :1;
> > + /* Work queue completion status byte offset */
> > + uint64_t wqecsoff :7;
> > + } s __packed;
> > +};
>
> Is this a hardware structure? If it is, you probably don't want to use bit fields
> here, even in the best case that is a bug that prevents you from using the
> driver in big-endian mode.
>
> I also see that there are only 86 bits defined, and one field crosses a 64-bit
> boundary, which feels odd.
It's a software structure only, will fix the bugs.
Thanks Arnd for the review comments.
>
> Arnd
Adds a driver for Marvell CN10K DPI(DMA Engine) device's physical function
which initializes DPI DMA hardware's global configuration and enables
hardware mailbox channels between physical function (PF) and it's virtual
functions (VF). VF device drivers (User space drivers) use this hw mailbox
to communicate any required device configuration on it's respective VF
device. Accordingly, this DPI PF driver provision the VF device resources.
At the hardware level, the DPI physical function (PF) acts as a management
interface to setup the VF device resources, VF devices are only provisioned
to handle or control the actual DMA Engine's data transfer capabilities.
Signed-off-by: Vamsi Attunuru <[email protected]>
---
Changes V1 -> V2:
- Fixed return values and busy-wait loops
- Merged .h file into .c file
- Fixed directory structure
- Removed module params
- Registered the device as misc device
- Fixed other V1 review commands
MAINTAINERS | 5 +
drivers/misc/Kconfig | 12 +
drivers/misc/Makefile | 1 +
drivers/misc/mrvl_cn10k_dpi.c | 750 ++++++++++++++++++++++++++++++++++
4 files changed, 768 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 960512bec428..ab77232d583e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13104,6 +13104,11 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
+MARVELL OCTEON CN10K DPI DRIVER
+M: Vamsi Attunuru <[email protected]>
+S: Maintained
+F: drivers/misc/mrvl_cn10k_dpi.c
+
MATROX FRAMEBUFFER DRIVER
L: [email protected]
S: Orphan
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4fb291f0bf7c..9ac68f90f500 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -574,6 +574,18 @@ config NSM
To compile this driver as a module, choose M here.
The module will be called nsm.
+config MARVELL_CN10K_DPI
+ tristate "Octeon CN10K DPI driver"
+ depends on ARM64 && PCI
+ help
+ Enables Octeon CN10K DPI driver which intializes DPI PF device's global configuration
+ and it's VFs resource configuration to enable DMA transfers. DPI PF device
+ does not have any data movement functionality, it only serves VF's resource
+ configuration requests.
+
+ To compile this driver as a module, choose M here: the module
+ will be called mrvl_cn10k_dpi.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ea6ea5bbbc9c..8fa2fbf8670f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
obj-$(CONFIG_NSM) += nsm.o
+obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
new file mode 100644
index 000000000000..12e092894448
--- /dev/null
+++ b/drivers/misc/mrvl_cn10k_dpi.c
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell International Ltd.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#define DPI_DRV_NAME "mrvl-cn10k-dpi"
+
+/* PCI device IDs */
+#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
+#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xBA00
+
+/* PCI BAR nos */
+#define PCI_DPI_CFG_BAR 0
+
+/* MSI-X interrupts */
+#define DPI_MAX_REQQ_INT 32
+#define DPI_MAX_CC_INT 64
+
+/* MBOX MSI-X interrupt vector index */
+#define DPI_MBOX_PF_VF_INT_IDX 0x75
+
+#define DPI_MAX_ENGINES 6
+#define DPI_MAX_VFS 32
+
+#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & 0x3fff)
+#define DPI_DMA_IBUFF_CSIZE_GET_CSIZE(x) ((x) & 0x3fff)
+
+#define DPI_DMA_IBUFF_CSIZE_NPA_FREE (1 << 16)
+
+#define DPI_DMA_IDS_INST_STRM(x) ((uint64_t)((x) & 0xff) << 40)
+#define DPI_DMA_IDS_GET_INST_STRM(x) (((x) >> 40) & 0xff)
+
+#define DPI_DMA_IDS_DMA_STRM(x) ((uint64_t)((x) & 0xff) << 32)
+#define DPI_DMA_IDS_GET_DMA_STRM(x) (((x) >> 32) & 0xff)
+
+#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) ((uint64_t)((x) & 0xffff) << 16)
+#define DPI_DMA_IDS_GET_DMA_NPA_PF_FUNC(x) (((x) >> 16) & 0xffff)
+
+#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((uint64_t)((x) & 0xffff))
+#define DPI_DMA_IDS_GET_DMA_SSO_PF_FUNC(x) ((x) & 0xffff)
+
+#define DPI_DMA_IDS2_INST_AURA(x) ((uint64_t)((x) & 0xfffff))
+#define DPI_DMA_IDS2_GET_INST_AURA(x) ((x) & 0xfffff)
+
+#define DPI_ENG_BUF_BLKS(x) ((x) & 0x1fULL)
+#define DPI_ENG_BUF_GET_BLKS(x) ((x) & 0x1fULL)
+
+#define DPI_ENG_BUF_BASE(x) (((x) & 0x3fULL) << 16)
+#define DPI_ENG_BUF_GET_BASE(x) (((x) >> 16) & 0x3fULL)
+
+#define DPI_DMA_ENG_EN_QEN(x) ((x) & 0xffULL)
+#define DPI_DMA_ENG_EN_GET_QEN(x) ((x) & 0xffULL)
+
+#define DPI_DMA_ENG_EN_MOLR(x) (((x) & 0x3ffULL) << 32)
+#define DPI_DMA_ENG_EN_GET_MOLR(x) (((x) >> 32) & 0x3ffULL)
+
+#define DPI_DMA_CONTROL_DMA_ENB(x) (((x) & 0x3fULL) << 48)
+#define DPI_DMA_CONTROL_GET_DMA_ENB(x) (((x) >> 48) & 0x3fULL)
+
+#define DPI_DMA_CONTROL_O_ES(x) (((x) & 0x3ULL) << 15)
+#define DPI_DMA_CONTROL_GET_O_ES(x) (((x) >> 15) & 0x3ULL)
+
+#define DPI_DMA_CONTROL_O_MODE (0x1ULL << 14)
+#define DPI_DMA_CONTROL_O_NS (0x1ULL << 17)
+#define DPI_DMA_CONTROL_O_RO (0x1ULL << 18)
+#define DPI_DMA_CONTROL_O_ADD1 (0x1ULL << 19)
+#define DPI_DMA_CONTROL_LDWB (0x1ULL << 32)
+#define DPI_DMA_CONTROL_NCB_TAG_DIS (0x1ULL << 34)
+#define DPI_DMA_CONTROL_WQECSMODE1 (0x1ULL << 37)
+#define DPI_DMA_CONTROL_ZBWCSEN (0x1ULL << 39)
+#define DPI_DMA_CONTROL_WQECSOFF(offset) (((uint64_t)offset) << 40)
+#define DPI_DMA_CONTROL_WQECSDIS (0x1ULL << 47)
+#define DPI_DMA_CONTROL_UIO_DIS (0x1ULL << 55)
+#define DPI_DMA_CONTROL_PKT_EN (0x1ULL << 56)
+#define DPI_DMA_CONTROL_FFP_DIS (0x1ULL << 59)
+
+#define DPI_CTL_EN (0x1ULL)
+
+#define DPI_DMA_CC_INT (0x1ULL)
+
+#define DPI_REQQ_INT_INSTRFLT (0x1ULL)
+#define DPI_REQQ_INT_RDFLT (0x1ULL << 1)
+#define DPI_REQQ_INT_WRFLT (0x1ULL << 2)
+#define DPI_REQQ_INT_CSFLT (0x1ULL << 3)
+#define DPI_REQQ_INT_INST_DBO (0x1ULL << 4)
+#define DPI_REQQ_INT_INST_ADDR_NULL (0x1ULL << 5)
+#define DPI_REQQ_INT_INST_FILL_INVAL (0x1ULL << 6)
+#define DPI_REQQ_INT_INSTR_PSN (0x1ULL << 7)
+
+#define DPI_REQQ_INT \
+ (DPI_REQQ_INT_INSTRFLT | \
+ DPI_REQQ_INT_RDFLT | \
+ DPI_REQQ_INT_WRFLT | \
+ DPI_REQQ_INT_CSFLT | \
+ DPI_REQQ_INT_INST_DBO | \
+ DPI_REQQ_INT_INST_ADDR_NULL | \
+ DPI_REQQ_INT_INST_FILL_INVAL | \
+ DPI_REQQ_INT_INSTR_PSN)
+
+#define DPI_PF_RAS_EBI_DAT_PSN (0x1ULL)
+#define DPI_PF_RAS_NCB_DAT_PSN (0x1ULL << 1)
+
+#define DPI_PF_RAS_NCB_CMD_PSN (0x1ULL << 2)
+#define DPI_PF_RAS_INT \
+ (DPI_PF_RAS_EBI_DAT_PSN | \
+ DPI_PF_RAS_NCB_DAT_PSN | \
+ DPI_PF_RAS_NCB_CMD_PSN)
+
+#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
+#define DPI_DMAX_REQBANK0(x) (0x8ULL | ((x) << 11))
+#define DPI_DMAX_REQBANK1(x) (0x10ULL | ((x) << 11))
+#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
+#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
+#define DPI_DMAX_IFLIGHT(x) (0x28ULL | ((x) << 11))
+#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
+#define DPI_DMAX_ERR_RSP_STATUS(x) (0x38ULL | ((x) << 11))
+
+#define DPI_CSCLK_ACTIVE_PC 0x10000ULL
+#define DPI_CTL 0x10010ULL
+#define DPI_DMA_CONTROL (0x10018ULL)
+#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
+#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
+
+#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
+#define DPI_EBUS_PORTX_ERR_INFO(x) (0x10200ULL | ((x) << 3))
+#define DPI_EBUS_PORTX_ERR(x) (0x10280ULL | ((x) << 3))
+
+#define DPI_PF_RAS (0x10308ULL)
+#define DPI_PF_RAS_ENA_W1C (0x10318ULL)
+
+#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
+
+#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
+#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
+
+#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
+#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
+
+#define DPI_MBOX_VF_PF_INT (0x16300ULL)
+#define DPI_MBOX_VF_PF_INT_W1S (0x16308ULL)
+#define DPI_MBOX_VF_PF_INT_ENA_W1C (0x16310ULL)
+#define DPI_MBOX_VF_PF_INT_ENA_W1S (0x16318ULL)
+
+#define DPI_WCTL_FIF_THR (0x17008ULL)
+
+#define DPI_EBUS_MAX_PORTS 2
+#define DPI_EBUS_PORTX_CFG_MRRS(x) (((x) & 0x7) << 0)
+#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & 0x7) << 4)
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+#define DPI_QUEUE_OPEN_V2 0x5
+
+enum dpi_mbox_word_type {
+ DPI_MBOX_TYPE_CMD,
+ DPI_MBOX_TYPE_RSP_ACK,
+ DPI_MBOX_TYPE_RSP_NACK,
+};
+
+struct dpivf_config {
+ uint16_t csize;
+ uint32_t aura;
+ uint16_t sso_pf_func;
+ uint16_t npa_pf_func;
+};
+
+struct dpipf_vf {
+ uint8_t this_vfid;
+ bool setup_done;
+ struct dpivf_config vf_config;
+};
+
+/* DPI device mailbox */
+struct dpi_mbox {
+ struct work_struct work;
+ struct mutex lock;
+ struct dpipf *pf;
+ u8 __iomem *pf_vf_data_reg;
+ u8 __iomem *vf_pf_data_reg;
+ u32 vf_id;
+};
+
+struct dpipf {
+ struct miscdevice miscdev;
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ int num_irqs;
+ int total_vfs;
+ struct dpipf_vf vf[DPI_MAX_VFS];
+ struct msix_entry *msix_entries;
+ /* Mailbox to talk to VFs */
+ struct dpi_mbox *mbox[DPI_MAX_VFS];
+ /* lock to serialize vf register access */
+ spinlock_t vf_lock;
+};
+
+union dpi_mbox_message_t {
+ uint64_t u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ uint64_t vfid :8;
+ /* Command code */
+ uint64_t cmd :4;
+ /* Command buffer size in 8-byte words */
+ uint64_t csize :14;
+ /* aura of the command buffer */
+ uint64_t aura :20;
+ /* SSO PF function */
+ uint64_t sso_pf_func :16;
+ /* NPA PF function */
+ uint64_t npa_pf_func :16;
+ /* Work queue completion status enable */
+ uint64_t wqecs :1;
+ /* Work queue completion status byte offset */
+ uint64_t wqecsoff :7;
+ /* Reserved */
+ uint64_t rsvd :42;
+ } s __packed;
+};
+
+static void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
+{
+ writeq(val, dpi->reg_base + offset);
+}
+
+static u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
+{
+ return readq(dpi->reg_base + offset);
+}
+
+static int dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
+{
+ u64 reg = 0ULL;
+
+ spin_lock(&dpi->vf_lock);
+ reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
+ reg &= ~DPI_DMA_CONTROL_WQECSDIS;
+ reg |= DPI_DMA_CONTROL_ZBWCSEN;
+ reg |= DPI_DMA_CONTROL_WQECSMODE1;
+ reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ spin_unlock(&dpi->vf_lock);
+
+ return 0;
+}
+
+static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
+ u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
+ u16 csize = dpivf->vf_config.csize;
+ u32 aura = dpivf->vf_config.aura;
+ unsigned long timeout;
+ int queue = vf;
+ u64 reg = 0ULL;
+
+ spin_lock(&dpi->vf_lock);
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(queue), 0x1ULL);
+
+ /* Wait for a maximum of 3 sec */
+ timeout = jiffies + msecs_to_jiffies(3000);
+ while (!time_after(jiffies, timeout)) {
+ reg = dpi_reg_read(dpi, DPI_DMAX_QRST(queue));
+ if (!(reg & 0x1))
+ break;
+
+ usleep_range(500, 1000);
+ }
+
+ if (reg & 0x1) {
+ dev_err(&dpi->pdev->dev, "Queue reset failed\n");
+ spin_unlock(&dpi->vf_lock);
+ return -EBUSY;
+ }
+
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), 0ULL);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(queue), 0ULL);
+
+ reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
+ dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(queue), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(queue));
+ reg |= DPI_DMA_IDS2_INST_AURA(aura);
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS(queue));
+ reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
+ reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
+ reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
+ reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(queue), reg);
+
+ spin_unlock(&dpi->vf_lock);
+
+ return 0;
+}
+
+static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ int queue = vf;
+
+ spin_lock(&dpi->vf_lock);
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(queue), 0x1ULL);
+
+ /* Reset IDS and IDS2 registers */
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(queue), 0ULL);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(queue), 0ULL);
+
+ spin_unlock(&dpi->vf_lock);
+}
+
+static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
+{
+ u64 reg;
+ u32 vf;
+
+ reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
+ if (reg) {
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ if (!(reg & (0x1UL << vf)))
+ continue;
+
+ if (!dpi->mbox[vf]) {
+ dev_err(&dpi->pdev->dev, "bad mbox vf %d\n", vf);
+ continue;
+ }
+
+ schedule_work(&dpi->mbox[vf]->work);
+ }
+
+ if (reg)
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
+ }
+}
+
+static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
+{
+ struct dpipf *dpi = data;
+
+ dpi_poll_pfvf_mbox(dpi);
+
+ return IRQ_HANDLED;
+}
+
+static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
+{
+ int ret = 0;
+
+ switch (msg->s.cmd) {
+ case DPI_QUEUE_OPEN:
+ case DPI_QUEUE_OPEN_V2:
+ dpivf->vf_config.aura = msg->s.aura;
+ dpivf->vf_config.csize = (msg->s.cmd == DPI_QUEUE_OPEN) ? (msg->s.csize / 8) :
+ msg->s.csize;
+ dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
+ ret = dpi_queue_init(dpi, dpivf, msg->s.vfid);
+ if (!ret) {
+ if (msg->s.wqecs)
+ dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
+ dpivf->setup_done = true;
+ }
+ break;
+ case DPI_QUEUE_CLOSE:
+ dpivf->vf_config.aura = 0;
+ dpivf->vf_config.csize = 0;
+ dpivf->vf_config.sso_pf_func = 0;
+ dpivf->vf_config.npa_pf_func = 0;
+ dpi_queue_fini(dpi, dpivf, msg->s.vfid);
+ dpivf->setup_done = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void dpi_pfvf_mbox_work(struct work_struct *work)
+{
+ struct dpi_mbox *mbox = container_of(work, struct dpi_mbox, work);
+ union dpi_mbox_message_t msg = { 0 };
+ struct dpipf_vf *dpivf;
+ struct dpipf *dpi;
+ int vf_id;
+
+ dpi = mbox->pf;
+ vf_id = mbox->vf_id;
+
+ mutex_lock(&mbox->lock);
+ msg.u[0] = readq(mbox->vf_pf_data_reg);
+ if (unlikely(msg.u[0] == 0xFFFFFFFFFFFFFFFFU))
+ goto exit;
+
+ if (msg.s.vfid > dpi->total_vfs) {
+ dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
+ goto exit;
+ }
+
+ dpivf = &dpi->vf[msg.s.vfid];
+ msg.u[1] = readq(mbox->pf_vf_data_reg);
+
+ if (queue_config(dpi, dpivf, &msg) < 0)
+ writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);
+ else
+ writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
+exit:
+ mutex_unlock(&mbox->lock);
+}
+
+/* Setup registers for a PF mailbox */
+static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf_id)
+{
+ struct dpi_mbox *mbox = dpi->mbox[vf_id];
+
+ mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf_id);
+ mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf_id);
+}
+
+static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
+{
+ int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ dpi->mbox[vf] = kzalloc(sizeof(*dpi->mbox[vf]), GFP_KERNEL);
+
+ if (!dpi->mbox[vf])
+ goto free_mbox;
+
+ memset(dpi->mbox[vf], 0, sizeof(struct dpi_mbox));
+ mutex_init(&dpi->mbox[vf]->lock);
+ INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
+ dpi->mbox[vf]->pf = dpi;
+ dpi->mbox[vf]->vf_id = vf;
+ dpi_setup_mbox_regs(dpi, vf);
+ }
+
+ return 0;
+
+free_mbox:
+ while (vf) {
+ vf--;
+ cancel_work_sync(&dpi->mbox[vf]->work);
+ mutex_destroy(&dpi->mbox[vf]->lock);
+ vfree(dpi->mbox[vf]);
+ dpi->mbox[vf] = NULL;
+ }
+
+ return -ENOMEM;
+}
+
+static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
+{
+ int vf_id;
+
+ for (vf_id = 0; vf_id < DPI_MAX_VFS; vf_id++) {
+ if (!dpi->mbox[vf_id])
+ continue;
+
+ if (work_pending(&dpi->mbox[vf_id]->work))
+ cancel_work_sync(&dpi->mbox[vf_id]->work);
+
+ mutex_destroy(&dpi->mbox[vf_id]->lock);
+ vfree(dpi->mbox[vf_id]);
+ dpi->mbox[vf_id] = NULL;
+ }
+}
+
+static int dpi_init(struct dpipf *dpi)
+{
+ u8 mrrs_val, mps_val;
+ int engine, port = 0;
+ u64 reg;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ if (engine == 4 || engine == 5)
+ reg = DPI_ENG_BUF_BLKS(16);
+ else
+ reg = DPI_ENG_BUF_BLKS(8);
+
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+ }
+
+ reg = 0ULL;
+ reg = (DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
+ DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB(0x3fULL));
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
+
+ mrrs_val = 2; /* 512B */
+ mps_val = 1; /* 256B */
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ reg |= (DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val));
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ /* Set the write control FIFO threshold as per HW recommendation */
+ dpi_reg_write(dpi, DPI_WCTL_FIF_THR, 0x30);
+
+ return 0;
+}
+
+static int dpi_fini(struct dpipf *dpi)
+{
+ int engine = 0, port;
+ u64 reg = 0ULL;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES ; engine++)
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, reg);
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ return 0;
+}
+
+static int dpi_irq_init(struct dpipf *dpi)
+{
+ int i, ret, num_msix = 1;
+
+ /* Clear all RAS interrupts */
+ dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
+
+ /* Clear all RAS interrupt enable bits */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ dpi->msix_entries = kcalloc(num_msix, sizeof(struct msix_entry), GFP_KERNEL);
+ if (!dpi->msix_entries)
+ return -ENOMEM;
+
+ for (i = 0; i < num_msix; i++)
+ dpi->msix_entries[i].entry = DPI_MBOX_PF_VF_INT_IDX;
+
+ ret = pci_enable_msix_range(dpi->pdev, dpi->msix_entries, num_msix, num_msix);
+ if (ret != num_msix) {
+ dev_err(&dpi->pdev->dev, "DPI: Failed to enable %d msix irqs; got only %d\n",
+ num_msix, ret);
+ goto enable_msix_err;
+ }
+
+ dpi->num_irqs = ret;
+ dev_info(&dpi->pdev->dev, "DPI: MSI-X enabled successfully\n");
+
+ ret = request_irq(dpi->msix_entries[0].vector, dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
+ if (ret) {
+ dev_err(&dpi->pdev->dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
+ goto enable_msix_err;
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, 0xFFFFFFFF);
+
+ return 0;
+
+enable_msix_err:
+ if (dpi->num_irqs > 0)
+ pci_disable_msix(dpi->pdev);
+ kfree(dpi->msix_entries);
+ dpi->msix_entries = NULL;
+ return ret;
+}
+
+static void dpi_irq_free(struct dpipf *dpi)
+{
+ int i = 0;
+
+ /* Clear All Enables */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ for (i = 0; i < dpi->num_irqs; i++)
+ free_irq(pci_irq_vector(dpi->pdev, DPI_MBOX_PF_VF_INT_IDX), dpi);
+
+ pci_free_irq_vectors(dpi->pdev);
+ kfree(dpi->msix_entries);
+ dpi->msix_entries = NULL;
+ dpi->num_irqs = 0;
+}
+
+static int dpi_sriov_configure(struct pci_dev *pdev, int numvfs)
+{
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+ int ret = 0;
+
+ if (numvfs == 0) {
+ pci_disable_sriov(pdev);
+ dpi->total_vfs = 0;
+ } else {
+ ret = pci_enable_sriov(pdev, numvfs);
+ if (ret == 0) {
+ dpi->total_vfs = numvfs;
+ ret = numvfs;
+ }
+ }
+
+ return ret;
+}
+
+static const struct file_operations dpi_device_fops = {
+ .owner = THIS_MODULE,
+};
+
+static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi->pdev = pdev;
+
+ ret = pcim_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to enable PCI device\n");
+ goto err_dpi_free;
+ }
+
+ ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to request MMIO region\n");
+ goto err_dpi_free;
+ }
+
+ dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
+
+ /* Initialize global PF registers */
+ ret = dpi_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize dpi\n");
+ goto err_dpi_free;
+ }
+
+ /* Setup PF-VF mailbox */
+ ret = dpi_pfvf_mbox_setup(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
+ goto err_dpi_fini;
+ }
+
+ /* Register interrupts */
+ ret = dpi_irq_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize irq vectors\n");
+ goto err_dpi_mbox_free;
+ }
+
+ pci_set_drvdata(pdev, dpi);
+ spin_lock_init(&dpi->vf_lock);
+
+ dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dpi->miscdev.name = DPI_DRV_NAME;
+ dpi->miscdev.fops = &dpi_device_fops;
+ dpi->miscdev.parent = dev;
+ ret = misc_register(&dpi->miscdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to register misc device\n");
+ goto err_dpi_irq_free;
+ }
+
+ return 0;
+
+err_dpi_irq_free:
+ dpi_irq_free(dpi);
+err_dpi_mbox_free:
+ dpi_pfvf_mbox_destroy(dpi);
+err_dpi_fini:
+ dpi_fini(dpi);
+err_dpi_free:
+ devm_kfree(dev, dpi);
+ return ret;
+}
+
+static void dpi_remove(struct pci_dev *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+
+ misc_deregister(&dpi->miscdev);
+ dpi_irq_free(dpi);
+ dpi_pfvf_mbox_destroy(dpi);
+ dpi_fini(dpi);
+ dpi_sriov_configure(pdev, 0);
+ pci_set_drvdata(pdev, NULL);
+ devm_kfree(dev, dpi);
+}
+
+static const struct pci_device_id dpi_id_table[] = {
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_MRVL_CN10K_DPI_PF,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
+ { 0, } /* end of table */
+};
+
+static struct pci_driver dpi_driver = {
+ .name = DPI_DRV_NAME,
+ .id_table = dpi_id_table,
+ .probe = dpi_probe,
+ .remove = dpi_remove,
+ .sriov_configure = dpi_sriov_configure,
+};
+
+module_pci_driver(dpi_driver);
+MODULE_DEVICE_TABLE(pci, dpi_id_table);
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
On Fri, Feb 16, 2024 at 02:32:25AM -0800, Vamsi Attunuru wrote:
> Adds a driver for Marvell CN10K DPI(DMA Engine) device's physical function
> which initializes DPI DMA hardware's global configuration and enables
> hardware mailbox channels between physical function (PF) and it's virtual
> functions (VF). VF device drivers (User space drivers) use this hw mailbox
> to communicate any required device configuration on it's respective VF
> device. Accordingly, this DPI PF driver provision the VF device resources.
>
> At the hardware level, the DPI physical function (PF) acts as a management
> interface to setup the VF device resources, VF devices are only provisioned
> to handle or control the actual DMA Engine's data transfer capabilities.
>
> Signed-off-by: Vamsi Attunuru <[email protected]>
> ---
>
> Changes V1 -> V2:
> - Fixed return values and busy-wait loops
> - Merged .h file into .c file
> - Fixed directory structure
> - Removed module params
> - Registered the device as misc device
Why register as a misc device if you don't actually use it at all? That
feels pointless and extra code and confusion for everyone as you have
created a device node in the system that will just fail all operations
made on it.
confused,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Saturday, February 17, 2024 1:44 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; [email protected]
> Subject: [EXT] Re: [PATCH v2 1/1] misc: mrvl-cn10k-dpi: add Octeon CN10K
> dpi driver
>
> External Email
>
> ----------------------------------------------------------------------
> On Fri, Feb 16, 2024 at 02:32:25AM -0800, Vamsi Attunuru wrote:
> > Adds a driver for Marvell CN10K DPI(DMA Engine) device's physical
> > function which initializes DPI DMA hardware's global configuration and
> > enables hardware mailbox channels between physical function (PF) and
> > it's virtual functions (VF). VF device drivers (User space drivers)
> > use this hw mailbox to communicate any required device configuration
> > on it's respective VF device. Accordingly, this DPI PF driver provision the VF
> device resources.
> >
> > At the hardware level, the DPI physical function (PF) acts as a
> > management interface to setup the VF device resources, VF devices are
> > only provisioned to handle or control the actual DMA Engine's data transfer
> capabilities.
> >
> > Signed-off-by: Vamsi Attunuru <[email protected]>
> > ---
> >
> > Changes V1 -> V2:
> > - Fixed return values and busy-wait loops
> > - Merged .h file into .c file
> > - Fixed directory structure
> > - Removed module params
> > - Registered the device as misc device
>
> Why register as a misc device if you don't actually use it at all? That feels
> pointless and extra code and confusion for everyone as you have created a
> device node in the system that will just fail all operations made on it.
>
> confused,
>
Module params are removed in V2, planning to use device node to pass the device configuration tuning parameters and other ops, can you please also share other v2 review comments, I will plan to address it in V3.
> greg k-h
On Mon, Feb 19, 2024 at 05:03:38AM +0000, Vamsi Krishna Attunuru wrote:
> > -----Original Message-----
> > From: Greg KH <[email protected]>
> > Sent: Saturday, February 17, 2024 1:44 PM
> > To: Vamsi Krishna Attunuru <[email protected]>
> > Cc: [email protected]; [email protected]
> > Subject: [EXT] Re: [PATCH v2 1/1] misc: mrvl-cn10k-dpi: add Octeon CN10K
> > dpi driver
Why is this here?
> > External Email
> >
> > ----------------------------------------------------------------------
> > On Fri, Feb 16, 2024 at 02:32:25AM -0800, Vamsi Attunuru wrote:
> > > Adds a driver for Marvell CN10K DPI(DMA Engine) device's physical
> > > function which initializes DPI DMA hardware's global configuration and
> > > enables hardware mailbox channels between physical function (PF) and
> > > it's virtual functions (VF). VF device drivers (User space drivers)
> > > use this hw mailbox to communicate any required device configuration
> > > on it's respective VF device. Accordingly, this DPI PF driver provision the VF
> > device resources.
> > >
> > > At the hardware level, the DPI physical function (PF) acts as a
> > > management interface to setup the VF device resources, VF devices are
> > > only provisioned to handle or control the actual DMA Engine's data transfer
> > capabilities.
> > >
> > > Signed-off-by: Vamsi Attunuru <[email protected]>
> > > ---
> > >
> > > Changes V1 -> V2:
> > > - Fixed return values and busy-wait loops
> > > - Merged .h file into .c file
> > > - Fixed directory structure
> > > - Removed module params
> > > - Registered the device as misc device
> >
> > Why register as a misc device if you don't actually use it at all? That feels
> > pointless and extra code and confusion for everyone as you have created a
> > device node in the system that will just fail all operations made on it.
> >
> > confused,
> >
>
> Module params are removed in V2, planning to use device node to pass the device configuration tuning parameters and other ops, can you please also share other v2 review comments, I will plan to address it in V3.
How is a reviewer supposed to know that you are going to use unused code
sometime in the future when you do not say that here?
What would you do if you had to review such code? You would stop there
and wait for it all to make sense.
Please try to get some internal review next time before you send out
your next version so that you don't waste other's time reviewing dead
code like this.
thanks,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Monday, February 19, 2024 11:49 AM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; [email protected]
> Subject: Re: [EXT] Re: [PATCH v2 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K dpi driver
>
> On Mon, Feb 19, 2024 at 05:03:38AM +0000, Vamsi Krishna Attunuru wrote:
> > > -----Original Message-----
> > > From: Greg KH <[email protected]>
> > > Sent: Saturday, February 17, 2024 1:44 PM
> > > To: Vamsi Krishna Attunuru <[email protected]>
> > > Cc: [email protected]; [email protected]
> > > Subject: [EXT] Re: [PATCH v2 1/1] misc: mrvl-cn10k-dpi: add Octeon
> > > CN10K dpi driver
>
> Why is this here?
>
> > > External Email
> > >
> > > --------------------------------------------------------------------
> > > -- On Fri, Feb 16, 2024 at 02:32:25AM -0800, Vamsi Attunuru wrote:
> > > > Adds a driver for Marvell CN10K DPI(DMA Engine) device's physical
> > > > function which initializes DPI DMA hardware's global configuration
> > > > and enables hardware mailbox channels between physical function
> > > > (PF) and it's virtual functions (VF). VF device drivers (User
> > > > space drivers) use this hw mailbox to communicate any required
> > > > device configuration on it's respective VF device. Accordingly,
> > > > this DPI PF driver provision the VF
> > > device resources.
> > > >
> > > > At the hardware level, the DPI physical function (PF) acts as a
> > > > management interface to setup the VF device resources, VF devices
> > > > are only provisioned to handle or control the actual DMA Engine's
> > > > data transfer
> > > capabilities.
> > > >
> > > > Signed-off-by: Vamsi Attunuru <[email protected]>
> > > > ---
> > > >
> > > > Changes V1 -> V2:
> > > > - Fixed return values and busy-wait loops
> > > > - Merged .h file into .c file
> > > > - Fixed directory structure
> > > > - Removed module params
> > > > - Registered the device as misc device
> > >
> > > Why register as a misc device if you don't actually use it at all?
> > > That feels pointless and extra code and confusion for everyone as
> > > you have created a device node in the system that will just fail all
> operations made on it.
> > >
> > > confused,
> > >
> >
> > Module params are removed in V2, planning to use device node to pass the
> device configuration tuning parameters and other ops, can you please also
> share other v2 review comments, I will plan to address it in V3.
>
> How is a reviewer supposed to know that you are going to use unused code
> sometime in the future when you do not say that here?
>
> What would you do if you had to review such code? You would stop there
> and wait for it all to make sense.
>
> Please try to get some internal review next time before you send out your
> next version so that you don't waste other's time reviewing dead code like
> this.
Sure, sorry for the inconvenience.
>
> thanks,
>
> greg k-h
Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
function which initializes DPI DMA hardware's global configuration and
enables hardware mailbox channels between physical function (PF) and
it's virtual functions (VF). VF device drivers (User space drivers) use
this hw mailbox to communicate any required device configuration on it's
respective VF device. Accordingly, this DPI PF driver provisions the
VF device resources.
At the hardware level, the DPI physical function (PF) acts as a management
interface to setup the VF device resources, VF devices are only provisioned
to handle or control the actual DMA Engine's data transfer capabilities.
Signed-off-by: Vamsi Attunuru <[email protected]>
---
Changes V2 -> V3:
- Added ioctl operation to the fops
- Used managed version of kzalloc & request_irq
- Addressed miscellaneous comments
Changes V1 -> V2:
- Fixed return values and busy-wait loops
- Merged .h file into .c file
- Fixed directory structure
- Removed module params
- Registered the device as misc device
MAINTAINERS | 5 +
drivers/misc/Kconfig | 12 +
drivers/misc/Makefile | 1 +
drivers/misc/mrvl_cn10k_dpi.c | 717 ++++++++++++++++++++++++++++++++++
4 files changed, 735 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 960512bec428..ab77232d583e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13104,6 +13104,11 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
+MARVELL OCTEON CN10K DPI DRIVER
+M: Vamsi Attunuru <[email protected]>
+S: Maintained
+F: drivers/misc/mrvl_cn10k_dpi.c
+
MATROX FRAMEBUFFER DRIVER
L: [email protected]
S: Orphan
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4fb291f0bf7c..58de5844ecef 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -574,6 +574,18 @@ config NSM
To compile this driver as a module, choose M here.
The module will be called nsm.
+config MARVELL_CN10K_DPI
+ tristate "Octeon CN10K DPI driver"
+ depends on ARM64 && PCI
+ help
+ Enables Octeon CN10K DPI driver which intializes DPI PF device's global configuration
+ and its VFs resource configuration to enable DMA transfers. DPI PF device
+ does not have any data movement functionality, it only serves VF's resource
+ configuration requests.
+
+ To compile this driver as a module, choose M here: the module
+ will be called mrvl_cn10k_dpi.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ea6ea5bbbc9c..8fa2fbf8670f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
obj-$(CONFIG_NSM) += nsm.o
+obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
new file mode 100644
index 000000000000..3d33395feaa3
--- /dev/null
+++ b/drivers/misc/mrvl_cn10k_dpi.c
@@ -0,0 +1,717 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#define DPI_DRV_NAME "mrvl-cn10k-dpi"
+
+/* PCI device IDs */
+#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
+#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xBA00
+
+/* PCI BAR nos */
+#define PCI_DPI_CFG_BAR 0
+
+/* MSI-X interrupts */
+#define DPI_MAX_REQQ_INT 32
+#define DPI_MAX_CC_INT 64
+
+/* MBOX MSI-X interrupt vector index */
+#define DPI_MBOX_PF_VF_INT_IDX 0x75
+
+#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
+
+#define DPI_MAX_ENGINES 6
+#define DPI_MAX_VFS 32
+
+#define DPI_ENGINE_MASK GENMASK(2, 0)
+
+#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) ((u64)((x) & GENMASK(15, 0)) << 16)
+#define DPI_DMA_IDS_INST_STRM(x) ((u64)((x) & GENMASK(7, 0)) << 40)
+#define DPI_DMA_IDS_DMA_STRM(x) ((u64)((x) & GENMASK(7, 0)) << 32)
+#define DPI_DMA_ENG_EN_MOLR(x) ((u64)((x) & GENMASK(9, 0)) << 32)
+#define DPI_EBUS_PORTX_CFG_MPS(x) ((x) & GENMASK(2, 0) << 4)
+#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) & GENMASK(15, 0))
+#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19, 0))
+#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13, 0))
+#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2, 0))
+#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5, 0))
+#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)
+
+#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
+#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
+#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
+#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
+#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
+#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
+#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
+#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
+
+#define DPI_CTL_EN BIT_ULL(0)
+#define DPI_DMA_CC_INT BIT_ULL(0)
+#define DPI_DMA_QRST BIT_ULL(0)
+
+#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
+#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
+#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
+#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
+#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
+#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
+#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
+#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
+
+#define DPI_REQQ_INT \
+ (DPI_REQQ_INT_INSTRFLT | \
+ DPI_REQQ_INT_RDFLT | \
+ DPI_REQQ_INT_WRFLT | \
+ DPI_REQQ_INT_CSFLT | \
+ DPI_REQQ_INT_INST_DBO | \
+ DPI_REQQ_INT_INST_ADDR_NULL | \
+ DPI_REQQ_INT_INST_FILL_INVAL | \
+ DPI_REQQ_INT_INSTR_PSN)
+
+#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
+#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
+#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
+
+#define DPI_PF_RAS_INT \
+ (DPI_PF_RAS_EBI_DAT_PSN | \
+ DPI_PF_RAS_NCB_DAT_PSN | \
+ DPI_PF_RAS_NCB_CMD_PSN)
+
+#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
+#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
+#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
+#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
+
+#define DPI_CTL 0x10010ULL
+#define DPI_DMA_CONTROL 0x10018ULL
+#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
+#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
+
+#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
+
+#define DPI_PF_RAS 0x10308ULL
+#define DPI_PF_RAS_ENA_W1C 0x10318ULL
+
+#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
+
+#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
+#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
+
+#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
+#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
+
+#define DPI_MBOX_VF_PF_INT 0x16300ULL
+#define DPI_MBOX_VF_PF_INT_W1S 0x16308ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
+
+#define DPI_WCTL_FIF_THR 0x17008ULL
+
+#define DPI_EBUS_MAX_PORTS 2
+
+#define DPI_EBUS_MRRS_MIN 128
+#define DPI_EBUS_MRRS_MAX 1024
+#define DPI_EBUS_MPS_MIN 128
+#define DPI_EBUS_MPS_MAX 1024
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+#define DPI_QUEUE_OPEN_V2 0x5
+
+#define DPI_MAGIC_NUM 0xf
+
+struct dpi_mps_mrrs_cfg {
+ u16 mrrs; /* Max read request size */
+ u16 mps; /* Max packet size */
+ u8 port; /* Ebus port */
+};
+
+struct dpi_engine_cfg {
+ u64 fifo_mask; /* FIFO size mask in KBytes */
+ u16 molr[DPI_MAX_ENGINES];
+ u8 update_molr; /* '1' to update engine MOLR */
+};
+
+enum dpi_mbox_rsp_type {
+ DPI_MBOX_TYPE_CMD,
+ DPI_MBOX_TYPE_RSP_ACK,
+ DPI_MBOX_TYPE_RSP_NACK,
+};
+
+struct dpivf_config {
+ u16 csize;
+ u32 aura;
+ u16 sso_pf_func;
+ u16 npa_pf_func;
+};
+
+struct dpipf_vf {
+ u8 this_vfid;
+ bool setup_done;
+ struct dpivf_config vf_config;
+};
+
+/* DPI device mailbox */
+struct dpi_mbox {
+ struct work_struct work;
+ /* lock to serialize mbox requests */
+ struct mutex lock;
+ struct dpipf *pf;
+ u8 __iomem *pf_vf_data_reg;
+ u8 __iomem *vf_pf_data_reg;
+};
+
+struct dpipf {
+ struct miscdevice miscdev;
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ struct dpipf_vf vf[DPI_MAX_VFS];
+ /* Mailbox to talk to VFs */
+ struct dpi_mbox *mbox[DPI_MAX_VFS];
+};
+
+union dpi_mbox_message_t {
+ u64 u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ u64 vfid :8;
+ /* Command code */
+ u64 cmd :4;
+ /* Command buffer size in 8-byte words */
+ u64 csize :14;
+ /* aura of the command buffer */
+ u64 aura :20;
+ /* SSO PF function */
+ u64 sso_pf_func :16;
+ /* NPA PF function */
+ u64 npa_pf_func :16;
+ /* Work queue completion status enable */
+ u64 wqecs :1;
+ /* Work queue completion status byte offset */
+ u64 wqecsoff :7;
+ /* Reserved */
+ u64 rsvd :42;
+ } s __packed;
+};
+
+/* Set MPS & MRRS parameters */
+#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 0, struct dpi_mps_mrrs_cfg)
+
+/* Set Engine FIFO configuration */
+#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 1, struct dpi_engine_cfg)
+
+static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
+{
+ writeq(val, dpi->reg_base + offset);
+}
+
+static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
+{
+ return readq(dpi->reg_base + offset);
+}
+
+static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
+{
+ u64 reg;
+
+ reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
+ reg &= ~DPI_DMA_CONTROL_WQECSDIS;
+ reg |= DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_WQECSMODE1;
+ reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+}
+
+static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
+ u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
+ u16 csize = dpivf->vf_config.csize;
+ u32 aura = dpivf->vf_config.aura;
+ unsigned long timeout;
+ u64 reg;
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Wait for a maximum of 3 sec */
+ timeout = jiffies + msecs_to_jiffies(3000);
+ while (!time_after(jiffies, timeout)) {
+ reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf));
+ if (!(reg & DPI_DMA_QRST))
+ break;
+
+ usleep_range(500, 1000);
+ }
+
+ if (reg & DPI_DMA_QRST) {
+ dev_err(&dpi->pdev->dev, "Queue reset failed\n");
+ return -EBUSY;
+ }
+
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+
+ reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
+ dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf));
+ reg |= DPI_DMA_IDS2_INST_AURA(aura);
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf));
+ reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
+ reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
+ reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
+ reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
+
+ return 0;
+}
+
+static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Reset IDS and IDS2 registers */
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+}
+
+static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
+{
+ u64 reg;
+ u32 vf;
+
+ reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
+ if (reg) {
+ for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) {
+ if (reg & BIT_ULL(vf)) {
+ if (!dpi->mbox[vf]) {
+ dev_err(&dpi->pdev->dev, "bad mbox vf %d\n", vf);
+ continue;
+ }
+ schedule_work(&dpi->mbox[vf]->work);
+ }
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
+ }
+}
+
+static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
+{
+ struct dpipf *dpi = data;
+
+ dpi_poll_pfvf_mbox(dpi);
+
+ return IRQ_HANDLED;
+}
+
+static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
+{
+ int ret = 0;
+
+ switch (msg->s.cmd) {
+ case DPI_QUEUE_OPEN:
+ case DPI_QUEUE_OPEN_V2:
+ dpivf->vf_config.aura = msg->s.aura;
+ dpivf->vf_config.csize = (msg->s.cmd == DPI_QUEUE_OPEN) ? (msg->s.csize / 8) :
+ msg->s.csize;
+ dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
+ ret = dpi_queue_init(dpi, dpivf, msg->s.vfid);
+ if (!ret) {
+ if (msg->s.wqecs)
+ dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
+ dpivf->setup_done = true;
+ }
+ break;
+ case DPI_QUEUE_CLOSE:
+ dpivf->vf_config.aura = 0;
+ dpivf->vf_config.csize = 0;
+ dpivf->vf_config.sso_pf_func = 0;
+ dpivf->vf_config.npa_pf_func = 0;
+ dpi_queue_fini(dpi, dpivf, msg->s.vfid);
+ dpivf->setup_done = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void dpi_pfvf_mbox_work(struct work_struct *work)
+{
+ struct dpi_mbox *mbox = container_of(work, struct dpi_mbox, work);
+ union dpi_mbox_message_t msg = { 0 };
+ struct dpipf_vf *dpivf;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = mbox->pf;
+
+ mutex_lock(&mbox->lock);
+ msg.u[0] = readq(mbox->vf_pf_data_reg);
+ if (unlikely(msg.u[0] == GENMASK_ULL(63, 0)))
+ goto exit;
+
+ if (msg.s.vfid >= pci_num_vf(dpi->pdev)) {
+ dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
+ goto exit;
+ }
+
+ dpivf = &dpi->vf[msg.s.vfid];
+ msg.u[1] = readq(mbox->pf_vf_data_reg);
+
+ ret = queue_config(dpi, dpivf, &msg);
+ if (ret < 0)
+ writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);
+ else
+ writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
+exit:
+ mutex_unlock(&mbox->lock);
+}
+
+/* Setup registers for a PF mailbox */
+static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf)
+{
+ struct dpi_mbox *mbox = dpi->mbox[vf];
+
+ mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf);
+ mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf);
+}
+
+static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
+{
+ int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev, sizeof(*dpi->mbox[vf]), GFP_KERNEL);
+
+ if (!dpi->mbox[vf])
+ goto free_mbox;
+
+ mutex_init(&dpi->mbox[vf]->lock);
+ INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
+ dpi->mbox[vf]->pf = dpi;
+ dpi_setup_mbox_regs(dpi, vf);
+ }
+
+ return 0;
+
+free_mbox:
+ while (vf--) {
+ cancel_work_sync(&dpi->mbox[vf]->work);
+ dpi->mbox[vf] = NULL;
+ }
+
+ return -ENOMEM;
+}
+
+static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
+{
+ unsigned int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ if (!dpi->mbox[vf])
+ continue;
+
+ if (work_pending(&dpi->mbox[vf]->work))
+ cancel_work_sync(&dpi->mbox[vf]->work);
+
+ dpi->mbox[vf] = NULL;
+ }
+}
+
+static void dpi_init(struct dpipf *dpi)
+{
+ unsigned int engine, port;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ if (engine == 4 || engine == 5)
+ reg = DPI_ENG_BUF_BLKS(16);
+ else
+ reg = DPI_ENG_BUF_BLKS(8);
+
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+ }
+
+ reg = DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
+ DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB;
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
+
+ mrrs_val = 2; /* 512B */
+ mps_val = 1; /* 256B */
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(7) | DPI_EBUS_PORTX_CFG_MPS(7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ /* Set the write control FIFO threshold as per HW recommendation */
+ dpi_reg_write(dpi, DPI_WCTL_FIF_THR, 0x30);
+}
+
+static void dpi_fini(struct dpipf *dpi)
+{
+ unsigned int engine;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++)
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
+ dpi_reg_write(dpi, DPI_CTL, 0);
+}
+
+static int dpi_irq_init(struct dpipf *dpi)
+{
+ struct pci_dev *pdev = dpi->pdev;
+ int i, ret;
+
+ /* Clear all RAS interrupts */
+ dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
+
+ /* Clear all RAS interrupt enable bits */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ ret = pci_alloc_irq_vectors(pdev, DPI_MAX_IRQS, DPI_MAX_IRQS, PCI_IRQ_MSIX);
+ if (ret != DPI_MAX_IRQS) {
+ dev_err(&pdev->dev, "DPI: Failed to alloc %d msix irqs\n", DPI_MAX_IRQS);
+ return ret;
+ }
+
+ ret = devm_request_irq(&pdev->dev, pci_irq_vector(pdev, DPI_MBOX_PF_VF_INT_IDX),
+ dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
+ if (ret) {
+ dev_err(&pdev->dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
+ return ret;
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));
+
+ return 0;
+}
+
+static void dpi_free_irq_vectors(void *pdev)
+{
+ pci_free_irq_vectors((struct pci_dev *)pdev);
+}
+
+static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_mps_mrrs_cfg cfg;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_mps_mrrs_cfg)))
+ return -EFAULT;
+
+ if (cfg.mrrs < DPI_EBUS_MRRS_MIN || cfg.mrrs > DPI_EBUS_MRRS_MAX ||
+ !is_power_of_2(cfg.mrrs)) {
+ dev_err(&dpi->pdev->dev, "Invalid MRRS size:%u\n", cfg.mrrs);
+ return -EINVAL;
+ }
+
+ if (cfg.mps < DPI_EBUS_MPS_MIN || cfg.mps > DPI_EBUS_MPS_MAX ||
+ !is_power_of_2(cfg.mps)) {
+ dev_err(&dpi->pdev->dev, "Invalid MPS size:%u\n", cfg.mps);
+ return -EINVAL;
+ }
+
+ if (cfg.port >= DPI_EBUS_MAX_PORTS) {
+ dev_err(&dpi->pdev->dev, "Invalid EBUS port:%u\n", cfg.mps);
+ return -EINVAL;
+ }
+
+ mrrs_val = fls(cfg.mrrs) - 8;
+ mps_val = fls(cfg.mps) - 8;
+
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
+
+ return 0;
+}
+
+static int dpi_engine_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_engine_cfg cfg;
+ unsigned int engine;
+ u8 *eng_buf;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_engine_cfg)))
+ return -EFAULT;
+
+ eng_buf = (u8 *)&cfg.fifo_mask;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ reg = DPI_ENG_BUF_BLKS(eng_buf[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+
+ if (cfg.update_molr) {
+ reg = DPI_DMA_ENG_EN_MOLR(cfg.molr[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg);
+ }
+ }
+
+ return 0;
+}
+
+static long dpi_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data)
+{
+ void __user *arg = (void __user *)data;
+ struct dpipf *dpi;
+ int ret = -EINVAL;
+
+ dpi = container_of(fptr->private_data, struct dpipf, miscdev);
+
+ switch (cmd) {
+ case DPI_MPS_MRRS_CFG:
+ ret = dpi_mps_mrrs_config(dpi, arg);
+ break;
+ case DPI_ENGINE_CFG:
+ ret = dpi_engine_config(dpi, arg);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static const struct file_operations dpi_device_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = dpi_dev_ioctl,
+ .compat_ioctl = compat_ptr_ioctl,
+};
+
+static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi->pdev = pdev;
+
+ ret = pcim_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to enable PCI device\n");
+ return ret;
+ }
+
+ ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to request MMIO region\n");
+ return ret;
+ }
+
+ dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
+
+ /* Initialize global PF registers */
+ dpi_init(dpi);
+
+ /* Setup PF-VF mailbox */
+ ret = dpi_pfvf_mbox_setup(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
+ goto err_dpi_fini;
+ }
+
+ ret = devm_add_action(dev, dpi_free_irq_vectors, pdev);
+ if (ret)
+ goto err_dpi_mbox_free;
+
+ /* Register interrupts */
+ ret = dpi_irq_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize irq vectors\n");
+ goto err_dpi_mbox_free;
+ }
+
+ pci_set_drvdata(pdev, dpi);
+ dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dpi->miscdev.name = DPI_DRV_NAME;
+ dpi->miscdev.fops = &dpi_device_fops;
+ dpi->miscdev.parent = dev;
+
+ ret = misc_register(&dpi->miscdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to register misc device\n");
+ goto err_dpi_mbox_free;
+ }
+
+ return 0;
+
+err_dpi_mbox_free:
+ dpi_pfvf_mbox_destroy(dpi);
+err_dpi_fini:
+ dpi_fini(dpi);
+ return ret;
+}
+
+static void dpi_remove(struct pci_dev *pdev)
+{
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+
+ misc_deregister(&dpi->miscdev);
+ pci_sriov_configure_simple(pdev, 0);
+ dpi_pfvf_mbox_destroy(dpi);
+ dpi_fini(dpi);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id dpi_id_table[] = {
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_MRVL_CN10K_DPI_PF,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
+ { 0, } /* end of table */
+};
+
+static struct pci_driver dpi_driver = {
+ .name = DPI_DRV_NAME,
+ .id_table = dpi_id_table,
+ .probe = dpi_probe,
+ .remove = dpi_remove,
+ .sriov_configure = pci_sriov_configure_simple,
+};
+
+module_pci_driver(dpi_driver);
+MODULE_DEVICE_TABLE(pci, dpi_id_table);
+MODULE_AUTHOR("Marvell.");
+MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
On Wed, Feb 28, 2024 at 08:21:41AM -0800, Vamsi Attunuru wrote:
> Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> function which initializes DPI DMA hardware's global configuration and
> enables hardware mailbox channels between physical function (PF) and
> it's virtual functions (VF). VF device drivers (User space drivers) use
> this hw mailbox to communicate any required device configuration on it's
> respective VF device. Accordingly, this DPI PF driver provisions the
> VF device resources.
>
> At the hardware level, the DPI physical function (PF) acts as a management
> interface to setup the VF device resources, VF devices are only provisioned
> to handle or control the actual DMA Engine's data transfer capabilities.
>
> Signed-off-by: Vamsi Attunuru <[email protected]>
> ---
> Changes V2 -> V3:
> - Added ioctl operation to the fops
> - Used managed version of kzalloc & request_irq
> - Addressed miscellaneous comments
>
> Changes V1 -> V2:
> - Fixed return values and busy-wait loops
> - Merged .h file into .c file
> - Fixed directory structure
> - Removed module params
> - Registered the device as misc device
>
> MAINTAINERS | 5 +
> drivers/misc/Kconfig | 12 +
> drivers/misc/Makefile | 1 +
> drivers/misc/mrvl_cn10k_dpi.c | 717 ++++++++++++++++++++++++++++++++++
> 4 files changed, 735 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 960512bec428..ab77232d583e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -13104,6 +13104,11 @@ S: Supported
> F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
> F: drivers/mmc/host/sdhci-xenon*
>
> +MARVELL OCTEON CN10K DPI DRIVER
> +M: Vamsi Attunuru <[email protected]>
> +S: Maintained
> +F: drivers/misc/mrvl_cn10k_dpi.c
> +
> MATROX FRAMEBUFFER DRIVER
> L: [email protected]
> S: Orphan
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 4fb291f0bf7c..58de5844ecef 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -574,6 +574,18 @@ config NSM
> To compile this driver as a module, choose M here.
> The module will be called nsm.
>
> +config MARVELL_CN10K_DPI
> + tristate "Octeon CN10K DPI driver"
> + depends on ARM64 && PCI
> + help
> + Enables Octeon CN10K DPI driver which intializes DPI PF device's global configuration
> + and its VFs resource configuration to enable DMA transfers. DPI PF device
> + does not have any data movement functionality, it only serves VF's resource
> + configuration requests.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called mrvl_cn10k_dpi.
> +
> source "drivers/misc/c2port/Kconfig"
> source "drivers/misc/eeprom/Kconfig"
> source "drivers/misc/cb710/Kconfig"
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index ea6ea5bbbc9c..8fa2fbf8670f 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
> obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
> obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
> obj-$(CONFIG_NSM) += nsm.o
> +obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
> diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
> new file mode 100644
> index 000000000000..3d33395feaa3
> --- /dev/null
> +++ b/drivers/misc/mrvl_cn10k_dpi.c
> @@ -0,0 +1,717 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Marvell Octeon CN10K DPI driver
> + *
> + * Copyright (C) 2024 Marvell.
> + *
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/miscdevice.h>
> +#include <linux/module.h>
> +#include <linux/pci.h>
> +#include <linux/irq.h>
> +#include <linux/interrupt.h>
> +
> +#define DPI_DRV_NAME "mrvl-cn10k-dpi"
> +
> +/* PCI device IDs */
> +#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
> +#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xBA00
> +
> +/* PCI BAR nos */
> +#define PCI_DPI_CFG_BAR 0
> +
> +/* MSI-X interrupts */
> +#define DPI_MAX_REQQ_INT 32
> +#define DPI_MAX_CC_INT 64
> +
> +/* MBOX MSI-X interrupt vector index */
> +#define DPI_MBOX_PF_VF_INT_IDX 0x75
> +
> +#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
> +
> +#define DPI_MAX_ENGINES 6
> +#define DPI_MAX_VFS 32
> +
> +#define DPI_ENGINE_MASK GENMASK(2, 0)
> +
> +#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) ((u64)((x) & GENMASK(15, 0)) << 16)
> +#define DPI_DMA_IDS_INST_STRM(x) ((u64)((x) & GENMASK(7, 0)) << 40)
> +#define DPI_DMA_IDS_DMA_STRM(x) ((u64)((x) & GENMASK(7, 0)) << 32)
> +#define DPI_DMA_ENG_EN_MOLR(x) ((u64)((x) & GENMASK(9, 0)) << 32)
> +#define DPI_EBUS_PORTX_CFG_MPS(x) ((x) & GENMASK(2, 0) << 4)
> +#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) & GENMASK(15, 0))
> +#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19, 0))
> +#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13, 0))
> +#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2, 0))
> +#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5, 0))
> +#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)
> +
> +#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
> +#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
> +#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
> +#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
> +#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
> +#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
> +#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
> +#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
> +
> +#define DPI_CTL_EN BIT_ULL(0)
> +#define DPI_DMA_CC_INT BIT_ULL(0)
> +#define DPI_DMA_QRST BIT_ULL(0)
> +
> +#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
> +#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
> +#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
> +#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
> +#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
> +#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
> +#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
> +#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
> +
> +#define DPI_REQQ_INT \
> + (DPI_REQQ_INT_INSTRFLT | \
> + DPI_REQQ_INT_RDFLT | \
> + DPI_REQQ_INT_WRFLT | \
> + DPI_REQQ_INT_CSFLT | \
> + DPI_REQQ_INT_INST_DBO | \
> + DPI_REQQ_INT_INST_ADDR_NULL | \
> + DPI_REQQ_INT_INST_FILL_INVAL | \
> + DPI_REQQ_INT_INSTR_PSN)
> +
> +#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
> +#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
> +#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
> +
> +#define DPI_PF_RAS_INT \
> + (DPI_PF_RAS_EBI_DAT_PSN | \
> + DPI_PF_RAS_NCB_DAT_PSN | \
> + DPI_PF_RAS_NCB_CMD_PSN)
> +
> +#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
> +#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
> +#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
> +#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
> +
> +#define DPI_CTL 0x10010ULL
> +#define DPI_DMA_CONTROL 0x10018ULL
> +#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
> +#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
> +
> +#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
> +
> +#define DPI_PF_RAS 0x10308ULL
> +#define DPI_PF_RAS_ENA_W1C 0x10318ULL
> +
> +#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
> +#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
> +
> +#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
> +#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
> +
> +#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
> +#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
> +
> +#define DPI_MBOX_VF_PF_INT 0x16300ULL
> +#define DPI_MBOX_VF_PF_INT_W1S 0x16308ULL
> +#define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
> +#define DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
> +
> +#define DPI_WCTL_FIF_THR 0x17008ULL
> +
> +#define DPI_EBUS_MAX_PORTS 2
> +
> +#define DPI_EBUS_MRRS_MIN 128
> +#define DPI_EBUS_MRRS_MAX 1024
> +#define DPI_EBUS_MPS_MIN 128
> +#define DPI_EBUS_MPS_MAX 1024
> +
> +#define DPI_QUEUE_OPEN 0x1
> +#define DPI_QUEUE_CLOSE 0x2
> +#define DPI_REG_DUMP 0x3
> +#define DPI_GET_REG_CFG 0x4
> +#define DPI_QUEUE_OPEN_V2 0x5
> +
> +#define DPI_MAGIC_NUM 0xf
> +
> +struct dpi_mps_mrrs_cfg {
> + u16 mrrs; /* Max read request size */
> + u16 mps; /* Max packet size */
> + u8 port; /* Ebus port */
> +};
> +
> +struct dpi_engine_cfg {
> + u64 fifo_mask; /* FIFO size mask in KBytes */
> + u16 molr[DPI_MAX_ENGINES];
> + u8 update_molr; /* '1' to update engine MOLR */
> +};
> +
> +enum dpi_mbox_rsp_type {
> + DPI_MBOX_TYPE_CMD,
> + DPI_MBOX_TYPE_RSP_ACK,
> + DPI_MBOX_TYPE_RSP_NACK,
> +};
> +
> +struct dpivf_config {
> + u16 csize;
> + u32 aura;
> + u16 sso_pf_func;
> + u16 npa_pf_func;
> +};
> +
> +struct dpipf_vf {
> + u8 this_vfid;
> + bool setup_done;
> + struct dpivf_config vf_config;
> +};
> +
> +/* DPI device mailbox */
> +struct dpi_mbox {
> + struct work_struct work;
> + /* lock to serialize mbox requests */
> + struct mutex lock;
> + struct dpipf *pf;
> + u8 __iomem *pf_vf_data_reg;
> + u8 __iomem *vf_pf_data_reg;
> +};
> +
> +struct dpipf {
> + struct miscdevice miscdev;
> + void __iomem *reg_base;
> + struct pci_dev *pdev;
> + struct dpipf_vf vf[DPI_MAX_VFS];
> + /* Mailbox to talk to VFs */
> + struct dpi_mbox *mbox[DPI_MAX_VFS];
> +};
> +
> +union dpi_mbox_message_t {
> + u64 u[2];
> + struct dpi_mbox_message_s {
> + /* VF ID to configure */
> + u64 vfid :8;
> + /* Command code */
> + u64 cmd :4;
> + /* Command buffer size in 8-byte words */
> + u64 csize :14;
> + /* aura of the command buffer */
> + u64 aura :20;
> + /* SSO PF function */
> + u64 sso_pf_func :16;
> + /* NPA PF function */
> + u64 npa_pf_func :16;
> + /* Work queue completion status enable */
> + u64 wqecs :1;
> + /* Work queue completion status byte offset */
> + u64 wqecsoff :7;
> + /* Reserved */
> + u64 rsvd :42;
> + } s __packed;
> +};
> +
> +/* Set MPS & MRRS parameters */
> +#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 0, struct dpi_mps_mrrs_cfg)
> +
> +/* Set Engine FIFO configuration */
> +#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 1, struct dpi_engine_cfg)
How is an ioctl description living in a .c file? This obviously isn't
tested and will not work :(
And those structures will also not work properly as an ioctl, please
read the kernel documentation for how to do this correctly.
thanks,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Friday, March 8, 2024 3:26 AM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; [email protected]
> Subject: [EXTERNAL] Re: [PATCH v3 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K DPI administrative driver
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
> On Wed, Feb 28, 2024 at 08:21:41AM -0800, Vamsi Attunuru wrote:
> > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> > function which initializes DPI DMA hardware's global configuration and
> > enables hardware mailbox channels between physical function (PF) and
> > it's virtual functions (VF). VF device drivers (User space drivers)
> > use this hw mailbox to communicate any required device configuration
> > on it's respective VF device. Accordingly, this DPI PF driver
> > provisions the VF device resources.
> >
> > At the hardware level, the DPI physical function (PF) acts as a
> > management interface to setup the VF device resources, VF devices are
> > only provisioned to handle or control the actual DMA Engine's data transfer
> capabilities.
> >
> > Signed-off-by: Vamsi Attunuru <[email protected]>
> > ---
> > Changes V2 -> V3:
> > - Added ioctl operation to the fops
> > - Used managed version of kzalloc & request_irq
> > - Addressed miscellaneous comments
> >
> > Changes V1 -> V2:
> > - Fixed return values and busy-wait loops
> > - Merged .h file into .c file
> > - Fixed directory structure
> > - Removed module params
> > - Registered the device as misc device
> >
> > MAINTAINERS | 5 +
> > drivers/misc/Kconfig | 12 +
> > drivers/misc/Makefile | 1 +
> > drivers/misc/mrvl_cn10k_dpi.c | 717
> > ++++++++++++++++++++++++++++++++++
> > 4 files changed, 735 insertions(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > 960512bec428..ab77232d583e 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -13104,6 +13104,11 @@ S: Supported
> > F: Documentation/devicetree/bindings/mmc/marvell,xenon-
> sdhci.yaml
> > F: drivers/mmc/host/sdhci-xenon*
> >
> > +MARVELL OCTEON CN10K DPI DRIVER
> > +M: Vamsi Attunuru <[email protected]>
> > +S: Maintained
> > +F: drivers/misc/mrvl_cn10k_dpi.c
> > +
> > MATROX FRAMEBUFFER DRIVER
> > L: [email protected]
> > S: Orphan
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > 4fb291f0bf7c..58de5844ecef 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -574,6 +574,18 @@ config NSM
> > To compile this driver as a module, choose M here.
> > The module will be called nsm.
> >
> > +config MARVELL_CN10K_DPI
> > + tristate "Octeon CN10K DPI driver"
> > + depends on ARM64 && PCI
> > + help
> > + Enables Octeon CN10K DPI driver which intializes DPI PF device's
> global configuration
> > + and its VFs resource configuration to enable DMA transfers. DPI PF
> device
> > + does not have any data movement functionality, it only serves VF's
> resource
> > + configuration requests.
> > +
> > + To compile this driver as a module, choose M here: the module
> > + will be called mrvl_cn10k_dpi.
> > +
> > source "drivers/misc/c2port/Kconfig"
> > source "drivers/misc/eeprom/Kconfig"
> > source "drivers/misc/cb710/Kconfig"
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > ea6ea5bbbc9c..8fa2fbf8670f 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
> > obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
> > obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
> > obj-$(CONFIG_NSM) += nsm.o
> > +obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
> > diff --git a/drivers/misc/mrvl_cn10k_dpi.c
> > b/drivers/misc/mrvl_cn10k_dpi.c new file mode 100644 index
> > 000000000000..3d33395feaa3
> > --- /dev/null
> > +++ b/drivers/misc/mrvl_cn10k_dpi.c
> > @@ -0,0 +1,717 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/* Marvell Octeon CN10K DPI driver
> > + *
> > + * Copyright (C) 2024 Marvell.
> > + *
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/miscdevice.h>
> > +#include <linux/module.h>
> > +#include <linux/pci.h>
> > +#include <linux/irq.h>
> > +#include <linux/interrupt.h>
> > +
> > +#define DPI_DRV_NAME "mrvl-cn10k-dpi"
> > +
> > +/* PCI device IDs */
> > +#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
> > +#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xBA00
> > +
> > +/* PCI BAR nos */
> > +#define PCI_DPI_CFG_BAR 0
> > +
> > +/* MSI-X interrupts */
> > +#define DPI_MAX_REQQ_INT 32
> > +#define DPI_MAX_CC_INT 64
> > +
> > +/* MBOX MSI-X interrupt vector index */ #define
> > +DPI_MBOX_PF_VF_INT_IDX 0x75
> > +
> > +#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
> > +
> > +#define DPI_MAX_ENGINES 6
> > +#define DPI_MAX_VFS 32
> > +
> > +#define DPI_ENGINE_MASK GENMASK(2, 0)
> > +
> > +#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) ((u64)((x) &
> GENMASK(15, 0)) << 16)
> > +#define DPI_DMA_IDS_INST_STRM(x) ((u64)((x) &
> GENMASK(7, 0)) << 40)
> > +#define DPI_DMA_IDS_DMA_STRM(x) ((u64)((x) &
> GENMASK(7, 0)) << 32)
> > +#define DPI_DMA_ENG_EN_MOLR(x) ((u64)((x) &
> GENMASK(9, 0)) << 32)
> > +#define DPI_EBUS_PORTX_CFG_MPS(x) ((x) & GENMASK(2, 0)
> << 4)
> > +#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) &
> GENMASK(15, 0))
> > +#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19,
> 0))
> > +#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13,
> 0))
> > +#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2,
> 0))
> > +#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5,
> 0))
> > +#define DPI_DMA_CONTROL_DMA_ENB
> GENMASK_ULL(53, 48)
> > +
> > +#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
> > +#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
> > +#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
> > +#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
> > +#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
> > +#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
> > +#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
> > +#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
> > +
> > +#define DPI_CTL_EN BIT_ULL(0)
> > +#define DPI_DMA_CC_INT BIT_ULL(0)
> > +#define DPI_DMA_QRST BIT_ULL(0)
> > +
> > +#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
> > +#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
> > +#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
> > +#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
> > +#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
> > +#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
> > +#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
> > +#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
> > +
> > +#define DPI_REQQ_INT \
> > + (DPI_REQQ_INT_INSTRFLT | \
> > + DPI_REQQ_INT_RDFLT | \
> > + DPI_REQQ_INT_WRFLT | \
> > + DPI_REQQ_INT_CSFLT | \
> > + DPI_REQQ_INT_INST_DBO | \
> > + DPI_REQQ_INT_INST_ADDR_NULL | \
> > + DPI_REQQ_INT_INST_FILL_INVAL | \
> > + DPI_REQQ_INT_INSTR_PSN)
> > +
> > +#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
> > +#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
> > +#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
> > +
> > +#define DPI_PF_RAS_INT \
> > + (DPI_PF_RAS_EBI_DAT_PSN | \
> > + DPI_PF_RAS_NCB_DAT_PSN | \
> > + DPI_PF_RAS_NCB_CMD_PSN)
> > +
> > +#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
> > +#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
> > +#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
> > +#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
> > +
> > +#define DPI_CTL 0x10010ULL
> > +#define DPI_DMA_CONTROL 0x10018ULL
> > +#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
> > +#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
> > +
> > +#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
> > +
> > +#define DPI_PF_RAS 0x10308ULL
> > +#define DPI_PF_RAS_ENA_W1C 0x10318ULL
> > +
> > +#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3)) #define
> > +DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
> > +
> > +#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5)) #define
> > +DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
> > +
> > +#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4)) #define
> > +DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
> > +
> > +#define DPI_MBOX_VF_PF_INT 0x16300ULL #define
> DPI_MBOX_VF_PF_INT_W1S
> > +0x16308ULL #define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
> #define
> > +DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
> > +
> > +#define DPI_WCTL_FIF_THR 0x17008ULL
> > +
> > +#define DPI_EBUS_MAX_PORTS 2
> > +
> > +#define DPI_EBUS_MRRS_MIN 128
> > +#define DPI_EBUS_MRRS_MAX 1024
> > +#define DPI_EBUS_MPS_MIN 128
> > +#define DPI_EBUS_MPS_MAX 1024
> > +
> > +#define DPI_QUEUE_OPEN 0x1
> > +#define DPI_QUEUE_CLOSE 0x2
> > +#define DPI_REG_DUMP 0x3
> > +#define DPI_GET_REG_CFG 0x4
> > +#define DPI_QUEUE_OPEN_V2 0x5
> > +
> > +#define DPI_MAGIC_NUM 0xf
> > +
> > +struct dpi_mps_mrrs_cfg {
> > + u16 mrrs; /* Max read request size */
> > + u16 mps; /* Max packet size */
> > + u8 port; /* Ebus port */
> > +};
> > +
> > +struct dpi_engine_cfg {
> > + u64 fifo_mask; /* FIFO size mask in KBytes */
> > + u16 molr[DPI_MAX_ENGINES];
> > + u8 update_molr; /* '1' to update engine MOLR */ };
> > +
> > +enum dpi_mbox_rsp_type {
> > + DPI_MBOX_TYPE_CMD,
> > + DPI_MBOX_TYPE_RSP_ACK,
> > + DPI_MBOX_TYPE_RSP_NACK,
> > +};
> > +
> > +struct dpivf_config {
> > + u16 csize;
> > + u32 aura;
> > + u16 sso_pf_func;
> > + u16 npa_pf_func;
> > +};
> > +
> > +struct dpipf_vf {
> > + u8 this_vfid;
> > + bool setup_done;
> > + struct dpivf_config vf_config;
> > +};
> > +
> > +/* DPI device mailbox */
> > +struct dpi_mbox {
> > + struct work_struct work;
> > + /* lock to serialize mbox requests */
> > + struct mutex lock;
> > + struct dpipf *pf;
> > + u8 __iomem *pf_vf_data_reg;
> > + u8 __iomem *vf_pf_data_reg;
> > +};
> > +
> > +struct dpipf {
> > + struct miscdevice miscdev;
> > + void __iomem *reg_base;
> > + struct pci_dev *pdev;
> > + struct dpipf_vf vf[DPI_MAX_VFS];
> > + /* Mailbox to talk to VFs */
> > + struct dpi_mbox *mbox[DPI_MAX_VFS];
> > +};
> > +
> > +union dpi_mbox_message_t {
> > + u64 u[2];
> > + struct dpi_mbox_message_s {
> > + /* VF ID to configure */
> > + u64 vfid :8;
> > + /* Command code */
> > + u64 cmd :4;
> > + /* Command buffer size in 8-byte words */
> > + u64 csize :14;
> > + /* aura of the command buffer */
> > + u64 aura :20;
> > + /* SSO PF function */
> > + u64 sso_pf_func :16;
> > + /* NPA PF function */
> > + u64 npa_pf_func :16;
> > + /* Work queue completion status enable */
> > + u64 wqecs :1;
> > + /* Work queue completion status byte offset */
> > + u64 wqecsoff :7;
> > + /* Reserved */
> > + u64 rsvd :42;
> > + } s __packed;
> > +};
> > +
> > +/* Set MPS & MRRS parameters */
> > +#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 0, struct
> > +dpi_mps_mrrs_cfg)
> > +
> > +/* Set Engine FIFO configuration */
> > +#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 1, struct
> dpi_engine_cfg)
>
> How is an ioctl description living in a .c file? This obviously isn't tested and will
> not work :(
>
Thanks for the comments.
It did work in my environment that had limited configs enabled. I will move it to include/uapi/misc/*.h file and correct the ioctls as per documentation in next version.
> And those structures will also not work properly as an ioctl, please read the
> kernel documentation for how to do this correctly.
>
> thanks,
>
> greg k-h
Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
function which initializes DPI DMA hardware's global configuration and
enables hardware mailbox channels between physical function (PF) and
it's virtual functions (VF). VF device drivers (User space drivers) use
this hw mailbox to communicate any required device configuration on it's
respective VF device. Accordingly, this DPI PF driver provisions the
VF device resources.
At the hardware level, the DPI physical function (PF) acts as a management
interface to setup the VF device resources, VF devices are only provisioned
to handle or control the actual DMA Engine's data transfer capabilities.
Signed-off-by: Vamsi Attunuru <[email protected]>
---
Changes V3 -> V4:
- Moved ioctl definations to .h file
- Fixed structure alignements which are passed in ioctl
Changes V2 -> V3:
- Added ioctl operation to the fops
- Used managed version of kzalloc & request_irq
- Addressed miscellaneous comments
Changes V1 -> V2:
- Fixed return values and busy-wait loops
- Merged .h file into .c file
- Fixed directory structure
- Removed module params
- Registered the device as misc device
.../userspace-api/ioctl/ioctl-number.rst | 1 +
MAINTAINERS | 5 +
drivers/misc/Kconfig | 12 +
drivers/misc/Makefile | 1 +
drivers/misc/mrvl_cn10k_dpi.c | 685 ++++++++++++++++++
include/uapi/misc/mrvl_cn10k_dpi.h | 35 +
6 files changed, 739 insertions(+)
diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst
index 457e16f06e04..e6fd0c386b59 100644
--- a/Documentation/userspace-api/ioctl/ioctl-number.rst
+++ b/Documentation/userspace-api/ioctl/ioctl-number.rst
@@ -358,6 +358,7 @@ Code Seq# Include File Comments
0xB6 all linux/fpga-dfl.h
0xB7 all uapi/linux/remoteproc_cdev.h <mailto:[email protected]>
0xB7 all uapi/linux/nsfs.h <mailto:Andrei Vagin <[email protected]>>
+0xB8 01-02 uapi/misc/mrvl_cn10k_dpi.h Marvell CN10K DPI driver
0xC0 00-0F linux/usb/iowarrior.h
0xCA 00-0F uapi/misc/cxl.h
0xCA 10-2F uapi/misc/ocxl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 960512bec428..ab77232d583e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13104,6 +13104,11 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
+MARVELL OCTEON CN10K DPI DRIVER
+M: Vamsi Attunuru <[email protected]>
+S: Maintained
+F: drivers/misc/mrvl_cn10k_dpi.c
+
MATROX FRAMEBUFFER DRIVER
L: [email protected]
S: Orphan
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4fb291f0bf7c..58de5844ecef 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -574,6 +574,18 @@ config NSM
To compile this driver as a module, choose M here.
The module will be called nsm.
+config MARVELL_CN10K_DPI
+ tristate "Octeon CN10K DPI driver"
+ depends on ARM64 && PCI
+ help
+ Enables Octeon CN10K DPI driver which intializes DPI PF device's global configuration
+ and its VFs resource configuration to enable DMA transfers. DPI PF device
+ does not have any data movement functionality, it only serves VF's resource
+ configuration requests.
+
+ To compile this driver as a module, choose M here: the module
+ will be called mrvl_cn10k_dpi.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ea6ea5bbbc9c..8fa2fbf8670f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -68,3 +68,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
obj-$(CONFIG_NSM) += nsm.o
+obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
new file mode 100644
index 000000000000..c35bffbe8a40
--- /dev/null
+++ b/drivers/misc/mrvl_cn10k_dpi.c
@@ -0,0 +1,685 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <uapi/misc/mrvl_cn10k_dpi.h>
+
+#define DPI_DRV_NAME "mrvl-cn10k-dpi"
+
+/* PCI device IDs */
+#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
+#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xB900
+
+/* PCI BAR nos */
+#define PCI_DPI_CFG_BAR 0
+
+/* MSI-X interrupts */
+#define DPI_MAX_REQQ_INT 32
+#define DPI_MAX_CC_INT 64
+
+/* MBOX MSI-X interrupt vector index */
+#define DPI_MBOX_PF_VF_INT_IDX 0x75
+
+#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
+
+#define DPI_MAX_VFS 32
+
+#define DPI_ENGINE_MASK GENMASK(2, 0)
+
+#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) (((x) & GENMASK_ULL(15, 0)) << 16)
+#define DPI_DMA_IDS_INST_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 40)
+#define DPI_DMA_IDS_DMA_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 32)
+#define DPI_DMA_ENG_EN_MOLR(x) (((x) & GENMASK_ULL(9, 0)) << 32)
+#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & GENMASK(2, 0)) << 4)
+#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) & GENMASK(15, 0))
+#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19, 0))
+#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13, 0))
+#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2, 0))
+#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5, 0))
+#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)
+
+#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
+#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
+#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
+#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
+#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
+#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
+#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
+#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
+
+#define DPI_CTL_EN BIT_ULL(0)
+#define DPI_DMA_CC_INT BIT_ULL(0)
+#define DPI_DMA_QRST BIT_ULL(0)
+
+#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
+#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
+#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
+#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
+#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
+#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
+#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
+#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
+
+#define DPI_REQQ_INT \
+ (DPI_REQQ_INT_INSTRFLT | \
+ DPI_REQQ_INT_RDFLT | \
+ DPI_REQQ_INT_WRFLT | \
+ DPI_REQQ_INT_CSFLT | \
+ DPI_REQQ_INT_INST_DBO | \
+ DPI_REQQ_INT_INST_ADDR_NULL | \
+ DPI_REQQ_INT_INST_FILL_INVAL | \
+ DPI_REQQ_INT_INSTR_PSN)
+
+#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
+#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
+#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
+
+#define DPI_PF_RAS_INT \
+ (DPI_PF_RAS_EBI_DAT_PSN | \
+ DPI_PF_RAS_NCB_DAT_PSN | \
+ DPI_PF_RAS_NCB_CMD_PSN)
+
+#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
+#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
+#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
+#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
+
+#define DPI_CTL 0x10010ULL
+#define DPI_DMA_CONTROL 0x10018ULL
+#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
+#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
+
+#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
+
+#define DPI_PF_RAS 0x10308ULL
+#define DPI_PF_RAS_ENA_W1C 0x10318ULL
+
+#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
+
+#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
+#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
+
+#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
+#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
+
+#define DPI_MBOX_VF_PF_INT 0x16300ULL
+#define DPI_MBOX_VF_PF_INT_W1S 0x16308ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
+
+#define DPI_WCTL_FIF_THR 0x17008ULL
+
+#define DPI_EBUS_MAX_PORTS 2
+
+#define DPI_EBUS_MRRS_MIN 128
+#define DPI_EBUS_MRRS_MAX 1024
+#define DPI_EBUS_MPS_MIN 128
+#define DPI_EBUS_MPS_MAX 1024
+#define DPI_WCTL_FIFO_THRESHOLD 0x30
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+#define DPI_QUEUE_OPEN_V2 0x5
+
+enum dpi_mbox_rsp_type {
+ DPI_MBOX_TYPE_CMD,
+ DPI_MBOX_TYPE_RSP_ACK,
+ DPI_MBOX_TYPE_RSP_NACK,
+};
+
+struct dpivf_config {
+ u16 csize;
+ u32 aura;
+ u16 sso_pf_func;
+ u16 npa_pf_func;
+};
+
+struct dpipf_vf {
+ u8 this_vfid;
+ bool setup_done;
+ struct dpivf_config vf_config;
+};
+
+/* DPI device mailbox */
+struct dpi_mbox {
+ struct work_struct work;
+ /* lock to serialize mbox requests */
+ struct mutex lock;
+ struct dpipf *pf;
+ u8 __iomem *pf_vf_data_reg;
+ u8 __iomem *vf_pf_data_reg;
+};
+
+struct dpipf {
+ struct miscdevice miscdev;
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ struct dpipf_vf vf[DPI_MAX_VFS];
+ /* Mailbox to talk to VFs */
+ struct dpi_mbox *mbox[DPI_MAX_VFS];
+};
+
+union dpi_mbox_message_t {
+ u64 u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ u64 vfid :8;
+ /* Command code */
+ u64 cmd :4;
+ /* Command buffer size in 8-byte words */
+ u64 csize :14;
+ /* Aura of the command buffer */
+ u64 aura :20;
+ /* SSO PF function */
+ u64 sso_pf_func :16;
+ /* NPA PF function */
+ u64 npa_pf_func :16;
+ /* Work queue completion status enable */
+ u64 wqecs :1;
+ /* Work queue completion status byte offset */
+ u64 wqecsoff :7;
+ /* Reserved */
+ u64 rsvd :42;
+ } s __packed;
+};
+
+static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
+{
+ writeq(val, dpi->reg_base + offset);
+}
+
+static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
+{
+ return readq(dpi->reg_base + offset);
+}
+
+static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
+{
+ u64 reg;
+
+ reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
+ reg &= ~DPI_DMA_CONTROL_WQECSDIS;
+ reg |= DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_WQECSMODE1;
+ reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+}
+
+static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
+ u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
+ u16 csize = dpivf->vf_config.csize;
+ u32 aura = dpivf->vf_config.aura;
+ unsigned long timeout;
+ u64 reg;
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Wait for a maximum of 3 sec */
+ timeout = jiffies + msecs_to_jiffies(3000);
+ while (!time_after(jiffies, timeout)) {
+ reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf));
+ if (!(reg & DPI_DMA_QRST))
+ break;
+
+ usleep_range(500, 1000);
+ }
+
+ if (reg & DPI_DMA_QRST) {
+ dev_err(&dpi->pdev->dev, "Queue reset failed\n");
+ return -EBUSY;
+ }
+
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+
+ reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
+ dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf));
+ reg |= DPI_DMA_IDS2_INST_AURA(aura);
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf));
+ reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
+ reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
+ reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
+ reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
+
+ return 0;
+}
+
+static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Reset IDS and IDS2 registers */
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+}
+
+static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
+{
+ u64 reg;
+ u32 vf;
+
+ reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
+ if (reg) {
+ for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) {
+ if (reg & BIT_ULL(vf))
+ schedule_work(&dpi->mbox[vf]->work);
+ }
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
+ }
+}
+
+static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
+{
+ struct dpipf *dpi = data;
+
+ dpi_poll_pfvf_mbox(dpi);
+
+ return IRQ_HANDLED;
+}
+
+static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
+{
+ int ret = 0;
+
+ switch (msg->s.cmd) {
+ case DPI_QUEUE_OPEN:
+ case DPI_QUEUE_OPEN_V2:
+ dpivf->vf_config.aura = msg->s.aura;
+ dpivf->vf_config.csize = msg->s.cmd == DPI_QUEUE_OPEN ? msg->s.csize / 8 :
+ msg->s.csize;
+ dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
+ ret = dpi_queue_init(dpi, dpivf, msg->s.vfid);
+ if (!ret) {
+ if (msg->s.wqecs)
+ dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
+ dpivf->setup_done = true;
+ }
+ break;
+ case DPI_QUEUE_CLOSE:
+ dpivf->vf_config.aura = 0;
+ dpivf->vf_config.csize = 0;
+ dpivf->vf_config.sso_pf_func = 0;
+ dpivf->vf_config.npa_pf_func = 0;
+ dpi_queue_fini(dpi, dpivf, msg->s.vfid);
+ dpivf->setup_done = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void dpi_pfvf_mbox_work(struct work_struct *work)
+{
+ struct dpi_mbox *mbox = container_of(work, struct dpi_mbox, work);
+ union dpi_mbox_message_t msg = { 0 };
+ struct dpipf_vf *dpivf;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = mbox->pf;
+
+ mutex_lock(&mbox->lock);
+ msg.u[0] = readq(mbox->vf_pf_data_reg);
+ if (unlikely(msg.u[0] == (u64)-1))
+ goto exit;
+
+ if (unlikely(msg.s.vfid >= pci_num_vf(dpi->pdev))) {
+ dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
+ goto exit;
+ }
+
+ dpivf = &dpi->vf[msg.s.vfid];
+ msg.u[1] = readq(mbox->pf_vf_data_reg);
+
+ ret = queue_config(dpi, dpivf, &msg);
+ if (ret < 0)
+ writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);
+ else
+ writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
+exit:
+ mutex_unlock(&mbox->lock);
+}
+
+/* Setup registers for a PF mailbox */
+static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf)
+{
+ struct dpi_mbox *mbox = dpi->mbox[vf];
+
+ mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf);
+ mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf);
+}
+
+static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
+{
+ int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev, sizeof(*dpi->mbox[vf]), GFP_KERNEL);
+
+ if (!dpi->mbox[vf])
+ return -ENOMEM;
+
+ mutex_init(&dpi->mbox[vf]->lock);
+ INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
+ dpi->mbox[vf]->pf = dpi;
+ dpi_setup_mbox_regs(dpi, vf);
+ }
+
+ return 0;
+}
+
+static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
+{
+ unsigned int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ if (work_pending(&dpi->mbox[vf]->work))
+ cancel_work_sync(&dpi->mbox[vf]->work);
+
+ dpi->mbox[vf] = NULL;
+ }
+}
+
+static void dpi_init(struct dpipf *dpi)
+{
+ unsigned int engine, port;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ if (engine == 4 || engine == 5)
+ reg = DPI_ENG_BUF_BLKS(16);
+ else
+ reg = DPI_ENG_BUF_BLKS(8);
+
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+ }
+
+ reg = DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
+ DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB;
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
+
+ mrrs_val = 2; /* 512B */
+ mps_val = 1; /* 256B */
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(7) | DPI_EBUS_PORTX_CFG_MPS(7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ dpi_reg_write(dpi, DPI_WCTL_FIF_THR, DPI_WCTL_FIFO_THRESHOLD);
+}
+
+static void dpi_fini(struct dpipf *dpi)
+{
+ unsigned int engine;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++)
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
+ dpi_reg_write(dpi, DPI_CTL, 0);
+}
+
+static void dpi_free_irq_vectors(void *pdev)
+{
+ pci_free_irq_vectors((struct pci_dev *)pdev);
+}
+
+static int dpi_irq_init(struct dpipf *dpi)
+{
+ struct pci_dev *pdev = dpi->pdev;
+ struct device *dev = &pdev->dev;
+ int i, ret;
+
+ /* Clear all RAS interrupts */
+ dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
+
+ /* Clear all RAS interrupt enable bits */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ ret = pci_alloc_irq_vectors(pdev, DPI_MAX_IRQS, DPI_MAX_IRQS, PCI_IRQ_MSIX);
+ if (ret != DPI_MAX_IRQS) {
+ dev_err(dev, "DPI: Failed to alloc %d msix irqs\n", DPI_MAX_IRQS);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(dev, dpi_free_irq_vectors, pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to add irq free action\n");
+ return ret;
+ }
+
+ ret = devm_request_irq(dev, pci_irq_vector(pdev, DPI_MBOX_PF_VF_INT_IDX),
+ dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
+ if (ret) {
+ dev_err(dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
+ return ret;
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));
+
+ return 0;
+}
+
+static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_mps_mrrs_cfg cfg;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_mps_mrrs_cfg)))
+ return -EFAULT;
+
+ if (cfg.mrrs < DPI_EBUS_MRRS_MIN || cfg.mrrs > DPI_EBUS_MRRS_MAX ||
+ !is_power_of_2(cfg.mrrs)) {
+ dev_err(&dpi->pdev->dev, "Invalid MRRS size:%llu\n", cfg.mrrs);
+ return -EINVAL;
+ }
+
+ if (cfg.mps < DPI_EBUS_MPS_MIN || cfg.mps > DPI_EBUS_MPS_MAX ||
+ !is_power_of_2(cfg.mps)) {
+ dev_err(&dpi->pdev->dev, "Invalid MPS size:%llu\n", cfg.mps);
+ return -EINVAL;
+ }
+
+ if (cfg.port >= DPI_EBUS_MAX_PORTS) {
+ dev_err(&dpi->pdev->dev, "Invalid EBUS port:%llu\n", cfg.mps);
+ return -EINVAL;
+ }
+
+ mrrs_val = fls(cfg.mrrs >> 8);
+ mps_val = fls(cfg.mps >> 8);
+
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
+
+ return 0;
+}
+
+static int dpi_engine_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_engine_cfg cfg;
+ unsigned int engine;
+ u8 *eng_buf;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_engine_cfg)))
+ return -EFAULT;
+
+ eng_buf = (u8 *)&cfg.fifo_mask;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ reg = DPI_ENG_BUF_BLKS(eng_buf[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+
+ if (cfg.update_molr) {
+ reg = DPI_DMA_ENG_EN_MOLR(cfg.molr[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg);
+ }
+ }
+
+ return 0;
+}
+
+static long dpi_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data)
+{
+ void __user *arg = (void __user *)data;
+ struct dpipf *dpi;
+ int ret = -EINVAL;
+
+ dpi = container_of(fptr->private_data, struct dpipf, miscdev);
+
+ switch (cmd) {
+ case DPI_MPS_MRRS_CFG:
+ ret = dpi_mps_mrrs_config(dpi, arg);
+ break;
+ case DPI_ENGINE_CFG:
+ ret = dpi_engine_config(dpi, arg);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static const struct file_operations dpi_device_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = dpi_dev_ioctl,
+ .compat_ioctl = compat_ptr_ioctl,
+};
+
+static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi->pdev = pdev;
+
+ ret = pcim_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to enable PCI device\n");
+ return ret;
+ }
+
+ ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to request MMIO region\n");
+ return ret;
+ }
+
+ dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
+
+ /* Initialize global PF registers */
+ dpi_init(dpi);
+
+ /* Setup PF-VF mailbox */
+ ret = dpi_pfvf_mbox_setup(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
+ goto err_dpi_fini;
+ }
+
+ /* Register interrupts */
+ ret = dpi_irq_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize irq vectors\n");
+ goto err_dpi_mbox_free;
+ }
+
+ pci_set_drvdata(pdev, dpi);
+ dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dpi->miscdev.name = DPI_DRV_NAME;
+ dpi->miscdev.fops = &dpi_device_fops;
+ dpi->miscdev.parent = dev;
+
+ ret = misc_register(&dpi->miscdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to register misc device\n");
+ goto err_dpi_mbox_free;
+ }
+
+ return 0;
+
+err_dpi_mbox_free:
+ dpi_pfvf_mbox_destroy(dpi);
+err_dpi_fini:
+ dpi_fini(dpi);
+ return ret;
+}
+
+static void dpi_remove(struct pci_dev *pdev)
+{
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+
+ misc_deregister(&dpi->miscdev);
+ pci_sriov_configure_simple(pdev, 0);
+ dpi_pfvf_mbox_destroy(dpi);
+ dpi_fini(dpi);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id dpi_id_table[] = {
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_MRVL_CN10K_DPI_PF,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
+ { 0, } /* end of table */
+};
+
+static struct pci_driver dpi_driver = {
+ .name = DPI_DRV_NAME,
+ .id_table = dpi_id_table,
+ .probe = dpi_probe,
+ .remove = dpi_remove,
+ .sriov_configure = pci_sriov_configure_simple,
+};
+
+module_pci_driver(dpi_driver);
+MODULE_DEVICE_TABLE(pci, dpi_id_table);
+MODULE_AUTHOR("Marvell.");
+MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/misc/mrvl_cn10k_dpi.h b/include/uapi/misc/mrvl_cn10k_dpi.h
new file mode 100644
index 000000000000..cfd5b74ce17d
--- /dev/null
+++ b/include/uapi/misc/mrvl_cn10k_dpi.h
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#ifndef __MRVL_CN10K_DPI_H__
+#define __MRVL_CN10K_DPI_H__
+
+#include <linux/types.h>
+
+#define DPI_MAX_ENGINES 6
+
+struct dpi_mps_mrrs_cfg {
+ u64 mrrs; /* Max read request size */
+ u64 mps; /* Max packet size */
+ u64 port; /* Ebus port */
+};
+
+struct dpi_engine_cfg {
+ u64 fifo_mask; /* FIFO size mask in KBytes */
+ u64 molr[DPI_MAX_ENGINES];
+ u64 update_molr; /* '1' to update engine MOLR */
+};
+
+#define DPI_MAGIC_NUM 0xB8
+
+/* Set MPS & MRRS parameters */
+#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 1, struct dpi_mps_mrrs_cfg)
+
+/* Set Engine FIFO configuration */
+#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 2, struct dpi_engine_cfg)
+
+#endif /* __MRVL_CN10K_DPI_H__ */
--
2.25.1
On Tue, Mar 12, 2024 at 03:56:57AM -0700, Vamsi Attunuru wrote:
> --- /dev/null
> +++ b/include/uapi/misc/mrvl_cn10k_dpi.h
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0
Wrong license for a uapi file, right? Please work with your lawyers to
figure out the correct one if you have any questions.
> +/* Marvell Octeon CN10K DPI driver
> + *
> + * Copyright (C) 2024 Marvell.
> + *
> + */
> +
> +#ifndef __MRVL_CN10K_DPI_H__
> +#define __MRVL_CN10K_DPI_H__
> +
> +#include <linux/types.h>
> +
> +#define DPI_MAX_ENGINES 6
> +
> +struct dpi_mps_mrrs_cfg {
> + u64 mrrs; /* Max read request size */
> + u64 mps; /* Max packet size */
> + u64 port; /* Ebus port */
> +};
> +
> +struct dpi_engine_cfg {
> + u64 fifo_mask; /* FIFO size mask in KBytes */
> + u64 molr[DPI_MAX_ENGINES];
> + u64 update_molr; /* '1' to update engine MOLR */
This is not how you create an ioctl, please read the kernel
documentation for how to do it properly please. (hint, wrong data
types.)
Also, a pointer to the userspace code that is going to use this new api
you are creating would be apprecaited.
thanks,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Thursday, April 11, 2024 6:32 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; [email protected]
> Subject: [EXTERNAL] Re: [PATCH v4 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K DPI administrative driver
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
> On Tue, Mar 12, 2024 at 03:56:57AM -0700, Vamsi Attunuru wrote:
> > --- /dev/null
> > +++ b/include/uapi/misc/mrvl_cn10k_dpi.h
> > @@ -0,0 +1,35 @@
> > +// SPDX-License-Identifier: GPL-2.0
>
> Wrong license for a uapi file, right? Please work with your lawyers to figure
> out the correct one if you have any questions.
>
No concerns in using general licensing for uapi file, will fix in next version.
> > +/* Marvell Octeon CN10K DPI driver
> > + *
> > + * Copyright (C) 2024 Marvell.
> > + *
> > + */
> > +
> > +#ifndef __MRVL_CN10K_DPI_H__
> > +#define __MRVL_CN10K_DPI_H__
> > +
> > +#include <linux/types.h>
> > +
> > +#define DPI_MAX_ENGINES 6
> > +
> > +struct dpi_mps_mrrs_cfg {
> > + u64 mrrs; /* Max read request size */
> > + u64 mps; /* Max packet size */
> > + u64 port; /* Ebus port */
> > +};
> > +
> > +struct dpi_engine_cfg {
> > + u64 fifo_mask; /* FIFO size mask in KBytes */
> > + u64 molr[DPI_MAX_ENGINES];
> > + u64 update_molr; /* '1' to update engine MOLR */
>
> This is not how you create an ioctl, please read the kernel documentation for
> how to do it properly please. (hint, wrong data
> types.)
Sure, will send next version with the fixes( u64 --> __u64). Thanks.
>
> Also, a pointer to the userspace code that is going to use this new api you are
> creating would be apprecaited.
>
> thanks,
>
> greg k-h
Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
function which initializes DPI DMA hardware's global configuration and
enables hardware mailbox channels between physical function (PF) and
it's virtual functions (VF). VF device drivers (User space drivers) use
this hw mailbox to communicate any required device configuration on it's
respective VF device. Accordingly, this DPI PF driver provisions the
VF device resources.
At the hardware level, the DPI physical function (PF) acts as a management
interface to setup the VF device resources, VF devices are only provisioned
to handle or control the actual DMA Engine's data transfer capabilities.
Signed-off-by: Vamsi Attunuru <[email protected]>
---
Changes V4 -> V5:
- Fixed license and data types in uapi file
Changes V3 -> V4:
- Moved ioctl definations to .h file
- Fixed structure alignements which are passed in ioctl
Changes V2 -> V3:
- Added ioctl operation to the fops
- Used managed version of kzalloc & request_irq
- Addressed miscellaneous comments
Changes V1 -> V2:
- Fixed return values and busy-wait loops
- Merged .h file into .c file
- Fixed directory structure
- Removed module params
- Registered the device as misc device
.../userspace-api/ioctl/ioctl-number.rst | 1 +
MAINTAINERS | 5 +
drivers/misc/Kconfig | 12 +
drivers/misc/Makefile | 2 +
drivers/misc/mrvl_cn10k_dpi.c | 685 ++++++++++++++++++
include/uapi/misc/mrvl_cn10k_dpi.h | 36 +
6 files changed, 741 insertions(+)
diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst
index 457e16f06e04..e6fd0c386b59 100644
--- a/Documentation/userspace-api/ioctl/ioctl-number.rst
+++ b/Documentation/userspace-api/ioctl/ioctl-number.rst
@@ -358,6 +358,7 @@ Code Seq# Include File Comments
0xB6 all linux/fpga-dfl.h
0xB7 all uapi/linux/remoteproc_cdev.h <mailto:[email protected]>
0xB7 all uapi/linux/nsfs.h <mailto:Andrei Vagin <[email protected]>>
+0xB8 01-02 uapi/misc/mrvl_cn10k_dpi.h Marvell CN10K DPI driver
0xC0 00-0F linux/usb/iowarrior.h
0xCA 00-0F uapi/misc/cxl.h
0xCA 10-2F uapi/misc/ocxl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 960512bec428..ab77232d583e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13104,6 +13104,11 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
+MARVELL OCTEON CN10K DPI DRIVER
+M: Vamsi Attunuru <[email protected]>
+S: Maintained
+F: drivers/misc/mrvl_cn10k_dpi.c
+
MATROX FRAMEBUFFER DRIVER
L: [email protected]
S: Orphan
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4fb291f0bf7c..58de5844ecef 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -574,6 +574,18 @@ config NSM
To compile this driver as a module, choose M here.
The module will be called nsm.
+config MARVELL_CN10K_DPI
+ tristate "Octeon CN10K DPI driver"
+ depends on ARM64 && PCI
+ help
+ Enables Octeon CN10K DPI driver which intializes DPI PF device's global configuration
+ and its VFs resource configuration to enable DMA transfers. DPI PF device
+ does not have any data movement functionality, it only serves VF's resource
+ configuration requests.
+
+ To compile this driver as a module, choose M here: the module
+ will be called mrvl_cn10k_dpi.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ea6ea5bbbc9c..5106bf96ea5c 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -68,3 +68,5 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
obj-$(CONFIG_NSM) += nsm.o
+obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
+obj-y += mrvl_cn10k_dpi.o
diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
new file mode 100644
index 000000000000..c35bffbe8a40
--- /dev/null
+++ b/drivers/misc/mrvl_cn10k_dpi.c
@@ -0,0 +1,685 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <uapi/misc/mrvl_cn10k_dpi.h>
+
+#define DPI_DRV_NAME "mrvl-cn10k-dpi"
+
+/* PCI device IDs */
+#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
+#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xB900
+
+/* PCI BAR nos */
+#define PCI_DPI_CFG_BAR 0
+
+/* MSI-X interrupts */
+#define DPI_MAX_REQQ_INT 32
+#define DPI_MAX_CC_INT 64
+
+/* MBOX MSI-X interrupt vector index */
+#define DPI_MBOX_PF_VF_INT_IDX 0x75
+
+#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
+
+#define DPI_MAX_VFS 32
+
+#define DPI_ENGINE_MASK GENMASK(2, 0)
+
+#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) (((x) & GENMASK_ULL(15, 0)) << 16)
+#define DPI_DMA_IDS_INST_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 40)
+#define DPI_DMA_IDS_DMA_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 32)
+#define DPI_DMA_ENG_EN_MOLR(x) (((x) & GENMASK_ULL(9, 0)) << 32)
+#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & GENMASK(2, 0)) << 4)
+#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) & GENMASK(15, 0))
+#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19, 0))
+#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13, 0))
+#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2, 0))
+#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5, 0))
+#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)
+
+#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
+#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
+#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
+#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
+#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
+#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
+#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
+#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
+
+#define DPI_CTL_EN BIT_ULL(0)
+#define DPI_DMA_CC_INT BIT_ULL(0)
+#define DPI_DMA_QRST BIT_ULL(0)
+
+#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
+#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
+#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
+#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
+#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
+#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
+#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
+#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
+
+#define DPI_REQQ_INT \
+ (DPI_REQQ_INT_INSTRFLT | \
+ DPI_REQQ_INT_RDFLT | \
+ DPI_REQQ_INT_WRFLT | \
+ DPI_REQQ_INT_CSFLT | \
+ DPI_REQQ_INT_INST_DBO | \
+ DPI_REQQ_INT_INST_ADDR_NULL | \
+ DPI_REQQ_INT_INST_FILL_INVAL | \
+ DPI_REQQ_INT_INSTR_PSN)
+
+#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
+#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
+#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
+
+#define DPI_PF_RAS_INT \
+ (DPI_PF_RAS_EBI_DAT_PSN | \
+ DPI_PF_RAS_NCB_DAT_PSN | \
+ DPI_PF_RAS_NCB_CMD_PSN)
+
+#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
+#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
+#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
+#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
+
+#define DPI_CTL 0x10010ULL
+#define DPI_DMA_CONTROL 0x10018ULL
+#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
+#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
+
+#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
+
+#define DPI_PF_RAS 0x10308ULL
+#define DPI_PF_RAS_ENA_W1C 0x10318ULL
+
+#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
+
+#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
+#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
+
+#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
+#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
+
+#define DPI_MBOX_VF_PF_INT 0x16300ULL
+#define DPI_MBOX_VF_PF_INT_W1S 0x16308ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
+
+#define DPI_WCTL_FIF_THR 0x17008ULL
+
+#define DPI_EBUS_MAX_PORTS 2
+
+#define DPI_EBUS_MRRS_MIN 128
+#define DPI_EBUS_MRRS_MAX 1024
+#define DPI_EBUS_MPS_MIN 128
+#define DPI_EBUS_MPS_MAX 1024
+#define DPI_WCTL_FIFO_THRESHOLD 0x30
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+#define DPI_QUEUE_OPEN_V2 0x5
+
+enum dpi_mbox_rsp_type {
+ DPI_MBOX_TYPE_CMD,
+ DPI_MBOX_TYPE_RSP_ACK,
+ DPI_MBOX_TYPE_RSP_NACK,
+};
+
+struct dpivf_config {
+ u16 csize;
+ u32 aura;
+ u16 sso_pf_func;
+ u16 npa_pf_func;
+};
+
+struct dpipf_vf {
+ u8 this_vfid;
+ bool setup_done;
+ struct dpivf_config vf_config;
+};
+
+/* DPI device mailbox */
+struct dpi_mbox {
+ struct work_struct work;
+ /* lock to serialize mbox requests */
+ struct mutex lock;
+ struct dpipf *pf;
+ u8 __iomem *pf_vf_data_reg;
+ u8 __iomem *vf_pf_data_reg;
+};
+
+struct dpipf {
+ struct miscdevice miscdev;
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ struct dpipf_vf vf[DPI_MAX_VFS];
+ /* Mailbox to talk to VFs */
+ struct dpi_mbox *mbox[DPI_MAX_VFS];
+};
+
+union dpi_mbox_message_t {
+ u64 u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ u64 vfid :8;
+ /* Command code */
+ u64 cmd :4;
+ /* Command buffer size in 8-byte words */
+ u64 csize :14;
+ /* Aura of the command buffer */
+ u64 aura :20;
+ /* SSO PF function */
+ u64 sso_pf_func :16;
+ /* NPA PF function */
+ u64 npa_pf_func :16;
+ /* Work queue completion status enable */
+ u64 wqecs :1;
+ /* Work queue completion status byte offset */
+ u64 wqecsoff :7;
+ /* Reserved */
+ u64 rsvd :42;
+ } s __packed;
+};
+
+static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
+{
+ writeq(val, dpi->reg_base + offset);
+}
+
+static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
+{
+ return readq(dpi->reg_base + offset);
+}
+
+static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
+{
+ u64 reg;
+
+ reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
+ reg &= ~DPI_DMA_CONTROL_WQECSDIS;
+ reg |= DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_WQECSMODE1;
+ reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+}
+
+static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
+ u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
+ u16 csize = dpivf->vf_config.csize;
+ u32 aura = dpivf->vf_config.aura;
+ unsigned long timeout;
+ u64 reg;
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Wait for a maximum of 3 sec */
+ timeout = jiffies + msecs_to_jiffies(3000);
+ while (!time_after(jiffies, timeout)) {
+ reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf));
+ if (!(reg & DPI_DMA_QRST))
+ break;
+
+ usleep_range(500, 1000);
+ }
+
+ if (reg & DPI_DMA_QRST) {
+ dev_err(&dpi->pdev->dev, "Queue reset failed\n");
+ return -EBUSY;
+ }
+
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+
+ reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
+ dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf));
+ reg |= DPI_DMA_IDS2_INST_AURA(aura);
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf));
+ reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
+ reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
+ reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
+ reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
+
+ return 0;
+}
+
+static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Reset IDS and IDS2 registers */
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+}
+
+static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
+{
+ u64 reg;
+ u32 vf;
+
+ reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
+ if (reg) {
+ for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) {
+ if (reg & BIT_ULL(vf))
+ schedule_work(&dpi->mbox[vf]->work);
+ }
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
+ }
+}
+
+static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
+{
+ struct dpipf *dpi = data;
+
+ dpi_poll_pfvf_mbox(dpi);
+
+ return IRQ_HANDLED;
+}
+
+static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
+{
+ int ret = 0;
+
+ switch (msg->s.cmd) {
+ case DPI_QUEUE_OPEN:
+ case DPI_QUEUE_OPEN_V2:
+ dpivf->vf_config.aura = msg->s.aura;
+ dpivf->vf_config.csize = msg->s.cmd == DPI_QUEUE_OPEN ? msg->s.csize / 8 :
+ msg->s.csize;
+ dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
+ ret = dpi_queue_init(dpi, dpivf, msg->s.vfid);
+ if (!ret) {
+ if (msg->s.wqecs)
+ dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
+ dpivf->setup_done = true;
+ }
+ break;
+ case DPI_QUEUE_CLOSE:
+ dpivf->vf_config.aura = 0;
+ dpivf->vf_config.csize = 0;
+ dpivf->vf_config.sso_pf_func = 0;
+ dpivf->vf_config.npa_pf_func = 0;
+ dpi_queue_fini(dpi, dpivf, msg->s.vfid);
+ dpivf->setup_done = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void dpi_pfvf_mbox_work(struct work_struct *work)
+{
+ struct dpi_mbox *mbox = container_of(work, struct dpi_mbox, work);
+ union dpi_mbox_message_t msg = { 0 };
+ struct dpipf_vf *dpivf;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = mbox->pf;
+
+ mutex_lock(&mbox->lock);
+ msg.u[0] = readq(mbox->vf_pf_data_reg);
+ if (unlikely(msg.u[0] == (u64)-1))
+ goto exit;
+
+ if (unlikely(msg.s.vfid >= pci_num_vf(dpi->pdev))) {
+ dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
+ goto exit;
+ }
+
+ dpivf = &dpi->vf[msg.s.vfid];
+ msg.u[1] = readq(mbox->pf_vf_data_reg);
+
+ ret = queue_config(dpi, dpivf, &msg);
+ if (ret < 0)
+ writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);
+ else
+ writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
+exit:
+ mutex_unlock(&mbox->lock);
+}
+
+/* Setup registers for a PF mailbox */
+static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf)
+{
+ struct dpi_mbox *mbox = dpi->mbox[vf];
+
+ mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf);
+ mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf);
+}
+
+static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
+{
+ int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev, sizeof(*dpi->mbox[vf]), GFP_KERNEL);
+
+ if (!dpi->mbox[vf])
+ return -ENOMEM;
+
+ mutex_init(&dpi->mbox[vf]->lock);
+ INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
+ dpi->mbox[vf]->pf = dpi;
+ dpi_setup_mbox_regs(dpi, vf);
+ }
+
+ return 0;
+}
+
+static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
+{
+ unsigned int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ if (work_pending(&dpi->mbox[vf]->work))
+ cancel_work_sync(&dpi->mbox[vf]->work);
+
+ dpi->mbox[vf] = NULL;
+ }
+}
+
+static void dpi_init(struct dpipf *dpi)
+{
+ unsigned int engine, port;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ if (engine == 4 || engine == 5)
+ reg = DPI_ENG_BUF_BLKS(16);
+ else
+ reg = DPI_ENG_BUF_BLKS(8);
+
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+ }
+
+ reg = DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
+ DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB;
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
+
+ mrrs_val = 2; /* 512B */
+ mps_val = 1; /* 256B */
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(7) | DPI_EBUS_PORTX_CFG_MPS(7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ dpi_reg_write(dpi, DPI_WCTL_FIF_THR, DPI_WCTL_FIFO_THRESHOLD);
+}
+
+static void dpi_fini(struct dpipf *dpi)
+{
+ unsigned int engine;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++)
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
+ dpi_reg_write(dpi, DPI_CTL, 0);
+}
+
+static void dpi_free_irq_vectors(void *pdev)
+{
+ pci_free_irq_vectors((struct pci_dev *)pdev);
+}
+
+static int dpi_irq_init(struct dpipf *dpi)
+{
+ struct pci_dev *pdev = dpi->pdev;
+ struct device *dev = &pdev->dev;
+ int i, ret;
+
+ /* Clear all RAS interrupts */
+ dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
+
+ /* Clear all RAS interrupt enable bits */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ ret = pci_alloc_irq_vectors(pdev, DPI_MAX_IRQS, DPI_MAX_IRQS, PCI_IRQ_MSIX);
+ if (ret != DPI_MAX_IRQS) {
+ dev_err(dev, "DPI: Failed to alloc %d msix irqs\n", DPI_MAX_IRQS);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(dev, dpi_free_irq_vectors, pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to add irq free action\n");
+ return ret;
+ }
+
+ ret = devm_request_irq(dev, pci_irq_vector(pdev, DPI_MBOX_PF_VF_INT_IDX),
+ dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
+ if (ret) {
+ dev_err(dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
+ return ret;
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));
+
+ return 0;
+}
+
+static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_mps_mrrs_cfg cfg;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_mps_mrrs_cfg)))
+ return -EFAULT;
+
+ if (cfg.mrrs < DPI_EBUS_MRRS_MIN || cfg.mrrs > DPI_EBUS_MRRS_MAX ||
+ !is_power_of_2(cfg.mrrs)) {
+ dev_err(&dpi->pdev->dev, "Invalid MRRS size:%llu\n", cfg.mrrs);
+ return -EINVAL;
+ }
+
+ if (cfg.mps < DPI_EBUS_MPS_MIN || cfg.mps > DPI_EBUS_MPS_MAX ||
+ !is_power_of_2(cfg.mps)) {
+ dev_err(&dpi->pdev->dev, "Invalid MPS size:%llu\n", cfg.mps);
+ return -EINVAL;
+ }
+
+ if (cfg.port >= DPI_EBUS_MAX_PORTS) {
+ dev_err(&dpi->pdev->dev, "Invalid EBUS port:%llu\n", cfg.mps);
+ return -EINVAL;
+ }
+
+ mrrs_val = fls(cfg.mrrs >> 8);
+ mps_val = fls(cfg.mps >> 8);
+
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
+
+ return 0;
+}
+
+static int dpi_engine_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_engine_cfg cfg;
+ unsigned int engine;
+ u8 *eng_buf;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_engine_cfg)))
+ return -EFAULT;
+
+ eng_buf = (u8 *)&cfg.fifo_mask;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ reg = DPI_ENG_BUF_BLKS(eng_buf[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+
+ if (cfg.update_molr) {
+ reg = DPI_DMA_ENG_EN_MOLR(cfg.molr[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg);
+ }
+ }
+
+ return 0;
+}
+
+static long dpi_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data)
+{
+ void __user *arg = (void __user *)data;
+ struct dpipf *dpi;
+ int ret = -EINVAL;
+
+ dpi = container_of(fptr->private_data, struct dpipf, miscdev);
+
+ switch (cmd) {
+ case DPI_MPS_MRRS_CFG:
+ ret = dpi_mps_mrrs_config(dpi, arg);
+ break;
+ case DPI_ENGINE_CFG:
+ ret = dpi_engine_config(dpi, arg);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static const struct file_operations dpi_device_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = dpi_dev_ioctl,
+ .compat_ioctl = compat_ptr_ioctl,
+};
+
+static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi->pdev = pdev;
+
+ ret = pcim_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to enable PCI device\n");
+ return ret;
+ }
+
+ ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to request MMIO region\n");
+ return ret;
+ }
+
+ dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
+
+ /* Initialize global PF registers */
+ dpi_init(dpi);
+
+ /* Setup PF-VF mailbox */
+ ret = dpi_pfvf_mbox_setup(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
+ goto err_dpi_fini;
+ }
+
+ /* Register interrupts */
+ ret = dpi_irq_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize irq vectors\n");
+ goto err_dpi_mbox_free;
+ }
+
+ pci_set_drvdata(pdev, dpi);
+ dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dpi->miscdev.name = DPI_DRV_NAME;
+ dpi->miscdev.fops = &dpi_device_fops;
+ dpi->miscdev.parent = dev;
+
+ ret = misc_register(&dpi->miscdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to register misc device\n");
+ goto err_dpi_mbox_free;
+ }
+
+ return 0;
+
+err_dpi_mbox_free:
+ dpi_pfvf_mbox_destroy(dpi);
+err_dpi_fini:
+ dpi_fini(dpi);
+ return ret;
+}
+
+static void dpi_remove(struct pci_dev *pdev)
+{
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+
+ misc_deregister(&dpi->miscdev);
+ pci_sriov_configure_simple(pdev, 0);
+ dpi_pfvf_mbox_destroy(dpi);
+ dpi_fini(dpi);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id dpi_id_table[] = {
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_MRVL_CN10K_DPI_PF,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
+ { 0, } /* end of table */
+};
+
+static struct pci_driver dpi_driver = {
+ .name = DPI_DRV_NAME,
+ .id_table = dpi_id_table,
+ .probe = dpi_probe,
+ .remove = dpi_remove,
+ .sriov_configure = pci_sriov_configure_simple,
+};
+
+module_pci_driver(dpi_driver);
+MODULE_DEVICE_TABLE(pci, dpi_id_table);
+MODULE_AUTHOR("Marvell.");
+MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/misc/mrvl_cn10k_dpi.h b/include/uapi/misc/mrvl_cn10k_dpi.h
new file mode 100644
index 000000000000..a999992e641c
--- /dev/null
+++ b/include/uapi/misc/mrvl_cn10k_dpi.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/*
+ * Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#ifndef __MRVL_CN10K_DPI_H__
+#define __MRVL_CN10K_DPI_H__
+
+#include <linux/types.h>
+
+#define DPI_MAX_ENGINES 6
+
+struct dpi_mps_mrrs_cfg {
+ __u64 mrrs; /* Max read request size */
+ __u64 mps; /* Max packet size */
+ __u64 port; /* Ebus port */
+};
+
+struct dpi_engine_cfg {
+ __u64 fifo_mask; /* FIFO size mask in KBytes */
+ __u64 molr[DPI_MAX_ENGINES];
+ __u64 update_molr; /* '1' to update engine MOLR */
+};
+
+#define DPI_MAGIC_NUM 0xB8
+
+/* Set MPS & MRRS parameters */
+#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 1, struct dpi_mps_mrrs_cfg)
+
+/* Set Engine FIFO configuration */
+#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 2, struct dpi_engine_cfg)
+
+#endif /* __MRVL_CN10K_DPI_H__ */
--
2.25.1
On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> function which initializes DPI DMA hardware's global configuration and
> enables hardware mailbox channels between physical function (PF) and
> it's virtual functions (VF). VF device drivers (User space drivers) use
> this hw mailbox to communicate any required device configuration on it's
> respective VF device. Accordingly, this DPI PF driver provisions the
> VF device resources.
>
> At the hardware level, the DPI physical function (PF) acts as a management
> interface to setup the VF device resources, VF devices are only provisioned
> to handle or control the actual DMA Engine's data transfer capabilities.
No pointer to the userspace code that uses this? Why not? How are we
supposed to be able to review this?
> +config MARVELL_CN10K_DPI
> + tristate "Octeon CN10K DPI driver"
> + depends on ARM64 && PCI
> + help
> + Enables Octeon CN10K DPI driver which intializes DPI PF device's global configuration
> + and its VFs resource configuration to enable DMA transfers. DPI PF device
> + does not have any data movement functionality, it only serves VF's resource
> + configuration requests.
Did this pass checkpatch? Please wrap your help text at the proper
boundry.
And what is "DPI"? What is "PF"? What is "VF"? These are all terms
that need to be documented somewhere, right?
> --- /dev/null
> +++ b/include/uapi/misc/mrvl_cn10k_dpi.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
> +/*
> + * Marvell Octeon CN10K DPI driver
> + *
> + * Copyright (C) 2024 Marvell.
> + *
> + */
> +
> +#ifndef __MRVL_CN10K_DPI_H__
> +#define __MRVL_CN10K_DPI_H__
> +
> +#include <linux/types.h>
> +
> +#define DPI_MAX_ENGINES 6
> +
> +struct dpi_mps_mrrs_cfg {
> + __u64 mrrs; /* Max read request size */
> + __u64 mps; /* Max packet size */
You can spell out variables with more characters :)
> + __u64 port; /* Ebus port */
> +};
> +
> +struct dpi_engine_cfg {
> + __u64 fifo_mask; /* FIFO size mask in KBytes */
> + __u64 molr[DPI_MAX_ENGINES];
What is a "molr"?
> + __u64 update_molr; /* '1' to update engine MOLR */
You "burn" a whole 64 for 1 bit? That feels wrong, who on your end
reviewed this api to be correct?
> +#define DPI_MAGIC_NUM 0xB8
Did you document this api somewhere?
> +
> +/* Set MPS & MRRS parameters */
> +#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 1, struct dpi_mps_mrrs_cfg)
> +
> +/* Set Engine FIFO configuration */
> +#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 2, struct dpi_engine_cfg)
> +
> +#endif /* __MRVL_CN10K_DPI_H__ */
> --
> 2.25.1
>
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Friday, April 12, 2024 5:57 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; [email protected]
> Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K DPI administrative driver
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
> On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> > function which initializes DPI DMA hardware's global configuration and
> > enables hardware mailbox channels between physical function (PF) and
> > it's virtual functions (VF). VF device drivers (User space drivers)
> > use this hw mailbox to communicate any required device configuration
> > on it's respective VF device. Accordingly, this DPI PF driver
> > provisions the VF device resources.
> >
> > At the hardware level, the DPI physical function (PF) acts as a
> > management interface to setup the VF device resources, VF devices are
> > only provisioned to handle or control the actual DMA Engine's data transfer
> capabilities.
>
> No pointer to the userspace code that uses this? Why not? How are we
> supposed to be able to review this?
Userspace code will use two functionalities (mailbox & ioctl) from this driver. DPDK DMA driver uses the mailbox and
the dpdk application uses the ioctl to setup the device attributes. We are waiting for this kernel driver get merged
to update the corresponding support in DPDK driver and applications. I will provide the pointers to both the use
cases in userspace code.
Meanwhile below is the current dpdk dma driver that uses sysfs based scheme to convey mbox requests to
the kernel DPI driver which gets replaced with hardware mailbox scheme once mrvl-cn10k-dpi kernel driver is merged.
https://github.com/DPDK/dpdk/blob/main/drivers/common/cnxk/roc_dpi.c
>
> > +config MARVELL_CN10K_DPI
> > + tristate "Octeon CN10K DPI driver"
> > + depends on ARM64 && PCI
> > + help
> > + Enables Octeon CN10K DPI driver which intializes DPI PF device's
> global configuration
> > + and its VFs resource configuration to enable DMA transfers. DPI PF
> device
> > + does not have any data movement functionality, it only serves VF's
> resource
> > + configuration requests.
>
> Did this pass checkpatch? Please wrap your help text at the proper boundry.
Yes, I did not find any failure, will double check and wrap the text as suggested.
>
> And what is "DPI"? What is "PF"? What is "VF"? These are all terms that
> need to be documented somewhere, right?
Yes, I will describe in full form or document it somewhere.
>
> > --- /dev/null
> > +++ b/include/uapi/misc/mrvl_cn10k_dpi.h
> > @@ -0,0 +1,36 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
> > +/*
> > + * Marvell Octeon CN10K DPI driver
> > + *
> > + * Copyright (C) 2024 Marvell.
> > + *
> > + */
> > +
> > +#ifndef __MRVL_CN10K_DPI_H__
> > +#define __MRVL_CN10K_DPI_H__
> > +
> > +#include <linux/types.h>
> > +
> > +#define DPI_MAX_ENGINES 6
> > +
> > +struct dpi_mps_mrrs_cfg {
> > + __u64 mrrs; /* Max read request size */
> > + __u64 mps; /* Max packet size */
>
> You can spell out variables with more characters :)
ack
>
> > + __u64 port; /* Ebus port */
> > +};
> > +
> > +struct dpi_engine_cfg {
> > + __u64 fifo_mask; /* FIFO size mask in KBytes */
> > + __u64 molr[DPI_MAX_ENGINES];
>
> What is a "molr"?
Sorry, I will add required full forms. It's maximum outstanding load requests.
>
> > + __u64 update_molr; /* '1' to update engine MOLR */
>
> You "burn" a whole 64 for 1 bit? That feels wrong, who on your end
> reviewed this api to be correct?
Just for the explicit alignment, defined all variables as __u64. I will shrink it to minimal sizes
considering any reserved fields if required.
>
> > +#define DPI_MAGIC_NUM 0xB8
>
> Did you document this api somewhere?
No, I followed as other MAGIC NUM api definations, will document it as required.
>
> > +
> > +/* Set MPS & MRRS parameters */
> > +#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 1, struct
> > +dpi_mps_mrrs_cfg)
> > +
> > +/* Set Engine FIFO configuration */
> > +#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 2, struct
> dpi_engine_cfg)
> > +
> > +#endif /* __MRVL_CN10K_DPI_H__ */
> > --
> > 2.25.1
> >
On Fri, Apr 12, 2024 at 01:56:36PM +0000, Vamsi Krishna Attunuru wrote:
>
>
> > -----Original Message-----
> > From: Greg KH <[email protected]>
> > Sent: Friday, April 12, 2024 5:57 PM
> > To: Vamsi Krishna Attunuru <[email protected]>
> > Cc: [email protected]; [email protected]
> > Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add Octeon
> > CN10K DPI administrative driver
> >
> > Prioritize security for external emails: Confirm sender and content safety
> > before clicking links or opening attachments
> >
> > ----------------------------------------------------------------------
> > On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> > > function which initializes DPI DMA hardware's global configuration and
> > > enables hardware mailbox channels between physical function (PF) and
> > > it's virtual functions (VF). VF device drivers (User space drivers)
> > > use this hw mailbox to communicate any required device configuration
> > > on it's respective VF device. Accordingly, this DPI PF driver
> > > provisions the VF device resources.
> > >
> > > At the hardware level, the DPI physical function (PF) acts as a
> > > management interface to setup the VF device resources, VF devices are
> > > only provisioned to handle or control the actual DMA Engine's data transfer
> > capabilities.
> >
> > No pointer to the userspace code that uses this? Why not? How are we
> > supposed to be able to review this?
>
> Userspace code will use two functionalities (mailbox & ioctl) from this driver. DPDK DMA driver uses the mailbox and
> the dpdk application uses the ioctl to setup the device attributes. We are waiting for this kernel driver get merged
> to update the corresponding support in DPDK driver and applications. I will provide the pointers to both the use
> cases in userspace code.
> Meanwhile below is the current dpdk dma driver that uses sysfs based scheme to convey mbox requests to
> the kernel DPI driver which gets replaced with hardware mailbox scheme once mrvl-cn10k-dpi kernel driver is merged.
> https://github.com/DPDK/dpdk/blob/main/drivers/common/cnxk/roc_dpi.c
So this is a DPDK thing? Ugh, do the networking people know about this?
If not, why aren't they reviewing this?
> > > + __u64 update_molr; /* '1' to update engine MOLR */
> >
> > You "burn" a whole 64 for 1 bit? That feels wrong, who on your end
> > reviewed this api to be correct?
>
> Just for the explicit alignment, defined all variables as __u64. I will shrink it to minimal sizes
> considering any reserved fields if required.
The alignment is fine, but wasting 63 bits feels odd, make it a bit
field at worst case, or just make it __u8 if you don't want a bitfield.
thanks,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Friday, April 12, 2024 9:05 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; [email protected]
> Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> Octeon CN10K DPI administrative driver
>
> On Fri, Apr 12, 2024 at 01:56:36PM +0000, Vamsi Krishna Attunuru wrote:
> >
> >
> > > -----Original Message-----
> > > From: Greg KH <[email protected]>
> > > Sent: Friday, April 12, 2024 5:57 PM
> > > To: Vamsi Krishna Attunuru <[email protected]>
> > > Cc: [email protected]; [email protected]
> > > Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > Octeon CN10K DPI administrative driver
> > >
> > > Prioritize security for external emails: Confirm sender and content
> > > safety before clicking links or opening attachments
> > >
> > > --------------------------------------------------------------------
> > > -- On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > > > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's
> > > > physical function which initializes DPI DMA hardware's global
> > > > configuration and enables hardware mailbox channels between
> > > > physical function (PF) and it's virtual functions (VF). VF device
> > > > drivers (User space drivers) use this hw mailbox to communicate
> > > > any required device configuration on it's respective VF device.
> > > > Accordingly, this DPI PF driver provisions the VF device resources.
> > > >
> > > > At the hardware level, the DPI physical function (PF) acts as a
> > > > management interface to setup the VF device resources, VF devices
> > > > are only provisioned to handle or control the actual DMA Engine's
> > > > data transfer
> > > capabilities.
> > >
> > > No pointer to the userspace code that uses this? Why not? How are
> > > we supposed to be able to review this?
> >
> > Userspace code will use two functionalities (mailbox & ioctl) from
> > this driver. DPDK DMA driver uses the mailbox and the dpdk application
> > uses the ioctl to setup the device attributes. We are waiting for this
> > kernel driver get merged to update the corresponding support in DPDK
> driver and applications. I will provide the pointers to both the use cases in
> userspace code.
> > Meanwhile below is the current dpdk dma driver that uses sysfs based
> > scheme to convey mbox requests to the kernel DPI driver which gets
> replaced with hardware mailbox scheme once mrvl-cn10k-dpi kernel driver is
> merged.
> > https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__github.com_DPDK_d
> > pdk_blob_main_drivers_common_cnxk_roc-
> 5Fdpi.c&d=DwIBAg&c=nKjWec2b6R0mO
> >
> yPaz7xtfQ&r=WllrYaumVkxaWjgKto6E_rtDQshhIhik2jkvzFyRhW8&m=o3EhoL
> s7dsod
> > -YHS438Wl2Pf_MKMBYegGSKteoX3qFTB0HV897ykpCVbTp-
> nmj4e&s=A6TJDFUtPm3ksJh
> > qop89CL8GgKj4sjkJIVi1-RdnUr8&e=
>
> So this is a DPDK thing? Ugh, do the networking people know about this?
> If not, why aren't they reviewing this?
Actually, It's not networking related. Like the Linux kernel, DPDK also supports multiple subsystems like
network, scheduler, DMA, mempool etc. Regarding the usecases, the DPDK Marvell DMA/DPI VF driver
interacts(over hardware mailbox) with the mrvl-cn10k-dpi misc kernel driver(administrative driver) for setting
up the VF device resources.
DPDK is one example that uses this driver, there can be other userspace generic frameworks/applications
where the virtual functions are binded to userspace drivers and interact with physical/administrative function
driver running in the kernel.
>
> > > > + __u64 update_molr; /* '1' to update engine MOLR */
> > >
> > > You "burn" a whole 64 for 1 bit? That feels wrong, who on your end
> > > reviewed this api to be correct?
> >
> > Just for the explicit alignment, defined all variables as __u64. I
> > will shrink it to minimal sizes considering any reserved fields if required.
>
> The alignment is fine, but wasting 63 bits feels odd, make it a bit field at worst
> case, or just make it __u8 if you don't want a bitfield.
ack
>
> thanks,
>
> greg k-h
On Fri, Apr 12, 2024 at 04:19:58PM +0000, Vamsi Krishna Attunuru wrote:
>
>
> > -----Original Message-----
> > From: Greg KH <[email protected]>
> > Sent: Friday, April 12, 2024 9:05 PM
> > To: Vamsi Krishna Attunuru <[email protected]>
> > Cc: [email protected]; [email protected]
> > Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > Octeon CN10K DPI administrative driver
> >
> > On Fri, Apr 12, 2024 at 01:56:36PM +0000, Vamsi Krishna Attunuru wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Greg KH <[email protected]>
> > > > Sent: Friday, April 12, 2024 5:57 PM
> > > > To: Vamsi Krishna Attunuru <[email protected]>
> > > > Cc: [email protected]; [email protected]
> > > > Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > > Octeon CN10K DPI administrative driver
> > > >
> > > > Prioritize security for external emails: Confirm sender and content
> > > > safety before clicking links or opening attachments
> > > >
> > > > --------------------------------------------------------------------
> > > > -- On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > > > > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's
> > > > > physical function which initializes DPI DMA hardware's global
> > > > > configuration and enables hardware mailbox channels between
> > > > > physical function (PF) and it's virtual functions (VF). VF device
> > > > > drivers (User space drivers) use this hw mailbox to communicate
> > > > > any required device configuration on it's respective VF device.
> > > > > Accordingly, this DPI PF driver provisions the VF device resources.
> > > > >
> > > > > At the hardware level, the DPI physical function (PF) acts as a
> > > > > management interface to setup the VF device resources, VF devices
> > > > > are only provisioned to handle or control the actual DMA Engine's
> > > > > data transfer
> > > > capabilities.
> > > >
> > > > No pointer to the userspace code that uses this? Why not? How are
> > > > we supposed to be able to review this?
> > >
> > > Userspace code will use two functionalities (mailbox & ioctl) from
> > > this driver. DPDK DMA driver uses the mailbox and the dpdk application
> > > uses the ioctl to setup the device attributes. We are waiting for this
> > > kernel driver get merged to update the corresponding support in DPDK
> > driver and applications. I will provide the pointers to both the use cases in
> > userspace code.
> > > Meanwhile below is the current dpdk dma driver that uses sysfs based
> > > scheme to convey mbox requests to the kernel DPI driver which gets
> > replaced with hardware mailbox scheme once mrvl-cn10k-dpi kernel driver is
> > merged.
> > > https://urldefense.proofpoint.com/v2/url?u=https-
> > 3A__github.com_DPDK_d
> > > pdk_blob_main_drivers_common_cnxk_roc-
> > 5Fdpi.c&d=DwIBAg&c=nKjWec2b6R0mO
> > >
> > yPaz7xtfQ&r=WllrYaumVkxaWjgKto6E_rtDQshhIhik2jkvzFyRhW8&m=o3EhoL
> > s7dsod
> > > -YHS438Wl2Pf_MKMBYegGSKteoX3qFTB0HV897ykpCVbTp-
> > nmj4e&s=A6TJDFUtPm3ksJh
> > > qop89CL8GgKj4sjkJIVi1-RdnUr8&e=
> >
> > So this is a DPDK thing? Ugh, do the networking people know about this?
> > If not, why aren't they reviewing this?
>
> Actually, It's not networking related. Like the Linux kernel, DPDK also supports multiple subsystems like
> network, scheduler, DMA, mempool etc. Regarding the usecases, the DPDK Marvell DMA/DPI VF driver
> interacts(over hardware mailbox) with the mrvl-cn10k-dpi misc kernel driver(administrative driver) for setting
> up the VF device resources.
So this is something that the PCI core should be concerned about then?
> DPDK is one example that uses this driver, there can be other userspace generic frameworks/applications
> where the virtual functions are binded to userspace drivers and interact with physical/administrative function
> driver running in the kernel.
Are there other devices/drivers that do this today in Linux? Why make a
device-specific api for this common functionality?
thanks,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Saturday, April 13, 2024 11:18 AM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; [email protected]; Jerin Jacob
> <[email protected]>
> Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> Octeon CN10K DPI administrative driver
>
> On Fri, Apr 12, 2024 at 04:19:58PM +0000, Vamsi Krishna Attunuru wrote:
> >
> >
> > > -----Original Message-----
> > > From: Greg KH <[email protected]>
> > > Sent: Friday, April 12, 2024 9:05 PM
> > > To: Vamsi Krishna Attunuru <[email protected]>
> > > Cc: [email protected]; [email protected]
> > > Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > Octeon CN10K DPI administrative driver
> > >
> > > On Fri, Apr 12, 2024 at 01:56:36PM +0000, Vamsi Krishna Attunuru wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Greg KH <[email protected]>
> > > > > Sent: Friday, April 12, 2024 5:57 PM
> > > > > To: Vamsi Krishna Attunuru <[email protected]>
> > > > > Cc: [email protected]; [email protected]
> > > > > Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > > > Octeon CN10K DPI administrative driver
> > > > >
> > > > > Prioritize security for external emails: Confirm sender and
> > > > > content safety before clicking links or opening attachments
> > > > >
> > > > > ----------------------------------------------------------------
> > > > > ----
> > > > > -- On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > > > > > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's
> > > > > > physical function which initializes DPI DMA hardware's global
> > > > > > configuration and enables hardware mailbox channels between
> > > > > > physical function (PF) and it's virtual functions (VF). VF
> > > > > > device drivers (User space drivers) use this hw mailbox to
> > > > > > communicate any required device configuration on it's respective
> VF device.
> > > > > > Accordingly, this DPI PF driver provisions the VF device resources.
> > > > > >
> > > > > > At the hardware level, the DPI physical function (PF) acts as
> > > > > > a management interface to setup the VF device resources, VF
> > > > > > devices are only provisioned to handle or control the actual
> > > > > > DMA Engine's data transfer
> > > > > capabilities.
> > > > >
> > > > > No pointer to the userspace code that uses this? Why not? How
> > > > > are we supposed to be able to review this?
> > > >
> > > > Userspace code will use two functionalities (mailbox & ioctl) from
> > > > this driver. DPDK DMA driver uses the mailbox and the dpdk
> > > > application uses the ioctl to setup the device attributes. We are
> > > > waiting for this kernel driver get merged to update the
> > > > corresponding support in DPDK
> > > driver and applications. I will provide the pointers to both the use
> > > cases in userspace code.
> > > > Meanwhile below is the current dpdk dma driver that uses sysfs
> > > > based scheme to convey mbox requests to the kernel DPI driver
> > > > which gets
> > > replaced with hardware mailbox scheme once mrvl-cn10k-dpi kernel
> > > driver is merged.
> > > > https://urldefense.proofpoint.com/v2/url?u=https-
> > > 3A__github.com_DPDK_d
> > > > pdk_blob_main_drivers_common_cnxk_roc-
> > > 5Fdpi.c&d=DwIBAg&c=nKjWec2b6R0mO
> > > >
> > >
> yPaz7xtfQ&r=WllrYaumVkxaWjgKto6E_rtDQshhIhik2jkvzFyRhW8&m=o3EhoL
> > > s7dsod
> > > > -YHS438Wl2Pf_MKMBYegGSKteoX3qFTB0HV897ykpCVbTp-
> > > nmj4e&s=A6TJDFUtPm3ksJh
> > > > qop89CL8GgKj4sjkJIVi1-RdnUr8&e=
> > >
> > > So this is a DPDK thing? Ugh, do the networking people know about this?
> > > If not, why aren't they reviewing this?
> >
> > Actually, It's not networking related. Like the Linux kernel, DPDK
> > also supports multiple subsystems like network, scheduler, DMA,
> > mempool etc. Regarding the usecases, the DPDK Marvell DMA/DPI VF
> > driver interacts(over hardware mailbox) with the mrvl-cn10k-dpi misc
> kernel driver(administrative driver) for setting up the VF device resources.
>
> So this is something that the PCI core should be concerned about then?
No, it's a normal PCIe sriov capability implemented in all sriov capable PCIe devices.
Our PF device aka this driver in kernel space service mailbox requests from userspace
applications via VF devices. For instance, DPI VF device from user space writes into
mailbox registers and the DPI hardware triggers an interrupt to DPI PF device.
Upon PF interrupt, this driver services the mailbox requests.
>
> > DPDK is one example that uses this driver, there can be other
> > userspace generic frameworks/applications where the virtual functions
> > are binded to userspace drivers and interact with physical/administrative
> function driver running in the kernel.
>
> Are there other devices/drivers that do this today in Linux? Why make a
> device-specific api for this common functionality?
The apis defined in this driver are specific to Marvell DPI hardware. For instance,
the variables molr(max outstanding load requests), fifo_max, ebus_port are
DPI hardware specific. Generally, drivers use driver-specific api to configure
any device-specific configuration which does not fit in common functionality right.
Mailbox operations like dpi_queue_open & close are requests sent from VF device
to PF device for setting up the VF queue resources.
>
> thanks,
>
> greg k-h
On Sat, Apr 13, 2024 at 10:58:37AM +0000, Vamsi Krishna Attunuru wrote:
>
>
> > -----Original Message-----
> > From: Greg KH <[email protected]>
> > Sent: Saturday, April 13, 2024 11:18 AM
> > To: Vamsi Krishna Attunuru <[email protected]>
> > Cc: [email protected]; [email protected]; Jerin Jacob
> > <[email protected]>
> > Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > Octeon CN10K DPI administrative driver
> >
> > On Fri, Apr 12, 2024 at 04:19:58PM +0000, Vamsi Krishna Attunuru wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Greg KH <[email protected]>
> > > > Sent: Friday, April 12, 2024 9:05 PM
> > > > To: Vamsi Krishna Attunuru <[email protected]>
> > > > Cc: [email protected]; [email protected]
> > > > Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > > Octeon CN10K DPI administrative driver
> > > >
> > > > On Fri, Apr 12, 2024 at 01:56:36PM +0000, Vamsi Krishna Attunuru wrote:
> > > > >
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Greg KH <[email protected]>
> > > > > > Sent: Friday, April 12, 2024 5:57 PM
> > > > > > To: Vamsi Krishna Attunuru <[email protected]>
> > > > > > Cc: [email protected]; [email protected]
> > > > > > Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > > > > Octeon CN10K DPI administrative driver
> > > > > >
> > > > > > Prioritize security for external emails: Confirm sender and
> > > > > > content safety before clicking links or opening attachments
> > > > > >
> > > > > > ----------------------------------------------------------------
> > > > > > ----
> > > > > > -- On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > > > > > > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's
> > > > > > > physical function which initializes DPI DMA hardware's global
> > > > > > > configuration and enables hardware mailbox channels between
> > > > > > > physical function (PF) and it's virtual functions (VF). VF
> > > > > > > device drivers (User space drivers) use this hw mailbox to
> > > > > > > communicate any required device configuration on it's respective
> > VF device.
> > > > > > > Accordingly, this DPI PF driver provisions the VF device resources.
> > > > > > >
> > > > > > > At the hardware level, the DPI physical function (PF) acts as
> > > > > > > a management interface to setup the VF device resources, VF
> > > > > > > devices are only provisioned to handle or control the actual
> > > > > > > DMA Engine's data transfer
> > > > > > capabilities.
> > > > > >
> > > > > > No pointer to the userspace code that uses this? Why not? How
> > > > > > are we supposed to be able to review this?
> > > > >
> > > > > Userspace code will use two functionalities (mailbox & ioctl) from
> > > > > this driver. DPDK DMA driver uses the mailbox and the dpdk
> > > > > application uses the ioctl to setup the device attributes. We are
> > > > > waiting for this kernel driver get merged to update the
> > > > > corresponding support in DPDK
> > > > driver and applications. I will provide the pointers to both the use
> > > > cases in userspace code.
> > > > > Meanwhile below is the current dpdk dma driver that uses sysfs
> > > > > based scheme to convey mbox requests to the kernel DPI driver
> > > > > which gets
> > > > replaced with hardware mailbox scheme once mrvl-cn10k-dpi kernel
> > > > driver is merged.
> > > > > https://urldefense.proofpoint.com/v2/url?u=https-
> > > > 3A__github.com_DPDK_d
> > > > > pdk_blob_main_drivers_common_cnxk_roc-
> > > > 5Fdpi.c&d=DwIBAg&c=nKjWec2b6R0mO
> > > > >
> > > >
> > yPaz7xtfQ&r=WllrYaumVkxaWjgKto6E_rtDQshhIhik2jkvzFyRhW8&m=o3EhoL
> > > > s7dsod
> > > > > -YHS438Wl2Pf_MKMBYegGSKteoX3qFTB0HV897ykpCVbTp-
> > > > nmj4e&s=A6TJDFUtPm3ksJh
> > > > > qop89CL8GgKj4sjkJIVi1-RdnUr8&e=
> > > >
> > > > So this is a DPDK thing? Ugh, do the networking people know about this?
> > > > If not, why aren't they reviewing this?
> > >
> > > Actually, It's not networking related. Like the Linux kernel, DPDK
> > > also supports multiple subsystems like network, scheduler, DMA,
> > > mempool etc. Regarding the usecases, the DPDK Marvell DMA/DPI VF
> > > driver interacts(over hardware mailbox) with the mrvl-cn10k-dpi misc
> > kernel driver(administrative driver) for setting up the VF device resources.
> >
> > So this is something that the PCI core should be concerned about then?
>
> No, it's a normal PCIe sriov capability implemented in all sriov capable PCIe devices.
> Our PF device aka this driver in kernel space service mailbox requests from userspace
> applications via VF devices. For instance, DPI VF device from user space writes into
> mailbox registers and the DPI hardware triggers an interrupt to DPI PF device.
> Upon PF interrupt, this driver services the mailbox requests.
Isn't that a "normal" PCI thing? How is this different from other
devices that have VF?
> > > DPDK is one example that uses this driver, there can be other
> > > userspace generic frameworks/applications where the virtual functions
> > > are binded to userspace drivers and interact with physical/administrative
> > function driver running in the kernel.
> >
> > Are there other devices/drivers that do this today in Linux? Why make a
> > device-specific api for this common functionality?
>
> The apis defined in this driver are specific to Marvell DPI hardware.
The api, yes, but that's the point, shouldn't this be generic for all
hardware that supports this? Implementation should be device specific,
in the driver.
> For instance,
> the variables molr(max outstanding load requests), fifo_max, ebus_port are
> DPI hardware specific. Generally, drivers use driver-specific api to configure
> any device-specific configuration which does not fit in common functionality right.
>
> Mailbox operations like dpi_queue_open & close are requests sent from VF device
> to PF device for setting up the VF queue resources.
Why is an ioctl to a random character device the correct api to
userspace for this type of thing? Shouldn't this go through the PCI
layer api instead?
thanks,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Saturday, April 13, 2024 4:55 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; [email protected]; Jerin Jacob
> <[email protected]>
> Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> Octeon CN10K DPI administrative driver
>
> On Sat, Apr 13, 2024 at 10:58:37AM +0000, Vamsi Krishna Attunuru wrote:
> >
> >
> > > -----Original Message-----
> > > From: Greg KH <[email protected]>
> > > Sent: Saturday, April 13, 2024 11:18 AM
> > > To: Vamsi Krishna Attunuru <[email protected]>
> > > Cc: [email protected]; [email protected]; Jerin Jacob
> > > <[email protected]>
> > > Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > Octeon CN10K DPI administrative driver
> > >
> > > On Fri, Apr 12, 2024 at 04:19:58PM +0000, Vamsi Krishna Attunuru wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Greg KH <[email protected]>
> > > > > Sent: Friday, April 12, 2024 9:05 PM
> > > > > To: Vamsi Krishna Attunuru <[email protected]>
> > > > > Cc: [email protected]; [email protected]
> > > > > Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi:
> > > > > add Octeon CN10K DPI administrative driver
> > > > >
> > > > > On Fri, Apr 12, 2024 at 01:56:36PM +0000, Vamsi Krishna Attunuru
> wrote:
> > > > > >
> > > > > >
> > > > > > > -----Original Message-----
> > > > > > > From: Greg KH <[email protected]>
> > > > > > > Sent: Friday, April 12, 2024 5:57 PM
> > > > > > > To: Vamsi Krishna Attunuru <[email protected]>
> > > > > > > Cc: [email protected]; [email protected]
> > > > > > > Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi:
> > > > > > > add Octeon CN10K DPI administrative driver
> > > > > > >
> > > > > > > Prioritize security for external emails: Confirm sender and
> > > > > > > content safety before clicking links or opening attachments
> > > > > > >
> > > > > > > ------------------------------------------------------------
> > > > > > > ----
> > > > > > > ----
> > > > > > > -- On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > > > > > > > Adds a misc driver for Marvell CN10K DPI(DMA Engine)
> > > > > > > > device's physical function which initializes DPI DMA
> > > > > > > > hardware's global configuration and enables hardware
> > > > > > > > mailbox channels between physical function (PF) and it's
> > > > > > > > virtual functions (VF). VF device drivers (User space
> > > > > > > > drivers) use this hw mailbox to communicate any required
> > > > > > > > device configuration on it's respective
> > > VF device.
> > > > > > > > Accordingly, this DPI PF driver provisions the VF device
> resources.
> > > > > > > >
> > > > > > > > At the hardware level, the DPI physical function (PF) acts
> > > > > > > > as a management interface to setup the VF device
> > > > > > > > resources, VF devices are only provisioned to handle or
> > > > > > > > control the actual DMA Engine's data transfer
> > > > > > > capabilities.
> > > > > > >
> > > > > > > No pointer to the userspace code that uses this? Why not?
> > > > > > > How are we supposed to be able to review this?
> > > > > >
> > > > > > Userspace code will use two functionalities (mailbox & ioctl)
> > > > > > from this driver. DPDK DMA driver uses the mailbox and the
> > > > > > dpdk application uses the ioctl to setup the device
> > > > > > attributes. We are waiting for this kernel driver get merged
> > > > > > to update the corresponding support in DPDK
> > > > > driver and applications. I will provide the pointers to both the
> > > > > use cases in userspace code.
> > > > > > Meanwhile below is the current dpdk dma driver that uses sysfs
> > > > > > based scheme to convey mbox requests to the kernel DPI driver
> > > > > > which gets
> > > > > replaced with hardware mailbox scheme once mrvl-cn10k-dpi kernel
> > > > > driver is merged.
> > > > > > https://urldefense.proofpoint.com/v2/url?u=https-
> > > > > 3A__github.com_DPDK_d
> > > > > > pdk_blob_main_drivers_common_cnxk_roc-
> > > > > 5Fdpi.c&d=DwIBAg&c=nKjWec2b6R0mO
> > > > > >
> > > > >
> > >
> yPaz7xtfQ&r=WllrYaumVkxaWjgKto6E_rtDQshhIhik2jkvzFyRhW8&m=o3EhoL
> > > > > s7dsod
> > > > > > -YHS438Wl2Pf_MKMBYegGSKteoX3qFTB0HV897ykpCVbTp-
> > > > > nmj4e&s=A6TJDFUtPm3ksJh
> > > > > > qop89CL8GgKj4sjkJIVi1-RdnUr8&e=
> > > > >
> > > > > So this is a DPDK thing? Ugh, do the networking people know about
> this?
> > > > > If not, why aren't they reviewing this?
> > > >
> > > > Actually, It's not networking related. Like the Linux kernel, DPDK
> > > > also supports multiple subsystems like network, scheduler, DMA,
> > > > mempool etc. Regarding the usecases, the DPDK Marvell DMA/DPI VF
> > > > driver interacts(over hardware mailbox) with the mrvl-cn10k-dpi
> > > > misc
> > > kernel driver(administrative driver) for setting up the VF device
> resources.
> > >
> > > So this is something that the PCI core should be concerned about then?
> >
> > No, it's a normal PCIe sriov capability implemented in all sriov capable PCIe
> devices.
> > Our PF device aka this driver in kernel space service mailbox requests
> > from userspace applications via VF devices. For instance, DPI VF
> > device from user space writes into mailbox registers and the DPI hardware
> triggers an interrupt to DPI PF device.
> > Upon PF interrupt, this driver services the mailbox requests.
>
> Isn't that a "normal" PCI thing? How is this different from other devices that
> have VF?
Looks like there is a lot of confusion for this device. Let me explain
There are two aspects for this DPI PF device.
a) It's a PCIe device so it is "using" some of the PCI services provided PCIe HW or PCI subsystem
b) It is "providing" non PCIe service(DPI HW administrative function) by using (a)
Let me enumerate PF device operations with above aspects.
1) Means to create VF(s) from PF. It's category (a) service and driver uses API (pci_sriov_configure_simple()) from PCI subsystem to implement it.
2) Means to get the interrupt(mailbox or any device specific interrupt). It's category (a) service and driver uses API (pci_alloc_irq_vectors()) from PCI subsystem to implement it.
3) Means to get the mailbox content from VF by using (2). It's category (b) service. This service is not part of PCI specification.
DPI PF device has the mailbox registers(DPI_MBOX_PF_VF_DATA registers) in its PCIe BAR space which are device specific.
4) Upon receiving DPI HW administrative function mailbox request, service it. Its category (b) service. This service is not part of PCI specification.
For instance, dpi_queue_open & close are requests sent from DPI VF device to DPI PF device for setting up the DPI VF queue resources. Once its setup by DPI PF,
then DPI VF device can use these queues. These queues are not part of PCIe specification. These queues are used for making DMA by DPI VF device/driver.
>
> > > > DPDK is one example that uses this driver, there can be other
> > > > userspace generic frameworks/applications where the virtual
> > > > functions are binded to userspace drivers and interact with
> > > > physical/administrative
> > > function driver running in the kernel.
> > >
> > > Are there other devices/drivers that do this today in Linux? Why
> > > make a device-specific api for this common functionality?
> >
> > The apis defined in this driver are specific to Marvell DPI hardware.
>
> The api, yes, but that's the point, shouldn't this be generic for all hardware
> that supports this? Implementation should be device specific, in the driver.
No. As mentioned above, it is not generic for all devices. (3) and (4) are specific to Marvell DPI PF device/driver. (1) and (2) are common for all the PCIe PF
device, which, this driver is using APIs from PCI subsystem.
>
> > For instance,
> > the variables molr(max outstanding load requests), fifo_max, ebus_port
> > are DPI hardware specific. Generally, drivers use driver-specific api
> > to configure any device-specific configuration which does not fit in common
> functionality right.
> >
> > Mailbox operations like dpi_queue_open & close are requests sent from
> > VF device to PF device for setting up the VF queue resources.
>
> Why is an ioctl to a random character device the correct api to userspace for
> this type of thing? Shouldn't this go through the PCI layer api instead?
No. Because it is not part of PCIe specification. PCI specification operations are controlled through PCI config space and extended config space.
These are some DPI device global configuration operations(ex: DPI_EBUS_PORTX_CFG, DPI_ENGX_BUF cfg) which are NOT part of PCI config space or extended config space.
There by, it does have any role in PCI layer API.
>
> thanks,
>
> greg k-h
On Sat, Apr 13, 2024, at 18:17, Vamsi Krishna Attunuru wrote:
> From: Greg KH <[email protected]>
>> On Sat, Apr 13, 2024 at 10:58:37AM +0000, Vamsi Krishna Attunuru wrote:
>> > From: Greg KH <[email protected]>
>> >
>> > No, it's a normal PCIe sriov capability implemented in all sriov capable PCIe
>> devices.
>> > Our PF device aka this driver in kernel space service mailbox requests
>> > from userspace applications via VF devices. For instance, DPI VF
>> > device from user space writes into mailbox registers and the DPI hardware
>> triggers an interrupt to DPI PF device.
>> > Upon PF interrupt, this driver services the mailbox requests.
>>
>> Isn't that a "normal" PCI thing? How is this different from other devices that
>> have VF?
>
> Looks like there is a lot of confusion for this device. Let me explain
> There are two aspects for this DPI PF device.
> a) It's a PCIe device so it is "using" some of the PCI services
> provided PCIe HW or PCI subsystem
> b) It is "providing" non PCIe service(DPI HW administrative function)
> by using (a)
> Let me enumerate PF device operations with above aspects.
> 1) Means to create VF(s) from PF. It's category (a) service and driver
> uses API (pci_sriov_configure_simple()) from PCI subsystem to implement
> it.
> 2) Means to get the interrupt(mailbox or any device specific
> interrupt). It's category (a) service and driver uses API
> (pci_alloc_irq_vectors()) from PCI subsystem to implement it.
> 3) Means to get the mailbox content from VF by using (2). It's category
> (b) service. This service is not part of PCI specification.
> DPI PF device has the mailbox registers(DPI_MBOX_PF_VF_DATA registers)
> in its PCIe BAR space which are device specific.
> 4) Upon receiving DPI HW administrative function mailbox request,
> service it. Its category (b) service. This service is not part of PCI
> specification.
> For instance, dpi_queue_open & close are requests sent from DPI VF
> device to DPI PF device for setting up the DPI VF queue resources. Once
> its setup by DPI PF,
> then DPI VF device can use these queues. These queues are not part of
> PCIe specification. These queues are used for making DMA by DPI VF
> device/driver.
It's not directly my area either, but as far as I can tell
from reading the competing sr-iov based device drivers, these
seem to handle all of the above in the network driver that
owns the PF rather than a separate driver, e.g. for the
first point:
$ git grep -w sriov_configure.= drivers/net/
drivers/net/ethernet/amazon/ena/ena_netdev.c: .sriov_configure = pci_sriov_configure_simple,
drivers/net/ethernet/amd/pds_core/main.c: .sriov_configure = pdsc_sriov_configure,
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c: .sriov_configure = bnx2x_sriov_configure,
drivers/net/ethernet/broadcom/bnxt/bnxt.c: .sriov_configure = bnxt_sriov_configure,
drivers/net/ethernet/cavium/liquidio/lio_main.c: .sriov_configure = liquidio_enable_sriov,
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c: .sriov_configure = cxgb4_iov_configure,
drivers/net/ethernet/emulex/benet/be_main.c: .sriov_configure = be_pci_sriov_configure,
drivers/net/ethernet/freescale/enetc/enetc_pf.c: .sriov_configure = enetc_sriov_configure,
drivers/net/ethernet/fungible/funeth/funeth_main.c: .sriov_configure = funeth_sriov_configure,
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c: .sriov_configure = hns3_pci_sriov_configure,
drivers/net/ethernet/huawei/hinic/hinic_main.c: .sriov_configure = hinic_pci_sriov_configure,
drivers/net/ethernet/intel/fm10k/fm10k_pci.c: .sriov_configure = fm10k_iov_configure,
drivers/net/ethernet/intel/i40e/i40e_main.c: .sriov_configure = i40e_pci_sriov_configure,
drivers/net/ethernet/intel/ice/ice_main.c: .sriov_configure = ice_sriov_configure,
drivers/net/ethernet/intel/idpf/idpf_main.c: .sriov_configure = idpf_sriov_configure,
drivers/net/ethernet/intel/igb/igb_main.c: .sriov_configure = igb_pci_sriov_configure,
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c: .sriov_configure = ixgbe_pci_sriov_configure,
drivers/net/ethernet/marvell/octeon_ep/octep_main.c: .sriov_configure = octep_sriov_configure,
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c: .sriov_configure = otx2_sriov_configure
drivers/net/ethernet/netronome/nfp/nfp_main.c: .sriov_configure = nfp_pcie_sriov_configure,
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c: .sriov_configure = ionic_sriov_configure,
drivers/net/ethernet/qlogic/qede/qede_main.c: .sriov_configure = qede_sriov_configure,
drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c: .sriov_configure = qlcnic_pci_sriov_configure,
drivers/net/ethernet/sfc/ef10.c: .sriov_configure = efx_ef10_sriov_configure,
drivers/net/ethernet/sfc/ef100.c: .sriov_configure = ef100_pci_sriov_configure,
drivers/net/ethernet/sfc/ef100_nic.c: .sriov_configure = IS_ENABLED(CONFIG_SFC_SRIOV) ?
drivers/net/ethernet/sfc/efx.c: .sriov_configure = efx_pci_sriov_configure,
drivers/net/ethernet/sfc/siena/efx.c: .sriov_configure = efx_pci_sriov_configure,
drivers/net/ethernet/sfc/siena/siena.c: .sriov_configure = efx_siena_sriov_configure,
In what way is your hardware different from all the others?
Arnd
> -----Original Message-----
> From: Arnd Bergmann <[email protected]>
> Sent: Sunday, April 14, 2024 12:41 AM
> To: Vamsi Krishna Attunuru <[email protected]>; Greg Kroah-Hartman
> <[email protected]>
> Cc: [email protected]; Jerin Jacob <[email protected]>
> Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> Octeon CN10K DPI administrative driver
>
> On Sat, Apr 13, 2024, at 18:17, Vamsi Krishna Attunuru wrote:
> > From: Greg KH <[email protected]>
> >> On Sat, Apr 13, 2024 at 10:58:37AM +0000, Vamsi Krishna Attunuru wrote:
> >> > From: Greg KH <[email protected]>
> >> >
> >> > No, it's a normal PCIe sriov capability implemented in all sriov
> >> > capable PCIe
> >> devices.
> >> > Our PF device aka this driver in kernel space service mailbox
> >> > requests from userspace applications via VF devices. For instance,
> >> > DPI VF device from user space writes into mailbox registers and the
> >> > DPI hardware
> >> triggers an interrupt to DPI PF device.
> >> > Upon PF interrupt, this driver services the mailbox requests.
> >>
> >> Isn't that a "normal" PCI thing? How is this different from other
> >> devices that have VF?
> >
> > Looks like there is a lot of confusion for this device. Let me explain
> > There are two aspects for this DPI PF device.
> > a) It's a PCIe device so it is "using" some of the PCI services
> > provided PCIe HW or PCI subsystem
> > b) It is "providing" non PCIe service(DPI HW administrative function)
> > by using (a) Let me enumerate PF device operations with above aspects.
> > 1) Means to create VF(s) from PF. It's category (a) service and driver
> > uses API (pci_sriov_configure_simple()) from PCI subsystem to
> > implement it.
> > 2) Means to get the interrupt(mailbox or any device specific
> > interrupt). It's category (a) service and driver uses API
> > (pci_alloc_irq_vectors()) from PCI subsystem to implement it.
> > 3) Means to get the mailbox content from VF by using (2). It's
> > category
> > (b) service. This service is not part of PCI specification.
> > DPI PF device has the mailbox registers(DPI_MBOX_PF_VF_DATA
> registers)
> > in its PCIe BAR space which are device specific.
> > 4) Upon receiving DPI HW administrative function mailbox request,
> > service it. Its category (b) service. This service is not part of PCI
> > specification.
> > For instance, dpi_queue_open & close are requests sent from DPI VF
> > device to DPI PF device for setting up the DPI VF queue resources.
> > Once its setup by DPI PF, then DPI VF device can use these queues.
> > These queues are not part of PCIe specification. These queues are used
> > for making DMA by DPI VF device/driver.
>
> It's not directly my area either, but as far as I can tell from reading the
> competing sr-iov based device drivers, these seem to handle all of the above
> in the network driver that owns the PF rather than a separate driver, e.g for
> the first point:
>
> $ git grep -w sriov_configure.= drivers/net/
> drivers/net/ethernet/amazon/ena/ena_netdev.c: .sriov_configure =
> pci_sriov_configure_simple,
> drivers/net/ethernet/amd/pds_core/main.c: .sriov_configure =
> pdsc_sriov_configure,
> drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c: .sriov_configure =
> bnx2x_sriov_configure,
> drivers/net/ethernet/broadcom/bnxt/bnxt.c: .sriov_configure =
> bnxt_sriov_configure,
> drivers/net/ethernet/cavium/liquidio/lio_main.c: .sriov_configure =
> liquidio_enable_sriov,
> drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c: .sriov_configure =
> cxgb4_iov_configure,
> drivers/net/ethernet/emulex/benet/be_main.c: .sriov_configure =
> be_pci_sriov_configure,
> drivers/net/ethernet/freescale/enetc/enetc_pf.c: .sriov_configure =
> enetc_sriov_configure,
> drivers/net/ethernet/fungible/funeth/funeth_main.c: .sriov_configure =
> funeth_sriov_configure,
> drivers/net/ethernet/hisilicon/hns3/hns3_enet.c: .sriov_configure =
> hns3_pci_sriov_configure,
> drivers/net/ethernet/huawei/hinic/hinic_main.c: .sriov_configure =
> hinic_pci_sriov_configure,
> drivers/net/ethernet/intel/fm10k/fm10k_pci.c: .sriov_configure =
> fm10k_iov_configure,
> drivers/net/ethernet/intel/i40e/i40e_main.c: .sriov_configure =
> i40e_pci_sriov_configure,
> drivers/net/ethernet/intel/ice/ice_main.c: .sriov_configure =
> ice_sriov_configure,
> drivers/net/ethernet/intel/idpf/idpf_main.c: .sriov_configure =
> idpf_sriov_configure,
> drivers/net/ethernet/intel/igb/igb_main.c: .sriov_configure =
> igb_pci_sriov_configure,
> drivers/net/ethernet/intel/ixgbe/ixgbe_main.c: .sriov_configure =
> ixgbe_pci_sriov_configure,
> drivers/net/ethernet/marvell/octeon_ep/octep_main.c: .sriov_configure =
> octep_sriov_configure,
> drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c: .sriov_configure =
> otx2_sriov_configure
> drivers/net/ethernet/netronome/nfp/nfp_main.c: .sriov_configure =
> nfp_pcie_sriov_configure,
> drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c: .sriov_configure =
> ionic_sriov_configure,
> drivers/net/ethernet/qlogic/qede/qede_main.c: .sriov_configure =
> qede_sriov_configure,
> drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c: .sriov_configure =
> qlcnic_pci_sriov_configure,
> drivers/net/ethernet/sfc/ef10.c: .sriov_configure =
> efx_ef10_sriov_configure,
> drivers/net/ethernet/sfc/ef100.c: .sriov_configure =
> ef100_pci_sriov_configure,
> drivers/net/ethernet/sfc/ef100_nic.c: .sriov_configure =
> IS_ENABLED(CONFIG_SFC_SRIOV) ?
> drivers/net/ethernet/sfc/efx.c: .sriov_configure = efx_pci_sriov_configure,
> drivers/net/ethernet/sfc/siena/efx.c: .sriov_configure =
> efx_pci_sriov_configure,
> drivers/net/ethernet/sfc/siena/siena.c: .sriov_configure =
> efx_siena_sriov_configure,
>
> In what way is your hardware different from all the others?
All of above devices are network devices which implements struct net_device_ops.
i.e Those PCI devices are networking devices which are capable of sending/receiving network packets.
This device doesn't have networking functionality to implement struct net_device_ops, It's a simple PCIe PF
device enables it's VFs and services any mailbox requests.
Couple of misc pcie drivers that enable its VFs are
UPSTREAM/linux# grep -nr "sriov_configure" drivers/misc/
drivers/misc/genwqe/card_base.c:1327:static int genwqe_sriov_configure(struct pci_dev *dev, int numvfs)
drivers/misc/genwqe/card_base.c:1358: .sriov_configure = genwqe_sriov_configure,
drivers/misc/pci_endpoint_test.c:1011: .sriov_configure = pci_sriov_configure_simple,
>
> Arnd
On Sun, Apr 14, 2024 at 09:33:37AM +0000, Vamsi Krishna Attunuru wrote:
>
>
> > -----Original Message-----
> > From: Arnd Bergmann <[email protected]>
> > Sent: Sunday, April 14, 2024 12:41 AM
> > To: Vamsi Krishna Attunuru <[email protected]>; Greg Kroah-Hartman
> > <[email protected]>
> > Cc: [email protected]; Jerin Jacob <[email protected]>
> > Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > Octeon CN10K DPI administrative driver
> >
> > On Sat, Apr 13, 2024, at 18:17, Vamsi Krishna Attunuru wrote:
> > > From: Greg KH <[email protected]>
> > >> On Sat, Apr 13, 2024 at 10:58:37AM +0000, Vamsi Krishna Attunuru wrote:
> > >> > From: Greg KH <[email protected]>
> > >> >
> > >> > No, it's a normal PCIe sriov capability implemented in all sriov
> > >> > capable PCIe
> > >> devices.
> > >> > Our PF device aka this driver in kernel space service mailbox
> > >> > requests from userspace applications via VF devices. For instance,
> > >> > DPI VF device from user space writes into mailbox registers and the
> > >> > DPI hardware
> > >> triggers an interrupt to DPI PF device.
> > >> > Upon PF interrupt, this driver services the mailbox requests.
> > >>
> > >> Isn't that a "normal" PCI thing? How is this different from other
> > >> devices that have VF?
> > >
> > > Looks like there is a lot of confusion for this device. Let me explain
> > > There are two aspects for this DPI PF device.
> > > a) It's a PCIe device so it is "using" some of the PCI services
> > > provided PCIe HW or PCI subsystem
> > > b) It is "providing" non PCIe service(DPI HW administrative function)
> > > by using (a) Let me enumerate PF device operations with above aspects.
> > > 1) Means to create VF(s) from PF. It's category (a) service and driver
> > > uses API (pci_sriov_configure_simple()) from PCI subsystem to
> > > implement it.
> > > 2) Means to get the interrupt(mailbox or any device specific
> > > interrupt). It's category (a) service and driver uses API
> > > (pci_alloc_irq_vectors()) from PCI subsystem to implement it.
> > > 3) Means to get the mailbox content from VF by using (2). It's
> > > category
> > > (b) service. This service is not part of PCI specification.
> > > DPI PF device has the mailbox registers(DPI_MBOX_PF_VF_DATA
> > registers)
> > > in its PCIe BAR space which are device specific.
> > > 4) Upon receiving DPI HW administrative function mailbox request,
> > > service it. Its category (b) service. This service is not part of PCI
> > > specification.
> > > For instance, dpi_queue_open & close are requests sent from DPI VF
> > > device to DPI PF device for setting up the DPI VF queue resources.
> > > Once its setup by DPI PF, then DPI VF device can use these queues.
> > > These queues are not part of PCIe specification. These queues are used
> > > for making DMA by DPI VF device/driver.
> >
> > It's not directly my area either, but as far as I can tell from reading the
> > competing sr-iov based device drivers, these seem to handle all of the above
> > in the network driver that owns the PF rather than a separate driver, e.g. for
> > the first point:
> >
> > $ git grep -w sriov_configure.= drivers/net/
> > drivers/net/ethernet/amazon/ena/ena_netdev.c: .sriov_configure =
> > pci_sriov_configure_simple,
> > drivers/net/ethernet/amd/pds_core/main.c: .sriov_configure =
> > pdsc_sriov_configure,
> > drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c: .sriov_configure =
> > bnx2x_sriov_configure,
> > drivers/net/ethernet/broadcom/bnxt/bnxt.c: .sriov_configure =
> > bnxt_sriov_configure,
> > drivers/net/ethernet/cavium/liquidio/lio_main.c: .sriov_configure =
> > liquidio_enable_sriov,
> > drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c: .sriov_configure =
> > cxgb4_iov_configure,
> > drivers/net/ethernet/emulex/benet/be_main.c: .sriov_configure =
> > be_pci_sriov_configure,
> > drivers/net/ethernet/freescale/enetc/enetc_pf.c: .sriov_configure =
> > enetc_sriov_configure,
> > drivers/net/ethernet/fungible/funeth/funeth_main.c: .sriov_configure =
> > funeth_sriov_configure,
> > drivers/net/ethernet/hisilicon/hns3/hns3_enet.c: .sriov_configure =
> > hns3_pci_sriov_configure,
> > drivers/net/ethernet/huawei/hinic/hinic_main.c: .sriov_configure =
> > hinic_pci_sriov_configure,
> > drivers/net/ethernet/intel/fm10k/fm10k_pci.c: .sriov_configure =
> > fm10k_iov_configure,
> > drivers/net/ethernet/intel/i40e/i40e_main.c: .sriov_configure =
> > i40e_pci_sriov_configure,
> > drivers/net/ethernet/intel/ice/ice_main.c: .sriov_configure =
> > ice_sriov_configure,
> > drivers/net/ethernet/intel/idpf/idpf_main.c: .sriov_configure =
> > idpf_sriov_configure,
> > drivers/net/ethernet/intel/igb/igb_main.c: .sriov_configure =
> > igb_pci_sriov_configure,
> > drivers/net/ethernet/intel/ixgbe/ixgbe_main.c: .sriov_configure =
> > ixgbe_pci_sriov_configure,
> > drivers/net/ethernet/marvell/octeon_ep/octep_main.c: .sriov_configure =
> > octep_sriov_configure,
> > drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c: .sriov_configure =
> > otx2_sriov_configure
> > drivers/net/ethernet/netronome/nfp/nfp_main.c: .sriov_configure =
> > nfp_pcie_sriov_configure,
> > drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c: .sriov_configure =
> > ionic_sriov_configure,
> > drivers/net/ethernet/qlogic/qede/qede_main.c: .sriov_configure =
> > qede_sriov_configure,
> > drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c: .sriov_configure =
> > qlcnic_pci_sriov_configure,
> > drivers/net/ethernet/sfc/ef10.c: .sriov_configure =
> > efx_ef10_sriov_configure,
> > drivers/net/ethernet/sfc/ef100.c: .sriov_configure =
> > ef100_pci_sriov_configure,
> > drivers/net/ethernet/sfc/ef100_nic.c: .sriov_configure =
> > IS_ENABLED(CONFIG_SFC_SRIOV) ?
> > drivers/net/ethernet/sfc/efx.c: .sriov_configure = efx_pci_sriov_configure,
> > drivers/net/ethernet/sfc/siena/efx.c: .sriov_configure =
> > efx_pci_sriov_configure,
> > drivers/net/ethernet/sfc/siena/siena.c: .sriov_configure =
> > efx_siena_sriov_configure,
> >
> > In what way is your hardware different from all the others?
>
> All of above devices are network devices which implements struct net_device_ops.
> i.e Those PCI devices are networking devices which are capable of sending/receiving network packets.
> This device doesn't have networking functionality to implement struct net_device_ops, It's a simple PCIe PF
> device enables it's VFs and services any mailbox requests.
What driver handles the "mailbox requests"? What are these requests
for?
thanks,
greg k-h
> -----Original Message-----
> From: Greg Kroah-Hartman <[email protected]>
> Sent: Sunday, April 14, 2024 3:16 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: Arnd Bergmann <[email protected]>; [email protected]; Jerin
> Jacob <[email protected]>
> Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> Octeon CN10K DPI administrative driver
>
> On Sun, Apr 14, 2024 at 09:33:37AM +0000, Vamsi Krishna Attunuru wrote:
> >
> >
> > > -----Original Message-----
> > > From: Arnd Bergmann <[email protected]>
> > > Sent: Sunday, April 14, 2024 12:41 AM
> > > To: Vamsi Krishna Attunuru <[email protected]>; Greg
> > > Kroah-Hartman <[email protected]>
> > > Cc: [email protected]; Jerin Jacob <[email protected]>
> > > Subject: Re: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > Octeon CN10K DPI administrative driver
> > >
> > > On Sat, Apr 13, 2024, at 18:17, Vamsi Krishna Attunuru wrote:
> > > > From: Greg KH <[email protected]>
> > > >> On Sat, Apr 13, 2024 at 10:58:37AM +0000, Vamsi Krishna Attunuru
> wrote:
> > > >> > From: Greg KH <[email protected]>
> > > >> >
> > > >> > No, it's a normal PCIe sriov capability implemented in all
> > > >> > sriov capable PCIe
> > > >> devices.
> > > >> > Our PF device aka this driver in kernel space service mailbox
> > > >> > requests from userspace applications via VF devices. For
> > > >> > instance, DPI VF device from user space writes into mailbox
> > > >> > registers and the DPI hardware
> > > >> triggers an interrupt to DPI PF device.
> > > >> > Upon PF interrupt, this driver services the mailbox requests.
> > > >>
> > > >> Isn't that a "normal" PCI thing? How is this different from
> > > >> other devices that have VF?
> > > >
> > > > Looks like there is a lot of confusion for this device. Let me
> > > > explain There are two aspects for this DPI PF device.
> > > > a) It's a PCIe device so it is "using" some of the PCI services
> > > > provided PCIe HW or PCI subsystem
> > > > b) It is "providing" non PCIe service(DPI HW administrative
> > > > function) by using (a) Let me enumerate PF device operations with
> above aspects.
> > > > 1) Means to create VF(s) from PF. It's category (a) service and
> > > > driver uses API (pci_sriov_configure_simple()) from PCI subsystem
> > > > to implement it.
> > > > 2) Means to get the interrupt(mailbox or any device specific
> > > > interrupt). It's category (a) service and driver uses API
> > > > (pci_alloc_irq_vectors()) from PCI subsystem to implement it.
> > > > 3) Means to get the mailbox content from VF by using (2). It's
> > > > category
> > > > (b) service. This service is not part of PCI specification.
> > > > DPI PF device has the mailbox registers(DPI_MBOX_PF_VF_DATA
> > > registers)
> > > > in its PCIe BAR space which are device specific.
> > > > 4) Upon receiving DPI HW administrative function mailbox request,
> > > > service it. Its category (b) service. This service is not part of
> > > > PCI specification.
> > > > For instance, dpi_queue_open & close are requests sent from DPI VF
> > > > device to DPI PF device for setting up the DPI VF queue resources.
> > > > Once its setup by DPI PF, then DPI VF device can use these queues.
> > > > These queues are not part of PCIe specification. These queues are
> > > > used for making DMA by DPI VF device/driver.
> > >
> > > It's not directly my area either, but as far as I can tell from
> > > reading the competing sr-iov based device drivers, these seem to
> > > handle all of the above in the network driver that owns the PF
> > > rather than a separate driver, e.g. for the first point:
> > >
> > > $ git grep -w sriov_configure.= drivers/net/
> > > drivers/net/ethernet/amazon/ena/ena_netdev.c: .sriov_configure =
> > > pci_sriov_configure_simple,
> > > drivers/net/ethernet/amd/pds_core/main.c: .sriov_configure =
> > > pdsc_sriov_configure,
> > > drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c:
> .sriov_configure =
> > > bnx2x_sriov_configure,
> > > drivers/net/ethernet/broadcom/bnxt/bnxt.c: .sriov_configure =
> > > bnxt_sriov_configure,
> > > drivers/net/ethernet/cavium/liquidio/lio_main.c: .sriov_configure =
> > > liquidio_enable_sriov,
> > > drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c: .sriov_configure =
> > > cxgb4_iov_configure,
> > > drivers/net/ethernet/emulex/benet/be_main.c: .sriov_configure =
> > > be_pci_sriov_configure,
> > > drivers/net/ethernet/freescale/enetc/enetc_pf.c: .sriov_configure =
> > > enetc_sriov_configure,
> > > drivers/net/ethernet/fungible/funeth/funeth_main.c: .sriov_configure
> =
> > > funeth_sriov_configure,
> > > drivers/net/ethernet/hisilicon/hns3/hns3_enet.c: .sriov_configure =
> > > hns3_pci_sriov_configure,
> > > drivers/net/ethernet/huawei/hinic/hinic_main.c: .sriov_configure =
> > > hinic_pci_sriov_configure,
> > > drivers/net/ethernet/intel/fm10k/fm10k_pci.c: .sriov_configure =
> > > fm10k_iov_configure,
> > > drivers/net/ethernet/intel/i40e/i40e_main.c: .sriov_configure =
> > > i40e_pci_sriov_configure,
> > > drivers/net/ethernet/intel/ice/ice_main.c: .sriov_configure =
> > > ice_sriov_configure,
> > > drivers/net/ethernet/intel/idpf/idpf_main.c: .sriov_configure =
> > > idpf_sriov_configure,
> > > drivers/net/ethernet/intel/igb/igb_main.c: .sriov_configure =
> > > igb_pci_sriov_configure,
> > > drivers/net/ethernet/intel/ixgbe/ixgbe_main.c: .sriov_configure =
> > > ixgbe_pci_sriov_configure,
> > > drivers/net/ethernet/marvell/octeon_ep/octep_main.c:
> .sriov_configure =
> > > octep_sriov_configure,
> > > drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c: .sriov_configure
> =
> > > otx2_sriov_configure
> > > drivers/net/ethernet/netronome/nfp/nfp_main.c: .sriov_configure
> =
> > > nfp_pcie_sriov_configure,
> > > drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c: .sriov_configure
> =
> > > ionic_sriov_configure,
> > > drivers/net/ethernet/qlogic/qede/qede_main.c: .sriov_configure =
> > > qede_sriov_configure,
> > > drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c: .sriov_configure =
> > > qlcnic_pci_sriov_configure,
> > > drivers/net/ethernet/sfc/ef10.c: .sriov_configure =
> > > efx_ef10_sriov_configure,
> > > drivers/net/ethernet/sfc/ef100.c: .sriov_configure =
> > > ef100_pci_sriov_configure,
> > > drivers/net/ethernet/sfc/ef100_nic.c: .sriov_configure =
> > > IS_ENABLED(CONFIG_SFC_SRIOV) ?
> > > drivers/net/ethernet/sfc/efx.c: .sriov_configure =
> efx_pci_sriov_configure,
> > > drivers/net/ethernet/sfc/siena/efx.c: .sriov_configure =
> > > efx_pci_sriov_configure,
> > > drivers/net/ethernet/sfc/siena/siena.c: .sriov_configure =
> > > efx_siena_sriov_configure,
> > >
> > > In what way is your hardware different from all the others?
> >
> > All of above devices are network devices which implements struct
> net_device_ops.
> > i.e Those PCI devices are networking devices which are capable of
> sending/receiving network packets.
> > This device doesn't have networking functionality to implement struct
> > net_device_ops, It's a simple PCIe PF device enables it's VFs and services
> any mailbox requests.
>
> What driver handles the "mailbox requests"? What are these requests for?
I think, I have already mentioned this in the previous reply. Copying the same here. Please see (4) in [1].
The DPI PF driver(this driver) handles the mailbox request from DPI VF (a userspace driver implemented using vfio uapis).
DPI PF driver(this driver) does not fit to any of the device class(ethernet, crypto, dma..) in linux kernel hence making it
as misc device driver. Standard device class always will have standard device function. For example,
ethernet device to send/receive ethernet frames, crypto device to enable crypto transformations,
dma device to enable copying data from source to destination memory.
Now, Why HW designers choose to have DPI(DMA Engine) PF device in first place?
a) DPI VF(not DPI PF) device has capability to do the DMA (copying data from source to destination memory).
b) In order to do DMA, DPI VF device needs a DPI queue.
c) Now here is the catch, when VF device starts, it does not have its queues configured. So, DPI VF device/driver
asks(via mailbox) DPI PF(this driver) for the queue setup with required configuration. dpi_queue_open() does the same.
d) Now you may ask, why VF device does NOT configure its queues on its own. That is HW resources
provision optimization(introduced by HW designers), where DMA engines are provisioned across the VF device queues.
So, PF (administrative) arbitrates the request from different VF devices via mailbox and allow to configure _global_ resources
which does not belong to VF.
Hope it clarifies.
[1]
------------------------------
Looks like there is a lot of confusion for this device. Let me explain
There are two aspects for this DPI PF device.
a) It's a PCIe device so it is "using" some of the PCI services provided PCIe HW or PCI subsystem
b) It is "providing" non PCIe service(DPI HW administrative function) by using (a)
Let me enumerate PF device operations with above aspects.
1) Means to create VF(s) from PF. It's category (a) service and driver uses API (pci_sriov_configure_simple()) from PCI subsystem to implement it.
2) Means to get the interrupt(mailbox or any device specific interrupt). It's category (a) service and driver uses API (pci_alloc_irq_vectors()) from PCI subsystem to implement it.
3) Means to get the mailbox content from VF by using (2). It's category (b) service. This service is not part of PCI specification.
DPI PF device has the mailbox registers(DPI_MBOX_PF_VF_DATA registers) in its PCIe BAR space which are device specific.
4) Upon receiving DPI HW administrative function mailbox request, service it. Its category (b) service. This service is not part of PCI specification.
For instance, dpi_queue_open & close are requests sent from DPI VF device to DPI PF device for setting up the DPI VF queue resources. Once its setup by DPI PF,
then DPI VF device can use these queues. These queues are not part of PCIe specification. These queues are used for making DMA by DPI VF device/driver.
-------------------------------
>
> thanks,
>
> greg k-h
>
> > -----Original Message-----
> > From: Greg KH <[email protected]>
> > Sent: Friday, April 12, 2024 5:57 PM
> > To: Vamsi Krishna Attunuru <[email protected]>
> > Cc: [email protected]; [email protected]
> > Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > Octeon CN10K DPI administrative driver
> >
> > Prioritize security for external emails: Confirm sender and content
> > safety before clicking links or opening attachments
> >
> > ----------------------------------------------------------------------
> > On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's
> > > physical function which initializes DPI DMA hardware's global
> > > configuration and enables hardware mailbox channels between physical
> > > function (PF) and it's virtual functions (VF). VF device drivers
> > > (User space drivers) use this hw mailbox to communicate any required
> > > device configuration on it's respective VF device. Accordingly, this
> > > DPI PF driver provisions the VF device resources.
> > >
> > > At the hardware level, the DPI physical function (PF) acts as a
> > > management interface to setup the VF device resources, VF devices
> > > are only provisioned to handle or control the actual DMA Engine's
> > > data transfer
> > capabilities.
> >
> > No pointer to the userspace code that uses this? Why not? How are we
> > supposed to be able to review this?
>
Hi Greg, please check the below files for userspace code that interact with this kernel driver.
driver/roc_dpi.c provides the mailbox interface to communicate with this kernel driver.
application/main.c is the DPI DMA application which uses this misc driver to configure
the device with required mps, mrrs, fifo_mask parameters.
https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/driver/roc_dpi.c
https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/application/main.c
On Thu, Apr 25, 2024 at 01:36:05PM +0000, Vamsi Krishna Attunuru wrote:
> >
> > > -----Original Message-----
> > > From: Greg KH <[email protected]>
> > > Sent: Friday, April 12, 2024 5:57 PM
> > > To: Vamsi Krishna Attunuru <[email protected]>
> > > Cc: [email protected]; [email protected]
> > > Subject: [EXTERNAL] Re: [PATCH v5 1/1] misc: mrvl-cn10k-dpi: add
> > > Octeon CN10K DPI administrative driver
> > >
> > > Prioritize security for external emails: Confirm sender and content
> > > safety before clicking links or opening attachments
> > >
> > > ----------------------------------------------------------------------
> > > On Fri, Apr 12, 2024 at 05:10:05AM -0700, Vamsi Attunuru wrote:
> > > > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's
> > > > physical function which initializes DPI DMA hardware's global
> > > > configuration and enables hardware mailbox channels between physical
> > > > function (PF) and it's virtual functions (VF). VF device drivers
> > > > (User space drivers) use this hw mailbox to communicate any required
> > > > device configuration on it's respective VF device. Accordingly, this
> > > > DPI PF driver provisions the VF device resources.
> > > >
> > > > At the hardware level, the DPI physical function (PF) acts as a
> > > > management interface to setup the VF device resources, VF devices
> > > > are only provisioned to handle or control the actual DMA Engine's
> > > > data transfer
> > > capabilities.
> > >
> > > No pointer to the userspace code that uses this? Why not? How are we
> > > supposed to be able to review this?
> >
> Hi Greg, please check the below files for userspace code that interact with this kernel driver.
> driver/roc_dpi.c provides the mailbox interface to communicate with this kernel driver.
> application/main.c is the DPI DMA application which uses this misc driver to configure
> the device with required mps, mrrs, fifo_mask parameters.
>
> https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/driver/roc_dpi.c
> https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/application/main.c
Please provide this information in a new version of the patch, looking
at this now when we don't have the kernel code present is almost
impossible, sorry.
thanks,
greg k-h
Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
function which initializes DPI DMA hardware's global configuration and
enables hardware mailbox channels between physical function (PF) and
it's virtual functions (VF). VF device drivers (User space drivers) use
this hw mailbox to communicate any required device configuration on it's
respective VF device. Accordingly, this DPI PF driver provisions the
VF device resources.
At the hardware level, the DPI physical function (PF) acts as a management
interface to setup the VF device resources, VF devices are only provisioned
to handle or control the actual DMA Engine's data transfer capabilities.
Signed-off-by: Vamsi Attunuru <[email protected]>
---
Changes V5 -> V6:
- Updated documentation
- Fixed data types in uapi file
Changes V4 -> V5:
- Fixed license and data types in uapi file
Changes V3 -> V4:
- Moved ioctl definations to .h file
- Fixed structure alignements which are passed in ioctl
Changes V2 -> V3:
- Added ioctl operation to the fops
- Used managed version of kzalloc & request_irq
- Addressed miscellaneous comments
Changes V1 -> V2:
- Fixed return values and busy-wait loops
- Merged .h file into .c file
- Fixed directory structure
- Removed module params
- Registered the device as misc device
Below are the userspace code details that interacts with this kernel driver.
driver/roc_dpi.c provides the mailbox interface to communicate with this kernel driver.[1]
application/main.c is the DPI DMA application which uses this misc driver to configure.
the device with required mps, mrrs, fifo_mask parameters. [2]
[1]. https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/driver/roc_dpi.c
[2]. https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/application/main.c
Documentation/misc-devices/index.rst | 1 +
Documentation/misc-devices/mrvl_cn10k_dpi.rst | 43 ++
.../userspace-api/ioctl/ioctl-number.rst | 1 +
MAINTAINERS | 5 +
drivers/misc/Kconfig | 13 +
drivers/misc/Makefile | 2 +
drivers/misc/mrvl_cn10k_dpi.c | 685 ++++++++++++++++++
include/uapi/misc/mrvl_cn10k_dpi.h | 37 +
8 files changed, 787 insertions(+)
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index 2d0ce9138588..10f2e0f74e45 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -20,6 +20,7 @@ fit into other categories.
ics932s401
isl29003
lis3lv02d
+ mrvl_cn10k_dpi
max6875
oxsemi-tornado
pci-endpoint-test
diff --git a/Documentation/misc-devices/mrvl_cn10k_dpi.rst b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
new file mode 100644
index 000000000000..a1a914fb2d27
--- /dev/null
+++ b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
@@ -0,0 +1,43 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===============================================
+Marvell CN10K DMA packet interface (DPI) driver
+===============================================
+
+Overview
+========
+
+DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
+DPI hardware comprises a physical function (PF), its virtual functions,
+mailbox logic, and a set of DMA engines & DMA command queues.
+
+DPI PF function is an administrative function which services the mailbox
+requests from its VF functions and provisions DMA engine resources to
+it's VF functions.
+
+mrvl_cn10k_dpi.ko misc driver loads on DPI PF device and services the
+mailbox commands submitted by the VF devices and accordingly initializes
+the DMA engines and VF device's DMA command queues. Also, driver creates
+/dev/mrvl-cn10k-dpi node to set DMA engine and pem port attributes like
+fifo length, molr, mps & mrrs.
+
+DPI PF driver is just an administrative driver to setup its VF device's
+queues and provisions the hardware resources, it can not initiate any
+DMA operations. Only VF devices are provisioned with DMA capabilities.
+
+Driver location
+===============
+
+drivers/misc/mrvl_cn10k_dpi.c
+
+Driver IOCTLs
+=============
+
+:c:macro::`DPI_MPS_MRRS_CFG`
+ioctl that sets max payload size & max read request size parameters of
+a pem port to which DMA engines are wired.
+
+
+:c:macro::`DPI_ENGINE_CFG`
+ioctl that sets DMA engine's fifo sizes & max outstanding load request
+thresholds.
diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst
index 457e16f06e04..e6fd0c386b59 100644
--- a/Documentation/userspace-api/ioctl/ioctl-number.rst
+++ b/Documentation/userspace-api/ioctl/ioctl-number.rst
@@ -358,6 +358,7 @@ Code Seq# Include File Comments
0xB6 all linux/fpga-dfl.h
0xB7 all uapi/linux/remoteproc_cdev.h <mailto:[email protected]>
0xB7 all uapi/linux/nsfs.h <mailto:Andrei Vagin <[email protected]>>
+0xB8 01-02 uapi/misc/mrvl_cn10k_dpi.h Marvell CN10K DPI driver
0xC0 00-0F linux/usb/iowarrior.h
0xCA 00-0F uapi/misc/cxl.h
0xCA 10-2F uapi/misc/ocxl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 960512bec428..ab77232d583e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13104,6 +13104,11 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
+MARVELL OCTEON CN10K DPI DRIVER
+M: Vamsi Attunuru <[email protected]>
+S: Maintained
+F: drivers/misc/mrvl_cn10k_dpi.c
+
MATROX FRAMEBUFFER DRIVER
L: [email protected]
S: Orphan
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4fb291f0bf7c..78470ef2538f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -574,6 +574,19 @@ config NSM
To compile this driver as a module, choose M here.
The module will be called nsm.
+config MARVELL_CN10K_DPI
+ tristate "Octeon CN10K DPI driver"
+ depends on ARM64 && PCI
+ help
+ Enables Octeon CN10K DMA packet interface (DPI) driver which intializes
+ DPI hardware's physical function (PF) device's global configuration and
+ its virtual function's (VFs) resource configuration to enable DMA transfers.
+ DPI PF device does not have any data movement functionality, it only serves
+ VF's resource configuration requests.
+
+ To compile this driver as a module, choose M here: the module
+ will be called mrvl_cn10k_dpi.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ea6ea5bbbc9c..5106bf96ea5c 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -68,3 +68,5 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
obj-$(CONFIG_NSM) += nsm.o
+obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
+obj-y += mrvl_cn10k_dpi.o
diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
new file mode 100644
index 000000000000..bd99583994f9
--- /dev/null
+++ b/drivers/misc/mrvl_cn10k_dpi.c
@@ -0,0 +1,685 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <uapi/misc/mrvl_cn10k_dpi.h>
+
+#define DPI_DRV_NAME "mrvl-cn10k-dpi"
+
+/* PCI device IDs */
+#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
+#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xB900
+
+/* PCI BAR nos */
+#define PCI_DPI_CFG_BAR 0
+
+/* MSI-X interrupts */
+#define DPI_MAX_REQQ_INT 32
+#define DPI_MAX_CC_INT 64
+
+/* MBOX MSI-X interrupt vector index */
+#define DPI_MBOX_PF_VF_INT_IDX 0x75
+
+#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
+
+#define DPI_MAX_VFS 32
+
+#define DPI_ENGINE_MASK GENMASK(2, 0)
+
+#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) (((x) & GENMASK_ULL(15, 0)) << 16)
+#define DPI_DMA_IDS_INST_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 40)
+#define DPI_DMA_IDS_DMA_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 32)
+#define DPI_DMA_ENG_EN_MOLR(x) (((x) & GENMASK_ULL(9, 0)) << 32)
+#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & GENMASK(2, 0)) << 4)
+#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) & GENMASK(15, 0))
+#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19, 0))
+#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13, 0))
+#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2, 0))
+#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5, 0))
+#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)
+
+#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
+#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
+#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
+#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
+#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
+#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
+#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
+#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
+
+#define DPI_CTL_EN BIT_ULL(0)
+#define DPI_DMA_CC_INT BIT_ULL(0)
+#define DPI_DMA_QRST BIT_ULL(0)
+
+#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
+#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
+#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
+#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
+#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
+#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
+#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
+#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
+
+#define DPI_REQQ_INT \
+ (DPI_REQQ_INT_INSTRFLT | \
+ DPI_REQQ_INT_RDFLT | \
+ DPI_REQQ_INT_WRFLT | \
+ DPI_REQQ_INT_CSFLT | \
+ DPI_REQQ_INT_INST_DBO | \
+ DPI_REQQ_INT_INST_ADDR_NULL | \
+ DPI_REQQ_INT_INST_FILL_INVAL | \
+ DPI_REQQ_INT_INSTR_PSN)
+
+#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
+#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
+#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
+
+#define DPI_PF_RAS_INT \
+ (DPI_PF_RAS_EBI_DAT_PSN | \
+ DPI_PF_RAS_NCB_DAT_PSN | \
+ DPI_PF_RAS_NCB_CMD_PSN)
+
+#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
+#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
+#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
+#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
+
+#define DPI_CTL 0x10010ULL
+#define DPI_DMA_CONTROL 0x10018ULL
+#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
+#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
+
+#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
+
+#define DPI_PF_RAS 0x10308ULL
+#define DPI_PF_RAS_ENA_W1C 0x10318ULL
+
+#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
+
+#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
+#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
+
+#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
+#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
+
+#define DPI_MBOX_VF_PF_INT 0x16300ULL
+#define DPI_MBOX_VF_PF_INT_W1S 0x16308ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
+
+#define DPI_WCTL_FIF_THR 0x17008ULL
+
+#define DPI_EBUS_MAX_PORTS 2
+
+#define DPI_EBUS_MRRS_MIN 128
+#define DPI_EBUS_MRRS_MAX 1024
+#define DPI_EBUS_MPS_MIN 128
+#define DPI_EBUS_MPS_MAX 1024
+#define DPI_WCTL_FIFO_THRESHOLD 0x30
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+#define DPI_QUEUE_OPEN_V2 0x5
+
+enum dpi_mbox_rsp_type {
+ DPI_MBOX_TYPE_CMD,
+ DPI_MBOX_TYPE_RSP_ACK,
+ DPI_MBOX_TYPE_RSP_NACK,
+};
+
+struct dpivf_config {
+ u16 csize;
+ u32 aura;
+ u16 sso_pf_func;
+ u16 npa_pf_func;
+};
+
+struct dpipf_vf {
+ u8 this_vfid;
+ bool setup_done;
+ struct dpivf_config vf_config;
+};
+
+/* DPI device mailbox */
+struct dpi_mbox {
+ struct work_struct work;
+ /* lock to serialize mbox requests */
+ struct mutex lock;
+ struct dpipf *pf;
+ u8 __iomem *pf_vf_data_reg;
+ u8 __iomem *vf_pf_data_reg;
+};
+
+struct dpipf {
+ struct miscdevice miscdev;
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ struct dpipf_vf vf[DPI_MAX_VFS];
+ /* Mailbox to talk to VFs */
+ struct dpi_mbox *mbox[DPI_MAX_VFS];
+};
+
+union dpi_mbox_message_t {
+ u64 u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ u64 vfid :8;
+ /* Command code */
+ u64 cmd :4;
+ /* Command buffer size in 8-byte words */
+ u64 csize :14;
+ /* Aura of the command buffer */
+ u64 aura :20;
+ /* SSO PF function */
+ u64 sso_pf_func :16;
+ /* NPA PF function */
+ u64 npa_pf_func :16;
+ /* Work queue completion status enable */
+ u64 wqecs :1;
+ /* Work queue completion status byte offset */
+ u64 wqecsoff :7;
+ /* Reserved */
+ u64 rsvd :42;
+ } s __packed;
+};
+
+static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
+{
+ writeq(val, dpi->reg_base + offset);
+}
+
+static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
+{
+ return readq(dpi->reg_base + offset);
+}
+
+static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
+{
+ u64 reg;
+
+ reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
+ reg &= ~DPI_DMA_CONTROL_WQECSDIS;
+ reg |= DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_WQECSMODE1;
+ reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+}
+
+static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
+ u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
+ u16 csize = dpivf->vf_config.csize;
+ u32 aura = dpivf->vf_config.aura;
+ unsigned long timeout;
+ u64 reg;
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Wait for a maximum of 3 sec */
+ timeout = jiffies + msecs_to_jiffies(3000);
+ while (!time_after(jiffies, timeout)) {
+ reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf));
+ if (!(reg & DPI_DMA_QRST))
+ break;
+
+ usleep_range(500, 1000);
+ }
+
+ if (reg & DPI_DMA_QRST) {
+ dev_err(&dpi->pdev->dev, "Queue reset failed\n");
+ return -EBUSY;
+ }
+
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+
+ reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
+ dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf));
+ reg |= DPI_DMA_IDS2_INST_AURA(aura);
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf));
+ reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
+ reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
+ reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
+ reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
+
+ return 0;
+}
+
+static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Reset IDS and IDS2 registers */
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+}
+
+static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
+{
+ u64 reg;
+ u32 vf;
+
+ reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
+ if (reg) {
+ for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) {
+ if (reg & BIT_ULL(vf))
+ schedule_work(&dpi->mbox[vf]->work);
+ }
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
+ }
+}
+
+static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
+{
+ struct dpipf *dpi = data;
+
+ dpi_poll_pfvf_mbox(dpi);
+
+ return IRQ_HANDLED;
+}
+
+static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
+{
+ int ret = 0;
+
+ switch (msg->s.cmd) {
+ case DPI_QUEUE_OPEN:
+ case DPI_QUEUE_OPEN_V2:
+ dpivf->vf_config.aura = msg->s.aura;
+ dpivf->vf_config.csize = msg->s.cmd == DPI_QUEUE_OPEN ? msg->s.csize / 8 :
+ msg->s.csize;
+ dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
+ ret = dpi_queue_init(dpi, dpivf, msg->s.vfid);
+ if (!ret) {
+ if (msg->s.wqecs)
+ dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
+ dpivf->setup_done = true;
+ }
+ break;
+ case DPI_QUEUE_CLOSE:
+ dpivf->vf_config.aura = 0;
+ dpivf->vf_config.csize = 0;
+ dpivf->vf_config.sso_pf_func = 0;
+ dpivf->vf_config.npa_pf_func = 0;
+ dpi_queue_fini(dpi, dpivf, msg->s.vfid);
+ dpivf->setup_done = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void dpi_pfvf_mbox_work(struct work_struct *work)
+{
+ struct dpi_mbox *mbox = container_of(work, struct dpi_mbox, work);
+ union dpi_mbox_message_t msg = { 0 };
+ struct dpipf_vf *dpivf;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = mbox->pf;
+
+ mutex_lock(&mbox->lock);
+ msg.u[0] = readq(mbox->vf_pf_data_reg);
+ if (unlikely(msg.u[0] == (u64)-1))
+ goto exit;
+
+ if (unlikely(msg.s.vfid >= pci_num_vf(dpi->pdev))) {
+ dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
+ goto exit;
+ }
+
+ dpivf = &dpi->vf[msg.s.vfid];
+ msg.u[1] = readq(mbox->pf_vf_data_reg);
+
+ ret = queue_config(dpi, dpivf, &msg);
+ if (ret < 0)
+ writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);
+ else
+ writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
+exit:
+ mutex_unlock(&mbox->lock);
+}
+
+/* Setup registers for a PF mailbox */
+static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf)
+{
+ struct dpi_mbox *mbox = dpi->mbox[vf];
+
+ mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf);
+ mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf);
+}
+
+static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
+{
+ int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev, sizeof(*dpi->mbox[vf]), GFP_KERNEL);
+
+ if (!dpi->mbox[vf])
+ return -ENOMEM;
+
+ mutex_init(&dpi->mbox[vf]->lock);
+ INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
+ dpi->mbox[vf]->pf = dpi;
+ dpi_setup_mbox_regs(dpi, vf);
+ }
+
+ return 0;
+}
+
+static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
+{
+ unsigned int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ if (work_pending(&dpi->mbox[vf]->work))
+ cancel_work_sync(&dpi->mbox[vf]->work);
+
+ dpi->mbox[vf] = NULL;
+ }
+}
+
+static void dpi_init(struct dpipf *dpi)
+{
+ unsigned int engine, port;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ if (engine == 4 || engine == 5)
+ reg = DPI_ENG_BUF_BLKS(16);
+ else
+ reg = DPI_ENG_BUF_BLKS(8);
+
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+ }
+
+ reg = DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
+ DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB;
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
+
+ mrrs_val = 2; /* 512B */
+ mps_val = 1; /* 256B */
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(7) | DPI_EBUS_PORTX_CFG_MPS(7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ dpi_reg_write(dpi, DPI_WCTL_FIF_THR, DPI_WCTL_FIFO_THRESHOLD);
+}
+
+static void dpi_fini(struct dpipf *dpi)
+{
+ unsigned int engine;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++)
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
+ dpi_reg_write(dpi, DPI_CTL, 0);
+}
+
+static void dpi_free_irq_vectors(void *pdev)
+{
+ pci_free_irq_vectors((struct pci_dev *)pdev);
+}
+
+static int dpi_irq_init(struct dpipf *dpi)
+{
+ struct pci_dev *pdev = dpi->pdev;
+ struct device *dev = &pdev->dev;
+ int i, ret;
+
+ /* Clear all RAS interrupts */
+ dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
+
+ /* Clear all RAS interrupt enable bits */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ ret = pci_alloc_irq_vectors(pdev, DPI_MAX_IRQS, DPI_MAX_IRQS, PCI_IRQ_MSIX);
+ if (ret != DPI_MAX_IRQS) {
+ dev_err(dev, "DPI: Failed to alloc %d msix irqs\n", DPI_MAX_IRQS);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(dev, dpi_free_irq_vectors, pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to add irq free action\n");
+ return ret;
+ }
+
+ ret = devm_request_irq(dev, pci_irq_vector(pdev, DPI_MBOX_PF_VF_INT_IDX),
+ dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
+ if (ret) {
+ dev_err(dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
+ return ret;
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));
+
+ return 0;
+}
+
+static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_mps_mrrs_cfg cfg;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_mps_mrrs_cfg)))
+ return -EFAULT;
+
+ if (cfg.max_read_req_sz < DPI_EBUS_MRRS_MIN || cfg.max_read_req_sz > DPI_EBUS_MRRS_MAX ||
+ !is_power_of_2(cfg.max_read_req_sz)) {
+ dev_err(&dpi->pdev->dev, "Invalid MRRS size:%u\n", cfg.max_read_req_sz);
+ return -EINVAL;
+ }
+
+ if (cfg.max_payload_sz < DPI_EBUS_MPS_MIN || cfg.max_payload_sz > DPI_EBUS_MPS_MAX ||
+ !is_power_of_2(cfg.max_payload_sz)) {
+ dev_err(&dpi->pdev->dev, "Invalid MPS size:%u\n", cfg.max_payload_sz);
+ return -EINVAL;
+ }
+
+ if (cfg.port >= DPI_EBUS_MAX_PORTS) {
+ dev_err(&dpi->pdev->dev, "Invalid EBUS port:%u\n", cfg.port);
+ return -EINVAL;
+ }
+
+ mrrs_val = fls(cfg.max_read_req_sz >> 8);
+ mps_val = fls(cfg.max_payload_sz >> 8);
+
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
+
+ return 0;
+}
+
+static int dpi_engine_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_engine_cfg cfg;
+ unsigned int engine;
+ u8 *eng_buf;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_engine_cfg)))
+ return -EFAULT;
+
+ eng_buf = (u8 *)&cfg.fifo_mask;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ reg = DPI_ENG_BUF_BLKS(eng_buf[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+
+ if (cfg.update_molr) {
+ reg = DPI_DMA_ENG_EN_MOLR(cfg.molr[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg);
+ }
+ }
+
+ return 0;
+}
+
+static long dpi_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data)
+{
+ void __user *arg = (void __user *)data;
+ struct dpipf *dpi;
+ int ret = -EINVAL;
+
+ dpi = container_of(fptr->private_data, struct dpipf, miscdev);
+
+ switch (cmd) {
+ case DPI_MPS_MRRS_CFG:
+ ret = dpi_mps_mrrs_config(dpi, arg);
+ break;
+ case DPI_ENGINE_CFG:
+ ret = dpi_engine_config(dpi, arg);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static const struct file_operations dpi_device_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = dpi_dev_ioctl,
+ .compat_ioctl = compat_ptr_ioctl,
+};
+
+static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi->pdev = pdev;
+
+ ret = pcim_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to enable PCI device\n");
+ return ret;
+ }
+
+ ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to request MMIO region\n");
+ return ret;
+ }
+
+ dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
+
+ /* Initialize global PF registers */
+ dpi_init(dpi);
+
+ /* Setup PF-VF mailbox */
+ ret = dpi_pfvf_mbox_setup(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
+ goto err_dpi_fini;
+ }
+
+ /* Register interrupts */
+ ret = dpi_irq_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize irq vectors\n");
+ goto err_dpi_mbox_free;
+ }
+
+ pci_set_drvdata(pdev, dpi);
+ dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dpi->miscdev.name = DPI_DRV_NAME;
+ dpi->miscdev.fops = &dpi_device_fops;
+ dpi->miscdev.parent = dev;
+
+ ret = misc_register(&dpi->miscdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to register misc device\n");
+ goto err_dpi_mbox_free;
+ }
+
+ return 0;
+
+err_dpi_mbox_free:
+ dpi_pfvf_mbox_destroy(dpi);
+err_dpi_fini:
+ dpi_fini(dpi);
+ return ret;
+}
+
+static void dpi_remove(struct pci_dev *pdev)
+{
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+
+ misc_deregister(&dpi->miscdev);
+ pci_sriov_configure_simple(pdev, 0);
+ dpi_pfvf_mbox_destroy(dpi);
+ dpi_fini(dpi);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id dpi_id_table[] = {
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_MRVL_CN10K_DPI_PF,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
+ { 0, } /* end of table */
+};
+
+static struct pci_driver dpi_driver = {
+ .name = DPI_DRV_NAME,
+ .id_table = dpi_id_table,
+ .probe = dpi_probe,
+ .remove = dpi_remove,
+ .sriov_configure = pci_sriov_configure_simple,
+};
+
+module_pci_driver(dpi_driver);
+MODULE_DEVICE_TABLE(pci, dpi_id_table);
+MODULE_AUTHOR("Marvell.");
+MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/misc/mrvl_cn10k_dpi.h b/include/uapi/misc/mrvl_cn10k_dpi.h
new file mode 100644
index 000000000000..a1951644448a
--- /dev/null
+++ b/include/uapi/misc/mrvl_cn10k_dpi.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/*
+ * Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#ifndef __MRVL_CN10K_DPI_H__
+#define __MRVL_CN10K_DPI_H__
+
+#include <linux/types.h>
+
+#define DPI_MAX_ENGINES 6
+
+struct dpi_mps_mrrs_cfg {
+ __u16 max_read_req_sz; /* Max read request size */
+ __u16 max_payload_sz; /* Max payload size */
+ __u8 port; /* Ebus port */
+};
+
+struct dpi_engine_cfg {
+ __u64 fifo_mask; /* FIFO size mask in KBytes */
+ __u16 molr[DPI_MAX_ENGINES]; /* Max outstanding load requests */
+ __u8 update_molr; /* '1' to update engine MOLR */
+};
+
+/* DPI ioctl numbers */
+#define DPI_MAGIC_NUM 0xB8
+
+/* Set MPS & MRRS parameters */
+#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 1, struct dpi_mps_mrrs_cfg)
+
+/* Set Engine FIFO configuration */
+#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 2, struct dpi_engine_cfg)
+
+#endif /* __MRVL_CN10K_DPI_H__ */
--
2.25.1
On Fri, Apr 26, 2024 at 11:20:11AM -0700, Vamsi Attunuru wrote:
> Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> function which initializes DPI DMA hardware's global configuration and
> enables hardware mailbox channels between physical function (PF) and
> it's virtual functions (VF). VF device drivers (User space drivers) use
> this hw mailbox to communicate any required device configuration on it's
> respective VF device. Accordingly, this DPI PF driver provisions the
> VF device resources.
>
> At the hardware level, the DPI physical function (PF) acts as a management
> interface to setup the VF device resources, VF devices are only provisioned
> to handle or control the actual DMA Engine's data transfer capabilities.
>
> Signed-off-by: Vamsi Attunuru <[email protected]>
> ---
> Changes V5 -> V6:
> - Updated documentation
The documentation for where to find the userspace code needs to be in
the documentation file, not buried in a comment here in a changelog
section that will never show up anywhere.
thanks,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Saturday, April 27, 2024 4:37 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; Jerin Jacob <[email protected]>; linux-
> [email protected]
> Subject: [EXTERNAL] Re: [PATCH v6 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K DPI administrative driver
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
> On Fri, Apr 26, 2024 at 11:20:11AM -0700, Vamsi Attunuru wrote:
> > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> > function which initializes DPI DMA hardware's global configuration and
> > enables hardware mailbox channels between physical function (PF) and
> > it's virtual functions (VF). VF device drivers (User space drivers)
> > use this hw mailbox to communicate any required device configuration
> > on it's respective VF device. Accordingly, this DPI PF driver
> > provisions the VF device resources.
> >
> > At the hardware level, the DPI physical function (PF) acts as a
> > management interface to setup the VF device resources, VF devices are
> > only provisioned to handle or control the actual DMA Engine's data transfer
> capabilities.
> >
> > Signed-off-by: Vamsi Attunuru <[email protected]>
> > ---
> > Changes V5 -> V6:
> > - Updated documentation
>
> The documentation for where to find the userspace code needs to be in the
> documentation file, not buried in a comment here in a changelog section that
> will never show up anywhere.
Sure, I will add the details in documentation file and resend. I assumed like you wanted the user space code references for the review purpose, so mentioned as separately.
Thanks
Vamsi
>
> thanks,
>
> greg k-h
Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
function which initializes DPI DMA hardware's global configuration and
enables hardware mailbox channels between physical function (PF) and
it's virtual functions (VF). VF device drivers (User space drivers) use
this hw mailbox to communicate any required device configuration on it's
respective VF device. Accordingly, this DPI PF driver provisions the
VF device resources.
At the hardware level, the DPI physical function (PF) acts as a management
interface to setup the VF device resources, VF devices are only provisioned
to handle or control the actual DMA Engine's data transfer capabilities.
Signed-off-by: Vamsi Attunuru <[email protected]>
---
Changes V5 -> V6:
- Updated documentation
- Fixed data types in uapi file
Changes V4 -> V5:
- Fixed license and data types in uapi file
Changes V3 -> V4:
- Moved ioctl definations to .h file
- Fixed structure alignements which are passed in ioctl
Changes V2 -> V3:
- Added ioctl operation to the fops
- Used managed version of kzalloc & request_irq
- Addressed miscellaneous comments
Changes V1 -> V2:
- Fixed return values and busy-wait loops
- Merged .h file into .c file
- Fixed directory structure
- Removed module params
- Registered the device as misc device
Documentation/misc-devices/index.rst | 1 +
Documentation/misc-devices/mrvl_cn10k_dpi.rst | 57 ++
.../userspace-api/ioctl/ioctl-number.rst | 1 +
MAINTAINERS | 5 +
drivers/misc/Kconfig | 13 +
drivers/misc/Makefile | 2 +
drivers/misc/mrvl_cn10k_dpi.c | 685 ++++++++++++++++++
include/uapi/misc/mrvl_cn10k_dpi.h | 37 +
8 files changed, 801 insertions(+)
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index 2d0ce9138588..10f2e0f74e45 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -20,6 +20,7 @@ fit into other categories.
ics932s401
isl29003
lis3lv02d
+ mrvl_cn10k_dpi
max6875
oxsemi-tornado
pci-endpoint-test
diff --git a/Documentation/misc-devices/mrvl_cn10k_dpi.rst b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
new file mode 100644
index 000000000000..cce202f114b7
--- /dev/null
+++ b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
@@ -0,0 +1,57 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===============================================
+Marvell CN10K DMA packet interface (DPI) driver
+===============================================
+
+Overview
+========
+
+DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
+DPI hardware comprises a physical function (PF), its virtual functions,
+mailbox logic, and a set of DMA engines & DMA command queues.
+
+DPI PF function is an administrative function which services the mailbox
+requests from its VF functions and provisions DMA engine resources to
+it's VF functions.
+
+mrvl_cn10k_dpi.ko misc driver loads on DPI PF device and services the
+mailbox commands submitted by the VF devices and accordingly initializes
+the DMA engines and VF device's DMA command queues. Also, driver creates
+/dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
+attributes like fifo length, molr, mps & mrrs.
+
+DPI PF driver is just an administrative driver to setup its VF device's
+queues and provisions the hardware resources, it can not initiate any
+DMA operations. Only VF devices are provisioned with DMA capabilities.
+
+Driver location
+===============
+
+drivers/misc/mrvl_cn10k_dpi.c
+
+Driver IOCTLs
+=============
+
+:c:macro::`DPI_MPS_MRRS_CFG`
+ioctl that sets max payload size & max read request size parameters of
+a pem port to which DMA engines are wired.
+
+
+:c:macro::`DPI_ENGINE_CFG`
+ioctl that sets DMA engine's fifo sizes & max outstanding load request
+thresholds.
+
+Userspace code example
+----------------------
+
+DPI VF devices are managed by user space drivers, below is a reference
+code to the user space driver's mailbox command exchange with DPI PF
+driver through hardware mailbox.
+
+https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/driver/roc_dpi.c
+
+Below is a sample application that uses driver IOCTLs to setup DMA engine
+and PEM port attributes over `/dev/mrvl-cn10k-dpi` node.
+
+https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/application/main.c
diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst
index 457e16f06e04..e6fd0c386b59 100644
--- a/Documentation/userspace-api/ioctl/ioctl-number.rst
+++ b/Documentation/userspace-api/ioctl/ioctl-number.rst
@@ -358,6 +358,7 @@ Code Seq# Include File Comments
0xB6 all linux/fpga-dfl.h
0xB7 all uapi/linux/remoteproc_cdev.h <mailto:[email protected]>
0xB7 all uapi/linux/nsfs.h <mailto:Andrei Vagin <[email protected]>>
+0xB8 01-02 uapi/misc/mrvl_cn10k_dpi.h Marvell CN10K DPI driver
0xC0 00-0F linux/usb/iowarrior.h
0xCA 00-0F uapi/misc/cxl.h
0xCA 10-2F uapi/misc/ocxl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 960512bec428..ab77232d583e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13104,6 +13104,11 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
+MARVELL OCTEON CN10K DPI DRIVER
+M: Vamsi Attunuru <[email protected]>
+S: Maintained
+F: drivers/misc/mrvl_cn10k_dpi.c
+
MATROX FRAMEBUFFER DRIVER
L: [email protected]
S: Orphan
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4fb291f0bf7c..78470ef2538f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -574,6 +574,19 @@ config NSM
To compile this driver as a module, choose M here.
The module will be called nsm.
+config MARVELL_CN10K_DPI
+ tristate "Octeon CN10K DPI driver"
+ depends on ARM64 && PCI
+ help
+ Enables Octeon CN10K DMA packet interface (DPI) driver which intializes
+ DPI hardware's physical function (PF) device's global configuration and
+ its virtual function's (VFs) resource configuration to enable DMA transfers.
+ DPI PF device does not have any data movement functionality, it only serves
+ VF's resource configuration requests.
+
+ To compile this driver as a module, choose M here: the module
+ will be called mrvl_cn10k_dpi.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ea6ea5bbbc9c..5106bf96ea5c 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -68,3 +68,5 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
obj-$(CONFIG_NSM) += nsm.o
+obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
+obj-y += mrvl_cn10k_dpi.o
diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
new file mode 100644
index 000000000000..bd99583994f9
--- /dev/null
+++ b/drivers/misc/mrvl_cn10k_dpi.c
@@ -0,0 +1,685 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <uapi/misc/mrvl_cn10k_dpi.h>
+
+#define DPI_DRV_NAME "mrvl-cn10k-dpi"
+
+/* PCI device IDs */
+#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
+#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xB900
+
+/* PCI BAR nos */
+#define PCI_DPI_CFG_BAR 0
+
+/* MSI-X interrupts */
+#define DPI_MAX_REQQ_INT 32
+#define DPI_MAX_CC_INT 64
+
+/* MBOX MSI-X interrupt vector index */
+#define DPI_MBOX_PF_VF_INT_IDX 0x75
+
+#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
+
+#define DPI_MAX_VFS 32
+
+#define DPI_ENGINE_MASK GENMASK(2, 0)
+
+#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) (((x) & GENMASK_ULL(15, 0)) << 16)
+#define DPI_DMA_IDS_INST_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 40)
+#define DPI_DMA_IDS_DMA_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 32)
+#define DPI_DMA_ENG_EN_MOLR(x) (((x) & GENMASK_ULL(9, 0)) << 32)
+#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & GENMASK(2, 0)) << 4)
+#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) & GENMASK(15, 0))
+#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19, 0))
+#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13, 0))
+#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2, 0))
+#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5, 0))
+#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)
+
+#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
+#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
+#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
+#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
+#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
+#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
+#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
+#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
+
+#define DPI_CTL_EN BIT_ULL(0)
+#define DPI_DMA_CC_INT BIT_ULL(0)
+#define DPI_DMA_QRST BIT_ULL(0)
+
+#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
+#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
+#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
+#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
+#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
+#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
+#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
+#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
+
+#define DPI_REQQ_INT \
+ (DPI_REQQ_INT_INSTRFLT | \
+ DPI_REQQ_INT_RDFLT | \
+ DPI_REQQ_INT_WRFLT | \
+ DPI_REQQ_INT_CSFLT | \
+ DPI_REQQ_INT_INST_DBO | \
+ DPI_REQQ_INT_INST_ADDR_NULL | \
+ DPI_REQQ_INT_INST_FILL_INVAL | \
+ DPI_REQQ_INT_INSTR_PSN)
+
+#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
+#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
+#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
+
+#define DPI_PF_RAS_INT \
+ (DPI_PF_RAS_EBI_DAT_PSN | \
+ DPI_PF_RAS_NCB_DAT_PSN | \
+ DPI_PF_RAS_NCB_CMD_PSN)
+
+#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
+#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
+#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
+#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
+
+#define DPI_CTL 0x10010ULL
+#define DPI_DMA_CONTROL 0x10018ULL
+#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
+#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
+
+#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
+
+#define DPI_PF_RAS 0x10308ULL
+#define DPI_PF_RAS_ENA_W1C 0x10318ULL
+
+#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
+
+#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
+#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
+
+#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
+#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
+
+#define DPI_MBOX_VF_PF_INT 0x16300ULL
+#define DPI_MBOX_VF_PF_INT_W1S 0x16308ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
+
+#define DPI_WCTL_FIF_THR 0x17008ULL
+
+#define DPI_EBUS_MAX_PORTS 2
+
+#define DPI_EBUS_MRRS_MIN 128
+#define DPI_EBUS_MRRS_MAX 1024
+#define DPI_EBUS_MPS_MIN 128
+#define DPI_EBUS_MPS_MAX 1024
+#define DPI_WCTL_FIFO_THRESHOLD 0x30
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+#define DPI_QUEUE_OPEN_V2 0x5
+
+enum dpi_mbox_rsp_type {
+ DPI_MBOX_TYPE_CMD,
+ DPI_MBOX_TYPE_RSP_ACK,
+ DPI_MBOX_TYPE_RSP_NACK,
+};
+
+struct dpivf_config {
+ u16 csize;
+ u32 aura;
+ u16 sso_pf_func;
+ u16 npa_pf_func;
+};
+
+struct dpipf_vf {
+ u8 this_vfid;
+ bool setup_done;
+ struct dpivf_config vf_config;
+};
+
+/* DPI device mailbox */
+struct dpi_mbox {
+ struct work_struct work;
+ /* lock to serialize mbox requests */
+ struct mutex lock;
+ struct dpipf *pf;
+ u8 __iomem *pf_vf_data_reg;
+ u8 __iomem *vf_pf_data_reg;
+};
+
+struct dpipf {
+ struct miscdevice miscdev;
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ struct dpipf_vf vf[DPI_MAX_VFS];
+ /* Mailbox to talk to VFs */
+ struct dpi_mbox *mbox[DPI_MAX_VFS];
+};
+
+union dpi_mbox_message_t {
+ u64 u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ u64 vfid :8;
+ /* Command code */
+ u64 cmd :4;
+ /* Command buffer size in 8-byte words */
+ u64 csize :14;
+ /* Aura of the command buffer */
+ u64 aura :20;
+ /* SSO PF function */
+ u64 sso_pf_func :16;
+ /* NPA PF function */
+ u64 npa_pf_func :16;
+ /* Work queue completion status enable */
+ u64 wqecs :1;
+ /* Work queue completion status byte offset */
+ u64 wqecsoff :7;
+ /* Reserved */
+ u64 rsvd :42;
+ } s __packed;
+};
+
+static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
+{
+ writeq(val, dpi->reg_base + offset);
+}
+
+static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
+{
+ return readq(dpi->reg_base + offset);
+}
+
+static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
+{
+ u64 reg;
+
+ reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
+ reg &= ~DPI_DMA_CONTROL_WQECSDIS;
+ reg |= DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_WQECSMODE1;
+ reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+}
+
+static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
+ u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
+ u16 csize = dpivf->vf_config.csize;
+ u32 aura = dpivf->vf_config.aura;
+ unsigned long timeout;
+ u64 reg;
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Wait for a maximum of 3 sec */
+ timeout = jiffies + msecs_to_jiffies(3000);
+ while (!time_after(jiffies, timeout)) {
+ reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf));
+ if (!(reg & DPI_DMA_QRST))
+ break;
+
+ usleep_range(500, 1000);
+ }
+
+ if (reg & DPI_DMA_QRST) {
+ dev_err(&dpi->pdev->dev, "Queue reset failed\n");
+ return -EBUSY;
+ }
+
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+
+ reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
+ dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf));
+ reg |= DPI_DMA_IDS2_INST_AURA(aura);
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf));
+ reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
+ reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
+ reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
+ reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
+
+ return 0;
+}
+
+static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Reset IDS and IDS2 registers */
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+}
+
+static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
+{
+ u64 reg;
+ u32 vf;
+
+ reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
+ if (reg) {
+ for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) {
+ if (reg & BIT_ULL(vf))
+ schedule_work(&dpi->mbox[vf]->work);
+ }
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
+ }
+}
+
+static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
+{
+ struct dpipf *dpi = data;
+
+ dpi_poll_pfvf_mbox(dpi);
+
+ return IRQ_HANDLED;
+}
+
+static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
+{
+ int ret = 0;
+
+ switch (msg->s.cmd) {
+ case DPI_QUEUE_OPEN:
+ case DPI_QUEUE_OPEN_V2:
+ dpivf->vf_config.aura = msg->s.aura;
+ dpivf->vf_config.csize = msg->s.cmd == DPI_QUEUE_OPEN ? msg->s.csize / 8 :
+ msg->s.csize;
+ dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
+ ret = dpi_queue_init(dpi, dpivf, msg->s.vfid);
+ if (!ret) {
+ if (msg->s.wqecs)
+ dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
+ dpivf->setup_done = true;
+ }
+ break;
+ case DPI_QUEUE_CLOSE:
+ dpivf->vf_config.aura = 0;
+ dpivf->vf_config.csize = 0;
+ dpivf->vf_config.sso_pf_func = 0;
+ dpivf->vf_config.npa_pf_func = 0;
+ dpi_queue_fini(dpi, dpivf, msg->s.vfid);
+ dpivf->setup_done = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void dpi_pfvf_mbox_work(struct work_struct *work)
+{
+ struct dpi_mbox *mbox = container_of(work, struct dpi_mbox, work);
+ union dpi_mbox_message_t msg = { 0 };
+ struct dpipf_vf *dpivf;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = mbox->pf;
+
+ mutex_lock(&mbox->lock);
+ msg.u[0] = readq(mbox->vf_pf_data_reg);
+ if (unlikely(msg.u[0] == (u64)-1))
+ goto exit;
+
+ if (unlikely(msg.s.vfid >= pci_num_vf(dpi->pdev))) {
+ dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
+ goto exit;
+ }
+
+ dpivf = &dpi->vf[msg.s.vfid];
+ msg.u[1] = readq(mbox->pf_vf_data_reg);
+
+ ret = queue_config(dpi, dpivf, &msg);
+ if (ret < 0)
+ writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);
+ else
+ writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
+exit:
+ mutex_unlock(&mbox->lock);
+}
+
+/* Setup registers for a PF mailbox */
+static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf)
+{
+ struct dpi_mbox *mbox = dpi->mbox[vf];
+
+ mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf);
+ mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf);
+}
+
+static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
+{
+ int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev, sizeof(*dpi->mbox[vf]), GFP_KERNEL);
+
+ if (!dpi->mbox[vf])
+ return -ENOMEM;
+
+ mutex_init(&dpi->mbox[vf]->lock);
+ INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
+ dpi->mbox[vf]->pf = dpi;
+ dpi_setup_mbox_regs(dpi, vf);
+ }
+
+ return 0;
+}
+
+static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
+{
+ unsigned int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ if (work_pending(&dpi->mbox[vf]->work))
+ cancel_work_sync(&dpi->mbox[vf]->work);
+
+ dpi->mbox[vf] = NULL;
+ }
+}
+
+static void dpi_init(struct dpipf *dpi)
+{
+ unsigned int engine, port;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ if (engine == 4 || engine == 5)
+ reg = DPI_ENG_BUF_BLKS(16);
+ else
+ reg = DPI_ENG_BUF_BLKS(8);
+
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+ }
+
+ reg = DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
+ DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB;
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
+
+ mrrs_val = 2; /* 512B */
+ mps_val = 1; /* 256B */
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(7) | DPI_EBUS_PORTX_CFG_MPS(7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ dpi_reg_write(dpi, DPI_WCTL_FIF_THR, DPI_WCTL_FIFO_THRESHOLD);
+}
+
+static void dpi_fini(struct dpipf *dpi)
+{
+ unsigned int engine;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++)
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
+ dpi_reg_write(dpi, DPI_CTL, 0);
+}
+
+static void dpi_free_irq_vectors(void *pdev)
+{
+ pci_free_irq_vectors((struct pci_dev *)pdev);
+}
+
+static int dpi_irq_init(struct dpipf *dpi)
+{
+ struct pci_dev *pdev = dpi->pdev;
+ struct device *dev = &pdev->dev;
+ int i, ret;
+
+ /* Clear all RAS interrupts */
+ dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
+
+ /* Clear all RAS interrupt enable bits */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ ret = pci_alloc_irq_vectors(pdev, DPI_MAX_IRQS, DPI_MAX_IRQS, PCI_IRQ_MSIX);
+ if (ret != DPI_MAX_IRQS) {
+ dev_err(dev, "DPI: Failed to alloc %d msix irqs\n", DPI_MAX_IRQS);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(dev, dpi_free_irq_vectors, pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to add irq free action\n");
+ return ret;
+ }
+
+ ret = devm_request_irq(dev, pci_irq_vector(pdev, DPI_MBOX_PF_VF_INT_IDX),
+ dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
+ if (ret) {
+ dev_err(dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
+ return ret;
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));
+
+ return 0;
+}
+
+static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_mps_mrrs_cfg cfg;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_mps_mrrs_cfg)))
+ return -EFAULT;
+
+ if (cfg.max_read_req_sz < DPI_EBUS_MRRS_MIN || cfg.max_read_req_sz > DPI_EBUS_MRRS_MAX ||
+ !is_power_of_2(cfg.max_read_req_sz)) {
+ dev_err(&dpi->pdev->dev, "Invalid MRRS size:%u\n", cfg.max_read_req_sz);
+ return -EINVAL;
+ }
+
+ if (cfg.max_payload_sz < DPI_EBUS_MPS_MIN || cfg.max_payload_sz > DPI_EBUS_MPS_MAX ||
+ !is_power_of_2(cfg.max_payload_sz)) {
+ dev_err(&dpi->pdev->dev, "Invalid MPS size:%u\n", cfg.max_payload_sz);
+ return -EINVAL;
+ }
+
+ if (cfg.port >= DPI_EBUS_MAX_PORTS) {
+ dev_err(&dpi->pdev->dev, "Invalid EBUS port:%u\n", cfg.port);
+ return -EINVAL;
+ }
+
+ mrrs_val = fls(cfg.max_read_req_sz >> 8);
+ mps_val = fls(cfg.max_payload_sz >> 8);
+
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
+
+ return 0;
+}
+
+static int dpi_engine_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_engine_cfg cfg;
+ unsigned int engine;
+ u8 *eng_buf;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_engine_cfg)))
+ return -EFAULT;
+
+ eng_buf = (u8 *)&cfg.fifo_mask;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ reg = DPI_ENG_BUF_BLKS(eng_buf[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+
+ if (cfg.update_molr) {
+ reg = DPI_DMA_ENG_EN_MOLR(cfg.molr[engine & DPI_ENGINE_MASK]);
+ dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg);
+ }
+ }
+
+ return 0;
+}
+
+static long dpi_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data)
+{
+ void __user *arg = (void __user *)data;
+ struct dpipf *dpi;
+ int ret = -EINVAL;
+
+ dpi = container_of(fptr->private_data, struct dpipf, miscdev);
+
+ switch (cmd) {
+ case DPI_MPS_MRRS_CFG:
+ ret = dpi_mps_mrrs_config(dpi, arg);
+ break;
+ case DPI_ENGINE_CFG:
+ ret = dpi_engine_config(dpi, arg);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static const struct file_operations dpi_device_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = dpi_dev_ioctl,
+ .compat_ioctl = compat_ptr_ioctl,
+};
+
+static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi->pdev = pdev;
+
+ ret = pcim_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to enable PCI device\n");
+ return ret;
+ }
+
+ ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to request MMIO region\n");
+ return ret;
+ }
+
+ dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
+
+ /* Initialize global PF registers */
+ dpi_init(dpi);
+
+ /* Setup PF-VF mailbox */
+ ret = dpi_pfvf_mbox_setup(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
+ goto err_dpi_fini;
+ }
+
+ /* Register interrupts */
+ ret = dpi_irq_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize irq vectors\n");
+ goto err_dpi_mbox_free;
+ }
+
+ pci_set_drvdata(pdev, dpi);
+ dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dpi->miscdev.name = DPI_DRV_NAME;
+ dpi->miscdev.fops = &dpi_device_fops;
+ dpi->miscdev.parent = dev;
+
+ ret = misc_register(&dpi->miscdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to register misc device\n");
+ goto err_dpi_mbox_free;
+ }
+
+ return 0;
+
+err_dpi_mbox_free:
+ dpi_pfvf_mbox_destroy(dpi);
+err_dpi_fini:
+ dpi_fini(dpi);
+ return ret;
+}
+
+static void dpi_remove(struct pci_dev *pdev)
+{
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+
+ misc_deregister(&dpi->miscdev);
+ pci_sriov_configure_simple(pdev, 0);
+ dpi_pfvf_mbox_destroy(dpi);
+ dpi_fini(dpi);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id dpi_id_table[] = {
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_MRVL_CN10K_DPI_PF,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
+ { 0, } /* end of table */
+};
+
+static struct pci_driver dpi_driver = {
+ .name = DPI_DRV_NAME,
+ .id_table = dpi_id_table,
+ .probe = dpi_probe,
+ .remove = dpi_remove,
+ .sriov_configure = pci_sriov_configure_simple,
+};
+
+module_pci_driver(dpi_driver);
+MODULE_DEVICE_TABLE(pci, dpi_id_table);
+MODULE_AUTHOR("Marvell.");
+MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/misc/mrvl_cn10k_dpi.h b/include/uapi/misc/mrvl_cn10k_dpi.h
new file mode 100644
index 000000000000..a1951644448a
--- /dev/null
+++ b/include/uapi/misc/mrvl_cn10k_dpi.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/*
+ * Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#ifndef __MRVL_CN10K_DPI_H__
+#define __MRVL_CN10K_DPI_H__
+
+#include <linux/types.h>
+
+#define DPI_MAX_ENGINES 6
+
+struct dpi_mps_mrrs_cfg {
+ __u16 max_read_req_sz; /* Max read request size */
+ __u16 max_payload_sz; /* Max payload size */
+ __u8 port; /* Ebus port */
+};
+
+struct dpi_engine_cfg {
+ __u64 fifo_mask; /* FIFO size mask in KBytes */
+ __u16 molr[DPI_MAX_ENGINES]; /* Max outstanding load requests */
+ __u8 update_molr; /* '1' to update engine MOLR */
+};
+
+/* DPI ioctl numbers */
+#define DPI_MAGIC_NUM 0xB8
+
+/* Set MPS & MRRS parameters */
+#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 1, struct dpi_mps_mrrs_cfg)
+
+/* Set Engine FIFO configuration */
+#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 2, struct dpi_engine_cfg)
+
+#endif /* __MRVL_CN10K_DPI_H__ */
--
2.25.1
On Sun, Apr 28, 2024 at 10:50:27PM -0700, Vamsi Attunuru wrote:
> Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> function which initializes DPI DMA hardware's global configuration and
> enables hardware mailbox channels between physical function (PF) and
> it's virtual functions (VF). VF device drivers (User space drivers) use
> this hw mailbox to communicate any required device configuration on it's
> respective VF device. Accordingly, this DPI PF driver provisions the
> VF device resources.
>
> At the hardware level, the DPI physical function (PF) acts as a management
> interface to setup the VF device resources, VF devices are only provisioned
> to handle or control the actual DMA Engine's data transfer capabilities.
>
> Signed-off-by: Vamsi Attunuru <[email protected]>
No one else at Marvell has reviewed this before you submitted this?
> ---
> Changes V5 -> V6:
> - Updated documentation
> - Fixed data types in uapi file
>
> Changes V4 -> V5:
> - Fixed license and data types in uapi file
>
> Changes V3 -> V4:
> - Moved ioctl definations to .h file
> - Fixed structure alignements which are passed in ioctl
>
> Changes V2 -> V3:
> - Added ioctl operation to the fops
> - Used managed version of kzalloc & request_irq
> - Addressed miscellaneous comments
>
> Changes V1 -> V2:
> - Fixed return values and busy-wait loops
> - Merged .h file into .c file
> - Fixed directory structure
> - Removed module params
> - Registered the device as misc device
>
> Documentation/misc-devices/index.rst | 1 +
> Documentation/misc-devices/mrvl_cn10k_dpi.rst | 57 ++
> .../userspace-api/ioctl/ioctl-number.rst | 1 +
> MAINTAINERS | 5 +
> drivers/misc/Kconfig | 13 +
> drivers/misc/Makefile | 2 +
> drivers/misc/mrvl_cn10k_dpi.c | 685 ++++++++++++++++++
> include/uapi/misc/mrvl_cn10k_dpi.h | 37 +
> 8 files changed, 801 insertions(+)
>
> diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
> index 2d0ce9138588..10f2e0f74e45 100644
> --- a/Documentation/misc-devices/index.rst
> +++ b/Documentation/misc-devices/index.rst
> @@ -20,6 +20,7 @@ fit into other categories.
> ics932s401
> isl29003
> lis3lv02d
> + mrvl_cn10k_dpi
> max6875
> oxsemi-tornado
> pci-endpoint-test
Why not in sorted order?
> diff --git a/Documentation/misc-devices/mrvl_cn10k_dpi.rst b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
> new file mode 100644
> index 000000000000..cce202f114b7
> --- /dev/null
> +++ b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
> @@ -0,0 +1,57 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +===============================================
> +Marvell CN10K DMA packet interface (DPI) driver
> +===============================================
> +
> +Overview
> +========
> +
> +DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
> +DPI hardware comprises a physical function (PF), its virtual functions,
> +mailbox logic, and a set of DMA engines & DMA command queues.
> +
> +DPI PF function is an administrative function which services the mailbox
> +requests from its VF functions and provisions DMA engine resources to
> +it's VF functions.
> +
> +mrvl_cn10k_dpi.ko misc driver loads on DPI PF device and services the
> +mailbox commands submitted by the VF devices and accordingly initializes
> +the DMA engines and VF device's DMA command queues. Also, driver creates
> +/dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
> +attributes like fifo length, molr, mps & mrrs.
> +
> +DPI PF driver is just an administrative driver to setup its VF device's
> +queues and provisions the hardware resources, it can not initiate any
> +DMA operations. Only VF devices are provisioned with DMA capabilities.
> +
> +Driver location
> +===============
> +
> +drivers/misc/mrvl_cn10k_dpi.c
> +
> +Driver IOCTLs
> +=============
> +
> +:c:macro::`DPI_MPS_MRRS_CFG`
> +ioctl that sets max payload size & max read request size parameters of
> +a pem port to which DMA engines are wired.
> +
> +
> +:c:macro::`DPI_ENGINE_CFG`
> +ioctl that sets DMA engine's fifo sizes & max outstanding load request
> +thresholds.
> +
> +Userspace code example
> +----------------------
> +
> +DPI VF devices are managed by user space drivers, below is a reference
> +code to the user space driver's mailbox command exchange with DPI PF
> +driver through hardware mailbox.
> +
> +https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/driver/roc_dpi.c
> +
> +Below is a sample application that uses driver IOCTLs to setup DMA engine
> +and PEM port attributes over `/dev/mrvl-cn10k-dpi` node.
> +
> +https://github.com/VamsiKrishnaA99/dpi-dma/blob/main/application/main.c
I appreciate the code being open, but this is on a personal account that
was created for only this one package, and it doesn't even have a
README. Yet it is fully owned/copyrighted by Marvell and the code has
been around since 2021? Why isn't this on a Marvell-controlled page to
show that this really is supported and is the proper interface to use
this driver that it provides to their customers?
> diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst
> index 457e16f06e04..e6fd0c386b59 100644
> --- a/Documentation/userspace-api/ioctl/ioctl-number.rst
> +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst
> @@ -358,6 +358,7 @@ Code Seq# Include File Comments
> 0xB6 all linux/fpga-dfl.h
> 0xB7 all uapi/linux/remoteproc_cdev.h <mailto:[email protected]>
> 0xB7 all uapi/linux/nsfs.h <mailto:Andrei Vagin <[email protected]>>
> +0xB8 01-02 uapi/misc/mrvl_cn10k_dpi.h Marvell CN10K DPI driver
> 0xC0 00-0F linux/usb/iowarrior.h
> 0xCA 00-0F uapi/misc/cxl.h
> 0xCA 10-2F uapi/misc/ocxl.h
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 960512bec428..ab77232d583e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -13104,6 +13104,11 @@ S: Supported
> F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
> F: drivers/mmc/host/sdhci-xenon*
>
> +MARVELL OCTEON CN10K DPI DRIVER
> +M: Vamsi Attunuru <[email protected]>
> +S: Maintained
So this is not part of your job to support this code? Why isn't Marvell
allowing that to happen?
> +F: drivers/misc/mrvl_cn10k_dpi.c
> +
> MATROX FRAMEBUFFER DRIVER
> L: [email protected]
> S: Orphan
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 4fb291f0bf7c..78470ef2538f 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -574,6 +574,19 @@ config NSM
> To compile this driver as a module, choose M here.
> The module will be called nsm.
>
> +config MARVELL_CN10K_DPI
> + tristate "Octeon CN10K DPI driver"
> + depends on ARM64 && PCI
> + help
> + Enables Octeon CN10K DMA packet interface (DPI) driver which intializes
> + DPI hardware's physical function (PF) device's global configuration and
> + its virtual function's (VFs) resource configuration to enable DMA transfers.
> + DPI PF device does not have any data movement functionality, it only serves
> + VF's resource configuration requests.
Nit, please wrap at 72 columns, didn't checkpatch.pl complain about
this?
> +
> + To compile this driver as a module, choose M here: the module
> + will be called mrvl_cn10k_dpi.
> +
> source "drivers/misc/c2port/Kconfig"
> source "drivers/misc/eeprom/Kconfig"
> source "drivers/misc/cb710/Kconfig"
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index ea6ea5bbbc9c..5106bf96ea5c 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -68,3 +68,5 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
> obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
> obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
> obj-$(CONFIG_NSM) += nsm.o
> +obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
> +obj-y += mrvl_cn10k_dpi.o
That is odd, why are you saying obj-y here? You want everyone to always
build this code into the kernel image no matter what
> diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
> new file mode 100644
> index 000000000000..bd99583994f9
> --- /dev/null
> +++ b/drivers/misc/mrvl_cn10k_dpi.c
> @@ -0,0 +1,685 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Marvell Octeon CN10K DPI driver
> + *
> + * Copyright (C) 2024 Marvell.
> + *
> + */
> +
> +#include <linux/compat.h>
> +#include <linux/delay.h>
> +#include <linux/miscdevice.h>
> +#include <linux/module.h>
> +#include <linux/pci.h>
> +#include <linux/irq.h>
> +#include <linux/interrupt.h>
> +
> +#include <uapi/misc/mrvl_cn10k_dpi.h>
> +
> +#define DPI_DRV_NAME "mrvl-cn10k-dpi"
KBUILD_MODNAME please.
> +
> +/* PCI device IDs */
> +#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
> +#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xB900
> +
> +/* PCI BAR nos */
What is "nos"?
> +#define PCI_DPI_CFG_BAR 0
> +
> +/* MSI-X interrupts */
> +#define DPI_MAX_REQQ_INT 32
> +#define DPI_MAX_CC_INT 64
> +
> +/* MBOX MSI-X interrupt vector index */
> +#define DPI_MBOX_PF_VF_INT_IDX 0x75
> +
> +#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
> +
> +#define DPI_MAX_VFS 32
> +
> +#define DPI_ENGINE_MASK GENMASK(2, 0)
> +
> +#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) (((x) & GENMASK_ULL(15, 0)) << 16)
> +#define DPI_DMA_IDS_INST_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 40)
> +#define DPI_DMA_IDS_DMA_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 32)
> +#define DPI_DMA_ENG_EN_MOLR(x) (((x) & GENMASK_ULL(9, 0)) << 32)
> +#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & GENMASK(2, 0)) << 4)
> +#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) & GENMASK(15, 0))
> +#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19, 0))
> +#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13, 0))
> +#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2, 0))
> +#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5, 0))
> +#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)
> +
> +#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
> +#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
> +#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
> +#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
> +#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
> +#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
> +#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
> +#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
> +
> +#define DPI_CTL_EN BIT_ULL(0)
> +#define DPI_DMA_CC_INT BIT_ULL(0)
> +#define DPI_DMA_QRST BIT_ULL(0)
> +
> +#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
> +#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
> +#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
> +#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
> +#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
> +#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
> +#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
> +#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
> +
> +#define DPI_REQQ_INT \
> + (DPI_REQQ_INT_INSTRFLT | \
> + DPI_REQQ_INT_RDFLT | \
> + DPI_REQQ_INT_WRFLT | \
> + DPI_REQQ_INT_CSFLT | \
> + DPI_REQQ_INT_INST_DBO | \
> + DPI_REQQ_INT_INST_ADDR_NULL | \
> + DPI_REQQ_INT_INST_FILL_INVAL | \
> + DPI_REQQ_INT_INSTR_PSN)
> +
> +#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
> +#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
> +#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
> +
> +#define DPI_PF_RAS_INT \
> + (DPI_PF_RAS_EBI_DAT_PSN | \
> + DPI_PF_RAS_NCB_DAT_PSN | \
> + DPI_PF_RAS_NCB_CMD_PSN)
> +
> +#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
> +#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
> +#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
> +#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
> +
> +#define DPI_CTL 0x10010ULL
> +#define DPI_DMA_CONTROL 0x10018ULL
> +#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
> +#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
> +
> +#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
> +
> +#define DPI_PF_RAS 0x10308ULL
> +#define DPI_PF_RAS_ENA_W1C 0x10318ULL
> +
> +#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
> +#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
> +
> +#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
> +#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
> +
> +#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
> +#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
> +
> +#define DPI_MBOX_VF_PF_INT 0x16300ULL
> +#define DPI_MBOX_VF_PF_INT_W1S 0x16308ULL
> +#define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
> +#define DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
> +
> +#define DPI_WCTL_FIF_THR 0x17008ULL
> +
> +#define DPI_EBUS_MAX_PORTS 2
> +
> +#define DPI_EBUS_MRRS_MIN 128
> +#define DPI_EBUS_MRRS_MAX 1024
> +#define DPI_EBUS_MPS_MIN 128
> +#define DPI_EBUS_MPS_MAX 1024
> +#define DPI_WCTL_FIFO_THRESHOLD 0x30
> +
> +#define DPI_QUEUE_OPEN 0x1
> +#define DPI_QUEUE_CLOSE 0x2
> +#define DPI_REG_DUMP 0x3
> +#define DPI_GET_REG_CFG 0x4
> +#define DPI_QUEUE_OPEN_V2 0x5
> +
> +enum dpi_mbox_rsp_type {
> + DPI_MBOX_TYPE_CMD,
> + DPI_MBOX_TYPE_RSP_ACK,
> + DPI_MBOX_TYPE_RSP_NACK,
> +};
> +
> +struct dpivf_config {
> + u16 csize;
> + u32 aura;
> + u16 sso_pf_func;
> + u16 npa_pf_func;
Do you intend to have unaligned accesses to the fields in this
structure?
> +};
> +
> +struct dpipf_vf {
> + u8 this_vfid;
> + bool setup_done;
> + struct dpivf_config vf_config;
> +};
> +
> +/* DPI device mailbox */
> +struct dpi_mbox {
> + struct work_struct work;
> + /* lock to serialize mbox requests */
> + struct mutex lock;
> + struct dpipf *pf;
> + u8 __iomem *pf_vf_data_reg;
> + u8 __iomem *vf_pf_data_reg;
> +};
> +
> +struct dpipf {
> + struct miscdevice miscdev;
> + void __iomem *reg_base;
> + struct pci_dev *pdev;
> + struct dpipf_vf vf[DPI_MAX_VFS];
> + /* Mailbox to talk to VFs */
> + struct dpi_mbox *mbox[DPI_MAX_VFS];
> +};
> +
> +union dpi_mbox_message_t {
Didn't checkpatch complain about the "_t" here?
> + u64 u[2];
What is "u"?
> + struct dpi_mbox_message_s {
> + /* VF ID to configure */
> + u64 vfid :8;
> + /* Command code */
> + u64 cmd :4;
> + /* Command buffer size in 8-byte words */
> + u64 csize :14;
> + /* Aura of the command buffer */
> + u64 aura :20;
> + /* SSO PF function */
> + u64 sso_pf_func :16;
> + /* NPA PF function */
> + u64 npa_pf_func :16;
> + /* Work queue completion status enable */
> + u64 wqecs :1;
> + /* Work queue completion status byte offset */
> + u64 wqecsoff :7;
> + /* Reserved */
> + u64 rsvd :42;
reserved for what?
If you are reading this from hardware, the bit fields you created here
will NOT work or be portable at all. Please do this properly.
Also you have a mix of tabs and spaces for some reason in this
structure, again, checkpatch should have caught that.
> + } s __packed;
"s"?
What is "u" and "s" here?
> +};
> +
> +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
> +{
> + writeq(val, dpi->reg_base + offset);
No need to read to ensure that the write succeeded? Or are you doing
that in individual places where you want to make sure it happened? If
so, I didn't see that in the use of this.
> +}
> +
> +static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
> +{
> + return readq(dpi->reg_base + offset);
> +}
> +
> +static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
> +{
> + u64 reg;
> +
> + reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
> + reg &= ~DPI_DMA_CONTROL_WQECSDIS;
> + reg |= DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_WQECSMODE1;
> + reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
> + dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
> +}
> +
> +static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
> +{
> + u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
> + u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
> + u16 csize = dpivf->vf_config.csize;
> + u32 aura = dpivf->vf_config.aura;
> + unsigned long timeout;
> + u64 reg;
> +
> + dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
> +
> + /* Wait for a maximum of 3 sec */
> + timeout = jiffies + msecs_to_jiffies(3000);
> + while (!time_after(jiffies, timeout)) {
> + reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf));
> + if (!(reg & DPI_DMA_QRST))
> + break;
> +
> + usleep_range(500, 1000);
Why sleep this value? Please document.
> + }
> +
> + if (reg & DPI_DMA_QRST) {
> + dev_err(&dpi->pdev->dev, "Queue reset failed\n");
> + return -EBUSY;
> + }
> +
> + dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
> + dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
> +
> + reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
> + dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
> +
> + reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf));
> + reg |= DPI_DMA_IDS2_INST_AURA(aura);
> + dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
> +
> + reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf));
> + reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
> + reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
> + reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
> + reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
> + dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
> +
> + return 0;
> +}
> +
> +static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
> +{
> + dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
> +
> + /* Reset IDS and IDS2 registers */
> + dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
> + dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
> +}
> +
> +static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
> +{
> + u64 reg;
> + u32 vf;
> +
> + reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
> + if (reg) {
> + for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) {
> + if (reg & BIT_ULL(vf))
> + schedule_work(&dpi->mbox[vf]->work);
> + }
> + dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
> + }
No error if reg was not read properly?
> +}
> +
> +static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
> +{
> + struct dpipf *dpi = data;
> +
> + dpi_poll_pfvf_mbox(dpi);
> +
> + return IRQ_HANDLED;
So this can always succeed?
> +}
> +
> +static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message_t *msg)
> +{
> + int ret = 0;
> +
> + switch (msg->s.cmd) {
> + case DPI_QUEUE_OPEN:
> + case DPI_QUEUE_OPEN_V2:
> + dpivf->vf_config.aura = msg->s.aura;
> + dpivf->vf_config.csize = msg->s.cmd == DPI_QUEUE_OPEN ? msg->s.csize / 8 :
> + msg->s.csize;
> + dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
> + dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
> + ret = dpi_queue_init(dpi, dpivf, msg->s.vfid);
> + if (!ret) {
> + if (msg->s.wqecs)
> + dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
> + dpivf->setup_done = true;
> + }
> + break;
> + case DPI_QUEUE_CLOSE:
> + dpivf->vf_config.aura = 0;
> + dpivf->vf_config.csize = 0;
> + dpivf->vf_config.sso_pf_func = 0;
> + dpivf->vf_config.npa_pf_func = 0;
> + dpi_queue_fini(dpi, dpivf, msg->s.vfid);
> + dpivf->setup_done = false;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +static void dpi_pfvf_mbox_work(struct work_struct *work)
> +{
> + struct dpi_mbox *mbox = container_of(work, struct dpi_mbox, work);
> + union dpi_mbox_message_t msg = { 0 };
Are you sure this can be on the stack?
> + struct dpipf_vf *dpivf;
> + struct dpipf *dpi;
> + int ret;
> +
> + dpi = mbox->pf;
> +
> + mutex_lock(&mbox->lock);
> + msg.u[0] = readq(mbox->vf_pf_data_reg);
> + if (unlikely(msg.u[0] == (u64)-1))
> + goto exit;
Only use likely/unlikely if you can prove with a benchmark that it makes
a difference. Otherwise let the CPU and compiler choose for you, as it
knows better than you do (and will know better over time.)
If you want to use unlikely, you have to document it as to how it
matters.
> +
> + if (unlikely(msg.s.vfid >= pci_num_vf(dpi->pdev))) {
> + dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
You send this to the kernel log if a device is broken?
> + goto exit;
> + }
> +
> + dpivf = &dpi->vf[msg.s.vfid];
> + msg.u[1] = readq(mbox->pf_vf_data_reg);
> +
> + ret = queue_config(dpi, dpivf, &msg);
> + if (ret < 0)
> + writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);
> + else
> + writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
> +exit:
> + mutex_unlock(&mbox->lock);
> +}
> +
> +/* Setup registers for a PF mailbox */
> +static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf)
> +{
> + struct dpi_mbox *mbox = dpi->mbox[vf];
> +
> + mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf);
> + mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf);
> +}
> +
> +static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
> +{
> + int vf;
> +
> + for (vf = 0; vf < DPI_MAX_VFS; vf++) {
> + dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev, sizeof(*dpi->mbox[vf]), GFP_KERNEL);
> +
> + if (!dpi->mbox[vf])
> + return -ENOMEM;
> +
> + mutex_init(&dpi->mbox[vf]->lock);
> + INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
> + dpi->mbox[vf]->pf = dpi;
> + dpi_setup_mbox_regs(dpi, vf);
> + }
> +
> + return 0;
> +}
> +
> +static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
> +{
> + unsigned int vf;
> +
> + for (vf = 0; vf < DPI_MAX_VFS; vf++) {
> + if (work_pending(&dpi->mbox[vf]->work))
> + cancel_work_sync(&dpi->mbox[vf]->work);
> +
> + dpi->mbox[vf] = NULL;
> + }
> +}
> +
> +static void dpi_init(struct dpipf *dpi)
> +{
> + unsigned int engine, port;
> + u8 mrrs_val, mps_val;
> + u64 reg;
> +
> + for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
> + if (engine == 4 || engine == 5)
> + reg = DPI_ENG_BUF_BLKS(16);
> + else
> + reg = DPI_ENG_BUF_BLKS(8);
> +
> + dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
> + }
> +
> + reg = DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
> + DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB;
> +
> + dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
> + dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
> +
> + mrrs_val = 2; /* 512B */
> + mps_val = 1; /* 256B */
> +
> + for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
> + reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
> + reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(7) | DPI_EBUS_PORTX_CFG_MPS(7));
> + reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
> + dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
> + }
> +
> + dpi_reg_write(dpi, DPI_WCTL_FIF_THR, DPI_WCTL_FIFO_THRESHOLD);
> +}
> +
> +static void dpi_fini(struct dpipf *dpi)
> +{
> + unsigned int engine;
> +
> + for (engine = 0; engine < DPI_MAX_ENGINES; engine++)
> + dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
> +
> + dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
> + dpi_reg_write(dpi, DPI_CTL, 0);
> +}
> +
> +static void dpi_free_irq_vectors(void *pdev)
> +{
> + pci_free_irq_vectors((struct pci_dev *)pdev);
> +}
> +
> +static int dpi_irq_init(struct dpipf *dpi)
> +{
> + struct pci_dev *pdev = dpi->pdev;
> + struct device *dev = &pdev->dev;
> + int i, ret;
> +
> + /* Clear all RAS interrupts */
> + dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
> +
> + /* Clear all RAS interrupt enable bits */
> + dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
> +
> + for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
> + dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
> + dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
> + }
> +
> + for (i = 0; i < DPI_MAX_CC_INT; i++) {
> + dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
> + dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
> + }
> +
> + ret = pci_alloc_irq_vectors(pdev, DPI_MAX_IRQS, DPI_MAX_IRQS, PCI_IRQ_MSIX);
> + if (ret != DPI_MAX_IRQS) {
> + dev_err(dev, "DPI: Failed to alloc %d msix irqs\n", DPI_MAX_IRQS);
> + return ret;
> + }
> +
> + ret = devm_add_action_or_reset(dev, dpi_free_irq_vectors, pdev);
> + if (ret) {
> + dev_err(dev, "DPI: Failed to add irq free action\n");
> + return ret;
> + }
> +
> + ret = devm_request_irq(dev, pci_irq_vector(pdev, DPI_MBOX_PF_VF_INT_IDX),
> + dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
> + if (ret) {
> + dev_err(dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
> + return ret;
> + }
> +
> + dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));
> +
> + return 0;
> +}
> +
> +static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg)
> +{
> + struct dpi_mps_mrrs_cfg cfg;
> + u8 mrrs_val, mps_val;
> + u64 reg;
> +
> + if (copy_from_user(&cfg, arg, sizeof(struct dpi_mps_mrrs_cfg)))
> + return -EFAULT;
> +
> + if (cfg.max_read_req_sz < DPI_EBUS_MRRS_MIN || cfg.max_read_req_sz > DPI_EBUS_MRRS_MAX ||
> + !is_power_of_2(cfg.max_read_req_sz)) {
> + dev_err(&dpi->pdev->dev, "Invalid MRRS size:%u\n", cfg.max_read_req_sz);
You are allowing userspace to spam the kernel log with messages by
sending the driver invalid data. THat is a denial of service, please
never do that.
> + return -EINVAL;
> + }
> +
> + if (cfg.max_payload_sz < DPI_EBUS_MPS_MIN || cfg.max_payload_sz > DPI_EBUS_MPS_MAX ||
> + !is_power_of_2(cfg.max_payload_sz)) {
> + dev_err(&dpi->pdev->dev, "Invalid MPS size:%u\n", cfg.max_payload_sz);
> + return -EINVAL;
> + }
> +
> + if (cfg.port >= DPI_EBUS_MAX_PORTS) {
> + dev_err(&dpi->pdev->dev, "Invalid EBUS port:%u\n", cfg.port);
> + return -EINVAL;
> + }
> +
> + mrrs_val = fls(cfg.max_read_req_sz >> 8);
> + mps_val = fls(cfg.max_payload_sz >> 8);
> +
> + reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port));
> + reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
> + reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
> + dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
> +
> + return 0;
> +}
> +
> +static int dpi_engine_config(struct dpipf *dpi, void __user *arg)
> +{
> + struct dpi_engine_cfg cfg;
> + unsigned int engine;
> + u8 *eng_buf;
> + u64 reg;
> +
> + if (copy_from_user(&cfg, arg, sizeof(struct dpi_engine_cfg)))
> + return -EFAULT;
No need to ever validate any information in that structure from
userspace? You always blindly copy it on to the device? Userspace can
never get this wrong?
> +
> + eng_buf = (u8 *)&cfg.fifo_mask;
> +
> + for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
> + reg = DPI_ENG_BUF_BLKS(eng_buf[engine & DPI_ENGINE_MASK]);
> + dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
> +
> + if (cfg.update_molr) {
> + reg = DPI_DMA_ENG_EN_MOLR(cfg.molr[engine & DPI_ENGINE_MASK]);
> + dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static long dpi_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data)
> +{
> + void __user *arg = (void __user *)data;
> + struct dpipf *dpi;
> + int ret = -EINVAL;
Wrong error code for an invalid ioctl command :(
> +
> + dpi = container_of(fptr->private_data, struct dpipf, miscdev);
> +
> + switch (cmd) {
> + case DPI_MPS_MRRS_CFG:
> + ret = dpi_mps_mrrs_config(dpi, arg);
> + break;
> + case DPI_ENGINE_CFG:
> + ret = dpi_engine_config(dpi, arg);
> + break;
> + default:
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static const struct file_operations dpi_device_fops = {
> + .owner = THIS_MODULE,
> + .unlocked_ioctl = dpi_dev_ioctl,
> + .compat_ioctl = compat_ptr_ioctl,
> +};
> +
> +static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> +{
> + struct device *dev = &pdev->dev;
> + struct dpipf *dpi;
> + int ret;
> +
> + dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
> + if (!dpi)
> + return -ENOMEM;
> +
> + dpi->pdev = pdev;
> +
> + ret = pcim_enable_device(pdev);
> + if (ret) {
> + dev_err(dev, "DPI: Failed to enable PCI device\n");
> + return ret;
> + }
> +
> + ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
> + if (ret) {
> + dev_err(dev, "DPI: Failed to request MMIO region\n");
> + return ret;
> + }
> +
> + dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
> +
> + /* Initialize global PF registers */
> + dpi_init(dpi);
> +
> + /* Setup PF-VF mailbox */
> + ret = dpi_pfvf_mbox_setup(dpi);
> + if (ret) {
> + dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
> + goto err_dpi_fini;
> + }
> +
> + /* Register interrupts */
> + ret = dpi_irq_init(dpi);
> + if (ret) {
> + dev_err(dev, "DPI: Failed to initialize irq vectors\n");
> + goto err_dpi_mbox_free;
> + }
> +
> + pci_set_drvdata(pdev, dpi);
> + dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
> + dpi->miscdev.name = DPI_DRV_NAME;
> + dpi->miscdev.fops = &dpi_device_fops;
> + dpi->miscdev.parent = dev;
> +
> + ret = misc_register(&dpi->miscdev);
> + if (ret) {
> + dev_err(dev, "DPI: Failed to register misc device\n");
> + goto err_dpi_mbox_free;
> + }
> +
> + return 0;
> +
> +err_dpi_mbox_free:
> + dpi_pfvf_mbox_destroy(dpi);
> +err_dpi_fini:
> + dpi_fini(dpi);
> + return ret;
> +}
> +
> +static void dpi_remove(struct pci_dev *pdev)
> +{
> + struct dpipf *dpi = pci_get_drvdata(pdev);
> +
> + misc_deregister(&dpi->miscdev);
> + pci_sriov_configure_simple(pdev, 0);
> + dpi_pfvf_mbox_destroy(dpi);
> + dpi_fini(dpi);
> + pci_set_drvdata(pdev, NULL);
> +}
> +
> +static const struct pci_device_id dpi_id_table[] = {
> + { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_MRVL_CN10K_DPI_PF,
> + PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
> + { 0, } /* end of table */
> +};
> +
> +static struct pci_driver dpi_driver = {
> + .name = DPI_DRV_NAME,
> + .id_table = dpi_id_table,
> + .probe = dpi_probe,
> + .remove = dpi_remove,
> + .sriov_configure = pci_sriov_configure_simple,
> +};
> +
> +module_pci_driver(dpi_driver);
> +MODULE_DEVICE_TABLE(pci, dpi_id_table);
> +MODULE_AUTHOR("Marvell.");
> +MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
> +MODULE_LICENSE("GPL");
> diff --git a/include/uapi/misc/mrvl_cn10k_dpi.h b/include/uapi/misc/mrvl_cn10k_dpi.h
> new file mode 100644
> index 000000000000..a1951644448a
> --- /dev/null
> +++ b/include/uapi/misc/mrvl_cn10k_dpi.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
Why is this file "GPL-2.0+" but your driver is "GPL-2.0"? Is that what
your lawyers want to have happen (sorry, I have to ask.)
thanks,
greg k-h
Hi Vamsi,
kernel test robot noticed the following build errors:
[auto build test ERROR on char-misc/char-misc-testing]
[also build test ERROR on char-misc/char-misc-next char-misc/char-misc-linus soc/for-next linus/master v6.9-rc6 next-20240430]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Vamsi-Attunuru/misc-mrvl-cn10k-dpi-add-Octeon-CN10K-DPI-administrative-driver/20240430-142354
base: char-misc/char-misc-testing
patch link: https://lore.kernel.org/r/20240429055027.2162310-1-vattunuru%40marvell.com
patch subject: [PATCH v6 1/1] misc: mrvl-cn10k-dpi: add Octeon CN10K DPI administrative driver
config: arc-allnoconfig (https://download.01.org/0day-ci/archive/20240430/[email protected]/config)
compiler: arc-elf-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240430/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All error/warnings (new ones prefixed by >>):
drivers/misc/mrvl_cn10k_dpi.c: In function 'dpi_reg_write':
>> drivers/misc/mrvl_cn10k_dpi.c:202:9: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Werror=implicit-function-declaration]
202 | writeq(val, dpi->reg_base + offset);
| ^~~~~~
| writeb
drivers/misc/mrvl_cn10k_dpi.c: In function 'dpi_reg_read':
>> drivers/misc/mrvl_cn10k_dpi.c:207:16: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration]
207 | return readq(dpi->reg_base + offset);
| ^~~~~
| readb
drivers/misc/mrvl_cn10k_dpi.c: In function 'dpi_free_irq_vectors':
>> drivers/misc/mrvl_cn10k_dpi.c:453:9: error: implicit declaration of function 'pci_free_irq_vectors'; did you mean 'dpi_free_irq_vectors'? [-Werror=implicit-function-declaration]
453 | pci_free_irq_vectors((struct pci_dev *)pdev);
| ^~~~~~~~~~~~~~~~~~~~
| dpi_free_irq_vectors
In file included from include/uapi/linux/posix_types.h:5,
from include/uapi/linux/types.h:14,
from include/linux/types.h:6,
from include/linux/compat.h:9,
from drivers/misc/mrvl_cn10k_dpi.c:8:
drivers/misc/mrvl_cn10k_dpi.c: In function 'dpi_remove':
include/linux/stddef.h:8:14: error: called object is not a function or function pointer
8 | #define NULL ((void *)0)
| ^
include/linux/pci.h:2445:41: note: in expansion of macro 'NULL'
2445 | #define pci_sriov_configure_simple NULL
| ^~~~
drivers/misc/mrvl_cn10k_dpi.c:661:9: note: in expansion of macro 'pci_sriov_configure_simple'
661 | pci_sriov_configure_simple(pdev, 0);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/misc/mrvl_cn10k_dpi.c: At top level:
>> drivers/misc/mrvl_cn10k_dpi.c:681:1: warning: data definition has no type or storage class
681 | module_pci_driver(dpi_driver);
| ^~~~~~~~~~~~~~~~~
>> drivers/misc/mrvl_cn10k_dpi.c:681:1: error: type defaults to 'int' in declaration of 'module_pci_driver' [-Werror=implicit-int]
>> drivers/misc/mrvl_cn10k_dpi.c:681:1: warning: parameter names (without types) in function declaration
>> drivers/misc/mrvl_cn10k_dpi.c:673:26: warning: 'dpi_driver' defined but not used [-Wunused-variable]
673 | static struct pci_driver dpi_driver = {
| ^~~~~~~~~~
cc1: some warnings being treated as errors
vim +202 drivers/misc/mrvl_cn10k_dpi.c
199
200 static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
201 {
> 202 writeq(val, dpi->reg_base + offset);
203 }
204
205 static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
206 {
> 207 return readq(dpi->reg_base + offset);
208 }
209
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Vamsi,
kernel test robot noticed the following build errors:
[auto build test ERROR on char-misc/char-misc-testing]
[also build test ERROR on char-misc/char-misc-next char-misc/char-misc-linus soc/for-next linus/master v6.9-rc6 next-20240430]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Vamsi-Attunuru/misc-mrvl-cn10k-dpi-add-Octeon-CN10K-DPI-administrative-driver/20240430-142354
base: char-misc/char-misc-testing
patch link: https://lore.kernel.org/r/20240429055027.2162310-1-vattunuru%40marvell.com
patch subject: [PATCH v6 1/1] misc: mrvl-cn10k-dpi: add Octeon CN10K DPI administrative driver
config: um-allmodconfig (https://download.01.org/0day-ci/archive/20240430/[email protected]/config)
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project 37ae4ad0eef338776c7e2cffb3896153d43dcd90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240430/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
In file included from drivers/misc/mrvl_cn10k_dpi.c:12:
In file included from include/linux/pci.h:38:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:11:
In file included from arch/um/include/asm/hardirq.h:5:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/um/include/asm/io.h:24:
include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
547 | val = __raw_readb(PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
560 | val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
| ~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu'
37 | #define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
| ^
In file included from drivers/misc/mrvl_cn10k_dpi.c:12:
In file included from include/linux/pci.h:38:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:11:
In file included from arch/um/include/asm/hardirq.h:5:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/um/include/asm/io.h:24:
include/asm-generic/io.h:573:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
573 | val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
| ~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu'
35 | #define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
| ^
In file included from drivers/misc/mrvl_cn10k_dpi.c:12:
In file included from include/linux/pci.h:38:
In file included from include/linux/interrupt.h:11:
In file included from include/linux/hardirq.h:11:
In file included from arch/um/include/asm/hardirq.h:5:
In file included from include/asm-generic/hardirq.h:17:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:13:
In file included from arch/um/include/asm/io.h:24:
include/asm-generic/io.h:584:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
584 | __raw_writeb(value, PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:594:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
594 | __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:604:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
604 | __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:692:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
692 | readsb(PCI_IOBASE + addr, buffer, count);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:700:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
700 | readsw(PCI_IOBASE + addr, buffer, count);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:708:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
708 | readsl(PCI_IOBASE + addr, buffer, count);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:717:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
717 | writesb(PCI_IOBASE + addr, buffer, count);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:726:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
726 | writesw(PCI_IOBASE + addr, buffer, count);
| ~~~~~~~~~~ ^
include/asm-generic/io.h:735:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
735 | writesl(PCI_IOBASE + addr, buffer, count);
| ~~~~~~~~~~ ^
In file included from drivers/misc/mrvl_cn10k_dpi.c:12:
In file included from include/linux/pci.h:2693:
In file included from include/linux/dma-mapping.h:11:
In file included from include/linux/scatterlist.h:8:
In file included from include/linux/mm.h:2208:
include/linux/vmstat.h:522:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
522 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
| ~~~~~~~~~~~ ^ ~~~
>> drivers/misc/mrvl_cn10k_dpi.c:453:2: error: call to undeclared function 'pci_free_irq_vectors'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
453 | pci_free_irq_vectors((struct pci_dev *)pdev);
| ^
drivers/misc/mrvl_cn10k_dpi.c:453:2: note: did you mean 'dpi_free_irq_vectors'?
drivers/misc/mrvl_cn10k_dpi.c:451:13: note: 'dpi_free_irq_vectors' declared here
451 | static void dpi_free_irq_vectors(void *pdev)
| ^
452 | {
453 | pci_free_irq_vectors((struct pci_dev *)pdev);
| ~~~~~~~~~~~~~~~~~~~~
| dpi_free_irq_vectors
>> drivers/misc/mrvl_cn10k_dpi.c:661:28: error: called object type 'void *' is not a function or function pointer
661 | pci_sriov_configure_simple(pdev, 0);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^
>> drivers/misc/mrvl_cn10k_dpi.c:681:1: error: type specifier missing, defaults to 'int'; ISO C99 and later do not support implicit int [-Wimplicit-int]
681 | module_pci_driver(dpi_driver);
| ^
| int
>> drivers/misc/mrvl_cn10k_dpi.c:681:19: error: a parameter list without types is only allowed in a function definition
681 | module_pci_driver(dpi_driver);
| ^
13 warnings and 4 errors generated.
vim +/pci_free_irq_vectors +453 drivers/misc/mrvl_cn10k_dpi.c
450
451 static void dpi_free_irq_vectors(void *pdev)
452 {
> 453 pci_free_irq_vectors((struct pci_dev *)pdev);
454 }
455
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Vamsi,
kernel test robot noticed the following build warnings:
[auto build test WARNING on char-misc/char-misc-testing]
[also build test WARNING on char-misc/char-misc-next char-misc/char-misc-linus soc/for-next linus/master v6.9-rc6 next-20240430]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Vamsi-Attunuru/misc-mrvl-cn10k-dpi-add-Octeon-CN10K-DPI-administrative-driver/20240430-142354
base: char-misc/char-misc-testing
patch link: https://lore.kernel.org/r/20240429055027.2162310-1-vattunuru%40marvell.com
patch subject: [PATCH v6 1/1] misc: mrvl-cn10k-dpi: add Octeon CN10K DPI administrative driver
config: m68k-m5208evb_defconfig (https://download.01.org/0day-ci/archive/20240430/[email protected]/config)
compiler: m68k-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240430/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
>> drivers/misc/mrvl_cn10k_dpi.c:197:9: warning: 'packed' attribute ignored for field of type 'struct dpi_mbox_message_s' [-Wattributes]
197 | } s __packed;
| ^
drivers/misc/mrvl_cn10k_dpi.c: In function 'dpi_reg_write':
drivers/misc/mrvl_cn10k_dpi.c:202:9: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Werror=implicit-function-declaration]
202 | writeq(val, dpi->reg_base + offset);
| ^~~~~~
| writeb
drivers/misc/mrvl_cn10k_dpi.c: In function 'dpi_reg_read':
drivers/misc/mrvl_cn10k_dpi.c:207:16: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration]
207 | return readq(dpi->reg_base + offset);
| ^~~~~
| readb
drivers/misc/mrvl_cn10k_dpi.c: In function 'dpi_free_irq_vectors':
drivers/misc/mrvl_cn10k_dpi.c:453:9: error: implicit declaration of function 'pci_free_irq_vectors'; did you mean 'dpi_free_irq_vectors'? [-Werror=implicit-function-declaration]
453 | pci_free_irq_vectors((struct pci_dev *)pdev);
| ^~~~~~~~~~~~~~~~~~~~
| dpi_free_irq_vectors
In file included from include/uapi/linux/posix_types.h:5,
from include/uapi/linux/types.h:14,
from include/linux/types.h:6,
from include/linux/compat.h:9,
from drivers/misc/mrvl_cn10k_dpi.c:8:
drivers/misc/mrvl_cn10k_dpi.c: In function 'dpi_remove':
include/linux/stddef.h:8:14: error: called object is not a function or function pointer
8 | #define NULL ((void *)0)
| ^
include/linux/pci.h:2445:41: note: in expansion of macro 'NULL'
2445 | #define pci_sriov_configure_simple NULL
| ^~~~
drivers/misc/mrvl_cn10k_dpi.c:661:9: note: in expansion of macro 'pci_sriov_configure_simple'
661 | pci_sriov_configure_simple(pdev, 0);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/misc/mrvl_cn10k_dpi.c: At top level:
drivers/misc/mrvl_cn10k_dpi.c:681:1: warning: data definition has no type or storage class
681 | module_pci_driver(dpi_driver);
| ^~~~~~~~~~~~~~~~~
drivers/misc/mrvl_cn10k_dpi.c:681:1: error: type defaults to 'int' in declaration of 'module_pci_driver' [-Werror=implicit-int]
drivers/misc/mrvl_cn10k_dpi.c:681:1: warning: parameter names (without types) in function declaration
drivers/misc/mrvl_cn10k_dpi.c:673:26: warning: 'dpi_driver' defined but not used [-Wunused-variable]
673 | static struct pci_driver dpi_driver = {
| ^~~~~~~~~~
cc1: some warnings being treated as errors
vim +197 drivers/misc/mrvl_cn10k_dpi.c
175
176 union dpi_mbox_message_t {
177 u64 u[2];
178 struct dpi_mbox_message_s {
179 /* VF ID to configure */
180 u64 vfid :8;
181 /* Command code */
182 u64 cmd :4;
183 /* Command buffer size in 8-byte words */
184 u64 csize :14;
185 /* Aura of the command buffer */
186 u64 aura :20;
187 /* SSO PF function */
188 u64 sso_pf_func :16;
189 /* NPA PF function */
190 u64 npa_pf_func :16;
191 /* Work queue completion status enable */
192 u64 wqecs :1;
193 /* Work queue completion status byte offset */
194 u64 wqecsoff :7;
195 /* Reserved */
196 u64 rsvd :42;
> 197 } s __packed;
198 };
199
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Monday, April 29, 2024 2:44 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: [email protected]; Jerin Jacob <[email protected]>; linux-
> [email protected]
> Subject: [EXTERNAL] Re: [PATCH v6 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K DPI administrative driver
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
> On Sun, Apr 28, 2024 at 10:50:27PM -0700, Vamsi Attunuru wrote:
> > Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
> > function which initializes DPI DMA hardware's global configuration and
> > enables hardware mailbox channels between physical function (PF) and
> > it's virtual functions (VF). VF device drivers (User space drivers)
> > use this hw mailbox to communicate any required device configuration
> > on it's respective VF device. Accordingly, this DPI PF driver
> > provisions the VF device resources.
> >
> > At the hardware level, the DPI physical function (PF) acts as a
> > management interface to setup the VF device resources, VF devices are
> > only provisioned to handle or control the actual DMA Engine's data transfer
> capabilities.
> >
> > Signed-off-by: Vamsi Attunuru <[email protected]>
>
> No one else at Marvell has reviewed this before you submitted this?
It was reviewed until V3, sorry for the inconvenience. I will get the next version
thoroughly reviewed and will send with reviewed-by sign off.
>
> > ---
> > Changes V5 -> V6:
> > - Updated documentation
> > - Fixed data types in uapi file
> >
> > Changes V4 -> V5:
> > - Fixed license and data types in uapi file
> >
> > Changes V3 -> V4:
> > - Moved ioctl definations to .h file
> > - Fixed structure alignements which are passed in ioctl
> >
> > Changes V2 -> V3:
> > - Added ioctl operation to the fops
> > - Used managed version of kzalloc & request_irq
> > - Addressed miscellaneous comments
> >
> > Changes V1 -> V2:
> > - Fixed return values and busy-wait loops
> > - Merged .h file into .c file
> > - Fixed directory structure
> > - Removed module params
> > - Registered the device as misc device
> >
> > Documentation/misc-devices/index.rst | 1 +
> > Documentation/misc-devices/mrvl_cn10k_dpi.rst | 57 ++
> > .../userspace-api/ioctl/ioctl-number.rst | 1 +
> > MAINTAINERS | 5 +
> > drivers/misc/Kconfig | 13 +
> > drivers/misc/Makefile | 2 +
> > drivers/misc/mrvl_cn10k_dpi.c | 685 ++++++++++++++++++
> > include/uapi/misc/mrvl_cn10k_dpi.h | 37 +
> > 8 files changed, 801 insertions(+)
> >
> > diff --git a/Documentation/misc-devices/index.rst
> > b/Documentation/misc-devices/index.rst
> > index 2d0ce9138588..10f2e0f74e45 100644
> > --- a/Documentation/misc-devices/index.rst
> > +++ b/Documentation/misc-devices/index.rst
> > @@ -20,6 +20,7 @@ fit into other categories.
> > ics932s401
> > isl29003
> > lis3lv02d
> > + mrvl_cn10k_dpi
> > max6875
> > oxsemi-tornado
> > pci-endpoint-test
>
> Why not in sorted order?
Ack, will fix it.
>
> > diff --git a/Documentation/misc-devices/mrvl_cn10k_dpi.rst
> > b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
> > new file mode 100644
> > index 000000000000..cce202f114b7
> > --- /dev/null
> > +++ b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
> > @@ -0,0 +1,57 @@
> > +.. SPDX-License-Identifier: GPL-2.0
> > +
> > +===============================================
> > +Marvell CN10K DMA packet interface (DPI) driver
> > +===============================================
> > +
> > +Overview
> > +========
> > +
> > +DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
> > +DPI hardware comprises a physical function (PF), its virtual
> > +functions, mailbox logic, and a set of DMA engines & DMA command
> queues.
> > +
> > +DPI PF function is an administrative function which services the
> > +mailbox requests from its VF functions and provisions DMA engine
> > +resources to it's VF functions.
> > +
> > +mrvl_cn10k_dpi.ko misc driver loads on DPI PF device and services the
> > +mailbox commands submitted by the VF devices and accordingly
> > +initializes the DMA engines and VF device's DMA command queues. Also,
> > +driver creates /dev/mrvl-cn10k-dpi node to set DMA engine and PEM
> > +(PCIe interface) port attributes like fifo length, molr, mps & mrrs.
> > +
> > +DPI PF driver is just an administrative driver to setup its VF
> > +device's queues and provisions the hardware resources, it can not
> > +initiate any DMA operations. Only VF devices are provisioned with DMA
> capabilities.
> > +
> > +Driver location
> > +===============
> > +
> > +drivers/misc/mrvl_cn10k_dpi.c
> > +
> > +Driver IOCTLs
> > +=============
> > +
> > +:c:macro::`DPI_MPS_MRRS_CFG`
> > +ioctl that sets max payload size & max read request size parameters
> > +of a pem port to which DMA engines are wired.
> > +
> > +
> > +:c:macro::`DPI_ENGINE_CFG`
> > +ioctl that sets DMA engine's fifo sizes & max outstanding load
> > +request thresholds.
> > +
> > +Userspace code example
> > +----------------------
> > +
> > +DPI VF devices are managed by user space drivers, below is a
> > +reference code to the user space driver's mailbox command exchange
> > +with DPI PF driver through hardware mailbox.
> > +
> > +https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__github.com_Vamsi
> > +KrishnaA99_dpi-2Ddma_blob_main_driver_roc-
> 5Fdpi.c&d=DwIBAg&c=nKjWec2b
> >
> +6R0mOyPaz7xtfQ&r=WllrYaumVkxaWjgKto6E_rtDQshhIhik2jkvzFyRhW8&m
> =7PlVgM
> > +7n0EhJ17QxPm3mXq6PT0CQzsOn2YFnRB8RMsIQdFAsZ5UKdTFmkcChUrf-
> &s=8wLYfXsc
> > +lLz7Fuvz9FfyEehC5xTSiIa88PJzturPF4U&e=
> > +
> > +Below is a sample application that uses driver IOCTLs to setup DMA
> > +engine and PEM port attributes over `/dev/mrvl-cn10k-dpi` node.
> > +
> > +https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__github.com_Vamsi
> > +KrishnaA99_dpi-
> 2Ddma_blob_main_application_main.c&d=DwIBAg&c=nKjWec2b
> >
> +6R0mOyPaz7xtfQ&r=WllrYaumVkxaWjgKto6E_rtDQshhIhik2jkvzFyRhW8&m
> =7PlVgM
> > +7n0EhJ17QxPm3mXq6PT0CQzsOn2YFnRB8RMsIQdFAsZ5UKdTFmkcChUrf-
> &s=BMRvLLAx
> > +cnlsyZlVCgOoUXju_jKom8zbKQ9GxlxlApg&e=
>
> I appreciate the code being open, but this is on a personal account that was
> created for only this one package, and it doesn't even have a README. Yet it
> is fully owned/copyrighted by Marvell and the code has been around since
> 2021? Why isn't this on a Marvell-controlled page to show that this really is
> supported and is the proper interface to use this driver that it provides to
> their customers?
>
User space driver is already part of open-source code base(github.com/DPDK/dpdk.git).
The mailbox related changes in user driver (roc_dpi.c file) are not yet upstreamed
which has the dependency with this kernel driver. So, I put the latest user driver
in personal account and shared so that it's helpful for reviewing kernel driver.
I will work internally and get it moved to Marvell-controlled page, will host at
https://github.com/MarvellEmbeddedProcessors and update the same in
Documentation page in next version.
>
>
> > diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst
> > b/Documentation/userspace-api/ioctl/ioctl-number.rst
> > index 457e16f06e04..e6fd0c386b59 100644
> > --- a/Documentation/userspace-api/ioctl/ioctl-number.rst
> > +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst
> > @@ -358,6 +358,7 @@ Code Seq# Include File
> Comments
> > 0xB6 all linux/fpga-dfl.h
> > 0xB7 all uapi/linux/remoteproc_cdev.h <mailto:linux-
> [email protected]>
> > 0xB7 all uapi/linux/nsfs.h <mailto:Andrei Vagin
> <[email protected]>>
> > +0xB8 01-02 uapi/misc/mrvl_cn10k_dpi.h Marvell CN10K DPI
> driver
> > 0xC0 00-0F linux/usb/iowarrior.h
> > 0xCA 00-0F uapi/misc/cxl.h
> > 0xCA 10-2F uapi/misc/ocxl.h
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > 960512bec428..ab77232d583e 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -13104,6 +13104,11 @@ S: Supported
> > F: Documentation/devicetree/bindings/mmc/marvell,xenon-
> sdhci.yaml
> > F: drivers/mmc/host/sdhci-xenon*
> >
> > +MARVELL OCTEON CN10K DPI DRIVER
> > +M: Vamsi Attunuru <[email protected]>
> > +S: Maintained
>
> So this is not part of your job to support this code? Why isn't Marvell allowing
> that to happen?
No, we are happy to support it further, will fix this.
>
> > +F: drivers/misc/mrvl_cn10k_dpi.c
> > +
> > MATROX FRAMEBUFFER DRIVER
> > L: [email protected]
> > S: Orphan
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > 4fb291f0bf7c..78470ef2538f 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -574,6 +574,19 @@ config NSM
> > To compile this driver as a module, choose M here.
> > The module will be called nsm.
> >
> > +config MARVELL_CN10K_DPI
> > + tristate "Octeon CN10K DPI driver"
> > + depends on ARM64 && PCI
> > + help
> > + Enables Octeon CN10K DMA packet interface (DPI) driver which
> intializes
> > + DPI hardware's physical function (PF) device's global configuration
> and
> > + its virtual function's (VFs) resource configuration to enable DMA
> transfers.
> > + DPI PF device does not have any data movement functionality, it
> only serves
> > + VF's resource configuration requests.
>
> Nit, please wrap at 72 columns, didn't checkpatch.pl complain about this?
>
Yes, I did not see any complains, not sure if I am missing any options. I will
double check and ensure clean patch in next version.
> > +
> > + To compile this driver as a module, choose M here: the module
> > + will be called mrvl_cn10k_dpi.
> > +
> > source "drivers/misc/c2port/Kconfig"
> > source "drivers/misc/eeprom/Kconfig"
> > source "drivers/misc/cb710/Kconfig"
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > ea6ea5bbbc9c..5106bf96ea5c 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -68,3 +68,5 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
> > obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
> > obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
> > obj-$(CONFIG_NSM) += nsm.o
> > +obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
> > +obj-y += mrvl_cn10k_dpi.o
>
> That is odd, why are you saying obj-y here? You want everyone to always
> build this code into the kernel image no matter what
>
Sorry, it's my bad, this change(2nd line) was mistakenly added, will remove it.
> > diff --git a/drivers/misc/mrvl_cn10k_dpi.c
> > b/drivers/misc/mrvl_cn10k_dpi.c new file mode 100644 index
> > 000000000000..bd99583994f9
> > --- /dev/null
> > +++ b/drivers/misc/mrvl_cn10k_dpi.c
> > @@ -0,0 +1,685 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/* Marvell Octeon CN10K DPI driver
> > + *
> > + * Copyright (C) 2024 Marvell.
> > + *
> > + */
> > +
> > +#include <linux/compat.h>
> > +#include <linux/delay.h>
> > +#include <linux/miscdevice.h>
> > +#include <linux/module.h>
> > +#include <linux/pci.h>
> > +#include <linux/irq.h>
> > +#include <linux/interrupt.h>
> > +
> > +#include <uapi/misc/mrvl_cn10k_dpi.h>
> > +
> > +#define DPI_DRV_NAME "mrvl-cn10k-dpi"
>
> KBUILD_MODNAME please.
ack
>
> > +
> > +/* PCI device IDs */
> > +#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
> > +#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xB900
> > +
> > +/* PCI BAR nos */
>
> What is "nos"?
It's numbers, will add full wording.
>
> > +#define PCI_DPI_CFG_BAR 0
> > +
> > +/* MSI-X interrupts */
> > +#define DPI_MAX_REQQ_INT 32
> > +#define DPI_MAX_CC_INT 64
> > +
> > +/* MBOX MSI-X interrupt vector index */ #define
> > +DPI_MBOX_PF_VF_INT_IDX 0x75
> > +
> > +#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
> > +
> > +#define DPI_MAX_VFS 32
> > +
> > +#define DPI_ENGINE_MASK GENMASK(2, 0)
> > +
> > +#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) (((x) &
> GENMASK_ULL(15, 0)) << 16)
> > +#define DPI_DMA_IDS_INST_STRM(x) (((x) &
> GENMASK_ULL(7, 0)) << 40)
> > +#define DPI_DMA_IDS_DMA_STRM(x) (((x) &
> GENMASK_ULL(7, 0)) << 32)
> > +#define DPI_DMA_ENG_EN_MOLR(x) (((x) &
> GENMASK_ULL(9, 0)) << 32)
> > +#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & GENMASK(2,
> 0)) << 4)
> > +#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) &
> GENMASK(15, 0))
> > +#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19,
> 0))
> > +#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13,
> 0))
> > +#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2,
> 0))
> > +#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5,
> 0))
> > +#define DPI_DMA_CONTROL_DMA_ENB
> GENMASK_ULL(53, 48)
> > +
> > +#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
> > +#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
> > +#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
> > +#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
> > +#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
> > +#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
> > +#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
> > +#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
> > +
> > +#define DPI_CTL_EN BIT_ULL(0)
> > +#define DPI_DMA_CC_INT BIT_ULL(0)
> > +#define DPI_DMA_QRST BIT_ULL(0)
> > +
> > +#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
> > +#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
> > +#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
> > +#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
> > +#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
> > +#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
> > +#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
> > +#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
> > +
> > +#define DPI_REQQ_INT \
> > + (DPI_REQQ_INT_INSTRFLT | \
> > + DPI_REQQ_INT_RDFLT | \
> > + DPI_REQQ_INT_WRFLT | \
> > + DPI_REQQ_INT_CSFLT | \
> > + DPI_REQQ_INT_INST_DBO | \
> > + DPI_REQQ_INT_INST_ADDR_NULL | \
> > + DPI_REQQ_INT_INST_FILL_INVAL | \
> > + DPI_REQQ_INT_INSTR_PSN)
> > +
> > +#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
> > +#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
> > +#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
> > +
> > +#define DPI_PF_RAS_INT \
> > + (DPI_PF_RAS_EBI_DAT_PSN | \
> > + DPI_PF_RAS_NCB_DAT_PSN | \
> > + DPI_PF_RAS_NCB_CMD_PSN)
> > +
> > +#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
> > +#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
> > +#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
> > +#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
> > +
> > +#define DPI_CTL 0x10010ULL
> > +#define DPI_DMA_CONTROL 0x10018ULL
> > +#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
> > +#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
> > +
> > +#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
> > +
> > +#define DPI_PF_RAS 0x10308ULL
> > +#define DPI_PF_RAS_ENA_W1C 0x10318ULL
> > +
> > +#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3)) #define
> > +DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
> > +
> > +#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5)) #define
> > +DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
> > +
> > +#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4)) #define
> > +DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
> > +
> > +#define DPI_MBOX_VF_PF_INT 0x16300ULL #define
> DPI_MBOX_VF_PF_INT_W1S
> > +0x16308ULL #define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
> #define
> > +DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
> > +
> > +#define DPI_WCTL_FIF_THR 0x17008ULL
> > +
> > +#define DPI_EBUS_MAX_PORTS 2
> > +
> > +#define DPI_EBUS_MRRS_MIN 128
> > +#define DPI_EBUS_MRRS_MAX 1024
> > +#define DPI_EBUS_MPS_MIN 128
> > +#define DPI_EBUS_MPS_MAX 1024
> > +#define DPI_WCTL_FIFO_THRESHOLD 0x30
> > +
> > +#define DPI_QUEUE_OPEN 0x1
> > +#define DPI_QUEUE_CLOSE 0x2
> > +#define DPI_REG_DUMP 0x3
> > +#define DPI_GET_REG_CFG 0x4
> > +#define DPI_QUEUE_OPEN_V2 0x5
> > +
> > +enum dpi_mbox_rsp_type {
> > + DPI_MBOX_TYPE_CMD,
> > + DPI_MBOX_TYPE_RSP_ACK,
> > + DPI_MBOX_TYPE_RSP_NACK,
> > +};
> > +
> > +struct dpivf_config {
> > + u16 csize;
> > + u32 aura;
> > + u16 sso_pf_func;
> > + u16 npa_pf_func;
>
> Do you intend to have unaligned accesses to the fields in this structure?
>
No, I will fix it.
> > +};
> > +
> > +struct dpipf_vf {
> > + u8 this_vfid;
> > + bool setup_done;
> > + struct dpivf_config vf_config;
> > +};
> > +
> > +/* DPI device mailbox */
> > +struct dpi_mbox {
> > + struct work_struct work;
> > + /* lock to serialize mbox requests */
> > + struct mutex lock;
> > + struct dpipf *pf;
> > + u8 __iomem *pf_vf_data_reg;
> > + u8 __iomem *vf_pf_data_reg;
> > +};
> > +
> > +struct dpipf {
> > + struct miscdevice miscdev;
> > + void __iomem *reg_base;
> > + struct pci_dev *pdev;
> > + struct dpipf_vf vf[DPI_MAX_VFS];
> > + /* Mailbox to talk to VFs */
> > + struct dpi_mbox *mbox[DPI_MAX_VFS];
> > +};
> > +
> > +union dpi_mbox_message_t {
>
> Didn't checkpatch complain about the "_t" here?
>
No, I will double check and fix it.
> > + u64 u[2];
>
> What is "u"?
>
> > + struct dpi_mbox_message_s {
> > + /* VF ID to configure */
> > + u64 vfid :8;
> > + /* Command code */
> > + u64 cmd :4;
> > + /* Command buffer size in 8-byte words */
> > + u64 csize :14;
> > + /* Aura of the command buffer */
> > + u64 aura :20;
> > + /* SSO PF function */
> > + u64 sso_pf_func :16;
> > + /* NPA PF function */
> > + u64 npa_pf_func :16;
> > + /* Work queue completion status enable */
> > + u64 wqecs :1;
> > + /* Work queue completion status byte offset */
> > + u64 wqecsoff :7;
> > + /* Reserved */
> > + u64 rsvd :42;
>
> reserved for what?
>
> If you are reading this from hardware, the bit fields you created here will
> NOT work or be portable at all. Please do this properly.
Sure, I will fix it properly.
>
> Also you have a mix of tabs and spaces for some reason in this structure,
> again, checkpatch should have caught that.
>
> > + } s __packed;
>
> "s"?
>
> What is "u" and "s" here?
>
>
> > +};
> > +
> > +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64
> > +val) {
> > + writeq(val, dpi->reg_base + offset);
>
> No need to read to ensure that the write succeeded? Or are you doing that
> in individual places where you want to make sure it happened? If so, I didn't
> see that in the use of this.
Yes, writes are guaranteed as it's an onboard pcie device and register writes
are uncached memory accesses.
>
> > +}
> > +
> > +static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset) {
> > + return readq(dpi->reg_base + offset); }
> > +
> > +static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset) {
> > + u64 reg;
> > +
> > + reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
> > + reg &= ~DPI_DMA_CONTROL_WQECSDIS;
> > + reg |= DPI_DMA_CONTROL_ZBWCSEN |
> DPI_DMA_CONTROL_WQECSMODE1;
> > + reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
> > + dpi_reg_write(dpi, DPI_DMA_CONTROL, reg); }
> > +
> > +static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf,
> > +u8 vf) {
> > + u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
> > + u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
> > + u16 csize = dpivf->vf_config.csize;
> > + u32 aura = dpivf->vf_config.aura;
> > + unsigned long timeout;
> > + u64 reg;
> > +
> > + dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
> > +
> > + /* Wait for a maximum of 3 sec */
> > + timeout = jiffies + msecs_to_jiffies(3000);
> > + while (!time_after(jiffies, timeout)) {
> > + reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf));
> > + if (!(reg & DPI_DMA_QRST))
> > + break;
> > +
> > + usleep_range(500, 1000);
>
> Why sleep this value? Please document.
ack
>
> > + }
> > +
> > + if (reg & DPI_DMA_QRST) {
> > + dev_err(&dpi->pdev->dev, "Queue reset failed\n");
> > + return -EBUSY;
> > + }
> > +
> > + dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
> > + dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
> > +
> > + reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) |
> DPI_DMA_IBUFF_CSIZE_NPA_FREE;
> > + dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
> > +
> > + reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf));
> > + reg |= DPI_DMA_IDS2_INST_AURA(aura);
> > + dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
> > +
> > + reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf));
> > + reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
> > + reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
> > + reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
> > + reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
> > + dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
> > +
> > + return 0;
> > +}
> > +
> > +static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf,
> > +u8 vf) {
> > + dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
> > +
> > + /* Reset IDS and IDS2 registers */
> > + dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
> > + dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0); }
> > +
> > +static void dpi_poll_pfvf_mbox(struct dpipf *dpi) {
> > + u64 reg;
> > + u32 vf;
> > +
> > + reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
> > + if (reg) {
> > + for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) {
> > + if (reg & BIT_ULL(vf))
> > + schedule_work(&dpi->mbox[vf]->work);
> > + }
> > + dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
> > + }
>
> No error if reg was not read properly?
Yes, ideally no errors as it's an on board pcie device.
>
> > +}
> > +
> > +static irqreturn_t dpi_mbox_intr_handler(int irq, void *data) {
> > + struct dpipf *dpi = data;
> > +
> > + dpi_poll_pfvf_mbox(dpi);
> > +
> > + return IRQ_HANDLED;
>
> So this can always succeed?
Yes. It's msix interrupt and not shared, I will check and fix if any thing
need to be validated.
>
> > +}
> > +
> > +static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf,
> > +union dpi_mbox_message_t *msg) {
> > + int ret = 0;
> > +
> > + switch (msg->s.cmd) {
> > + case DPI_QUEUE_OPEN:
> > + case DPI_QUEUE_OPEN_V2:
> > + dpivf->vf_config.aura = msg->s.aura;
> > + dpivf->vf_config.csize = msg->s.cmd == DPI_QUEUE_OPEN ?
> msg->s.csize / 8 :
> > + msg->s.csize;
> > + dpivf->vf_config.sso_pf_func = msg->s.sso_pf_func;
> > + dpivf->vf_config.npa_pf_func = msg->s.npa_pf_func;
> > + ret = dpi_queue_init(dpi, dpivf, msg->s.vfid);
> > + if (!ret) {
> > + if (msg->s.wqecs)
> > + dpi_wqe_cs_offset(dpi, msg->s.wqecsoff);
> > + dpivf->setup_done = true;
> > + }
> > + break;
> > + case DPI_QUEUE_CLOSE:
> > + dpivf->vf_config.aura = 0;
> > + dpivf->vf_config.csize = 0;
> > + dpivf->vf_config.sso_pf_func = 0;
> > + dpivf->vf_config.npa_pf_func = 0;
> > + dpi_queue_fini(dpi, dpivf, msg->s.vfid);
> > + dpivf->setup_done = false;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static void dpi_pfvf_mbox_work(struct work_struct *work) {
> > + struct dpi_mbox *mbox = container_of(work, struct dpi_mbox,
> work);
> > + union dpi_mbox_message_t msg = { 0 };
>
> Are you sure this can be on the stack?
No, it's not guaranteed, will use memset. Thanks.
>
> > + struct dpipf_vf *dpivf;
> > + struct dpipf *dpi;
> > + int ret;
> > +
> > + dpi = mbox->pf;
> > +
> > + mutex_lock(&mbox->lock);
> > + msg.u[0] = readq(mbox->vf_pf_data_reg);
> > + if (unlikely(msg.u[0] == (u64)-1))
> > + goto exit;
>
> Only use likely/unlikely if you can prove with a benchmark that it makes a
> difference. Otherwise let the CPU and compiler choose for you, as it knows
> better than you do (and will know better over time.)
Ack.
>
> If you want to use unlikely, you have to document it as to how it matters.
>
> > +
> > + if (unlikely(msg.s.vfid >= pci_num_vf(dpi->pdev))) {
> > + dev_err(&dpi->pdev->dev, "Invalid vfid:%d\n", msg.s.vfid);
>
> You send this to the kernel log if a device is broken?
Ok, ideally, it's not case, will remove log.
>
> > + goto exit;
> > + }
> > +
> > + dpivf = &dpi->vf[msg.s.vfid];
> > + msg.u[1] = readq(mbox->pf_vf_data_reg);
> > +
> > + ret = queue_config(dpi, dpivf, &msg);
> > + if (ret < 0)
> > + writeq(DPI_MBOX_TYPE_RSP_NACK, mbox-
> >pf_vf_data_reg);
> > + else
> > + writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
> > +exit:
> > + mutex_unlock(&mbox->lock);
> > +}
> > +
> > +/* Setup registers for a PF mailbox */ static void
> > +dpi_setup_mbox_regs(struct dpipf *dpi, int vf) {
> > + struct dpi_mbox *mbox = dpi->mbox[vf];
> > +
> > + mbox->pf_vf_data_reg = dpi->reg_base +
> DPI_MBOX_PF_VF_DATA0(vf);
> > + mbox->vf_pf_data_reg = dpi->reg_base +
> DPI_MBOX_PF_VF_DATA1(vf); }
> > +
> > +static int dpi_pfvf_mbox_setup(struct dpipf *dpi) {
> > + int vf;
> > +
> > + for (vf = 0; vf < DPI_MAX_VFS; vf++) {
> > + dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev,
> > +sizeof(*dpi->mbox[vf]), GFP_KERNEL);
> > +
> > + if (!dpi->mbox[vf])
> > + return -ENOMEM;
> > +
> > + mutex_init(&dpi->mbox[vf]->lock);
> > + INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
> > + dpi->mbox[vf]->pf = dpi;
> > + dpi_setup_mbox_regs(dpi, vf);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void dpi_pfvf_mbox_destroy(struct dpipf *dpi) {
> > + unsigned int vf;
> > +
> > + for (vf = 0; vf < DPI_MAX_VFS; vf++) {
> > + if (work_pending(&dpi->mbox[vf]->work))
> > + cancel_work_sync(&dpi->mbox[vf]->work);
> > +
> > + dpi->mbox[vf] = NULL;
> > + }
> > +}
> > +
> > +static void dpi_init(struct dpipf *dpi) {
> > + unsigned int engine, port;
> > + u8 mrrs_val, mps_val;
> > + u64 reg;
> > +
> > + for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
> > + if (engine == 4 || engine == 5)
> > + reg = DPI_ENG_BUF_BLKS(16);
> > + else
> > + reg = DPI_ENG_BUF_BLKS(8);
> > +
> > + dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
> > + }
> > +
> > + reg = DPI_DMA_CONTROL_ZBWCSEN |
> DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
> > + DPI_DMA_CONTROL_O_MODE |
> DPI_DMA_CONTROL_DMA_ENB;
> > +
> > + dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
> > + dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
> > +
> > + mrrs_val = 2; /* 512B */
> > + mps_val = 1; /* 256B */
> > +
> > + for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
> > + reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
> > + reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(7) |
> DPI_EBUS_PORTX_CFG_MPS(7));
> > + reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) |
> DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
> > + dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
> > + }
> > +
> > + dpi_reg_write(dpi, DPI_WCTL_FIF_THR,
> DPI_WCTL_FIFO_THRESHOLD); }
> > +
> > +static void dpi_fini(struct dpipf *dpi) {
> > + unsigned int engine;
> > +
> > + for (engine = 0; engine < DPI_MAX_ENGINES; engine++)
> > + dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
> > +
> > + dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
> > + dpi_reg_write(dpi, DPI_CTL, 0);
> > +}
> > +
> > +static void dpi_free_irq_vectors(void *pdev) {
> > + pci_free_irq_vectors((struct pci_dev *)pdev); }
> > +
> > +static int dpi_irq_init(struct dpipf *dpi) {
> > + struct pci_dev *pdev = dpi->pdev;
> > + struct device *dev = &pdev->dev;
> > + int i, ret;
> > +
> > + /* Clear all RAS interrupts */
> > + dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
> > +
> > + /* Clear all RAS interrupt enable bits */
> > + dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
> > +
> > + for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
> > + dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
> > + dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i),
> DPI_REQQ_INT);
> > + }
> > +
> > + for (i = 0; i < DPI_MAX_CC_INT; i++) {
> > + dpi_reg_write(dpi, DPI_DMA_CCX_INT(i),
> DPI_DMA_CC_INT);
> > + dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i),
> DPI_DMA_CC_INT);
> > + }
> > +
> > + ret = pci_alloc_irq_vectors(pdev, DPI_MAX_IRQS, DPI_MAX_IRQS,
> PCI_IRQ_MSIX);
> > + if (ret != DPI_MAX_IRQS) {
> > + dev_err(dev, "DPI: Failed to alloc %d msix irqs\n",
> DPI_MAX_IRQS);
> > + return ret;
> > + }
> > +
> > + ret = devm_add_action_or_reset(dev, dpi_free_irq_vectors, pdev);
> > + if (ret) {
> > + dev_err(dev, "DPI: Failed to add irq free action\n");
> > + return ret;
> > + }
> > +
> > + ret = devm_request_irq(dev, pci_irq_vector(pdev,
> DPI_MBOX_PF_VF_INT_IDX),
> > + dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
> > + if (ret) {
> > + dev_err(dev, "DPI: request_irq failed for mbox; err=%d\n",
> ret);
> > + return ret;
> > + }
> > +
> > + dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S,
> GENMASK_ULL(31, 0));
> > +
> > + return 0;
> > +}
> > +
> > +static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg) {
> > + struct dpi_mps_mrrs_cfg cfg;
> > + u8 mrrs_val, mps_val;
> > + u64 reg;
> > +
> > + if (copy_from_user(&cfg, arg, sizeof(struct dpi_mps_mrrs_cfg)))
> > + return -EFAULT;
> > +
> > + if (cfg.max_read_req_sz < DPI_EBUS_MRRS_MIN ||
> cfg.max_read_req_sz > DPI_EBUS_MRRS_MAX ||
> > + !is_power_of_2(cfg.max_read_req_sz)) {
> > + dev_err(&dpi->pdev->dev, "Invalid MRRS size:%u\n",
> > +cfg.max_read_req_sz);
>
> You are allowing userspace to spam the kernel log with messages by sending
> the driver invalid data. THat is a denial of service, please never do that.
Sure, will fix it.
>
> > + return -EINVAL;
> > + }
> > +
> > + if (cfg.max_payload_sz < DPI_EBUS_MPS_MIN ||
> cfg.max_payload_sz > DPI_EBUS_MPS_MAX ||
> > + !is_power_of_2(cfg.max_payload_sz)) {
> > + dev_err(&dpi->pdev->dev, "Invalid MPS size:%u\n",
> cfg.max_payload_sz);
> > + return -EINVAL;
> > + }
> > +
> > + if (cfg.port >= DPI_EBUS_MAX_PORTS) {
> > + dev_err(&dpi->pdev->dev, "Invalid EBUS port:%u\n",
> cfg.port);
> > + return -EINVAL;
> > + }
> > +
> > + mrrs_val = fls(cfg.max_read_req_sz >> 8);
> > + mps_val = fls(cfg.max_payload_sz >> 8);
> > +
> > + reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port));
> > + reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) |
> DPI_EBUS_PORTX_CFG_MPS(0x7));
> > + reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) |
> DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
> > + dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
> > +
> > + return 0;
> > +}
> > +
> > +static int dpi_engine_config(struct dpipf *dpi, void __user *arg) {
> > + struct dpi_engine_cfg cfg;
> > + unsigned int engine;
> > + u8 *eng_buf;
> > + u64 reg;
> > +
> > + if (copy_from_user(&cfg, arg, sizeof(struct dpi_engine_cfg)))
> > + return -EFAULT;
>
> No need to ever validate any information in that structure from userspace?
> You always blindly copy it on to the device? Userspace can never get this
> wrong?
>
Yes, couple of range checks are needed, will address in next patch.
> > +
> > + eng_buf = (u8 *)&cfg.fifo_mask;
> > +
> > + for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
> > + reg = DPI_ENG_BUF_BLKS(eng_buf[engine &
> DPI_ENGINE_MASK]);
> > + dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
> > +
> > + if (cfg.update_molr) {
> > + reg = DPI_DMA_ENG_EN_MOLR(cfg.molr[engine &
> DPI_ENGINE_MASK]);
> > + dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine),
> reg);
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static long dpi_dev_ioctl(struct file *fptr, unsigned int cmd,
> > +unsigned long data) {
> > + void __user *arg = (void __user *)data;
> > + struct dpipf *dpi;
> > + int ret = -EINVAL;
>
> Wrong error code for an invalid ioctl command :(
ack
>
> > +
> > + dpi = container_of(fptr->private_data, struct dpipf, miscdev);
> > +
> > + switch (cmd) {
> > + case DPI_MPS_MRRS_CFG:
> > + ret = dpi_mps_mrrs_config(dpi, arg);
> > + break;
> > + case DPI_ENGINE_CFG:
> > + ret = dpi_engine_config(dpi, arg);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static const struct file_operations dpi_device_fops = {
> > + .owner = THIS_MODULE,
> > + .unlocked_ioctl = dpi_dev_ioctl,
> > + .compat_ioctl = compat_ptr_ioctl,
> > +};
> > +
> > +static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id
> > +*id) {
> > + struct device *dev = &pdev->dev;
> > + struct dpipf *dpi;
> > + int ret;
> > +
> > + dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
> > + if (!dpi)
> > + return -ENOMEM;
> > +
> > + dpi->pdev = pdev;
> > +
> > + ret = pcim_enable_device(pdev);
> > + if (ret) {
> > + dev_err(dev, "DPI: Failed to enable PCI device\n");
> > + return ret;
> > + }
> > +
> > + ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), DPI_DRV_NAME);
> > + if (ret) {
> > + dev_err(dev, "DPI: Failed to request MMIO region\n");
> > + return ret;
> > + }
> > +
> > + dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
> > +
> > + /* Initialize global PF registers */
> > + dpi_init(dpi);
> > +
> > + /* Setup PF-VF mailbox */
> > + ret = dpi_pfvf_mbox_setup(dpi);
> > + if (ret) {
> > + dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
> > + goto err_dpi_fini;
> > + }
> > +
> > + /* Register interrupts */
> > + ret = dpi_irq_init(dpi);
> > + if (ret) {
> > + dev_err(dev, "DPI: Failed to initialize irq vectors\n");
> > + goto err_dpi_mbox_free;
> > + }
> > +
> > + pci_set_drvdata(pdev, dpi);
> > + dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
> > + dpi->miscdev.name = DPI_DRV_NAME;
> > + dpi->miscdev.fops = &dpi_device_fops;
> > + dpi->miscdev.parent = dev;
> > +
> > + ret = misc_register(&dpi->miscdev);
> > + if (ret) {
> > + dev_err(dev, "DPI: Failed to register misc device\n");
> > + goto err_dpi_mbox_free;
> > + }
> > +
> > + return 0;
> > +
> > +err_dpi_mbox_free:
> > + dpi_pfvf_mbox_destroy(dpi);
> > +err_dpi_fini:
> > + dpi_fini(dpi);
> > + return ret;
> > +}
> > +
> > +static void dpi_remove(struct pci_dev *pdev) {
> > + struct dpipf *dpi = pci_get_drvdata(pdev);
> > +
> > + misc_deregister(&dpi->miscdev);
> > + pci_sriov_configure_simple(pdev, 0);
> > + dpi_pfvf_mbox_destroy(dpi);
> > + dpi_fini(dpi);
> > + pci_set_drvdata(pdev, NULL);
> > +}
> > +
> > +static const struct pci_device_id dpi_id_table[] = {
> > + { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
> PCI_DEVID_MRVL_CN10K_DPI_PF,
> > + PCI_VENDOR_ID_CAVIUM,
> PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
> > + { 0, } /* end of table */
> > +};
> > +
> > +static struct pci_driver dpi_driver = {
> > + .name = DPI_DRV_NAME,
> > + .id_table = dpi_id_table,
> > + .probe = dpi_probe,
> > + .remove = dpi_remove,
> > + .sriov_configure = pci_sriov_configure_simple, };
> > +
> > +module_pci_driver(dpi_driver);
> > +MODULE_DEVICE_TABLE(pci, dpi_id_table);
> MODULE_AUTHOR("Marvell.");
> > +MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/include/uapi/misc/mrvl_cn10k_dpi.h
> > b/include/uapi/misc/mrvl_cn10k_dpi.h
> > new file mode 100644
> > index 000000000000..a1951644448a
> > --- /dev/null
> > +++ b/include/uapi/misc/mrvl_cn10k_dpi.h
> > @@ -0,0 +1,37 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
>
> Why is this file "GPL-2.0+" but your driver is "GPL-2.0"? Is that what your
> lawyers want to have happen (sorry, I have to ask.)
No specific reason, I think I need to use " GPL-2.0-or-later" instead of
"GPL-2.0+", will fix it.
Thanks
Vamsi
>
> thanks,
>
> greg k-h
On Wed, May 01, 2024 at 07:46:55AM +0000, Vamsi Krishna Attunuru wrote:
> > > --- /dev/null
> > > +++ b/include/uapi/misc/mrvl_cn10k_dpi.h
> > > @@ -0,0 +1,37 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
> >
> > Why is this file "GPL-2.0+" but your driver is "GPL-2.0"? Is that what your
> > lawyers want to have happen (sorry, I have to ask.)
>
> No specific reason, I think I need to use " GPL-2.0-or-later" instead of
> "GPL-2.0+", will fix it.
No, that's not the problem here at all, either of those are the same.
The problem is that it does not match with the C file. Please work with
your legal department to choose what license you want for the files and
be consistent.
thanks,
greg k-h
Adds a misc driver for Marvell CN10K DPI(DMA Engine) device's physical
function which initializes DPI DMA hardware's global configuration and
enables hardware mailbox channels between physical function (PF) and
it's virtual functions (VF). VF device drivers (User space drivers) use
this hw mailbox to communicate any required device configuration on it's
respective VF device. Accordingly, this DPI PF driver provisions the
VF device resources.
At the hardware level, the DPI physical function (PF) acts as a management
interface to setup the VF device resources, VF devices are only provisioned
to handle or control the actual DMA Engine's data transfer capabilities.
Signed-off-by: Vamsi Attunuru <[email protected]>
Reviewed-by: Srujana Challa <[email protected]>
---
Changes V6 -> V7:
- Updated documentation with required references
- Addressed V6 review comments
Changes V5 -> V6:
- Updated documentation
- Fixed data types in uapi file
Changes V4 -> V5:
- Fixed license and data types in uapi file
Changes V3 -> V4:
- Moved ioctl definations to .h file
- Fixed structure alignements which are passed in ioctl
Changes V2 -> V3:
- Added ioctl operation to the fops
- Used managed version of kzalloc & request_irq
- Addressed miscellaneous comments
Changes V1 -> V2:
- Fixed return values and busy-wait loops
- Merged .h file into .c file
- Fixed directory structure
- Removed module params
- Registered the device as misc device
Documentation/misc-devices/index.rst | 1 +
Documentation/misc-devices/mrvl_cn10k_dpi.rst | 53 ++
.../userspace-api/ioctl/ioctl-number.rst | 1 +
MAINTAINERS | 5 +
drivers/misc/Kconfig | 14 +
drivers/misc/Makefile | 1 +
drivers/misc/mrvl_cn10k_dpi.c | 698 ++++++++++++++++++
include/uapi/misc/mrvl_cn10k_dpi.h | 37 +
8 files changed, 810 insertions(+)
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index 2d0ce9138588..8c5b226d8313 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -21,6 +21,7 @@ fit into other categories.
isl29003
lis3lv02d
max6875
+ mrvl_cn10k_dpi
oxsemi-tornado
pci-endpoint-test
spear-pcie-gadget
diff --git a/Documentation/misc-devices/mrvl_cn10k_dpi.rst b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
new file mode 100644
index 000000000000..ff59560a25cf
--- /dev/null
+++ b/Documentation/misc-devices/mrvl_cn10k_dpi.rst
@@ -0,0 +1,53 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===============================================
+Marvell CN10K DMA packet interface (DPI) driver
+===============================================
+
+Overview
+========
+
+DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
+DPI hardware comprises a physical function (PF), its virtual functions,
+mailbox logic, and a set of DMA engines & DMA command queues.
+
+DPI PF function is an administrative function which services the mailbox
+requests from its VF functions and provisions DMA engine resources to
+it's VF functions.
+
+mrvl_cn10k_dpi.ko misc driver loads on DPI PF device and services the
+mailbox commands submitted by the VF devices and accordingly initializes
+the DMA engines and VF device's DMA command queues. Also, driver creates
+/dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
+attributes like fifo length, molr, mps & mrrs.
+
+DPI PF driver is just an administrative driver to setup its VF device's
+queues and provisions the hardware resources, it cannot initiate any
+DMA operations. Only VF devices are provisioned with DMA capabilities.
+
+Driver location
+===============
+
+drivers/misc/mrvl_cn10k_dpi.c
+
+Driver IOCTLs
+=============
+
+:c:macro::`DPI_MPS_MRRS_CFG`
+ioctl that sets max payload size & max read request size parameters of
+a pem port to which DMA engines are wired.
+
+
+:c:macro::`DPI_ENGINE_CFG`
+ioctl that sets DMA engine's fifo sizes & max outstanding load request
+thresholds.
+
+User space code example
+=======================
+
+DPI VF devices are probed and accessed from user space applications using
+vfio-pci driver. Below is a sample dpi dma application to demonstrate on
+how applications use mailbox and ioctl services from DPI PF kernel driver.
+
+https://github.com/MarvellEmbeddedProcessors/dpi-sample-app
+
diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst
index a141e8e65c5d..def539770439 100644
--- a/Documentation/userspace-api/ioctl/ioctl-number.rst
+++ b/Documentation/userspace-api/ioctl/ioctl-number.rst
@@ -362,6 +362,7 @@ Code Seq# Include File Comments
0xB6 all linux/fpga-dfl.h
0xB7 all uapi/linux/remoteproc_cdev.h <mailto:[email protected]>
0xB7 all uapi/linux/nsfs.h <mailto:Andrei Vagin <[email protected]>>
+0xB8 01-02 uapi/misc/mrvl_cn10k_dpi.h Marvell CN10K DPI driver
0xC0 00-0F linux/usb/iowarrior.h
0xCA 00-0F uapi/misc/cxl.h
0xCA 10-2F uapi/misc/ocxl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 758c202ec712..091660ae2758 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13238,6 +13238,11 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
+MARVELL OCTEON CN10K DPI DRIVER
+M: Vamsi Attunuru <[email protected]>
+S: Supported
+F: drivers/misc/mrvl_cn10k_dpi.c
+
MATROX FRAMEBUFFER DRIVER
L: [email protected]
S: Orphan
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 2907b5c23368..68dcbb76bd4e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -584,6 +584,20 @@ config NSM
To compile this driver as a module, choose M here.
The module will be called nsm.
+config MARVELL_CN10K_DPI
+ tristate "Octeon CN10K DPI driver"
+ depends on ARM64 && PCI
+ help
+ Enables Octeon CN10K DMA packet interface (DPI) driver which
+ intializes DPI hardware's physical function (PF) device's
+ global configuration and its virtual function (VFs) resource
+ configuration to enable DMA transfers. DPI PF device does not
+ have any data movement functionality, it only serves VF's
+ resource configuration requests.
+
+ To compile this driver as a module, choose M here: the module
+ will be called mrvl_cn10k_dpi.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 153a3f4837e8..852a7e3a5472 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -69,3 +69,4 @@ obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o
obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o
obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o
obj-$(CONFIG_NSM) += nsm.o
+obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o
diff --git a/drivers/misc/mrvl_cn10k_dpi.c b/drivers/misc/mrvl_cn10k_dpi.c
new file mode 100644
index 000000000000..33337873afde
--- /dev/null
+++ b/drivers/misc/mrvl_cn10k_dpi.c
@@ -0,0 +1,698 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#include <linux/compat.h>
+#include <linux/delay.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <uapi/misc/mrvl_cn10k_dpi.h>
+
+/* PCI device IDs */
+#define PCI_DEVID_MRVL_CN10K_DPI_PF 0xA080
+#define PCI_SUBDEVID_MRVL_CN10K_DPI_PF 0xB900
+
+/* PCI BAR Number */
+#define PCI_DPI_CFG_BAR 0
+
+/* MSI-X interrupts */
+#define DPI_MAX_REQQ_INT 0x20
+#define DPI_MAX_CC_INT 0x40
+
+/* MBOX MSI-X interrupt vector index */
+#define DPI_MBOX_PF_VF_INT_IDX 0x75
+
+#define DPI_MAX_IRQS (DPI_MBOX_PF_VF_INT_IDX + 1)
+
+#define DPI_MAX_VFS 0x20
+
+#define DPI_MAX_ENG_FIFO_SZ 0x20
+#define DPI_MAX_ENG_MOLR 0x400
+
+#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) (((x) & GENMASK_ULL(15, 0)) << 16)
+#define DPI_DMA_IDS_INST_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 40)
+#define DPI_DMA_IDS_DMA_STRM(x) (((x) & GENMASK_ULL(7, 0)) << 32)
+#define DPI_DMA_ENG_EN_MOLR(x) (((x) & GENMASK_ULL(9, 0)) << 32)
+#define DPI_EBUS_PORTX_CFG_MPS(x) (((x) & GENMASK(2, 0)) << 4)
+#define DPI_DMA_IDS_DMA_SSO_PF_FUNC(x) ((x) & GENMASK(15, 0))
+#define DPI_DMA_IDS2_INST_AURA(x) ((x) & GENMASK(19, 0))
+#define DPI_DMA_IBUFF_CSIZE_CSIZE(x) ((x) & GENMASK(13, 0))
+#define DPI_EBUS_PORTX_CFG_MRRS(x) ((x) & GENMASK(2, 0))
+#define DPI_ENG_BUF_BLKS(x) ((x) & GENMASK(5, 0))
+#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)
+
+#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
+#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
+#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
+#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
+#define DPI_DMA_CONTROL_WQECSOFF(offset) (((u64)offset) << 40)
+#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
+#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
+#define DPI_DMA_IBUFF_CSIZE_NPA_FREE BIT(16)
+
+#define DPI_CTL_EN BIT_ULL(0)
+#define DPI_DMA_CC_INT BIT_ULL(0)
+#define DPI_DMA_QRST BIT_ULL(0)
+
+#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
+#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
+#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
+#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
+#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
+#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
+#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
+#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
+
+#define DPI_REQQ_INT \
+ (DPI_REQQ_INT_INSTRFLT | \
+ DPI_REQQ_INT_RDFLT | \
+ DPI_REQQ_INT_WRFLT | \
+ DPI_REQQ_INT_CSFLT | \
+ DPI_REQQ_INT_INST_DBO | \
+ DPI_REQQ_INT_INST_ADDR_NULL | \
+ DPI_REQQ_INT_INST_FILL_INVAL | \
+ DPI_REQQ_INT_INSTR_PSN)
+
+#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
+#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
+#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
+
+#define DPI_PF_RAS_INT \
+ (DPI_PF_RAS_EBI_DAT_PSN | \
+ DPI_PF_RAS_NCB_DAT_PSN | \
+ DPI_PF_RAS_NCB_CMD_PSN)
+
+#define DPI_DMAX_IBUFF_CSIZE(x) (0x0ULL | ((x) << 11))
+#define DPI_DMAX_IDS(x) (0x18ULL | ((x) << 11))
+#define DPI_DMAX_IDS2(x) (0x20ULL | ((x) << 11))
+#define DPI_DMAX_QRST(x) (0x30ULL | ((x) << 11))
+
+#define DPI_CTL 0x10010ULL
+#define DPI_DMA_CONTROL 0x10018ULL
+#define DPI_PF_RAS 0x10308ULL
+#define DPI_PF_RAS_ENA_W1C 0x10318ULL
+#define DPI_MBOX_VF_PF_INT 0x16300ULL
+#define DPI_MBOX_VF_PF_INT_W1S 0x16308ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1C 0x16310ULL
+#define DPI_MBOX_VF_PF_INT_ENA_W1S 0x16318ULL
+
+#define DPI_DMA_ENGX_EN(x) (0x10040ULL | ((x) << 3))
+#define DPI_ENGX_BUF(x) (0x100C0ULL | ((x) << 3))
+#define DPI_EBUS_PORTX_CFG(x) (0x10100ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT(x) (0x11000ULL | ((x) << 3))
+#define DPI_DMA_CCX_INT_ENA_W1C(x) (0x11800ULL | ((x) << 3))
+#define DPI_REQQX_INT(x) (0x12C00ULL | ((x) << 5))
+#define DPI_REQQX_INT_ENA_W1C(x) (0x13800ULL | ((x) << 5))
+#define DPI_MBOX_PF_VF_DATA0(x) (0x16000ULL | ((x) << 4))
+#define DPI_MBOX_PF_VF_DATA1(x) (0x16008ULL | ((x) << 4))
+
+#define DPI_WCTL_FIF_THR 0x17008ULL
+
+#define DPI_EBUS_MAX_PORTS 2
+
+#define DPI_EBUS_MRRS_MIN 128
+#define DPI_EBUS_MRRS_MAX 1024
+#define DPI_EBUS_MPS_MIN 128
+#define DPI_EBUS_MPS_MAX 1024
+#define DPI_WCTL_FIFO_THRESHOLD 0x30
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+#define DPI_QUEUE_OPEN_V2 0x5
+
+enum dpi_mbox_rsp_type {
+ DPI_MBOX_TYPE_CMD,
+ DPI_MBOX_TYPE_RSP_ACK,
+ DPI_MBOX_TYPE_RSP_NACK,
+};
+
+struct dpivf_config {
+ u32 aura;
+ u16 csize;
+ u16 sso_pf_func;
+ u16 npa_pf_func;
+};
+
+struct dpipf_vf {
+ struct dpivf_config vf_config;
+ bool setup_done;
+ u8 this_vfid;
+};
+
+/* DPI device mailbox */
+struct dpi_mbox {
+ struct work_struct work;
+ /* lock to serialize mbox requests */
+ struct mutex lock;
+ struct dpipf *pf;
+ u8 __iomem *pf_vf_data_reg;
+ u8 __iomem *vf_pf_data_reg;
+};
+
+struct dpipf {
+ struct miscdevice miscdev;
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ struct dpipf_vf vf[DPI_MAX_VFS];
+ /* Mailbox to talk to VFs */
+ struct dpi_mbox *mbox[DPI_MAX_VFS];
+};
+
+union dpi_mbox_message {
+ u64 word[2];
+ struct {
+#if defined(__BIG_ENDIAN_BITFIELD)
+ /* SSO PF function */
+ u64 sso_pf_func :16;
+ /* Aura of the command buffer */
+ u64 aura :20;
+ /* Command buffer size in 8-byte words */
+ u64 csize :16;
+ /* Command code */
+ u64 cmd :4;
+ /* VF ID to configure */
+ u64 vfid :8;
+ /* Reserved for future use */
+ u64 rsvd_85_127 :40;
+ /* Work queue completion status byte offset */
+ u64 wqecsoff :7;
+ /* Work queue completion status enable */
+ u64 wqecs :1;
+ /* NPA PF function */
+ u64 npa_pf_func :16;
+#else
+ /* VF ID to configure */
+ u64 vfid :8;
+ /* Command code */
+ u64 cmd :4;
+ /* Command buffer size in 8-byte words */
+ u64 csize :16;
+ /* Aura of the command buffer */
+ u64 aura :20;
+ /* SSO PF function */
+ u64 sso_pf_func :16;
+ /* NPA PF function */
+ u64 npa_pf_func :16;
+ /* Work queue completion status enable */
+ u64 wqecs :1;
+ /* Work queue completion status byte offset */
+ u64 wqecsoff :7;
+ /* Reserved for future use */
+ u64 rsvd_85_127 :40;
+#endif
+ };
+};
+
+static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
+{
+ writeq(val, dpi->reg_base + offset);
+}
+
+static inline u64 dpi_reg_read(struct dpipf *dpi, u64 offset)
+{
+ return readq(dpi->reg_base + offset);
+}
+
+static void dpi_wqe_cs_offset(struct dpipf *dpi, u8 offset)
+{
+ u64 reg;
+
+ reg = dpi_reg_read(dpi, DPI_DMA_CONTROL);
+ reg &= ~DPI_DMA_CONTROL_WQECSDIS;
+ reg |= DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_WQECSMODE1;
+ reg |= DPI_DMA_CONTROL_WQECSOFF(offset);
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+}
+
+static int dpi_queue_init(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ u16 sso_pf_func = dpivf->vf_config.sso_pf_func;
+ u16 npa_pf_func = dpivf->vf_config.npa_pf_func;
+ u16 csize = dpivf->vf_config.csize;
+ u32 aura = dpivf->vf_config.aura;
+ unsigned long timeout;
+ u64 reg;
+
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Wait for a maximum of 3 sec */
+ timeout = jiffies + msecs_to_jiffies(3000);
+ while (!time_after(jiffies, timeout)) {
+ reg = dpi_reg_read(dpi, DPI_DMAX_QRST(vf));
+ if (!(reg & DPI_DMA_QRST))
+ break;
+
+ /* Reset would take time for the request cache to drain */
+ usleep_range(500, 1000);
+ }
+
+ if (reg & DPI_DMA_QRST) {
+ dev_err(&dpi->pdev->dev, "Queue reset failed\n");
+ return -EBUSY;
+ }
+
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+
+ reg = DPI_DMA_IBUFF_CSIZE_CSIZE(csize) | DPI_DMA_IBUFF_CSIZE_NPA_FREE;
+ dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS2(vf));
+ reg |= DPI_DMA_IDS2_INST_AURA(aura);
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
+
+ reg = dpi_reg_read(dpi, DPI_DMAX_IDS(vf));
+ reg |= DPI_DMA_IDS_DMA_NPA_PF_FUNC(npa_pf_func);
+ reg |= DPI_DMA_IDS_DMA_SSO_PF_FUNC(sso_pf_func);
+ reg |= DPI_DMA_IDS_DMA_STRM(vf + 1);
+ reg |= DPI_DMA_IDS_INST_STRM(vf + 1);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
+
+ return 0;
+}
+
+static void dpi_queue_fini(struct dpipf *dpi, struct dpipf_vf *dpivf, u8 vf)
+{
+ dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
+
+ /* Reset IDS and IDS2 registers */
+ dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
+ dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
+}
+
+static void dpi_poll_pfvf_mbox(struct dpipf *dpi)
+{
+ u64 reg;
+ u32 vf;
+
+ reg = dpi_reg_read(dpi, DPI_MBOX_VF_PF_INT);
+ if (reg) {
+ for (vf = 0; vf < pci_num_vf(dpi->pdev); vf++) {
+ if (reg & BIT_ULL(vf))
+ schedule_work(&dpi->mbox[vf]->work);
+ }
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
+ }
+}
+
+static irqreturn_t dpi_mbox_intr_handler(int irq, void *data)
+{
+ struct dpipf *dpi = data;
+
+ dpi_poll_pfvf_mbox(dpi);
+
+ return IRQ_HANDLED;
+}
+
+static int queue_config(struct dpipf *dpi, struct dpipf_vf *dpivf, union dpi_mbox_message *msg)
+{
+ int ret = 0;
+
+ switch (msg->cmd) {
+ case DPI_QUEUE_OPEN:
+ case DPI_QUEUE_OPEN_V2:
+ dpivf->vf_config.aura = msg->aura;
+ dpivf->vf_config.csize = msg->cmd == DPI_QUEUE_OPEN ? msg->csize / 8 :
+ msg->csize;
+ dpivf->vf_config.sso_pf_func = msg->sso_pf_func;
+ dpivf->vf_config.npa_pf_func = msg->npa_pf_func;
+ ret = dpi_queue_init(dpi, dpivf, msg->vfid);
+ if (!ret) {
+ if (msg->wqecs)
+ dpi_wqe_cs_offset(dpi, msg->wqecsoff);
+ dpivf->setup_done = true;
+ }
+ break;
+ case DPI_QUEUE_CLOSE:
+ dpivf->vf_config.aura = 0;
+ dpivf->vf_config.csize = 0;
+ dpivf->vf_config.sso_pf_func = 0;
+ dpivf->vf_config.npa_pf_func = 0;
+ dpi_queue_fini(dpi, dpivf, msg->vfid);
+ dpivf->setup_done = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void dpi_pfvf_mbox_work(struct work_struct *work)
+{
+ struct dpi_mbox *mbox = container_of(work, struct dpi_mbox, work);
+ union dpi_mbox_message msg;
+ struct dpipf_vf *dpivf;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = mbox->pf;
+ memset(&msg, 0, sizeof(msg));
+
+ mutex_lock(&mbox->lock);
+ msg.word[0] = readq(mbox->vf_pf_data_reg);
+ if (msg.word[0] == (u64)-1)
+ goto exit;
+
+ if (msg.vfid >= pci_num_vf(dpi->pdev))
+ goto exit;
+
+ dpivf = &dpi->vf[msg.vfid];
+ msg.word[1] = readq(mbox->pf_vf_data_reg);
+
+ ret = queue_config(dpi, dpivf, &msg);
+ if (ret < 0)
+ writeq(DPI_MBOX_TYPE_RSP_NACK, mbox->pf_vf_data_reg);
+ else
+ writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
+exit:
+ mutex_unlock(&mbox->lock);
+}
+
+/* Setup registers for a PF mailbox */
+static void dpi_setup_mbox_regs(struct dpipf *dpi, int vf)
+{
+ struct dpi_mbox *mbox = dpi->mbox[vf];
+
+ mbox->pf_vf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA0(vf);
+ mbox->vf_pf_data_reg = dpi->reg_base + DPI_MBOX_PF_VF_DATA1(vf);
+}
+
+static int dpi_pfvf_mbox_setup(struct dpipf *dpi)
+{
+ int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ dpi->mbox[vf] = devm_kzalloc(&dpi->pdev->dev, sizeof(*dpi->mbox[vf]), GFP_KERNEL);
+
+ if (!dpi->mbox[vf])
+ return -ENOMEM;
+
+ mutex_init(&dpi->mbox[vf]->lock);
+ INIT_WORK(&dpi->mbox[vf]->work, dpi_pfvf_mbox_work);
+ dpi->mbox[vf]->pf = dpi;
+ dpi_setup_mbox_regs(dpi, vf);
+ }
+
+ return 0;
+}
+
+static void dpi_pfvf_mbox_destroy(struct dpipf *dpi)
+{
+ unsigned int vf;
+
+ for (vf = 0; vf < DPI_MAX_VFS; vf++) {
+ if (work_pending(&dpi->mbox[vf]->work))
+ cancel_work_sync(&dpi->mbox[vf]->work);
+
+ dpi->mbox[vf] = NULL;
+ }
+}
+
+static void dpi_init(struct dpipf *dpi)
+{
+ unsigned int engine, port;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ if (engine == 4 || engine == 5)
+ reg = DPI_ENG_BUF_BLKS(16);
+ else
+ reg = DPI_ENG_BUF_BLKS(8);
+
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
+ }
+
+ reg = DPI_DMA_CONTROL_ZBWCSEN | DPI_DMA_CONTROL_PKT_EN | DPI_DMA_CONTROL_LDWB |
+ DPI_DMA_CONTROL_O_MODE | DPI_DMA_CONTROL_DMA_ENB;
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
+ dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
+
+ mrrs_val = 2; /* 512B */
+ mps_val = 1; /* 256B */
+
+ for (port = 0; port < DPI_EBUS_MAX_PORTS; port++) {
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(7) | DPI_EBUS_PORTX_CFG_MPS(7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
+ }
+
+ dpi_reg_write(dpi, DPI_WCTL_FIF_THR, DPI_WCTL_FIFO_THRESHOLD);
+}
+
+static void dpi_fini(struct dpipf *dpi)
+{
+ unsigned int engine;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++)
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
+
+ dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
+ dpi_reg_write(dpi, DPI_CTL, 0);
+}
+
+static void dpi_free_irq_vectors(void *pdev)
+{
+ pci_free_irq_vectors((struct pci_dev *)pdev);
+}
+
+static int dpi_irq_init(struct dpipf *dpi)
+{
+ struct pci_dev *pdev = dpi->pdev;
+ struct device *dev = &pdev->dev;
+ int i, ret;
+
+ /* Clear all RAS interrupts */
+ dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
+
+ /* Clear all RAS interrupt enable bits */
+ dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
+
+ for (i = 0; i < DPI_MAX_REQQ_INT; i++) {
+ dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
+ dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
+ }
+
+ for (i = 0; i < DPI_MAX_CC_INT; i++) {
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
+ dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
+ }
+
+ ret = pci_alloc_irq_vectors(pdev, DPI_MAX_IRQS, DPI_MAX_IRQS, PCI_IRQ_MSIX);
+ if (ret != DPI_MAX_IRQS) {
+ dev_err(dev, "DPI: Failed to alloc %d msix irqs\n", DPI_MAX_IRQS);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(dev, dpi_free_irq_vectors, pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to add irq free action\n");
+ return ret;
+ }
+
+ ret = devm_request_irq(dev, pci_irq_vector(pdev, DPI_MBOX_PF_VF_INT_IDX),
+ dpi_mbox_intr_handler, 0, "dpi-mbox", dpi);
+ if (ret) {
+ dev_err(dev, "DPI: request_irq failed for mbox; err=%d\n", ret);
+ return ret;
+ }
+
+ dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));
+
+ return 0;
+}
+
+static int dpi_mps_mrrs_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_mps_mrrs_cfg cfg;
+ u8 mrrs_val, mps_val;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_mps_mrrs_cfg)))
+ return -EFAULT;
+
+ if (cfg.max_read_req_sz < DPI_EBUS_MRRS_MIN || cfg.max_read_req_sz > DPI_EBUS_MRRS_MAX ||
+ !is_power_of_2(cfg.max_read_req_sz))
+ return -EINVAL;
+
+ if (cfg.max_payload_sz < DPI_EBUS_MPS_MIN || cfg.max_payload_sz > DPI_EBUS_MPS_MAX ||
+ !is_power_of_2(cfg.max_payload_sz))
+ return -EINVAL;
+
+ if (cfg.port >= DPI_EBUS_MAX_PORTS)
+ return -EINVAL;
+
+ mrrs_val = fls(cfg.max_read_req_sz >> 8);
+ mps_val = fls(cfg.max_payload_sz >> 8);
+
+ reg = dpi_reg_read(dpi, DPI_EBUS_PORTX_CFG(cfg.port));
+ reg &= ~(DPI_EBUS_PORTX_CFG_MRRS(0x7) | DPI_EBUS_PORTX_CFG_MPS(0x7));
+ reg |= DPI_EBUS_PORTX_CFG_MPS(mps_val) | DPI_EBUS_PORTX_CFG_MRRS(mrrs_val);
+ dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
+
+ return 0;
+}
+
+static int dpi_engine_config(struct dpipf *dpi, void __user *arg)
+{
+ struct dpi_engine_cfg cfg;
+ unsigned int engine;
+ u8 *eng_buf;
+ u64 reg;
+
+ if (copy_from_user(&cfg, arg, sizeof(struct dpi_engine_cfg)))
+ return -EFAULT;
+
+ eng_buf = (u8 *)&cfg.fifo_mask;
+
+ for (engine = 0; engine < DPI_MAX_ENGINES; engine++) {
+ if (eng_buf[engine] > DPI_MAX_ENG_FIFO_SZ)
+ return -EINVAL;
+ dpi_reg_write(dpi, DPI_ENGX_BUF(engine), eng_buf[engine]);
+
+ if (cfg.update_molr) {
+ if (cfg.molr[engine] > DPI_MAX_ENG_MOLR)
+ return -EINVAL;
+ reg = DPI_DMA_ENG_EN_MOLR(cfg.molr[engine]);
+ dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg);
+ }
+ }
+
+ return 0;
+}
+
+static long dpi_dev_ioctl(struct file *fptr, unsigned int cmd, unsigned long data)
+{
+ void __user *arg = (void __user *)data;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = container_of(fptr->private_data, struct dpipf, miscdev);
+
+ switch (cmd) {
+ case DPI_MPS_MRRS_CFG:
+ ret = dpi_mps_mrrs_config(dpi, arg);
+ break;
+ case DPI_ENGINE_CFG:
+ ret = dpi_engine_config(dpi, arg);
+ break;
+ default:
+ ret = -ENOTTY;
+ break;
+ }
+
+ return ret;
+}
+
+static const struct file_operations dpi_device_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = dpi_dev_ioctl,
+ .compat_ioctl = compat_ptr_ioctl,
+};
+
+static int dpi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct dpipf *dpi;
+ int ret;
+
+ dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi->pdev = pdev;
+
+ ret = pcim_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to enable PCI device\n");
+ return ret;
+ }
+
+ ret = pcim_iomap_regions(pdev, BIT(0) | BIT(4), KBUILD_MODNAME);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to request MMIO region\n");
+ return ret;
+ }
+
+ dpi->reg_base = pcim_iomap_table(pdev)[PCI_DPI_CFG_BAR];
+
+ /* Initialize global PF registers */
+ dpi_init(dpi);
+
+ /* Setup PF-VF mailbox */
+ ret = dpi_pfvf_mbox_setup(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to setup pf-vf mbox\n");
+ goto err_dpi_fini;
+ }
+
+ /* Register interrupts */
+ ret = dpi_irq_init(dpi);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to initialize irq vectors\n");
+ goto err_dpi_mbox_free;
+ }
+
+ pci_set_drvdata(pdev, dpi);
+ dpi->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dpi->miscdev.name = KBUILD_MODNAME;
+ dpi->miscdev.fops = &dpi_device_fops;
+ dpi->miscdev.parent = dev;
+
+ ret = misc_register(&dpi->miscdev);
+ if (ret) {
+ dev_err(dev, "DPI: Failed to register misc device\n");
+ goto err_dpi_mbox_free;
+ }
+
+ return 0;
+
+err_dpi_mbox_free:
+ dpi_pfvf_mbox_destroy(dpi);
+err_dpi_fini:
+ dpi_fini(dpi);
+ return ret;
+}
+
+static void dpi_remove(struct pci_dev *pdev)
+{
+ struct dpipf *dpi = pci_get_drvdata(pdev);
+
+ misc_deregister(&dpi->miscdev);
+ pci_sriov_configure_simple(pdev, 0);
+ dpi_pfvf_mbox_destroy(dpi);
+ dpi_fini(dpi);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id dpi_id_table[] = {
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_MRVL_CN10K_DPI_PF,
+ PCI_VENDOR_ID_CAVIUM, PCI_SUBDEVID_MRVL_CN10K_DPI_PF) },
+ { 0, } /* end of table */
+};
+
+static struct pci_driver dpi_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = dpi_id_table,
+ .probe = dpi_probe,
+ .remove = dpi_remove,
+ .sriov_configure = pci_sriov_configure_simple,
+};
+
+module_pci_driver(dpi_driver);
+MODULE_DEVICE_TABLE(pci, dpi_id_table);
+MODULE_AUTHOR("Marvell.");
+MODULE_DESCRIPTION("Marvell Octeon CN10K DPI Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/misc/mrvl_cn10k_dpi.h b/include/uapi/misc/mrvl_cn10k_dpi.h
new file mode 100644
index 000000000000..d27b1bd8cd8d
--- /dev/null
+++ b/include/uapi/misc/mrvl_cn10k_dpi.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Marvell Octeon CN10K DPI driver
+ *
+ * Copyright (C) 2024 Marvell.
+ *
+ */
+
+#ifndef __MRVL_CN10K_DPI_H__
+#define __MRVL_CN10K_DPI_H__
+
+#include <linux/types.h>
+
+#define DPI_MAX_ENGINES 6
+
+struct dpi_mps_mrrs_cfg {
+ __u16 max_read_req_sz; /* Max read request size */
+ __u16 max_payload_sz; /* Max payload size */
+ __u8 port; /* Ebus port */
+};
+
+struct dpi_engine_cfg {
+ __u64 fifo_mask; /* FIFO size mask in KBytes */
+ __u16 molr[DPI_MAX_ENGINES]; /* Max outstanding load requests */
+ __u8 update_molr; /* '1' to update engine MOLR */
+};
+
+/* DPI ioctl numbers */
+#define DPI_MAGIC_NUM 0xB8
+
+/* Set MPS & MRRS parameters */
+#define DPI_MPS_MRRS_CFG _IOW(DPI_MAGIC_NUM, 1, struct dpi_mps_mrrs_cfg)
+
+/* Set Engine FIFO configuration */
+#define DPI_ENGINE_CFG _IOW(DPI_MAGIC_NUM, 2, struct dpi_engine_cfg)
+
+#endif /* __MRVL_CN10K_DPI_H__ */
--
2.25.1
On Mon, May 20, 2024 at 04:06:30AM -0700, Vamsi Attunuru wrote:
> +union dpi_mbox_message {
> + u64 word[2];
> + struct {
> +#if defined(__BIG_ENDIAN_BITFIELD)
> + /* SSO PF function */
> + u64 sso_pf_func :16;
> + /* Aura of the command buffer */
> + u64 aura :20;
> + /* Command buffer size in 8-byte words */
> + u64 csize :16;
> + /* Command code */
> + u64 cmd :4;
> + /* VF ID to configure */
> + u64 vfid :8;
> + /* Reserved for future use */
> + u64 rsvd_85_127 :40;
> + /* Work queue completion status byte offset */
> + u64 wqecsoff :7;
> + /* Work queue completion status enable */
> + u64 wqecs :1;
> + /* NPA PF function */
> + u64 npa_pf_func :16;
> +#else
> + /* VF ID to configure */
> + u64 vfid :8;
> + /* Command code */
> + u64 cmd :4;
> + /* Command buffer size in 8-byte words */
> + u64 csize :16;
> + /* Aura of the command buffer */
> + u64 aura :20;
> + /* SSO PF function */
> + u64 sso_pf_func :16;
> + /* NPA PF function */
> + u64 npa_pf_func :16;
> + /* Work queue completion status enable */
> + u64 wqecs :1;
> + /* Work queue completion status byte offset */
> + u64 wqecsoff :7;
> + /* Reserved for future use */
> + u64 rsvd_85_127 :40;
> +#endif
> + };
> +};
The ifdef is cute, but not correct, sorry. Please use bit shifts to
handle this properly without any #ifdef needed at all.
> +
> +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64 val)
> +{
> + writeq(val, dpi->reg_base + offset);
No read needed after a write to ensure the write made it to the hardware
properly?
thanks,
greg k-h
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Tuesday, June 4, 2024 9:23 PM
> To: Vamsi Krishna Attunuru <[email protected]>
> Cc: Jerin Jacob <[email protected]>; Srujana Challa <[email protected]>;
> [email protected]; [email protected]
> Subject: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K DPI administrative driver
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
> On Mon, May 20, 2024 at 04:06:30AM -0700, Vamsi Attunuru wrote:
> > +union dpi_mbox_message {
> > + u64 word[2];
> > + struct {
> > +#if defined(__BIG_ENDIAN_BITFIELD)
> > + /* SSO PF function */
> > + u64 sso_pf_func :16;
> > + /* Aura of the command buffer */
> > + u64 aura :20;
> > + /* Command buffer size in 8-byte words */
> > + u64 csize :16;
> > + /* Command code */
> > + u64 cmd :4;
> > + /* VF ID to configure */
> > + u64 vfid :8;
> > + /* Reserved for future use */
> > + u64 rsvd_85_127 :40;
> > + /* Work queue completion status byte offset */
> > + u64 wqecsoff :7;
> > + /* Work queue completion status enable */
> > + u64 wqecs :1;
> > + /* NPA PF function */
> > + u64 npa_pf_func :16;
> > +#else
> > + /* VF ID to configure */
> > + u64 vfid :8;
> > + /* Command code */
> > + u64 cmd :4;
> > + /* Command buffer size in 8-byte words */
> > + u64 csize :16;
> > + /* Aura of the command buffer */
> > + u64 aura :20;
> > + /* SSO PF function */
> > + u64 sso_pf_func :16;
> > + /* NPA PF function */
> > + u64 npa_pf_func :16;
> > + /* Work queue completion status enable */
> > + u64 wqecs :1;
> > + /* Work queue completion status byte offset */
> > + u64 wqecsoff :7;
> > + /* Reserved for future use */
> > + u64 rsvd_85_127 :40;
> > +#endif
> > + };
> > +};
>
> The ifdef is cute, but not correct, sorry. Please use bit shifts to handle this
> properly without any #ifdef needed at all.
>
Ack, will fix it next version. Thanks for the suggestion.
>
>
>
> > +
> > +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64
> > +val) {
> > + writeq(val, dpi->reg_base + offset);
>
> No read needed after a write to ensure the write made it to the hardware
> properly?
Yes, as it's an onboard PCIe device, writes will happen properly. I will modify it as write followed by
a write barrier to avoid any reordering.
Thanks
Vamsi
>
> thanks,
>
> greg k-h
On Tue, Jun 4, 2024, at 18:21, Vamsi Krishna Attunuru wrote:
>> From: Greg KH <[email protected]>
>> > +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64
>> > +val) {
>> > + writeq(val, dpi->reg_base + offset);
>>
>> No read needed after a write to ensure the write made it to the hardware
>> properly?
>
> Yes, as it's an onboard PCIe device, writes will happen properly. I
> will modify it as write followed by
> a write barrier to avoid any reordering.
I don't think a write barrier after the I/O is what you want here,
they don't just make I/O finish before the next instruction or unlock.
When you have like
mutex_lock(&mbox->lock);
msg.word[0] = readq(mbox->vf_pf_data_reg);
...
writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
mutex_unlock(&mbox->lock);
there is no guarantee that the writeq() completes before the
mutex_unlock(), regardless of what barriers you put after it:
even if the device is synchronous, the CPU itself does not wait
for the store on device memory to complete.
If you actually need the writeq() to be serialized with
the lock, a dummy readq() is usually the safe option,
though for arm64 specific code, you can use ioremap_np()
in place of ioremap() to turn the readq() into a non-posted
store.
Arnd
> -----Original Message-----
> From: Arnd Bergmann <[email protected]>
> Sent: Wednesday, June 5, 2024 5:27 PM
> To: Vamsi Krishna Attunuru <[email protected]>; Greg Kroah-Hartman
> <[email protected]>
> Cc: Jerin Jacob <[email protected]>; Srujana Challa <[email protected]>;
> [email protected]
> Subject: Re: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add
> Octeon CN10K DPI administrative driver
>
> On Tue, Jun 4, 2024, at 18:21, Vamsi Krishna Attunuru wrote:
> >> From: Greg KH <[email protected]>
>
> >> > +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset,
> >> > +u64
> >> > +val) {
> >> > + writeq(val, dpi->reg_base + offset);
> >>
> >> No read needed after a write to ensure the write made it to the
> >> hardware properly?
> >
> > Yes, as it's an onboard PCIe device, writes will happen properly. I
> > will modify it as write followed by a write barrier to avoid any
> > reordering.
>
> I don't think a write barrier after the I/O is what you want here, they don't
> just make I/O finish before the next instruction or unlock.
>
> When you have like
>
> mutex_lock(&mbox->lock);
> msg.word[0] = readq(mbox->vf_pf_data_reg); ...
> writeq(DPI_MBOX_TYPE_RSP_ACK, mbox->pf_vf_data_reg);
> mutex_unlock(&mbox->lock);
>
> there is no guarantee that the writeq() completes before the
> mutex_unlock(), regardless of what barriers you put after it:
> even if the device is synchronous, the CPU itself does not wait for the store
> on device memory to complete.
>
> If you actually need the writeq() to be serialized with the lock, a dummy
> readq() is usually the safe option, though for arm64 specific code, you can
> use ioremap_np() in place of ioremap() to turn the readq() into a non-posted
> store.
Writeq() & readq() are already having the barriers internally (arch/arm64/include/asm/io.h). Below commit describes the requirement.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=22ec71615d824f4f11d38d0e55a88d8956b7e45f
If the driver needs to make sure writes are done then driver can read back at appropriate places.
>
> Arnd
> -----Original Message-----
> From: Vamsi Krishna Attunuru
> Sent: Tuesday, June 4, 2024 9:51 PM
> To: 'Greg KH' <[email protected]>
> Cc: Jerin Jacob <[email protected]>; Srujana Challa <[email protected]>;
> [email protected]; [email protected]
> Subject: RE: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add Octeon
> CN10K DPI administrative driver
>
>
>
> > -----Original Message-----
> > From: Greg KH <[email protected]>
> > Sent: Tuesday, June 4, 2024 9:23 PM
> > To: Vamsi Krishna Attunuru <[email protected]>
> > Cc: Jerin Jacob <[email protected]>; Srujana Challa
> > <[email protected]>; [email protected]; [email protected]
> > Subject: [EXTERNAL] Re: [PATCH v7 1/1] misc: mrvl-cn10k-dpi: add
> > Octeon CN10K DPI administrative driver
> >
> > Prioritize security for external emails: Confirm sender and content
> > safety before clicking links or opening attachments
> >
> > ----------------------------------------------------------------------
> > On Mon, May 20, 2024 at 04:06:30AM -0700, Vamsi Attunuru wrote:
> > > +union dpi_mbox_message {
> > > + u64 word[2];
> > > + struct {
> > > +#if defined(__BIG_ENDIAN_BITFIELD)
> > > + /* SSO PF function */
> > > + u64 sso_pf_func :16;
> > > + /* Aura of the command buffer */
> > > + u64 aura :20;
> > > + /* Command buffer size in 8-byte words */
> > > + u64 csize :16;
> > > + /* Command code */
> > > + u64 cmd :4;
> > > + /* VF ID to configure */
> > > + u64 vfid :8;
> > > + /* Reserved for future use */
> > > + u64 rsvd_85_127 :40;
> > > + /* Work queue completion status byte offset */
> > > + u64 wqecsoff :7;
> > > + /* Work queue completion status enable */
> > > + u64 wqecs :1;
> > > + /* NPA PF function */
> > > + u64 npa_pf_func :16;
> > > +#else
> > > + /* VF ID to configure */
> > > + u64 vfid :8;
> > > + /* Command code */
> > > + u64 cmd :4;
> > > + /* Command buffer size in 8-byte words */
> > > + u64 csize :16;
> > > + /* Aura of the command buffer */
> > > + u64 aura :20;
> > > + /* SSO PF function */
> > > + u64 sso_pf_func :16;
> > > + /* NPA PF function */
> > > + u64 npa_pf_func :16;
> > > + /* Work queue completion status enable */
> > > + u64 wqecs :1;
> > > + /* Work queue completion status byte offset */
> > > + u64 wqecsoff :7;
> > > + /* Reserved for future use */
> > > + u64 rsvd_85_127 :40;
> > > +#endif
> > > + };
> > > +};
> >
> > The ifdef is cute, but not correct, sorry. Please use bit shifts to
> > handle this properly without any #ifdef needed at all.
> >
> Ack, will fix it next version. Thanks for the suggestion.
>
Hi Greg, the ARM64 cores on the Octeon CN10K hardware platform always run in LE mode and this CN10K DPI PF driver is only supported on Octeon CN10K platforms as the DPI PF device is an onboard PCIe device. Can I remove the BE format and only define the LE format for the dpi_mbox_message structure?, other HW device drivers of Octeon CN10K platform also only support LE format.
Regards
Vamsi
> >
> >
> >
> > > +
> > > +static inline void dpi_reg_write(struct dpipf *dpi, u64 offset, u64
> > > +val) {
> > > + writeq(val, dpi->reg_base + offset);
> >
> > No read needed after a write to ensure the write made it to the
> > hardware properly?
>
> Yes, as it's an onboard PCIe device, writes will happen properly. I will modify
> it as write followed by a write barrier to avoid any reordering.
>
> Thanks
> Vamsi
> >
> > thanks,
> >
> > greg k-h
On Thu, Jun 6, 2024, at 18:42, Vamsi Krishna Attunuru wrote:
>> -----Original Message-----
>> > -----Original Message-----
>> > The ifdef is cute, but not correct, sorry. Please use bit shifts to
>> > handle this properly without any #ifdef needed at all.
>> >
>> Ack, will fix it next version. Thanks for the suggestion.
>>
>
> Hi Greg, the ARM64 cores on the Octeon CN10K hardware platform always
> run in LE mode and this CN10K DPI PF driver is only supported on Octeon
> CN10K platforms as the DPI PF device is an onboard PCIe device. Can I
> remove the BE format and only define the LE format for the
> dpi_mbox_message structure?, other HW device drivers of Octeon CN10K
> platform also only support LE format.
Isn't this a regular Neoverse-N2 core? That means the hardware does
support big-endian in principle, though it's usually only used
in VM guests, not on bare bare metal and the driver is fairly
safe.
In general, I would always suggest writing portable code, as
you never know who is going to copy from your driver into
something else. Writing this portably is not that hard or
less readable than using bit fields.
Arnd