Loongson have a long history of contributing their code to mainline kernel.
However, it seems like recent years, they are focusing on maintain a kernel by themselves
rather than contribute there code to the community.
Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
maintainance and became outdated.
This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
Loongson 2e/f alone since they are too legacy to touch.
Jiaxun Yang (13):
MIPS: Loongson64: Rename CPU TYPES
MIPS: Loongson64: Sepreate loongson2ef/loongson64 code
MAINTAINERS: Fix entries for new loongson64 path
irqchip: Add driver for Loongson-3 I/O interrupt controller
dt-bindings: interrupt-controller: Add Loongson-3 IOINTC
irqchip: Add driver for Loongson-3 HyperTransport interrupt controller
dt-bindings: interrupt-controller: Add Loongson-3 HTINTC
irqchip: i8259: Add plat-poll support
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson cpus & boards
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
.../loongson,ls3-htintc.yaml | 53 +++++
.../loongson,ls3-iointc.yaml | 61 +++++
.../bindings/mips/loongson/cpus.yaml | 38 +++
.../bindings/mips/loongson/devices.yaml | 64 ++++++
MAINTAINERS | 9 +-
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 83 +++++--
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 8 +
arch/mips/boot/dts/loongson/ls3-2nodes.dtsi | 8 +
arch/mips/boot/dts/loongson/ls3-4nodes.dtsi | 15 ++
arch/mips/boot/dts/loongson/ls3-cpus.dtsi | 150 ++++++++++++
arch/mips/boot/dts/loongson/ls3-gs464.dtsi | 18 ++
arch/mips/boot/dts/loongson/ls3-gs464e.dtsi | 18 ++
.../boot/dts/loongson/ls3-rs780e-pch.dtsi | 35 +++
arch/mips/boot/dts/loongson/ls3a-package.dtsi | 59 +++++
.../boot/dts/loongson/ls3a1000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a1000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a1000_780e_4way.dts | 13 ++
.../boot/dts/loongson/ls3a2000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a2000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a2000_780e_4way.dts | 13 ++
.../boot/dts/loongson/ls3a3000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a3000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a3000_780e_4way.dts | 13 ++
arch/mips/boot/dts/loongson/ls3b-package.dtsi | 59 +++++
.../mips/boot/dts/loongson/ls3b_780e_1way.dts | 13 ++
.../mips/boot/dts/loongson/ls3b_780e_2way.dts | 13 ++
arch/mips/include/asm/bootinfo.h | 1 -
arch/mips/include/asm/cop2.h | 2 +-
arch/mips/include/asm/cpu-type.h | 6 +-
arch/mips/include/asm/cpu.h | 4 +-
arch/mips/include/asm/hazards.h | 2 +-
arch/mips/include/asm/io.h | 2 +-
arch/mips/include/asm/irqflags.h | 2 +-
.../mach-loongson2ef/cpu-feature-overrides.h | 45 ++++
.../cs5536/cs5536.h | 0
.../cs5536/cs5536_mfgpt.h | 0
.../cs5536/cs5536_pci.h | 0
.../cs5536/cs5536_vsm.h | 0
.../loongson2ef.h} | 31 +--
.../machine.h | 6 -
.../mc146818rtc.h | 5 +-
.../mem.h | 6 +-
arch/mips/include/asm/mach-loongson2ef/pci.h | 43 ++++
.../include/asm/mach-loongson2ef/spaces.h | 10 +
.../asm/mach-loongson64/builtin_dtbs.h | 26 +++
.../mach-loongson64/cpu-feature-overrides.h | 3 -
arch/mips/include/asm/mach-loongson64/irq.h | 6 +-
.../asm/mach-loongson64/kernel-entry-init.h | 74 ------
.../include/asm/mach-loongson64/loongson64.h | 50 ++++
.../mips/include/asm/mach-loongson64/mmzone.h | 16 --
arch/mips/include/asm/mach-loongson64/pci.h | 41 +---
.../include/asm/mach-loongson64/workarounds.h | 4 +-
arch/mips/include/asm/module.h | 8 +-
arch/mips/include/asm/pgtable-bits.h | 2 +-
arch/mips/include/asm/processor.h | 2 +-
arch/mips/include/asm/r4kcache.h | 4 +-
arch/mips/kernel/cpu-probe.c | 14 +-
arch/mips/kernel/idle.c | 2 +-
arch/mips/kernel/perf_event_mipsxx.c | 4 +-
arch/mips/kernel/setup.c | 2 +-
arch/mips/kernel/traps.c | 2 +-
arch/mips/lib/csum_partial.S | 4 +-
arch/mips/loongson2ef/Kconfig | 93 ++++++++
arch/mips/loongson2ef/Makefile | 18 ++
arch/mips/loongson2ef/Platform | 32 +++
.../common/Makefile | 0
.../common/bonito-irq.c | 2 +-
.../common/cmdline.c | 2 +-
.../common/cs5536/Makefile | 0
.../common/cs5536/cs5536_acc.c | 0
.../common/cs5536/cs5536_ehci.c | 0
.../common/cs5536/cs5536_ide.c | 0
.../common/cs5536/cs5536_isa.c | 0
.../common/cs5536/cs5536_mfgpt.c | 0
.../common/cs5536/cs5536_ohci.c | 0
.../common/cs5536/cs5536_pci.c | 0
.../common/early_printk.c | 2 +-
arch/mips/loongson2ef/common/env.c | 71 ++++++
.../{loongson64 => loongson2ef}/common/init.c | 7 +-
.../{loongson64 => loongson2ef}/common/irq.c | 2 +-
.../common/machtype.c | 3 +-
.../{loongson64 => loongson2ef}/common/mem.c | 40 +---
.../{loongson64 => loongson2ef}/common/pci.c | 11 +-
.../common/platform.c | 0
.../{loongson64 => loongson2ef}/common/pm.c | 2 +-
.../common/reset.c | 23 +-
.../{loongson64 => loongson2ef}/common/rtc.c | 0
.../common/serial.c | 37 +--
.../common/setup.c | 2 +-
.../{loongson64 => loongson2ef}/common/time.c | 2 +-
.../common/uart_base.c | 10 +-
.../fuloong-2e/Makefile | 0
.../fuloong-2e/dma.c | 0
.../fuloong-2e/irq.c | 2 +-
.../fuloong-2e/reset.c | 2 +-
.../lemote-2f/Makefile | 0
.../lemote-2f/clock.c | 2 +-
.../lemote-2f/dma.c | 0
.../lemote-2f/ec_kb3310b.c | 0
.../lemote-2f/ec_kb3310b.h | 0
.../lemote-2f/irq.c | 2 +-
.../lemote-2f/machtype.c | 2 +-
.../lemote-2f/pm.c | 2 +-
.../lemote-2f/reset.c | 2 +-
arch/mips/loongson64/Kconfig | 126 +---------
arch/mips/loongson64/Makefile | 23 +-
arch/mips/loongson64/Platform | 36 +--
.../loongson64/{loongson-3 => }/acpi_init.c | 3 +-
.../loongson64/{loongson-3 => }/cop2-ex.c | 5 +-
arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +-
arch/mips/loongson64/{common => }/env.c | 139 ++++++-----
arch/mips/loongson64/{loongson-3 => }/hpet.c | 0
arch/mips/loongson64/irq.c | 27 +++
arch/mips/loongson64/loongson-3/Makefile | 11 -
arch/mips/loongson64/loongson-3/irq.c | 158 -------------
arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +-
arch/mips/loongson64/pci.c | 45 ++++
.../loongson64/{loongson-3 => }/platform.c | 0
arch/mips/loongson64/reset.c | 58 +++++
arch/mips/loongson64/setup.c | 107 +++++++++
arch/mips/loongson64/{loongson-3 => }/smp.c | 28 +--
arch/mips/loongson64/{loongson-3 => }/smp.h | 0
arch/mips/mm/c-r4k.c | 32 +--
arch/mips/mm/page.c | 2 +-
arch/mips/mm/tlb-r4k.c | 4 +-
arch/mips/mm/tlbex.c | 6 +-
arch/mips/oprofile/Makefile | 4 +-
arch/mips/oprofile/common.c | 4 +-
arch/mips/oprofile/op_model_loongson2.c | 2 +-
arch/mips/oprofile/op_model_loongson3.c | 2 +-
arch/mips/pci/Makefile | 2 +-
arch/mips/pci/fixup-fuloong2e.c | 2 +-
arch/mips/pci/fixup-lemote2f.c | 2 +-
arch/mips/pci/ops-loongson2.c | 2 +-
arch/mips/pci/ops-loongson3.c | 2 +-
drivers/cpufreq/loongson2_cpufreq.c | 2 +-
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-loongson.c | 4 +-
drivers/irqchip/Kconfig | 17 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-i8259.c | 47 +++-
drivers/irqchip/irq-ls3-htintc.c | 145 ++++++++++++
drivers/irqchip/irq-ls3-iointc.c | 216 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
drivers/platform/mips/cpu_hwmon.c | 2 +-
include/drm/drm_cache.h | 2 +-
148 files changed, 2064 insertions(+), 841 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/ls3-2nodes.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-4nodes.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-cpus.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464e.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3a-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3b-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_2way.dts
create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%)
rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%)
create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h
create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h
create mode 100644 arch/mips/loongson2ef/Kconfig
create mode 100644 arch/mips/loongson2ef/Makefile
create mode 100644 arch/mips/loongson2ef/Platform
rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%)
create mode 100644 arch/mips/loongson2ef/common/env.c
rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%)
rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%)
rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%)
rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%)
rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%)
rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%)
rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%)
rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%)
rename arch/mips/loongson64/{common => }/env.c (77%)
rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%)
create mode 100644 arch/mips/loongson64/irq.c
delete mode 100644 arch/mips/loongson64/loongson-3/Makefile
delete mode 100644 arch/mips/loongson64/loongson-3/irq.c
rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%)
create mode 100644 arch/mips/loongson64/pci.c
rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%)
create mode 100644 arch/mips/loongson64/reset.c
create mode 100644 arch/mips/loongson64/setup.c
rename arch/mips/loongson64/{loongson-3 => }/smp.c (98%)
rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%)
create mode 100644 drivers/irqchip/irq-ls3-htintc.c
create mode 100644 drivers/irqchip/irq-ls3-iointc.c
--
2.22.0
As we sepreated the code of loongson2ef/loongson3a, they can
now have their own entries.
Signed-off-by: Jiaxun Yang <[email protected]>
---
MAINTAINERS | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a2c343ee3b2c..d5d4fed632e6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10747,17 +10747,16 @@ F: arch/mips/include/asm/mach-loongson32/
F: drivers/*/*loongson1*
F: drivers/*/*/*loongson1*
-MIPS/LOONGSON2 ARCHITECTURE
+MIPS/LOONGSON2E/F ARCHITECTURE
M: Jiaxun Yang <[email protected]>
L: [email protected]
S: Maintained
-F: arch/mips/loongson64/fuloong-2e/
-F: arch/mips/loongson64/lemote-2f/
-F: arch/mips/include/asm/mach-loongson64/
+F: arch/mips/loongson2ef/
+F: arch/mips/include/asm/mach-loongson2ef/
F: drivers/*/*loongson2*
F: drivers/*/*/*loongson2*
-MIPS/LOONGSON3 ARCHITECTURE
+MIPS/LOONGSON64 ARCHITECTURE
M: Huacai Chen <[email protected]>
L: [email protected]
S: Maintained
--
2.22.0
Document Loongson-3 I/O Interrupt controller.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../loongson,ls3-iointc.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
new file mode 100644
index 000000000000..cc6ac8b2cd7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-iointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt source which can route interrupt to interrupt line of cores.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - loongson,ls3-iointc
+
+ reg:
+ maxItems: 1
+
+ 'loongson,map-ip':
+ description:
+ The interrupt line it's going to map to.
+ allOf:
+ - maximum: 5
+ minimum: 0
+
+ 'loongson,map-core':
+ description:
+ The core it's going to map to.
+ allOf:
+ - maximum: 5
+ minimum: 0
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,ls3-io-intc";
+ reg = <0x3ff01400 0x60>;
+ interrupts = <2>;
+ loongson,map-ip = <0>;
+ loongson,map-core = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
--
2.22.0
The old code is using legacy domain to setup irq_domain for CPU interrupts
which requires irq_desc being preallocated.
However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up
unallocated and lead to incorrect behavior.
Thus we convert the legacy domain to simple domain which can allocate irq_desc
during initialization.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..c3cf7fa76424 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+ irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
&mips_cpu_intc_irq_domain_ops,
NULL);
if (!irq_domain)
--
2.22.0
As later model of GSx64 family processors including 2-series-soc have
similar design with initial loongson3a while loongson2e/f seems less
identical, we seprate loongson2e/f support code out of mach-loongson64
to make our life easier.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 51 +++++--
arch/mips/include/asm/bootinfo.h | 1 -
.../mach-loongson2ef/cpu-feature-overrides.h | 45 +++++++
.../cs5536/cs5536.h | 0
.../cs5536/cs5536_mfgpt.h | 0
.../cs5536/cs5536_pci.h | 0
.../cs5536/cs5536_vsm.h | 0
.../loongson2ef.h} | 29 +---
.../machine.h | 6 -
.../mc146818rtc.h | 5 +-
.../mem.h | 6 +-
arch/mips/include/asm/mach-loongson2ef/pci.h | 43 ++++++
.../include/asm/mach-loongson2ef/spaces.h | 10 ++
.../mach-loongson64/cpu-feature-overrides.h | 3 -
arch/mips/include/asm/mach-loongson64/irq.h | 7 +-
.../asm/mach-loongson64/kernel-entry-init.h | 74 ----------
.../include/asm/mach-loongson64/loongson64.h | 48 +++++++
.../mips/include/asm/mach-loongson64/mmzone.h | 16 ---
arch/mips/include/asm/mach-loongson64/pci.h | 41 +-----
.../include/asm/mach-loongson64/workarounds.h | 4 +-
arch/mips/loongson2ef/Kconfig | 93 +++++++++++++
arch/mips/loongson2ef/Makefile | 18 +++
arch/mips/loongson2ef/Platform | 32 +++++
.../common/Makefile | 0
.../common/bonito-irq.c | 2 +-
.../common/cmdline.c | 2 +-
.../common/cs5536/Makefile | 0
.../common/cs5536/cs5536_acc.c | 0
.../common/cs5536/cs5536_ehci.c | 0
.../common/cs5536/cs5536_ide.c | 0
.../common/cs5536/cs5536_isa.c | 0
.../common/cs5536/cs5536_mfgpt.c | 0
.../common/cs5536/cs5536_ohci.c | 0
.../common/cs5536/cs5536_pci.c | 0
.../common/early_printk.c | 2 +-
arch/mips/loongson2ef/common/env.c | 71 ++++++++++
.../{loongson64 => loongson2ef}/common/init.c | 7 +-
.../{loongson64 => loongson2ef}/common/irq.c | 2 +-
.../common/machtype.c | 3 +-
.../{loongson64 => loongson2ef}/common/mem.c | 40 +-----
.../{loongson64 => loongson2ef}/common/pci.c | 11 +-
.../common/platform.c | 0
.../{loongson64 => loongson2ef}/common/pm.c | 2 +-
.../common/reset.c | 23 +---
.../{loongson64 => loongson2ef}/common/rtc.c | 0
.../common/serial.c | 37 +----
.../common/setup.c | 2 +-
.../{loongson64 => loongson2ef}/common/time.c | 2 +-
.../common/uart_base.c | 10 +-
.../fuloong-2e/Makefile | 0
.../fuloong-2e/dma.c | 0
.../fuloong-2e/irq.c | 2 +-
.../fuloong-2e/reset.c | 2 +-
.../lemote-2f/Makefile | 0
.../lemote-2f/clock.c | 2 +-
.../lemote-2f/dma.c | 0
.../lemote-2f/ec_kb3310b.c | 0
.../lemote-2f/ec_kb3310b.h | 0
.../lemote-2f/irq.c | 2 +-
.../lemote-2f/machtype.c | 2 +-
.../lemote-2f/pm.c | 2 +-
.../lemote-2f/reset.c | 2 +-
arch/mips/loongson64/Kconfig | 126 +-----------------
arch/mips/loongson64/Makefile | 23 +---
arch/mips/loongson64/Platform | 26 +---
.../loongson64/{loongson-3 => }/acpi_init.c | 3 +-
.../loongson64/{loongson-3 => }/cop2-ex.c | 5 +-
arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +-
arch/mips/loongson64/{common => }/env.c | 72 +++-------
arch/mips/loongson64/{loongson-3 => }/hpet.c | 0
arch/mips/loongson64/{loongson-3 => }/irq.c | 40 +++++-
arch/mips/loongson64/loongson-3/Makefile | 11 --
arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +-
arch/mips/loongson64/pci.c | 45 +++++++
.../loongson64/{loongson-3 => }/platform.c | 0
arch/mips/loongson64/reset.c | 58 ++++++++
arch/mips/loongson64/setup.c | 92 +++++++++++++
arch/mips/loongson64/{loongson-3 => }/smp.c | 4 +-
arch/mips/loongson64/{loongson-3 => }/smp.h | 0
arch/mips/oprofile/op_model_loongson2.c | 2 +-
arch/mips/oprofile/op_model_loongson3.c | 2 +-
arch/mips/pci/Makefile | 2 +-
arch/mips/pci/fixup-fuloong2e.c | 2 +-
arch/mips/pci/fixup-lemote2f.c | 2 +-
arch/mips/pci/ops-loongson2.c | 2 +-
arch/mips/pci/ops-loongson3.c | 2 +-
drivers/cpufreq/loongson2_cpufreq.c | 2 +-
drivers/gpio/gpio-loongson.c | 2 +-
drivers/platform/mips/cpu_hwmon.c | 2 +-
90 files changed, 720 insertions(+), 578 deletions(-)
create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%)
rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%)
create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h
create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h
delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h
create mode 100644 arch/mips/loongson2ef/Kconfig
create mode 100644 arch/mips/loongson2ef/Makefile
create mode 100644 arch/mips/loongson2ef/Platform
rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%)
create mode 100644 arch/mips/loongson2ef/common/env.c
rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%)
rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%)
rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%)
rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%)
rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%)
rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%)
rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%)
rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%)
rename arch/mips/loongson64/{common => }/env.c (79%)
rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%)
rename arch/mips/loongson64/{loongson-3 => }/irq.c (77%)
delete mode 100644 arch/mips/loongson64/loongson-3/Makefile
rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%)
create mode 100644 arch/mips/loongson64/pci.c
rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%)
create mode 100644 arch/mips/loongson64/reset.c
create mode 100644 arch/mips/loongson64/setup.c
rename arch/mips/loongson64/{loongson-3 => }/smp.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%)
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 0de839882106..7c0d461483ef 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -17,6 +17,7 @@ platforms += jazz
platforms += jz4740
platforms += lantiq
platforms += lasat
+platforms += loongson2ef
platforms += loongson32
platforms += loongson64
platforms += mti-malta
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cbc76f00d1fc..92a2ee773a40 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -445,18 +445,52 @@ config MACH_LOONGSON32
the Institute of Computing Technology (ICT), Chinese Academy of
Sciences (CAS).
+config MACH_LOONGSON2EF
+ bool "Loongson-2E/F family of machines"
+ select SYS_SUPPORTS_ZBOOT
+ help
+ This enables the support of Loongson-2E/F family of machines.
+
+ Loongson-2E/F is a family of single-core CPUs, They are 64-bit
+ general-purpose MIPS-III compatible CPUs. Loongson-2E/F are developed
+ by the Institute of Computing Technology (ICT), Chinese Academy of
+ Sciences (CAS) in the People's Republic of China.
+ The chief architect is Professor Weiwu Hu.
+
config MACH_LOONGSON64
- bool "Loongson-2/3 family of machines"
+ bool "Loongson GSx64 family of machines"
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
+ select BOOT_ELF32
+ select BOARD_SCACHE
+ select CSRC_R4K
+ select CEVT_R4K
+ select CPU_HAS_WB
+ select FORCE_PCI
+ select ISA
+ select I8259
+ select IRQ_MIPS_CPU
+ select NUMA
+ select NR_CPUS_DEFAULT_32
+ select SYS_HAS_CPU_LOONGSON64
+ select SYS_HAS_EARLY_PRINTK
+ select USE_GENERIC_EARLY_PRINTK_8250
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_HOTPLUG_CPU
+ select SYS_SUPPORTS_NUMA
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select ZONE_DMA32
select SYS_SUPPORTS_ZBOOT
help
- This enables the support of Loongson-2/3 family of machines.
+ This enables the support of Loongson-3A/3B/2-series-soc processors
- Loongson-2 is a family of single-core CPUs and Loongson-3 is a
- family of multi-core CPUs. They are both 64-bit general-purpose
- MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
- of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
- in the People's Republic of China. The chief architect is Professor
- Weiwu Hu.
+ GSx64 is a family of general-purpose MIPS64R2+ procossor featured
+ multi-core support. Their firmwares are passing parameters according
+ to uniformed "Loongson Firmware Kernel Interface Specification".
config MACH_PISTACHIO
bool "IMG Pistachio SoC based boards"
@@ -1033,6 +1067,7 @@ source "arch/mips/sibyte/Kconfig"
source "arch/mips/txx9/Kconfig"
source "arch/mips/vr41xx/Kconfig"
source "arch/mips/cavium-octeon/Kconfig"
+source "arch/mips/loongson2ef/Kconfig"
source "arch/mips/loongson32/Kconfig"
source "arch/mips/loongson64/Kconfig"
source "arch/mips/netlogic/Kconfig"
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index f711ccf7bace..6c1602af2bf4 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -70,7 +70,6 @@ enum loongson_machine_type {
MACH_DEXXON_GDIUM2F10,
MACH_LEMOTE_NAS,
MACH_LEMOTE_LL2F,
- MACH_LOONGSON_GENERIC,
MACH_LOONGSON_END
};
diff --git a/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
new file mode 100644
index 000000000000..961ce43c6c98
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2009 Wu Zhangjin <[email protected]>
+ * Copyright (C) 2009 Philippe Vachon <[email protected]>
+ * Copyright (C) 2009 Zhang Le <[email protected]>
+ *
+ * reference: /proc/cpuinfo,
+ * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
+ * arch/mips/kernel/proc.c(show_cpuinfo),
+ * loongson2f user manual.
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_32fpr 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_4kex 1
+#define cpu_has_64bits 1
+#define cpu_has_cache_cdex_p 0
+#define cpu_has_cache_cdex_s 0
+#define cpu_has_counter 1
+#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
+#define cpu_has_divec 0
+#define cpu_has_ejtag 0
+#define cpu_has_inclusive_pcaches 1
+#define cpu_has_llsc 1
+#define cpu_has_mcheck 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips16 0
+#define cpu_has_mips16e2 0
+#define cpu_has_mips3d 0
+#define cpu_has_mipsmt 0
+#define cpu_has_smartmips 0
+#define cpu_has_tlb 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_vce 0
+#define cpu_has_veic 0
+#define cpu_has_vint 0
+#define cpu_has_vtag_icache 0
+#define cpu_has_watch 1
+#define cpu_has_local_ebase 0
+
+#endif /* __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h
similarity index 100%
rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536.h
rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h
diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h
similarity index 100%
rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_mfgpt.h
rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h
diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
similarity index 100%
rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_pci.h
rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h
similarity index 100%
rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h
rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson2ef/loongson2ef.h
similarity index 91%
rename from arch/mips/include/asm/mach-loongson64/loongson.h
rename to arch/mips/include/asm/mach-loongson2ef/loongson2ef.h
index 40a24b76b874..b4524937df0e 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson2ef/loongson2ef.h
@@ -4,13 +4,12 @@
* Author: Wu Zhangjin <[email protected]>
*/
-#ifndef __ASM_MACH_LOONGSON64_LOONGSON_H
-#define __ASM_MACH_LOONGSON64_LOONGSON_H
+#ifndef __ASM_MACH_LOONGSON2EF_LOONGSON2EF_H
+#define __ASM_MACH_LOONGSON2EF_LOONGSON2EF_H
#include <linux/io.h>
#include <linux/init.h>
#include <linux/irq.h>
-#include <boot_param.h>
/* loongson internal northbridge initialization */
extern void bonito_irq_init(void);
@@ -22,7 +21,6 @@ extern void mach_prepare_shutdown(void);
/* environment arguments from bootloader */
extern u32 cpu_clock_freq;
extern u32 memsize, highmemsize;
-extern const struct plat_smp_ops loongson3_smp_ops;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
@@ -58,11 +56,6 @@ extern int mach_i8259_irq(void);
#define LOONGSON_REG(x) \
(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
-#define LOONGSON3_REG8(base, x) \
- (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
-
-#define LOONGSON3_REG32(base, x) \
- (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
#define LOONGSON_IRQ_BASE 32
#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
@@ -89,10 +82,6 @@ static inline void do_perfcnt_IRQ(void)
#define LOONGSON_REG_BASE 0x1fe00000
#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
-/* Loongson-3 specific registers */
-#define LOONGSON3_REG_BASE 0x3ff00000
-#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
-#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
#define LOONGSON_LIO1_BASE 0x1ff00000
#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
@@ -247,19 +236,9 @@ static inline void do_perfcnt_IRQ(void)
#define MAX_PACKAGES 4
/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
-extern u64 loongson_chipcfg[MAX_PACKAGES];
-#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
-
-/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
-extern u64 loongson_chiptemp[MAX_PACKAGES];
-#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
-
-/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
-extern u64 loongson_freqctrl[MAX_PACKAGES];
-#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
+#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(0xffffffffbfc00180))
/* pcimap */
-
#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
@@ -352,4 +331,4 @@ extern unsigned long _loongson_addrwincfg_base;
#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
-#endif /* __ASM_MACH_LOONGSON64_LOONGSON_H */
+#endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson64/machine.h b/arch/mips/include/asm/mach-loongson2ef/machine.h
similarity index 80%
rename from arch/mips/include/asm/mach-loongson64/machine.h
rename to arch/mips/include/asm/mach-loongson2ef/machine.h
index 8ef7ea94a26d..2a032259041d 100644
--- a/arch/mips/include/asm/mach-loongson64/machine.h
+++ b/arch/mips/include/asm/mach-loongson2ef/machine.h
@@ -20,10 +20,4 @@
#endif
-#ifdef CONFIG_LOONGSON_MACH3X
-
-#define LOONGSON_MACHTYPE MACH_LOONGSON_GENERIC
-
-#endif /* CONFIG_LOONGSON_MACH3X */
-
#endif /* __ASM_MACH_LOONGSON64_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson64/mc146818rtc.h b/arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h
similarity index 80%
rename from arch/mips/include/asm/mach-loongson64/mc146818rtc.h
rename to arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h
index ebdccfee50be..7b42c9efccc0 100644
--- a/arch/mips/include/asm/mach-loongson64/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h
@@ -1,8 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle ([email protected])
*
* RTC routines for PC style attached Dallas chip.
diff --git a/arch/mips/include/asm/mach-loongson64/mem.h b/arch/mips/include/asm/mach-loongson2ef/mem.h
similarity index 86%
rename from arch/mips/include/asm/mach-loongson64/mem.h
rename to arch/mips/include/asm/mach-loongson2ef/mem.h
index ce33c174c04d..d1d759b8974e 100644
--- a/arch/mips/include/asm/mach-loongson64/mem.h
+++ b/arch/mips/include/asm/mach-loongson2ef/mem.h
@@ -4,8 +4,8 @@
* Author: Wu Zhangjin <[email protected]>
*/
-#ifndef __ASM_MACH_LOONGSON64_MEM_H
-#define __ASM_MACH_LOONGSON64_MEM_H
+#ifndef __ASM_MACH_LOONGSON2EF_MEM_H
+#define __ASM_MACH_LOONGSON2EF_MEM_H
/*
* high memory space
@@ -34,4 +34,4 @@
#define LOONGSON_MMIO_MEM_END 0x80000000
#endif
-#endif /* __ASM_MACH_LOONGSON64_MEM_H */
+#endif /* __ASM_MACH_LOONGSON2EF_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/pci.h b/arch/mips/include/asm/mach-loongson2ef/pci.h
new file mode 100644
index 000000000000..df65d3c14896
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/pci.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2008 Zhang Le <[email protected]>
+ * Copyright (c) 2009 Wu Zhangjin <[email protected]>
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_
+#define __ASM_MACH_LOONGSON2EF_PCI_H_
+
+extern struct pci_ops loongson_pci_ops;
+
+/* this is an offset from mips_io_port_base */
+#define LOONGSON_PCI_IO_START 0x00004000UL
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/*
+ * we use address window2 to map cpu address space to pci space
+ * window2: cpu [1G, 2G] -> pci [1G, 2G]
+ * why not use window 0 & 1? because they are used by cpu when booting.
+ * window0: cpu [0, 256M] -> ddr [0, 256M]
+ * window1: cpu [256M, 512M] -> pci [256M, 512M]
+ */
+
+/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
+#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
+#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
+
+#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
+#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
+
+#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
+ LOONGSON_PCI_MEM_START + 1)
+
+#else /* loongson2f/32bit & loongson2e */
+
+/* this pci memory space is mapped by pcimap in pci.c */
+#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
+#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
+
+#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
+
+#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson2ef/spaces.h b/arch/mips/include/asm/mach-loongson2ef/spaces.h
new file mode 100644
index 000000000000..ba4e8e9b618e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/spaces.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_LOONGSON2EF_SPACES_H_
+#define __ASM_MACH_LOONGSON2EF_SPACES_H_
+
+#if defined(CONFIG_64BIT)
+#define CAC_BASE _AC(0x9800000000000000, UL)
+#endif /* CONFIG_64BIT */
+
+#include <asm/mach-generic/spaces.h>
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 153b6042e174..e70e8abc8348 100644
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -44,11 +44,8 @@
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1
#define cpu_has_local_ebase 0
-
-#ifdef CONFIG_CPU_LOONGSON64
#define cpu_has_wsbh 1
#define cpu_has_ic_fills_f_dc 1
#define cpu_hwrena_impl_bits 0xc0000000
-#endif
#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 557e069c400c..baed43285163 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -2,10 +2,9 @@
#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
#define __ASM_MACH_LOONGSON64_IRQ_H_
+#include <loongson64.h>
#include <boot_param.h>
-#ifdef CONFIG_CPU_LOONGSON64
-
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
@@ -35,10 +34,8 @@
#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
-#endif
-
extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(struct pt_regs *regs);
+extern void loongson3_ipi_interrupt(void);
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
deleted file mode 100644
index 74d94fc1ed53..000000000000
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005 Embedded Alley Solutions, Inc
- * Copyright (C) 2005 Ralf Baechle ([email protected])
- * Copyright (C) 2009 Jiajie Chen ([email protected])
- * Copyright (C) 2012 Huacai Chen ([email protected])
- */
-#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
-#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
-
-#include <asm/cpu.h>
-
-/*
- * Override macros used in arch/mips/kernel/head.S.
- */
- .macro kernel_entry_setup
-#ifdef CONFIG_CPU_LOONGSON64
- .set push
- .set mips64
- /* Set LPA on LOONGSON3 config3 */
- mfc0 t0, CP0_CONFIG3
- or t0, (0x1 << 7)
- mtc0 t0, CP0_CONFIG3
- /* Set ELPA on LOONGSON3 pagegrain */
- mfc0 t0, CP0_PAGEGRAIN
- or t0, (0x1 << 29)
- mtc0 t0, CP0_PAGEGRAIN
- /* Enable STFill Buffer */
- mfc0 t0, CP0_PRID
- andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
- slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)
- bnez t0, 1f
- mfc0 t0, CP0_CONFIG6
- or t0, 0x100
- mtc0 t0, CP0_CONFIG6
-1:
- _ehb
- .set pop
-#endif
- .endm
-
-/*
- * Do SMP slave processor setup.
- */
- .macro smp_slave_setup
-#ifdef CONFIG_CPU_LOONGSON64
- .set push
- .set mips64
- /* Set LPA on LOONGSON3 config3 */
- mfc0 t0, CP0_CONFIG3
- or t0, (0x1 << 7)
- mtc0 t0, CP0_CONFIG3
- /* Set ELPA on LOONGSON3 pagegrain */
- mfc0 t0, CP0_PAGEGRAIN
- or t0, (0x1 << 29)
- mtc0 t0, CP0_PAGEGRAIN
- /* Enable STFill Buffer */
- mfc0 t0, CP0_PRID
- andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
- slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)
- bnez t0, 1f
- mfc0 t0, CP0_CONFIG6
- or t0, 0x100
- mtc0 t0, CP0_CONFIG6
-1:
- _ehb
- .set pop
-#endif
- .endm
-
-#endif /* __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-loongson64/loongson64.h b/arch/mips/include/asm/mach-loongson64/loongson64.h
new file mode 100644
index 000000000000..d877adb99d33
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/loongson64.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Generic definitions for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_LOONGSON64_H
+#define __ASM_MACH_LOONGSON64_LOONGSON64_H
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#define MAX_PACKAGES 4
+
+#define LOONGSON_REG_BASE 0x1fe00000
+#define LOONGSON_REGBASE 0x100
+
+#define LOONGSON3_REG_BASE 0x3ff00000
+#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
+
+#define LOONGSON_REG(x) \
+ (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+
+#define LOONGSON3_REG8(base, x) \
+ (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
+
+#define LOONGSON3_REG32(base, x) \
+ (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))/* Loongson-3 specific registers */
+
+#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
+
+/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
+extern u64 loongson_chipcfg[MAX_PACKAGES];
+#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
+
+/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
+extern u64 loongson_chiptemp[MAX_PACKAGES];
+#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
+
+/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
+extern u64 loongson_freqctrl[MAX_PACKAGES];
+#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
+
+extern const struct plat_smp_ops loongson3_smp_ops;
+extern void __init prom_init_lefi(void);
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/mmzone.h b/arch/mips/include/asm/mach-loongson64/mmzone.h
index 62073d60739f..eec8057d3ec9 100644
--- a/arch/mips/include/asm/mach-loongson64/mmzone.h
+++ b/arch/mips/include/asm/mach-loongson64/mmzone.h
@@ -19,30 +19,14 @@
#define pa_to_nid(addr) (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT)
#define nid_to_addrbase(nid) ((nid) << NODE_ADDRSPACE_SHIFT)
-#define LEVELS_PER_SLICE 128
-
-struct slice_data {
- unsigned long irq_enable_mask[2];
- int level_to_irq[LEVELS_PER_SLICE];
-};
-
-struct hub_data {
- cpumask_t h_cpus;
- unsigned long slice_map;
- unsigned long irq_alloc_mask[2];
- struct slice_data slice[2];
-};
-
struct node_data {
struct pglist_data pglist;
- struct hub_data hub;
cpumask_t cpumask;
};
extern struct node_data *__node_data[];
#define NODE_DATA(n) (&__node_data[(n)]->pglist)
-#define hub_data(n) (&__node_data[(n)]->hub)
extern void setup_zero_pages(void);
extern void __init prom_init_numa_memory(void);
diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h
index 05cc9052772f..a30024499590 100644
--- a/arch/mips/include/asm/mach-loongson64/pci.h
+++ b/arch/mips/include/asm/mach-loongson64/pci.h
@@ -4,47 +4,12 @@
* Copyright (c) 2009 Wu Zhangjin <[email protected]>
*/
-#ifndef __ASM_MACH_LOONGSON64_PCI_H_
-#define __ASM_MACH_LOONGSON64_PCI_H_
+#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_
+#define __ASM_MACH_LOONGSON2EF_PCI_H_
extern struct pci_ops loongson_pci_ops;
-/* this is an offset from mips_io_port_base */
-#define LOONGSON_PCI_IO_START 0x00004000UL
-
-#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
-
-/*
- * we use address window2 to map cpu address space to pci space
- * window2: cpu [1G, 2G] -> pci [1G, 2G]
- * why not use window 0 & 1? because they are used by cpu when booting.
- * window0: cpu [0, 256M] -> ddr [0, 256M]
- * window1: cpu [256M, 512M] -> pci [256M, 512M]
- */
-
-/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
-#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
-#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
-
-#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
-#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
-
-#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
- LOONGSON_PCI_MEM_START + 1)
-
-#else /* loongson2f/32bit & loongson2e */
-
-/* this pci memory space is mapped by pcimap in pci.c */
-#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_PCI_MEM_START 0x40000000UL
#define LOONGSON_PCI_MEM_END 0x7effffffUL
-#else
-#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
-#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
-#endif
-/* this is an offset from mips_io_port_base */
-#define LOONGSON_PCI_IO_START 0x00004000UL
-
-#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
-#endif /* !__ASM_MACH_LOONGSON64_PCI_H_ */
+#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson64/workarounds.h b/arch/mips/include/asm/mach-loongson64/workarounds.h
index 17b71172a097..e30415bef7b7 100644
--- a/arch/mips/include/asm/mach-loongson64/workarounds.h
+++ b/arch/mips/include/asm/mach-loongson64/workarounds.h
@@ -2,7 +2,7 @@
#ifndef __ASM_MACH_LOONGSON64_WORKAROUNDS_H_
#define __ASM_MACH_LOONGSON64_WORKAROUNDS_H_
-#define WORKAROUND_CPUFREQ 0x00000001
-#define WORKAROUND_CPUHOTPLUG 0x00000002
+#define WORKAROUND_CPUFREQ BIT(1)
+#define WORKAROUND_CPUHOTPLUG BIT(2)
#endif
diff --git a/arch/mips/loongson2ef/Kconfig b/arch/mips/loongson2ef/Kconfig
new file mode 100644
index 000000000000..cb2f523d9e30
--- /dev/null
+++ b/arch/mips/loongson2ef/Kconfig
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0
+if MACH_LOONGSON2EF
+
+choice
+ prompt "Machine Type"
+
+config LEMOTE_FULOONG2E
+ bool "Lemote Fuloong(2e) mini-PC"
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
+ select CEVT_R4K
+ select CSRC_R4K
+ select SYS_HAS_CPU_LOONGSON2E
+ select DMA_NONCOHERENT
+ select BOOT_ELF32
+ select BOARD_SCACHE
+ select HAVE_PCI
+ select I8259
+ select ISA
+ select IRQ_MIPS_CPU
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_HAS_EARLY_PRINTK
+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
+ select CPU_HAS_WB
+ select LOONGSON_MC146818
+ help
+ Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
+ an FPGA northbridge
+
+ Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
+
+config LEMOTE_MACH2F
+ bool "Lemote Loongson 2F family machines"
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
+ select BOARD_SCACHE
+ select BOOT_ELF32
+ select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
+ select CPU_HAS_WB
+ select CS5536
+ select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
+ select DMA_NONCOHERENT
+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
+ select HAVE_CLK
+ select HAVE_PCI
+ select I8259
+ select IRQ_MIPS_CPU
+ select ISA
+ select SYS_HAS_CPU_LOONGSON2F
+ select SYS_HAS_EARLY_PRINTK
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select LOONGSON_MC146818
+ help
+ Lemote Loongson 2F family machines utilize the 2F revision of
+ Loongson processor and the AMD CS5536 south bridge.
+
+ These family machines include fuloong2f mini PC, yeeloong2f notebook,
+ LingLoong allinone PC and so forth.
+
+endchoice
+
+config CS5536
+ bool
+
+config CS5536_MFGPT
+ bool "CS5536 MFGPT Timer"
+ depends on CS5536 && !HIGH_RES_TIMERS
+ select MIPS_EXTERNAL_TIMER
+ help
+ This option enables the mfgpt0 timer of AMD CS5536. With this timer
+ switched on you can not use high resolution timers.
+
+ If you want to enable the Loongson2 CPUFreq Driver, Please enable
+ this option at first, otherwise, You will get wrong system time.
+
+ If unsure, say Yes.
+
+config LOONGSON_UART_BASE
+ bool
+ default y
+ depends on EARLY_PRINTK || SERIAL_8250
+
+config LOONGSON_MC146818
+ bool
+ default n
+
+endif # MACH_LOONGSON2EF
diff --git a/arch/mips/loongson2ef/Makefile b/arch/mips/loongson2ef/Makefile
new file mode 100644
index 000000000000..0535d244d75b
--- /dev/null
+++ b/arch/mips/loongson2ef/Makefile
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Common code for all Loongson based systems
+#
+
+obj-y += common/
+
+#
+# Lemote Fuloong mini-PC (Loongson 2E-based)
+#
+
+obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
+
+#
+# Lemote loongson2f family machines
+#
+
+obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
diff --git a/arch/mips/loongson2ef/Platform b/arch/mips/loongson2ef/Platform
new file mode 100644
index 000000000000..3aca42963f35
--- /dev/null
+++ b/arch/mips/loongson2ef/Platform
@@ -0,0 +1,32 @@
+#
+# Loongson Processors' Support
+#
+
+# Only gcc >= 4.4 have Loongson specific support
+cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2E) += \
+ $(call cc-option,-march=loongson2e,-march=r4600)
+cflags-$(CONFIG_CPU_LOONGSON2F) += \
+ $(call cc-option,-march=loongson2f,-march=r4600)
+# Enable the workarounds for Loongson2f
+ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
+ ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
+ $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
+ else
+ cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
+ endif
+ ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
+ $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
+ else
+ cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
+ endif
+endif
+
+#
+# Loongson Machines' Support
+#
+
+platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/
+cflags-$(CONFIG_MACH_LOONGSON2EF) += -I$(srctree)/arch/mips/include/asm/mach-loongson2ef -mno-branch-likely
+load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
+load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
diff --git a/arch/mips/loongson64/common/Makefile b/arch/mips/loongson2ef/common/Makefile
similarity index 100%
rename from arch/mips/loongson64/common/Makefile
rename to arch/mips/loongson2ef/common/Makefile
diff --git a/arch/mips/loongson64/common/bonito-irq.c b/arch/mips/loongson2ef/common/bonito-irq.c
similarity index 97%
rename from arch/mips/loongson64/common/bonito-irq.c
rename to arch/mips/loongson2ef/common/bonito-irq.c
index 82352cc25e4c..e59248c53bc5 100644
--- a/arch/mips/loongson64/common/bonito-irq.c
+++ b/arch/mips/loongson2ef/common/bonito-irq.c
@@ -10,7 +10,7 @@
#include <linux/interrupt.h>
#include <linux/compiler.h>
-#include <loongson.h>
+#include <loongson2ef.h>
static inline void bonito_irq_enable(struct irq_data *d)
{
diff --git a/arch/mips/loongson64/common/cmdline.c b/arch/mips/loongson2ef/common/cmdline.c
similarity index 97%
rename from arch/mips/loongson64/common/cmdline.c
rename to arch/mips/loongson2ef/common/cmdline.c
index a735460682cf..ab126a7cefdc 100644
--- a/arch/mips/loongson64/common/cmdline.c
+++ b/arch/mips/loongson2ef/common/cmdline.c
@@ -15,7 +15,7 @@
*/
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
void __init prom_init_cmdline(void)
{
diff --git a/arch/mips/loongson64/common/cs5536/Makefile b/arch/mips/loongson2ef/common/cs5536/Makefile
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/Makefile
rename to arch/mips/loongson2ef/common/cs5536/Makefile
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_acc.c b/arch/mips/loongson2ef/common/cs5536/cs5536_acc.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_acc.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_acc.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ehci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ehci.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_ehci.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_ehci.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ide.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ide.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_ide.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_ide.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_isa.c b/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_isa.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_isa.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ohci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ohci.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_ohci.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_ohci.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_pci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_pci.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_pci.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_pci.c
diff --git a/arch/mips/loongson64/common/early_printk.c b/arch/mips/loongson2ef/common/early_printk.c
similarity index 97%
rename from arch/mips/loongson64/common/early_printk.c
rename to arch/mips/loongson2ef/common/early_printk.c
index 5e2a151aa30c..e22d16728e13 100644
--- a/arch/mips/loongson64/common/early_printk.c
+++ b/arch/mips/loongson2ef/common/early_printk.c
@@ -8,7 +8,7 @@
#include <linux/serial_reg.h>
#include <asm/setup.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#define PORT(base, offset) (u8 *)(base + offset)
diff --git a/arch/mips/loongson2ef/common/env.c b/arch/mips/loongson2ef/common/env.c
new file mode 100644
index 000000000000..03a8d0165d2e
--- /dev/null
+++ b/arch/mips/loongson2ef/common/env.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Based on Ocelot Linux port, which is
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: [email protected] or [email protected]
+ *
+ * Copyright 2003 ICT CAS
+ * Author: Michael Guo <[email protected]>
+ *
+ * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, [email protected]
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, [email protected]
+ */
+#include <linux/export.h>
+#include <asm/bootinfo.h>
+#include <loongson2ef.h>
+
+u32 cpu_clock_freq;
+EXPORT_SYMBOL(cpu_clock_freq);
+
+unsigned long long smp_group[4];
+
+#define parse_even_earlier(res, option, p) \
+do { \
+ unsigned int tmp __maybe_unused; \
+ \
+ if (strncmp(option, (char *)p, strlen(option)) == 0) \
+ tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \
+} while (0)
+
+void __init prom_init_env(void)
+{
+ /* pmon passes arguments in 32bit pointers */
+ unsigned int processor_id;
+ int *_prom_envp;
+ long l;
+
+ /* firmware arguments are initialized in head.S */
+ _prom_envp = (int *)fw_arg2;
+
+ l = (long)*_prom_envp;
+ while (l != 0) {
+ parse_even_earlier(cpu_clock_freq, "cpuclock", l);
+ parse_even_earlier(memsize, "memsize", l);
+ parse_even_earlier(highmemsize, "highmemsize", l);
+ _prom_envp++;
+ l = (long)*_prom_envp;
+ }
+ if (memsize == 0)
+ memsize = 256;
+
+ pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize);
+
+ if (cpu_clock_freq == 0) {
+ processor_id = (¤t_cpu_data)->processor_id;
+ switch (processor_id & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON2E:
+ cpu_clock_freq = 533080000;
+ break;
+ case PRID_REV_LOONGSON2F:
+ cpu_clock_freq = 797000000;
+ break;
+ default:
+ cpu_clock_freq = 100000000;
+ break;
+ }
+ }
+ pr_info("CpuClock = %u\n", cpu_clock_freq);
+}
diff --git a/arch/mips/loongson64/common/init.c b/arch/mips/loongson2ef/common/init.c
similarity index 90%
rename from arch/mips/loongson64/common/init.c
rename to arch/mips/loongson2ef/common/init.c
index 912fe61c4fc7..b65763818911 100644
--- a/arch/mips/loongson64/common/init.c
+++ b/arch/mips/loongson2ef/common/init.c
@@ -10,7 +10,7 @@
#include <asm/smp-ops.h>
#include <asm/cacheflush.h>
-#include <loongson.h>
+#include <loongson2ef.h>
/* Loongson CPU address windows config space base address */
unsigned long __maybe_unused _loongson_addrwincfg_base;
@@ -39,15 +39,10 @@ void __init prom_init(void)
set_io_port_base((unsigned long)
ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
-#ifdef CONFIG_NUMA
- prom_init_numa_memory();
-#else
prom_init_memory();
-#endif
/*init the uart base address */
prom_init_uart_base();
- register_smp_ops(&loongson3_smp_ops);
board_nmi_handler_setup = mips_nmi_setup;
}
diff --git a/arch/mips/loongson64/common/irq.c b/arch/mips/loongson2ef/common/irq.c
similarity index 98%
rename from arch/mips/loongson64/common/irq.c
rename to arch/mips/loongson2ef/common/irq.c
index 0ea93c1c0a97..96d492511e41 100644
--- a/arch/mips/loongson64/common/irq.c
+++ b/arch/mips/loongson2ef/common/irq.c
@@ -6,7 +6,7 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
-#include <loongson.h>
+#include <loongson2ef.h>
/*
* the first level int-handler will jump here if it is a bonito irq
*/
diff --git a/arch/mips/loongson64/common/machtype.c b/arch/mips/loongson2ef/common/machtype.c
similarity index 94%
rename from arch/mips/loongson64/common/machtype.c
rename to arch/mips/loongson2ef/common/machtype.c
index 4e42d929f1c7..d2ea4d25246a 100644
--- a/arch/mips/loongson64/common/machtype.c
+++ b/arch/mips/loongson2ef/common/machtype.c
@@ -8,7 +8,7 @@
#include <linux/errno.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <machine.h>
/* please ensure the length of the machtype string is less than 50 */
@@ -23,7 +23,6 @@ static const char *system_types[] = {
[MACH_DEXXON_GDIUM2F10] = "dexxon-gdium-2f",
[MACH_LEMOTE_NAS] = "lemote-nas-2f",
[MACH_LEMOTE_LL2F] = "lemote-lynloong-2f",
- [MACH_LOONGSON_GENERIC] = "generic-loongson-machine",
[MACH_LOONGSON_END] = NULL,
};
diff --git a/arch/mips/loongson64/common/mem.c b/arch/mips/loongson2ef/common/mem.c
similarity index 72%
rename from arch/mips/loongson64/common/mem.c
rename to arch/mips/loongson2ef/common/mem.c
index 4abb92e0fc39..c90beb048233 100644
--- a/arch/mips/loongson64/common/mem.c
+++ b/arch/mips/loongson2ef/common/mem.c
@@ -7,12 +7,10 @@
#include <asm/bootinfo.h>
-#include <loongson.h>
-#include <boot_param.h>
+#include <loongson2ef.h>
#include <mem.h>
#include <pci.h>
-#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
u32 memsize, highmemsize;
@@ -51,42 +49,6 @@ void __init prom_init_memory(void)
#endif /* !CONFIG_64BIT */
}
-#else /* CONFIG_LEFI_FIRMWARE_INTERFACE */
-
-void __init prom_init_memory(void)
-{
- int i;
- u32 node_id;
- u32 mem_type;
-
- /* parse memory information */
- for (i = 0; i < loongson_memmap->nr_map; i++) {
- node_id = loongson_memmap->map[i].node_id;
- mem_type = loongson_memmap->map[i].mem_type;
-
- if (node_id == 0) {
- switch (mem_type) {
- case SYSTEM_RAM_LOW:
- add_memory_region(loongson_memmap->map[i].mem_start,
- (u64)loongson_memmap->map[i].mem_size << 20,
- BOOT_MEM_RAM);
- break;
- case SYSTEM_RAM_HIGH:
- add_memory_region(loongson_memmap->map[i].mem_start,
- (u64)loongson_memmap->map[i].mem_size << 20,
- BOOT_MEM_RAM);
- break;
- case SYSTEM_RAM_RESERVED:
- add_memory_region(loongson_memmap->map[i].mem_start,
- (u64)loongson_memmap->map[i].mem_size << 20,
- BOOT_MEM_RESERVED);
- break;
- }
- }
- }
-}
-
-#endif /* CONFIG_LEFI_FIRMWARE_INTERFACE */
/* override of arch/mips/mm/cache.c: __uncached_access */
int __uncached_access(struct file *file, unsigned long addr)
diff --git a/arch/mips/loongson64/common/pci.c b/arch/mips/loongson2ef/common/pci.c
similarity index 89%
rename from arch/mips/loongson64/common/pci.c
rename to arch/mips/loongson2ef/common/pci.c
index 2d9755c49524..3df8d1695243 100644
--- a/arch/mips/loongson64/common/pci.c
+++ b/arch/mips/loongson2ef/common/pci.c
@@ -6,8 +6,7 @@
#include <linux/pci.h>
#include <pci.h>
-#include <loongson.h>
-#include <boot_param.h>
+#include <loongson2ef.h>
static struct resource loongson_pci_mem_resource = {
.name = "pci memory space",
@@ -81,16 +80,8 @@ static int __init pcibios_init(void)
setup_pcimap();
loongson_pci_controller.io_map_base = mips_io_port_base;
-#ifdef CONFIG_LEFI_FIRMWARE_INTERFACE
- loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
- loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
-#endif
register_pci_controller(&loongson_pci_controller);
-#ifdef CONFIG_CPU_LOONGSON64
- sbx00_acpi_init();
-#endif
-
return 0;
}
diff --git a/arch/mips/loongson64/common/platform.c b/arch/mips/loongson2ef/common/platform.c
similarity index 100%
rename from arch/mips/loongson64/common/platform.c
rename to arch/mips/loongson2ef/common/platform.c
diff --git a/arch/mips/loongson64/common/pm.c b/arch/mips/loongson2ef/common/pm.c
similarity index 99%
rename from arch/mips/loongson64/common/pm.c
rename to arch/mips/loongson2ef/common/pm.c
index b8aed878d912..0e3c9f245215 100644
--- a/arch/mips/loongson64/common/pm.c
+++ b/arch/mips/loongson2ef/common/pm.c
@@ -12,7 +12,7 @@
#include <asm/i8259.h>
#include <asm/mipsregs.h>
-#include <loongson.h>
+#include <loongson2ef.h>
static unsigned int __maybe_unused cached_master_mask; /* i8259A */
static unsigned int __maybe_unused cached_slave_mask;
diff --git a/arch/mips/loongson64/common/reset.c b/arch/mips/loongson2ef/common/reset.c
similarity index 77%
rename from arch/mips/loongson64/common/reset.c
rename to arch/mips/loongson2ef/common/reset.c
index ce39e918e4d5..fc296ac979c6 100644
--- a/arch/mips/loongson64/common/reset.c
+++ b/arch/mips/loongson2ef/common/reset.c
@@ -12,8 +12,7 @@
#include <asm/idle.h>
#include <asm/reboot.h>
-#include <loongson.h>
-#include <boot_param.h>
+#include <loongson2ef.h>
static inline void loongson_reboot(void)
{
@@ -35,26 +34,15 @@ static inline void loongson_reboot(void)
static void loongson_restart(char *command)
{
-#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
/* do preparation for reboot */
mach_prepare_reboot();
/* reboot via jumping to boot base address */
loongson_reboot();
-#else
- void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr;
-
- fw_restart();
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
-#endif
}
static void loongson_poweroff(void)
{
-#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
mach_prepare_shutdown();
/*
@@ -62,15 +50,6 @@ static void loongson_poweroff(void)
* a generic delay loop, machine_hang(), so simply return.
*/
return;
-#else
- void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr;
-
- fw_poweroff();
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
-#endif
}
static void loongson_halt(void)
diff --git a/arch/mips/loongson64/common/rtc.c b/arch/mips/loongson2ef/common/rtc.c
similarity index 100%
rename from arch/mips/loongson64/common/rtc.c
rename to arch/mips/loongson2ef/common/rtc.c
diff --git a/arch/mips/loongson64/common/serial.c b/arch/mips/loongson2ef/common/serial.c
similarity index 63%
rename from arch/mips/loongson64/common/serial.c
rename to arch/mips/loongson2ef/common/serial.c
index ffefc1cb2612..4203486b1570 100644
--- a/arch/mips/loongson64/common/serial.c
+++ b/arch/mips/loongson2ef/common/serial.c
@@ -16,7 +16,7 @@
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <machine.h>
#define PORT(int, clk) \
@@ -38,7 +38,7 @@
.regshift = 0, \
}
-static struct plat_serial8250_port uart8250_data[][MAX_UARTS + 1] = {
+static struct plat_serial8250_port uart8250_data[][16] = {
[MACH_LOONGSON_UNKNOWN] = {},
[MACH_LEMOTE_FL2E] = {PORT(4, 1843200), {} },
[MACH_LEMOTE_FL2F] = {PORT(3, 1843200), {} },
@@ -47,7 +47,6 @@ static struct plat_serial8250_port uart8250_data[][MAX_UARTS + 1] = {
[MACH_DEXXON_GDIUM2F10] = {PORT_M(3, 3686400), {} },
[MACH_LEMOTE_NAS] = {PORT_M(3, 3686400), {} },
[MACH_LEMOTE_LL2F] = {PORT(3, 1843200), {} },
- [MACH_LOONGSON_GENERIC] = {PORT_M(2, 25000000), {} },
[MACH_LOONGSON_END] = {},
};
@@ -58,7 +57,6 @@ static struct platform_device uart8250_device = {
static int __init serial_init(void)
{
- int i;
unsigned char iotype;
iotype = uart8250_data[mips_machtype][0].iotype;
@@ -73,36 +71,7 @@ static int __init serial_init(void)
uart8250_data[mips_machtype][0].iobase =
loongson_uart_base[0] - LOONGSON_PCIIO_BASE;
- if (loongson_sysconf.uarts[0].uartclk)
- uart8250_data[mips_machtype][0].uartclk =
- loongson_sysconf.uarts[0].uartclk;
-
- for (i = 1; i < loongson_sysconf.nr_uarts; i++) {
- iotype = loongson_sysconf.uarts[i].iotype;
- uart8250_data[mips_machtype][i].iotype = iotype;
- loongson_uart_base[i] = loongson_sysconf.uarts[i].uart_base;
-
- if (UPIO_MEM == iotype) {
- uart8250_data[mips_machtype][i].irq =
- MIPS_CPU_IRQ_BASE + loongson_sysconf.uarts[i].int_offset;
- uart8250_data[mips_machtype][i].mapbase =
- loongson_uart_base[i];
- uart8250_data[mips_machtype][i].membase =
- ioremap_nocache(loongson_uart_base[i], 8);
- } else if (UPIO_PORT == iotype) {
- uart8250_data[mips_machtype][i].irq =
- loongson_sysconf.uarts[i].int_offset;
- uart8250_data[mips_machtype][i].iobase =
- loongson_uart_base[i] - LOONGSON_PCIIO_BASE;
- }
-
- uart8250_data[mips_machtype][i].uartclk =
- loongson_sysconf.uarts[i].uartclk;
- uart8250_data[mips_machtype][i].flags =
- UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- }
-
- memset(&uart8250_data[mips_machtype][loongson_sysconf.nr_uarts],
+ memset(&uart8250_data[mips_machtype][1],
0, sizeof(struct plat_serial8250_port));
uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
diff --git a/arch/mips/loongson64/common/setup.c b/arch/mips/loongson2ef/common/setup.c
similarity index 97%
rename from arch/mips/loongson64/common/setup.c
rename to arch/mips/loongson2ef/common/setup.c
index bc2da4c140c4..278d2b62d9a6 100644
--- a/arch/mips/loongson64/common/setup.c
+++ b/arch/mips/loongson2ef/common/setup.c
@@ -9,7 +9,7 @@
#include <asm/wbflush.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#ifdef CONFIG_VT
#include <linux/console.h>
diff --git a/arch/mips/loongson64/common/time.c b/arch/mips/loongson2ef/common/time.c
similarity index 96%
rename from arch/mips/loongson64/common/time.c
rename to arch/mips/loongson2ef/common/time.c
index e78760ce475b..b29f89a9db8e 100644
--- a/arch/mips/loongson64/common/time.c
+++ b/arch/mips/loongson2ef/common/time.c
@@ -10,7 +10,7 @@
#include <asm/time.h>
#include <asm/hpet.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <cs5536/cs5536_mfgpt.h>
void __init plat_time_init(void)
diff --git a/arch/mips/loongson64/common/uart_base.c b/arch/mips/loongson2ef/common/uart_base.c
similarity index 77%
rename from arch/mips/loongson64/common/uart_base.c
rename to arch/mips/loongson2ef/common/uart_base.c
index e88d937f10fe..27d073f1cd48 100644
--- a/arch/mips/loongson64/common/uart_base.c
+++ b/arch/mips/loongson2ef/common/uart_base.c
@@ -7,12 +7,12 @@
#include <linux/export.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
/* raw */
-unsigned long loongson_uart_base[MAX_UARTS] = {};
+unsigned long loongson_uart_base[16] = {};
/* ioremapped */
-unsigned long _loongson_uart_base[MAX_UARTS] = {};
+unsigned long _loongson_uart_base[16] = {};
EXPORT_SYMBOL(loongson_uart_base);
EXPORT_SYMBOL(_loongson_uart_base);
@@ -20,10 +20,6 @@ EXPORT_SYMBOL(_loongson_uart_base);
void prom_init_loongson_uart_base(void)
{
switch (mips_machtype) {
- case MACH_LOONGSON_GENERIC:
- /* The CPU provided serial port (CPU) */
- loongson_uart_base[0] = LOONGSON_REG_BASE + 0x1e0;
- break;
case MACH_LEMOTE_FL2E:
loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x3f8;
break;
diff --git a/arch/mips/loongson64/fuloong-2e/Makefile b/arch/mips/loongson2ef/fuloong-2e/Makefile
similarity index 100%
rename from arch/mips/loongson64/fuloong-2e/Makefile
rename to arch/mips/loongson2ef/fuloong-2e/Makefile
diff --git a/arch/mips/loongson64/fuloong-2e/dma.c b/arch/mips/loongson2ef/fuloong-2e/dma.c
similarity index 100%
rename from arch/mips/loongson64/fuloong-2e/dma.c
rename to arch/mips/loongson2ef/fuloong-2e/dma.c
diff --git a/arch/mips/loongson64/fuloong-2e/irq.c b/arch/mips/loongson2ef/fuloong-2e/irq.c
similarity index 98%
rename from arch/mips/loongson64/fuloong-2e/irq.c
rename to arch/mips/loongson2ef/fuloong-2e/irq.c
index 32278e7bf85c..caaf9e907dd2 100644
--- a/arch/mips/loongson64/fuloong-2e/irq.c
+++ b/arch/mips/loongson2ef/fuloong-2e/irq.c
@@ -8,7 +8,7 @@
#include <asm/irq_cpu.h>
#include <asm/i8259.h>
-#include <loongson.h>
+#include <loongson2ef.h>
static void i8259_irqdispatch(void)
{
diff --git a/arch/mips/loongson64/fuloong-2e/reset.c b/arch/mips/loongson2ef/fuloong-2e/reset.c
similarity index 93%
rename from arch/mips/loongson64/fuloong-2e/reset.c
rename to arch/mips/loongson2ef/fuloong-2e/reset.c
index 8273de1cf4bb..df60685d0626 100644
--- a/arch/mips/loongson64/fuloong-2e/reset.c
+++ b/arch/mips/loongson2ef/fuloong-2e/reset.c
@@ -6,7 +6,7 @@
* Author: Wu Zhangjin, [email protected]
*/
-#include <loongson.h>
+#include <loongson2ef.h>
void mach_prepare_reboot(void)
{
diff --git a/arch/mips/loongson64/lemote-2f/Makefile b/arch/mips/loongson2ef/lemote-2f/Makefile
similarity index 100%
rename from arch/mips/loongson64/lemote-2f/Makefile
rename to arch/mips/loongson2ef/lemote-2f/Makefile
diff --git a/arch/mips/loongson64/lemote-2f/clock.c b/arch/mips/loongson2ef/lemote-2f/clock.c
similarity index 98%
rename from arch/mips/loongson64/lemote-2f/clock.c
rename to arch/mips/loongson2ef/lemote-2f/clock.c
index 8281334df9c8..83f7b9cabcd1 100644
--- a/arch/mips/loongson64/lemote-2f/clock.c
+++ b/arch/mips/loongson2ef/lemote-2f/clock.c
@@ -15,7 +15,7 @@
#include <linux/spinlock.h>
#include <asm/clock.h>
-#include <asm/mach-loongson64/loongson.h>
+#include <asm/mach-loongson2ef/loongson2ef.h>
static LIST_HEAD(clock_list);
static DEFINE_SPINLOCK(clock_lock);
diff --git a/arch/mips/loongson64/lemote-2f/dma.c b/arch/mips/loongson2ef/lemote-2f/dma.c
similarity index 100%
rename from arch/mips/loongson64/lemote-2f/dma.c
rename to arch/mips/loongson2ef/lemote-2f/dma.c
diff --git a/arch/mips/loongson64/lemote-2f/ec_kb3310b.c b/arch/mips/loongson2ef/lemote-2f/ec_kb3310b.c
similarity index 100%
rename from arch/mips/loongson64/lemote-2f/ec_kb3310b.c
rename to arch/mips/loongson2ef/lemote-2f/ec_kb3310b.c
diff --git a/arch/mips/loongson64/lemote-2f/ec_kb3310b.h b/arch/mips/loongson2ef/lemote-2f/ec_kb3310b.h
similarity index 100%
rename from arch/mips/loongson64/lemote-2f/ec_kb3310b.h
rename to arch/mips/loongson2ef/lemote-2f/ec_kb3310b.h
diff --git a/arch/mips/loongson64/lemote-2f/irq.c b/arch/mips/loongson2ef/lemote-2f/irq.c
similarity index 99%
rename from arch/mips/loongson64/lemote-2f/irq.c
rename to arch/mips/loongson2ef/lemote-2f/irq.c
index c58a044c6c07..2906f6fb2243 100644
--- a/arch/mips/loongson64/lemote-2f/irq.c
+++ b/arch/mips/loongson2ef/lemote-2f/irq.c
@@ -12,7 +12,7 @@
#include <asm/i8259.h>
#include <asm/mipsregs.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <machine.h>
#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
diff --git a/arch/mips/loongson64/lemote-2f/machtype.c b/arch/mips/loongson2ef/lemote-2f/machtype.c
similarity index 98%
rename from arch/mips/loongson64/lemote-2f/machtype.c
rename to arch/mips/loongson2ef/lemote-2f/machtype.c
index 9462a3ab57be..0200e4223771 100644
--- a/arch/mips/loongson64/lemote-2f/machtype.c
+++ b/arch/mips/loongson2ef/lemote-2f/machtype.c
@@ -5,7 +5,7 @@
*/
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
void __init mach_prom_init_machtype(void)
{
diff --git a/arch/mips/loongson64/lemote-2f/pm.c b/arch/mips/loongson2ef/lemote-2f/pm.c
similarity index 99%
rename from arch/mips/loongson64/lemote-2f/pm.c
rename to arch/mips/loongson2ef/lemote-2f/pm.c
index 3d0027229e3c..339601752d40 100644
--- a/arch/mips/loongson64/lemote-2f/pm.c
+++ b/arch/mips/loongson2ef/lemote-2f/pm.c
@@ -16,7 +16,7 @@
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <cs5536/cs5536_mfgpt.h>
#include "ec_kb3310b.h"
diff --git a/arch/mips/loongson64/lemote-2f/reset.c b/arch/mips/loongson2ef/lemote-2f/reset.c
similarity index 99%
rename from arch/mips/loongson64/lemote-2f/reset.c
rename to arch/mips/loongson2ef/lemote-2f/reset.c
index 0db0934302ea..faec0d919889 100644
--- a/arch/mips/loongson64/lemote-2f/reset.c
+++ b/arch/mips/loongson2ef/lemote-2f/reset.c
@@ -13,7 +13,7 @@
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <cs5536/cs5536.h>
#include "ec_kb3310b.h"
diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index d08b20ff2b27..025cd274146f 100644
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -1,119 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
if MACH_LOONGSON64
-choice
- prompt "Machine Type"
-
-config LEMOTE_FULOONG2E
- bool "Lemote Fuloong(2e) mini-PC"
- select ARCH_SPARSEMEM_ENABLE
- select ARCH_MIGHT_HAVE_PC_PARPORT
- select ARCH_MIGHT_HAVE_PC_SERIO
- select CEVT_R4K
- select CSRC_R4K
- select SYS_HAS_CPU_LOONGSON2E
- select DMA_NONCOHERENT
- select BOOT_ELF32
- select BOARD_SCACHE
- select HAVE_PCI
- select I8259
- select ISA
- select IRQ_MIPS_CPU
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
- select SYS_HAS_EARLY_PRINTK
- select GENERIC_ISA_DMA_SUPPORT_BROKEN
- select CPU_HAS_WB
- select LOONGSON_MC146818
- help
- Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
- an FPGA northbridge
-
- Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
-
-config LEMOTE_MACH2F
- bool "Lemote Loongson 2F family machines"
- select ARCH_SPARSEMEM_ENABLE
- select ARCH_MIGHT_HAVE_PC_PARPORT
- select ARCH_MIGHT_HAVE_PC_SERIO
- select BOARD_SCACHE
- select BOOT_ELF32
- select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
- select CPU_HAS_WB
- select CS5536
- select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
- select DMA_NONCOHERENT
- select GENERIC_ISA_DMA_SUPPORT_BROKEN
- select HAVE_CLK
- select HAVE_PCI
- select I8259
- select IRQ_MIPS_CPU
- select ISA
- select SYS_HAS_CPU_LOONGSON2F
- select SYS_HAS_EARLY_PRINTK
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_HIGHMEM
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select LOONGSON_MC146818
- help
- Lemote Loongson 2F family machines utilize the 2F revision of
- Loongson processor and the AMD CS5536 south bridge.
-
- These family machines include fuloong2f mini PC, yeeloong2f notebook,
- LingLoong allinone PC and so forth.
-
-config LOONGSON_MACH3X
- bool "Generic Loongson 3 family machines"
- select ARCH_SPARSEMEM_ENABLE
- select ARCH_MIGHT_HAVE_PC_PARPORT
- select ARCH_MIGHT_HAVE_PC_SERIO
- select GENERIC_ISA_DMA_SUPPORT_BROKEN
- select BOOT_ELF32
- select BOARD_SCACHE
- select CSRC_R4K
- select CEVT_R4K
- select CPU_HAS_WB
- select FORCE_PCI
- select ISA
- select I8259
- select IRQ_MIPS_CPU
- select NR_CPUS_DEFAULT_4
- select SYS_HAS_CPU_LOONGSON64
- select SYS_HAS_EARLY_PRINTK
- select SYS_SUPPORTS_SMP
- select SYS_SUPPORTS_HOTPLUG_CPU
- select SYS_SUPPORTS_NUMA
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_HIGHMEM
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select LOONGSON_MC146818
- select ZONE_DMA32
- select LEFI_FIRMWARE_INTERFACE
- help
- Generic Loongson 3 family machines utilize the 3A/3B revision
- of Loongson processor and RS780/SBX00 chipset.
-endchoice
-
-config CS5536
- bool
-
-config CS5536_MFGPT
- bool "CS5536 MFGPT Timer"
- depends on CS5536 && !HIGH_RES_TIMERS
- select MIPS_EXTERNAL_TIMER
- help
- This option enables the mfgpt0 timer of AMD CS5536. With this timer
- switched on you can not use high resolution timers.
-
- If you want to enable the Loongson2 CPUFreq Driver, Please enable
- this option at first, otherwise, You will get wrong system time.
-
- If unsure, say Yes.
-
config RS780_HPET
bool "RS780/SBX00 HPET Timer"
- depends on LOONGSON_MACH3X
+ depends on MACH_LOONGSON64
select MIPS_EXTERNAL_TIMER
help
This option enables the hpet timer of AMD RS780/SBX00.
@@ -123,16 +13,4 @@ config RS780_HPET
If unsure, say Yes.
-config LOONGSON_UART_BASE
- bool
- default y
- depends on EARLY_PRINTK || SERIAL_8250
-
-config LOONGSON_MC146818
- bool
- default n
-
-config LEFI_FIRMWARE_INTERFACE
- bool
-
-endif # MACH_LOONGSON64
+endif
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index c74bc0251e9d..3c92e04e3827 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -1,24 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-only
#
-# Common code for all Loongson based systems
+# Makefile for Loongson64 family machines
#
+obj-y += irq.o cop2-ex.o platform.o acpi_init.o dma.o env.o platform.o reset.o setup.o pci.o
-obj-$(CONFIG_MACH_LOONGSON64) += common/
+obj-$(CONFIG_SMP) += smp.o
-#
-# Lemote Fuloong mini-PC (Loongson 2E-based)
-#
-
-obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
-
-#
-# Lemote loongson2f family machines
-#
-
-obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
-
-#
-# All Loongson-3 family machines
-#
+obj-$(CONFIG_NUMA) += numa.o
-obj-$(CONFIG_CPU_LOONGSON64) += loongson-3/
+obj-$(CONFIG_RS780_HPET) += hpet.o
diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform
index b4d2582eb1ef..7f4006833fa5 100644
--- a/arch/mips/loongson64/Platform
+++ b/arch/mips/loongson64/Platform
@@ -1,27 +1,7 @@
#
-# Loongson Processors' Support
+# Loongson64 Processors' Support
#
-# Only gcc >= 4.4 have Loongson specific support
-cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2E) += \
- $(call cc-option,-march=loongson2e,-march=r4600)
-cflags-$(CONFIG_CPU_LOONGSON2F) += \
- $(call cc-option,-march=loongson2f,-march=r4600)
-# Enable the workarounds for Loongson2f
-ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
- ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
- $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
- else
- cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
- endif
- ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
- $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
- else
- cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
- endif
-endif
-
cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
#
@@ -72,6 +52,4 @@ endif
platform-$(CONFIG_MACH_LOONGSON64) += loongson64/
cflags-$(CONFIG_MACH_LOONGSON64) += -I$(srctree)/arch/mips/include/asm/mach-loongson64 -mno-branch-likely
-load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
-load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
-load-$(CONFIG_LOONGSON_MACH3X) += 0xffffffff80200000
+load-$(CONFIG_MACH_LOONGSON64) += 0xffffffff80200000
diff --git a/arch/mips/loongson64/loongson-3/acpi_init.c b/arch/mips/loongson64/acpi_init.c
similarity index 99%
rename from arch/mips/loongson64/loongson-3/acpi_init.c
rename to arch/mips/loongson64/acpi_init.c
index 8d7c119ddf91..3dd8135d2911 100644
--- a/arch/mips/loongson64/loongson-3/acpi_init.c
+++ b/arch/mips/loongson64/acpi_init.c
@@ -99,7 +99,8 @@ void acpi_registers_setup(void)
pm_iowrite(0x2f, ACPI_END >> 8);
/* IO Decode: When AcpiDecodeEnable set, South-Bridge uses the contents
- * of the PM registers at index 0x20~0x2B to decode ACPI I/O address. */
+ * of the PM registers at index 0x20~0x2B to decode ACPI I/O address.
+ */
pm_iowrite(0x0e, 1 << 3);
/* SCI_EN set */
diff --git a/arch/mips/loongson64/loongson-3/cop2-ex.c b/arch/mips/loongson64/cop2-ex.c
similarity index 88%
rename from arch/mips/loongson64/loongson-3/cop2-ex.c
rename to arch/mips/loongson64/cop2-ex.c
index 9efdfe430ff0..508c707627ba 100644
--- a/arch/mips/loongson64/loongson-3/cop2-ex.c
+++ b/arch/mips/loongson64/cop2-ex.c
@@ -1,8 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 2014 Lemote Corporation.
* written by Huacai Chen <[email protected]>
*
diff --git a/arch/mips/loongson64/loongson-3/dma.c b/arch/mips/loongson64/dma.c
similarity index 82%
rename from arch/mips/loongson64/loongson-3/dma.c
rename to arch/mips/loongson64/dma.c
index 5e86635f71db..e2c3354d1d30 100644
--- a/arch/mips/loongson64/loongson-3/dma.c
+++ b/arch/mips/loongson64/dma.c
@@ -6,7 +6,8 @@
dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
/* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from
- * Loongson-3's 48bit address space and embed it into 40bit */
+ * Loongson-3's 48bit address space and embed it into 40bit
+ */
long nid = (paddr >> 44) & 0x3;
return ((nid << 44) ^ paddr) | (nid << 37);
}
@@ -14,7 +15,8 @@ dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
/* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from
- * Loongson-3's 48bit address space and embed it into 40bit */
+ * Loongson-3's 48bit address space and embed it into 40bit
+ */
long nid = (daddr >> 37) & 0x3;
return ((nid << 37) ^ daddr) | (nid << 44);
}
diff --git a/arch/mips/loongson64/common/env.c b/arch/mips/loongson64/env.c
similarity index 79%
rename from arch/mips/loongson64/common/env.c
rename to arch/mips/loongson64/env.c
index 09d5cf4676ca..93658cfbf3a6 100644
--- a/arch/mips/loongson64/common/env.c
+++ b/arch/mips/loongson64/env.c
@@ -15,7 +15,10 @@
*/
#include <linux/export.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <asm/time.h>
+#include <asm/prom.h>
+
+#include <loongson64.h>
#include <boot_param.h>
#include <workarounds.h>
@@ -30,45 +33,17 @@ u64 loongson_freqctrl[MAX_PACKAGES];
unsigned long long smp_group[4];
-#define parse_even_earlier(res, option, p) \
-do { \
- unsigned int tmp __maybe_unused; \
- \
- if (strncmp(option, (char *)p, strlen(option)) == 0) \
- tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \
-} while (0)
-void __init prom_init_env(void)
+void __init prom_init_lefi(void)
{
/* pmon passes arguments in 32bit pointers */
unsigned int processor_id;
-#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
- int *_prom_envp;
- long l;
-
- /* firmware arguments are initialized in head.S */
- _prom_envp = (int *)fw_arg2;
-
- l = (long)*_prom_envp;
- while (l != 0) {
- parse_even_earlier(cpu_clock_freq, "cpuclock", l);
- parse_even_earlier(memsize, "memsize", l);
- parse_even_earlier(highmemsize, "highmemsize", l);
- _prom_envp++;
- l = (long)*_prom_envp;
- }
- if (memsize == 0)
- memsize = 256;
-
- loongson_sysconf.nr_uarts = 1;
-
- pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize);
-#else
struct boot_params *boot_p;
struct loongson_params *loongson_p;
struct system_loongson *esys;
struct efi_cpuinfo_loongson *ecpu;
+ struct board_devices *eboard;
struct irq_source_routing_table *eirq_source;
/* firmware arguments are initialized in head.S */
@@ -79,12 +54,15 @@ void __init prom_init_env(void)
((u64)loongson_p + loongson_p->system_offset);
ecpu = (struct efi_cpuinfo_loongson *)
((u64)loongson_p + loongson_p->cpu_offset);
+ eboard = (struct board_devices *)
+ ((u64)loongson_p + loongson_p->boarddev_table_offset);
eirq_source = (struct irq_source_routing_table *)
((u64)loongson_p + loongson_p->irq_offset);
loongson_memmap = (struct efi_memory_map_loongson *)
((u64)loongson_p + loongson_p->memory_offset);
cpu_clock_freq = ecpu->cpu_clock_freq;
+ mips_hpt_frequency = cpu_clock_freq / 2;
loongson_sysconf.cputype = ecpu->cputype;
switch (ecpu->cputype) {
case Legacy_3A:
@@ -151,6 +129,7 @@ void __init prom_init_env(void)
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
+ set_io_port_base(loongson_sysconf.pci_io_base);
loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
if (loongson_sysconf.dma_mask_bits < 32 ||
loongson_sysconf.dma_mask_bits > 64)
@@ -165,6 +144,9 @@ void __init prom_init_env(void)
loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
loongson_sysconf.vgabios_addr);
+ if (eboard->name)
+ mips_set_machine_name(eboard->name);
+
memset(loongson_sysconf.ecname, 0, 32);
if (esys->has_ec)
memcpy(loongson_sysconf.ecname, esys->ec_name, 32);
@@ -182,31 +164,7 @@ void __init prom_init_env(void)
if (loongson_sysconf.nr_sensors)
memcpy(loongson_sysconf.sensors, esys->sensors,
sizeof(struct sensor_device) * loongson_sysconf.nr_sensors);
-#endif
- if (cpu_clock_freq == 0) {
- processor_id = (¤t_cpu_data)->processor_id;
- switch (processor_id & PRID_REV_MASK) {
- case PRID_REV_LOONGSON2E:
- cpu_clock_freq = 533080000;
- break;
- case PRID_REV_LOONGSON2F:
- cpu_clock_freq = 797000000;
- break;
- case PRID_REV_LOONGSON3A_R1:
- case PRID_REV_LOONGSON3A_R2_0:
- case PRID_REV_LOONGSON3A_R2_1:
- case PRID_REV_LOONGSON3A_R3_0:
- case PRID_REV_LOONGSON3A_R3_1:
- cpu_clock_freq = 900000000;
- break;
- case PRID_REV_LOONGSON3B_R1:
- case PRID_REV_LOONGSON3B_R2:
- cpu_clock_freq = 1000000000;
- break;
- default:
- cpu_clock_freq = 100000000;
- break;
- }
- }
+ processor_id = (¤t_cpu_data)->processor_id;
+
pr_info("CpuClock = %u\n", cpu_clock_freq);
}
diff --git a/arch/mips/loongson64/loongson-3/hpet.c b/arch/mips/loongson64/hpet.c
similarity index 100%
rename from arch/mips/loongson64/loongson-3/hpet.c
rename to arch/mips/loongson64/hpet.c
diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/irq.c
similarity index 77%
rename from arch/mips/loongson64/loongson-3/irq.c
rename to arch/mips/loongson64/irq.c
index 5605061f5f98..4d7b80a0ffb9 100644
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/irq.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <loongson.h>
+#include <loongson64.h>
#include <irq.h>
#include <linux/interrupt.h>
#include <linux/init.h>
@@ -10,6 +10,19 @@
#include "smp.h"
+/* ICU Configuration Regs - r/w */
+
+#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
+#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
+#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
+#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
+#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
+#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
+
extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
unsigned int irq_cpu[16] = {[0 ... 15] = -1};
@@ -78,13 +91,17 @@ static void ht_irqdispatch(void)
#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-void mach_irq_dispatch(unsigned int pending)
+asmlinkage void plat_irq_dispatch(void)
{
+ unsigned int pending;
+
+ pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
if (pending & CAUSEF_IP7)
do_IRQ(LOONGSON_TIMER_IRQ);
#if defined(CONFIG_SMP)
if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt(NULL);
+ loongson3_ipi_interrupt();
#endif
if (pending & CAUSEF_IP3)
ht_irqdispatch();
@@ -127,10 +144,25 @@ void irq_router_init(void)
LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
}
-void __init mach_init_irq(void)
+void __init arch_init_irq(void)
{
struct irq_chip *chip;
+ /*
+ * Clear all of the interrupts while we change the able around a bit.
+ * int-handler is not on bootstrap
+ */
+ clear_c0_status(ST0_IM | ST0_BEV);
+
+ /* no steer */
+ LOONGSON_INTSTEER = 0;
+
+ /*
+ * Mask out all interrupt by writing "1" to all bit position in
+ * the interrupt reset reg.
+ */
+ LOONGSON_INTENCLR = ~0;
+
clear_c0_status(ST0_IM | ST0_BEV);
irq_router_init();
diff --git a/arch/mips/loongson64/loongson-3/Makefile b/arch/mips/loongson64/loongson-3/Makefile
deleted file mode 100644
index df39598742b2..000000000000
--- a/arch/mips/loongson64/loongson-3/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Makefile for Loongson-3 family machines
-#
-obj-y += irq.o cop2-ex.o platform.o acpi_init.o dma.o
-
-obj-$(CONFIG_SMP) += smp.o
-
-obj-$(CONFIG_NUMA) += numa.o
-
-obj-$(CONFIG_RS780_HPET) += hpet.o
diff --git a/arch/mips/loongson64/loongson-3/numa.c b/arch/mips/loongson64/numa.c
similarity index 98%
rename from arch/mips/loongson64/loongson-3/numa.c
rename to arch/mips/loongson64/numa.c
index 414e97de5dc0..de3d3d682694 100644
--- a/arch/mips/loongson64/loongson-3/numa.c
+++ b/arch/mips/loongson64/numa.c
@@ -98,6 +98,7 @@ static void __init init_topology_matrix(void)
static unsigned long nid_to_addroffset(unsigned int nid)
{
unsigned long result;
+
switch (nid) {
case 0:
default:
@@ -119,7 +120,7 @@ static unsigned long nid_to_addroffset(unsigned int nid)
static void __init szmem(unsigned int node)
{
u32 i, mem_type;
- static unsigned long num_physpages = 0;
+ static unsigned long num_physpages;
u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size;
/* Parse memory information and activate */
@@ -276,4 +277,3 @@ void __init prom_init_numa_memory(void)
enable_lpa();
prom_meminit();
}
-EXPORT_SYMBOL(prom_init_numa_memory);
diff --git a/arch/mips/loongson64/pci.c b/arch/mips/loongson64/pci.c
new file mode 100644
index 000000000000..4e896817aadc
--- /dev/null
+++ b/arch/mips/loongson64/pci.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, [email protected]
+ */
+#include <linux/pci.h>
+
+#include <pci.h>
+#include <loongson64.h>
+
+static struct resource loongson_pci_mem_resource = {
+ .name = "PCI Memory Space",
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource loongson_pci_io_resource = {
+ .name = "PCI IO Space",
+ .end = IO_SPACE_LIMIT,
+ .flags = IORESOURCE_IO,
+};
+
+static struct pci_controller loongson_pci_controller = {
+ .pci_ops = &loongson_pci_ops,
+ .io_resource = &loongson_pci_io_resource,
+ .mem_resource = &loongson_pci_mem_resource,
+ .mem_offset = 0x00000000UL,
+ .io_offset = 0x00000000UL,
+};
+
+extern int sbx00_acpi_init(void);
+
+static int __init pcibios_init(void)
+{
+ loongson_pci_controller.io_map_base = mips_io_port_base;
+ loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
+ loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
+
+ register_pci_controller(&loongson_pci_controller);
+
+ sbx00_acpi_init();
+
+ return 0;
+}
+
+arch_initcall(pcibios_init);
diff --git a/arch/mips/loongson64/loongson-3/platform.c b/arch/mips/loongson64/platform.c
similarity index 100%
rename from arch/mips/loongson64/loongson-3/platform.c
rename to arch/mips/loongson64/platform.c
diff --git a/arch/mips/loongson64/reset.c b/arch/mips/loongson64/reset.c
new file mode 100644
index 000000000000..0bbd2a38c127
--- /dev/null
+++ b/arch/mips/loongson64/reset.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, [email protected]
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Zhangjin Wu, [email protected]
+ */
+#include <linux/init.h>
+#include <linux/pm.h>
+
+#include <asm/idle.h>
+#include <asm/reboot.h>
+
+#include <loongson64.h>
+#include <boot_param.h>
+
+static void loongson_restart(char *command)
+{
+ void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr;
+
+ fw_restart();
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ }
+}
+
+static void loongson_poweroff(void)
+{
+ void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr;
+
+ fw_poweroff();
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ }
+}
+
+static void loongson_halt(void)
+{
+ pr_notice("\n\n** You can safely turn off the power now **\n\n");
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ }
+}
+
+static int __init mips_reboot_setup(void)
+{
+ _machine_restart = loongson_restart;
+ _machine_halt = loongson_halt;
+ pm_power_off = loongson_poweroff;
+
+ return 0;
+}
+
+arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
new file mode 100644
index 000000000000..24432adc8350
--- /dev/null
+++ b/arch/mips/loongson64/setup.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <asm/bootinfo.h>
+#include <linux/memblock.h>
+#include <asm/bootinfo.h>
+#include <asm/prom.h>
+#include <asm/traps.h>
+#include <asm/setup.h>
+#include <asm/smp-ops.h>
+#include <asm/cacheflush.h>
+
+#include <loongson64.h>
+
+static void wbflush_loongson(void)
+{
+ asm(".set\tpush\n\t"
+ ".set\tnoreorder\n\t"
+ ".set mips3\n\t"
+ "sync\n\t"
+ "nop\n\t"
+ ".set\tpop\n\t"
+ ".set mips0\n\t");
+}
+
+void (*__wbflush)(void) = wbflush_loongson;
+EXPORT_SYMBOL(__wbflush);
+
+const char *get_system_type(void)
+{
+ return mips_get_machine_name();
+}
+
+static void __init mips_nmi_setup(void)
+{
+ void *base;
+ extern char except_vec_nmi;
+
+ base = (void *)(CAC_BASE + 0x380);
+ memcpy(base, &except_vec_nmi, 0x80);
+ flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
+}
+
+void __init prom_init_cmdline(void)
+{
+ int prom_argc;
+ /* pmon passes arguments in 32bit pointers */
+ int *_prom_argv;
+ int i;
+ long l;
+
+ /* firmware arguments are initialized in head.S */
+ prom_argc = fw_arg0;
+ _prom_argv = (int *)fw_arg1;
+
+ /* arg[0] is "g", the rest is boot parameters */
+ arcs_cmdline[0] = '\0';
+ for (i = 1; i < prom_argc; i++) {
+ l = (long)_prom_argv[i];
+ if (strlen(arcs_cmdline) + strlen(((char *)l) + 1)
+ >= sizeof(arcs_cmdline))
+ break;
+ strcat(arcs_cmdline, ((char *)l));
+ strcat(arcs_cmdline, " ");
+ }
+}
+
+void __init prom_init(void)
+{
+ prom_init_cmdline();
+ setup_8250_early_printk_port(CKSEG1ADDR(LOONGSON_REG_BASE + 0x1e0), 0, 0);
+
+ prom_init_lefi();
+ prom_init_numa_memory();
+
+ register_smp_ops(&loongson3_smp_ops);
+ board_nmi_handler_setup = mips_nmi_setup;
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+void __init plat_mem_setup(void)
+{
+}
+
+void __init plat_time_init(void)
+{
+#ifdef CONFIG_RS780_HPET
+ setup_hpet_timer();
+#endif
+}
+
diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/smp.c
similarity index 99%
rename from arch/mips/loongson64/loongson-3/smp.c
rename to arch/mips/loongson64/smp.c
index ce68cdaaf33c..8ad845e522fb 100644
--- a/arch/mips/loongson64/loongson-3/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -17,7 +17,7 @@
#include <asm/clock.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
-#include <loongson.h>
+#include <loongson64.h>
#include <workarounds.h>
#include "smp.h"
@@ -252,7 +252,7 @@ void loongson3_send_irq_by_ipi(int cpu, int irqs)
loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]);
}
-void loongson3_ipi_interrupt(struct pt_regs *regs)
+void loongson3_ipi_interrupt()
{
int i, cpu = smp_processor_id();
unsigned int action, c0count, irqs;
diff --git a/arch/mips/loongson64/loongson-3/smp.h b/arch/mips/loongson64/smp.h
similarity index 100%
rename from arch/mips/loongson64/loongson-3/smp.h
rename to arch/mips/loongson64/smp.h
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index b249ec0bebb2..8f739679a5e8 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -13,7 +13,7 @@
#include <linux/oprofile.h>
#include <linux/interrupt.h>
-#include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */
+#include <loongson2ef.h> /* LOONGSON2_PERFCNT_IRQ */
#include "op_impl.h"
#define LOONGSON2_CPU_TYPE "mips/loongson2"
diff --git a/arch/mips/oprofile/op_model_loongson3.c b/arch/mips/oprofile/op_model_loongson3.c
index 436b1fc99f2c..222077e49bc6 100644
--- a/arch/mips/oprofile/op_model_loongson3.c
+++ b/arch/mips/oprofile/op_model_loongson3.c
@@ -13,7 +13,7 @@
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <irq.h>
-#include <loongson.h>
+#include <loongson64.h>
#include "op_impl.h"
#define LOONGSON3_PERFCNT_OVERFLOW (1ULL << 63)
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index d6de4cb2e31c..342ce10ef593 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_LOONGSON_MACH3X) += fixup-loongson3.o ops-loongson3.o
+obj-$(CONFIG_MACH_LOONGSON64) += fixup-loongson3.o ops-loongson3.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o
obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 91aa923234bc..60b6caec02c0 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -10,7 +10,7 @@
#include <linux/init.h>
#include <linux/pci.h>
-#include <loongson.h>
+#include <loongson2ef.h>
/* South bridge slot number is set by the pci probe process */
static u8 sb_slot = 5;
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index 632ff2daa338..f998ca1555a5 100644
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -10,7 +10,7 @@
#include <linux/init.h>
#include <linux/pci.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <cs5536/cs5536.h>
#include <cs5536/cs5536_pci.h>
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index 0d1b36ba1c21..f5f479252a3a 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -13,7 +13,7 @@
#include <linux/kernel.h>
#include <linux/export.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#ifdef CONFIG_CS5536
#include <cs5536/cs5536_pci.h>
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
index 2f6ad36bdea6..7f66c8cde773 100644
--- a/arch/mips/pci/ops-loongson3.c
+++ b/arch/mips/pci/ops-loongson3.c
@@ -5,7 +5,7 @@
#include <asm/mips-boards/bonito64.h>
-#include <loongson.h>
+#include <loongson64.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
diff --git a/drivers/cpufreq/loongson2_cpufreq.c b/drivers/cpufreq/loongson2_cpufreq.c
index 890813e0bb76..a3b6f17e6e0a 100644
--- a/drivers/cpufreq/loongson2_cpufreq.c
+++ b/drivers/cpufreq/loongson2_cpufreq.c
@@ -23,7 +23,7 @@
#include <asm/clock.h>
#include <asm/idle.h>
-#include <asm/mach-loongson64/loongson.h>
+#include <asm/mach-loongson2ef/loongson2ef.h>
static uint nowait;
diff --git a/drivers/gpio/gpio-loongson.c b/drivers/gpio/gpio-loongson.c
index a42145873cc9..7b72846a6dc7 100644
--- a/drivers/gpio/gpio-loongson.c
+++ b/drivers/gpio/gpio-loongson.c
@@ -17,7 +17,7 @@
#include <linux/platform_device.h>
#include <linux/bitops.h>
#include <asm/types.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#define STLS2F_N_GPIO 4
#define STLS3A_N_GPIO 16
diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c
index a7f184bb47e0..7b5805b4988c 100644
--- a/drivers/platform/mips/cpu_hwmon.c
+++ b/drivers/platform/mips/cpu_hwmon.c
@@ -6,7 +6,7 @@
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
-#include <loongson.h>
+#include <loongson64.h>
#include <boot_param.h>
#include <loongson_hwmon.h>
--
2.22.0
This controller appeared on Loongson-3 family of chips to receive interrupts
from PCH chip.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/Kconfig | 8 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ls3-htintc.c | 145 +++++++++++++++++++++++++++++++
3 files changed, 154 insertions(+)
create mode 100644 drivers/irqchip/irq-ls3-htintc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 8d9eac5fd4a7..b3ce0f3e43ae 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -480,6 +480,14 @@ config LS3_IOINTC
help
Support for the Loongson-3 I/O Interrupt Controller.
+config LS3_HTINTC
+ bool "Loongson3 HyperTransport Interrupt Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson-3 HyperTransport Interrupt Controller.
endmenu
config SIFIVE_PLIC
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 49ecb8d38138..0fda94c319e9 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -103,3 +103,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_LS3_IOINTC) += irq-ls3-iointc.o
+obj-$(CONFIG_LS3_HTINTC) += irq-ls3-htintc.o
diff --git a/drivers/irqchip/irq-ls3-htintc.c b/drivers/irqchip/irq-ls3-htintc.c
new file mode 100644
index 000000000000..c53bbb0bd78c
--- /dev/null
+++ b/drivers/irqchip/irq-ls3-htintc.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Jiaxun Yang <[email protected]>
+ * Loongson-3 HyperTransport IRQ support
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
+
+#define HTINTC_NUM_GC 4
+#define HTINTC_GC_SIZE 0x4
+#define HTINTC_NUM_HANDLER 4
+#define HTINTC_HANDLER_SIZE 0x8
+#define HTINTC_HANDLER_IRQ 64
+
+#define HTINTC_VECTOR_OFFSET 0x0
+#define HTINTC_EN_OFFSET 0x20
+
+struct htintc_handler_priv {
+ struct irq_domain *domain;
+ void __iomem *handler_base;
+};
+
+static void htintc_chained_handle_irq(struct irq_desc *desc)
+{
+ struct htintc_handler_priv *priv = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ int i;
+ bool handled;
+
+ chained_irq_enter(chip, desc);
+
+ for (i = 0; i < HTINTC_NUM_GC; i++) {
+ uint32_t irqs = readl(priv->handler_base + HTINTC_GC_SIZE * i);
+
+ while (irqs) {
+ int bit = __ffs(irqs);
+
+ generic_handle_irq(irq_find_mapping(priv->domain, bit + 32 * i));
+ irqs &= ~BIT(bit);
+ handled = true;
+ }
+ }
+
+ if (!handled)
+ spurious_interrupt();
+
+ chained_irq_exit(chip, desc);
+}
+
+int __init ls3_htintc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+ struct htintc_handler_priv *priv;
+ struct irq_domain *domain;
+ void __iomem *base;
+ int parent_irq[HTINTC_NUM_HANDLER], err = 0;
+ int i;
+
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+
+ for (i = 0; i < HTINTC_NUM_HANDLER; i++) {
+ parent_irq[i] = irq_of_parse_and_map(node, i);
+ if (!parent_irq[i]) {
+ pr_err("ls3-htintc: unable to get parent irq %d\n", i);
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+ }
+ /* Set up an IRQ domain */
+ domain = irq_domain_add_linear(node, 32 * HTINTC_NUM_GC,
+ &irq_generic_chip_ops, NULL);
+ if (!domain) {
+ pr_err("ls3-htintc: cannot add IRQ domain\n");
+ err = -ENOMEM;
+ goto out_iounmap;
+ }
+
+ for (i = 0; i < HTINTC_NUM_HANDLER; i++) {
+ /* Mask all interrupts */
+ writeq(0x0, base + HTINTC_EN_OFFSET + HTINTC_HANDLER_SIZE * i);
+ }
+
+ err = irq_alloc_domain_generic_chips(domain, 32, 1,
+ node->full_name, handle_fasteoi_irq,
+ IRQ_NOPROBE, 0, IRQ_GC_INIT_MASK_CACHE);
+ if (err) {
+ pr_err("ls3-htintc: unable to register IRQ domain\n");
+ err = -ENOMEM;
+ goto out_free_domain;
+ }
+
+ for (i = 0; i < HTINTC_NUM_GC; i++) {
+ gc = irq_get_domain_generic_chip(domain, i * 32);
+ gc->reg_base = base + HTINTC_GC_SIZE * i;
+ gc->domain = domain;
+
+ ct = gc->chip_types;
+ ct->regs.mask = HTINTC_EN_OFFSET;
+ ct->regs.ack = HTINTC_VECTOR_OFFSET;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_ack = irq_gc_ack_set_bit;
+ }
+
+ priv->domain = domain;
+ priv->handler_base = base + HTINTC_VECTOR_OFFSET;
+
+ for (i = 0; i < HTINTC_NUM_HANDLER; i++) {
+ irq_set_chained_handler_and_data(parent_irq[i],
+ htintc_chained_handle_irq, priv);
+ }
+
+ return 0;
+
+out_free_domain:
+ irq_domain_remove(domain);
+out_iounmap:
+ iounmap(base);
+out_free_priv:
+ kfree(priv);
+
+ return err;
+}
+
+IRQCHIP_DECLARE(ls3_htintc, "loongson,ls3-htintc", ls3_htintc_of_init);
--
2.22.0
Load proper dtb according to firmware passed parameters and
CPU PRID.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../asm/mach-loongson64/builtin_dtbs.h | 26 +++++++
.../include/asm/mach-loongson64/loongson64.h | 2 +
arch/mips/loongson64/env.c | 67 +++++++++++++++++++
arch/mips/loongson64/setup.c | 15 +++++
4 files changed, 110 insertions(+)
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
new file mode 100644
index 000000000000..234803ba9d82
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Built-in Generic dtbs for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+
+extern u32 __dtb_ls3a1000_780e_1way_begin[];
+extern u32 __dtb_ls3a1000_780e_2way_begin[];
+extern u32 __dtb_ls3a1000_780e_4way_begin[];
+
+extern u32 __dtb_ls3b_780e_1way_begin[];
+extern u32 __dtb_ls3b_780e_2way_begin[];
+
+extern u32 __dtb_ls3a2000_780e_1way_begin[];
+extern u32 __dtb_ls3a2000_780e_2way_begin[];
+extern u32 __dtb_ls3a2000_780e_4way_begin[];
+
+extern u32 __dtb_ls3a3000_780e_1way_begin[];
+extern u32 __dtb_ls3a3000_780e_2way_begin[];
+extern u32 __dtb_ls3a3000_780e_4way_begin[];
+
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/loongson64.h b/arch/mips/include/asm/mach-loongson64/loongson64.h
index d877adb99d33..78daa3fb3fa7 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson64.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson64.h
@@ -45,4 +45,6 @@ extern u64 loongson_freqctrl[MAX_PACKAGES];
extern const struct plat_smp_ops loongson3_smp_ops;
extern void __init prom_init_lefi(void);
+extern void *loongson_fdt_blob;
+
#endif
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 93658cfbf3a6..4336bd7c1b94 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -20,6 +20,7 @@
#include <loongson64.h>
#include <boot_param.h>
+#include <builtin_dtbs.h>
#include <workarounds.h>
u32 cpu_clock_freq;
@@ -126,6 +127,72 @@ void __init prom_init_lefi(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ switch (loongson_sysconf.nr_nodes) {
+ case 4:
+ loongson_fdt_blob = __dtb_ls3a1000_780e_4way_begin;
+ break;
+ case 2:
+ loongson_fdt_blob = __dtb_ls3a1000_780e_2way_begin;
+ break;
+ case 1:
+ default:
+ loongson_fdt_blob = __dtb_ls3a1000_780e_1way_begin;
+ break;
+ }
+ break;
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ switch (loongson_sysconf.nr_nodes) {
+ case 4:
+ loongson_fdt_blob = __dtb_ls3a2000_780e_4way_begin;
+ break;
+ case 2:
+ loongson_fdt_blob = __dtb_ls3a2000_780e_2way_begin;
+ break;
+ case 1:
+ default:
+ loongson_fdt_blob = __dtb_ls3a2000_780e_1way_begin;
+ break;
+ }
+ break;
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ switch (loongson_sysconf.nr_nodes) {
+ case 4:
+ loongson_fdt_blob = __dtb_ls3a3000_780e_4way_begin;
+ break;
+ case 2:
+ loongson_fdt_blob = __dtb_ls3a3000_780e_2way_begin;
+ break;
+ case 1:
+ default:
+ loongson_fdt_blob = __dtb_ls3a3000_780e_1way_begin;
+ break;
+ }
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ switch (loongson_sysconf.nr_nodes) {
+ case 4:
+ loongson_fdt_blob = __dtb_ls3b_780e_2way_begin;
+ break;
+ case 2:
+ default:
+ loongson_fdt_blob = __dtb_ls3b_780e_1way_begin;
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ if(!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
+
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
index 24432adc8350..3b850b3128ea 100644
--- a/arch/mips/loongson64/setup.c
+++ b/arch/mips/loongson64/setup.c
@@ -7,9 +7,15 @@
#include <asm/setup.h>
#include <asm/smp-ops.h>
#include <asm/cacheflush.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
#include <loongson64.h>
+void *loongson_fdt_blob;
+
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
@@ -81,6 +87,8 @@ void __init prom_free_prom_memory(void)
void __init plat_mem_setup(void)
{
+ if (loongson_fdt_blob)
+ __dt_setup_arch(loongson_fdt_blob);
}
void __init plat_time_init(void)
@@ -90,3 +98,10 @@ void __init plat_time_init(void)
#endif
}
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
+}
--
2.22.0
Prepare for later dts.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../bindings/mips/loongson/cpus.yaml | 38 +++++++++++
.../bindings/mips/loongson/devices.yaml | 64 +++++++++++++++++++
2 files changed, 102 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
new file mode 100644
index 000000000000..410d896a0078
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson CPUs bindings
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |+
+ The device tree allows to describe the layout of CPUs in a system through
+ the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+ defining properties for every cpu.
+
+ Bindings for CPU nodes follow the Devicetree Specification, available from:
+
+ https://www.devicetree.org/specifications/
+
+properties:
+ reg:
+ maxItems: 1
+ description: |
+ Physical ID of a CPU, Can be read from CP0 EBase.CPUNum.
+
+ compatible:
+ enum:
+ - loongson,gs464
+ - loongson,gs464e
+ - loongson,gs264
+ - loongson,gs464v
+
+required:
+ - device_type
+ - reg
+ - compatible
+...
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
new file mode 100644
index 000000000000..181881a9f4a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SoC based Platforms Device Tree Bindings
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+description: |
+ Devices with a Loongson CPU shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Loongson 3A1000 + RS780E 1Way
+ items:
+ - const: loongson,ls3a1000-780e-1way
+
+ - description: Loongson 3A1000 + RS780E 2Way
+ items:
+ - const: loongson,ls3a1000-780e-2way
+
+ - description: Loongson 3A1000 + RS780E 4Way
+ items:
+ - const: loongson,ls3a1000-780e-4way
+
+ - description: Loongson 3B1000/1500 + RS780E 1Way
+ items:
+ - const: loongson,ls3b-780e-1way
+
+ - description: Loongson 3B1000/1500 + RS780E 2Way
+ items:
+ - const: loongson,ls3b-780e-2way
+
+ - description: Loongson 3A2000 + RS780E 1Way
+ items:
+ - const: loongson,ls3a2000-780e-1way
+
+ - description: Loongson 3A2000 + RS780E 2Way
+ items:
+ - const: loongson,ls3a2000-780e-2way
+
+ - description: Loongson 3A2000 + RS780E 4Way
+ items:
+ - const: loongson,ls3a2000-780e-4way
+
+ - description: Loongson 3A3000 + RS780E 1Way
+ items:
+ - const: loongson,ls3a3000-780e-1way
+
+ - description: Loongson 3A3000 + RS780E 2Way
+ items:
+ - const: loongson,ls3a3000-780e-2way
+
+ - description: Loongson 3A3000 + RS780E 4Way
+ items:
+ - const: loongson,ls3a3000-780e-4way
+
+...
--
2.22.0
We've made generic irqchip drivers for Loongson-3 platform, it's time
to say goodbye to these legacy code.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mach-loongson64/irq.h | 1 -
arch/mips/loongson64/irq.c | 167 +-------------------
arch/mips/loongson64/smp.c | 26 ++-
3 files changed, 11 insertions(+), 183 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index baed43285163..e57a21fc581c 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -35,7 +35,6 @@
#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(void);
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c
index 4d7b80a0ffb9..78cd824cc84e 100644
--- a/arch/mips/loongson64/irq.c
+++ b/arch/mips/loongson64/irq.c
@@ -3,180 +3,17 @@
#include <irq.h>
#include <linux/interrupt.h>
#include <linux/init.h>
+#include <linux/irqchip.h>
#include <asm/irq_cpu.h>
-#include <asm/i8259.h>
#include <asm/mipsregs.h>
#include "smp.h"
-/* ICU Configuration Regs - r/w */
-
-#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
-#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
-#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
-
-/* ICU Enable Regs - IntEn & IntISR are r/o. */
-
-#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
-#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
-#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
-#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
-
-extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
-
-unsigned int irq_cpu[16] = {[0 ... 15] = -1};
-unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
-unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
-
-int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
- bool force)
-{
- unsigned int cpu;
- struct cpumask new_affinity;
-
- /* I/O devices are connected on package-0 */
- cpumask_copy(&new_affinity, affinity);
- for_each_cpu(cpu, affinity)
- if (cpu_data[cpu].package > 0)
- cpumask_clear_cpu(cpu, &new_affinity);
-
- if (cpumask_empty(&new_affinity))
- return -EINVAL;
-
- cpumask_copy(d->common->affinity, &new_affinity);
-
- return IRQ_SET_MASK_OK_NOCOPY;
-}
-
-static void ht_irqdispatch(void)
-{
- unsigned int i, irq;
- struct irq_data *irqd;
- struct cpumask affinity;
-
- irq = LOONGSON_HT1_INT_VECTOR(0);
- LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
-
- for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
- if (!(irq & (0x1 << ht_irq[i])))
- continue;
-
- /* handled by local core */
- if (local_irq & (0x1 << ht_irq[i])) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irqd = irq_get_irq_data(ht_irq[i]);
- cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
- if (cpumask_empty(&affinity)) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
- if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
- irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
-
- if (irq_cpu[ht_irq[i]] == 0) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- /* balanced by other cores */
- loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
- }
-}
-
-#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & CAUSEF_IP7)
- do_IRQ(LOONGSON_TIMER_IRQ);
-#if defined(CONFIG_SMP)
- if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt();
-#endif
- if (pending & CAUSEF_IP3)
- ht_irqdispatch();
- if (pending & CAUSEF_IP2)
- do_IRQ(LOONGSON_UART_IRQ);
- if (pending & UNUSED_IPS) {
- pr_err("%s : spurious interrupt\n", __func__);
- spurious_interrupt();
- }
-}
-
-static inline void mask_loongson_irq(struct irq_data *d) { }
-static inline void unmask_loongson_irq(struct irq_data *d) { }
-
- /* For MIPS IRQs which shared by all cores */
-static struct irq_chip loongson_irq_chip = {
- .name = "Loongson",
- .irq_ack = mask_loongson_irq,
- .irq_mask = mask_loongson_irq,
- .irq_mask_ack = mask_loongson_irq,
- .irq_unmask = unmask_loongson_irq,
- .irq_eoi = unmask_loongson_irq,
-};
-
-void irq_router_init(void)
-{
- int i;
-
- /* route LPC int to cpu core0 int 0 */
- LOONGSON_INT_ROUTER_LPC =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
- /* route HT1 int0 ~ int7 to cpu core0 INT1*/
- for (i = 0; i < 8; i++)
- LOONGSON_INT_ROUTER_HT1(i) =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
- /* enable HT1 interrupt */
- LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
- /* enable router interrupt intenset */
- LOONGSON_INT_ROUTER_INTENSET =
- LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
-}
void __init arch_init_irq(void)
{
- struct irq_chip *chip;
-
- /*
- * Clear all of the interrupts while we change the able around a bit.
- * int-handler is not on bootstrap
- */
- clear_c0_status(ST0_IM | ST0_BEV);
-
- /* no steer */
- LOONGSON_INTSTEER = 0;
-
- /*
- * Mask out all interrupt by writing "1" to all bit position in
- * the interrupt reset reg.
- */
- LOONGSON_INTENCLR = ~0;
-
- clear_c0_status(ST0_IM | ST0_BEV);
-
- irq_router_init();
- mips_cpu_irq_init();
- init_i8259_irqs();
- chip = irq_get_chip(I8259A_IRQ_BASE);
- chip->irq_set_affinity = plat_set_irq_affinity;
-
- irq_set_chip_and_handler(LOONGSON_UART_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
- irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
-
- set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
+ irqchip_init();
}
#ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index 8ad845e522fb..d53942c56a16 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -4,6 +4,7 @@
* Author: Chen Huacai, [email protected]
*/
+#include <irq.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/sched.h>
@@ -24,6 +25,8 @@
DEFINE_PER_CPU(int, cpu_state);
+#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
+
static void *ipi_set0_regs[16];
static void *ipi_clear0_regs[16];
static void *ipi_status0_regs[16];
@@ -245,21 +248,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]);
}
-#define IPI_IRQ_OFFSET 6
-
-void loongson3_send_irq_by_ipi(int cpu, int irqs)
-{
- loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]);
-}
-
-void loongson3_ipi_interrupt()
+static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
{
int i, cpu = smp_processor_id();
- unsigned int action, c0count, irqs;
+ unsigned int action, c0count;
/* Load the ipi register to figure out what we're supposed to do */
action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]);
- irqs = action >> IPI_IRQ_OFFSET;
/* Clear the ipi register to clear the interrupt */
loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]);
@@ -282,13 +277,7 @@ void loongson3_ipi_interrupt()
__wbflush(); /* Let others see the result ASAP */
}
- if (irqs) {
- int irq;
- while ((irq = ffs(irqs))) {
- do_IRQ(irq-1);
- irqs &= ~(1<<(irq-1));
- }
- }
+ return IRQ_HANDLED;
}
#define MAX_LOOPS 800
@@ -384,6 +373,9 @@ static void __init loongson3_smp_setup(void)
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
{
+ if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
+ pr_err("Failed to request IPI IRQ\n");
init_cpu_present(cpu_possible_mask);
per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
}
--
2.22.0
On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <[email protected]> wrote:
>
> Prepare for later dts.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> .../bindings/mips/loongson/cpus.yaml | 38 +++++++++++
> .../bindings/mips/loongson/devices.yaml | 64 +++++++++++++++++++
> 2 files changed, 102 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
>
> diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> new file mode 100644
> index 000000000000..410d896a0078
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> @@ -0,0 +1,38 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license for new bindings please:
(GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson CPUs bindings
> +
> +maintainers:
> + - Jiaxun Yang <[email protected]>
> +
> +description: |+
> + The device tree allows to describe the layout of CPUs in a system through
> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> + defining properties for every cpu.
> +
> + Bindings for CPU nodes follow the Devicetree Specification, available from:
> +
> + https://www.devicetree.org/specifications/
> +
> +properties:
> + reg:
> + maxItems: 1
> + description: |
> + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum.
Is this definition specific to Loongson CPUs or all MIPS?
I would expect to see a common MIPS CPU schema with these compatibles
listed there.
> +
> + compatible:
> + enum:
> + - loongson,gs464
> + - loongson,gs464e
> + - loongson,gs264
> + - loongson,gs464v
> +
> +required:
> + - device_type
> + - reg
> + - compatible
> +...
> diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> new file mode 100644
> index 000000000000..181881a9f4a9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek SoC based Platforms Device Tree Bindings
MediaTek SoC?
> +
> +maintainers:
> + - Jiaxun Yang <[email protected]>
> +description: |
> + Devices with a Loongson CPU shall have the following properties.
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> +
> + - description: Loongson 3A1000 + RS780E 1Way
> + items:
> + - const: loongson,ls3a1000-780e-1way
> +
> + - description: Loongson 3A1000 + RS780E 2Way
> + items:
> + - const: loongson,ls3a1000-780e-2way
> +
> + - description: Loongson 3A1000 + RS780E 4Way
> + items:
> + - const: loongson,ls3a1000-780e-4way
> +
> + - description: Loongson 3B1000/1500 + RS780E 1Way
> + items:
> + - const: loongson,ls3b-780e-1way
> +
> + - description: Loongson 3B1000/1500 + RS780E 2Way
> + items:
> + - const: loongson,ls3b-780e-2way
> +
> + - description: Loongson 3A2000 + RS780E 1Way
> + items:
> + - const: loongson,ls3a2000-780e-1way
> +
> + - description: Loongson 3A2000 + RS780E 2Way
> + items:
> + - const: loongson,ls3a2000-780e-2way
> +
> + - description: Loongson 3A2000 + RS780E 4Way
> + items:
> + - const: loongson,ls3a2000-780e-4way
> +
> + - description: Loongson 3A3000 + RS780E 1Way
> + items:
> + - const: loongson,ls3a3000-780e-1way
> +
> + - description: Loongson 3A3000 + RS780E 2Way
> + items:
> + - const: loongson,ls3a3000-780e-2way
> +
> + - description: Loongson 3A3000 + RS780E 4Way
> + items:
> + - const: loongson,ls3a3000-780e-4way
> +
> +...
> --
> 2.22.0
>
On 27/08/2019 09:52, Jiaxun Yang wrote:
> This controller appeared on Loongson-3 family of chips to receive interrupts
> from PCH chip.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> drivers/irqchip/Kconfig | 8 ++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ls3-htintc.c | 145 +++++++++++++++++++++++++++++++
> 3 files changed, 154 insertions(+)
> create mode 100644 drivers/irqchip/irq-ls3-htintc.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 8d9eac5fd4a7..b3ce0f3e43ae 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -480,6 +480,14 @@ config LS3_IOINTC
> help
> Support for the Loongson-3 I/O Interrupt Controller.
>
> +config LS3_HTINTC
> + bool "Loongson3 HyperTransport Interrupt Controller"
> + depends on MACH_LOONGSON64
> + default y
> + select IRQ_DOMAIN
> + select GENERIC_IRQ_CHIP
> + help
> + Support for the Loongson-3 HyperTransport Interrupt Controller.
> endmenu
>
> config SIFIVE_PLIC
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 49ecb8d38138..0fda94c319e9 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -103,3 +103,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
> obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
> obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
> obj-$(CONFIG_LS3_IOINTC) += irq-ls3-iointc.o
> +obj-$(CONFIG_LS3_HTINTC) += irq-ls3-htintc.o
> diff --git a/drivers/irqchip/irq-ls3-htintc.c b/drivers/irqchip/irq-ls3-htintc.c
> new file mode 100644
> index 000000000000..c53bbb0bd78c
> --- /dev/null
> +++ b/drivers/irqchip/irq-ls3-htintc.c
> @@ -0,0 +1,145 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019, Jiaxun Yang <[email protected]>
> + * Loongson-3 HyperTransport IRQ support
> + */
> +
> +#include <linux/errno.h>
> +#include <linux/init.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/ioport.h>
> +#include <linux/irqchip.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/io.h>
> +#include <linux/irqchip/chained_irq.h>
> +
> +#define HTINTC_NUM_GC 4
> +#define HTINTC_GC_SIZE 0x4
> +#define HTINTC_NUM_HANDLER 4
> +#define HTINTC_HANDLER_SIZE 0x8
> +#define HTINTC_HANDLER_IRQ 64
> +
> +#define HTINTC_VECTOR_OFFSET 0x0
> +#define HTINTC_EN_OFFSET 0x20
> +
> +struct htintc_handler_priv {
> + struct irq_domain *domain;
> + void __iomem *handler_base;
> +};
> +
> +static void htintc_chained_handle_irq(struct irq_desc *desc)
> +{
> + struct htintc_handler_priv *priv = irq_desc_get_handler_data(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + int i;
> + bool handled;
> +
> + chained_irq_enter(chip, desc);
> +
> + for (i = 0; i < HTINTC_NUM_GC; i++) {
> + uint32_t irqs = readl(priv->handler_base + HTINTC_GC_SIZE * i);
> +
> + while (irqs) {
> + int bit = __ffs(irqs);
> +
> + generic_handle_irq(irq_find_mapping(priv->domain, bit + 32 * i));
> + irqs &= ~BIT(bit);
> + handled = true;
> + }
> + }
> +
> + if (!handled)
Uninitialized variable. I'm pretty sure your compiler warns about that.
> + spurious_interrupt();
> +
> + chained_irq_exit(chip, desc);
> +}
> +
> +int __init ls3_htintc_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct irq_chip_generic *gc;
> + struct irq_chip_type *ct;
> + struct htintc_handler_priv *priv;
> + struct irq_domain *domain;
> + void __iomem *base;
> + int parent_irq[HTINTC_NUM_HANDLER], err = 0;
> + int i;
> +
> +
Spurious empty line.
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + base = of_iomap(node, 0);
> + if (!base) {
> + err = -ENODEV;
> + goto out_free_priv;
> + }
> +
> + for (i = 0; i < HTINTC_NUM_HANDLER; i++) {
> + parent_irq[i] = irq_of_parse_and_map(node, i);
> + if (!parent_irq[i]) {
> + pr_err("ls3-htintc: unable to get parent irq %d\n", i);
> + err = -ENODEV;
> + goto out_iounmap;
> + }
> + }
> + /* Set up an IRQ domain */
> + domain = irq_domain_add_linear(node, 32 * HTINTC_NUM_GC,
> + &irq_generic_chip_ops, NULL);
Please align the second line on the opening bracket from the previous line.
> + if (!domain) {
> + pr_err("ls3-htintc: cannot add IRQ domain\n");
> + err = -ENOMEM;
> + goto out_iounmap;
> + }
> +
> + for (i = 0; i < HTINTC_NUM_HANDLER; i++) {
> + /* Mask all interrupts */
> + writeq(0x0, base + HTINTC_EN_OFFSET + HTINTC_HANDLER_SIZE * i);
> + }
> +
> + err = irq_alloc_domain_generic_chips(domain, 32, 1,
> + node->full_name, handle_fasteoi_irq,
handle_fast_eoi? Where is your irq_eoi callback? That looks wrong given
that you're using a mask/ack/unmask sequence.
> + IRQ_NOPROBE, 0, IRQ_GC_INIT_MASK_CACHE);
> + if (err) {
> + pr_err("ls3-htintc: unable to register IRQ domain\n");
> + err = -ENOMEM;
> + goto out_free_domain;
> + }
> +
> + for (i = 0; i < HTINTC_NUM_GC; i++) {
> + gc = irq_get_domain_generic_chip(domain, i * 32);
> + gc->reg_base = base + HTINTC_GC_SIZE * i;
> + gc->domain = domain;
> +
> + ct = gc->chip_types;
> + ct->regs.mask = HTINTC_EN_OFFSET;
> + ct->regs.ack = HTINTC_VECTOR_OFFSET;
> + ct->chip.irq_unmask = irq_gc_mask_set_bit;
> + ct->chip.irq_mask = irq_gc_mask_clr_bit;
> + ct->chip.irq_ack = irq_gc_ack_set_bit;
> + }
> +
> + priv->domain = domain;
> + priv->handler_base = base + HTINTC_VECTOR_OFFSET;
> +
> + for (i = 0; i < HTINTC_NUM_HANDLER; i++) {
> + irq_set_chained_handler_and_data(parent_irq[i],
> + htintc_chained_handle_irq, priv);
> + }
> +
> + return 0;
> +
> +out_free_domain:
> + irq_domain_remove(domain);
> +out_iounmap:
> + iounmap(base);
> +out_free_priv:
> + kfree(priv);
> +
> + return err;
> +}
> +
> +IRQCHIP_DECLARE(ls3_htintc, "loongson,ls3-htintc", ls3_htintc_of_init);
>
M.
--
Jazz is not dead, it just smells funny...
On Tue, Aug 27, 2019 at 4:00 AM Jiaxun Yang <[email protected]> wrote:
>
> Document Loongson-3 I/O Interrupt controller.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> .../loongson,ls3-iointc.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
> new file mode 100644
> index 000000000000..cc6ac8b2cd7c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license please.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-iointc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Loongson-3 I/O Interrupt Controller
> +
> +maintainers:
> + - Jiaxun Yang <[email protected]>
> +
> +description: |
> + This interrupt controller is found in the Loongson-3 family of chips as the primary
> + package interrupt source which can route interrupt to interrupt line of cores.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - loongson,ls3-iointc
Same comment here.
> +
> + reg:
> + maxItems: 1
> +
> + 'loongson,map-ip':
> + description:
> + The interrupt line it's going to map to.
I don't understand. Needs a better description.
> + allOf:
You need to define the type here with a $ref.
> + - maximum: 5
> + minimum: 0
> +
> + 'loongson,map-core':
> + description:
> + The core it's going to map to.
There's 1 interrupt ctrlr per core or what?
> + allOf:
> + - maximum: 5
> + minimum: 0
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - '#interrupt-cells'
Add a:
additionalProperties: false
> +
> +examples:
> + - |
> + iointc: interrupt-controller@3ff01400 {
> + compatible = "loongson,ls3-io-intc";
> + reg = <0x3ff01400 0x60>;
> + interrupts = <2>;
> + loongson,map-ip = <0>;
> + loongson,map-core = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> --
> 2.22.0
>
Hi, Jiaxun,
1, To describe CPU I prefer "loongson" to "ls" because "ls" is confusing, and in future we will use ls2h/ls7a to describe Loongson's bridge.
2, I think it is better to use loongson64c/loongson64g than loongson2ef/loongson64. As we disscussed, we will use PRID_IMP_LOONGSON_64C/PRID_IMP_LOONGSON_64G to describe 0x6300/0xc000.
Huacai
------------------ Original ------------------
From: "Jiaxun Yang"<[email protected]>;Date: Tue, Aug 27, 2019 04:52 PMTo: "linux-mips"<[email protected]>; Cc: "chenhc"<[email protected]>; "paul.burton"<[email protected]>; "tglx"<[email protected]>; "jason"<[email protected]>; "maz"<[email protected]>; "linux-kernel"<[email protected]>; "robh+dt"<[email protected]>; "mark.rutland"<[email protected]>; "devicetree"<[email protected]>; "Jiaxun Yang"<[email protected]>; Subject: [PATCH 00/13] Modernize Loongson64 Machine Loongson have a long history of contributing their code to mainline kernel.
However, it seems like recent years, they are focusing on maintain a kernel by themselves
rather than contribute there code to the community.
Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
maintainance and became outdated.
This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
Loongson 2e/f alone since they are too legacy to touch.
Jiaxun Yang (13):
MIPS: Loongson64: Rename CPU TYPES
MIPS: Loongson64: Sepreate loongson2ef/loongson64 code
MAINTAINERS: Fix entries for new loongson64 path
irqchip: Add driver for Loongson-3 I/O interrupt controller
dt-bindings: interrupt-controller: Add Loongson-3 IOINTC
irqchip: Add driver for Loongson-3 HyperTransport interrupt controller
dt-bindings: interrupt-controller: Add Loongson-3 HTINTC
irqchip: i8259: Add plat-poll support
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson cpus & boards
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
.../loongson,ls3-htintc.yaml | 53 +++++
.../loongson,ls3-iointc.yaml | 61 +++++
.../bindings/mips/loongson/cpus.yaml | 38 +++
.../bindings/mips/loongson/devices.yaml | 64 ++++++
MAINTAINERS | 9 +-
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 83 +++++--
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 8 +
arch/mips/boot/dts/loongson/ls3-2nodes.dtsi | 8 +
arch/mips/boot/dts/loongson/ls3-4nodes.dtsi | 15 ++
arch/mips/boot/dts/loongson/ls3-cpus.dtsi | 150 ++++++++++++
arch/mips/boot/dts/loongson/ls3-gs464.dtsi | 18 ++
arch/mips/boot/dts/loongson/ls3-gs464e.dtsi | 18 ++
.../boot/dts/loongson/ls3-rs780e-pch.dtsi | 35 +++
arch/mips/boot/dts/loongson/ls3a-package.dtsi | 59 +++++
.../boot/dts/loongson/ls3a1000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a1000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a1000_780e_4way.dts | 13 ++
.../boot/dts/loongson/ls3a2000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a2000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a2000_780e_4way.dts | 13 ++
.../boot/dts/loongson/ls3a3000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a3000_780e_2way.dts | 13 ++
.../boot/dts/loongson/ls3a3000_780e_4way.dts | 13 ++
arch/mips/boot/dts/loongson/ls3b-package.dtsi | 59 +++++
.../mips/boot/dts/loongson/ls3b_780e_1way.dts | 13 ++
.../mips/boot/dts/loongson/ls3b_780e_2way.dts | 13 ++
arch/mips/include/asm/bootinfo.h | 1 -
arch/mips/include/asm/cop2.h | 2 +-
arch/mips/include/asm/cpu-type.h | 6 +-
arch/mips/include/asm/cpu.h | 4 +-
arch/mips/include/asm/hazards.h | 2 +-
arch/mips/include/asm/io.h | 2 +-
arch/mips/include/asm/irqflags.h | 2 +-
.../mach-loongson2ef/cpu-feature-overrides.h | 45 ++++
.../cs5536/cs5536.h | 0
.../cs5536/cs5536_mfgpt.h | 0
.../cs5536/cs5536_pci.h | 0
.../cs5536/cs5536_vsm.h | 0
.../loongson2ef.h} | 31 +--
.../machine.h | 6 -
.../mc146818rtc.h | 5 +-
.../mem.h | 6 +-
arch/mips/include/asm/mach-loongson2ef/pci.h | 43 ++++
.../include/asm/mach-loongson2ef/spaces.h | 10 +
.../asm/mach-loongson64/builtin_dtbs.h | 26 +++
.../mach-loongson64/cpu-feature-overrides.h | 3 -
arch/mips/include/asm/mach-loongson64/irq.h | 6 +-
.../asm/mach-loongson64/kernel-entry-init.h | 74 ------
.../include/asm/mach-loongson64/loongson64.h | 50 ++++
.../mips/include/asm/mach-loongson64/mmzone.h | 16 --
arch/mips/include/asm/mach-loongson64/pci.h | 41 +---
.../include/asm/mach-loongson64/workarounds.h | 4 +-
arch/mips/include/asm/module.h | 8 +-
arch/mips/include/asm/pgtable-bits.h | 2 +-
arch/mips/include/asm/processor.h | 2 +-
arch/mips/include/asm/r4kcache.h | 4 +-
arch/mips/kernel/cpu-probe.c | 14 +-
arch/mips/kernel/idle.c | 2 +-
arch/mips/kernel/perf_event_mipsxx.c | 4 +-
arch/mips/kernel/setup.c | 2 +-
arch/mips/kernel/traps.c | 2 +-
arch/mips/lib/csum_partial.S | 4 +-
arch/mips/loongson2ef/Kconfig | 93 ++++++++
arch/mips/loongson2ef/Makefile | 18 ++
arch/mips/loongson2ef/Platform | 32 +++
.../common/Makefile | 0
.../common/bonito-irq.c | 2 +-
.../common/cmdline.c | 2 +-
.../common/cs5536/Makefile | 0
.../common/cs5536/cs5536_acc.c | 0
.../common/cs5536/cs5536_ehci.c | 0
.../common/cs5536/cs5536_ide.c | 0
.../common/cs5536/cs5536_isa.c | 0
.../common/cs5536/cs5536_mfgpt.c | 0
.../common/cs5536/cs5536_ohci.c | 0
.../common/cs5536/cs5536_pci.c | 0
.../common/early_printk.c | 2 +-
arch/mips/loongson2ef/common/env.c | 71 ++++++
.../{loongson64 => loongson2ef}/common/init.c | 7 +-
.../{loongson64 => loongson2ef}/common/irq.c | 2 +-
.../common/machtype.c | 3 +-
.../{loongson64 => loongson2ef}/common/mem.c | 40 +---
.../{loongson64 => loongson2ef}/common/pci.c | 11 +-
.../common/platform.c | 0
.../{loongson64 => loongson2ef}/common/pm.c | 2 +-
.../common/reset.c | 23 +-
.../{loongson64 => loongson2ef}/common/rtc.c | 0
.../common/serial.c | 37 +--
.../common/setup.c | 2 +-
.../{loongson64 => loongson2ef}/common/time.c | 2 +-
.../common/uart_base.c | 10 +-
.../fuloong-2e/Makefile | 0
.../fuloong-2e/dma.c | 0
.../fuloong-2e/irq.c | 2 +-
.../fuloong-2e/reset.c | 2 +-
.../lemote-2f/Makefile | 0
.../lemote-2f/clock.c | 2 +-
.../lemote-2f/dma.c | 0
.../lemote-2f/ec_kb3310b.c | 0
.../lemote-2f/ec_kb3310b.h | 0
.../lemote-2f/irq.c | 2 +-
.../lemote-2f/machtype.c | 2 +-
.../lemote-2f/pm.c | 2 +-
.../lemote-2f/reset.c | 2 +-
arch/mips/loongson64/Kconfig | 126 +---------
arch/mips/loongson64/Makefile | 23 +-
arch/mips/loongson64/Platform | 36 +--
.../loongson64/{loongson-3 => }/acpi_init.c | 3 +-
.../loongson64/{loongson-3 => }/cop2-ex.c | 5 +-
arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +-
arch/mips/loongson64/{common => }/env.c | 139 ++++++-----
arch/mips/loongson64/{loongson-3 => }/hpet.c | 0
arch/mips/loongson64/irq.c | 27 +++
arch/mips/loongson64/loongson-3/Makefile | 11 -
arch/mips/loongson64/loongson-3/irq.c | 158 -------------
arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +-
arch/mips/loongson64/pci.c | 45 ++++
.../loongson64/{loongson-3 => }/platform.c | 0
arch/mips/loongson64/reset.c | 58 +++++
arch/mips/loongson64/setup.c | 107 +++++++++
arch/mips/loongson64/{loongson-3 => }/smp.c | 28 +--
arch/mips/loongson64/{loongson-3 => }/smp.h | 0
arch/mips/mm/c-r4k.c | 32 +--
arch/mips/mm/page.c | 2 +-
arch/mips/mm/tlb-r4k.c | 4 +-
arch/mips/mm/tlbex.c | 6 +-
arch/mips/oprofile/Makefile | 4 +-
arch/mips/oprofile/common.c | 4 +-
arch/mips/oprofile/op_model_loongson2.c | 2 +-
arch/mips/oprofile/op_model_loongson3.c | 2 +-
arch/mips/pci/Makefile | 2 +-
arch/mips/pci/fixup-fuloong2e.c | 2 +-
arch/mips/pci/fixup-lemote2f.c | 2 +-
arch/mips/pci/ops-loongson2.c | 2 +-
arch/mips/pci/ops-loongson3.c | 2 +-
drivers/cpufreq/loongson2_cpufreq.c | 2 +-
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-loongson.c | 4 +-
drivers/irqchip/Kconfig | 17 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-i8259.c | 47 +++-
drivers/irqchip/irq-ls3-htintc.c | 145 ++++++++++++
drivers/irqchip/irq-ls3-iointc.c | 216 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
drivers/platform/mips/cpu_hwmon.c | 2 +-
include/drm/drm_cache.h | 2 +-
148 files changed, 2064 insertions(+), 841 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/ls3-2nodes.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-4nodes.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-cpus.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464e.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3a-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3b-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_2way.dts
create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%)
rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%)
create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h
create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h
create mode 100644 arch/mips/loongson2ef/Kconfig
create mode 100644 arch/mips/loongson2ef/Makefile
create mode 100644 arch/mips/loongson2ef/Platform
rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%)
create mode 100644 arch/mips/loongson2ef/common/env.c
rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%)
rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%)
rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%)
rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%)
rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%)
rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%)
rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%)
rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%)
rename arch/mips/loongson64/{common => }/env.c (77%)
rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%)
create mode 100644 arch/mips/loongson64/irq.c
delete mode 100644 arch/mips/loongson64/loongson-3/Makefile
delete mode 100644 arch/mips/loongson64/loongson-3/irq.c
rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%)
create mode 100644 arch/mips/loongson64/pci.c
rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%)
create mode 100644 arch/mips/loongson64/reset.c
create mode 100644 arch/mips/loongson64/setup.c
rename arch/mips/loongson64/{loongson-3 => }/smp.c (98%)
rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%)
create mode 100644 drivers/irqchip/irq-ls3-htintc.c
create mode 100644 drivers/irqchip/irq-ls3-iointc.c
--
2.22.0
On 2019/8/27 下午8:45, Rob Herring wrote:
> On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <[email protected]> wrote:
>> Prepare for later dts.
>>
>> Signed-off-by: Jiaxun Yang <[email protected]>
>> ---
>> .../bindings/mips/loongson/cpus.yaml | 38 +++++++++++
>> .../bindings/mips/loongson/devices.yaml | 64 +++++++++++++++++++
>> 2 files changed, 102 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml
>> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
>> new file mode 100644
>> index 000000000000..410d896a0078
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
>> @@ -0,0 +1,38 @@
>> +# SPDX-License-Identifier: GPL-2.0
> Dual license for new bindings please:
>
> (GPL-2.0-only OR BSD-2-Clause)
>
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Loongson CPUs bindings
>> +
>> +maintainers:
>> + - Jiaxun Yang <[email protected]>
>> +
>> +description: |+
>> + The device tree allows to describe the layout of CPUs in a system through
>> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>> + defining properties for every cpu.
>> +
>> + Bindings for CPU nodes follow the Devicetree Specification, available from:
>> +
>> + https://www.devicetree.org/specifications/
>> +
>> +properties:
>> + reg:
>> + maxItems: 1
>> + description: |
>> + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum.
> Is this definition specific to Loongson CPUs or all MIPS?
Currently it's specific to Loongson CPU only, as other processors may
using different method to express CPU map.
Different from Arm, MIPS family of processors seems less uniform and
have their own designs.
For this point, we'd better ask Paul's opinion.
--
Jiaxun Yang
On 2019/8/27 下午9:25, 陈华才 wrote:
> Hi, Jiaxun,
Hi Huacai
Thanks for your response.
>
> 1, To describe CPU I prefer "loongson" to "ls" because "ls" is confusing, and in future we will use ls2h/ls7a to describe Loongson's bridge.
"Loongson" seems too long in some cases, for DeviceTree Bindings, it
will also delicate with vendor String.
As you can see on Loongson's official website
[http://loongson.cn/product/cpu/3/3A3000.html], "LS3A3000" had been
written on the chip as the model name.
In my opinion, "ls3" is a proper abbreviation of Loongson-3 processors.
But it's fine for me to convert "ls" to "loongson" if all people agree
with this.
Btw: I don't think it's a good idea to bring Loongson-2H PCH support to
mainline, as we can see the vendor code have a lot of dirty hacks that
are totally unacceptable to us.
> 2, I think it is better to use loongson64c/loongson64g than loongson2ef/loongson64. As we disscussed, we will use PRID_IMP_LOONGSON_64C/PRID_IMP_LOONGSON_64G to describe 0x6300/0xc000.
Our discussion was limited on PRID. However, Early Loongson-3A/B
processors is sharing the same PRID_IMP with Loongson-2E/F.
It may lead to confusion if we're using the same way to express totally
different contents.
Notice me if any one have better idea on how to express loongson2ef
family machines.
--
Jiaxun Yang
> Huacai
>
>
>
> ------------------ Original ------------------
> From: "Jiaxun Yang"<[email protected]>;Date: Tue, Aug 27, 2019 04:52 PMTo: "linux-mips"<[email protected]>; Cc: "chenhc"<[email protected]>; "paul.burton"<[email protected]>; "tglx"<[email protected]>; "jason"<[email protected]>; "maz"<[email protected]>; "linux-kernel"<[email protected]>; "robh+dt"<[email protected]>; "mark.rutland"<[email protected]>; "devicetree"<[email protected]>; "Jiaxun Yang"<[email protected]>; Subject: [PATCH 00/13] Modernize Loongson64 Machine Loongson have a long history of contributing their code to mainline kernel.
> However, it seems like recent years, they are focusing on maintain a kernel by themselves
> rather than contribute there code to the community.
>
> Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
> maintainance and became outdated.
>
> This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
> Loongson 2e/f alone since they are too legacy to touch.
>
>
> Jiaxun Yang (13):
> MIPS: Loongson64: Rename CPU TYPES
> MIPS: Loongson64: Sepreate loongson2ef/loongson64 code
> MAINTAINERS: Fix entries for new loongson64 path
> irqchip: Add driver for Loongson-3 I/O interrupt controller
> dt-bindings: interrupt-controller: Add Loongson-3 IOINTC
> irqchip: Add driver for Loongson-3 HyperTransport interrupt controller
> dt-bindings: interrupt-controller: Add Loongson-3 HTINTC
> irqchip: i8259: Add plat-poll support
> irqchip: mips-cpu: Convert to simple domain
> MIPS: Loongson64: Drop legacy IRQ code
> dt-bindings: mips: Add loongson cpus & boards
> MIPS: Loongson64: Add generic dts
> MIPS: Loongson64: Load built-in dtbs
>
> .../loongson,ls3-htintc.yaml | 53 +++++
> .../loongson,ls3-iointc.yaml | 61 +++++
> .../bindings/mips/loongson/cpus.yaml | 38 +++
> .../bindings/mips/loongson/devices.yaml | 64 ++++++
> MAINTAINERS | 9 +-
> arch/mips/Kbuild.platforms | 1 +
> arch/mips/Kconfig | 83 +++++--
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/loongson/Makefile | 8 +
> arch/mips/boot/dts/loongson/ls3-2nodes.dtsi | 8 +
> arch/mips/boot/dts/loongson/ls3-4nodes.dtsi | 15 ++
> arch/mips/boot/dts/loongson/ls3-cpus.dtsi | 150 ++++++++++++
> arch/mips/boot/dts/loongson/ls3-gs464.dtsi | 18 ++
> arch/mips/boot/dts/loongson/ls3-gs464e.dtsi | 18 ++
> .../boot/dts/loongson/ls3-rs780e-pch.dtsi | 35 +++
> arch/mips/boot/dts/loongson/ls3a-package.dtsi | 59 +++++
> .../boot/dts/loongson/ls3a1000_780e_1way.dts | 12 +
> .../boot/dts/loongson/ls3a1000_780e_2way.dts | 13 ++
> .../boot/dts/loongson/ls3a1000_780e_4way.dts | 13 ++
> .../boot/dts/loongson/ls3a2000_780e_1way.dts | 12 +
> .../boot/dts/loongson/ls3a2000_780e_2way.dts | 13 ++
> .../boot/dts/loongson/ls3a2000_780e_4way.dts | 13 ++
> .../boot/dts/loongson/ls3a3000_780e_1way.dts | 12 +
> .../boot/dts/loongson/ls3a3000_780e_2way.dts | 13 ++
> .../boot/dts/loongson/ls3a3000_780e_4way.dts | 13 ++
> arch/mips/boot/dts/loongson/ls3b-package.dtsi | 59 +++++
> .../mips/boot/dts/loongson/ls3b_780e_1way.dts | 13 ++
> .../mips/boot/dts/loongson/ls3b_780e_2way.dts | 13 ++
> arch/mips/include/asm/bootinfo.h | 1 -
> arch/mips/include/asm/cop2.h | 2 +-
> arch/mips/include/asm/cpu-type.h | 6 +-
> arch/mips/include/asm/cpu.h | 4 +-
> arch/mips/include/asm/hazards.h | 2 +-
> arch/mips/include/asm/io.h | 2 +-
> arch/mips/include/asm/irqflags.h | 2 +-
> .../mach-loongson2ef/cpu-feature-overrides.h | 45 ++++
> .../cs5536/cs5536.h | 0
> .../cs5536/cs5536_mfgpt.h | 0
> .../cs5536/cs5536_pci.h | 0
> .../cs5536/cs5536_vsm.h | 0
> .../loongson2ef.h} | 31 +--
> .../machine.h | 6 -
> .../mc146818rtc.h | 5 +-
> .../mem.h | 6 +-
> arch/mips/include/asm/mach-loongson2ef/pci.h | 43 ++++
> .../include/asm/mach-loongson2ef/spaces.h | 10 +
> .../asm/mach-loongson64/builtin_dtbs.h | 26 +++
> .../mach-loongson64/cpu-feature-overrides.h | 3 -
> arch/mips/include/asm/mach-loongson64/irq.h | 6 +-
> .../asm/mach-loongson64/kernel-entry-init.h | 74 ------
> .../include/asm/mach-loongson64/loongson64.h | 50 ++++
> .../mips/include/asm/mach-loongson64/mmzone.h | 16 --
> arch/mips/include/asm/mach-loongson64/pci.h | 41 +---
> .../include/asm/mach-loongson64/workarounds.h | 4 +-
> arch/mips/include/asm/module.h | 8 +-
> arch/mips/include/asm/pgtable-bits.h | 2 +-
> arch/mips/include/asm/processor.h | 2 +-
> arch/mips/include/asm/r4kcache.h | 4 +-
> arch/mips/kernel/cpu-probe.c | 14 +-
> arch/mips/kernel/idle.c | 2 +-
> arch/mips/kernel/perf_event_mipsxx.c | 4 +-
> arch/mips/kernel/setup.c | 2 +-
> arch/mips/kernel/traps.c | 2 +-
> arch/mips/lib/csum_partial.S | 4 +-
> arch/mips/loongson2ef/Kconfig | 93 ++++++++
> arch/mips/loongson2ef/Makefile | 18 ++
> arch/mips/loongson2ef/Platform | 32 +++
> .../common/Makefile | 0
> .../common/bonito-irq.c | 2 +-
> .../common/cmdline.c | 2 +-
> .../common/cs5536/Makefile | 0
> .../common/cs5536/cs5536_acc.c | 0
> .../common/cs5536/cs5536_ehci.c | 0
> .../common/cs5536/cs5536_ide.c | 0
> .../common/cs5536/cs5536_isa.c | 0
> .../common/cs5536/cs5536_mfgpt.c | 0
> .../common/cs5536/cs5536_ohci.c | 0
> .../common/cs5536/cs5536_pci.c | 0
> .../common/early_printk.c | 2 +-
> arch/mips/loongson2ef/common/env.c | 71 ++++++
> .../{loongson64 => loongson2ef}/common/init.c | 7 +-
> .../{loongson64 => loongson2ef}/common/irq.c | 2 +-
> .../common/machtype.c | 3 +-
> .../{loongson64 => loongson2ef}/common/mem.c | 40 +---
> .../{loongson64 => loongson2ef}/common/pci.c | 11 +-
> .../common/platform.c | 0
> .../{loongson64 => loongson2ef}/common/pm.c | 2 +-
> .../common/reset.c | 23 +-
> .../{loongson64 => loongson2ef}/common/rtc.c | 0
> .../common/serial.c | 37 +--
> .../common/setup.c | 2 +-
> .../{loongson64 => loongson2ef}/common/time.c | 2 +-
> .../common/uart_base.c | 10 +-
> .../fuloong-2e/Makefile | 0
> .../fuloong-2e/dma.c | 0
> .../fuloong-2e/irq.c | 2 +-
> .../fuloong-2e/reset.c | 2 +-
> .../lemote-2f/Makefile | 0
> .../lemote-2f/clock.c | 2 +-
> .../lemote-2f/dma.c | 0
> .../lemote-2f/ec_kb3310b.c | 0
> .../lemote-2f/ec_kb3310b.h | 0
> .../lemote-2f/irq.c | 2 +-
> .../lemote-2f/machtype.c | 2 +-
> .../lemote-2f/pm.c | 2 +-
> .../lemote-2f/reset.c | 2 +-
> arch/mips/loongson64/Kconfig | 126 +---------
> arch/mips/loongson64/Makefile | 23 +-
> arch/mips/loongson64/Platform | 36 +--
> .../loongson64/{loongson-3 => }/acpi_init.c | 3 +-
> .../loongson64/{loongson-3 => }/cop2-ex.c | 5 +-
> arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +-
> arch/mips/loongson64/{common => }/env.c | 139 ++++++-----
> arch/mips/loongson64/{loongson-3 => }/hpet.c | 0
> arch/mips/loongson64/irq.c | 27 +++
> arch/mips/loongson64/loongson-3/Makefile | 11 -
> arch/mips/loongson64/loongson-3/irq.c | 158 -------------
> arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +-
> arch/mips/loongson64/pci.c | 45 ++++
> .../loongson64/{loongson-3 => }/platform.c | 0
> arch/mips/loongson64/reset.c | 58 +++++
> arch/mips/loongson64/setup.c | 107 +++++++++
> arch/mips/loongson64/{loongson-3 => }/smp.c | 28 +--
> arch/mips/loongson64/{loongson-3 => }/smp.h | 0
> arch/mips/mm/c-r4k.c | 32 +--
> arch/mips/mm/page.c | 2 +-
> arch/mips/mm/tlb-r4k.c | 4 +-
> arch/mips/mm/tlbex.c | 6 +-
> arch/mips/oprofile/Makefile | 4 +-
> arch/mips/oprofile/common.c | 4 +-
> arch/mips/oprofile/op_model_loongson2.c | 2 +-
> arch/mips/oprofile/op_model_loongson3.c | 2 +-
> arch/mips/pci/Makefile | 2 +-
> arch/mips/pci/fixup-fuloong2e.c | 2 +-
> arch/mips/pci/fixup-lemote2f.c | 2 +-
> arch/mips/pci/ops-loongson2.c | 2 +-
> arch/mips/pci/ops-loongson3.c | 2 +-
> drivers/cpufreq/loongson2_cpufreq.c | 2 +-
> drivers/gpio/Kconfig | 2 +-
> drivers/gpio/gpio-loongson.c | 4 +-
> drivers/irqchip/Kconfig | 17 ++
> drivers/irqchip/Makefile | 2 +
> drivers/irqchip/irq-i8259.c | 47 +++-
> drivers/irqchip/irq-ls3-htintc.c | 145 ++++++++++++
> drivers/irqchip/irq-ls3-iointc.c | 216 ++++++++++++++++++
> drivers/irqchip/irq-mips-cpu.c | 2 +-
> drivers/platform/mips/cpu_hwmon.c | 2 +-
> include/drm/drm_cache.h | 2 +-
> 148 files changed, 2064 insertions(+), 841 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
> create mode 100644 arch/mips/boot/dts/loongson/Makefile
> create mode 100644 arch/mips/boot/dts/loongson/ls3-2nodes.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/ls3-4nodes.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/ls3-cpus.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464e.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/ls3a-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3b-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_1way.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_2way.dts
> create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%)
> rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%)
> create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h
> create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h
> create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
> delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h
> create mode 100644 arch/mips/loongson2ef/Kconfig
> create mode 100644 arch/mips/loongson2ef/Makefile
> create mode 100644 arch/mips/loongson2ef/Platform
> rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%)
> create mode 100644 arch/mips/loongson2ef/common/env.c
> rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%)
> rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%)
> rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%)
> rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%)
> rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%)
> rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%)
> rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%)
> rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%)
> rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%)
> rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%)
> rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%)
> rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%)
> rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%)
> rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%)
> rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%)
> rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%)
> rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%)
> rename arch/mips/loongson64/{common => }/env.c (77%)
> rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%)
> create mode 100644 arch/mips/loongson64/irq.c
> delete mode 100644 arch/mips/loongson64/loongson-3/Makefile
> delete mode 100644 arch/mips/loongson64/loongson-3/irq.c
> rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%)
> create mode 100644 arch/mips/loongson64/pci.c
> rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%)
> create mode 100644 arch/mips/loongson64/reset.c
> create mode 100644 arch/mips/loongson64/setup.c
> rename arch/mips/loongson64/{loongson-3 => }/smp.c (98%)
> rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%)
> create mode 100644 drivers/irqchip/irq-ls3-htintc.c
> create mode 100644 drivers/irqchip/irq-ls3-iointc.c
>
Hi guys,
On Tue, Aug 27, 2019 at 10:18:46PM +0800, Jiaxun Yang wrote:
> On 2019/8/27 下午8:45, Rob Herring wrote:
> > On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <[email protected]> wrote:
> > > diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> > > new file mode 100644
> > > index 000000000000..410d896a0078
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> > > @@ -0,0 +1,38 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> > Dual license for new bindings please:
> >
> > (GPL-2.0-only OR BSD-2-Clause)
> >
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Loongson CPUs bindings
> > > +
> > > +maintainers:
> > > + - Jiaxun Yang <[email protected]>
> > > +
> > > +description: |+
> > > + The device tree allows to describe the layout of CPUs in a system through
> > > + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > > + defining properties for every cpu.
> > > +
> > > + Bindings for CPU nodes follow the Devicetree Specification, available from:
> > > +
> > > + https://www.devicetree.org/specifications/
> > > +
> > > +properties:
> > > + reg:
> > > + maxItems: 1
> > > + description: |
> > > + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum.
> > Is this definition specific to Loongson CPUs or all MIPS?
>
> Currently it's specific to Loongson CPU only, as other processors may using
> different method to express CPU map.
>
> Different from Arm, MIPS family of processors seems less uniform and have
> their own designs.
>
> For this point, we'd better ask Paul's opinion.
In general on MIPS we detect CPU properties at runtime from coprocessor
0 registers & similar sources of information, so there's not really a
need to specify anything about the CPU in devicetree. For example here
you say yourself that the value for this property can be read from
EBase.CPUNum - so why specify it in DT?
Thanks,
Paul
Hi,
On Tue, Aug 27, 2019 at 04:52:51PM +0800, Jiaxun Yang wrote:
> As later model of GSx64 family processors including 2-series-soc have
> similar design with initial loongson3a while loongson2e/f seems less
> identical, we seprate loongson2e/f support code out of mach-loongson64
^^^^^^^
separate (typo in patch title as well)
> to make our life easier.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
[...]
> +config MACH_LOONGSON2EF
You need to update lemote2f_defconfig with his patch.
A.
On 2019/8/28 上午4:41, Paul Burton wrote:
> Hi guys,
>
> On Tue, Aug 27, 2019 at 10:18:46PM +0800, Jiaxun Yang wrote:
>> On 2019/8/27 下午8:45, Rob Herring wrote:
>>> On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <[email protected]> wrote:
>>>> diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
>>>> new file mode 100644
>>>> index 000000000000..410d896a0078
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
>>>> @@ -0,0 +1,38 @@
>>>> +# SPDX-License-Identifier: GPL-2.0
>>> Dual license for new bindings please:
>>>
>>> (GPL-2.0-only OR BSD-2-Clause)
>>>
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Loongson CPUs bindings
>>>> +
>>>> +maintainers:
>>>> + - Jiaxun Yang <[email protected]>
>>>> +
>>>> +description: |+
>>>> + The device tree allows to describe the layout of CPUs in a system through
>>>> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>>>> + defining properties for every cpu.
>>>> +
>>>> + Bindings for CPU nodes follow the Devicetree Specification, available from:
>>>> +
>>>> + https://www.devicetree.org/specifications/
>>>> +
>>>> +properties:
>>>> + reg:
>>>> + maxItems: 1
>>>> + description: |
>>>> + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum.
>>> Is this definition specific to Loongson CPUs or all MIPS?
>> Currently it's specific to Loongson CPU only, as other processors may using
>> different method to express CPU map.
>>
>> Different from Arm, MIPS family of processors seems less uniform and have
>> their own designs.
>>
>> For this point, we'd better ask Paul's opinion.
> In general on MIPS we detect CPU properties at runtime from coprocessor
> 0 registers & similar sources of information, so there's not really a
> need to specify anything about the CPU in devicetree. For example here
> you say yourself that the value for this property can be read from
> EBase.CPUNum - so why specify it in DT?
Hi Paul,
CPU itself doesn't have to expressed by DT, but other nodes (like NUMA)
will use CPU Node to determine the physical core.
Also CPU Node can be used to express the total number of CPUs. We need
this property to bind a CPU Node to a fixed core.
Or we'd better describe "reg" as "Physical Core ID" rather than specify
"EBase.CPUNum"?
--
Jiaxun Yang
>
> Thanks,
> Paul
On 2019/8/28 上午6:05, Aaro Koskinen wrote:
> Hi,
>
> On Tue, Aug 27, 2019 at 04:52:51PM +0800, Jiaxun Yang wrote:
>> As later model of GSx64 family processors including 2-series-soc have
>> similar design with initial loongson3a while loongson2e/f seems less
>> identical, we seprate loongson2e/f support code out of mach-loongson64
> ^^^^^^^
>
> separate (typo in patch title as well)
>
>> to make our life easier.
>>
>> Signed-off-by: Jiaxun Yang <[email protected]>
> [...]
>
>> +config MACH_LOONGSON2EF
Hi Aaro,
> You need to update lemote2f_defconfig with his patch.
How to generate this config? We should not edit it manually right?
Thanks
--
Jiaxun Yang
> A.
v1:
- dt-bindings fixup according to Rob's comments
- irqchip fixup according to Marc's comments
- ls3-iointc: Make Core&IP map per-IRQ
- Regenerate kconfigs
- Typo & style improvements
Jiaxun Yang (18):
MIPS: Loongson64: Rename CPU TYPES
MIPS: Loongson64: separate loongson2ef/loongson64 code
MAINTAINERS: Fix entries for new loongson64 path
irqchip: Export generic chip domain map/unmap functions
irqchip: Add driver for Loongson-3 I/O interrupt controller
dt-bindings: interrupt-controller: Add Loongson-3 IOINTC
irqchip: Add driver for Loongson-3 HyperTransport interrupt controller
dt-bindings: interrupt-controller: Add Loongson-3 HTINTC
irqchip: i8259: Add plat-poll support
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson cpus & boards
dt-bindings: Document loongson vendor-prefix
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
MIPS: Loongson: Regenerate defconfigs
MAINTAINERS: Add new pathes to LOONGSON64 ARCHITECTURE
MAINTAINERS: Add myself as maintainer of LOONGSON64
.../loongson,ls3-htintc.yaml | 55 ++++
.../loongson,ls3-iointc.yaml | 75 +++++
.../bindings/mips/loongson/cpus.yaml | 38 +++
.../bindings/mips/loongson/devices.yaml | 64 ++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 13 +-
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 83 ++++--
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 8 +
arch/mips/boot/dts/loongson/ls3-2nodes.dtsi | 8 +
arch/mips/boot/dts/loongson/ls3-4nodes.dtsi | 15 +
arch/mips/boot/dts/loongson/ls3-cpus.dtsi | 150 ++++++++++
arch/mips/boot/dts/loongson/ls3-gs464.dtsi | 18 ++
arch/mips/boot/dts/loongson/ls3-gs464e.dtsi | 18 ++
.../boot/dts/loongson/ls3-rs780e-pch.dtsi | 35 +++
arch/mips/boot/dts/loongson/ls3a-package.dtsi | 59 ++++
.../boot/dts/loongson/ls3a1000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a1000_780e_2way.dts | 13 +
.../boot/dts/loongson/ls3a1000_780e_4way.dts | 13 +
.../boot/dts/loongson/ls3a2000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a2000_780e_2way.dts | 13 +
.../boot/dts/loongson/ls3a2000_780e_4way.dts | 13 +
.../boot/dts/loongson/ls3a3000_780e_1way.dts | 12 +
.../boot/dts/loongson/ls3a3000_780e_2way.dts | 13 +
.../boot/dts/loongson/ls3a3000_780e_4way.dts | 13 +
arch/mips/boot/dts/loongson/ls3b-package.dtsi | 59 ++++
.../mips/boot/dts/loongson/ls3b_780e_1way.dts | 13 +
.../mips/boot/dts/loongson/ls3b_780e_2way.dts | 13 +
arch/mips/configs/fuloong2e_defconfig | 8 +-
arch/mips/configs/lemote2f_defconfig | 8 +-
arch/mips/configs/loongson3_defconfig | 12 +-
arch/mips/include/asm/bootinfo.h | 1 -
arch/mips/include/asm/cop2.h | 2 +-
arch/mips/include/asm/cpu-type.h | 6 +-
arch/mips/include/asm/cpu.h | 4 +-
arch/mips/include/asm/hazards.h | 2 +-
arch/mips/include/asm/io.h | 2 +-
arch/mips/include/asm/irqflags.h | 2 +-
.../mach-loongson2ef/cpu-feature-overrides.h | 45 +++
.../cs5536/cs5536.h | 0
.../cs5536/cs5536_mfgpt.h | 0
.../cs5536/cs5536_pci.h | 0
.../cs5536/cs5536_vsm.h | 0
.../loongson2ef.h} | 31 +-
.../machine.h | 6 -
.../mc146818rtc.h | 5 +-
.../mem.h | 6 +-
arch/mips/include/asm/mach-loongson2ef/pci.h | 43 +++
.../include/asm/mach-loongson2ef/spaces.h | 10 +
.../asm/mach-loongson64/builtin_dtbs.h | 26 ++
.../mach-loongson64/cpu-feature-overrides.h | 3 -
arch/mips/include/asm/mach-loongson64/irq.h | 6 +-
.../asm/mach-loongson64/kernel-entry-init.h | 74 -----
.../include/asm/mach-loongson64/loongson64.h | 50 ++++
.../mips/include/asm/mach-loongson64/mmzone.h | 16 -
arch/mips/include/asm/mach-loongson64/pci.h | 41 +--
.../include/asm/mach-loongson64/workarounds.h | 4 +-
arch/mips/include/asm/module.h | 8 +-
arch/mips/include/asm/pgtable-bits.h | 2 +-
arch/mips/include/asm/processor.h | 2 +-
arch/mips/include/asm/r4kcache.h | 4 +-
arch/mips/kernel/cpu-probe.c | 14 +-
arch/mips/kernel/idle.c | 2 +-
arch/mips/kernel/perf_event_mipsxx.c | 4 +-
arch/mips/kernel/setup.c | 2 +-
arch/mips/kernel/traps.c | 2 +-
arch/mips/lib/csum_partial.S | 4 +-
arch/mips/loongson2ef/Kconfig | 93 ++++++
arch/mips/loongson2ef/Makefile | 18 ++
arch/mips/loongson2ef/Platform | 32 ++
.../common/Makefile | 0
.../common/bonito-irq.c | 2 +-
.../common/cmdline.c | 2 +-
.../common/cs5536/Makefile | 0
.../common/cs5536/cs5536_acc.c | 0
.../common/cs5536/cs5536_ehci.c | 0
.../common/cs5536/cs5536_ide.c | 0
.../common/cs5536/cs5536_isa.c | 0
.../common/cs5536/cs5536_mfgpt.c | 0
.../common/cs5536/cs5536_ohci.c | 0
.../common/cs5536/cs5536_pci.c | 0
.../common/early_printk.c | 2 +-
arch/mips/loongson2ef/common/env.c | 71 +++++
.../{loongson64 => loongson2ef}/common/init.c | 7 +-
.../{loongson64 => loongson2ef}/common/irq.c | 2 +-
.../common/machtype.c | 3 +-
.../{loongson64 => loongson2ef}/common/mem.c | 40 +--
.../{loongson64 => loongson2ef}/common/pci.c | 11 +-
.../common/platform.c | 0
.../{loongson64 => loongson2ef}/common/pm.c | 2 +-
.../common/reset.c | 23 +-
.../{loongson64 => loongson2ef}/common/rtc.c | 0
.../common/serial.c | 37 +--
.../common/setup.c | 2 +-
.../{loongson64 => loongson2ef}/common/time.c | 2 +-
.../common/uart_base.c | 10 +-
.../fuloong-2e/Makefile | 0
.../fuloong-2e/dma.c | 0
.../fuloong-2e/irq.c | 2 +-
.../fuloong-2e/reset.c | 2 +-
.../lemote-2f/Makefile | 0
.../lemote-2f/clock.c | 2 +-
.../lemote-2f/dma.c | 0
.../lemote-2f/ec_kb3310b.c | 0
.../lemote-2f/ec_kb3310b.h | 0
.../lemote-2f/irq.c | 2 +-
.../lemote-2f/machtype.c | 2 +-
.../lemote-2f/pm.c | 2 +-
.../lemote-2f/reset.c | 2 +-
arch/mips/loongson64/Kconfig | 126 +-------
arch/mips/loongson64/Makefile | 23 +-
arch/mips/loongson64/Platform | 36 +--
.../loongson64/{loongson-3 => }/acpi_init.c | 3 +-
.../loongson64/{loongson-3 => }/cop2-ex.c | 5 +-
arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +-
arch/mips/loongson64/{common => }/env.c | 139 +++++----
arch/mips/loongson64/{loongson-3 => }/hpet.c | 0
arch/mips/loongson64/irq.c | 27 ++
arch/mips/loongson64/loongson-3/Makefile | 11 -
arch/mips/loongson64/loongson-3/irq.c | 158 ----------
arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +-
arch/mips/loongson64/pci.c | 45 +++
.../loongson64/{loongson-3 => }/platform.c | 0
arch/mips/loongson64/reset.c | 58 ++++
arch/mips/loongson64/setup.c | 107 +++++++
arch/mips/loongson64/{loongson-3 => }/smp.c | 28 +-
arch/mips/loongson64/{loongson-3 => }/smp.h | 0
arch/mips/mm/c-r4k.c | 32 +-
arch/mips/mm/page.c | 2 +-
arch/mips/mm/tlb-r4k.c | 4 +-
arch/mips/mm/tlbex.c | 6 +-
arch/mips/oprofile/Makefile | 4 +-
arch/mips/oprofile/common.c | 4 +-
arch/mips/oprofile/op_model_loongson2.c | 2 +-
arch/mips/oprofile/op_model_loongson3.c | 2 +-
arch/mips/pci/Makefile | 2 +-
arch/mips/pci/fixup-fuloong2e.c | 2 +-
arch/mips/pci/fixup-lemote2f.c | 2 +-
arch/mips/pci/ops-loongson2.c | 2 +-
arch/mips/pci/ops-loongson3.c | 2 +-
drivers/cpufreq/loongson2_cpufreq.c | 2 +-
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-loongson.c | 4 +-
drivers/irqchip/Kconfig | 17 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-i8259.c | 47 ++-
drivers/irqchip/irq-ls3-htintc.c | 147 ++++++++++
drivers/irqchip/irq-ls3-iointc.c | 275 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
drivers/platform/mips/cpu_hwmon.c | 2 +-
include/drm/drm_cache.h | 2 +-
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 4 +-
154 files changed, 2160 insertions(+), 861 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/ls3-2nodes.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-4nodes.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-cpus.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-gs464e.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3-rs780e-pch.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3a-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a1000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a2000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_2way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3a3000_780e_4way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3b-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_1way.dts
create mode 100644 arch/mips/boot/dts/loongson/ls3b_780e_2way.dts
create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%)
rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%)
create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h
create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h
create mode 100644 arch/mips/loongson2ef/Kconfig
create mode 100644 arch/mips/loongson2ef/Makefile
create mode 100644 arch/mips/loongson2ef/Platform
rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%)
create mode 100644 arch/mips/loongson2ef/common/env.c
rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%)
rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%)
rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%)
rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%)
rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%)
rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%)
rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%)
rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%)
rename arch/mips/loongson64/{common => }/env.c (77%)
rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%)
create mode 100644 arch/mips/loongson64/irq.c
delete mode 100644 arch/mips/loongson64/loongson-3/Makefile
delete mode 100644 arch/mips/loongson64/loongson-3/irq.c
rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%)
create mode 100644 arch/mips/loongson64/pci.c
rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%)
create mode 100644 arch/mips/loongson64/reset.c
create mode 100644 arch/mips/loongson64/setup.c
rename arch/mips/loongson64/{loongson-3 => }/smp.c (98%)
rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%)
create mode 100644 drivers/irqchip/irq-ls3-htintc.c
create mode 100644 drivers/irqchip/irq-ls3-iointc.c
--
2.22.0
CPU_LOONGSON2 -> CPU_LOONGSON2EF
CPU_LOONGSON3 -> CPU_LOONGSON64
As newer loongson-2 products (2G/2H/2K1000) can share kernel
implementation with loongson-3 while 2E/2F are less similar with
other LOONGSON64 products.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 28 ++++++++--------
arch/mips/include/asm/cop2.h | 2 +-
arch/mips/include/asm/cpu-type.h | 6 ++--
arch/mips/include/asm/cpu.h | 4 +--
arch/mips/include/asm/hazards.h | 2 +-
arch/mips/include/asm/io.h | 2 +-
arch/mips/include/asm/irqflags.h | 2 +-
.../mach-loongson64/cpu-feature-overrides.h | 2 +-
arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
.../asm/mach-loongson64/kernel-entry-init.h | 4 +--
.../include/asm/mach-loongson64/loongson.h | 2 +-
arch/mips/include/asm/mach-loongson64/pci.h | 2 +-
arch/mips/include/asm/module.h | 8 ++---
arch/mips/include/asm/pgtable-bits.h | 2 +-
arch/mips/include/asm/processor.h | 2 +-
arch/mips/include/asm/r4kcache.h | 4 +--
arch/mips/kernel/cpu-probe.c | 14 ++++----
arch/mips/kernel/idle.c | 2 +-
arch/mips/kernel/perf_event_mipsxx.c | 4 +--
arch/mips/kernel/setup.c | 2 +-
arch/mips/kernel/traps.c | 2 +-
arch/mips/lib/csum_partial.S | 4 +--
arch/mips/loongson64/Kconfig | 2 +-
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/Platform | 12 +++----
arch/mips/loongson64/common/pci.c | 2 +-
arch/mips/mm/c-r4k.c | 32 +++++++++----------
arch/mips/mm/page.c | 2 +-
arch/mips/mm/tlb-r4k.c | 4 +--
arch/mips/mm/tlbex.c | 6 ++--
arch/mips/oprofile/Makefile | 4 +--
arch/mips/oprofile/common.c | 4 +--
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-loongson.c | 2 +-
include/drm/drm_cache.h | 2 +-
35 files changed, 89 insertions(+), 89 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d50fafd7bf3a..cbc76f00d1fc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1367,9 +1367,9 @@ choice
prompt "CPU type"
default CPU_R4X00
-config CPU_LOONGSON3
- bool "Loongson 3 CPU"
- depends on SYS_HAS_CPU_LOONGSON3
+config CPU_LOONGSON64
+ bool "Loongson GSx64 Family CPU"
+ depends on SYS_HAS_CPU_LOONGSON64
select ARCH_HAS_PHYS_TO_DMA
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1382,15 +1382,15 @@ config CPU_LOONGSON3
select GPIOLIB
select SWIOTLB
help
- The Loongson 3 processor implements the MIPS64R2 instruction
- set with many extensions.
+ The Loongson GSx64 Family cores including Loongson-3A/3B/2series-soc
+ implements the MIPS64R2 instruction set with many extensions.
config LOONGSON3_ENHANCEMENT
bool "New Loongson 3 CPU Enhancements"
default n
select CPU_MIPSR2
select CPU_HAS_PREFETCH
- depends on CPU_LOONGSON3
+ depends on CPU_LOONGSON64
help
New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
@@ -1406,7 +1406,7 @@ config LOONGSON3_ENHANCEMENT
config CPU_LOONGSON3_WORKAROUNDS
bool "Old Loongson 3 LLSC Workarounds"
default y if SMP
- depends on CPU_LOONGSON3
+ depends on CPU_LOONGSON64
help
Loongson 3 processors have the llsc issues which require workarounds.
Without workarounds the system may hang unexpectedly.
@@ -1421,7 +1421,7 @@ config CPU_LOONGSON3_WORKAROUNDS
config CPU_LOONGSON2E
bool "Loongson 2E"
depends on SYS_HAS_CPU_LOONGSON2E
- select CPU_LOONGSON2
+ select CPU_LOONGSON2EF
help
The Loongson 2E processor implements the MIPS III instruction set
with many extensions.
@@ -1432,7 +1432,7 @@ config CPU_LOONGSON2E
config CPU_LOONGSON2F
bool "Loongson 2F"
depends on SYS_HAS_CPU_LOONGSON2F
- select CPU_LOONGSON2
+ select CPU_LOONGSON2EF
select GPIOLIB
help
The Loongson 2F processor implements the MIPS III instruction set
@@ -1870,7 +1870,7 @@ config SYS_SUPPORTS_ZBOOT_UART_PROM
bool
select SYS_SUPPORTS_ZBOOT
-config CPU_LOONGSON2
+config CPU_LOONGSON2EF
bool
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
@@ -1913,7 +1913,7 @@ config CPU_BMIPS5000
select SYS_SUPPORTS_HOTPLUG_CPU
select CPU_HAS_RIXI
-config SYS_HAS_CPU_LOONGSON3
+config SYS_HAS_CPU_LOONGSON64
bool
select CPU_SUPPORTS_CPUFREQ
select CPU_HAS_RIXI
@@ -2183,7 +2183,7 @@ choice
config PAGE_SIZE_4KB
bool "4kB"
- depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
+ depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
help
This option select the standard 4kB Linux page size. On some
R3000-family processors this is the only available page size. Using
@@ -2631,7 +2631,7 @@ config CPU_SUPPORTS_MSA
config ARCH_FLATMEM_ENABLE
def_bool y
- depends on !NUMA && !CPU_LOONGSON2
+ depends on !NUMA && !CPU_LOONGSON2EF
config ARCH_DISCONTIGMEM_ENABLE
bool
@@ -2721,7 +2721,7 @@ config NODES_SHIFT
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
- depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
+ depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
default y
help
Enable hardware performance counter support for perf events. If
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 63b3468ede4c..6b7396a6a115 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -33,7 +33,7 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);
#define cop2_present 1
#define cop2_lazy_restore 0
-#elif defined(CONFIG_CPU_LOONGSON3)
+#elif defined(CONFIG_CPU_LOONGSON64)
#define cop2_present 1
#define cop2_lazy_restore 1
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index a45af3de075d..3d8911f8252b 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -17,11 +17,11 @@ static inline int __pure __get_cpu_type(const int cpu_type)
switch (cpu_type) {
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
#endif
-#ifdef CONFIG_SYS_HAS_CPU_LOONGSON3
- case CPU_LOONGSON3:
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON64
+ case CPU_LOONGSON64:
#endif
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 290369fa44a4..9f30234b2a3d 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -322,8 +322,8 @@ enum cpu_type_enum {
/*
* MIPS64 class processors
*/
- CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
- CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,
+ CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
CPU_QEMU_GENERIC,
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 0fa27446869a..a4f48b0f5541 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -158,7 +158,7 @@ do { \
} while (0)
#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
- defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
+ defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
/*
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 97a280640daf..173801d04faa 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -317,7 +317,7 @@ static inline void iounmap(const volatile void __iomem *addr)
#undef __IS_KSEG1
}
-#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
#define war_io_reorder_wmb() wmb()
#else
#define war_io_reorder_wmb() barrier()
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index f0b862a83816..4d742acf2be0 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -41,7 +41,7 @@ static inline unsigned long arch_local_irq_save(void)
" .set push \n"
" .set reorder \n"
" .set noat \n"
-#if defined(CONFIG_CPU_LOONGSON3) || defined (CONFIG_CPU_LOONGSON1)
+#if defined(CONFIG_CPU_LOONGSON64) || defined (CONFIG_CPU_LOONGSON1)
" mfc0 %[flags], $12 \n"
" di \n"
#else
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 581915ce231c..153b6042e174 100644
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -45,7 +45,7 @@
#define cpu_has_watch 1
#define cpu_has_local_ebase 0
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
#define cpu_has_wsbh 1
#define cpu_has_ic_fills_f_dc 1
#define cpu_hwrena_impl_bits 0xc0000000
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index be9f727a9328..557e069c400c 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -4,7 +4,7 @@
#include <boot_param.h>
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index b5e288a12dfe..74d94fc1ed53 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -17,7 +17,7 @@
* Override macros used in arch/mips/kernel/head.S.
*/
.macro kernel_entry_setup
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
@@ -46,7 +46,7 @@
* Do SMP slave processor setup.
*/
.macro smp_slave_setup
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index 694a58574ec0..40a24b76b874 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -109,7 +109,7 @@ static inline void do_perfcnt_IRQ(void)
#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base
#else
#define LOONGSON_PCIIO_BASE 0x1fd00000
diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h
index 97f807fb2117..05cc9052772f 100644
--- a/arch/mips/include/asm/mach-loongson64/pci.h
+++ b/arch/mips/include/asm/mach-loongson64/pci.h
@@ -35,7 +35,7 @@ extern struct pci_ops loongson_pci_ops;
#else /* loongson2f/32bit & loongson2e */
/* this pci memory space is mapped by pcimap in pci.c */
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_PCI_MEM_START 0x40000000UL
#define LOONGSON_PCI_MEM_END 0x7effffffUL
#else
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 6dc0b21b8acd..2e5aee37bade 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -127,10 +127,10 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "SB1 "
#elif defined CONFIG_CPU_LOONGSON1
#define MODULE_PROC_FAMILY "LOONGSON1 "
-#elif defined CONFIG_CPU_LOONGSON2
-#define MODULE_PROC_FAMILY "LOONGSON2 "
-#elif defined CONFIG_CPU_LOONGSON3
-#define MODULE_PROC_FAMILY "LOONGSON3 "
+#elif defined CONFIG_CPU_LOONGSON2EF
+#define MODULE_PROC_FAMILY "LOONGSON2EF "
+#elif defined CONFIG_CPU_LOONGSON64
+#define MODULE_PROC_FAMILY "LOONGSON64 "
#elif defined CONFIG_CPU_CAVIUM_OCTEON
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index f88a48cd68b2..9807f05945fc 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -216,7 +216,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
-#elif defined(CONFIG_CPU_LOONGSON3)
+#elif defined(CONFIG_CPU_LOONGSON64)
/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index aca909bd7841..684efaa990ee 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -390,7 +390,7 @@ unsigned long get_wchan(struct task_struct *p);
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
/*
* Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
* tight read loop is executed, because reads take priority over writes & the
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 7f4a32d3345a..769d8b63f9fa 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -67,7 +67,7 @@ static inline void flush_scache_line_indexed(unsigned long addr)
static inline void flush_icache_line(unsigned long addr)
{
switch (boot_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
cache_op(Hit_Invalidate_I_Loongson2, addr);
break;
@@ -149,7 +149,7 @@ static inline void flush_scache_line(unsigned long addr)
static inline int protected_flush_icache_line(unsigned long addr)
{
switch (boot_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
default:
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 9635c1db3ae6..b0517bfc2100 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -608,7 +608,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
if (!(flags & FTLB_EN))
return 1;
return 0;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
/* Flush ITLB, DTLB, VTLB and FTLB */
write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
@@ -1555,28 +1555,28 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
switch (c->processor_id & PRID_REV_MASK) {
case PRID_REV_LOONGSON2E:
- c->cputype = CPU_LOONGSON2;
+ c->cputype = CPU_LOONGSON2EF;
__cpu_name[cpu] = "ICT Loongson-2";
set_elf_platform(cpu, "loongson2e");
set_isa(c, MIPS_CPU_ISA_III);
c->fpu_msk31 |= FPU_CSR_CONDX;
break;
case PRID_REV_LOONGSON2F:
- c->cputype = CPU_LOONGSON2;
+ c->cputype = CPU_LOONGSON2EF;
__cpu_name[cpu] = "ICT Loongson-2";
set_elf_platform(cpu, "loongson2f");
set_isa(c, MIPS_CPU_ISA_III);
c->fpu_msk31 |= FPU_CSR_CONDX;
break;
case PRID_REV_LOONGSON3A_R1:
- c->cputype = CPU_LOONGSON3;
+ c->cputype = CPU_LOONGSON64;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3a");
set_isa(c, MIPS_CPU_ISA_M64R1);
break;
case PRID_REV_LOONGSON3B_R1:
case PRID_REV_LOONGSON3B_R2:
- c->cputype = CPU_LOONGSON3;
+ c->cputype = CPU_LOONGSON64;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3b");
set_isa(c, MIPS_CPU_ISA_M64R1);
@@ -1929,14 +1929,14 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
switch (c->processor_id & PRID_REV_MASK) {
case PRID_REV_LOONGSON3A_R2_0:
case PRID_REV_LOONGSON3A_R2_1:
- c->cputype = CPU_LOONGSON3;
+ c->cputype = CPU_LOONGSON64;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3a");
set_isa(c, MIPS_CPU_ISA_M64R2);
break;
case PRID_REV_LOONGSON3A_R3_0:
case PRID_REV_LOONGSON3A_R3_1:
- c->cputype = CPU_LOONGSON3;
+ c->cputype = CPU_LOONGSON64;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3a");
set_isa(c, MIPS_CPU_ISA_M64R2);
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 7388f1374d5f..2524da19fafb 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -179,7 +179,7 @@ void __init check_wait(void)
case CPU_XLP:
cpu_wait = r4k_wait;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0)
cpu_wait = r4k_wait;
break;
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index a3e2da8391ea..0af456a94916 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1623,7 +1623,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
raw_event.cntr_mask =
raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
break;
}
@@ -1769,7 +1769,7 @@ init_hw_perf_events(void)
mipspmu.general_event_map = &mipsxxcore_event_map;
mipspmu.cache_event_map = &mipsxxcore_cache_map;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
mipspmu.name = "mips/loongson3";
mipspmu.general_event_map = &loongson3_event_map;
mipspmu.cache_event_map = &loongson3_cache_map;
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index ceef8240f171..3765893824f3 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -282,7 +282,7 @@ static unsigned long __init init_initrd(void)
* Initialize the bootmem allocator. It also setup initrd related data
* if needed.
*/
-#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_NUMA))
+#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON64) && defined(CONFIG_NUMA))
static void __init bootmem_init(void)
{
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 342e41de9d64..0c2570e6fcf6 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2394,7 +2394,7 @@ void __init trap_init(void)
else {
if (cpu_has_vtag_icache)
set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
- else if (current_cpu_type() == CPU_LOONGSON3)
+ else if (current_cpu_type() == CPU_LOONGSON64)
set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
else
set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 2ff84f4b1717..fda7b57b826e 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -279,7 +279,7 @@ EXPORT_SYMBOL(csum_partial)
#endif
/* odd buffer alignment? */
-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64)
.set push
.set arch=mips32r2
wsbh v1, sum
@@ -732,7 +732,7 @@ EXPORT_SYMBOL(csum_partial)
addu sum, v1
#endif
-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64)
.set push
.set arch=mips32r2
wsbh v1, sum
diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index 4c14a11525f4..d08b20ff2b27 100644
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -79,7 +79,7 @@ config LOONGSON_MACH3X
select I8259
select IRQ_MIPS_CPU
select NR_CPUS_DEFAULT_4
- select SYS_HAS_CPU_LOONGSON3
+ select SYS_HAS_CPU_LOONGSON64
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_HOTPLUG_CPU
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 1a5df773707d..c74bc0251e9d 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -21,4 +21,4 @@ obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
# All Loongson-3 family machines
#
-obj-$(CONFIG_CPU_LOONGSON3) += loongson-3/
+obj-$(CONFIG_CPU_LOONGSON64) += loongson-3/
diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform
index c1a4d4dc4665..b4d2582eb1ef 100644
--- a/arch/mips/loongson64/Platform
+++ b/arch/mips/loongson64/Platform
@@ -3,7 +3,7 @@
#
# Only gcc >= 4.4 have Loongson specific support
-cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2E) += \
$(call cc-option,-march=loongson2e,-march=r4600)
cflags-$(CONFIG_CPU_LOONGSON2F) += \
@@ -22,7 +22,7 @@ ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
endif
endif
-cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
#
# Some versions of binutils, not currently mainline as of 2019/02/04, support
@@ -44,7 +44,7 @@ cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap
# binutils does not merge support for the flag then we can revisit & remove
# this later - for now it ensures vendor toolchains don't cause problems.
#
-cflags-$(CONFIG_CPU_LOONGSON3) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
+cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
#
# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
@@ -55,14 +55,14 @@ cflags-$(CONFIG_CPU_LOONGSON3) += $(call as-option,-Wa$(comma)-mno-fix-loongson3
#
ifeq ($(call cc-ifversion, -ge, 0409, y), y)
ifeq ($(call ld-ifversion, -ge, 225000000, y), y)
- cflags-$(CONFIG_CPU_LOONGSON3) += \
+ cflags-$(CONFIG_CPU_LOONGSON64) += \
$(call cc-option,-march=loongson3a -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
else
- cflags-$(CONFIG_CPU_LOONGSON3) += \
+ cflags-$(CONFIG_CPU_LOONGSON64) += \
$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
endif
else
- cflags-$(CONFIG_CPU_LOONGSON3) += \
+ cflags-$(CONFIG_CPU_LOONGSON64) += \
$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
endif
diff --git a/arch/mips/loongson64/common/pci.c b/arch/mips/loongson64/common/pci.c
index c47bb7bf3aa4..2d9755c49524 100644
--- a/arch/mips/loongson64/common/pci.c
+++ b/arch/mips/loongson64/common/pci.c
@@ -87,7 +87,7 @@ static int __init pcibios_init(void)
#endif
register_pci_controller(&loongson_pci_controller);
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
sbx00_acpi_init();
#endif
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5166e38cd1c6..38ed99b605a4 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -320,7 +320,7 @@ static void r4k_blast_icache_page_setup(void)
r4k_blast_icache_page = (void *)cache_noop;
else if (ic_lsize == 16)
r4k_blast_icache_page = blast_icache16_page;
- else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
+ else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache_page = loongson2_blast_icache32_page;
else if (ic_lsize == 32)
r4k_blast_icache_page = blast_icache32_page;
@@ -369,7 +369,7 @@ static void r4k_blast_icache_page_indexed_setup(void)
else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache_page_indexed =
tx49_blast_icache32_page_indexed;
- else if (current_cpu_type() == CPU_LOONGSON2)
+ else if (current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache_page_indexed =
loongson2_blast_icache32_page_indexed;
else
@@ -395,7 +395,7 @@ static void r4k_blast_icache_setup(void)
r4k_blast_icache = blast_r4600_v1_icache32;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache = tx49_blast_icache32;
- else if (current_cpu_type() == CPU_LOONGSON2)
+ else if (current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache = loongson2_blast_icache32;
else
r4k_blast_icache = blast_icache32;
@@ -465,7 +465,7 @@ static void r4k_blast_scache_node_setup(void)
{
unsigned long sc_lsize = cpu_scache_line_size();
- if (current_cpu_type() != CPU_LOONGSON3)
+ if (current_cpu_type() != CPU_LOONGSON64)
r4k_blast_scache_node = (void *)cache_noop;
else if (sc_lsize == 16)
r4k_blast_scache_node = blast_scache16_node;
@@ -480,7 +480,7 @@ static void r4k_blast_scache_node_setup(void)
static inline void local_r4k___flush_cache_all(void * args)
{
switch (current_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4400SC:
@@ -497,7 +497,7 @@ static inline void local_r4k___flush_cache_all(void * args)
r4k_blast_scache();
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
/* Use get_ebase_cpunum() for both NUMA=y/n */
r4k_blast_scache_node(get_ebase_cpunum() >> 2);
break;
@@ -770,7 +770,7 @@ static inline void __local_r4k_flush_icache_range(unsigned long start,
r4k_blast_icache();
else {
switch (boot_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
protected_loongson2_blast_icache_range(start, end);
break;
@@ -863,7 +863,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
preempt_disable();
if (cpu_has_inclusive_pcaches) {
if (size >= scache_size) {
- if (current_cpu_type() != CPU_LOONGSON3)
+ if (current_cpu_type() != CPU_LOONGSON64)
r4k_blast_scache();
else
r4k_blast_scache_node(pa_to_nid(addr));
@@ -904,7 +904,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
preempt_disable();
if (cpu_has_inclusive_pcaches) {
if (size >= scache_size) {
- if (current_cpu_type() != CPU_LOONGSON3)
+ if (current_cpu_type() != CPU_LOONGSON64)
r4k_blast_scache();
else
r4k_blast_scache_node(pa_to_nid(addr));
@@ -1226,7 +1226,7 @@ static void probe_pcache(void)
c->options |= MIPS_CPU_PREFETCH;
break;
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
if (prid & 0x3)
@@ -1244,7 +1244,7 @@ static void probe_pcache(void)
c->dcache.waybit = 0;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
config1 = read_c0_config1();
lsize = (config1 >> 19) & 7;
if (lsize)
@@ -1454,7 +1454,7 @@ static void probe_pcache(void)
c->dcache.flags &= ~MIPS_CACHE_ALIASES;
break;
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
/*
* LOONGSON2 has 4 way icache, but when using indexed cache op,
* one op will act on all 4 ways
@@ -1480,7 +1480,7 @@ static void probe_vcache(void)
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int config2, lsize;
- if (current_cpu_type() != CPU_LOONGSON3)
+ if (current_cpu_type() != CPU_LOONGSON64)
return;
config2 = read_c0_config2();
@@ -1655,11 +1655,11 @@ static void setup_scache(void)
#endif
return;
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
loongson2_sc_init();
return;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
loongson3_sc_init();
return;
@@ -1928,7 +1928,7 @@ void r4k_cache_init(void)
/* Optimization: an L2 flush implicitly flushes the L1 */
current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
/* Loongson-3 maintains cache coherency by hardware */
__flush_cache_all = cache_noop;
__flush_cache_vmap = cache_noop;
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 56e4f8bffd4c..c5578897a4fa 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -187,7 +187,7 @@ static void set_prefetch_parameters(void)
}
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
/* Loongson-3 only support the Pref_Load/Pref_Store. */
pref_bias_clear_store = 128;
pref_bias_copy_load = 128;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index c13e46ced425..83b450ddbbc2 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -35,10 +35,10 @@ extern void build_tlb_refill_handler(void);
static inline void flush_micro_tlb(void)
{
switch (current_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
write_c0_diag(LOONGSON_DIAG_ITLB);
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB);
break;
default:
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 144ceb0fba88..05e64217842e 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -572,8 +572,8 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_BMIPS4350:
case CPU_BMIPS4380:
case CPU_BMIPS5000:
- case CPU_LOONGSON2:
- case CPU_LOONGSON3:
+ case CPU_LOONGSON2EF:
+ case CPU_LOONGSON64:
case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
@@ -1372,7 +1372,7 @@ static void build_r4000_tlb_refill_handler(void)
switch (boot_cpu_type()) {
default:
if (sizeof(long) == 4) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
/* Loongson2 ebase is different than r4k, we have more space */
if ((p - tlb_handler) > 64)
panic("TLB refill handler space exceeded");
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 011cf9f891e7..e10f216d0422 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -14,5 +14,5 @@ oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_XLR) += op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o
-oprofile-$(CONFIG_CPU_LOONGSON3) += op_model_loongson3.o
+oprofile-$(CONFIG_CPU_LOONGSON2EF) += op_model_loongson2.o
+oprofile-$(CONFIG_CPU_LOONGSON64) += op_model_loongson3.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 2f33992f6dff..25cfa70f0ae4 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -104,10 +104,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
lmodel = &op_model_mipsxx_ops;
break;
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
lmodel = &op_model_loongson2_ops;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
lmodel = &op_model_loongson3_ops;
break;
};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index bb13c266c329..6ed3f380a45e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -298,7 +298,7 @@ config GPIO_IXP4XX
config GPIO_LOONGSON
bool "Loongson-2/3 GPIO support"
- depends on CPU_LOONGSON2 || CPU_LOONGSON3
+ depends on CPU_LOONGSON2EF || CPU_LOONGSON64
help
driver for GPIO functionality on Loongson-2F/3A/3B processors.
diff --git a/drivers/gpio/gpio-loongson.c b/drivers/gpio/gpio-loongson.c
index 00943170ce36..a42145873cc9 100644
--- a/drivers/gpio/gpio-loongson.c
+++ b/drivers/gpio/gpio-loongson.c
@@ -22,7 +22,7 @@
#define STLS2F_N_GPIO 4
#define STLS3A_N_GPIO 16
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_N_GPIO STLS3A_N_GPIO
#else
#define LOONGSON_N_GPIO STLS2F_N_GPIO
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 987ff16b9420..e9ad4863d915 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -45,7 +45,7 @@ static inline bool drm_arch_can_wc_memory(void)
{
#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
return false;
-#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
+#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)
return false;
#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
/*
--
2.22.0
As later model of GSx64 family processors including 2-series-soc have
similar design with initial loongson3a while loongson2e/f seems less
identical, we separate loongson2e/f support code out of mach-loongson64
to make our life easier.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 51 +++++--
arch/mips/include/asm/bootinfo.h | 1 -
.../mach-loongson2ef/cpu-feature-overrides.h | 45 +++++++
.../cs5536/cs5536.h | 0
.../cs5536/cs5536_mfgpt.h | 0
.../cs5536/cs5536_pci.h | 0
.../cs5536/cs5536_vsm.h | 0
.../loongson2ef.h} | 29 +---
.../machine.h | 6 -
.../mc146818rtc.h | 5 +-
.../mem.h | 6 +-
arch/mips/include/asm/mach-loongson2ef/pci.h | 43 ++++++
.../include/asm/mach-loongson2ef/spaces.h | 10 ++
.../mach-loongson64/cpu-feature-overrides.h | 3 -
arch/mips/include/asm/mach-loongson64/irq.h | 7 +-
.../asm/mach-loongson64/kernel-entry-init.h | 74 ----------
.../include/asm/mach-loongson64/loongson64.h | 48 +++++++
.../mips/include/asm/mach-loongson64/mmzone.h | 16 ---
arch/mips/include/asm/mach-loongson64/pci.h | 41 +-----
.../include/asm/mach-loongson64/workarounds.h | 4 +-
arch/mips/loongson2ef/Kconfig | 93 +++++++++++++
arch/mips/loongson2ef/Makefile | 18 +++
arch/mips/loongson2ef/Platform | 32 +++++
.../common/Makefile | 0
.../common/bonito-irq.c | 2 +-
.../common/cmdline.c | 2 +-
.../common/cs5536/Makefile | 0
.../common/cs5536/cs5536_acc.c | 0
.../common/cs5536/cs5536_ehci.c | 0
.../common/cs5536/cs5536_ide.c | 0
.../common/cs5536/cs5536_isa.c | 0
.../common/cs5536/cs5536_mfgpt.c | 0
.../common/cs5536/cs5536_ohci.c | 0
.../common/cs5536/cs5536_pci.c | 0
.../common/early_printk.c | 2 +-
arch/mips/loongson2ef/common/env.c | 71 ++++++++++
.../{loongson64 => loongson2ef}/common/init.c | 7 +-
.../{loongson64 => loongson2ef}/common/irq.c | 2 +-
.../common/machtype.c | 3 +-
.../{loongson64 => loongson2ef}/common/mem.c | 40 +-----
.../{loongson64 => loongson2ef}/common/pci.c | 11 +-
.../common/platform.c | 0
.../{loongson64 => loongson2ef}/common/pm.c | 2 +-
.../common/reset.c | 23 +---
.../{loongson64 => loongson2ef}/common/rtc.c | 0
.../common/serial.c | 37 +----
.../common/setup.c | 2 +-
.../{loongson64 => loongson2ef}/common/time.c | 2 +-
.../common/uart_base.c | 10 +-
.../fuloong-2e/Makefile | 0
.../fuloong-2e/dma.c | 0
.../fuloong-2e/irq.c | 2 +-
.../fuloong-2e/reset.c | 2 +-
.../lemote-2f/Makefile | 0
.../lemote-2f/clock.c | 2 +-
.../lemote-2f/dma.c | 0
.../lemote-2f/ec_kb3310b.c | 0
.../lemote-2f/ec_kb3310b.h | 0
.../lemote-2f/irq.c | 2 +-
.../lemote-2f/machtype.c | 2 +-
.../lemote-2f/pm.c | 2 +-
.../lemote-2f/reset.c | 2 +-
arch/mips/loongson64/Kconfig | 126 +-----------------
arch/mips/loongson64/Makefile | 23 +---
arch/mips/loongson64/Platform | 26 +---
.../loongson64/{loongson-3 => }/acpi_init.c | 3 +-
.../loongson64/{loongson-3 => }/cop2-ex.c | 5 +-
arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +-
arch/mips/loongson64/{common => }/env.c | 72 +++-------
arch/mips/loongson64/{loongson-3 => }/hpet.c | 0
arch/mips/loongson64/{loongson-3 => }/irq.c | 40 +++++-
arch/mips/loongson64/loongson-3/Makefile | 11 --
arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +-
arch/mips/loongson64/pci.c | 45 +++++++
.../loongson64/{loongson-3 => }/platform.c | 0
arch/mips/loongson64/reset.c | 58 ++++++++
arch/mips/loongson64/setup.c | 92 +++++++++++++
arch/mips/loongson64/{loongson-3 => }/smp.c | 4 +-
arch/mips/loongson64/{loongson-3 => }/smp.h | 0
arch/mips/oprofile/op_model_loongson2.c | 2 +-
arch/mips/oprofile/op_model_loongson3.c | 2 +-
arch/mips/pci/Makefile | 2 +-
arch/mips/pci/fixup-fuloong2e.c | 2 +-
arch/mips/pci/fixup-lemote2f.c | 2 +-
arch/mips/pci/ops-loongson2.c | 2 +-
arch/mips/pci/ops-loongson3.c | 2 +-
drivers/cpufreq/loongson2_cpufreq.c | 2 +-
drivers/gpio/gpio-loongson.c | 2 +-
drivers/platform/mips/cpu_hwmon.c | 2 +-
90 files changed, 720 insertions(+), 578 deletions(-)
create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%)
rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%)
create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h
create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h
delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h
create mode 100644 arch/mips/loongson2ef/Kconfig
create mode 100644 arch/mips/loongson2ef/Makefile
create mode 100644 arch/mips/loongson2ef/Platform
rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%)
create mode 100644 arch/mips/loongson2ef/common/env.c
rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%)
rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%)
rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%)
rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%)
rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%)
rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%)
rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%)
rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%)
rename arch/mips/loongson64/{common => }/env.c (79%)
rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%)
rename arch/mips/loongson64/{loongson-3 => }/irq.c (77%)
delete mode 100644 arch/mips/loongson64/loongson-3/Makefile
rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%)
create mode 100644 arch/mips/loongson64/pci.c
rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%)
create mode 100644 arch/mips/loongson64/reset.c
create mode 100644 arch/mips/loongson64/setup.c
rename arch/mips/loongson64/{loongson-3 => }/smp.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%)
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 0de839882106..7c0d461483ef 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -17,6 +17,7 @@ platforms += jazz
platforms += jz4740
platforms += lantiq
platforms += lasat
+platforms += loongson2ef
platforms += loongson32
platforms += loongson64
platforms += mti-malta
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cbc76f00d1fc..92a2ee773a40 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -445,18 +445,52 @@ config MACH_LOONGSON32
the Institute of Computing Technology (ICT), Chinese Academy of
Sciences (CAS).
+config MACH_LOONGSON2EF
+ bool "Loongson-2E/F family of machines"
+ select SYS_SUPPORTS_ZBOOT
+ help
+ This enables the support of Loongson-2E/F family of machines.
+
+ Loongson-2E/F is a family of single-core CPUs, They are 64-bit
+ general-purpose MIPS-III compatible CPUs. Loongson-2E/F are developed
+ by the Institute of Computing Technology (ICT), Chinese Academy of
+ Sciences (CAS) in the People's Republic of China.
+ The chief architect is Professor Weiwu Hu.
+
config MACH_LOONGSON64
- bool "Loongson-2/3 family of machines"
+ bool "Loongson GSx64 family of machines"
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
+ select BOOT_ELF32
+ select BOARD_SCACHE
+ select CSRC_R4K
+ select CEVT_R4K
+ select CPU_HAS_WB
+ select FORCE_PCI
+ select ISA
+ select I8259
+ select IRQ_MIPS_CPU
+ select NUMA
+ select NR_CPUS_DEFAULT_32
+ select SYS_HAS_CPU_LOONGSON64
+ select SYS_HAS_EARLY_PRINTK
+ select USE_GENERIC_EARLY_PRINTK_8250
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_HOTPLUG_CPU
+ select SYS_SUPPORTS_NUMA
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select ZONE_DMA32
select SYS_SUPPORTS_ZBOOT
help
- This enables the support of Loongson-2/3 family of machines.
+ This enables the support of Loongson-3A/3B/2-series-soc processors
- Loongson-2 is a family of single-core CPUs and Loongson-3 is a
- family of multi-core CPUs. They are both 64-bit general-purpose
- MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
- of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
- in the People's Republic of China. The chief architect is Professor
- Weiwu Hu.
+ GSx64 is a family of general-purpose MIPS64R2+ procossor featured
+ multi-core support. Their firmwares are passing parameters according
+ to uniformed "Loongson Firmware Kernel Interface Specification".
config MACH_PISTACHIO
bool "IMG Pistachio SoC based boards"
@@ -1033,6 +1067,7 @@ source "arch/mips/sibyte/Kconfig"
source "arch/mips/txx9/Kconfig"
source "arch/mips/vr41xx/Kconfig"
source "arch/mips/cavium-octeon/Kconfig"
+source "arch/mips/loongson2ef/Kconfig"
source "arch/mips/loongson32/Kconfig"
source "arch/mips/loongson64/Kconfig"
source "arch/mips/netlogic/Kconfig"
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index f711ccf7bace..6c1602af2bf4 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -70,7 +70,6 @@ enum loongson_machine_type {
MACH_DEXXON_GDIUM2F10,
MACH_LEMOTE_NAS,
MACH_LEMOTE_LL2F,
- MACH_LOONGSON_GENERIC,
MACH_LOONGSON_END
};
diff --git a/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
new file mode 100644
index 000000000000..961ce43c6c98
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2009 Wu Zhangjin <[email protected]>
+ * Copyright (C) 2009 Philippe Vachon <[email protected]>
+ * Copyright (C) 2009 Zhang Le <[email protected]>
+ *
+ * reference: /proc/cpuinfo,
+ * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
+ * arch/mips/kernel/proc.c(show_cpuinfo),
+ * loongson2f user manual.
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_32fpr 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_4kex 1
+#define cpu_has_64bits 1
+#define cpu_has_cache_cdex_p 0
+#define cpu_has_cache_cdex_s 0
+#define cpu_has_counter 1
+#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
+#define cpu_has_divec 0
+#define cpu_has_ejtag 0
+#define cpu_has_inclusive_pcaches 1
+#define cpu_has_llsc 1
+#define cpu_has_mcheck 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips16 0
+#define cpu_has_mips16e2 0
+#define cpu_has_mips3d 0
+#define cpu_has_mipsmt 0
+#define cpu_has_smartmips 0
+#define cpu_has_tlb 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_vce 0
+#define cpu_has_veic 0
+#define cpu_has_vint 0
+#define cpu_has_vtag_icache 0
+#define cpu_has_watch 1
+#define cpu_has_local_ebase 0
+
+#endif /* __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h
similarity index 100%
rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536.h
rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h
diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h
similarity index 100%
rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_mfgpt.h
rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_mfgpt.h
diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
similarity index 100%
rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_pci.h
rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
diff --git a/arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h
similarity index 100%
rename from arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h
rename to arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_vsm.h
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson2ef/loongson2ef.h
similarity index 91%
rename from arch/mips/include/asm/mach-loongson64/loongson.h
rename to arch/mips/include/asm/mach-loongson2ef/loongson2ef.h
index 40a24b76b874..b4524937df0e 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson2ef/loongson2ef.h
@@ -4,13 +4,12 @@
* Author: Wu Zhangjin <[email protected]>
*/
-#ifndef __ASM_MACH_LOONGSON64_LOONGSON_H
-#define __ASM_MACH_LOONGSON64_LOONGSON_H
+#ifndef __ASM_MACH_LOONGSON2EF_LOONGSON2EF_H
+#define __ASM_MACH_LOONGSON2EF_LOONGSON2EF_H
#include <linux/io.h>
#include <linux/init.h>
#include <linux/irq.h>
-#include <boot_param.h>
/* loongson internal northbridge initialization */
extern void bonito_irq_init(void);
@@ -22,7 +21,6 @@ extern void mach_prepare_shutdown(void);
/* environment arguments from bootloader */
extern u32 cpu_clock_freq;
extern u32 memsize, highmemsize;
-extern const struct plat_smp_ops loongson3_smp_ops;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
@@ -58,11 +56,6 @@ extern int mach_i8259_irq(void);
#define LOONGSON_REG(x) \
(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
-#define LOONGSON3_REG8(base, x) \
- (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
-
-#define LOONGSON3_REG32(base, x) \
- (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
#define LOONGSON_IRQ_BASE 32
#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
@@ -89,10 +82,6 @@ static inline void do_perfcnt_IRQ(void)
#define LOONGSON_REG_BASE 0x1fe00000
#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
-/* Loongson-3 specific registers */
-#define LOONGSON3_REG_BASE 0x3ff00000
-#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
-#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
#define LOONGSON_LIO1_BASE 0x1ff00000
#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
@@ -247,19 +236,9 @@ static inline void do_perfcnt_IRQ(void)
#define MAX_PACKAGES 4
/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
-extern u64 loongson_chipcfg[MAX_PACKAGES];
-#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
-
-/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
-extern u64 loongson_chiptemp[MAX_PACKAGES];
-#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
-
-/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
-extern u64 loongson_freqctrl[MAX_PACKAGES];
-#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
+#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(0xffffffffbfc00180))
/* pcimap */
-
#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
@@ -352,4 +331,4 @@ extern unsigned long _loongson_addrwincfg_base;
#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
-#endif /* __ASM_MACH_LOONGSON64_LOONGSON_H */
+#endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson64/machine.h b/arch/mips/include/asm/mach-loongson2ef/machine.h
similarity index 80%
rename from arch/mips/include/asm/mach-loongson64/machine.h
rename to arch/mips/include/asm/mach-loongson2ef/machine.h
index 8ef7ea94a26d..2a032259041d 100644
--- a/arch/mips/include/asm/mach-loongson64/machine.h
+++ b/arch/mips/include/asm/mach-loongson2ef/machine.h
@@ -20,10 +20,4 @@
#endif
-#ifdef CONFIG_LOONGSON_MACH3X
-
-#define LOONGSON_MACHTYPE MACH_LOONGSON_GENERIC
-
-#endif /* CONFIG_LOONGSON_MACH3X */
-
#endif /* __ASM_MACH_LOONGSON64_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson64/mc146818rtc.h b/arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h
similarity index 80%
rename from arch/mips/include/asm/mach-loongson64/mc146818rtc.h
rename to arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h
index ebdccfee50be..7b42c9efccc0 100644
--- a/arch/mips/include/asm/mach-loongson64/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-loongson2ef/mc146818rtc.h
@@ -1,8 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle ([email protected])
*
* RTC routines for PC style attached Dallas chip.
diff --git a/arch/mips/include/asm/mach-loongson64/mem.h b/arch/mips/include/asm/mach-loongson2ef/mem.h
similarity index 86%
rename from arch/mips/include/asm/mach-loongson64/mem.h
rename to arch/mips/include/asm/mach-loongson2ef/mem.h
index ce33c174c04d..d1d759b8974e 100644
--- a/arch/mips/include/asm/mach-loongson64/mem.h
+++ b/arch/mips/include/asm/mach-loongson2ef/mem.h
@@ -4,8 +4,8 @@
* Author: Wu Zhangjin <[email protected]>
*/
-#ifndef __ASM_MACH_LOONGSON64_MEM_H
-#define __ASM_MACH_LOONGSON64_MEM_H
+#ifndef __ASM_MACH_LOONGSON2EF_MEM_H
+#define __ASM_MACH_LOONGSON2EF_MEM_H
/*
* high memory space
@@ -34,4 +34,4 @@
#define LOONGSON_MMIO_MEM_END 0x80000000
#endif
-#endif /* __ASM_MACH_LOONGSON64_MEM_H */
+#endif /* __ASM_MACH_LOONGSON2EF_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson2ef/pci.h b/arch/mips/include/asm/mach-loongson2ef/pci.h
new file mode 100644
index 000000000000..df65d3c14896
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/pci.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2008 Zhang Le <[email protected]>
+ * Copyright (c) 2009 Wu Zhangjin <[email protected]>
+ */
+
+#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_
+#define __ASM_MACH_LOONGSON2EF_PCI_H_
+
+extern struct pci_ops loongson_pci_ops;
+
+/* this is an offset from mips_io_port_base */
+#define LOONGSON_PCI_IO_START 0x00004000UL
+
+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
+
+/*
+ * we use address window2 to map cpu address space to pci space
+ * window2: cpu [1G, 2G] -> pci [1G, 2G]
+ * why not use window 0 & 1? because they are used by cpu when booting.
+ * window0: cpu [0, 256M] -> ddr [0, 256M]
+ * window1: cpu [256M, 512M] -> pci [256M, 512M]
+ */
+
+/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
+#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
+#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
+
+#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
+#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
+
+#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
+ LOONGSON_PCI_MEM_START + 1)
+
+#else /* loongson2f/32bit & loongson2e */
+
+/* this pci memory space is mapped by pcimap in pci.c */
+#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
+#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
+
+#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
+
+#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson2ef/spaces.h b/arch/mips/include/asm/mach-loongson2ef/spaces.h
new file mode 100644
index 000000000000..ba4e8e9b618e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson2ef/spaces.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_LOONGSON2EF_SPACES_H_
+#define __ASM_MACH_LOONGSON2EF_SPACES_H_
+
+#if defined(CONFIG_64BIT)
+#define CAC_BASE _AC(0x9800000000000000, UL)
+#endif /* CONFIG_64BIT */
+
+#include <asm/mach-generic/spaces.h>
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 153b6042e174..e70e8abc8348 100644
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -44,11 +44,8 @@
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1
#define cpu_has_local_ebase 0
-
-#ifdef CONFIG_CPU_LOONGSON64
#define cpu_has_wsbh 1
#define cpu_has_ic_fills_f_dc 1
#define cpu_hwrena_impl_bits 0xc0000000
-#endif
#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 557e069c400c..baed43285163 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -2,10 +2,9 @@
#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
#define __ASM_MACH_LOONGSON64_IRQ_H_
+#include <loongson64.h>
#include <boot_param.h>
-#ifdef CONFIG_CPU_LOONGSON64
-
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
@@ -35,10 +34,8 @@
#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
-#endif
-
extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(struct pt_regs *regs);
+extern void loongson3_ipi_interrupt(void);
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
deleted file mode 100644
index 74d94fc1ed53..000000000000
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005 Embedded Alley Solutions, Inc
- * Copyright (C) 2005 Ralf Baechle ([email protected])
- * Copyright (C) 2009 Jiajie Chen ([email protected])
- * Copyright (C) 2012 Huacai Chen ([email protected])
- */
-#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
-#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
-
-#include <asm/cpu.h>
-
-/*
- * Override macros used in arch/mips/kernel/head.S.
- */
- .macro kernel_entry_setup
-#ifdef CONFIG_CPU_LOONGSON64
- .set push
- .set mips64
- /* Set LPA on LOONGSON3 config3 */
- mfc0 t0, CP0_CONFIG3
- or t0, (0x1 << 7)
- mtc0 t0, CP0_CONFIG3
- /* Set ELPA on LOONGSON3 pagegrain */
- mfc0 t0, CP0_PAGEGRAIN
- or t0, (0x1 << 29)
- mtc0 t0, CP0_PAGEGRAIN
- /* Enable STFill Buffer */
- mfc0 t0, CP0_PRID
- andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
- slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)
- bnez t0, 1f
- mfc0 t0, CP0_CONFIG6
- or t0, 0x100
- mtc0 t0, CP0_CONFIG6
-1:
- _ehb
- .set pop
-#endif
- .endm
-
-/*
- * Do SMP slave processor setup.
- */
- .macro smp_slave_setup
-#ifdef CONFIG_CPU_LOONGSON64
- .set push
- .set mips64
- /* Set LPA on LOONGSON3 config3 */
- mfc0 t0, CP0_CONFIG3
- or t0, (0x1 << 7)
- mtc0 t0, CP0_CONFIG3
- /* Set ELPA on LOONGSON3 pagegrain */
- mfc0 t0, CP0_PAGEGRAIN
- or t0, (0x1 << 29)
- mtc0 t0, CP0_PAGEGRAIN
- /* Enable STFill Buffer */
- mfc0 t0, CP0_PRID
- andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
- slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)
- bnez t0, 1f
- mfc0 t0, CP0_CONFIG6
- or t0, 0x100
- mtc0 t0, CP0_CONFIG6
-1:
- _ehb
- .set pop
-#endif
- .endm
-
-#endif /* __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-loongson64/loongson64.h b/arch/mips/include/asm/mach-loongson64/loongson64.h
new file mode 100644
index 000000000000..d877adb99d33
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/loongson64.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Generic definitions for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_LOONGSON64_H
+#define __ASM_MACH_LOONGSON64_LOONGSON64_H
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#define MAX_PACKAGES 4
+
+#define LOONGSON_REG_BASE 0x1fe00000
+#define LOONGSON_REGBASE 0x100
+
+#define LOONGSON3_REG_BASE 0x3ff00000
+#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
+
+#define LOONGSON_REG(x) \
+ (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+
+#define LOONGSON3_REG8(base, x) \
+ (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
+
+#define LOONGSON3_REG32(base, x) \
+ (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))/* Loongson-3 specific registers */
+
+#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
+
+/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
+extern u64 loongson_chipcfg[MAX_PACKAGES];
+#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
+
+/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
+extern u64 loongson_chiptemp[MAX_PACKAGES];
+#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
+
+/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
+extern u64 loongson_freqctrl[MAX_PACKAGES];
+#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
+
+extern const struct plat_smp_ops loongson3_smp_ops;
+extern void __init prom_init_lefi(void);
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/mmzone.h b/arch/mips/include/asm/mach-loongson64/mmzone.h
index 62073d60739f..eec8057d3ec9 100644
--- a/arch/mips/include/asm/mach-loongson64/mmzone.h
+++ b/arch/mips/include/asm/mach-loongson64/mmzone.h
@@ -19,30 +19,14 @@
#define pa_to_nid(addr) (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT)
#define nid_to_addrbase(nid) ((nid) << NODE_ADDRSPACE_SHIFT)
-#define LEVELS_PER_SLICE 128
-
-struct slice_data {
- unsigned long irq_enable_mask[2];
- int level_to_irq[LEVELS_PER_SLICE];
-};
-
-struct hub_data {
- cpumask_t h_cpus;
- unsigned long slice_map;
- unsigned long irq_alloc_mask[2];
- struct slice_data slice[2];
-};
-
struct node_data {
struct pglist_data pglist;
- struct hub_data hub;
cpumask_t cpumask;
};
extern struct node_data *__node_data[];
#define NODE_DATA(n) (&__node_data[(n)]->pglist)
-#define hub_data(n) (&__node_data[(n)]->hub)
extern void setup_zero_pages(void);
extern void __init prom_init_numa_memory(void);
diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h
index 05cc9052772f..a30024499590 100644
--- a/arch/mips/include/asm/mach-loongson64/pci.h
+++ b/arch/mips/include/asm/mach-loongson64/pci.h
@@ -4,47 +4,12 @@
* Copyright (c) 2009 Wu Zhangjin <[email protected]>
*/
-#ifndef __ASM_MACH_LOONGSON64_PCI_H_
-#define __ASM_MACH_LOONGSON64_PCI_H_
+#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_
+#define __ASM_MACH_LOONGSON2EF_PCI_H_
extern struct pci_ops loongson_pci_ops;
-/* this is an offset from mips_io_port_base */
-#define LOONGSON_PCI_IO_START 0x00004000UL
-
-#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
-
-/*
- * we use address window2 to map cpu address space to pci space
- * window2: cpu [1G, 2G] -> pci [1G, 2G]
- * why not use window 0 & 1? because they are used by cpu when booting.
- * window0: cpu [0, 256M] -> ddr [0, 256M]
- * window1: cpu [256M, 512M] -> pci [256M, 512M]
- */
-
-/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
-#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
-#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
-
-#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
-#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
-
-#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
- LOONGSON_PCI_MEM_START + 1)
-
-#else /* loongson2f/32bit & loongson2e */
-
-/* this pci memory space is mapped by pcimap in pci.c */
-#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_PCI_MEM_START 0x40000000UL
#define LOONGSON_PCI_MEM_END 0x7effffffUL
-#else
-#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
-#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
-#endif
-/* this is an offset from mips_io_port_base */
-#define LOONGSON_PCI_IO_START 0x00004000UL
-
-#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
-#endif /* !__ASM_MACH_LOONGSON64_PCI_H_ */
+#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson64/workarounds.h b/arch/mips/include/asm/mach-loongson64/workarounds.h
index 17b71172a097..e30415bef7b7 100644
--- a/arch/mips/include/asm/mach-loongson64/workarounds.h
+++ b/arch/mips/include/asm/mach-loongson64/workarounds.h
@@ -2,7 +2,7 @@
#ifndef __ASM_MACH_LOONGSON64_WORKAROUNDS_H_
#define __ASM_MACH_LOONGSON64_WORKAROUNDS_H_
-#define WORKAROUND_CPUFREQ 0x00000001
-#define WORKAROUND_CPUHOTPLUG 0x00000002
+#define WORKAROUND_CPUFREQ BIT(1)
+#define WORKAROUND_CPUHOTPLUG BIT(2)
#endif
diff --git a/arch/mips/loongson2ef/Kconfig b/arch/mips/loongson2ef/Kconfig
new file mode 100644
index 000000000000..cb2f523d9e30
--- /dev/null
+++ b/arch/mips/loongson2ef/Kconfig
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0
+if MACH_LOONGSON2EF
+
+choice
+ prompt "Machine Type"
+
+config LEMOTE_FULOONG2E
+ bool "Lemote Fuloong(2e) mini-PC"
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
+ select CEVT_R4K
+ select CSRC_R4K
+ select SYS_HAS_CPU_LOONGSON2E
+ select DMA_NONCOHERENT
+ select BOOT_ELF32
+ select BOARD_SCACHE
+ select HAVE_PCI
+ select I8259
+ select ISA
+ select IRQ_MIPS_CPU
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_HAS_EARLY_PRINTK
+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
+ select CPU_HAS_WB
+ select LOONGSON_MC146818
+ help
+ Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
+ an FPGA northbridge
+
+ Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
+
+config LEMOTE_MACH2F
+ bool "Lemote Loongson 2F family machines"
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
+ select BOARD_SCACHE
+ select BOOT_ELF32
+ select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
+ select CPU_HAS_WB
+ select CS5536
+ select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
+ select DMA_NONCOHERENT
+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
+ select HAVE_CLK
+ select HAVE_PCI
+ select I8259
+ select IRQ_MIPS_CPU
+ select ISA
+ select SYS_HAS_CPU_LOONGSON2F
+ select SYS_HAS_EARLY_PRINTK
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select LOONGSON_MC146818
+ help
+ Lemote Loongson 2F family machines utilize the 2F revision of
+ Loongson processor and the AMD CS5536 south bridge.
+
+ These family machines include fuloong2f mini PC, yeeloong2f notebook,
+ LingLoong allinone PC and so forth.
+
+endchoice
+
+config CS5536
+ bool
+
+config CS5536_MFGPT
+ bool "CS5536 MFGPT Timer"
+ depends on CS5536 && !HIGH_RES_TIMERS
+ select MIPS_EXTERNAL_TIMER
+ help
+ This option enables the mfgpt0 timer of AMD CS5536. With this timer
+ switched on you can not use high resolution timers.
+
+ If you want to enable the Loongson2 CPUFreq Driver, Please enable
+ this option at first, otherwise, You will get wrong system time.
+
+ If unsure, say Yes.
+
+config LOONGSON_UART_BASE
+ bool
+ default y
+ depends on EARLY_PRINTK || SERIAL_8250
+
+config LOONGSON_MC146818
+ bool
+ default n
+
+endif # MACH_LOONGSON2EF
diff --git a/arch/mips/loongson2ef/Makefile b/arch/mips/loongson2ef/Makefile
new file mode 100644
index 000000000000..0535d244d75b
--- /dev/null
+++ b/arch/mips/loongson2ef/Makefile
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Common code for all Loongson based systems
+#
+
+obj-y += common/
+
+#
+# Lemote Fuloong mini-PC (Loongson 2E-based)
+#
+
+obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
+
+#
+# Lemote loongson2f family machines
+#
+
+obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
diff --git a/arch/mips/loongson2ef/Platform b/arch/mips/loongson2ef/Platform
new file mode 100644
index 000000000000..3aca42963f35
--- /dev/null
+++ b/arch/mips/loongson2ef/Platform
@@ -0,0 +1,32 @@
+#
+# Loongson Processors' Support
+#
+
+# Only gcc >= 4.4 have Loongson specific support
+cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2E) += \
+ $(call cc-option,-march=loongson2e,-march=r4600)
+cflags-$(CONFIG_CPU_LOONGSON2F) += \
+ $(call cc-option,-march=loongson2f,-march=r4600)
+# Enable the workarounds for Loongson2f
+ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
+ ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
+ $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
+ else
+ cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
+ endif
+ ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
+ $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
+ else
+ cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
+ endif
+endif
+
+#
+# Loongson Machines' Support
+#
+
+platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/
+cflags-$(CONFIG_MACH_LOONGSON2EF) += -I$(srctree)/arch/mips/include/asm/mach-loongson2ef -mno-branch-likely
+load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
+load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
diff --git a/arch/mips/loongson64/common/Makefile b/arch/mips/loongson2ef/common/Makefile
similarity index 100%
rename from arch/mips/loongson64/common/Makefile
rename to arch/mips/loongson2ef/common/Makefile
diff --git a/arch/mips/loongson64/common/bonito-irq.c b/arch/mips/loongson2ef/common/bonito-irq.c
similarity index 97%
rename from arch/mips/loongson64/common/bonito-irq.c
rename to arch/mips/loongson2ef/common/bonito-irq.c
index 82352cc25e4c..e59248c53bc5 100644
--- a/arch/mips/loongson64/common/bonito-irq.c
+++ b/arch/mips/loongson2ef/common/bonito-irq.c
@@ -10,7 +10,7 @@
#include <linux/interrupt.h>
#include <linux/compiler.h>
-#include <loongson.h>
+#include <loongson2ef.h>
static inline void bonito_irq_enable(struct irq_data *d)
{
diff --git a/arch/mips/loongson64/common/cmdline.c b/arch/mips/loongson2ef/common/cmdline.c
similarity index 97%
rename from arch/mips/loongson64/common/cmdline.c
rename to arch/mips/loongson2ef/common/cmdline.c
index a735460682cf..ab126a7cefdc 100644
--- a/arch/mips/loongson64/common/cmdline.c
+++ b/arch/mips/loongson2ef/common/cmdline.c
@@ -15,7 +15,7 @@
*/
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
void __init prom_init_cmdline(void)
{
diff --git a/arch/mips/loongson64/common/cs5536/Makefile b/arch/mips/loongson2ef/common/cs5536/Makefile
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/Makefile
rename to arch/mips/loongson2ef/common/cs5536/Makefile
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_acc.c b/arch/mips/loongson2ef/common/cs5536/cs5536_acc.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_acc.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_acc.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ehci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ehci.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_ehci.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_ehci.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ide.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ide.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_ide.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_ide.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_isa.c b/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_isa.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_isa.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_ohci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_ohci.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_ohci.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_ohci.c
diff --git a/arch/mips/loongson64/common/cs5536/cs5536_pci.c b/arch/mips/loongson2ef/common/cs5536/cs5536_pci.c
similarity index 100%
rename from arch/mips/loongson64/common/cs5536/cs5536_pci.c
rename to arch/mips/loongson2ef/common/cs5536/cs5536_pci.c
diff --git a/arch/mips/loongson64/common/early_printk.c b/arch/mips/loongson2ef/common/early_printk.c
similarity index 97%
rename from arch/mips/loongson64/common/early_printk.c
rename to arch/mips/loongson2ef/common/early_printk.c
index 5e2a151aa30c..e22d16728e13 100644
--- a/arch/mips/loongson64/common/early_printk.c
+++ b/arch/mips/loongson2ef/common/early_printk.c
@@ -8,7 +8,7 @@
#include <linux/serial_reg.h>
#include <asm/setup.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#define PORT(base, offset) (u8 *)(base + offset)
diff --git a/arch/mips/loongson2ef/common/env.c b/arch/mips/loongson2ef/common/env.c
new file mode 100644
index 000000000000..03a8d0165d2e
--- /dev/null
+++ b/arch/mips/loongson2ef/common/env.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Based on Ocelot Linux port, which is
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: [email protected] or [email protected]
+ *
+ * Copyright 2003 ICT CAS
+ * Author: Michael Guo <[email protected]>
+ *
+ * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, [email protected]
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, [email protected]
+ */
+#include <linux/export.h>
+#include <asm/bootinfo.h>
+#include <loongson2ef.h>
+
+u32 cpu_clock_freq;
+EXPORT_SYMBOL(cpu_clock_freq);
+
+unsigned long long smp_group[4];
+
+#define parse_even_earlier(res, option, p) \
+do { \
+ unsigned int tmp __maybe_unused; \
+ \
+ if (strncmp(option, (char *)p, strlen(option)) == 0) \
+ tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \
+} while (0)
+
+void __init prom_init_env(void)
+{
+ /* pmon passes arguments in 32bit pointers */
+ unsigned int processor_id;
+ int *_prom_envp;
+ long l;
+
+ /* firmware arguments are initialized in head.S */
+ _prom_envp = (int *)fw_arg2;
+
+ l = (long)*_prom_envp;
+ while (l != 0) {
+ parse_even_earlier(cpu_clock_freq, "cpuclock", l);
+ parse_even_earlier(memsize, "memsize", l);
+ parse_even_earlier(highmemsize, "highmemsize", l);
+ _prom_envp++;
+ l = (long)*_prom_envp;
+ }
+ if (memsize == 0)
+ memsize = 256;
+
+ pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize);
+
+ if (cpu_clock_freq == 0) {
+ processor_id = (¤t_cpu_data)->processor_id;
+ switch (processor_id & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON2E:
+ cpu_clock_freq = 533080000;
+ break;
+ case PRID_REV_LOONGSON2F:
+ cpu_clock_freq = 797000000;
+ break;
+ default:
+ cpu_clock_freq = 100000000;
+ break;
+ }
+ }
+ pr_info("CpuClock = %u\n", cpu_clock_freq);
+}
diff --git a/arch/mips/loongson64/common/init.c b/arch/mips/loongson2ef/common/init.c
similarity index 90%
rename from arch/mips/loongson64/common/init.c
rename to arch/mips/loongson2ef/common/init.c
index 912fe61c4fc7..b65763818911 100644
--- a/arch/mips/loongson64/common/init.c
+++ b/arch/mips/loongson2ef/common/init.c
@@ -10,7 +10,7 @@
#include <asm/smp-ops.h>
#include <asm/cacheflush.h>
-#include <loongson.h>
+#include <loongson2ef.h>
/* Loongson CPU address windows config space base address */
unsigned long __maybe_unused _loongson_addrwincfg_base;
@@ -39,15 +39,10 @@ void __init prom_init(void)
set_io_port_base((unsigned long)
ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
-#ifdef CONFIG_NUMA
- prom_init_numa_memory();
-#else
prom_init_memory();
-#endif
/*init the uart base address */
prom_init_uart_base();
- register_smp_ops(&loongson3_smp_ops);
board_nmi_handler_setup = mips_nmi_setup;
}
diff --git a/arch/mips/loongson64/common/irq.c b/arch/mips/loongson2ef/common/irq.c
similarity index 98%
rename from arch/mips/loongson64/common/irq.c
rename to arch/mips/loongson2ef/common/irq.c
index 0ea93c1c0a97..96d492511e41 100644
--- a/arch/mips/loongson64/common/irq.c
+++ b/arch/mips/loongson2ef/common/irq.c
@@ -6,7 +6,7 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
-#include <loongson.h>
+#include <loongson2ef.h>
/*
* the first level int-handler will jump here if it is a bonito irq
*/
diff --git a/arch/mips/loongson64/common/machtype.c b/arch/mips/loongson2ef/common/machtype.c
similarity index 94%
rename from arch/mips/loongson64/common/machtype.c
rename to arch/mips/loongson2ef/common/machtype.c
index 4e42d929f1c7..d2ea4d25246a 100644
--- a/arch/mips/loongson64/common/machtype.c
+++ b/arch/mips/loongson2ef/common/machtype.c
@@ -8,7 +8,7 @@
#include <linux/errno.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <machine.h>
/* please ensure the length of the machtype string is less than 50 */
@@ -23,7 +23,6 @@ static const char *system_types[] = {
[MACH_DEXXON_GDIUM2F10] = "dexxon-gdium-2f",
[MACH_LEMOTE_NAS] = "lemote-nas-2f",
[MACH_LEMOTE_LL2F] = "lemote-lynloong-2f",
- [MACH_LOONGSON_GENERIC] = "generic-loongson-machine",
[MACH_LOONGSON_END] = NULL,
};
diff --git a/arch/mips/loongson64/common/mem.c b/arch/mips/loongson2ef/common/mem.c
similarity index 72%
rename from arch/mips/loongson64/common/mem.c
rename to arch/mips/loongson2ef/common/mem.c
index 4abb92e0fc39..c90beb048233 100644
--- a/arch/mips/loongson64/common/mem.c
+++ b/arch/mips/loongson2ef/common/mem.c
@@ -7,12 +7,10 @@
#include <asm/bootinfo.h>
-#include <loongson.h>
-#include <boot_param.h>
+#include <loongson2ef.h>
#include <mem.h>
#include <pci.h>
-#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
u32 memsize, highmemsize;
@@ -51,42 +49,6 @@ void __init prom_init_memory(void)
#endif /* !CONFIG_64BIT */
}
-#else /* CONFIG_LEFI_FIRMWARE_INTERFACE */
-
-void __init prom_init_memory(void)
-{
- int i;
- u32 node_id;
- u32 mem_type;
-
- /* parse memory information */
- for (i = 0; i < loongson_memmap->nr_map; i++) {
- node_id = loongson_memmap->map[i].node_id;
- mem_type = loongson_memmap->map[i].mem_type;
-
- if (node_id == 0) {
- switch (mem_type) {
- case SYSTEM_RAM_LOW:
- add_memory_region(loongson_memmap->map[i].mem_start,
- (u64)loongson_memmap->map[i].mem_size << 20,
- BOOT_MEM_RAM);
- break;
- case SYSTEM_RAM_HIGH:
- add_memory_region(loongson_memmap->map[i].mem_start,
- (u64)loongson_memmap->map[i].mem_size << 20,
- BOOT_MEM_RAM);
- break;
- case SYSTEM_RAM_RESERVED:
- add_memory_region(loongson_memmap->map[i].mem_start,
- (u64)loongson_memmap->map[i].mem_size << 20,
- BOOT_MEM_RESERVED);
- break;
- }
- }
- }
-}
-
-#endif /* CONFIG_LEFI_FIRMWARE_INTERFACE */
/* override of arch/mips/mm/cache.c: __uncached_access */
int __uncached_access(struct file *file, unsigned long addr)
diff --git a/arch/mips/loongson64/common/pci.c b/arch/mips/loongson2ef/common/pci.c
similarity index 89%
rename from arch/mips/loongson64/common/pci.c
rename to arch/mips/loongson2ef/common/pci.c
index 2d9755c49524..3df8d1695243 100644
--- a/arch/mips/loongson64/common/pci.c
+++ b/arch/mips/loongson2ef/common/pci.c
@@ -6,8 +6,7 @@
#include <linux/pci.h>
#include <pci.h>
-#include <loongson.h>
-#include <boot_param.h>
+#include <loongson2ef.h>
static struct resource loongson_pci_mem_resource = {
.name = "pci memory space",
@@ -81,16 +80,8 @@ static int __init pcibios_init(void)
setup_pcimap();
loongson_pci_controller.io_map_base = mips_io_port_base;
-#ifdef CONFIG_LEFI_FIRMWARE_INTERFACE
- loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
- loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
-#endif
register_pci_controller(&loongson_pci_controller);
-#ifdef CONFIG_CPU_LOONGSON64
- sbx00_acpi_init();
-#endif
-
return 0;
}
diff --git a/arch/mips/loongson64/common/platform.c b/arch/mips/loongson2ef/common/platform.c
similarity index 100%
rename from arch/mips/loongson64/common/platform.c
rename to arch/mips/loongson2ef/common/platform.c
diff --git a/arch/mips/loongson64/common/pm.c b/arch/mips/loongson2ef/common/pm.c
similarity index 99%
rename from arch/mips/loongson64/common/pm.c
rename to arch/mips/loongson2ef/common/pm.c
index b8aed878d912..0e3c9f245215 100644
--- a/arch/mips/loongson64/common/pm.c
+++ b/arch/mips/loongson2ef/common/pm.c
@@ -12,7 +12,7 @@
#include <asm/i8259.h>
#include <asm/mipsregs.h>
-#include <loongson.h>
+#include <loongson2ef.h>
static unsigned int __maybe_unused cached_master_mask; /* i8259A */
static unsigned int __maybe_unused cached_slave_mask;
diff --git a/arch/mips/loongson64/common/reset.c b/arch/mips/loongson2ef/common/reset.c
similarity index 77%
rename from arch/mips/loongson64/common/reset.c
rename to arch/mips/loongson2ef/common/reset.c
index ce39e918e4d5..fc296ac979c6 100644
--- a/arch/mips/loongson64/common/reset.c
+++ b/arch/mips/loongson2ef/common/reset.c
@@ -12,8 +12,7 @@
#include <asm/idle.h>
#include <asm/reboot.h>
-#include <loongson.h>
-#include <boot_param.h>
+#include <loongson2ef.h>
static inline void loongson_reboot(void)
{
@@ -35,26 +34,15 @@ static inline void loongson_reboot(void)
static void loongson_restart(char *command)
{
-#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
/* do preparation for reboot */
mach_prepare_reboot();
/* reboot via jumping to boot base address */
loongson_reboot();
-#else
- void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr;
-
- fw_restart();
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
-#endif
}
static void loongson_poweroff(void)
{
-#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
mach_prepare_shutdown();
/*
@@ -62,15 +50,6 @@ static void loongson_poweroff(void)
* a generic delay loop, machine_hang(), so simply return.
*/
return;
-#else
- void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr;
-
- fw_poweroff();
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
-#endif
}
static void loongson_halt(void)
diff --git a/arch/mips/loongson64/common/rtc.c b/arch/mips/loongson2ef/common/rtc.c
similarity index 100%
rename from arch/mips/loongson64/common/rtc.c
rename to arch/mips/loongson2ef/common/rtc.c
diff --git a/arch/mips/loongson64/common/serial.c b/arch/mips/loongson2ef/common/serial.c
similarity index 63%
rename from arch/mips/loongson64/common/serial.c
rename to arch/mips/loongson2ef/common/serial.c
index ffefc1cb2612..4203486b1570 100644
--- a/arch/mips/loongson64/common/serial.c
+++ b/arch/mips/loongson2ef/common/serial.c
@@ -16,7 +16,7 @@
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <machine.h>
#define PORT(int, clk) \
@@ -38,7 +38,7 @@
.regshift = 0, \
}
-static struct plat_serial8250_port uart8250_data[][MAX_UARTS + 1] = {
+static struct plat_serial8250_port uart8250_data[][16] = {
[MACH_LOONGSON_UNKNOWN] = {},
[MACH_LEMOTE_FL2E] = {PORT(4, 1843200), {} },
[MACH_LEMOTE_FL2F] = {PORT(3, 1843200), {} },
@@ -47,7 +47,6 @@ static struct plat_serial8250_port uart8250_data[][MAX_UARTS + 1] = {
[MACH_DEXXON_GDIUM2F10] = {PORT_M(3, 3686400), {} },
[MACH_LEMOTE_NAS] = {PORT_M(3, 3686400), {} },
[MACH_LEMOTE_LL2F] = {PORT(3, 1843200), {} },
- [MACH_LOONGSON_GENERIC] = {PORT_M(2, 25000000), {} },
[MACH_LOONGSON_END] = {},
};
@@ -58,7 +57,6 @@ static struct platform_device uart8250_device = {
static int __init serial_init(void)
{
- int i;
unsigned char iotype;
iotype = uart8250_data[mips_machtype][0].iotype;
@@ -73,36 +71,7 @@ static int __init serial_init(void)
uart8250_data[mips_machtype][0].iobase =
loongson_uart_base[0] - LOONGSON_PCIIO_BASE;
- if (loongson_sysconf.uarts[0].uartclk)
- uart8250_data[mips_machtype][0].uartclk =
- loongson_sysconf.uarts[0].uartclk;
-
- for (i = 1; i < loongson_sysconf.nr_uarts; i++) {
- iotype = loongson_sysconf.uarts[i].iotype;
- uart8250_data[mips_machtype][i].iotype = iotype;
- loongson_uart_base[i] = loongson_sysconf.uarts[i].uart_base;
-
- if (UPIO_MEM == iotype) {
- uart8250_data[mips_machtype][i].irq =
- MIPS_CPU_IRQ_BASE + loongson_sysconf.uarts[i].int_offset;
- uart8250_data[mips_machtype][i].mapbase =
- loongson_uart_base[i];
- uart8250_data[mips_machtype][i].membase =
- ioremap_nocache(loongson_uart_base[i], 8);
- } else if (UPIO_PORT == iotype) {
- uart8250_data[mips_machtype][i].irq =
- loongson_sysconf.uarts[i].int_offset;
- uart8250_data[mips_machtype][i].iobase =
- loongson_uart_base[i] - LOONGSON_PCIIO_BASE;
- }
-
- uart8250_data[mips_machtype][i].uartclk =
- loongson_sysconf.uarts[i].uartclk;
- uart8250_data[mips_machtype][i].flags =
- UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- }
-
- memset(&uart8250_data[mips_machtype][loongson_sysconf.nr_uarts],
+ memset(&uart8250_data[mips_machtype][1],
0, sizeof(struct plat_serial8250_port));
uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
diff --git a/arch/mips/loongson64/common/setup.c b/arch/mips/loongson2ef/common/setup.c
similarity index 97%
rename from arch/mips/loongson64/common/setup.c
rename to arch/mips/loongson2ef/common/setup.c
index bc2da4c140c4..278d2b62d9a6 100644
--- a/arch/mips/loongson64/common/setup.c
+++ b/arch/mips/loongson2ef/common/setup.c
@@ -9,7 +9,7 @@
#include <asm/wbflush.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#ifdef CONFIG_VT
#include <linux/console.h>
diff --git a/arch/mips/loongson64/common/time.c b/arch/mips/loongson2ef/common/time.c
similarity index 96%
rename from arch/mips/loongson64/common/time.c
rename to arch/mips/loongson2ef/common/time.c
index e78760ce475b..b29f89a9db8e 100644
--- a/arch/mips/loongson64/common/time.c
+++ b/arch/mips/loongson2ef/common/time.c
@@ -10,7 +10,7 @@
#include <asm/time.h>
#include <asm/hpet.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <cs5536/cs5536_mfgpt.h>
void __init plat_time_init(void)
diff --git a/arch/mips/loongson64/common/uart_base.c b/arch/mips/loongson2ef/common/uart_base.c
similarity index 77%
rename from arch/mips/loongson64/common/uart_base.c
rename to arch/mips/loongson2ef/common/uart_base.c
index e88d937f10fe..27d073f1cd48 100644
--- a/arch/mips/loongson64/common/uart_base.c
+++ b/arch/mips/loongson2ef/common/uart_base.c
@@ -7,12 +7,12 @@
#include <linux/export.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
/* raw */
-unsigned long loongson_uart_base[MAX_UARTS] = {};
+unsigned long loongson_uart_base[16] = {};
/* ioremapped */
-unsigned long _loongson_uart_base[MAX_UARTS] = {};
+unsigned long _loongson_uart_base[16] = {};
EXPORT_SYMBOL(loongson_uart_base);
EXPORT_SYMBOL(_loongson_uart_base);
@@ -20,10 +20,6 @@ EXPORT_SYMBOL(_loongson_uart_base);
void prom_init_loongson_uart_base(void)
{
switch (mips_machtype) {
- case MACH_LOONGSON_GENERIC:
- /* The CPU provided serial port (CPU) */
- loongson_uart_base[0] = LOONGSON_REG_BASE + 0x1e0;
- break;
case MACH_LEMOTE_FL2E:
loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x3f8;
break;
diff --git a/arch/mips/loongson64/fuloong-2e/Makefile b/arch/mips/loongson2ef/fuloong-2e/Makefile
similarity index 100%
rename from arch/mips/loongson64/fuloong-2e/Makefile
rename to arch/mips/loongson2ef/fuloong-2e/Makefile
diff --git a/arch/mips/loongson64/fuloong-2e/dma.c b/arch/mips/loongson2ef/fuloong-2e/dma.c
similarity index 100%
rename from arch/mips/loongson64/fuloong-2e/dma.c
rename to arch/mips/loongson2ef/fuloong-2e/dma.c
diff --git a/arch/mips/loongson64/fuloong-2e/irq.c b/arch/mips/loongson2ef/fuloong-2e/irq.c
similarity index 98%
rename from arch/mips/loongson64/fuloong-2e/irq.c
rename to arch/mips/loongson2ef/fuloong-2e/irq.c
index 32278e7bf85c..caaf9e907dd2 100644
--- a/arch/mips/loongson64/fuloong-2e/irq.c
+++ b/arch/mips/loongson2ef/fuloong-2e/irq.c
@@ -8,7 +8,7 @@
#include <asm/irq_cpu.h>
#include <asm/i8259.h>
-#include <loongson.h>
+#include <loongson2ef.h>
static void i8259_irqdispatch(void)
{
diff --git a/arch/mips/loongson64/fuloong-2e/reset.c b/arch/mips/loongson2ef/fuloong-2e/reset.c
similarity index 93%
rename from arch/mips/loongson64/fuloong-2e/reset.c
rename to arch/mips/loongson2ef/fuloong-2e/reset.c
index 8273de1cf4bb..df60685d0626 100644
--- a/arch/mips/loongson64/fuloong-2e/reset.c
+++ b/arch/mips/loongson2ef/fuloong-2e/reset.c
@@ -6,7 +6,7 @@
* Author: Wu Zhangjin, [email protected]
*/
-#include <loongson.h>
+#include <loongson2ef.h>
void mach_prepare_reboot(void)
{
diff --git a/arch/mips/loongson64/lemote-2f/Makefile b/arch/mips/loongson2ef/lemote-2f/Makefile
similarity index 100%
rename from arch/mips/loongson64/lemote-2f/Makefile
rename to arch/mips/loongson2ef/lemote-2f/Makefile
diff --git a/arch/mips/loongson64/lemote-2f/clock.c b/arch/mips/loongson2ef/lemote-2f/clock.c
similarity index 98%
rename from arch/mips/loongson64/lemote-2f/clock.c
rename to arch/mips/loongson2ef/lemote-2f/clock.c
index 8281334df9c8..83f7b9cabcd1 100644
--- a/arch/mips/loongson64/lemote-2f/clock.c
+++ b/arch/mips/loongson2ef/lemote-2f/clock.c
@@ -15,7 +15,7 @@
#include <linux/spinlock.h>
#include <asm/clock.h>
-#include <asm/mach-loongson64/loongson.h>
+#include <asm/mach-loongson2ef/loongson2ef.h>
static LIST_HEAD(clock_list);
static DEFINE_SPINLOCK(clock_lock);
diff --git a/arch/mips/loongson64/lemote-2f/dma.c b/arch/mips/loongson2ef/lemote-2f/dma.c
similarity index 100%
rename from arch/mips/loongson64/lemote-2f/dma.c
rename to arch/mips/loongson2ef/lemote-2f/dma.c
diff --git a/arch/mips/loongson64/lemote-2f/ec_kb3310b.c b/arch/mips/loongson2ef/lemote-2f/ec_kb3310b.c
similarity index 100%
rename from arch/mips/loongson64/lemote-2f/ec_kb3310b.c
rename to arch/mips/loongson2ef/lemote-2f/ec_kb3310b.c
diff --git a/arch/mips/loongson64/lemote-2f/ec_kb3310b.h b/arch/mips/loongson2ef/lemote-2f/ec_kb3310b.h
similarity index 100%
rename from arch/mips/loongson64/lemote-2f/ec_kb3310b.h
rename to arch/mips/loongson2ef/lemote-2f/ec_kb3310b.h
diff --git a/arch/mips/loongson64/lemote-2f/irq.c b/arch/mips/loongson2ef/lemote-2f/irq.c
similarity index 99%
rename from arch/mips/loongson64/lemote-2f/irq.c
rename to arch/mips/loongson2ef/lemote-2f/irq.c
index c58a044c6c07..2906f6fb2243 100644
--- a/arch/mips/loongson64/lemote-2f/irq.c
+++ b/arch/mips/loongson2ef/lemote-2f/irq.c
@@ -12,7 +12,7 @@
#include <asm/i8259.h>
#include <asm/mipsregs.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <machine.h>
#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
diff --git a/arch/mips/loongson64/lemote-2f/machtype.c b/arch/mips/loongson2ef/lemote-2f/machtype.c
similarity index 98%
rename from arch/mips/loongson64/lemote-2f/machtype.c
rename to arch/mips/loongson2ef/lemote-2f/machtype.c
index 9462a3ab57be..0200e4223771 100644
--- a/arch/mips/loongson64/lemote-2f/machtype.c
+++ b/arch/mips/loongson2ef/lemote-2f/machtype.c
@@ -5,7 +5,7 @@
*/
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
void __init mach_prom_init_machtype(void)
{
diff --git a/arch/mips/loongson64/lemote-2f/pm.c b/arch/mips/loongson2ef/lemote-2f/pm.c
similarity index 99%
rename from arch/mips/loongson64/lemote-2f/pm.c
rename to arch/mips/loongson2ef/lemote-2f/pm.c
index 3d0027229e3c..339601752d40 100644
--- a/arch/mips/loongson64/lemote-2f/pm.c
+++ b/arch/mips/loongson2ef/lemote-2f/pm.c
@@ -16,7 +16,7 @@
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <cs5536/cs5536_mfgpt.h>
#include "ec_kb3310b.h"
diff --git a/arch/mips/loongson64/lemote-2f/reset.c b/arch/mips/loongson2ef/lemote-2f/reset.c
similarity index 99%
rename from arch/mips/loongson64/lemote-2f/reset.c
rename to arch/mips/loongson2ef/lemote-2f/reset.c
index 0db0934302ea..faec0d919889 100644
--- a/arch/mips/loongson64/lemote-2f/reset.c
+++ b/arch/mips/loongson2ef/lemote-2f/reset.c
@@ -13,7 +13,7 @@
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <cs5536/cs5536.h>
#include "ec_kb3310b.h"
diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index d08b20ff2b27..025cd274146f 100644
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -1,119 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
if MACH_LOONGSON64
-choice
- prompt "Machine Type"
-
-config LEMOTE_FULOONG2E
- bool "Lemote Fuloong(2e) mini-PC"
- select ARCH_SPARSEMEM_ENABLE
- select ARCH_MIGHT_HAVE_PC_PARPORT
- select ARCH_MIGHT_HAVE_PC_SERIO
- select CEVT_R4K
- select CSRC_R4K
- select SYS_HAS_CPU_LOONGSON2E
- select DMA_NONCOHERENT
- select BOOT_ELF32
- select BOARD_SCACHE
- select HAVE_PCI
- select I8259
- select ISA
- select IRQ_MIPS_CPU
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
- select SYS_HAS_EARLY_PRINTK
- select GENERIC_ISA_DMA_SUPPORT_BROKEN
- select CPU_HAS_WB
- select LOONGSON_MC146818
- help
- Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
- an FPGA northbridge
-
- Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
-
-config LEMOTE_MACH2F
- bool "Lemote Loongson 2F family machines"
- select ARCH_SPARSEMEM_ENABLE
- select ARCH_MIGHT_HAVE_PC_PARPORT
- select ARCH_MIGHT_HAVE_PC_SERIO
- select BOARD_SCACHE
- select BOOT_ELF32
- select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
- select CPU_HAS_WB
- select CS5536
- select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
- select DMA_NONCOHERENT
- select GENERIC_ISA_DMA_SUPPORT_BROKEN
- select HAVE_CLK
- select HAVE_PCI
- select I8259
- select IRQ_MIPS_CPU
- select ISA
- select SYS_HAS_CPU_LOONGSON2F
- select SYS_HAS_EARLY_PRINTK
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_HIGHMEM
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select LOONGSON_MC146818
- help
- Lemote Loongson 2F family machines utilize the 2F revision of
- Loongson processor and the AMD CS5536 south bridge.
-
- These family machines include fuloong2f mini PC, yeeloong2f notebook,
- LingLoong allinone PC and so forth.
-
-config LOONGSON_MACH3X
- bool "Generic Loongson 3 family machines"
- select ARCH_SPARSEMEM_ENABLE
- select ARCH_MIGHT_HAVE_PC_PARPORT
- select ARCH_MIGHT_HAVE_PC_SERIO
- select GENERIC_ISA_DMA_SUPPORT_BROKEN
- select BOOT_ELF32
- select BOARD_SCACHE
- select CSRC_R4K
- select CEVT_R4K
- select CPU_HAS_WB
- select FORCE_PCI
- select ISA
- select I8259
- select IRQ_MIPS_CPU
- select NR_CPUS_DEFAULT_4
- select SYS_HAS_CPU_LOONGSON64
- select SYS_HAS_EARLY_PRINTK
- select SYS_SUPPORTS_SMP
- select SYS_SUPPORTS_HOTPLUG_CPU
- select SYS_SUPPORTS_NUMA
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_HIGHMEM
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select LOONGSON_MC146818
- select ZONE_DMA32
- select LEFI_FIRMWARE_INTERFACE
- help
- Generic Loongson 3 family machines utilize the 3A/3B revision
- of Loongson processor and RS780/SBX00 chipset.
-endchoice
-
-config CS5536
- bool
-
-config CS5536_MFGPT
- bool "CS5536 MFGPT Timer"
- depends on CS5536 && !HIGH_RES_TIMERS
- select MIPS_EXTERNAL_TIMER
- help
- This option enables the mfgpt0 timer of AMD CS5536. With this timer
- switched on you can not use high resolution timers.
-
- If you want to enable the Loongson2 CPUFreq Driver, Please enable
- this option at first, otherwise, You will get wrong system time.
-
- If unsure, say Yes.
-
config RS780_HPET
bool "RS780/SBX00 HPET Timer"
- depends on LOONGSON_MACH3X
+ depends on MACH_LOONGSON64
select MIPS_EXTERNAL_TIMER
help
This option enables the hpet timer of AMD RS780/SBX00.
@@ -123,16 +13,4 @@ config RS780_HPET
If unsure, say Yes.
-config LOONGSON_UART_BASE
- bool
- default y
- depends on EARLY_PRINTK || SERIAL_8250
-
-config LOONGSON_MC146818
- bool
- default n
-
-config LEFI_FIRMWARE_INTERFACE
- bool
-
-endif # MACH_LOONGSON64
+endif
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index c74bc0251e9d..3c92e04e3827 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -1,24 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-only
#
-# Common code for all Loongson based systems
+# Makefile for Loongson64 family machines
#
+obj-y += irq.o cop2-ex.o platform.o acpi_init.o dma.o env.o platform.o reset.o setup.o pci.o
-obj-$(CONFIG_MACH_LOONGSON64) += common/
+obj-$(CONFIG_SMP) += smp.o
-#
-# Lemote Fuloong mini-PC (Loongson 2E-based)
-#
-
-obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
-
-#
-# Lemote loongson2f family machines
-#
-
-obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
-
-#
-# All Loongson-3 family machines
-#
+obj-$(CONFIG_NUMA) += numa.o
-obj-$(CONFIG_CPU_LOONGSON64) += loongson-3/
+obj-$(CONFIG_RS780_HPET) += hpet.o
diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform
index b4d2582eb1ef..7f4006833fa5 100644
--- a/arch/mips/loongson64/Platform
+++ b/arch/mips/loongson64/Platform
@@ -1,27 +1,7 @@
#
-# Loongson Processors' Support
+# Loongson64 Processors' Support
#
-# Only gcc >= 4.4 have Loongson specific support
-cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2E) += \
- $(call cc-option,-march=loongson2e,-march=r4600)
-cflags-$(CONFIG_CPU_LOONGSON2F) += \
- $(call cc-option,-march=loongson2f,-march=r4600)
-# Enable the workarounds for Loongson2f
-ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
- ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
- $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
- else
- cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
- endif
- ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
- $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
- else
- cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
- endif
-endif
-
cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
#
@@ -72,6 +52,4 @@ endif
platform-$(CONFIG_MACH_LOONGSON64) += loongson64/
cflags-$(CONFIG_MACH_LOONGSON64) += -I$(srctree)/arch/mips/include/asm/mach-loongson64 -mno-branch-likely
-load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
-load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
-load-$(CONFIG_LOONGSON_MACH3X) += 0xffffffff80200000
+load-$(CONFIG_MACH_LOONGSON64) += 0xffffffff80200000
diff --git a/arch/mips/loongson64/loongson-3/acpi_init.c b/arch/mips/loongson64/acpi_init.c
similarity index 99%
rename from arch/mips/loongson64/loongson-3/acpi_init.c
rename to arch/mips/loongson64/acpi_init.c
index 8d7c119ddf91..3dd8135d2911 100644
--- a/arch/mips/loongson64/loongson-3/acpi_init.c
+++ b/arch/mips/loongson64/acpi_init.c
@@ -99,7 +99,8 @@ void acpi_registers_setup(void)
pm_iowrite(0x2f, ACPI_END >> 8);
/* IO Decode: When AcpiDecodeEnable set, South-Bridge uses the contents
- * of the PM registers at index 0x20~0x2B to decode ACPI I/O address. */
+ * of the PM registers at index 0x20~0x2B to decode ACPI I/O address.
+ */
pm_iowrite(0x0e, 1 << 3);
/* SCI_EN set */
diff --git a/arch/mips/loongson64/loongson-3/cop2-ex.c b/arch/mips/loongson64/cop2-ex.c
similarity index 88%
rename from arch/mips/loongson64/loongson-3/cop2-ex.c
rename to arch/mips/loongson64/cop2-ex.c
index 9efdfe430ff0..508c707627ba 100644
--- a/arch/mips/loongson64/loongson-3/cop2-ex.c
+++ b/arch/mips/loongson64/cop2-ex.c
@@ -1,8 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 2014 Lemote Corporation.
* written by Huacai Chen <[email protected]>
*
diff --git a/arch/mips/loongson64/loongson-3/dma.c b/arch/mips/loongson64/dma.c
similarity index 82%
rename from arch/mips/loongson64/loongson-3/dma.c
rename to arch/mips/loongson64/dma.c
index 5e86635f71db..e2c3354d1d30 100644
--- a/arch/mips/loongson64/loongson-3/dma.c
+++ b/arch/mips/loongson64/dma.c
@@ -6,7 +6,8 @@
dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
/* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from
- * Loongson-3's 48bit address space and embed it into 40bit */
+ * Loongson-3's 48bit address space and embed it into 40bit
+ */
long nid = (paddr >> 44) & 0x3;
return ((nid << 44) ^ paddr) | (nid << 37);
}
@@ -14,7 +15,8 @@ dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
/* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from
- * Loongson-3's 48bit address space and embed it into 40bit */
+ * Loongson-3's 48bit address space and embed it into 40bit
+ */
long nid = (daddr >> 37) & 0x3;
return ((nid << 37) ^ daddr) | (nid << 44);
}
diff --git a/arch/mips/loongson64/common/env.c b/arch/mips/loongson64/env.c
similarity index 79%
rename from arch/mips/loongson64/common/env.c
rename to arch/mips/loongson64/env.c
index 09d5cf4676ca..93658cfbf3a6 100644
--- a/arch/mips/loongson64/common/env.c
+++ b/arch/mips/loongson64/env.c
@@ -15,7 +15,10 @@
*/
#include <linux/export.h>
#include <asm/bootinfo.h>
-#include <loongson.h>
+#include <asm/time.h>
+#include <asm/prom.h>
+
+#include <loongson64.h>
#include <boot_param.h>
#include <workarounds.h>
@@ -30,45 +33,17 @@ u64 loongson_freqctrl[MAX_PACKAGES];
unsigned long long smp_group[4];
-#define parse_even_earlier(res, option, p) \
-do { \
- unsigned int tmp __maybe_unused; \
- \
- if (strncmp(option, (char *)p, strlen(option)) == 0) \
- tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \
-} while (0)
-void __init prom_init_env(void)
+void __init prom_init_lefi(void)
{
/* pmon passes arguments in 32bit pointers */
unsigned int processor_id;
-#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
- int *_prom_envp;
- long l;
-
- /* firmware arguments are initialized in head.S */
- _prom_envp = (int *)fw_arg2;
-
- l = (long)*_prom_envp;
- while (l != 0) {
- parse_even_earlier(cpu_clock_freq, "cpuclock", l);
- parse_even_earlier(memsize, "memsize", l);
- parse_even_earlier(highmemsize, "highmemsize", l);
- _prom_envp++;
- l = (long)*_prom_envp;
- }
- if (memsize == 0)
- memsize = 256;
-
- loongson_sysconf.nr_uarts = 1;
-
- pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize);
-#else
struct boot_params *boot_p;
struct loongson_params *loongson_p;
struct system_loongson *esys;
struct efi_cpuinfo_loongson *ecpu;
+ struct board_devices *eboard;
struct irq_source_routing_table *eirq_source;
/* firmware arguments are initialized in head.S */
@@ -79,12 +54,15 @@ void __init prom_init_env(void)
((u64)loongson_p + loongson_p->system_offset);
ecpu = (struct efi_cpuinfo_loongson *)
((u64)loongson_p + loongson_p->cpu_offset);
+ eboard = (struct board_devices *)
+ ((u64)loongson_p + loongson_p->boarddev_table_offset);
eirq_source = (struct irq_source_routing_table *)
((u64)loongson_p + loongson_p->irq_offset);
loongson_memmap = (struct efi_memory_map_loongson *)
((u64)loongson_p + loongson_p->memory_offset);
cpu_clock_freq = ecpu->cpu_clock_freq;
+ mips_hpt_frequency = cpu_clock_freq / 2;
loongson_sysconf.cputype = ecpu->cputype;
switch (ecpu->cputype) {
case Legacy_3A:
@@ -151,6 +129,7 @@ void __init prom_init_env(void)
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
+ set_io_port_base(loongson_sysconf.pci_io_base);
loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
if (loongson_sysconf.dma_mask_bits < 32 ||
loongson_sysconf.dma_mask_bits > 64)
@@ -165,6 +144,9 @@ void __init prom_init_env(void)
loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
loongson_sysconf.vgabios_addr);
+ if (eboard->name)
+ mips_set_machine_name(eboard->name);
+
memset(loongson_sysconf.ecname, 0, 32);
if (esys->has_ec)
memcpy(loongson_sysconf.ecname, esys->ec_name, 32);
@@ -182,31 +164,7 @@ void __init prom_init_env(void)
if (loongson_sysconf.nr_sensors)
memcpy(loongson_sysconf.sensors, esys->sensors,
sizeof(struct sensor_device) * loongson_sysconf.nr_sensors);
-#endif
- if (cpu_clock_freq == 0) {
- processor_id = (¤t_cpu_data)->processor_id;
- switch (processor_id & PRID_REV_MASK) {
- case PRID_REV_LOONGSON2E:
- cpu_clock_freq = 533080000;
- break;
- case PRID_REV_LOONGSON2F:
- cpu_clock_freq = 797000000;
- break;
- case PRID_REV_LOONGSON3A_R1:
- case PRID_REV_LOONGSON3A_R2_0:
- case PRID_REV_LOONGSON3A_R2_1:
- case PRID_REV_LOONGSON3A_R3_0:
- case PRID_REV_LOONGSON3A_R3_1:
- cpu_clock_freq = 900000000;
- break;
- case PRID_REV_LOONGSON3B_R1:
- case PRID_REV_LOONGSON3B_R2:
- cpu_clock_freq = 1000000000;
- break;
- default:
- cpu_clock_freq = 100000000;
- break;
- }
- }
+ processor_id = (¤t_cpu_data)->processor_id;
+
pr_info("CpuClock = %u\n", cpu_clock_freq);
}
diff --git a/arch/mips/loongson64/loongson-3/hpet.c b/arch/mips/loongson64/hpet.c
similarity index 100%
rename from arch/mips/loongson64/loongson-3/hpet.c
rename to arch/mips/loongson64/hpet.c
diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/irq.c
similarity index 77%
rename from arch/mips/loongson64/loongson-3/irq.c
rename to arch/mips/loongson64/irq.c
index 5605061f5f98..4d7b80a0ffb9 100644
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/irq.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <loongson.h>
+#include <loongson64.h>
#include <irq.h>
#include <linux/interrupt.h>
#include <linux/init.h>
@@ -10,6 +10,19 @@
#include "smp.h"
+/* ICU Configuration Regs - r/w */
+
+#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
+#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
+#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
+#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
+#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
+#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
+
extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
unsigned int irq_cpu[16] = {[0 ... 15] = -1};
@@ -78,13 +91,17 @@ static void ht_irqdispatch(void)
#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-void mach_irq_dispatch(unsigned int pending)
+asmlinkage void plat_irq_dispatch(void)
{
+ unsigned int pending;
+
+ pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
if (pending & CAUSEF_IP7)
do_IRQ(LOONGSON_TIMER_IRQ);
#if defined(CONFIG_SMP)
if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt(NULL);
+ loongson3_ipi_interrupt();
#endif
if (pending & CAUSEF_IP3)
ht_irqdispatch();
@@ -127,10 +144,25 @@ void irq_router_init(void)
LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
}
-void __init mach_init_irq(void)
+void __init arch_init_irq(void)
{
struct irq_chip *chip;
+ /*
+ * Clear all of the interrupts while we change the able around a bit.
+ * int-handler is not on bootstrap
+ */
+ clear_c0_status(ST0_IM | ST0_BEV);
+
+ /* no steer */
+ LOONGSON_INTSTEER = 0;
+
+ /*
+ * Mask out all interrupt by writing "1" to all bit position in
+ * the interrupt reset reg.
+ */
+ LOONGSON_INTENCLR = ~0;
+
clear_c0_status(ST0_IM | ST0_BEV);
irq_router_init();
diff --git a/arch/mips/loongson64/loongson-3/Makefile b/arch/mips/loongson64/loongson-3/Makefile
deleted file mode 100644
index df39598742b2..000000000000
--- a/arch/mips/loongson64/loongson-3/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Makefile for Loongson-3 family machines
-#
-obj-y += irq.o cop2-ex.o platform.o acpi_init.o dma.o
-
-obj-$(CONFIG_SMP) += smp.o
-
-obj-$(CONFIG_NUMA) += numa.o
-
-obj-$(CONFIG_RS780_HPET) += hpet.o
diff --git a/arch/mips/loongson64/loongson-3/numa.c b/arch/mips/loongson64/numa.c
similarity index 98%
rename from arch/mips/loongson64/loongson-3/numa.c
rename to arch/mips/loongson64/numa.c
index 414e97de5dc0..de3d3d682694 100644
--- a/arch/mips/loongson64/loongson-3/numa.c
+++ b/arch/mips/loongson64/numa.c
@@ -98,6 +98,7 @@ static void __init init_topology_matrix(void)
static unsigned long nid_to_addroffset(unsigned int nid)
{
unsigned long result;
+
switch (nid) {
case 0:
default:
@@ -119,7 +120,7 @@ static unsigned long nid_to_addroffset(unsigned int nid)
static void __init szmem(unsigned int node)
{
u32 i, mem_type;
- static unsigned long num_physpages = 0;
+ static unsigned long num_physpages;
u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size;
/* Parse memory information and activate */
@@ -276,4 +277,3 @@ void __init prom_init_numa_memory(void)
enable_lpa();
prom_meminit();
}
-EXPORT_SYMBOL(prom_init_numa_memory);
diff --git a/arch/mips/loongson64/pci.c b/arch/mips/loongson64/pci.c
new file mode 100644
index 000000000000..4e896817aadc
--- /dev/null
+++ b/arch/mips/loongson64/pci.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, [email protected]
+ */
+#include <linux/pci.h>
+
+#include <pci.h>
+#include <loongson64.h>
+
+static struct resource loongson_pci_mem_resource = {
+ .name = "PCI Memory Space",
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource loongson_pci_io_resource = {
+ .name = "PCI IO Space",
+ .end = IO_SPACE_LIMIT,
+ .flags = IORESOURCE_IO,
+};
+
+static struct pci_controller loongson_pci_controller = {
+ .pci_ops = &loongson_pci_ops,
+ .io_resource = &loongson_pci_io_resource,
+ .mem_resource = &loongson_pci_mem_resource,
+ .mem_offset = 0x00000000UL,
+ .io_offset = 0x00000000UL,
+};
+
+extern int sbx00_acpi_init(void);
+
+static int __init pcibios_init(void)
+{
+ loongson_pci_controller.io_map_base = mips_io_port_base;
+ loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
+ loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
+
+ register_pci_controller(&loongson_pci_controller);
+
+ sbx00_acpi_init();
+
+ return 0;
+}
+
+arch_initcall(pcibios_init);
diff --git a/arch/mips/loongson64/loongson-3/platform.c b/arch/mips/loongson64/platform.c
similarity index 100%
rename from arch/mips/loongson64/loongson-3/platform.c
rename to arch/mips/loongson64/platform.c
diff --git a/arch/mips/loongson64/reset.c b/arch/mips/loongson64/reset.c
new file mode 100644
index 000000000000..0bbd2a38c127
--- /dev/null
+++ b/arch/mips/loongson64/reset.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, [email protected]
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Zhangjin Wu, [email protected]
+ */
+#include <linux/init.h>
+#include <linux/pm.h>
+
+#include <asm/idle.h>
+#include <asm/reboot.h>
+
+#include <loongson64.h>
+#include <boot_param.h>
+
+static void loongson_restart(char *command)
+{
+ void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr;
+
+ fw_restart();
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ }
+}
+
+static void loongson_poweroff(void)
+{
+ void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr;
+
+ fw_poweroff();
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ }
+}
+
+static void loongson_halt(void)
+{
+ pr_notice("\n\n** You can safely turn off the power now **\n\n");
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ }
+}
+
+static int __init mips_reboot_setup(void)
+{
+ _machine_restart = loongson_restart;
+ _machine_halt = loongson_halt;
+ pm_power_off = loongson_poweroff;
+
+ return 0;
+}
+
+arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
new file mode 100644
index 000000000000..24432adc8350
--- /dev/null
+++ b/arch/mips/loongson64/setup.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <asm/bootinfo.h>
+#include <linux/memblock.h>
+#include <asm/bootinfo.h>
+#include <asm/prom.h>
+#include <asm/traps.h>
+#include <asm/setup.h>
+#include <asm/smp-ops.h>
+#include <asm/cacheflush.h>
+
+#include <loongson64.h>
+
+static void wbflush_loongson(void)
+{
+ asm(".set\tpush\n\t"
+ ".set\tnoreorder\n\t"
+ ".set mips3\n\t"
+ "sync\n\t"
+ "nop\n\t"
+ ".set\tpop\n\t"
+ ".set mips0\n\t");
+}
+
+void (*__wbflush)(void) = wbflush_loongson;
+EXPORT_SYMBOL(__wbflush);
+
+const char *get_system_type(void)
+{
+ return mips_get_machine_name();
+}
+
+static void __init mips_nmi_setup(void)
+{
+ void *base;
+ extern char except_vec_nmi;
+
+ base = (void *)(CAC_BASE + 0x380);
+ memcpy(base, &except_vec_nmi, 0x80);
+ flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
+}
+
+void __init prom_init_cmdline(void)
+{
+ int prom_argc;
+ /* pmon passes arguments in 32bit pointers */
+ int *_prom_argv;
+ int i;
+ long l;
+
+ /* firmware arguments are initialized in head.S */
+ prom_argc = fw_arg0;
+ _prom_argv = (int *)fw_arg1;
+
+ /* arg[0] is "g", the rest is boot parameters */
+ arcs_cmdline[0] = '\0';
+ for (i = 1; i < prom_argc; i++) {
+ l = (long)_prom_argv[i];
+ if (strlen(arcs_cmdline) + strlen(((char *)l) + 1)
+ >= sizeof(arcs_cmdline))
+ break;
+ strcat(arcs_cmdline, ((char *)l));
+ strcat(arcs_cmdline, " ");
+ }
+}
+
+void __init prom_init(void)
+{
+ prom_init_cmdline();
+ setup_8250_early_printk_port(CKSEG1ADDR(LOONGSON_REG_BASE + 0x1e0), 0, 0);
+
+ prom_init_lefi();
+ prom_init_numa_memory();
+
+ register_smp_ops(&loongson3_smp_ops);
+ board_nmi_handler_setup = mips_nmi_setup;
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+void __init plat_mem_setup(void)
+{
+}
+
+void __init plat_time_init(void)
+{
+#ifdef CONFIG_RS780_HPET
+ setup_hpet_timer();
+#endif
+}
+
diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/smp.c
similarity index 99%
rename from arch/mips/loongson64/loongson-3/smp.c
rename to arch/mips/loongson64/smp.c
index ce68cdaaf33c..8ad845e522fb 100644
--- a/arch/mips/loongson64/loongson-3/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -17,7 +17,7 @@
#include <asm/clock.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
-#include <loongson.h>
+#include <loongson64.h>
#include <workarounds.h>
#include "smp.h"
@@ -252,7 +252,7 @@ void loongson3_send_irq_by_ipi(int cpu, int irqs)
loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]);
}
-void loongson3_ipi_interrupt(struct pt_regs *regs)
+void loongson3_ipi_interrupt()
{
int i, cpu = smp_processor_id();
unsigned int action, c0count, irqs;
diff --git a/arch/mips/loongson64/loongson-3/smp.h b/arch/mips/loongson64/smp.h
similarity index 100%
rename from arch/mips/loongson64/loongson-3/smp.h
rename to arch/mips/loongson64/smp.h
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index b249ec0bebb2..8f739679a5e8 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -13,7 +13,7 @@
#include <linux/oprofile.h>
#include <linux/interrupt.h>
-#include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */
+#include <loongson2ef.h> /* LOONGSON2_PERFCNT_IRQ */
#include "op_impl.h"
#define LOONGSON2_CPU_TYPE "mips/loongson2"
diff --git a/arch/mips/oprofile/op_model_loongson3.c b/arch/mips/oprofile/op_model_loongson3.c
index 436b1fc99f2c..222077e49bc6 100644
--- a/arch/mips/oprofile/op_model_loongson3.c
+++ b/arch/mips/oprofile/op_model_loongson3.c
@@ -13,7 +13,7 @@
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <irq.h>
-#include <loongson.h>
+#include <loongson64.h>
#include "op_impl.h"
#define LOONGSON3_PERFCNT_OVERFLOW (1ULL << 63)
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index d6de4cb2e31c..342ce10ef593 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_LOONGSON_MACH3X) += fixup-loongson3.o ops-loongson3.o
+obj-$(CONFIG_MACH_LOONGSON64) += fixup-loongson3.o ops-loongson3.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o
obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 91aa923234bc..60b6caec02c0 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -10,7 +10,7 @@
#include <linux/init.h>
#include <linux/pci.h>
-#include <loongson.h>
+#include <loongson2ef.h>
/* South bridge slot number is set by the pci probe process */
static u8 sb_slot = 5;
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index 632ff2daa338..f998ca1555a5 100644
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -10,7 +10,7 @@
#include <linux/init.h>
#include <linux/pci.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#include <cs5536/cs5536.h>
#include <cs5536/cs5536_pci.h>
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index 0d1b36ba1c21..f5f479252a3a 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -13,7 +13,7 @@
#include <linux/kernel.h>
#include <linux/export.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#ifdef CONFIG_CS5536
#include <cs5536/cs5536_pci.h>
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
index 2f6ad36bdea6..7f66c8cde773 100644
--- a/arch/mips/pci/ops-loongson3.c
+++ b/arch/mips/pci/ops-loongson3.c
@@ -5,7 +5,7 @@
#include <asm/mips-boards/bonito64.h>
-#include <loongson.h>
+#include <loongson64.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
diff --git a/drivers/cpufreq/loongson2_cpufreq.c b/drivers/cpufreq/loongson2_cpufreq.c
index 890813e0bb76..a3b6f17e6e0a 100644
--- a/drivers/cpufreq/loongson2_cpufreq.c
+++ b/drivers/cpufreq/loongson2_cpufreq.c
@@ -23,7 +23,7 @@
#include <asm/clock.h>
#include <asm/idle.h>
-#include <asm/mach-loongson64/loongson.h>
+#include <asm/mach-loongson2ef/loongson2ef.h>
static uint nowait;
diff --git a/drivers/gpio/gpio-loongson.c b/drivers/gpio/gpio-loongson.c
index a42145873cc9..7b72846a6dc7 100644
--- a/drivers/gpio/gpio-loongson.c
+++ b/drivers/gpio/gpio-loongson.c
@@ -17,7 +17,7 @@
#include <linux/platform_device.h>
#include <linux/bitops.h>
#include <asm/types.h>
-#include <loongson.h>
+#include <loongson2ef.h>
#define STLS2F_N_GPIO 4
#define STLS3A_N_GPIO 16
diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c
index a7f184bb47e0..7b5805b4988c 100644
--- a/drivers/platform/mips/cpu_hwmon.c
+++ b/drivers/platform/mips/cpu_hwmon.c
@@ -6,7 +6,7 @@
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
-#include <loongson.h>
+#include <loongson64.h>
#include <boot_param.h>
#include <loongson_hwmon.h>
--
2.22.0
Export irq_map_generic_chip, irq_unmap_generic_chip so drivers
can use them to construct their own generic chip domain ops.
Signed-off-by: Jiaxun Yang <[email protected]>
---
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index fb301cf29148..3637c24046e1 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -1060,6 +1060,7 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on);
/* Setup functions for irq_chip_generic */
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw_irq);
+void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq);
struct irq_chip_generic *
irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
void __iomem *reg_base, irq_flow_handler_t handler);
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index e2999a070a99..211b15c0d647 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -423,8 +423,9 @@ int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
return 0;
}
+EXPORT_SYMBOL_GPL(irq_map_generic_chip);
-static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
+void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
{
struct irq_data *data = irq_domain_get_irq_data(d, virq);
struct irq_domain_chip_generic *dgc = d->gc;
@@ -443,6 +444,7 @@ static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
NULL);
}
+EXPORT_SYMBOL_GPL(irq_unmap_generic_chip);
struct irq_domain_ops irq_generic_chip_ops = {
.map = irq_map_generic_chip,
--
2.22.0
This controller appeared on Loongson-3 family of chips as the primary
package interrupt source.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ls3-iointc.c | 275 +++++++++++++++++++++++++++++++
3 files changed, 285 insertions(+)
create mode 100644 drivers/irqchip/irq-ls3-iointc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 80e10f4e213a..8d9eac5fd4a7 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -471,6 +471,15 @@ config TI_SCI_INTA_IRQCHIP
If you wish to use interrupt aggregator irq resources managed by the
TI System Controller, say Y here. Otherwise, say N.
+config LS3_IOINTC
+ bool "Loongson3 I/O Interrupt Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson-3 I/O Interrupt Controller.
+
endmenu
config SIFIVE_PLIC
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 8d0fcec6ab23..49ecb8d38138 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -102,3 +102,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
+obj-$(CONFIG_LS3_IOINTC) += irq-ls3-iointc.o
diff --git a/drivers/irqchip/irq-ls3-iointc.c b/drivers/irqchip/irq-ls3-iointc.c
new file mode 100644
index 000000000000..0fbff7afa43c
--- /dev/null
+++ b/drivers/irqchip/irq-ls3-iointc.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Jiaxun Yang <[email protected]>
+ * Loongson-3 IOINTC IRQ support
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/irqchip/chained_irq.h>
+
+
+#define LS3_CHIP_IRQ 32
+
+#define LS3_REG_INTx_MAP(x) (x * 0x1)
+#define LS3_INTC_CHIP_START 0x20
+
+#define LS3_REG_INTC_STATUS (LS3_INTC_CHIP_START + 0x00)
+#define LS3_REG_INTC_EN_STATUS (LS3_INTC_CHIP_START + 0x04)
+#define LS3_REG_INTC_ENABLE (LS3_INTC_CHIP_START + 0x08)
+#define LS3_REG_INTC_DISABLE (LS3_INTC_CHIP_START + 0x0c)
+#define LS3_REG_INTC_POL (LS3_INTC_CHIP_START + 0x10)
+#define LS3_REG_INTC_EDGE (LS3_INTC_CHIP_START + 0x18)
+
+#define LS3_MAP_CORE_INT(x, y) (u8)(BIT(x) | (BIT(y) << 4))
+
+struct ls3_iointc_priv {
+ u8 map_cache[LS3_CHIP_IRQ];
+};
+
+
+static void ls3_io_chained_handle_irq(struct irq_desc *desc)
+{
+ struct irq_chip_generic *gc = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 pending;
+
+ chained_irq_enter(chip, desc);
+
+ /* Check with mask_cache to prevent HW fake interrupt */
+ pending = ~gc->mask_cache &
+ readl(gc->reg_base + LS3_REG_INTC_STATUS);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ generic_handle_irq(irq_find_mapping(gc->domain, bit));
+ pending &= ~BIT(bit);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void ls_intc_set_bit(struct irq_chip_generic *gc,
+ unsigned int offset,
+ u32 mask, bool set)
+{
+ if (set)
+ writel(readl(gc->reg_base + offset) | mask,
+ gc->reg_base + offset);
+ else
+ writel(readl(gc->reg_base + offset) & ~mask,
+ gc->reg_base + offset);
+}
+
+static int ls_intc_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ u32 mask = data->mask;
+ unsigned long flags;
+
+ irq_gc_lock_irqsave(gc, flags);
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, false);
+ ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, false);
+ ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, false);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, true);
+ ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, true);
+ ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, false);
+ break;
+ default:
+ return -EINVAL;
+ }
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ irqd_set_trigger_type(data, type);
+ return 0;
+}
+
+static int ls_intc_set_affinity(struct irq_data *idata,
+ const cpumask_t *cpu_mask, bool force)
+{
+ return -ENAVAIL;
+}
+
+static int ls3_iointc_irq_domain_xlate(struct irq_domain *d,
+ struct device_node *ctrlr,
+ const u32 *intspec, unsigned int intsize,
+ unsigned long *out_hwirq,
+ unsigned int *out_type)
+{
+ struct ls3_iointc_priv *priv = d->host_data;
+ struct irq_chip_generic *gc;
+ int err;
+ unsigned long flags;
+
+ /* Call the generic xlate to process first two cells */
+ err = irq_domain_xlate_onetwocell(d, ctrlr, intspec,
+ intsize, out_hwirq, out_type);
+ if (err)
+ return err;
+ /* If we only have two cells, don't process map information */
+ if (intsize <= 2)
+ return 0;
+ else if (intsize != 4)
+ return -EINVAL; /* Only 4 cells is acceptable */
+
+ /* Third cell is the parent interrupt line, fourth is the Core */
+ if (intspec[3] > 5 || intspec[4] > 3)
+ return -EINVAL; /* Check IP & Core */
+
+ gc = irq_get_domain_generic_chip(d, *out_hwirq);
+ priv->map_cache[*out_hwirq] = LS3_MAP_CORE_INT(intspec[4], intspec[3]);
+
+ irq_gc_lock_irqsave(gc, flags);
+ writeb(priv->map_cache[*out_hwirq],
+ gc->reg_base + LS3_REG_INTx_MAP(*out_hwirq));
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ return 0;
+}
+
+static const struct irq_domain_ops ls3_iointc_irq_domain_ops = {
+ .map = irq_map_generic_chip,
+ .unmap = irq_unmap_generic_chip,
+ .xlate = ls3_iointc_irq_domain_xlate,
+};
+
+static void ls3_iointc_resume(struct irq_chip_generic *gc)
+{
+ struct ls3_iointc_priv *priv = gc->private;
+ unsigned long flags;
+ int i;
+
+ irq_gc_lock_irqsave(gc, flags);
+ /* Revert map cache */
+ for (i = 0; i < LS3_CHIP_IRQ; i++)
+ writeb(priv->map_cache[i],
+ gc->reg_base + LS3_REG_INTx_MAP(i));
+
+ /* Revert mask cache */
+ writel(gc->mask_cache, gc->reg_base + LS3_REG_INTC_DISABLE);
+ writel(~gc->mask_cache, gc->reg_base + LS3_REG_INTC_ENABLE);
+ irq_gc_unlock_irqrestore(gc, flags);
+}
+
+int __init ls3_iointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_domain *domain;
+ struct irq_chip_type *ct;
+ struct ls3_iointc_priv *priv;
+ void __iomem *intc_base;
+ int parent_irq, err = 0;
+ int core = cpu_logical_map(smp_processor_id());
+ int i;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ intc_base = of_iomap(node, 0);
+ if (!intc_base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+
+ parent_irq = irq_of_parse_and_map(node, 0);
+ if (!parent_irq) {
+ pr_err("ls3-iointc: unable to get parent irq\n");
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+ /* Setup IRQ domain */
+ domain = irq_domain_add_linear(node, 32,
+ &ls3_iointc_irq_domain_ops,
+ priv);
+ if (!domain) {
+ pr_err("ls3-iointc: cannot add IRQ domain\n");
+ err = -ENOMEM;
+ goto out_iounmap;
+ }
+
+ err = irq_alloc_domain_generic_chips(domain, 32, 1,
+ node->full_name,
+ handle_level_irq,
+ IRQ_NOPROBE, 0, 0);
+ if (err) {
+ pr_err("ls3-iointc: unable to register IRQ domain\n");
+ err = -ENOMEM;
+ goto out_free_domain;
+ }
+
+ /*
+ * Initialize the map_cache by routing all the interrupts
+ * to interrupt line 0 of the bootcore
+ */
+ pr_info("ls3-iointc: Mapping All ls3-iointc IRQ to core %d, IP 0\n",
+ core);
+ for (i = 0; i < LS3_CHIP_IRQ; i++) {
+ priv->map_cache[i] = LS3_MAP_CORE_INT(core, 0);
+ writeb(priv->map_cache[i],
+ intc_base + LS3_REG_INTx_MAP(i));
+ }
+
+ /* Disable all IRQs */
+ writel(0xffffffff, intc_base + LS3_REG_INTC_DISABLE);
+ /* Set to level triggered */
+ writel(0x0, intc_base + LS3_REG_INTC_EDGE);
+
+ gc = irq_get_domain_generic_chip(domain, 0);
+ gc->private = priv;
+ gc->reg_base = intc_base;
+ gc->domain = domain;
+ gc->resume = ls3_iointc_resume;
+
+ ct = gc->chip_types;
+ ct->regs.enable = LS3_REG_INTC_ENABLE;
+ ct->regs.disable = LS3_REG_INTC_DISABLE;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
+ ct->chip.irq_set_type = ls_intc_set_type;
+ ct->chip.irq_set_affinity = ls_intc_set_affinity;
+
+ /* Initialize mask_cache by read EN_STATUS register */
+ gc->mask_cache = ~readl(intc_base + LS3_REG_INTC_EN_STATUS);
+
+ irq_set_chained_handler_and_data(parent_irq,
+ ls3_io_chained_handle_irq,
+ gc);
+
+ return 0;
+
+out_free_domain:
+ irq_domain_remove(domain);
+out_iounmap:
+ iounmap(intc_base);
+out_free_priv:
+ kfree(priv);
+
+ return err;
+}
+
+IRQCHIP_DECLARE(ls3_iointc, "loongson,ls3-iointc", ls3_iointc_of_init);
--
2.22.0
Document Loongson-3 I/O Interrupt controller.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../loongson,ls3-iointc.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
new file mode 100644
index 000000000000..9aee10abd5cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-iointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt source which can route interrupt to interrupt line of cores.
+
+properties:
+ compatible:
+ const: loongson,ls3-iointc
+
+ reg:
+ maxItems: 1
+
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ description: |
+ Specifies the number of cells needed to encode an interrupt source.
+ Must be 2 or 4.
+ If the system requires describing interrupt line & core mapping, than
+ it must be 4.
+
+ The 1st cell is the hardware interrupt number.
+
+ The 2nd cell is the flags, encoded as follows:
+ bits[3:0] trigger type and level flags.
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive.
+
+ The 3rd is the parent interrupt line that interrupt would map to.
+ As the CPU preserved 4 interrupt lines for I/O, in theory any of the iointc
+ interrupt can be chained to any interrupt lines on a core. But currently
+ we can only map all the interrupt to a single parent, so this cell must be
+ set uniformly for all the child interrupts corresponding to the parent
+ interrupt.
+
+ The 4th is the parent core that interrupt would map to. The interrupt
+ contoller can map any of the interrupt to the specified core on a package.
+ This cell determined the core. It must be the bootcore.
+
+ If the 3rd, 4th cell is not set, it will default to the 0# interrupt line
+ and bootcore.
+
+ enum: [ 2, 4 ]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,ls3-io-intc";
+ reg = <0x3ff01400 0x60>;
+ interrupts = <2>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+...
--
2.22.0
As we sepreated the code of loongson2ef/loongson3a, they can
now have their own entries.
Signed-off-by: Jiaxun Yang <[email protected]>
---
MAINTAINERS | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a2c343ee3b2c..d5d4fed632e6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10747,17 +10747,16 @@ F: arch/mips/include/asm/mach-loongson32/
F: drivers/*/*loongson1*
F: drivers/*/*/*loongson1*
-MIPS/LOONGSON2 ARCHITECTURE
+MIPS/LOONGSON2E/F ARCHITECTURE
M: Jiaxun Yang <[email protected]>
L: [email protected]
S: Maintained
-F: arch/mips/loongson64/fuloong-2e/
-F: arch/mips/loongson64/lemote-2f/
-F: arch/mips/include/asm/mach-loongson64/
+F: arch/mips/loongson2ef/
+F: arch/mips/include/asm/mach-loongson2ef/
F: drivers/*/*loongson2*
F: drivers/*/*/*loongson2*
-MIPS/LOONGSON3 ARCHITECTURE
+MIPS/LOONGSON64 ARCHITECTURE
M: Huacai Chen <[email protected]>
L: [email protected]
S: Maintained
--
2.22.0
On Tue, Aug 27, 2019 at 9:41 PM Paul Burton <[email protected]> wrote:
>
> Hi guys,
>
> On Tue, Aug 27, 2019 at 10:18:46PM +0800, Jiaxun Yang wrote:
> > On 2019/8/27 下午8:45, Rob Herring wrote:
> > > On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <[email protected]> wrote:
> > > > diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> > > > new file mode 100644
> > > > index 000000000000..410d896a0078
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> > > > @@ -0,0 +1,38 @@
> > > > +# SPDX-License-Identifier: GPL-2.0
> > > Dual license for new bindings please:
> > >
> > > (GPL-2.0-only OR BSD-2-Clause)
> > >
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Loongson CPUs bindings
> > > > +
> > > > +maintainers:
> > > > + - Jiaxun Yang <[email protected]>
> > > > +
> > > > +description: |+
> > > > + The device tree allows to describe the layout of CPUs in a system through
> > > > + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > > > + defining properties for every cpu.
> > > > +
> > > > + Bindings for CPU nodes follow the Devicetree Specification, available from:
> > > > +
> > > > + https://www.devicetree.org/specifications/
> > > > +
> > > > +properties:
> > > > + reg:
> > > > + maxItems: 1
> > > > + description: |
> > > > + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum.
> > > Is this definition specific to Loongson CPUs or all MIPS?
> >
> > Currently it's specific to Loongson CPU only, as other processors may using
> > different method to express CPU map.
> >
> > Different from Arm, MIPS family of processors seems less uniform and have
> > their own designs.
> >
> > For this point, we'd better ask Paul's opinion.
>
> In general on MIPS we detect CPU properties at runtime from coprocessor
> 0 registers & similar sources of information, so there's not really a
> need to specify anything about the CPU in devicetree.
We thought the same thing initially for Arm... Mostly what is in DT is
not what is discoverable. Are clock speeds, power domains, low power
states, etc. all discoverable?
> For example here
> you say yourself that the value for this property can be read from
> EBase.CPUNum - so why specify it in DT?
To map DT nodes to cores?
Rob
On Wed, Aug 28, 2019 at 08:37:34AM +0800, Jiaxun Yang wrote:
> On 2019/8/28 上午6:05, Aaro Koskinen wrote:
> Hi Aaro,
> >You need to update lemote2f_defconfig with his patch.
>
> How to generate this config? We should not edit it manually right?
It's possible to edit changed symbols by hand. Minimal defconfigs are
generated with "make savedefconfig".
A.
Hi Rob,
On Mon, Sep 02, 2019 at 03:50:47PM +0100, Rob Herring wrote:
> > In general on MIPS we detect CPU properties at runtime from coprocessor
> > 0 registers & similar sources of information, so there's not really a
> > need to specify anything about the CPU in devicetree.
>
> We thought the same thing initially for Arm... Mostly what is in DT is
> not what is discoverable. Are clock speeds, power domains, low power
> states, etc. all discoverable?
No, that's a good point - clocks etc may need to be specified in DT. I
just don't see any of that in this patchset - it appears all that is
specified is cache sizes which we already detect. So in this case I
don't see a need for including CPUs in DT at all.
Jiaxun - did you add all this information to DT to avoid the "cacheinfo:
Unable to detect cache hierarchy for CPU" messages during boot? If so
that should be fixed by commit b8bea8a5e5d9 ("mips: fix cacheinfo"). If
not, could you describe why the CPU nodes are needed here?
Thanks,
Paul
On Tue, Sep 3, 2019 at 5:08 PM Paul Burton <[email protected]> wrote:
>
> Hi Rob,
>
> On Mon, Sep 02, 2019 at 03:50:47PM +0100, Rob Herring wrote:
> > > In general on MIPS we detect CPU properties at runtime from coprocessor
> > > 0 registers & similar sources of information, so there's not really a
> > > need to specify anything about the CPU in devicetree.
> >
> > We thought the same thing initially for Arm... Mostly what is in DT is
> > not what is discoverable. Are clock speeds, power domains, low power
> > states, etc. all discoverable?
>
> No, that's a good point - clocks etc may need to be specified in DT. I
> just don't see any of that in this patchset - it appears all that is
> specified is cache sizes which we already detect. So in this case I
> don't see a need for including CPUs in DT at all.
>
> Jiaxun - did you add all this information to DT to avoid the "cacheinfo:
> Unable to detect cache hierarchy for CPU" messages during boot? If so
> that should be fixed by commit b8bea8a5e5d9 ("mips: fix cacheinfo"). If
> not, could you describe why the CPU nodes are needed here?
Yes, this can avoid "cacheinfo: Unable to detect cache hierarchy for CPU".
In our own git repository we have already reverted commit b8bea8a5e5d9
("mips: fix cacheinfo")
Huacai
>
> Thanks,
> Paul
v1:
- dt-bindings fixup according to Rob's comments
- irqchip fixup according to Marc's comments
- ls3-iointc: Make Core&IP map per-IRQ
- Regenerate kconfigs
- Typo & style improvements
v2:
- dt-bindings: Fix IOINTC, collect Rob's review tag
- dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
Jiaxun Yang (19):
MIPS: Loongson64: Rename CPU TYPES
MIPS: Loongson64: separate loongson2ef/loongson64 code
MAINTAINERS: Fix entries for new loongson64 path
irqchip: Export generic chip domain map/unmap functions
irqchip: Add driver for Loongson-3 I/O interrupt controller
dt-bindings: interrupt-controller: Add Loongson-3 IOINTC
irqchip: Add driver for Loongson-3 HyperTransport interrupt controller
dt-bindings: interrupt-controller: Add Loongson-3 HTINTC
irqchip: i8259: Add plat-poll support
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson boards
dt-bindings: Document loongson vendor-prefix
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
GPIO: loongson: Drop Loongson-3A/3B support
MIPS: Loongson: Regenerate defconfigs
MAINTAINERS: Add new pathes to LOONGSON64 ARCHITECTURE
MAINTAINERS: Add myself as maintainer of LOONGSON64
.../loongson,ls3-htintc.yaml | 55 ++++
.../loongson,ls3-iointc.yaml | 79 +++++
.../bindings/mips/loongson/devices.yaml | 39 +++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 13 +-
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 83 ++++--
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/3a-package.dtsi | 69 +++++
arch/mips/boot/dts/loongson/3a1000_780e.dts | 10 +
arch/mips/boot/dts/loongson/3a2000_780e.dts | 10 +
arch/mips/boot/dts/loongson/3a3000_780e.dts | 10 +
arch/mips/boot/dts/loongson/3b-package.dtsi | 69 +++++
arch/mips/boot/dts/loongson/3b1x00_780e.dts | 10 +
arch/mips/boot/dts/loongson/Makefile | 5 +
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 35 +++
arch/mips/configs/fuloong2e_defconfig | 8 +-
arch/mips/configs/lemote2f_defconfig | 8 +-
arch/mips/configs/loongson3_defconfig | 13 +-
arch/mips/include/asm/bootinfo.h | 1 -
arch/mips/include/asm/cop2.h | 2 +-
arch/mips/include/asm/cpu-type.h | 6 +-
arch/mips/include/asm/cpu.h | 4 +-
arch/mips/include/asm/hazards.h | 2 +-
arch/mips/include/asm/io.h | 2 +-
arch/mips/include/asm/irqflags.h | 2 +-
.../mach-loongson2ef/cpu-feature-overrides.h | 45 +++
.../cs5536/cs5536.h | 0
.../cs5536/cs5536_mfgpt.h | 0
.../cs5536/cs5536_pci.h | 0
.../cs5536/cs5536_vsm.h | 0
.../loongson2ef.h} | 31 +-
.../machine.h | 6 -
.../mc146818rtc.h | 5 +-
.../mem.h | 6 +-
arch/mips/include/asm/mach-loongson2ef/pci.h | 43 +++
.../include/asm/mach-loongson2ef/spaces.h | 10 +
.../asm/mach-loongson64/builtin_dtbs.h | 16 +
.../mach-loongson64/cpu-feature-overrides.h | 8 +-
arch/mips/include/asm/mach-loongson64/irq.h | 6 +-
.../asm/mach-loongson64/kernel-entry-init.h | 74 -----
.../include/asm/mach-loongson64/loongson64.h | 50 ++++
.../mips/include/asm/mach-loongson64/mmzone.h | 16 -
arch/mips/include/asm/mach-loongson64/pci.h | 41 +--
.../include/asm/mach-loongson64/workarounds.h | 4 +-
arch/mips/include/asm/module.h | 8 +-
arch/mips/include/asm/processor.h | 2 +-
arch/mips/include/asm/r4kcache.h | 4 +-
arch/mips/kernel/cpu-probe.c | 14 +-
arch/mips/kernel/idle.c | 2 +-
arch/mips/kernel/perf_event_mipsxx.c | 4 +-
arch/mips/kernel/setup.c | 2 +-
arch/mips/kernel/traps.c | 2 +-
arch/mips/lib/csum_partial.S | 4 +-
arch/mips/loongson2ef/Kconfig | 93 ++++++
arch/mips/loongson2ef/Makefile | 18 ++
arch/mips/loongson2ef/Platform | 32 ++
.../common/Makefile | 0
.../common/bonito-irq.c | 2 +-
.../common/cmdline.c | 2 +-
.../common/cs5536/Makefile | 0
.../common/cs5536/cs5536_acc.c | 0
.../common/cs5536/cs5536_ehci.c | 0
.../common/cs5536/cs5536_ide.c | 0
.../common/cs5536/cs5536_isa.c | 0
.../common/cs5536/cs5536_mfgpt.c | 0
.../common/cs5536/cs5536_ohci.c | 0
.../common/cs5536/cs5536_pci.c | 0
.../common/early_printk.c | 2 +-
arch/mips/loongson2ef/common/env.c | 71 +++++
.../{loongson64 => loongson2ef}/common/init.c | 7 +-
.../{loongson64 => loongson2ef}/common/irq.c | 2 +-
.../common/machtype.c | 3 +-
.../{loongson64 => loongson2ef}/common/mem.c | 40 +--
.../{loongson64 => loongson2ef}/common/pci.c | 11 +-
.../common/platform.c | 0
.../{loongson64 => loongson2ef}/common/pm.c | 2 +-
.../common/reset.c | 23 +-
.../{loongson64 => loongson2ef}/common/rtc.c | 0
.../common/serial.c | 37 +--
.../common/setup.c | 2 +-
.../{loongson64 => loongson2ef}/common/time.c | 2 +-
.../common/uart_base.c | 10 +-
.../fuloong-2e/Makefile | 0
.../fuloong-2e/dma.c | 0
.../fuloong-2e/irq.c | 2 +-
.../fuloong-2e/reset.c | 2 +-
.../lemote-2f/Makefile | 0
.../lemote-2f/clock.c | 2 +-
.../lemote-2f/dma.c | 0
.../lemote-2f/ec_kb3310b.c | 0
.../lemote-2f/ec_kb3310b.h | 0
.../lemote-2f/irq.c | 2 +-
.../lemote-2f/machtype.c | 2 +-
.../lemote-2f/pm.c | 2 +-
.../lemote-2f/reset.c | 2 +-
arch/mips/loongson64/Kconfig | 126 +-------
arch/mips/loongson64/Makefile | 23 +-
arch/mips/loongson64/Platform | 36 +--
.../loongson64/{loongson-3 => }/acpi_init.c | 3 +-
.../loongson64/{loongson-3 => }/cop2-ex.c | 5 +-
arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +-
arch/mips/loongson64/{common => }/env.c | 98 +++----
arch/mips/loongson64/{loongson-3 => }/hpet.c | 0
arch/mips/loongson64/irq.c | 27 ++
arch/mips/loongson64/loongson-3/Makefile | 11 -
arch/mips/loongson64/loongson-3/irq.c | 158 ----------
arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +-
arch/mips/loongson64/pci.c | 45 +++
.../loongson64/{loongson-3 => }/platform.c | 0
arch/mips/loongson64/reset.c | 58 ++++
arch/mips/loongson64/setup.c | 107 +++++++
arch/mips/loongson64/{loongson-3 => }/smp.c | 28 +-
arch/mips/loongson64/{loongson-3 => }/smp.h | 0
arch/mips/mm/c-r4k.c | 32 +-
arch/mips/mm/page.c | 2 +-
arch/mips/mm/tlb-r4k.c | 4 +-
arch/mips/mm/tlbex.c | 6 +-
arch/mips/oprofile/Makefile | 4 +-
arch/mips/oprofile/common.c | 4 +-
arch/mips/oprofile/op_model_loongson2.c | 2 +-
arch/mips/oprofile/op_model_loongson3.c | 2 +-
arch/mips/pci/Makefile | 2 +-
arch/mips/pci/fixup-fuloong2e.c | 2 +-
arch/mips/pci/fixup-lemote2f.c | 2 +-
arch/mips/pci/ops-loongson2.c | 2 +-
arch/mips/pci/ops-loongson3.c | 2 +-
drivers/cpufreq/loongson2_cpufreq.c | 2 +-
drivers/gpio/Kconfig | 6 +-
drivers/gpio/gpio-loongson.c | 11 +-
drivers/irqchip/Kconfig | 17 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-i8259.c | 47 ++-
drivers/irqchip/irq-ls3-htintc.c | 147 ++++++++++
drivers/irqchip/irq-ls3-iointc.c | 275 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
drivers/platform/mips/cpu_hwmon.c | 2 +-
include/drm/drm_cache.h | 2 +-
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 4 +-
140 files changed, 1760 insertions(+), 874 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/3a-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/3a1000_780e.dts
create mode 100644 arch/mips/boot/dts/loongson/3a2000_780e.dts
create mode 100644 arch/mips/boot/dts/loongson/3a3000_780e.dts
create mode 100644 arch/mips/boot/dts/loongson/3b-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/3b1x00_780e.dts
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%)
rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%)
rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%)
create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h
create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h
create mode 100644 arch/mips/loongson2ef/Kconfig
create mode 100644 arch/mips/loongson2ef/Makefile
create mode 100644 arch/mips/loongson2ef/Platform
rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%)
create mode 100644 arch/mips/loongson2ef/common/env.c
rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%)
rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%)
rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%)
rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%)
rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%)
rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%)
rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%)
rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%)
rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%)
rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%)
rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%)
rename arch/mips/loongson64/{common => }/env.c (83%)
rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%)
create mode 100644 arch/mips/loongson64/irq.c
delete mode 100644 arch/mips/loongson64/loongson-3/Makefile
delete mode 100644 arch/mips/loongson64/loongson-3/irq.c
rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%)
create mode 100644 arch/mips/loongson64/pci.c
rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%)
create mode 100644 arch/mips/loongson64/reset.c
create mode 100644 arch/mips/loongson64/setup.c
rename arch/mips/loongson64/{loongson-3 => }/smp.c (98%)
rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%)
create mode 100644 drivers/irqchip/irq-ls3-htintc.c
create mode 100644 drivers/irqchip/irq-ls3-iointc.c
--
2.22.0
As we sepreated the code of loongson2ef/loongson3a, they can
now have their own entries.
Signed-off-by: Jiaxun Yang <[email protected]>
---
MAINTAINERS | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..b2ad16902d70 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10742,17 +10742,16 @@ F: arch/mips/include/asm/mach-loongson32/
F: drivers/*/*loongson1*
F: drivers/*/*/*loongson1*
-MIPS/LOONGSON2 ARCHITECTURE
+MIPS/LOONGSON2E/F ARCHITECTURE
M: Jiaxun Yang <[email protected]>
L: [email protected]
S: Maintained
-F: arch/mips/loongson64/fuloong-2e/
-F: arch/mips/loongson64/lemote-2f/
-F: arch/mips/include/asm/mach-loongson64/
+F: arch/mips/loongson2ef/
+F: arch/mips/include/asm/mach-loongson2ef/
F: drivers/*/*loongson2*
F: drivers/*/*/*loongson2*
-MIPS/LOONGSON3 ARCHITECTURE
+MIPS/LOONGSON64 ARCHITECTURE
M: Huacai Chen <[email protected]>
L: [email protected]
S: Maintained
--
2.22.0
This controller appeared on Loongson-3 family of chips as the primary
package interrupt source.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ls3-iointc.c | 275 +++++++++++++++++++++++++++++++
3 files changed, 285 insertions(+)
create mode 100644 drivers/irqchip/irq-ls3-iointc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index ccbb8973a324..4acf38a20a2c 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -483,6 +483,15 @@ config TI_SCI_INTA_IRQCHIP
If you wish to use interrupt aggregator irq resources managed by the
TI System Controller, say Y here. Otherwise, say N.
+config LS3_IOINTC
+ bool "Loongson3 I/O Interrupt Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson-3 I/O Interrupt Controller.
+
endmenu
config SIFIVE_PLIC
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cc7c43932f16..18ba8f203afd 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -103,3 +103,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
+obj-$(CONFIG_LS3_IOINTC) += irq-ls3-iointc.o
diff --git a/drivers/irqchip/irq-ls3-iointc.c b/drivers/irqchip/irq-ls3-iointc.c
new file mode 100644
index 000000000000..0fbff7afa43c
--- /dev/null
+++ b/drivers/irqchip/irq-ls3-iointc.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Jiaxun Yang <[email protected]>
+ * Loongson-3 IOINTC IRQ support
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/irqchip/chained_irq.h>
+
+
+#define LS3_CHIP_IRQ 32
+
+#define LS3_REG_INTx_MAP(x) (x * 0x1)
+#define LS3_INTC_CHIP_START 0x20
+
+#define LS3_REG_INTC_STATUS (LS3_INTC_CHIP_START + 0x00)
+#define LS3_REG_INTC_EN_STATUS (LS3_INTC_CHIP_START + 0x04)
+#define LS3_REG_INTC_ENABLE (LS3_INTC_CHIP_START + 0x08)
+#define LS3_REG_INTC_DISABLE (LS3_INTC_CHIP_START + 0x0c)
+#define LS3_REG_INTC_POL (LS3_INTC_CHIP_START + 0x10)
+#define LS3_REG_INTC_EDGE (LS3_INTC_CHIP_START + 0x18)
+
+#define LS3_MAP_CORE_INT(x, y) (u8)(BIT(x) | (BIT(y) << 4))
+
+struct ls3_iointc_priv {
+ u8 map_cache[LS3_CHIP_IRQ];
+};
+
+
+static void ls3_io_chained_handle_irq(struct irq_desc *desc)
+{
+ struct irq_chip_generic *gc = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ u32 pending;
+
+ chained_irq_enter(chip, desc);
+
+ /* Check with mask_cache to prevent HW fake interrupt */
+ pending = ~gc->mask_cache &
+ readl(gc->reg_base + LS3_REG_INTC_STATUS);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ generic_handle_irq(irq_find_mapping(gc->domain, bit));
+ pending &= ~BIT(bit);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void ls_intc_set_bit(struct irq_chip_generic *gc,
+ unsigned int offset,
+ u32 mask, bool set)
+{
+ if (set)
+ writel(readl(gc->reg_base + offset) | mask,
+ gc->reg_base + offset);
+ else
+ writel(readl(gc->reg_base + offset) & ~mask,
+ gc->reg_base + offset);
+}
+
+static int ls_intc_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ u32 mask = data->mask;
+ unsigned long flags;
+
+ irq_gc_lock_irqsave(gc, flags);
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, false);
+ ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, false);
+ ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, false);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, true);
+ ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ ls_intc_set_bit(gc, LS3_REG_INTC_EDGE, mask, true);
+ ls_intc_set_bit(gc, LS3_REG_INTC_POL, mask, false);
+ break;
+ default:
+ return -EINVAL;
+ }
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ irqd_set_trigger_type(data, type);
+ return 0;
+}
+
+static int ls_intc_set_affinity(struct irq_data *idata,
+ const cpumask_t *cpu_mask, bool force)
+{
+ return -ENAVAIL;
+}
+
+static int ls3_iointc_irq_domain_xlate(struct irq_domain *d,
+ struct device_node *ctrlr,
+ const u32 *intspec, unsigned int intsize,
+ unsigned long *out_hwirq,
+ unsigned int *out_type)
+{
+ struct ls3_iointc_priv *priv = d->host_data;
+ struct irq_chip_generic *gc;
+ int err;
+ unsigned long flags;
+
+ /* Call the generic xlate to process first two cells */
+ err = irq_domain_xlate_onetwocell(d, ctrlr, intspec,
+ intsize, out_hwirq, out_type);
+ if (err)
+ return err;
+ /* If we only have two cells, don't process map information */
+ if (intsize <= 2)
+ return 0;
+ else if (intsize != 4)
+ return -EINVAL; /* Only 4 cells is acceptable */
+
+ /* Third cell is the parent interrupt line, fourth is the Core */
+ if (intspec[3] > 5 || intspec[4] > 3)
+ return -EINVAL; /* Check IP & Core */
+
+ gc = irq_get_domain_generic_chip(d, *out_hwirq);
+ priv->map_cache[*out_hwirq] = LS3_MAP_CORE_INT(intspec[4], intspec[3]);
+
+ irq_gc_lock_irqsave(gc, flags);
+ writeb(priv->map_cache[*out_hwirq],
+ gc->reg_base + LS3_REG_INTx_MAP(*out_hwirq));
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ return 0;
+}
+
+static const struct irq_domain_ops ls3_iointc_irq_domain_ops = {
+ .map = irq_map_generic_chip,
+ .unmap = irq_unmap_generic_chip,
+ .xlate = ls3_iointc_irq_domain_xlate,
+};
+
+static void ls3_iointc_resume(struct irq_chip_generic *gc)
+{
+ struct ls3_iointc_priv *priv = gc->private;
+ unsigned long flags;
+ int i;
+
+ irq_gc_lock_irqsave(gc, flags);
+ /* Revert map cache */
+ for (i = 0; i < LS3_CHIP_IRQ; i++)
+ writeb(priv->map_cache[i],
+ gc->reg_base + LS3_REG_INTx_MAP(i));
+
+ /* Revert mask cache */
+ writel(gc->mask_cache, gc->reg_base + LS3_REG_INTC_DISABLE);
+ writel(~gc->mask_cache, gc->reg_base + LS3_REG_INTC_ENABLE);
+ irq_gc_unlock_irqrestore(gc, flags);
+}
+
+int __init ls3_iointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_domain *domain;
+ struct irq_chip_type *ct;
+ struct ls3_iointc_priv *priv;
+ void __iomem *intc_base;
+ int parent_irq, err = 0;
+ int core = cpu_logical_map(smp_processor_id());
+ int i;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ intc_base = of_iomap(node, 0);
+ if (!intc_base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+
+ parent_irq = irq_of_parse_and_map(node, 0);
+ if (!parent_irq) {
+ pr_err("ls3-iointc: unable to get parent irq\n");
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+ /* Setup IRQ domain */
+ domain = irq_domain_add_linear(node, 32,
+ &ls3_iointc_irq_domain_ops,
+ priv);
+ if (!domain) {
+ pr_err("ls3-iointc: cannot add IRQ domain\n");
+ err = -ENOMEM;
+ goto out_iounmap;
+ }
+
+ err = irq_alloc_domain_generic_chips(domain, 32, 1,
+ node->full_name,
+ handle_level_irq,
+ IRQ_NOPROBE, 0, 0);
+ if (err) {
+ pr_err("ls3-iointc: unable to register IRQ domain\n");
+ err = -ENOMEM;
+ goto out_free_domain;
+ }
+
+ /*
+ * Initialize the map_cache by routing all the interrupts
+ * to interrupt line 0 of the bootcore
+ */
+ pr_info("ls3-iointc: Mapping All ls3-iointc IRQ to core %d, IP 0\n",
+ core);
+ for (i = 0; i < LS3_CHIP_IRQ; i++) {
+ priv->map_cache[i] = LS3_MAP_CORE_INT(core, 0);
+ writeb(priv->map_cache[i],
+ intc_base + LS3_REG_INTx_MAP(i));
+ }
+
+ /* Disable all IRQs */
+ writel(0xffffffff, intc_base + LS3_REG_INTC_DISABLE);
+ /* Set to level triggered */
+ writel(0x0, intc_base + LS3_REG_INTC_EDGE);
+
+ gc = irq_get_domain_generic_chip(domain, 0);
+ gc->private = priv;
+ gc->reg_base = intc_base;
+ gc->domain = domain;
+ gc->resume = ls3_iointc_resume;
+
+ ct = gc->chip_types;
+ ct->regs.enable = LS3_REG_INTC_ENABLE;
+ ct->regs.disable = LS3_REG_INTC_DISABLE;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
+ ct->chip.irq_set_type = ls_intc_set_type;
+ ct->chip.irq_set_affinity = ls_intc_set_affinity;
+
+ /* Initialize mask_cache by read EN_STATUS register */
+ gc->mask_cache = ~readl(intc_base + LS3_REG_INTC_EN_STATUS);
+
+ irq_set_chained_handler_and_data(parent_irq,
+ ls3_io_chained_handle_irq,
+ gc);
+
+ return 0;
+
+out_free_domain:
+ irq_domain_remove(domain);
+out_iounmap:
+ iounmap(intc_base);
+out_free_priv:
+ kfree(priv);
+
+ return err;
+}
+
+IRQCHIP_DECLARE(ls3_iointc, "loongson,ls3-iointc", ls3_iointc_of_init);
--
2.22.0
Document Loongson-3 I/O Interrupt controller.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../loongson,ls3-iointc.yaml | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
new file mode 100644
index 000000000000..c6e58c83181e
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-iointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt source which can route interrupt to interrupt line of cores.
+
+properties:
+ compatible:
+ const: loongson,ls3-iointc
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ description: |
+ Specifies the number of cells needed to encode an interrupt source.
+ Must be 2 or 4.
+ If the system requires describing interrupt line & core mapping, than
+ it must be 4.
+
+ The 1st cell is the hardware interrupt number.
+
+ The 2nd cell is the flags, encoded as follows:
+ bits[3:0] trigger type and level flags.
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive.
+
+ The 3rd is the parent interrupt line that interrupt would map to.
+ As the CPU preserved 4 interrupt lines for I/O, in theory any of the iointc
+ interrupt can be chained to any interrupt lines on a core. But currently
+ we can only map all the interrupt to a single parent, so this cell must be
+ set uniformly for all the child interrupts corresponding to the parent
+ interrupt.
+
+ The 4th is the parent core that interrupt would map to. The interrupt
+ contoller can map any of the interrupt to the specified core on a package.
+ This cell determined the core. It must be the bootcore.
+
+ If the 3rd, 4th cell is not set, it will default to the 0# interrupt line
+ and bootcore.
+
+ enum: [ 2, 4 ]
+
+ interrupts:
+ description:
+ Interrupt source of the CPU interrupt.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,ls3-io-intc";
+ reg = <0x3ff01400 0x60>;
+ interrupts = <2>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+...
--
2.22.0
For some platforms (e.g. Loongson-3), platfrom interrupt controller
supports polling interrupt vector from i8259 automaticly and generating
sepreated interrupt.
Thus we add plat-poll OF property for these platforms and setup sepreated
chained interrupt handler.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-i8259.c | 47 ++++++++++++++++++++++++++++++++-----
1 file changed, 41 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index d000870d9b6b..e7a9895f3b2d 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -40,6 +40,12 @@ static void mask_and_ack_8259A(struct irq_data *d);
static void init_8259A(int auto_eoi);
static int (*i8259_poll)(void) = i8259_irq;
+struct plat_poll_priv {
+ struct irq_domain *domain;
+ int hwirq;
+};
+static struct plat_poll_priv plat_poll_priv[16];
+
static struct irq_chip i8259A_chip = {
.name = "XT-PIC",
.irq_mask = disable_8259A_irq,
@@ -346,22 +352,51 @@ static void i8259_irq_dispatch(struct irq_desc *desc)
generic_handle_irq(irq);
}
+static void plat_poll_irq_dispatch(struct irq_desc *desc)
+{
+ struct plat_poll_priv *priv = irq_desc_get_handler_data(desc);
+ unsigned int irq;
+
+ irq = irq_linear_revmap(priv->domain, priv->hwirq);
+ generic_handle_irq(irq);
+}
+
int __init i8259_of_init(struct device_node *node, struct device_node *parent)
{
struct irq_domain *domain;
- unsigned int parent_irq;
domain = __init_i8259_irqs(node);
- parent_irq = irq_of_parse_and_map(node, 0);
- if (!parent_irq) {
- pr_err("Failed to map i8259 parent IRQ\n");
- irq_domain_remove(domain);
- return -ENODEV;
+ if (of_find_property(node, "plat-poll", NULL)) {
+ int i;
+
+ for (i = 0; i < 16; i++) {
+ int parent_irq = irq_of_parse_and_map(node, i);
+
+ if (!parent_irq) {
+ pr_err("Failed to map %d plat-poll i8259 parent IRQ\n", i);
+ irq_domain_remove(domain);
+ return -ENODEV;
+ }
+ plat_poll_priv[i].domain = domain;
+ plat_poll_priv[i].hwirq = i;
+ irq_set_chained_handler_and_data(parent_irq,
+ plat_poll_irq_dispatch,
+ &plat_poll_priv[i]);
+ }
+ } else {
+ unsigned int parent_irq;
+
+ parent_irq = irq_of_parse_and_map(node, 0);
+ if (!parent_irq) {
+ pr_err("Failed to map i8259 parent IRQ\n");
+ irq_domain_remove(domain);
+ return -ENODEV;
}
irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch,
domain);
+ }
return 0;
}
IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init);
--
2.22.0
The old code is using legacy domain to setup irq_domain for CPU interrupts
which requires irq_desc being preallocated.
However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up
unallocated and lead to incorrect behavior.
Thus we convert the legacy domain to simple domain which can allocate irq_desc
during initialization.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..c3cf7fa76424 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+ irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
&mips_cpu_intc_irq_domain_ops,
NULL);
if (!irq_domain)
--
2.22.0
Document Loongson-3 HyperTransport Interrupt controller.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../loongson,ls3-htintc.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
new file mode 100644
index 000000000000..51fee46ab060
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-htintc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 HyperTransport Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips to transfer
+ interrupts from PCH connected on HyperTransport bus.
+
+properties:
+ compatible:
+ const: loongson,ls3-htintc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 4
+ description: |
+ Four parent interrupts that recieve chained interrupt randomly.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ htintc: interrupt-controller@fb000080 {
+ compatible = "loongson,ls3-htintc";
+ reg = <0xfb000080 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&iointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.22.0
Loongson is a MIPS-compatible processor vendor.
Signed-off-by: Jiaxun Yang <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6992bbbbffab..855d5b7a6660 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -529,6 +529,8 @@ patternProperties:
description: Linear Technology Corporation
"^logicpd,.*":
description: Logic PD, Inc.
+ "^loongson,.*":
+ description: Loongson Technology Corporation Limited
"^lsi,.*":
description: LSI Corp. (LSI Logic)
"^lwn,.*":
--
2.22.0
CPU_LOONGSON2 -> CPU_LOONGSON2EF
CPU_LOONGSON3 -> CPU_LOONGSON64
As newer loongson-2 products (2G/2H/2K1000) can share kernel
implementation with loongson-3 while 2E/2F are less similar with
other LOONGSON64 products.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 28 ++++++++--------
arch/mips/include/asm/cop2.h | 2 +-
arch/mips/include/asm/cpu-type.h | 6 ++--
arch/mips/include/asm/cpu.h | 4 +--
arch/mips/include/asm/hazards.h | 2 +-
arch/mips/include/asm/io.h | 2 +-
arch/mips/include/asm/irqflags.h | 2 +-
.../mach-loongson64/cpu-feature-overrides.h | 2 +-
arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
.../asm/mach-loongson64/kernel-entry-init.h | 4 +--
.../include/asm/mach-loongson64/loongson.h | 2 +-
arch/mips/include/asm/mach-loongson64/pci.h | 2 +-
arch/mips/include/asm/module.h | 8 ++---
arch/mips/include/asm/processor.h | 2 +-
arch/mips/include/asm/r4kcache.h | 4 +--
arch/mips/kernel/cpu-probe.c | 14 ++++----
arch/mips/kernel/idle.c | 2 +-
arch/mips/kernel/perf_event_mipsxx.c | 4 +--
arch/mips/kernel/setup.c | 2 +-
arch/mips/kernel/traps.c | 2 +-
arch/mips/lib/csum_partial.S | 4 +--
arch/mips/loongson64/Kconfig | 2 +-
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/Platform | 12 +++----
arch/mips/loongson64/common/pci.c | 2 +-
arch/mips/mm/c-r4k.c | 32 +++++++++----------
arch/mips/mm/page.c | 2 +-
arch/mips/mm/tlb-r4k.c | 4 +--
arch/mips/mm/tlbex.c | 6 ++--
arch/mips/oprofile/Makefile | 4 +--
arch/mips/oprofile/common.c | 4 +--
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-loongson.c | 2 +-
include/drm/drm_cache.h | 2 +-
34 files changed, 88 insertions(+), 88 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3f18aa018a0c..42fe63599dc7 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1371,9 +1371,9 @@ choice
prompt "CPU type"
default CPU_R4X00
-config CPU_LOONGSON3
- bool "Loongson 3 CPU"
- depends on SYS_HAS_CPU_LOONGSON3
+config CPU_LOONGSON64
+ bool "Loongson GSx64 Family CPU"
+ depends on SYS_HAS_CPU_LOONGSON64
select ARCH_HAS_PHYS_TO_DMA
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1386,15 +1386,15 @@ config CPU_LOONGSON3
select GPIOLIB
select SWIOTLB
help
- The Loongson 3 processor implements the MIPS64R2 instruction
- set with many extensions.
+ The Loongson GSx64 Family cores including Loongson-3A/3B/2series-soc
+ implements the MIPS64R2 instruction set with many extensions.
config LOONGSON3_ENHANCEMENT
bool "New Loongson 3 CPU Enhancements"
default n
select CPU_MIPSR2
select CPU_HAS_PREFETCH
- depends on CPU_LOONGSON3
+ depends on CPU_LOONGSON64
help
New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
@@ -1410,7 +1410,7 @@ config LOONGSON3_ENHANCEMENT
config CPU_LOONGSON3_WORKAROUNDS
bool "Old Loongson 3 LLSC Workarounds"
default y if SMP
- depends on CPU_LOONGSON3
+ depends on CPU_LOONGSON64
help
Loongson 3 processors have the llsc issues which require workarounds.
Without workarounds the system may hang unexpectedly.
@@ -1425,7 +1425,7 @@ config CPU_LOONGSON3_WORKAROUNDS
config CPU_LOONGSON2E
bool "Loongson 2E"
depends on SYS_HAS_CPU_LOONGSON2E
- select CPU_LOONGSON2
+ select CPU_LOONGSON2EF
help
The Loongson 2E processor implements the MIPS III instruction set
with many extensions.
@@ -1436,7 +1436,7 @@ config CPU_LOONGSON2E
config CPU_LOONGSON2F
bool "Loongson 2F"
depends on SYS_HAS_CPU_LOONGSON2F
- select CPU_LOONGSON2
+ select CPU_LOONGSON2EF
select GPIOLIB
help
The Loongson 2F processor implements the MIPS III instruction set
@@ -1849,7 +1849,7 @@ config SYS_SUPPORTS_ZBOOT_UART_PROM
bool
select SYS_SUPPORTS_ZBOOT
-config CPU_LOONGSON2
+config CPU_LOONGSON2EF
bool
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
@@ -1892,7 +1892,7 @@ config CPU_BMIPS5000
select SYS_SUPPORTS_HOTPLUG_CPU
select CPU_HAS_RIXI
-config SYS_HAS_CPU_LOONGSON3
+config SYS_HAS_CPU_LOONGSON64
bool
select CPU_SUPPORTS_CPUFREQ
select CPU_HAS_RIXI
@@ -2154,7 +2154,7 @@ choice
config PAGE_SIZE_4KB
bool "4kB"
- depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
+ depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
help
This option select the standard 4kB Linux page size. On some
R3000-family processors this is the only available page size. Using
@@ -2604,7 +2604,7 @@ config CPU_SUPPORTS_MSA
config ARCH_FLATMEM_ENABLE
def_bool y
- depends on !NUMA && !CPU_LOONGSON2
+ depends on !NUMA && !CPU_LOONGSON2EF
config ARCH_DISCONTIGMEM_ENABLE
bool
@@ -2694,7 +2694,7 @@ config NODES_SHIFT
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
- depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
+ depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
default y
help
Enable hardware performance counter support for perf events. If
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 63b3468ede4c..6b7396a6a115 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -33,7 +33,7 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);
#define cop2_present 1
#define cop2_lazy_restore 0
-#elif defined(CONFIG_CPU_LOONGSON3)
+#elif defined(CONFIG_CPU_LOONGSON64)
#define cop2_present 1
#define cop2_lazy_restore 1
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 7bbb66760a07..94d8c3653802 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -17,11 +17,11 @@ static inline int __pure __get_cpu_type(const int cpu_type)
switch (cpu_type) {
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
#endif
-#ifdef CONFIG_SYS_HAS_CPU_LOONGSON3
- case CPU_LOONGSON3:
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON64
+ case CPU_LOONGSON64:
#endif
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 7fddcb8350c6..afa1fec585c9 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -317,8 +317,8 @@ enum cpu_type_enum {
/*
* MIPS64 class processors
*/
- CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
- CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,
+ CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
CPU_QEMU_GENERIC,
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 0fa27446869a..a4f48b0f5541 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -158,7 +158,7 @@ do { \
} while (0)
#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
- defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
+ defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
/*
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 2b7b56736372..3f6ce74335b4 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -306,7 +306,7 @@ static inline void iounmap(const volatile void __iomem *addr)
#undef __IS_KSEG1
}
-#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
#define war_io_reorder_wmb() wmb()
#else
#define war_io_reorder_wmb() barrier()
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index f0b862a83816..4d742acf2be0 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -41,7 +41,7 @@ static inline unsigned long arch_local_irq_save(void)
" .set push \n"
" .set reorder \n"
" .set noat \n"
-#if defined(CONFIG_CPU_LOONGSON3) || defined (CONFIG_CPU_LOONGSON1)
+#if defined(CONFIG_CPU_LOONGSON64) || defined (CONFIG_CPU_LOONGSON1)
" mfc0 %[flags], $12 \n"
" di \n"
#else
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 4aca25f2ff06..83ad90d8005d 100644
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -44,7 +44,7 @@
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
#define cpu_has_wsbh 1
#define cpu_has_ic_fills_f_dc 1
#define cpu_hwrena_impl_bits 0xc0000000
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index be9f727a9328..557e069c400c 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -4,7 +4,7 @@
#include <boot_param.h>
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index b5e288a12dfe..74d94fc1ed53 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -17,7 +17,7 @@
* Override macros used in arch/mips/kernel/head.S.
*/
.macro kernel_entry_setup
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
@@ -46,7 +46,7 @@
* Do SMP slave processor setup.
*/
.macro smp_slave_setup
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index 694a58574ec0..40a24b76b874 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -109,7 +109,7 @@ static inline void do_perfcnt_IRQ(void)
#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base
#else
#define LOONGSON_PCIIO_BASE 0x1fd00000
diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h
index 97f807fb2117..05cc9052772f 100644
--- a/arch/mips/include/asm/mach-loongson64/pci.h
+++ b/arch/mips/include/asm/mach-loongson64/pci.h
@@ -35,7 +35,7 @@ extern struct pci_ops loongson_pci_ops;
#else /* loongson2f/32bit & loongson2e */
/* this pci memory space is mapped by pcimap in pci.c */
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_PCI_MEM_START 0x40000000UL
#define LOONGSON_PCI_MEM_END 0x7effffffUL
#else
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index ed70994fbbec..9fe9515204d6 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -121,10 +121,10 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "SB1 "
#elif defined CONFIG_CPU_LOONGSON1
#define MODULE_PROC_FAMILY "LOONGSON1 "
-#elif defined CONFIG_CPU_LOONGSON2
-#define MODULE_PROC_FAMILY "LOONGSON2 "
-#elif defined CONFIG_CPU_LOONGSON3
-#define MODULE_PROC_FAMILY "LOONGSON3 "
+#elif defined CONFIG_CPU_LOONGSON2EF
+#define MODULE_PROC_FAMILY "LOONGSON2EF "
+#elif defined CONFIG_CPU_LOONGSON64
+#define MODULE_PROC_FAMILY "LOONGSON64 "
#elif defined CONFIG_CPU_CAVIUM_OCTEON
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index aca909bd7841..684efaa990ee 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -390,7 +390,7 @@ unsigned long get_wchan(struct task_struct *p);
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
/*
* Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
* tight read loop is executed, because reads take priority over writes & the
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 7f4a32d3345a..769d8b63f9fa 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -67,7 +67,7 @@ static inline void flush_scache_line_indexed(unsigned long addr)
static inline void flush_icache_line(unsigned long addr)
{
switch (boot_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
cache_op(Hit_Invalidate_I_Loongson2, addr);
break;
@@ -149,7 +149,7 @@ static inline void flush_scache_line(unsigned long addr)
static inline int protected_flush_icache_line(unsigned long addr)
{
switch (boot_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
default:
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c2eb392597bf..73d474766b5b 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -608,7 +608,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
if (!(flags & FTLB_EN))
return 1;
return 0;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
/* Flush ITLB, DTLB, VTLB and FTLB */
write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
@@ -1529,21 +1529,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
switch (c->processor_id & PRID_REV_MASK) {
case PRID_REV_LOONGSON2E:
- c->cputype = CPU_LOONGSON2;
+ c->cputype = CPU_LOONGSON2EF;
__cpu_name[cpu] = "ICT Loongson-2";
set_elf_platform(cpu, "loongson2e");
set_isa(c, MIPS_CPU_ISA_III);
c->fpu_msk31 |= FPU_CSR_CONDX;
break;
case PRID_REV_LOONGSON2F:
- c->cputype = CPU_LOONGSON2;
+ c->cputype = CPU_LOONGSON2EF;
__cpu_name[cpu] = "ICT Loongson-2";
set_elf_platform(cpu, "loongson2f");
set_isa(c, MIPS_CPU_ISA_III);
c->fpu_msk31 |= FPU_CSR_CONDX;
break;
case PRID_REV_LOONGSON3A_R1:
- c->cputype = CPU_LOONGSON3;
+ c->cputype = CPU_LOONGSON64;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3a");
set_isa(c, MIPS_CPU_ISA_M64R1);
@@ -1552,7 +1552,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
break;
case PRID_REV_LOONGSON3B_R1:
case PRID_REV_LOONGSON3B_R2:
- c->cputype = CPU_LOONGSON3;
+ c->cputype = CPU_LOONGSON64;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3b");
set_isa(c, MIPS_CPU_ISA_M64R1);
@@ -1907,14 +1907,14 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
switch (c->processor_id & PRID_REV_MASK) {
case PRID_REV_LOONGSON3A_R2_0:
case PRID_REV_LOONGSON3A_R2_1:
- c->cputype = CPU_LOONGSON3;
+ c->cputype = CPU_LOONGSON64;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3a");
set_isa(c, MIPS_CPU_ISA_M64R2);
break;
case PRID_REV_LOONGSON3A_R3_0:
case PRID_REV_LOONGSON3A_R3_1:
- c->cputype = CPU_LOONGSON3;
+ c->cputype = CPU_LOONGSON64;
__cpu_name[cpu] = "ICT Loongson-3";
set_elf_platform(cpu, "loongson3a");
set_isa(c, MIPS_CPU_ISA_M64R2);
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index eb2afc0b8db1..09ca8fd51060 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -178,7 +178,7 @@ void __init check_wait(void)
case CPU_XLP:
cpu_wait = r4k_wait;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0)
cpu_wait = r4k_wait;
break;
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index a3e2da8391ea..0af456a94916 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1623,7 +1623,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
raw_event.cntr_mask =
raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
break;
}
@@ -1769,7 +1769,7 @@ init_hw_perf_events(void)
mipspmu.general_event_map = &mipsxxcore_event_map;
mipspmu.cache_event_map = &mipsxxcore_cache_map;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
mipspmu.name = "mips/loongson3";
mipspmu.general_event_map = &loongson3_event_map;
mipspmu.cache_event_map = &loongson3_cache_map;
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index b8249c233754..8e553fef7a39 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -282,7 +282,7 @@ static unsigned long __init init_initrd(void)
* Initialize the bootmem allocator. It also setup initrd related data
* if needed.
*/
-#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_NUMA))
+#if defined(CONFIG_SGI_IP27) || (defined(CONFIG_CPU_LOONGSON64) && defined(CONFIG_NUMA))
static void __init bootmem_init(void)
{
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 342e41de9d64..0c2570e6fcf6 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2394,7 +2394,7 @@ void __init trap_init(void)
else {
if (cpu_has_vtag_icache)
set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
- else if (current_cpu_type() == CPU_LOONGSON3)
+ else if (current_cpu_type() == CPU_LOONGSON64)
set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
else
set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 2ff84f4b1717..fda7b57b826e 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -279,7 +279,7 @@ EXPORT_SYMBOL(csum_partial)
#endif
/* odd buffer alignment? */
-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64)
.set push
.set arch=mips32r2
wsbh v1, sum
@@ -732,7 +732,7 @@ EXPORT_SYMBOL(csum_partial)
addu sum, v1
#endif
-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_LOONGSON64)
.set push
.set arch=mips32r2
wsbh v1, sum
diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index 4c14a11525f4..d08b20ff2b27 100644
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -79,7 +79,7 @@ config LOONGSON_MACH3X
select I8259
select IRQ_MIPS_CPU
select NR_CPUS_DEFAULT_4
- select SYS_HAS_CPU_LOONGSON3
+ select SYS_HAS_CPU_LOONGSON64
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_HOTPLUG_CPU
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 1a5df773707d..c74bc0251e9d 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -21,4 +21,4 @@ obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
# All Loongson-3 family machines
#
-obj-$(CONFIG_CPU_LOONGSON3) += loongson-3/
+obj-$(CONFIG_CPU_LOONGSON64) += loongson-3/
diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform
index c1a4d4dc4665..b4d2582eb1ef 100644
--- a/arch/mips/loongson64/Platform
+++ b/arch/mips/loongson64/Platform
@@ -3,7 +3,7 @@
#
# Only gcc >= 4.4 have Loongson specific support
-cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2E) += \
$(call cc-option,-march=loongson2e,-march=r4600)
cflags-$(CONFIG_CPU_LOONGSON2F) += \
@@ -22,7 +22,7 @@ ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
endif
endif
-cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
#
# Some versions of binutils, not currently mainline as of 2019/02/04, support
@@ -44,7 +44,7 @@ cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap
# binutils does not merge support for the flag then we can revisit & remove
# this later - for now it ensures vendor toolchains don't cause problems.
#
-cflags-$(CONFIG_CPU_LOONGSON3) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
+cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
#
# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
@@ -55,14 +55,14 @@ cflags-$(CONFIG_CPU_LOONGSON3) += $(call as-option,-Wa$(comma)-mno-fix-loongson3
#
ifeq ($(call cc-ifversion, -ge, 0409, y), y)
ifeq ($(call ld-ifversion, -ge, 225000000, y), y)
- cflags-$(CONFIG_CPU_LOONGSON3) += \
+ cflags-$(CONFIG_CPU_LOONGSON64) += \
$(call cc-option,-march=loongson3a -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
else
- cflags-$(CONFIG_CPU_LOONGSON3) += \
+ cflags-$(CONFIG_CPU_LOONGSON64) += \
$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
endif
else
- cflags-$(CONFIG_CPU_LOONGSON3) += \
+ cflags-$(CONFIG_CPU_LOONGSON64) += \
$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
endif
diff --git a/arch/mips/loongson64/common/pci.c b/arch/mips/loongson64/common/pci.c
index c47bb7bf3aa4..2d9755c49524 100644
--- a/arch/mips/loongson64/common/pci.c
+++ b/arch/mips/loongson64/common/pci.c
@@ -87,7 +87,7 @@ static int __init pcibios_init(void)
#endif
register_pci_controller(&loongson_pci_controller);
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
sbx00_acpi_init();
#endif
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 89b9c851d822..2ec67c937b89 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -320,7 +320,7 @@ static void r4k_blast_icache_page_setup(void)
r4k_blast_icache_page = (void *)cache_noop;
else if (ic_lsize == 16)
r4k_blast_icache_page = blast_icache16_page;
- else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
+ else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache_page = loongson2_blast_icache32_page;
else if (ic_lsize == 32)
r4k_blast_icache_page = blast_icache32_page;
@@ -369,7 +369,7 @@ static void r4k_blast_icache_page_indexed_setup(void)
else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache_page_indexed =
tx49_blast_icache32_page_indexed;
- else if (current_cpu_type() == CPU_LOONGSON2)
+ else if (current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache_page_indexed =
loongson2_blast_icache32_page_indexed;
else
@@ -395,7 +395,7 @@ static void r4k_blast_icache_setup(void)
r4k_blast_icache = blast_r4600_v1_icache32;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache = tx49_blast_icache32;
- else if (current_cpu_type() == CPU_LOONGSON2)
+ else if (current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache = loongson2_blast_icache32;
else
r4k_blast_icache = blast_icache32;
@@ -465,7 +465,7 @@ static void r4k_blast_scache_node_setup(void)
{
unsigned long sc_lsize = cpu_scache_line_size();
- if (current_cpu_type() != CPU_LOONGSON3)
+ if (current_cpu_type() != CPU_LOONGSON64)
r4k_blast_scache_node = (void *)cache_noop;
else if (sc_lsize == 16)
r4k_blast_scache_node = blast_scache16_node;
@@ -480,7 +480,7 @@ static void r4k_blast_scache_node_setup(void)
static inline void local_r4k___flush_cache_all(void * args)
{
switch (current_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4400SC:
@@ -497,7 +497,7 @@ static inline void local_r4k___flush_cache_all(void * args)
r4k_blast_scache();
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
/* Use get_ebase_cpunum() for both NUMA=y/n */
r4k_blast_scache_node(get_ebase_cpunum() >> 2);
break;
@@ -770,7 +770,7 @@ static inline void __local_r4k_flush_icache_range(unsigned long start,
r4k_blast_icache();
else {
switch (boot_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
protected_loongson2_blast_icache_range(start, end);
break;
@@ -863,7 +863,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
preempt_disable();
if (cpu_has_inclusive_pcaches) {
if (size >= scache_size) {
- if (current_cpu_type() != CPU_LOONGSON3)
+ if (current_cpu_type() != CPU_LOONGSON64)
r4k_blast_scache();
else
r4k_blast_scache_node(pa_to_nid(addr));
@@ -904,7 +904,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
preempt_disable();
if (cpu_has_inclusive_pcaches) {
if (size >= scache_size) {
- if (current_cpu_type() != CPU_LOONGSON3)
+ if (current_cpu_type() != CPU_LOONGSON64)
r4k_blast_scache();
else
r4k_blast_scache_node(pa_to_nid(addr));
@@ -1224,7 +1224,7 @@ static void probe_pcache(void)
c->options |= MIPS_CPU_PREFETCH;
break;
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
if (prid & 0x3)
@@ -1242,7 +1242,7 @@ static void probe_pcache(void)
c->dcache.waybit = 0;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
config1 = read_c0_config1();
lsize = (config1 >> 19) & 7;
if (lsize)
@@ -1452,7 +1452,7 @@ static void probe_pcache(void)
c->dcache.flags &= ~MIPS_CACHE_ALIASES;
break;
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
/*
* LOONGSON2 has 4 way icache, but when using indexed cache op,
* one op will act on all 4 ways
@@ -1478,7 +1478,7 @@ static void probe_vcache(void)
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int config2, lsize;
- if (current_cpu_type() != CPU_LOONGSON3)
+ if (current_cpu_type() != CPU_LOONGSON64)
return;
config2 = read_c0_config2();
@@ -1653,11 +1653,11 @@ static void setup_scache(void)
#endif
return;
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
loongson2_sc_init();
return;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
loongson3_sc_init();
return;
@@ -1926,7 +1926,7 @@ void r4k_cache_init(void)
/* Optimization: an L2 flush implicitly flushes the L1 */
current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
/* Loongson-3 maintains cache coherency by hardware */
__flush_cache_all = cache_noop;
__flush_cache_vmap = cache_noop;
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 56e4f8bffd4c..c5578897a4fa 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -187,7 +187,7 @@ static void set_prefetch_parameters(void)
}
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
/* Loongson-3 only support the Pref_Load/Pref_Store. */
pref_bias_clear_store = 128;
pref_bias_copy_load = 128;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index c13e46ced425..83b450ddbbc2 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -35,10 +35,10 @@ extern void build_tlb_refill_handler(void);
static inline void flush_micro_tlb(void)
{
switch (current_cpu_type()) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
write_c0_diag(LOONGSON_DIAG_ITLB);
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB);
break;
default:
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index e01cb33bfa1a..b963209bec02 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -571,8 +571,8 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_BMIPS4350:
case CPU_BMIPS4380:
case CPU_BMIPS5000:
- case CPU_LOONGSON2:
- case CPU_LOONGSON3:
+ case CPU_LOONGSON2EF:
+ case CPU_LOONGSON64:
case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
@@ -1370,7 +1370,7 @@ static void build_r4000_tlb_refill_handler(void)
switch (boot_cpu_type()) {
default:
if (sizeof(long) == 4) {
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
/* Loongson2 ebase is different than r4k, we have more space */
if ((p - tlb_handler) > 64)
panic("TLB refill handler space exceeded");
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 011cf9f891e7..e10f216d0422 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -14,5 +14,5 @@ oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o
oprofile-$(CONFIG_CPU_XLR) += op_model_mipsxx.o
-oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o
-oprofile-$(CONFIG_CPU_LOONGSON3) += op_model_loongson3.o
+oprofile-$(CONFIG_CPU_LOONGSON2EF) += op_model_loongson2.o
+oprofile-$(CONFIG_CPU_LOONGSON64) += op_model_loongson3.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 2f33992f6dff..25cfa70f0ae4 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -104,10 +104,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
lmodel = &op_model_mipsxx_ops;
break;
- case CPU_LOONGSON2:
+ case CPU_LOONGSON2EF:
lmodel = &op_model_loongson2_ops;
break;
- case CPU_LOONGSON3:
+ case CPU_LOONGSON64:
lmodel = &op_model_loongson3_ops;
break;
};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index bb13c266c329..6ed3f380a45e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -298,7 +298,7 @@ config GPIO_IXP4XX
config GPIO_LOONGSON
bool "Loongson-2/3 GPIO support"
- depends on CPU_LOONGSON2 || CPU_LOONGSON3
+ depends on CPU_LOONGSON2EF || CPU_LOONGSON64
help
driver for GPIO functionality on Loongson-2F/3A/3B processors.
diff --git a/drivers/gpio/gpio-loongson.c b/drivers/gpio/gpio-loongson.c
index 00943170ce36..a42145873cc9 100644
--- a/drivers/gpio/gpio-loongson.c
+++ b/drivers/gpio/gpio-loongson.c
@@ -22,7 +22,7 @@
#define STLS2F_N_GPIO 4
#define STLS3A_N_GPIO 16
-#ifdef CONFIG_CPU_LOONGSON3
+#ifdef CONFIG_CPU_LOONGSON64
#define LOONGSON_N_GPIO STLS3A_N_GPIO
#else
#define LOONGSON_N_GPIO STLS2F_N_GPIO
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 987ff16b9420..e9ad4863d915 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -45,7 +45,7 @@ static inline bool drm_arch_can_wc_memory(void)
{
#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
return false;
-#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
+#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)
return false;
#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
/*
--
2.22.0
We've made generic irqchip drivers for Loongson-3 platform, it's time
to say goodbye to these legacy code.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mach-loongson64/irq.h | 1 -
arch/mips/loongson64/irq.c | 167 +-------------------
arch/mips/loongson64/smp.c | 26 ++-
3 files changed, 11 insertions(+), 183 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index baed43285163..e57a21fc581c 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -35,7 +35,6 @@
#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(void);
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c
index 4d7b80a0ffb9..78cd824cc84e 100644
--- a/arch/mips/loongson64/irq.c
+++ b/arch/mips/loongson64/irq.c
@@ -3,180 +3,17 @@
#include <irq.h>
#include <linux/interrupt.h>
#include <linux/init.h>
+#include <linux/irqchip.h>
#include <asm/irq_cpu.h>
-#include <asm/i8259.h>
#include <asm/mipsregs.h>
#include "smp.h"
-/* ICU Configuration Regs - r/w */
-
-#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
-#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
-#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
-
-/* ICU Enable Regs - IntEn & IntISR are r/o. */
-
-#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
-#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
-#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
-#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
-
-extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
-
-unsigned int irq_cpu[16] = {[0 ... 15] = -1};
-unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
-unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
-
-int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
- bool force)
-{
- unsigned int cpu;
- struct cpumask new_affinity;
-
- /* I/O devices are connected on package-0 */
- cpumask_copy(&new_affinity, affinity);
- for_each_cpu(cpu, affinity)
- if (cpu_data[cpu].package > 0)
- cpumask_clear_cpu(cpu, &new_affinity);
-
- if (cpumask_empty(&new_affinity))
- return -EINVAL;
-
- cpumask_copy(d->common->affinity, &new_affinity);
-
- return IRQ_SET_MASK_OK_NOCOPY;
-}
-
-static void ht_irqdispatch(void)
-{
- unsigned int i, irq;
- struct irq_data *irqd;
- struct cpumask affinity;
-
- irq = LOONGSON_HT1_INT_VECTOR(0);
- LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
-
- for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
- if (!(irq & (0x1 << ht_irq[i])))
- continue;
-
- /* handled by local core */
- if (local_irq & (0x1 << ht_irq[i])) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irqd = irq_get_irq_data(ht_irq[i]);
- cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
- if (cpumask_empty(&affinity)) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
- if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
- irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
-
- if (irq_cpu[ht_irq[i]] == 0) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- /* balanced by other cores */
- loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
- }
-}
-
-#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & CAUSEF_IP7)
- do_IRQ(LOONGSON_TIMER_IRQ);
-#if defined(CONFIG_SMP)
- if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt();
-#endif
- if (pending & CAUSEF_IP3)
- ht_irqdispatch();
- if (pending & CAUSEF_IP2)
- do_IRQ(LOONGSON_UART_IRQ);
- if (pending & UNUSED_IPS) {
- pr_err("%s : spurious interrupt\n", __func__);
- spurious_interrupt();
- }
-}
-
-static inline void mask_loongson_irq(struct irq_data *d) { }
-static inline void unmask_loongson_irq(struct irq_data *d) { }
-
- /* For MIPS IRQs which shared by all cores */
-static struct irq_chip loongson_irq_chip = {
- .name = "Loongson",
- .irq_ack = mask_loongson_irq,
- .irq_mask = mask_loongson_irq,
- .irq_mask_ack = mask_loongson_irq,
- .irq_unmask = unmask_loongson_irq,
- .irq_eoi = unmask_loongson_irq,
-};
-
-void irq_router_init(void)
-{
- int i;
-
- /* route LPC int to cpu core0 int 0 */
- LOONGSON_INT_ROUTER_LPC =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
- /* route HT1 int0 ~ int7 to cpu core0 INT1*/
- for (i = 0; i < 8; i++)
- LOONGSON_INT_ROUTER_HT1(i) =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
- /* enable HT1 interrupt */
- LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
- /* enable router interrupt intenset */
- LOONGSON_INT_ROUTER_INTENSET =
- LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
-}
void __init arch_init_irq(void)
{
- struct irq_chip *chip;
-
- /*
- * Clear all of the interrupts while we change the able around a bit.
- * int-handler is not on bootstrap
- */
- clear_c0_status(ST0_IM | ST0_BEV);
-
- /* no steer */
- LOONGSON_INTSTEER = 0;
-
- /*
- * Mask out all interrupt by writing "1" to all bit position in
- * the interrupt reset reg.
- */
- LOONGSON_INTENCLR = ~0;
-
- clear_c0_status(ST0_IM | ST0_BEV);
-
- irq_router_init();
- mips_cpu_irq_init();
- init_i8259_irqs();
- chip = irq_get_chip(I8259A_IRQ_BASE);
- chip->irq_set_affinity = plat_set_irq_affinity;
-
- irq_set_chip_and_handler(LOONGSON_UART_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
- irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
-
- set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
+ irqchip_init();
}
#ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index 8ad845e522fb..d53942c56a16 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -4,6 +4,7 @@
* Author: Chen Huacai, [email protected]
*/
+#include <irq.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/sched.h>
@@ -24,6 +25,8 @@
DEFINE_PER_CPU(int, cpu_state);
+#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
+
static void *ipi_set0_regs[16];
static void *ipi_clear0_regs[16];
static void *ipi_status0_regs[16];
@@ -245,21 +248,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]);
}
-#define IPI_IRQ_OFFSET 6
-
-void loongson3_send_irq_by_ipi(int cpu, int irqs)
-{
- loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]);
-}
-
-void loongson3_ipi_interrupt()
+static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
{
int i, cpu = smp_processor_id();
- unsigned int action, c0count, irqs;
+ unsigned int action, c0count;
/* Load the ipi register to figure out what we're supposed to do */
action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]);
- irqs = action >> IPI_IRQ_OFFSET;
/* Clear the ipi register to clear the interrupt */
loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]);
@@ -282,13 +277,7 @@ void loongson3_ipi_interrupt()
__wbflush(); /* Let others see the result ASAP */
}
- if (irqs) {
- int irq;
- while ((irq = ffs(irqs))) {
- do_IRQ(irq-1);
- irqs &= ~(1<<(irq-1));
- }
- }
+ return IRQ_HANDLED;
}
#define MAX_LOOPS 800
@@ -384,6 +373,9 @@ static void __init loongson3_smp_setup(void)
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
{
+ if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
+ pr_err("Failed to request IPI IRQ\n");
init_cpu_present(cpu_possible_mask);
per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
}
--
2.22.0
Add generic device dts for Loongson-3 devices.
They seems identical but will be different later.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 4 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/3a-package.dtsi | 69 +++++++++++++++++++++
arch/mips/boot/dts/loongson/3a1000_780e.dts | 10 +++
arch/mips/boot/dts/loongson/3a2000_780e.dts | 10 +++
arch/mips/boot/dts/loongson/3a3000_780e.dts | 10 +++
arch/mips/boot/dts/loongson/3b-package.dtsi | 69 +++++++++++++++++++++
arch/mips/boot/dts/loongson/3b1x00_780e.dts | 10 +++
arch/mips/boot/dts/loongson/Makefile | 5 ++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 35 +++++++++++
10 files changed, 222 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/loongson/3a-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/3a1000_780e.dts
create mode 100644 arch/mips/boot/dts/loongson/3a2000_780e.dts
create mode 100644 arch/mips/boot/dts/loongson/3a3000_780e.dts
create mode 100644 arch/mips/boot/dts/loongson/3b-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/3b1x00_780e.dts
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b6bdd96ec74e..5bad9aafcbdf 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -489,6 +489,8 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_LITTLE_ENDIAN
select ZONE_DMA32
select SYS_SUPPORTS_ZBOOT
+ select USE_OF
+ select BUILTIN_DTB
help
This enables the support of Loongson-3A/3B/2-series-soc processors
@@ -3047,7 +3049,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && \
+ !MACH_LOONGSON64 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..d429a69bfe30 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
+subdir-y += loongson
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
diff --git a/arch/mips/boot/dts/loongson/3a-package.dtsi b/arch/mips/boot/dts/loongson/3a-package.dtsi
new file mode 100644
index 000000000000..739cf43c7310
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/3a-package.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package@0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0xEFD 0xFB000000 0xEFD 0xFB000000 0x10000000 /* 3A HT Config Space */>;
+
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,ls3-iointc";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupt-parent = <&iointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&iointc>;
+ no-loopback-test;
+ };
+
+ htintc: interrupt-controller@0xEFDFB000080 {
+ compatible = "loongson,ls3-htintc";
+ reg = <0xEFD 0xFB000080 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&iointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/3a1000_780e.dts b/arch/mips/boot/dts/loongson/3a1000_780e.dts
new file mode 100644
index 000000000000..dc1afe9410c8
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/3a1000_780e.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "3a-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a1000-780e";
+};
diff --git a/arch/mips/boot/dts/loongson/3a2000_780e.dts b/arch/mips/boot/dts/loongson/3a2000_780e.dts
new file mode 100644
index 000000000000..621e0d3b5fbd
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/3a2000_780e.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "3a-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a2000-780e";
+};
diff --git a/arch/mips/boot/dts/loongson/3a3000_780e.dts b/arch/mips/boot/dts/loongson/3a3000_780e.dts
new file mode 100644
index 000000000000..f170f1c2189d
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/3a3000_780e.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "3a-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3a3000-780e";
+};
diff --git a/arch/mips/boot/dts/loongson/3b-package.dtsi b/arch/mips/boot/dts/loongson/3b-package.dtsi
new file mode 100644
index 000000000000..af6e115d33c0
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/3b-package.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package@0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0x1EFD 0xFB000000 0x1EFD 0xFB000000 0x10000000 /* 3B HT Config Space */>;
+
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,ls3-iointc";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&iointc>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&iointc>;
+ no-loopback-test;
+ };
+
+ htintc: interrupt-controller@0x1EFDFB000080 {
+ compatible = "loongson,ls3-htintc";
+ reg = <0x1EFD 0xFB000080 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&iointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/3b1x00_780e.dts b/arch/mips/boot/dts/loongson/3b1x00_780e.dts
new file mode 100644
index 000000000000..9b0dff0b1482
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/3b1x00_780e.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "3b-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,ls3b-780e";
+};
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000000..a225d84a521e
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,5 @@
+# SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64) += 3a1000_780e.dtb 3a2000_780e.dtb 3a3000_780e.dtb 3b1x00_780e.dtb \
+
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
new file mode 100644
index 000000000000..915363eafa2f
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ pch {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x000 0x10000000 0x000 0x10000000 0x10000000
+ 0x000 0x40000000 0x000 0x40000000 0x40000000>;
+
+ isa {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0 0x1000>;
+
+ i8259: interrupt-controller@20 {
+ compatible = "intel,i8259";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ plat-poll;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>;
+ interrupt-parent = <&htintc>;
+ };
+
+ rtc0: rtc@70 {
+ compatible = "motorola,mc146818";
+ reg = <1 0x70 0x8>;
+ interrupts = <8>;
+ interrupt-parent = <&i8259>;
+ };
+ };
+ };
+};
--
2.22.0
Load proper dtb according to firmware passed parameters and
CPU PRID.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../asm/mach-loongson64/builtin_dtbs.h | 16 ++++++++++++
.../include/asm/mach-loongson64/loongson64.h | 2 ++
arch/mips/loongson64/env.c | 26 +++++++++++++++++++
arch/mips/loongson64/setup.c | 16 ++++++++++++
4 files changed, 60 insertions(+)
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
new file mode 100644
index 000000000000..38063c7d20b1
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Built-in Generic dtbs for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+
+extern u32 __dtb_3a1000_780e_begin[];
+extern u32 __dtb_3a2000_780e_begin[];
+extern u32 __dtb_3a3000_780e_begin[];
+extern u32 __dtb_3b1x00_780e_begin[];
+
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/loongson64.h b/arch/mips/include/asm/mach-loongson64/loongson64.h
index ace91d52744e..58e07b7d835f 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson64.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson64.h
@@ -45,4 +45,6 @@ extern u64 loongson_freqctrl[MAX_PACKAGES];
extern const struct plat_smp_ops loongson3_smp_ops;
extern void __init prom_init_lefi(void);
+extern void *loongson_fdt_blob;
+
#endif
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 93658cfbf3a6..34b4d77097f2 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -20,6 +20,7 @@
#include <loongson64.h>
#include <boot_param.h>
+#include <builtin_dtbs.h>
#include <workarounds.h>
u32 cpu_clock_freq;
@@ -126,6 +127,31 @@ void __init prom_init_lefi(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ loongson_fdt_blob = __dtb_3a1000_780e_begin;
+ break;
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ loongson_fdt_blob = __dtb_3a2000_780e_begin;
+ break;
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ loongson_fdt_blob = __dtb_3a3000_780e_begin;
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ loongson_fdt_blob = __dtb_3b1x00_780e_begin;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
+
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
index ed014374780a..3b850b3128ea 100644
--- a/arch/mips/loongson64/setup.c
+++ b/arch/mips/loongson64/setup.c
@@ -7,9 +7,15 @@
#include <asm/setup.h>
#include <asm/smp-ops.h>
#include <asm/cacheflush.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
#include <loongson64.h>
+void *loongson_fdt_blob;
+
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
@@ -81,6 +87,8 @@ void __init prom_free_prom_memory(void)
void __init plat_mem_setup(void)
{
+ if (loongson_fdt_blob)
+ __dt_setup_arch(loongson_fdt_blob);
}
void __init plat_time_init(void)
@@ -89,3 +97,11 @@ void __init plat_time_init(void)
setup_hpet_timer();
#endif
}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
+}
--
2.22.0
Prepare for later dts.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../bindings/mips/loongson/devices.yaml | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
new file mode 100644
index 000000000000..0665f0f7ec45
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson based Platforms Device Tree Bindings
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+description: |
+ Devices with a Loongson CPU shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Loongson 3A1000 + RS780E
+ items:
+ - const: loongson,ls3a1000-780e
+
+ - description: Loongson 3A2000 + RS780E
+ items:
+ - const: loongson,ls3a2000-780e
+
+ - description: Loongson 3A3000 + RS780E
+ items:
+ - const: loongson,ls3a3000-780e
+
+ - description: Loongson 3A3000 + 7A
+ items:
+ - const: loongson,ls3a3000-7a
+
+ - description: Loongson 3B1000/1500 + RS780E 2Way
+ items:
+ - const: loongson,ls3b1x00-780e
+...
--
2.22.0
Place newly submited irqchip drivers and devicetree support under
MIPS/LOONGSON64 ARCHITECTURE.
Signed-off-by: Jiaxun Yang <[email protected]>
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b2ad16902d70..836b21baeb20 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10755,9 +10755,12 @@ MIPS/LOONGSON64 ARCHITECTURE
M: Huacai Chen <[email protected]>
L: [email protected]
S: Maintained
+F: arch/mips/boot/dts/loongson/
F: arch/mips/loongson64/
F: arch/mips/include/asm/mach-loongson64/
F: drivers/platform/mips/cpu_hwmon.c
+F: drivers/irqchip/irq-ls3-*
+F: Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-*
F: drivers/*/*loongson3*
F: drivers/*/*/*loongson3*
--
2.22.0
I'm going to help with LOONGSON64 maintainance as well.
Signed-off-by: Jiaxun Yang <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 836b21baeb20..36b656ded1b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10753,6 +10753,7 @@ F: drivers/*/*/*loongson2*
MIPS/LOONGSON64 ARCHITECTURE
M: Huacai Chen <[email protected]>
+M: Jiaxun Yang <[email protected]>
L: [email protected]
S: Maintained
F: arch/mips/boot/dts/loongson/
--
2.22.0
Hi, Jiaxun,
All of us think that Loongson Technology Co. Ltd's naming is very
confusing. They call both their processors and their bridge-chipset
as "Loongson", so Loongson-3A is processor, Loongson-7A is bridge, and
Loongson-2H can be both processor and bridge.....
We all think this is a bad thing, so let's do something in our code to
make life easier:
1, Don't use raw "ls" to stand for loongson anywhere.
2, To describe CPU please use "loongson". E.g., Loongson, Loongson-3,
Loongson-2H, Loongson-3A, Loongson-3B, Loongson-3A4000.
3, To describe bridge (chipset, or PCH) please use LS2H, LS2K and
LS7A, and we can use LS2X to cover them all in some drivers.
4, In file names use their lower-case names. E.g., loongson,
loongson3, ls2h, ls7a.
Don't be afraid of long names. Long names is harmless, but disordered
abbreviation is a nightmare.
Huacai
On Thu, Sep 5, 2019 at 10:44 PM Jiaxun Yang <[email protected]> wrote:
>
> v1:
> - dt-bindings fixup according to Rob's comments
> - irqchip fixup according to Marc's comments
> - ls3-iointc: Make Core&IP map per-IRQ
> - Regenerate kconfigs
> - Typo & style improvements
>
> v2:
> - dt-bindings: Fix IOINTC, collect Rob's review tag
> - dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
>
> Jiaxun Yang (19):
> MIPS: Loongson64: Rename CPU TYPES
> MIPS: Loongson64: separate loongson2ef/loongson64 code
> MAINTAINERS: Fix entries for new loongson64 path
> irqchip: Export generic chip domain map/unmap functions
> irqchip: Add driver for Loongson-3 I/O interrupt controller
> dt-bindings: interrupt-controller: Add Loongson-3 IOINTC
> irqchip: Add driver for Loongson-3 HyperTransport interrupt controller
> dt-bindings: interrupt-controller: Add Loongson-3 HTINTC
> irqchip: i8259: Add plat-poll support
> irqchip: mips-cpu: Convert to simple domain
> MIPS: Loongson64: Drop legacy IRQ code
> dt-bindings: mips: Add loongson boards
> dt-bindings: Document loongson vendor-prefix
> MIPS: Loongson64: Add generic dts
> MIPS: Loongson64: Load built-in dtbs
> GPIO: loongson: Drop Loongson-3A/3B support
> MIPS: Loongson: Regenerate defconfigs
> MAINTAINERS: Add new pathes to LOONGSON64 ARCHITECTURE
> MAINTAINERS: Add myself as maintainer of LOONGSON64
>
> .../loongson,ls3-htintc.yaml | 55 ++++
> .../loongson,ls3-iointc.yaml | 79 +++++
> .../bindings/mips/loongson/devices.yaml | 39 +++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> MAINTAINERS | 13 +-
> arch/mips/Kbuild.platforms | 1 +
> arch/mips/Kconfig | 83 ++++--
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/loongson/3a-package.dtsi | 69 +++++
> arch/mips/boot/dts/loongson/3a1000_780e.dts | 10 +
> arch/mips/boot/dts/loongson/3a2000_780e.dts | 10 +
> arch/mips/boot/dts/loongson/3a3000_780e.dts | 10 +
> arch/mips/boot/dts/loongson/3b-package.dtsi | 69 +++++
> arch/mips/boot/dts/loongson/3b1x00_780e.dts | 10 +
> arch/mips/boot/dts/loongson/Makefile | 5 +
> arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 35 +++
> arch/mips/configs/fuloong2e_defconfig | 8 +-
> arch/mips/configs/lemote2f_defconfig | 8 +-
> arch/mips/configs/loongson3_defconfig | 13 +-
> arch/mips/include/asm/bootinfo.h | 1 -
> arch/mips/include/asm/cop2.h | 2 +-
> arch/mips/include/asm/cpu-type.h | 6 +-
> arch/mips/include/asm/cpu.h | 4 +-
> arch/mips/include/asm/hazards.h | 2 +-
> arch/mips/include/asm/io.h | 2 +-
> arch/mips/include/asm/irqflags.h | 2 +-
> .../mach-loongson2ef/cpu-feature-overrides.h | 45 +++
> .../cs5536/cs5536.h | 0
> .../cs5536/cs5536_mfgpt.h | 0
> .../cs5536/cs5536_pci.h | 0
> .../cs5536/cs5536_vsm.h | 0
> .../loongson2ef.h} | 31 +-
> .../machine.h | 6 -
> .../mc146818rtc.h | 5 +-
> .../mem.h | 6 +-
> arch/mips/include/asm/mach-loongson2ef/pci.h | 43 +++
> .../include/asm/mach-loongson2ef/spaces.h | 10 +
> .../asm/mach-loongson64/builtin_dtbs.h | 16 +
> .../mach-loongson64/cpu-feature-overrides.h | 8 +-
> arch/mips/include/asm/mach-loongson64/irq.h | 6 +-
> .../asm/mach-loongson64/kernel-entry-init.h | 74 -----
> .../include/asm/mach-loongson64/loongson64.h | 50 ++++
> .../mips/include/asm/mach-loongson64/mmzone.h | 16 -
> arch/mips/include/asm/mach-loongson64/pci.h | 41 +--
> .../include/asm/mach-loongson64/workarounds.h | 4 +-
> arch/mips/include/asm/module.h | 8 +-
> arch/mips/include/asm/processor.h | 2 +-
> arch/mips/include/asm/r4kcache.h | 4 +-
> arch/mips/kernel/cpu-probe.c | 14 +-
> arch/mips/kernel/idle.c | 2 +-
> arch/mips/kernel/perf_event_mipsxx.c | 4 +-
> arch/mips/kernel/setup.c | 2 +-
> arch/mips/kernel/traps.c | 2 +-
> arch/mips/lib/csum_partial.S | 4 +-
> arch/mips/loongson2ef/Kconfig | 93 ++++++
> arch/mips/loongson2ef/Makefile | 18 ++
> arch/mips/loongson2ef/Platform | 32 ++
> .../common/Makefile | 0
> .../common/bonito-irq.c | 2 +-
> .../common/cmdline.c | 2 +-
> .../common/cs5536/Makefile | 0
> .../common/cs5536/cs5536_acc.c | 0
> .../common/cs5536/cs5536_ehci.c | 0
> .../common/cs5536/cs5536_ide.c | 0
> .../common/cs5536/cs5536_isa.c | 0
> .../common/cs5536/cs5536_mfgpt.c | 0
> .../common/cs5536/cs5536_ohci.c | 0
> .../common/cs5536/cs5536_pci.c | 0
> .../common/early_printk.c | 2 +-
> arch/mips/loongson2ef/common/env.c | 71 +++++
> .../{loongson64 => loongson2ef}/common/init.c | 7 +-
> .../{loongson64 => loongson2ef}/common/irq.c | 2 +-
> .../common/machtype.c | 3 +-
> .../{loongson64 => loongson2ef}/common/mem.c | 40 +--
> .../{loongson64 => loongson2ef}/common/pci.c | 11 +-
> .../common/platform.c | 0
> .../{loongson64 => loongson2ef}/common/pm.c | 2 +-
> .../common/reset.c | 23 +-
> .../{loongson64 => loongson2ef}/common/rtc.c | 0
> .../common/serial.c | 37 +--
> .../common/setup.c | 2 +-
> .../{loongson64 => loongson2ef}/common/time.c | 2 +-
> .../common/uart_base.c | 10 +-
> .../fuloong-2e/Makefile | 0
> .../fuloong-2e/dma.c | 0
> .../fuloong-2e/irq.c | 2 +-
> .../fuloong-2e/reset.c | 2 +-
> .../lemote-2f/Makefile | 0
> .../lemote-2f/clock.c | 2 +-
> .../lemote-2f/dma.c | 0
> .../lemote-2f/ec_kb3310b.c | 0
> .../lemote-2f/ec_kb3310b.h | 0
> .../lemote-2f/irq.c | 2 +-
> .../lemote-2f/machtype.c | 2 +-
> .../lemote-2f/pm.c | 2 +-
> .../lemote-2f/reset.c | 2 +-
> arch/mips/loongson64/Kconfig | 126 +-------
> arch/mips/loongson64/Makefile | 23 +-
> arch/mips/loongson64/Platform | 36 +--
> .../loongson64/{loongson-3 => }/acpi_init.c | 3 +-
> .../loongson64/{loongson-3 => }/cop2-ex.c | 5 +-
> arch/mips/loongson64/{loongson-3 => }/dma.c | 6 +-
> arch/mips/loongson64/{common => }/env.c | 98 +++----
> arch/mips/loongson64/{loongson-3 => }/hpet.c | 0
> arch/mips/loongson64/irq.c | 27 ++
> arch/mips/loongson64/loongson-3/Makefile | 11 -
> arch/mips/loongson64/loongson-3/irq.c | 158 ----------
> arch/mips/loongson64/{loongson-3 => }/numa.c | 4 +-
> arch/mips/loongson64/pci.c | 45 +++
> .../loongson64/{loongson-3 => }/platform.c | 0
> arch/mips/loongson64/reset.c | 58 ++++
> arch/mips/loongson64/setup.c | 107 +++++++
> arch/mips/loongson64/{loongson-3 => }/smp.c | 28 +-
> arch/mips/loongson64/{loongson-3 => }/smp.h | 0
> arch/mips/mm/c-r4k.c | 32 +-
> arch/mips/mm/page.c | 2 +-
> arch/mips/mm/tlb-r4k.c | 4 +-
> arch/mips/mm/tlbex.c | 6 +-
> arch/mips/oprofile/Makefile | 4 +-
> arch/mips/oprofile/common.c | 4 +-
> arch/mips/oprofile/op_model_loongson2.c | 2 +-
> arch/mips/oprofile/op_model_loongson3.c | 2 +-
> arch/mips/pci/Makefile | 2 +-
> arch/mips/pci/fixup-fuloong2e.c | 2 +-
> arch/mips/pci/fixup-lemote2f.c | 2 +-
> arch/mips/pci/ops-loongson2.c | 2 +-
> arch/mips/pci/ops-loongson3.c | 2 +-
> drivers/cpufreq/loongson2_cpufreq.c | 2 +-
> drivers/gpio/Kconfig | 6 +-
> drivers/gpio/gpio-loongson.c | 11 +-
> drivers/irqchip/Kconfig | 17 ++
> drivers/irqchip/Makefile | 2 +
> drivers/irqchip/irq-i8259.c | 47 ++-
> drivers/irqchip/irq-ls3-htintc.c | 147 ++++++++++
> drivers/irqchip/irq-ls3-iointc.c | 275 ++++++++++++++++++
> drivers/irqchip/irq-mips-cpu.c | 2 +-
> drivers/platform/mips/cpu_hwmon.c | 2 +-
> include/drm/drm_cache.h | 2 +-
> include/linux/irq.h | 1 +
> kernel/irq/generic-chip.c | 4 +-
> 140 files changed, 1760 insertions(+), 874 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
> create mode 100644 arch/mips/boot/dts/loongson/3a-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/3a1000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3a2000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3a3000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3b-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/3b1x00_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/Makefile
> create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> create mode 100644 arch/mips/include/asm/mach-loongson2ef/cpu-feature-overrides.h
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536.h (100%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_mfgpt.h (100%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_pci.h (100%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/cs5536/cs5536_vsm.h (100%)
> rename arch/mips/include/asm/{mach-loongson64/loongson.h => mach-loongson2ef/loongson2ef.h} (91%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/machine.h (80%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mc146818rtc.h (80%)
> rename arch/mips/include/asm/{mach-loongson64 => mach-loongson2ef}/mem.h (86%)
> create mode 100644 arch/mips/include/asm/mach-loongson2ef/pci.h
> create mode 100644 arch/mips/include/asm/mach-loongson2ef/spaces.h
> create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
> delete mode 100644 arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> create mode 100644 arch/mips/include/asm/mach-loongson64/loongson64.h
> create mode 100644 arch/mips/loongson2ef/Kconfig
> create mode 100644 arch/mips/loongson2ef/Makefile
> create mode 100644 arch/mips/loongson2ef/Platform
> rename arch/mips/{loongson64 => loongson2ef}/common/Makefile (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/bonito-irq.c (97%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cmdline.c (97%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/Makefile (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_acc.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ehci.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ide.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_isa.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_mfgpt.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_ohci.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/cs5536/cs5536_pci.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/early_printk.c (97%)
> create mode 100644 arch/mips/loongson2ef/common/env.c
> rename arch/mips/{loongson64 => loongson2ef}/common/init.c (90%)
> rename arch/mips/{loongson64 => loongson2ef}/common/irq.c (98%)
> rename arch/mips/{loongson64 => loongson2ef}/common/machtype.c (94%)
> rename arch/mips/{loongson64 => loongson2ef}/common/mem.c (72%)
> rename arch/mips/{loongson64 => loongson2ef}/common/pci.c (89%)
> rename arch/mips/{loongson64 => loongson2ef}/common/platform.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/pm.c (99%)
> rename arch/mips/{loongson64 => loongson2ef}/common/reset.c (77%)
> rename arch/mips/{loongson64 => loongson2ef}/common/rtc.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/common/serial.c (63%)
> rename arch/mips/{loongson64 => loongson2ef}/common/setup.c (97%)
> rename arch/mips/{loongson64 => loongson2ef}/common/time.c (96%)
> rename arch/mips/{loongson64 => loongson2ef}/common/uart_base.c (77%)
> rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/Makefile (100%)
> rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/dma.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/irq.c (98%)
> rename arch/mips/{loongson64 => loongson2ef}/fuloong-2e/reset.c (93%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/Makefile (100%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/clock.c (98%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/dma.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.c (100%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/ec_kb3310b.h (100%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/irq.c (99%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/machtype.c (98%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/pm.c (99%)
> rename arch/mips/{loongson64 => loongson2ef}/lemote-2f/reset.c (99%)
> rename arch/mips/loongson64/{loongson-3 => }/acpi_init.c (99%)
> rename arch/mips/loongson64/{loongson-3 => }/cop2-ex.c (88%)
> rename arch/mips/loongson64/{loongson-3 => }/dma.c (82%)
> rename arch/mips/loongson64/{common => }/env.c (83%)
> rename arch/mips/loongson64/{loongson-3 => }/hpet.c (100%)
> create mode 100644 arch/mips/loongson64/irq.c
> delete mode 100644 arch/mips/loongson64/loongson-3/Makefile
> delete mode 100644 arch/mips/loongson64/loongson-3/irq.c
> rename arch/mips/loongson64/{loongson-3 => }/numa.c (98%)
> create mode 100644 arch/mips/loongson64/pci.c
> rename arch/mips/loongson64/{loongson-3 => }/platform.c (100%)
> create mode 100644 arch/mips/loongson64/reset.c
> create mode 100644 arch/mips/loongson64/setup.c
> rename arch/mips/loongson64/{loongson-3 => }/smp.c (98%)
> rename arch/mips/loongson64/{loongson-3 => }/smp.h (100%)
> create mode 100644 drivers/irqchip/irq-ls3-htintc.c
> create mode 100644 drivers/irqchip/irq-ls3-iointc.c
>
> --
> 2.22.0
>
On Thu, Sep 5, 2019 at 10:47 PM Jiaxun Yang <[email protected]> wrote:
>
> Add generic device dts for Loongson-3 devices.
> They seems identical but will be different later.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> arch/mips/Kconfig | 4 +-
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/loongson/3a-package.dtsi | 69 +++++++++++++++++++++
> arch/mips/boot/dts/loongson/3a1000_780e.dts | 10 +++
> arch/mips/boot/dts/loongson/3a2000_780e.dts | 10 +++
> arch/mips/boot/dts/loongson/3a3000_780e.dts | 10 +++
> arch/mips/boot/dts/loongson/3b-package.dtsi | 69 +++++++++++++++++++++
> arch/mips/boot/dts/loongson/3b1x00_780e.dts | 10 +++
> arch/mips/boot/dts/loongson/Makefile | 5 ++
> arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 35 +++++++++++
> 10 files changed, 222 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/boot/dts/loongson/3a-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/3a1000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3a2000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3a3000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3b-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/3b1x00_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/Makefile
> create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index b6bdd96ec74e..5bad9aafcbdf 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -489,6 +489,8 @@ config MACH_LOONGSON64
> select SYS_SUPPORTS_LITTLE_ENDIAN
> select ZONE_DMA32
> select SYS_SUPPORTS_ZBOOT
> + select USE_OF
> + select BUILTIN_DTB
> help
> This enables the support of Loongson-3A/3B/2-series-soc processors
>
> @@ -3047,7 +3049,7 @@ endchoice
> choice
> prompt "Kernel command line type" if !CMDLINE_OVERRIDE
> default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
> - !MIPS_MALTA && \
> + !MACH_LOONGSON64 && !MIPS_MALTA && \
> !CAVIUM_OCTEON_SOC
> default MIPS_CMDLINE_FROM_BOOTLOADER
>
> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> index 1e79cab8e269..d429a69bfe30 100644
> --- a/arch/mips/boot/dts/Makefile
> +++ b/arch/mips/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += cavium-octeon
> subdir-y += img
> subdir-y += ingenic
> subdir-y += lantiq
> +subdir-y += loongson
> subdir-y += mscc
> subdir-y += mti
> subdir-y += netlogic
> diff --git a/arch/mips/boot/dts/loongson/3a-package.dtsi b/arch/mips/boot/dts/loongson/3a-package.dtsi
> new file mode 100644
> index 000000000000..739cf43c7310
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3a-package.dtsi
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + package@0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
> + 0 0x3ff00000 0 0x3ff00000 0x100000
> + 0xEFD 0xFB000000 0xEFD 0xFB000000 0x10000000 /* 3A HT Config Space */>;
> +
> + iointc: interrupt-controller@3ff01400 {
> + compatible = "loongson,ls3-iointc";
> + reg = <0 0x3ff01400 0x64>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
> +
> + cpu_uart0: serial@1fe001e0 {
> + device_type = "serial";
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e0 0x8>;
> + clock-frequency = <33000000>;
> + interrupt-parent = <&iointc>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + no-loopback-test;
> + };
> +
> + cpu_uart1: serial@1fe001e8 {
> + status = "disabled";
> + device_type = "serial";
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e8 0x8>;
> + clock-frequency = <33000000>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&iointc>;
> + no-loopback-test;
> + };
> +
> + htintc: interrupt-controller@0xEFDFB000080 {
> + compatible = "loongson,ls3-htintc";
> + reg = <0xEFD 0xFB000080 0x100>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&iointc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> + <25 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +};
Hi, Jiaxun,
I'm very glad to see that dts files become less in this version, but I
think we also don't need to distinguish cpu types (i.e.,
3a1000/3b1500/3a2000/3a3000). Then, we only need three dts files
(loongson3_ls2h.dts, loongson3_ls7a.dts, loongson3_rs780.dts) which is
the same as in our own git repository. If we really need to
distinguish cpu type, PRID or CPUCFG in Loongson-3A4000 is more
suitable than dts. In other words, I want dts only do as minimal as
possible.
Huacai
> diff --git a/arch/mips/boot/dts/loongson/3a1000_780e.dts b/arch/mips/boot/dts/loongson/3a1000_780e.dts
> new file mode 100644
> index 000000000000..dc1afe9410c8
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3a1000_780e.dts
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "3a-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,ls3a1000-780e";
> +};
> diff --git a/arch/mips/boot/dts/loongson/3a2000_780e.dts b/arch/mips/boot/dts/loongson/3a2000_780e.dts
> new file mode 100644
> index 000000000000..621e0d3b5fbd
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3a2000_780e.dts
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "3a-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,ls3a2000-780e";
> +};
> diff --git a/arch/mips/boot/dts/loongson/3a3000_780e.dts b/arch/mips/boot/dts/loongson/3a3000_780e.dts
> new file mode 100644
> index 000000000000..f170f1c2189d
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3a3000_780e.dts
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "3a-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,ls3a3000-780e";
> +};
> diff --git a/arch/mips/boot/dts/loongson/3b-package.dtsi b/arch/mips/boot/dts/loongson/3b-package.dtsi
> new file mode 100644
> index 000000000000..af6e115d33c0
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3b-package.dtsi
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + package@0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
> + 0 0x3ff00000 0 0x3ff00000 0x100000
> + 0x1EFD 0xFB000000 0x1EFD 0xFB000000 0x10000000 /* 3B HT Config Space */>;
> +
> + iointc: interrupt-controller@3ff01400 {
> + compatible = "loongson,ls3-iointc";
> + reg = <0 0x3ff01400 0x64>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
> +
> + cpu_uart0: serial@1fe001e0 {
> + device_type = "serial";
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e0 0x8>;
> + clock-frequency = <33000000>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&iointc>;
> + no-loopback-test;
> + };
> +
> + cpu_uart1: serial@1fe001e8 {
> + status = "disabled";
> + device_type = "serial";
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e8 0x8>;
> + clock-frequency = <33000000>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&iointc>;
> + no-loopback-test;
> + };
> +
> + htintc: interrupt-controller@0x1EFDFB000080 {
> + compatible = "loongson,ls3-htintc";
> + reg = <0x1EFD 0xFB000080 0x100>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&iointc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> + <25 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/3b1x00_780e.dts b/arch/mips/boot/dts/loongson/3b1x00_780e.dts
> new file mode 100644
> index 000000000000..9b0dff0b1482
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3b1x00_780e.dts
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "3b-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,ls3b-780e";
> +};
> diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
> new file mode 100644
> index 000000000000..a225d84a521e
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX_License_Identifier: GPL_2.0
> +dtb-$(CONFIG_MACH_LOONGSON64) += 3a1000_780e.dtb 3a2000_780e.dtb 3a3000_780e.dtb 3b1x00_780e.dtb \
> +
> +
> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> new file mode 100644
> index 000000000000..915363eafa2f
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/ {
> + pch {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0x000 0x10000000 0x000 0x10000000 0x10000000
> + 0x000 0x40000000 0x000 0x40000000 0x40000000>;
> +
> + isa {
> + compatible = "isa";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <1 0 0 0 0x1000>;
> +
> + i8259: interrupt-controller@20 {
> + compatible = "intel,i8259";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + plat-poll;
> + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>;
> + interrupt-parent = <&htintc>;
> + };
> +
> + rtc0: rtc@70 {
> + compatible = "motorola,mc146818";
> + reg = <1 0x70 0x8>;
> + interrupts = <8>;
> + interrupt-parent = <&i8259>;
> + };
> + };
> + };
> +};
> --
> 2.22.0
>
On 2019/9/7 上午10:53, Huacai Chen wrote:
> On Thu, Sep 5, 2019 at 10:47 PM Jiaxun Yang <[email protected]> wrote:
>> Add generic device dts for Loongson-3 devices.
>> They seems identical but will be different later.
>>
>> Signed-off-by: Jiaxun Yang <[email protected]>
> Hi, Jiaxun,
>
> I'm very glad to see that dts files become less in this version, but I
> think we also don't need to distinguish cpu types (i.e.,
> 3a1000/3b1500/3a2000/3a3000). Then, we only need three dts files
> (loongson3_ls2h.dts, loongson3_ls7a.dts, loongson3_rs780.dts) which is
> the same as in our own git repository. If we really need to
> distinguish cpu type, PRID or CPUCFG in Loongson-3A4000 is more
> suitable than dts. In other words, I want dts only do as minimal as
> possible.
Hi Huacai,
I have the same consideration with you. However, the reason why I split
this dts is that these chips have significant differences.
For example, 3B1x00 have different memory and config registers layout,
Their HT config space is a delicate node, HTMSI interrupts is not
functional until 3A3000, and their syscon registers are not identical.
You may say they can be identified by PRID, but I'm not intend to spread
PRID all the way in other subsystems, thus I think dts is still the best
way to tell these differences.
Thanks
--
Jiaxun Yang
>
> Huacai
>
On Tue, Aug 27, 2019 at 1:53 AM Jiaxun Yang <[email protected]> wrote:
> Loongson have a long history of contributing their code to mainline kernel.
> However, it seems like recent years, they are focusing on maintain a kernel by themselves
> rather than contribute there code to the community.
Do you know more about this? I have a Loongson 3A3000 system that I
have never been able to make stable. I tried pulling patches out of
the glibc, binutils, gcc, and Linux repos I found at
https://github.com/loongson-community but my system still hardlocks,
preventing me from doing much of anything with it.
Do we know why critical looking toolchain patches like "Added misses
sync in mips_process_sync_loop for add sync before ll sc" [0] and "Fix
loads for Loongson3 to promoting stability" [1] have not been
submitted upstream?
I'm interested in supporting Loongson 3 in Gentoo, and the hardware
that has been given to me would be extremely useful for Gentoo's MIPS
port in general, but it's just not usable at all currently.
[0] https://github.com/loongson-community/gcc/commit/e7e3b0f956929f022caa01ed25a482495b11d575
[1] https://github.com/loongson-community/binutils-gdb/commit/2f0e91d2af6093097202fae3adab624ffa86a156
14:30, 2019年9月12日, Matt Turner <[email protected]>:
On Tue, Aug 27, 2019 at 1:53 AM Jiaxun Yang <[email protected]
<mailto:[email protected]>> wrote:
Loongson have a long history of contributing their code to
mainline kernel.
However, it seems like recent years, they are focusing on
maintain a kernel by themselves
rather than contribute there code to the community.
Hi Matt:
Do you know more about this? I have a Loongson 3A3000 system that I
have never been able to make stable. I tried pulling patches out of
the glibc, binutils, gcc, and Linux repos I found at
https://github.com/loongson-community but my system still hardlocks,
What's the behaviour of hardlock? Kernel RCU stall? Or simply no response?
preventing me from doing much of anything with it.
Do we know why critical looking toolchain patches like "Added misses
sync in mips_process_sync_loop for add sync before ll sc" [0] and "Fix
LLSC fixes have been mainlined in latest binutils.
And GCC-9.1 have introduced march=gs464e for 3A3000.
loads for Loongson3 to promoting stability" [1] have not been
submitted upstream?
Load issue only influence specified revisions of Loongson-3A2000, your
hardware shouldn't have that problem.
I'm interested in supporting Loongson 3 in Gentoo, and the hardware
that has been given to me would be extremely useful for Gentoo's MIPS
port in general, but it's just not usable at all currently.
You can try Fedora 28 maintained by Lemote which have been verified in
production environment for a period
[http://mirror.lemote.com:8000/fedora/fedora28-live/] if the hardware is
still unstable, then it might be a memory stability issue. You can try
to clean your DIMM solt and DDR golden finger, or even swap the memory
module.
Btw: Xuerui Wang <[email protected]> had maintained his 3A3000 Gentoo
port [https://github.com/xen0n/loongson-overlay] for a long time. I'll
Cc him this email and probability he can give you further assistance.
Thanks.
[0]
https://github.com/longson-community/gcc/commit/e7e3b0f956929f022caa01ed25a482495b11d575
<https://github.com/loongson-community/gcc/commit/e7e3b0f956929f022caa01ed25a482495b11d575>
[1]
https://github.com/loongson-community/binutils-gdb/commit/2f0e91d2af6093097202fae3adab624ffa86a156
--
Jiaxun Yang
On Thu, 5 Sep 2019 22:43:03 +0800, Jiaxun Yang wrote:
> Document Loongson-3 I/O Interrupt controller.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> .../loongson,ls3-iointc.yaml | 79 +++++++++++++++++++
> 1 file changed, 79 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On Thu, Sep 05, 2019 at 10:43:11PM +0800, Jiaxun Yang wrote:
> Add generic device dts for Loongson-3 devices.
> They seems identical but will be different later.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> arch/mips/Kconfig | 4 +-
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/loongson/3a-package.dtsi | 69 +++++++++++++++++++++
> arch/mips/boot/dts/loongson/3a1000_780e.dts | 10 +++
> arch/mips/boot/dts/loongson/3a2000_780e.dts | 10 +++
> arch/mips/boot/dts/loongson/3a3000_780e.dts | 10 +++
> arch/mips/boot/dts/loongson/3b-package.dtsi | 69 +++++++++++++++++++++
> arch/mips/boot/dts/loongson/3b1x00_780e.dts | 10 +++
> arch/mips/boot/dts/loongson/Makefile | 5 ++
> arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 35 +++++++++++
> 10 files changed, 222 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/boot/dts/loongson/3a-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/3a1000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3a2000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3a3000_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/3b-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/3b1x00_780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/Makefile
> create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index b6bdd96ec74e..5bad9aafcbdf 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -489,6 +489,8 @@ config MACH_LOONGSON64
> select SYS_SUPPORTS_LITTLE_ENDIAN
> select ZONE_DMA32
> select SYS_SUPPORTS_ZBOOT
> + select USE_OF
> + select BUILTIN_DTB
> help
> This enables the support of Loongson-3A/3B/2-series-soc processors
>
> @@ -3047,7 +3049,7 @@ endchoice
> choice
> prompt "Kernel command line type" if !CMDLINE_OVERRIDE
> default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
> - !MIPS_MALTA && \
> + !MACH_LOONGSON64 && !MIPS_MALTA && \
> !CAVIUM_OCTEON_SOC
> default MIPS_CMDLINE_FROM_BOOTLOADER
>
> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> index 1e79cab8e269..d429a69bfe30 100644
> --- a/arch/mips/boot/dts/Makefile
> +++ b/arch/mips/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += cavium-octeon
> subdir-y += img
> subdir-y += ingenic
> subdir-y += lantiq
> +subdir-y += loongson
> subdir-y += mscc
> subdir-y += mti
> subdir-y += netlogic
> diff --git a/arch/mips/boot/dts/loongson/3a-package.dtsi b/arch/mips/boot/dts/loongson/3a-package.dtsi
> new file mode 100644
> index 000000000000..739cf43c7310
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3a-package.dtsi
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + package@0 {
bus@1fe00000
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
> + 0 0x3ff00000 0 0x3ff00000 0x100000
> + 0xEFD 0xFB000000 0xEFD 0xFB000000 0x10000000 /* 3A HT Config Space */>;
Lowercase hex please.
> +
> + iointc: interrupt-controller@3ff01400 {
> + compatible = "loongson,ls3-iointc";
> + reg = <0 0x3ff01400 0x64>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
Too much indentation.
> +
> + cpu_uart0: serial@1fe001e0 {
> + device_type = "serial";
Drop device_type. It's deprecated for everything but cpu, memory, and
pci.
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e0 0x8>;
> + clock-frequency = <33000000>;
> + interrupt-parent = <&iointc>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + no-loopback-test;
> + };
> +
> + cpu_uart1: serial@1fe001e8 {
> + status = "disabled";
> + device_type = "serial";
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e8 0x8>;
> + clock-frequency = <33000000>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&iointc>;
> + no-loopback-test;
> + };
> +
> + htintc: interrupt-controller@0xEFDFB000080 {
Drop '0x' and lowercase. Building with 'W=12' will tell you this. Do
that, and fix the warnings.
> + compatible = "loongson,ls3-htintc";
> + reg = <0xEFD 0xFB000080 0x100>;
lowercase
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&iointc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> + <25 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/3a1000_780e.dts b/arch/mips/boot/dts/loongson/3a1000_780e.dts
> new file mode 100644
> index 000000000000..dc1afe9410c8
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3a1000_780e.dts
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "3a-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,ls3a1000-780e";
> +};
> diff --git a/arch/mips/boot/dts/loongson/3a2000_780e.dts b/arch/mips/boot/dts/loongson/3a2000_780e.dts
> new file mode 100644
> index 000000000000..621e0d3b5fbd
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3a2000_780e.dts
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "3a-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,ls3a2000-780e";
> +};
> diff --git a/arch/mips/boot/dts/loongson/3a3000_780e.dts b/arch/mips/boot/dts/loongson/3a3000_780e.dts
> new file mode 100644
> index 000000000000..f170f1c2189d
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3a3000_780e.dts
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "3a-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,ls3a3000-780e";
> +};
> diff --git a/arch/mips/boot/dts/loongson/3b-package.dtsi b/arch/mips/boot/dts/loongson/3b-package.dtsi
> new file mode 100644
> index 000000000000..af6e115d33c0
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3b-package.dtsi
Same comments apply to this file.
Looks like this one is pretty similar to 3a-package.dtsi. Can't you
share more?
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + package@0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
> + 0 0x3ff00000 0 0x3ff00000 0x100000
> + 0x1EFD 0xFB000000 0x1EFD 0xFB000000 0x10000000 /* 3B HT Config Space */>;
> +
> + iointc: interrupt-controller@3ff01400 {
> + compatible = "loongson,ls3-iointc";
> + reg = <0 0x3ff01400 0x64>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
> +
> + cpu_uart0: serial@1fe001e0 {
> + device_type = "serial";
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e0 0x8>;
> + clock-frequency = <33000000>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&iointc>;
> + no-loopback-test;
> + };
> +
> + cpu_uart1: serial@1fe001e8 {
> + status = "disabled";
> + device_type = "serial";
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e8 0x8>;
> + clock-frequency = <33000000>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&iointc>;
> + no-loopback-test;
> + };
> +
> + htintc: interrupt-controller@0x1EFDFB000080 {
> + compatible = "loongson,ls3-htintc";
> + reg = <0x1EFD 0xFB000080 0x100>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&iointc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> + <25 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/3b1x00_780e.dts b/arch/mips/boot/dts/loongson/3b1x00_780e.dts
> new file mode 100644
> index 000000000000..9b0dff0b1482
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/3b1x00_780e.dts
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "3b-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,ls3b-780e";
> +};
> diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
> new file mode 100644
> index 000000000000..a225d84a521e
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX_License_Identifier: GPL_2.0
> +dtb-$(CONFIG_MACH_LOONGSON64) += 3a1000_780e.dtb 3a2000_780e.dtb 3a3000_780e.dtb 3b1x00_780e.dtb \
> +
> +
> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> new file mode 100644
> index 000000000000..915363eafa2f
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/ {
> + pch {
bus@10000000
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0x000 0x10000000 0x000 0x10000000 0x10000000
> + 0x000 0x40000000 0x000 0x40000000 0x40000000>;
> +
> + isa {
This doesn't seem like it would be an accurate representation of the
h/w. I'd expect this would be behind a PCI bridge for example? How do
you identify a RS780E chip? Using the top level compatible is not the
right way to do it.
> + compatible = "isa";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <1 0 0 0 0x1000>;
> +
> + i8259: interrupt-controller@20 {
> + compatible = "intel,i8259";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + plat-poll;
> + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
> + <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>;
> + interrupt-parent = <&htintc>;
> + };
> +
> + rtc0: rtc@70 {
> + compatible = "motorola,mc146818";
> + reg = <1 0x70 0x8>;
> + interrupts = <8>;
> + interrupt-parent = <&i8259>;
> + };
> + };
> + };
> +};
> --
> 2.22.0
>
On Thu, Sep 05, 2019 at 10:43:09PM +0800, Jiaxun Yang wrote:
> Prepare for later dts.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> .../bindings/mips/loongson/devices.yaml | 39 +++++++++++++++++++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
>
> diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> new file mode 100644
> index 000000000000..0665f0f7ec45
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> @@ -0,0 +1,39 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson based Platforms Device Tree Bindings
> +
> +maintainers:
> + - Jiaxun Yang <[email protected]>
> +description: |
> + Devices with a Loongson CPU shall have the following properties.
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> +
> + - description: Loongson 3A1000 + RS780E
> + items:
> + - const: loongson,ls3a1000-780e
These should reflect the specific maker and model of board, not just
what's the cpu and south bridge.
> +
> + - description: Loongson 3A2000 + RS780E
> + items:
> + - const: loongson,ls3a2000-780e
> +
> + - description: Loongson 3A3000 + RS780E
> + items:
> + - const: loongson,ls3a3000-780e
> +
> + - description: Loongson 3A3000 + 7A
> + items:
> + - const: loongson,ls3a3000-7a
> +
> + - description: Loongson 3B1000/1500 + RS780E 2Way
> + items:
> + - const: loongson,ls3b1x00-780e
> +...
> --
> 2.22.0
>
Loongson have a long history of contributing their code to mainline kernel.
However, it seems like recent years, they are focusing on maintain a kernel by themselves
rather than contribute there code to the community.
Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
maintainance and became outdated.
This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
Loongson 2e/f alone since they are too legacy to touch.
PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
v1:
- dt-bindings fixup according to Rob's comments
- irqchip fixup according to Marc's comments
- ls3-iointc: Make Core&IP map per-IRQ
- Regenerate kconfigs
- Typo & style improvements
v2:
- dt-bindings: Fix IOINTC, collect Rob's review tag
- dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
v3:
- Split code have been merged
- Fix IOINTC binding to allow map any child IRQ to and parent
- Convert "HTINTC" into "HTPIC", which mixed HT vectors processing and i8259
- Naming style fix according to Huacai's suggestions
Jiaxun Yang (10):
dt-bindings: Document loongson vendor-prefix
irqchip: Add driver for Loongson I/O interrupt controller
dt-bindings: interrupt-controller: Add Loongson IOINTC
irqchip: Add driver for Loongson-3 HyperTransport PIC controller
dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson boards
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
.../interrupt-controller/loongson,htpic.yaml | 59 +++
.../interrupt-controller/loongson,iointc.yaml | 92 +++++
.../bindings/mips/loongson/devices.yaml | 29 ++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 5 +
.../boot/dts/loongson/loongson3-package.dtsi | 62 ++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++
arch/mips/include/asm/i8259.h | 1 +
.../include/asm/mach-loongson64/boot_param.h | 2 +
.../asm/mach-loongson64/builtin_dtbs.h | 13 +
arch/mips/include/asm/mach-loongson64/irq.h | 32 +-
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/env.c | 23 ++
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 ---------
arch/mips/loongson64/setup.c | 16 +
arch/mips/loongson64/smp.c | 28 +-
drivers/irqchip/Kconfig | 18 +
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-i8259.c | 6 +-
drivers/irqchip/irq-loongson-htpic.c | 147 ++++++++
drivers/irqchip/irq-loongson-iointc.c | 338 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
28 files changed, 915 insertions(+), 216 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/loongson64/irq.c
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
create mode 100644 drivers/irqchip/irq-loongson-iointc.c
--
2.24.1
Document Loongson-3 HyperTransport PIC controller.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../interrupt-controller/loongson,htpic.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
new file mode 100644
index 000000000000..efcc3f43e45b
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 HyperTransport Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips to transfer
+ interrupts from PCH PIC connected on HyperTransport bus.
+
+properties:
+ compatible:
+ const: loongson,htpic-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ description: |
+ Four parent interrupts that recieve chained interrupts.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ htintc: interrupt-controller@1fb000080 {
+ compatible = "loongson,htintc-1.0";
+ reg = <0x1fb000080 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&iointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.24.1
Loongson is a MIPS-compatible processor vendor.
Signed-off-by: Jiaxun Yang <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 50c2b635ecfd..31b364107e60 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -545,6 +545,8 @@ patternProperties:
description: Logic PD, Inc.
"^longcheer,.*":
description: Longcheer Technology (Shanghai) Co., Ltd.
+ "^loongson,.*":
+ description: Loongson Technology Corporation Limited
"^lsi,.*":
description: LSI Corp. (LSI Logic)
"^lwn,.*":
--
2.24.1
Document Loongson I/O Interrupt controller.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../interrupt-controller/loongson,iointc.yaml | 92 +++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
new file mode 100644
index 000000000000..b0fe6c551362
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,iointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt source which can route interrupt to interrupt line of cores.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,iointc-1.0
+ - const: loongson,iointc-1.0a
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ description:
+ Interrupt source of the CPU interrupts.
+ minItems: 1
+ maxItems: 4
+
+ interrupt-names:
+ description: List of names for the parent interrupts.
+ oneOf:
+ - items:
+ - const: int0
+ - const: int1
+ - const: int2
+ - const: int3
+ minItems: 1
+ maxItems: 4
+
+ '#interrupt-cells':
+ const: 2
+
+ 'loongson,parent_int_map':
+ description: |
+ This property points the accept range of children interrupts
+ that parents will recieve. Each cell refers to a parent interrupt line
+ and each bit in the cell refers to a children interrupt. If a parent
+ did not connected, than keep it's cell with zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - items:
+ minItems: 4
+ maxItems: 4
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - 'loongson,parent_int_map'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,iointc-1.0";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+...
--
2.24.1
This controller appeared on Loongson-3 family of chips to receive interrupts
from PCH PIC.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/i8259.h | 1 +
drivers/irqchip/Kconfig | 9 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-i8259.c | 6 +-
drivers/irqchip/irq-loongson-htpic.c | 147 +++++++++++++++++++++++++++
5 files changed, 161 insertions(+), 3 deletions(-)
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index 97a5e41ed1ab..1ec3dbb1588f 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -36,6 +36,7 @@ extern raw_spinlock_t i8259A_lock;
extern void make_8259A_irq(unsigned int irq);
extern void init_i8259_irqs(void);
+extern struct irq_domain *of_init_i8259_irqs(struct device_node *node);
/**
* i8159_set_poll() - Override the i8259 polling function
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3f220648151b..2d9fadb1b5d5 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -508,4 +508,13 @@ config LOONGSON_IOINTC
help
Support for the Loongson I/O Interrupt Controller.
+config LOONGSON_HTPIC
+ bool "Loongson3 HyperTransport PIC Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ select I8259
+ help
+ Support for the Loongson-3 HyperTransport PIC Controller.
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 3e98241401b3..96ed00da097d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -105,3 +105,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_LOONGSON_IOINTC) += irq-loongson-iointc.o
+obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index d000870d9b6b..9d79acce6c0c 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -309,7 +309,7 @@ static const struct irq_domain_ops i8259A_ops = {
* driver compatibility reasons interrupts 0 - 15 to be the i8259
* interrupts even if the hardware uses a different interrupt numbering.
*/
-struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
+struct irq_domain * __init of_init_i8259_irqs(struct device_node *node)
{
struct irq_domain *domain;
@@ -330,7 +330,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
void __init init_i8259_irqs(void)
{
- __init_i8259_irqs(NULL);
+ of_init_i8259_irqs(NULL);
}
static void i8259_irq_dispatch(struct irq_desc *desc)
@@ -351,7 +351,7 @@ int __init i8259_of_init(struct device_node *node, struct device_node *parent)
struct irq_domain *domain;
unsigned int parent_irq;
- domain = __init_i8259_irqs(node);
+ domain = of_init_i8259_irqs(node);
parent_irq = irq_of_parse_and_map(node, 0);
if (!parent_irq) {
diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c
new file mode 100644
index 000000000000..fa33176157d6
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-htpic.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <[email protected]>
+ * Loongson HTPIC IRQ support
+ */
+
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <asm/i8259.h>
+
+#define HTPIC_MAX_PARENT_IRQ 4
+#define HTINT_NUM_VECTORS 8
+#define HTINT_EN_OFF 0x20
+
+struct loongson_htpic {
+ void __iomem *base;
+ struct irq_domain *domain;
+};
+
+struct loongson_htpic *htpic;
+
+static void htpic_irq_dispatch(struct irq_desc *desc)
+{
+ struct loongson_htpic *priv = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ uint32_t pending;
+
+ chained_irq_enter(chip, desc);
+ pending = readl(priv->base);
+ /* Ack all irqs */
+ writel(pending, priv->base);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ if (unlikely(bit > 15))
+ spurious_interrupt();
+
+ generic_handle_irq(irq_linear_revmap(priv->domain, bit));
+ pending &= ~BIT(bit);
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static void htpic_reg_init(void)
+{
+ int i;
+
+ for (i = 0; i < HTINT_NUM_VECTORS; i++) {
+ uint32_t val;
+
+ /* Disable all HT Vectors */
+ writel(0x0, htpic->base + HTINT_EN_OFF + i * 0x4);
+ val = readl(htpic->base + i * 0x4);
+ /* Ack all possible pending IRQs */
+ writel(GENMASK(31, 0), htpic->base + i * 0x4);
+ }
+
+ /* Enable 16 vectors for PIC */
+ writel(0xffff, htpic->base + HTINT_EN_OFF);
+}
+
+static void htpic_resume(void)
+{
+ htpic_reg_init();
+}
+
+struct syscore_ops htpic_syscore_ops = {
+ .resume = htpic_resume,
+};
+
+int __init htpic_of_init(struct device_node *node, struct device_node *parent)
+{
+ unsigned int parent_irq[4];
+ int i, err;
+ int num_parents = 0;
+
+ if (htpic) {
+ pr_err("loongson-htpic: Only one htpic is allowed in the system\n");
+ return -ENODEV;
+ }
+
+ htpic = kzalloc(sizeof(*htpic), GFP_KERNEL);
+ if (!htpic) {
+ err = -ENOMEM;
+ goto out_free;
+ }
+
+ htpic->base = of_iomap(node, 0);
+ if (!htpic->base) {
+ pr_err("loongson-htpic: Failed to map io\n");
+ err = -ENODEV;
+ goto out_free;
+ }
+
+ htpic->domain = of_init_i8259_irqs(node);
+ if (!htpic->domain) {
+ pr_err("loongson-htpic: Failed to initialize i8259 irqs\n");
+ err = -ENOMEM;
+ goto out_iounmap;
+ }
+
+ for (i = 0; i < HTPIC_MAX_PARENT_IRQ; i++) {
+ parent_irq[i] = irq_of_parse_and_map(node, 0);
+ if (parent_irq[i] < 0)
+ break;
+
+ num_parents++;
+ }
+
+ if (!num_parents) {
+ pr_err("loongson-htpic: Failed to get parent irqs\n");
+ err = -ENODEV;
+ goto out_remove_domain;
+ }
+
+ htpic_reg_init();
+
+ for (i = 0; i < num_parents; i++) {
+ irq_set_chained_handler_and_data(parent_irq[i],
+ htpic_irq_dispatch, htpic);
+ }
+
+ register_syscore_ops(&htpic_syscore_ops);
+
+ return 0;
+
+out_remove_domain:
+ irq_domain_remove(htpic->domain);
+out_iounmap:
+ iounmap(htpic->base);
+out_free:
+ kfree(htpic);
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_htpic, "loongson,htpic-1.0", htpic_of_init);
--
2.24.1
Add generic device dts for Loongson-3 devices.
They seems identical but will be different later.
Some PCH devices like PCI Host Bridge is still enabled by platform
code for now.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 5 ++
.../boot/dts/loongson/loongson3-package.dtsi | 62 +++++++++++++++++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++
arch/mips/include/asm/mach-loongson64/irq.h | 3 +-
8 files changed, 150 insertions(+), 3 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4b83507499f4..47909e733c2d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -489,9 +489,11 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
- select LOONGSON_MC146818
select ZONE_DMA32
select NUMA
+ select COMMON_CLK
+ select USE_OF
+ select BUILTIN_DTB
help
This enables the support of Loongson-2/3 family of machines.
@@ -3085,7 +3087,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && \
+ !MACH_LOONGSON64 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..d429a69bfe30 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
+subdir-y += loongson
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000000..c0cedbaa9a78
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,5 @@
+# SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb\
+
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
new file mode 100644
index 000000000000..8a8d8c442dfe
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package0: bus@1fe00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 /* 3A HT Config Space */
+ 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000 /* 3B HT Config Space */>;
+
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,iointc-1.0";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupt-parent = <&iointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&iointc>;
+ no-loopback-test;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
new file mode 100644
index 000000000000..ef50ed9a4d59
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-4core-780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&iointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
new file mode 100644
index 000000000000..409473f1751b
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-8core-780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@1efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0x1efd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&iointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
new file mode 100644
index 000000000000..45c54d555fa4
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x10000000 0 0x10000000 0 0x10000000
+ 0 0x40000000 0 0x40000000 0 0x40000000
+ 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
+
+ isa {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0 0x1000>;
+
+ rtc0: rtc@70 {
+ compatible = "motorola,mc146818";
+ reg = <1 0x70 0x8>;
+ interrupts = <8>;
+ interrupt-parent = <&htpic>;
+ };
+ };
+ };
+};
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 12208119aac0..20e3d4e67788 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -4,8 +4,9 @@
#include <boot_param.h>
+#define NR_IRQS 512
/* cpu core interrupt numbers */
-#define MIPS_CPU_IRQ_BASE 56
+#define MIPS_CPU_IRQ_BASE 16
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
--
2.24.1
We've made generic irqchip drivers for Loongson-3 platform, it's time
to say goodbye to these legacy code.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../include/asm/mach-loongson64/boot_param.h | 2 +
arch/mips/include/asm/mach-loongson64/irq.h | 29 ----
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 ------------------
arch/mips/loongson64/smp.c | 28 ++-
6 files changed, 20 insertions(+), 209 deletions(-)
delete mode 100644 arch/mips/loongson64/irq.c
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index 8c286bedff3e..2ed483e32d8c 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -2,6 +2,8 @@
#ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
#define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
+#include <linux/types.h>
+
#define SYSTEM_RAM_LOW 1
#define SYSTEM_RAM_HIGH 2
#define SYSTEM_RAM_RESERVED 3
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 73a89913dc38..12208119aac0 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -7,34 +7,5 @@
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
-#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
-#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
-#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
-
-#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
-#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80)
-#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0)
-#define LOONGSON_HT1_INT_VECTOR(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
-#define LOONGSON_HT1_INTN_EN(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
-
-#define LOONGSON_INT_ROUTER_OFFSET 0x1400
-#define LOONGSON_INT_ROUTER_INTEN \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
-#define LOONGSON_INT_ROUTER_INTENSET \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
-#define LOONGSON_INT_ROUTER_INTENCLR \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
-#define LOONGSON_INT_ROUTER_ENTRY(n) \
- LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
-#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
-#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
-
-#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
-
-extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(struct pt_regs *regs);
-
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 7821891bc5d0..b7f40b179c71 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -2,7 +2,7 @@
#
# Makefile for Loongson-3 family machines
#
-obj-$(CONFIG_MACH_LOONGSON64) += irq.o cop2-ex.o platform.o acpi_init.o dma.o \
+obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \
setup.o init.o env.o time.o reset.o \
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index 5ac1a0f35ca4..da38944471f4 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -4,6 +4,7 @@
* Author: Wu Zhangjin, [email protected]
*/
+#include <linux/irqchip.h>
#include <linux/memblock.h>
#include <asm/bootinfo.h>
#include <asm/traps.h>
@@ -44,3 +45,8 @@ void __init prom_init(void)
void __init prom_free_prom_memory(void)
{
}
+
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c
deleted file mode 100644
index 79ad797497e4..000000000000
--- a/arch/mips/loongson64/irq.c
+++ /dev/null
@@ -1,162 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <loongson.h>
-#include <irq.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/i8259.h>
-#include <asm/mipsregs.h>
-
-#include "smp.h"
-
-extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
-
-unsigned int irq_cpu[16] = {[0 ... 15] = -1};
-unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
-unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
-
-int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
- bool force)
-{
- unsigned int cpu;
- struct cpumask new_affinity;
-
- /* I/O devices are connected on package-0 */
- cpumask_copy(&new_affinity, affinity);
- for_each_cpu(cpu, affinity)
- if (cpu_data[cpu].package > 0)
- cpumask_clear_cpu(cpu, &new_affinity);
-
- if (cpumask_empty(&new_affinity))
- return -EINVAL;
-
- cpumask_copy(d->common->affinity, &new_affinity);
-
- return IRQ_SET_MASK_OK_NOCOPY;
-}
-
-static void ht_irqdispatch(void)
-{
- unsigned int i, irq;
- struct irq_data *irqd;
- struct cpumask affinity;
-
- irq = LOONGSON_HT1_INT_VECTOR(0);
- LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
-
- for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
- if (!(irq & (0x1 << ht_irq[i])))
- continue;
-
- /* handled by local core */
- if (local_irq & (0x1 << ht_irq[i])) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irqd = irq_get_irq_data(ht_irq[i]);
- cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
- if (cpumask_empty(&affinity)) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
- if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
- irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
-
- if (irq_cpu[ht_irq[i]] == 0) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- /* balanced by other cores */
- loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
- }
-}
-
-#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & CAUSEF_IP7)
- do_IRQ(LOONGSON_TIMER_IRQ);
-#if defined(CONFIG_SMP)
- if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt(NULL);
-#endif
- if (pending & CAUSEF_IP3)
- ht_irqdispatch();
- if (pending & CAUSEF_IP2)
- do_IRQ(LOONGSON_UART_IRQ);
- if (pending & UNUSED_IPS) {
- pr_err("%s : spurious interrupt\n", __func__);
- spurious_interrupt();
- }
-}
-
-static inline void mask_loongson_irq(struct irq_data *d) { }
-static inline void unmask_loongson_irq(struct irq_data *d) { }
-
- /* For MIPS IRQs which shared by all cores */
-static struct irq_chip loongson_irq_chip = {
- .name = "Loongson",
- .irq_ack = mask_loongson_irq,
- .irq_mask = mask_loongson_irq,
- .irq_mask_ack = mask_loongson_irq,
- .irq_unmask = unmask_loongson_irq,
- .irq_eoi = unmask_loongson_irq,
-};
-
-void irq_router_init(void)
-{
- int i;
-
- /* route LPC int to cpu core0 int 0 */
- LOONGSON_INT_ROUTER_LPC =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
- /* route HT1 int0 ~ int7 to cpu core0 INT1*/
- for (i = 0; i < 8; i++)
- LOONGSON_INT_ROUTER_HT1(i) =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
- /* enable HT1 interrupt */
- LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
- /* enable router interrupt intenset */
- LOONGSON_INT_ROUTER_INTENSET =
- LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
-}
-
-void __init arch_init_irq(void)
-{
- struct irq_chip *chip;
-
- clear_c0_status(ST0_IM | ST0_BEV);
-
- irq_router_init();
- mips_cpu_irq_init();
- init_i8259_irqs();
- chip = irq_get_chip(I8259A_IRQ_BASE);
- chip->irq_set_affinity = plat_set_irq_affinity;
-
- irq_set_chip_and_handler(LOONGSON_UART_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
- irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
-
- set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-
-void fixup_irqs(void)
-{
- irq_cpu_offline();
- clear_c0_status(ST0_IM);
-}
-
-#endif
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index de8e0741ce2d..e1fe8bbb377d 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -4,6 +4,7 @@
* Author: Chen Huacai, [email protected]
*/
+#include <irq.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/sched.h>
@@ -25,6 +26,8 @@
DEFINE_PER_CPU(int, cpu_state);
+#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
+
static void *ipi_set0_regs[16];
static void *ipi_clear0_regs[16];
static void *ipi_status0_regs[16];
@@ -302,20 +305,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
ipi_write_action(cpu_logical_map(i), (u32)action);
}
-#define IPI_IRQ_OFFSET 6
-
-void loongson3_send_irq_by_ipi(int cpu, int irqs)
-{
- ipi_write_action(cpu_logical_map(cpu), irqs << IPI_IRQ_OFFSET);
-}
-void loongson3_ipi_interrupt(struct pt_regs *regs)
+static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
{
int i, cpu = smp_processor_id();
- unsigned int action, c0count, irqs;
+ unsigned int action, c0count;
action = ipi_read_clear(cpu);
- irqs = action >> IPI_IRQ_OFFSET;
if (action & SMP_RESCHEDULE_YOURSELF)
scheduler_ipi();
@@ -335,13 +331,7 @@ void loongson3_ipi_interrupt(struct pt_regs *regs)
__wbflush(); /* Let others see the result ASAP */
}
- if (irqs) {
- int irq;
- while ((irq = ffs(irqs))) {
- do_IRQ(irq-1);
- irqs &= ~(1<<(irq-1));
- }
- }
+ return IRQ_HANDLED;
}
#define MAX_LOOPS 800
@@ -438,6 +428,9 @@ static void __init loongson3_smp_setup(void)
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
{
+ if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
+ pr_err("Failed to request IPI IRQ\n");
init_cpu_present(cpu_possible_mask);
per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
}
@@ -484,7 +477,8 @@ static int loongson3_cpu_disable(void)
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
local_irq_save(flags);
- fixup_irqs();
+ irq_cpu_offline();
+ clear_c0_status(ST0_IM);
local_irq_restore(flags);
local_flush_tlb_all();
--
2.24.1
The old code is using legacy domain to setup irq_domain for CPU interrupts
which requires irq_desc being preallocated.
However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up
unallocated and lead to incorrect behavior.
Thus we convert the legacy domain to simple domain which can allocate irq_desc
during initialization.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..c3cf7fa76424 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+ irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
&mips_cpu_intc_irq_domain_ops,
NULL);
if (!irq_domain)
--
2.24.1
Load proper dtb according to firmware passed parameters and
CPU PRID.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../asm/mach-loongson64/builtin_dtbs.h | 13 +++++++++++
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/env.c | 23 +++++++++++++++++++
arch/mips/loongson64/setup.c | 16 +++++++++++++
4 files changed, 53 insertions(+)
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
new file mode 100644
index 000000000000..853c6d80887b
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Built-in Generic dtbs for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+
+extern u32 __dtb_loongson3_4core_rs780e_begin[];
+extern u32 __dtb_loongson3_8core_rs780e_begin[];
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index a8fce112a9b0..fde1b75c45ea 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -25,6 +25,7 @@ extern const struct plat_smp_ops loongson3_smp_ops;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
extern void __init prom_init_env(void);
+extern void *loongson_fdt_blob;
/* irq operation functions */
extern void mach_irq_dispatch(unsigned int pending);
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 0daeb7bcf023..2554ef11170d 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -17,6 +17,7 @@
#include <asm/bootinfo.h>
#include <loongson.h>
#include <boot_param.h>
+#include <builtin_dtbs.h>
#include <workarounds.h>
u32 cpu_clock_freq;
@@ -120,6 +121,28 @@ void __init prom_init_env(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
+ break;
+ default:
+ break;
+ }
+ }
+
+
+ if (!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
+
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
index 4fd27f4f90ed..6fe3ffffcaa6 100644
--- a/arch/mips/loongson64/setup.c
+++ b/arch/mips/loongson64/setup.c
@@ -8,9 +8,15 @@
#include <asm/wbflush.h>
#include <asm/bootinfo.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
#include <loongson.h>
+void *loongson_fdt_blob;
+
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
@@ -27,4 +33,14 @@ EXPORT_SYMBOL(__wbflush);
void __init plat_mem_setup(void)
{
+ if (loongson_fdt_blob)
+ __dt_setup_arch(loongson_fdt_blob);
+}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
}
--
2.24.1
Hi, Jiaxun,
On Sun, Jan 12, 2020 at 4:21 PM Jiaxun Yang <[email protected]> wrote:
>
> Loongson have a long history of contributing their code to mainline kernel.
> However, it seems like recent years, they are focusing on maintain a kernel by themselves
> rather than contribute there code to the community.
>
> Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
> maintainance and became outdated.
>
> This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
> Loongson 2e/f alone since they are too legacy to touch.
I think you can provide a irqchip hierarchy for Loongson3 here. i.e.,
the flowchart of cpuintc, iointc, htpic, i8259, and so on.
Huacai
>
> PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
>
> v1:
> - dt-bindings fixup according to Rob's comments
> - irqchip fixup according to Marc's comments
> - ls3-iointc: Make Core&IP map per-IRQ
> - Regenerate kconfigs
> - Typo & style improvements
>
> v2:
> - dt-bindings: Fix IOINTC, collect Rob's review tag
> - dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
>
> v3:
> - Split code have been merged
> - Fix IOINTC binding to allow map any child IRQ to and parent
> - Convert "HTINTC" into "HTPIC", which mixed HT vectors processing and i8259
> - Naming style fix according to Huacai's suggestions
>
> Jiaxun Yang (10):
> dt-bindings: Document loongson vendor-prefix
> irqchip: Add driver for Loongson I/O interrupt controller
> dt-bindings: interrupt-controller: Add Loongson IOINTC
> irqchip: Add driver for Loongson-3 HyperTransport PIC controller
> dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
> irqchip: mips-cpu: Convert to simple domain
> MIPS: Loongson64: Drop legacy IRQ code
> dt-bindings: mips: Add loongson boards
> MIPS: Loongson64: Add generic dts
> MIPS: Loongson64: Load built-in dtbs
>
> .../interrupt-controller/loongson,htpic.yaml | 59 +++
> .../interrupt-controller/loongson,iointc.yaml | 92 +++++
> .../bindings/mips/loongson/devices.yaml | 29 ++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> arch/mips/Kconfig | 6 +-
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/loongson/Makefile | 5 +
> .../boot/dts/loongson/loongson3-package.dtsi | 62 ++++
> .../dts/loongson/loongson3_4core_rs780e.dts | 25 ++
> .../dts/loongson/loongson3_8core_rs780e.dts | 25 ++
> arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++
> arch/mips/include/asm/i8259.h | 1 +
> .../include/asm/mach-loongson64/boot_param.h | 2 +
> .../asm/mach-loongson64/builtin_dtbs.h | 13 +
> arch/mips/include/asm/mach-loongson64/irq.h | 32 +-
> .../include/asm/mach-loongson64/loongson.h | 1 +
> arch/mips/loongson64/Makefile | 2 +-
> arch/mips/loongson64/env.c | 23 ++
> arch/mips/loongson64/init.c | 6 +
> arch/mips/loongson64/irq.c | 162 ---------
> arch/mips/loongson64/setup.c | 16 +
> arch/mips/loongson64/smp.c | 28 +-
> drivers/irqchip/Kconfig | 18 +
> drivers/irqchip/Makefile | 2 +
> drivers/irqchip/irq-i8259.c | 6 +-
> drivers/irqchip/irq-loongson-htpic.c | 147 ++++++++
> drivers/irqchip/irq-loongson-iointc.c | 338 ++++++++++++++++++
> drivers/irqchip/irq-mips-cpu.c | 2 +-
> 28 files changed, 915 insertions(+), 216 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
> create mode 100644 arch/mips/boot/dts/loongson/Makefile
> create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
> delete mode 100644 arch/mips/loongson64/irq.c
> create mode 100644 drivers/irqchip/irq-loongson-htpic.c
> create mode 100644 drivers/irqchip/irq-loongson-iointc.c
>
> --
> 2.24.1
>
Hi, Jiaxun,
On Sun, Jan 12, 2020 at 4:21 PM Jiaxun Yang <[email protected]> wrote:
>
> Document Loongson I/O Interrupt controller.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> .../interrupt-controller/loongson,iointc.yaml | 92 +++++++++++++++++++
> 1 file changed, 92 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
> new file mode 100644
> index 000000000000..b0fe6c551362
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,iointc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Loongson I/O Interrupt Controller
> +
> +maintainers:
> + - Jiaxun Yang <[email protected]>
> +
> +description: |
> + This interrupt controller is found in the Loongson-3 family of chips as the primary
> + package interrupt source which can route interrupt to interrupt line of cores.
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: loongson,iointc-1.0
> + - const: loongson,iointc-1.0a
As our early discussion, we should use liointc for the legacy Loongson
irq-controller ans use eiointc for the new irq-controller in
Loongson-3A4000. Moreover, could you please describe the difference
between 1.0 and 1.0a?
Huacai
> +
> + reg:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + interrupts:
> + description:
> + Interrupt source of the CPU interrupts.
> + minItems: 1
> + maxItems: 4
> +
> + interrupt-names:
> + description: List of names for the parent interrupts.
> + oneOf:
> + - items:
> + - const: int0
> + - const: int1
> + - const: int2
> + - const: int3
> + minItems: 1
> + maxItems: 4
> +
> + '#interrupt-cells':
> + const: 2
> +
> + 'loongson,parent_int_map':
> + description: |
> + This property points the accept range of children interrupts
> + that parents will recieve. Each cell refers to a parent interrupt line
> + and each bit in the cell refers to a children interrupt. If a parent
> + did not connected, than keep it's cell with zero.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32-array
> + - items:
> + minItems: 4
> + maxItems: 4
> +
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - '#interrupt-cells'
> + - 'loongson,parent_int_map'
> +
> +
> +examples:
> + - |
> + iointc: interrupt-controller@3ff01400 {
> + compatible = "loongson,iointc-1.0";
> + reg = <0 0x3ff01400 0x64>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>, <3>;
> + interrupt-names = "int0", "int1";
> +
> + loongson,parent_int_map = <0xf0ffffff>, /* int0 */
> + <0x0f000000>, /* int1 */
> + <0x00000000>, /* int2 */
> + <0x00000000>; /* int3 */
> +
> + };
> +
> +...
> --
> 2.24.1
>
于 2020年1月13日 GMT+08:00 上午11:44:10, Huacai Chen <[email protected]> 写到:
>Hi, Jiaxun,
>
>On Sun, Jan 12, 2020 at 4:21 PM Jiaxun Yang <[email protected]>
>wrote:
>>
>> Document Loongson I/O Interrupt controller.
>>
>> Signed-off-by: Jiaxun Yang <[email protected]>
>> Reviewed-by: Rob Herring <[email protected]>
>> ---
>> .../interrupt-controller/loongson,iointc.yaml | 92
>+++++++++++++++++++
>> 1 file changed, 92 insertions(+)
>> create mode 100644
>Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
>>
>> diff --git
>a/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
>b/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
>> new file mode 100644
>> index 000000000000..b0fe6c551362
>> --- /dev/null
>> +++
>b/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml
>> @@ -0,0 +1,92 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id:
>"http://devicetree.org/schemas/interrupt-controller/loongson,iointc.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Loongson I/O Interrupt Controller
>> +
>> +maintainers:
>> + - Jiaxun Yang <[email protected]>
>> +
>> +description: |
>> + This interrupt controller is found in the Loongson-3 family of
>chips as the primary
>> + package interrupt source which can route interrupt to interrupt
>line of cores.
>> +
>> +allOf:
>> + - $ref: /schemas/interrupt-controller.yaml#
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - const: loongson,iointc-1.0
>> + - const: loongson,iointc-1.0a
>As our early discussion, we should use liointc for the legacy Loongson
>irq-controller ans use eiointc for the new irq-controller in
Will do, thanks.
>Loongson-3A4000. Moreover, could you please describe the difference
>between 1.0 and 1.0a?
1.0a appears in Loongson-3A4000 doesn't have LPC spurious interrupt issue.
>
>Huacai
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupt-controller: true
>> +
>> + interrupts:
>> + description:
>> + Interrupt source of the CPU interrupts.
>> + minItems: 1
>> + maxItems: 4
>> +
>> + interrupt-names:
>> + description: List of names for the parent interrupts.
>> + oneOf:
>> + - items:
>> + - const: int0
>> + - const: int1
>> + - const: int2
>> + - const: int3
>> + minItems: 1
>> + maxItems: 4
>> +
>> + '#interrupt-cells':
>> + const: 2
>> +
>> + 'loongson,parent_int_map':
>> + description: |
>> + This property points the accept range of children interrupts
>> + that parents will recieve. Each cell refers to a parent
>interrupt line
>> + and each bit in the cell refers to a children interrupt. If a
>parent
>> + did not connected, than keep it's cell with zero.
>> + allOf:
>> + - $ref: /schemas/types.yaml#/definitions/uint32-array
>> + - items:
>> + minItems: 4
>> + maxItems: 4
>> +
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - interrupts
>> + - interrupt-controller
>> + - '#interrupt-cells'
>> + - 'loongson,parent_int_map'
>> +
>> +
>> +examples:
>> + - |
>> + iointc: interrupt-controller@3ff01400 {
>> + compatible = "loongson,iointc-1.0";
>> + reg = <0 0x3ff01400 0x64>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <2>, <3>;
>> + interrupt-names = "int0", "int1";
>> +
>> + loongson,parent_int_map = <0xf0ffffff>, /* int0 */
>> + <0x0f000000>, /* int1 */
>> + <0x00000000>, /* int2 */
>> + <0x00000000>; /* int3 */
>> +
>> + };
>> +
>> +...
>> --
>> 2.24.1
>>
--
Jiaxun Yang
Hello,
Jiaxun Yang wrote:
> Loongson is a MIPS-compatible processor vendor.
Applied to mips-next.
> commit 1590b1eb9370
> https://git.kernel.org/mips/c/1590b1eb9370
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> Signed-off-by: Paul Burton <[email protected]>
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email [email protected] to report it. ]
Loongson have a long history of contributing their code to mainline kernel.
However, it seems like recent years, they are focusing on maintain a kernel by themselves
rather than contribute there code to the community.
Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
maintainance and became outdated.
This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
Loongson 2e/f alone since they are too legacy to touch.
PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
v1:
- dt-bindings fixup according to Rob's comments
- irqchip fixup according to Marc's comments
- ls3-iointc: Make Core&IP map per-IRQ
- Regenerate kconfigs
- Typo & style improvements
v2:
- dt-bindings: Fix IOINTC, collect Rob's review tag
- dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
v3:
- Split code have been merged
- Fix IOINTC binding to allow map any child IRQ to and parent
- Convert "HTINTC" into "HTPIC", which mixed HT vectors processing and i8259
- Naming style fix according to Huacai's suggestions
v4:
- More naming related fixes
Jiaxun Yang (10):
irqchip: Add driver for Loongson I/O Local Interrupt Controller
dt-bindings: interrupt-controller: Add Loongson LIOINTC
irqchip: Add driver for Loongson-3 HyperTransport PIC controller
dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson boards
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE
.../interrupt-controller/loongson,htpic.yaml | 59 +++
.../loongson,liointc.yaml | 93 +++++
.../bindings/mips/loongson/devices.yaml | 29 ++
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 +
.../boot/dts/loongson/loongson3-package.dtsi | 62 ++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++
arch/mips/include/asm/i8259.h | 1 +
.../include/asm/mach-loongson64/boot_param.h | 2 +
.../asm/mach-loongson64/builtin_dtbs.h | 13 +
arch/mips/include/asm/mach-loongson64/irq.h | 31 +-
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/env.c | 23 ++
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 ---------
arch/mips/loongson64/setup.c | 16 +
arch/mips/loongson64/smp.c | 28 +-
drivers/irqchip/Kconfig | 19 +
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-i8259.c | 6 +-
drivers/irqchip/irq-loongson-htpic.c | 146 ++++++++
drivers/irqchip/irq-loongson-liointc.c | 338 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
27 files changed, 912 insertions(+), 216 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/loongson64/irq.c
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
--
2.25.0
Document Loongson-3 HyperTransport PIC controller.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../interrupt-controller/loongson,htpic.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
new file mode 100644
index 000000000000..c8861cbbb8b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 HyperTransport Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips to transmit
+ interrupts from PCH PIC connected on HyperTransport bus.
+
+properties:
+ compatible:
+ const: loongson,htpic-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ description: |
+ Four parent interrupts that receive chained interrupts.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ htintc: interrupt-controller@1fb000080 {
+ compatible = "loongson,htintc-1.0";
+ reg = <0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.25.0
Prepare for later dts.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../bindings/mips/loongson/devices.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
new file mode 100644
index 000000000000..32bec784da87
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson based Platforms Device Tree Bindings
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+description: |
+ Devices with a Loongson CPU shall have the following properties.
+ Note that generic device is used for built-in dtbs and will be
+ patched during boot on firmware without OF support.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Generic Loongson3 4Core + RS780E
+ items:
+ - const: loongson,loongson3-4core-rs780e
+
+ - description: Generic Loongson3 8Core + RS780E
+ items:
+ - const: loongson,loongson3-8core-rs780e
+...
--
2.25.0
We've made generic irqchip drivers for Loongson-3 platform, it's time
to say goodbye to these legacy code.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../include/asm/mach-loongson64/boot_param.h | 2 +
arch/mips/include/asm/mach-loongson64/irq.h | 29 ----
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 ------------------
arch/mips/loongson64/smp.c | 28 ++-
6 files changed, 20 insertions(+), 209 deletions(-)
delete mode 100644 arch/mips/loongson64/irq.c
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index 8c286bedff3e..2ed483e32d8c 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -2,6 +2,8 @@
#ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
#define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
+#include <linux/types.h>
+
#define SYSTEM_RAM_LOW 1
#define SYSTEM_RAM_HIGH 2
#define SYSTEM_RAM_RESERVED 3
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 73a89913dc38..12208119aac0 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -7,34 +7,5 @@
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
-#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
-#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
-#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
-
-#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
-#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80)
-#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0)
-#define LOONGSON_HT1_INT_VECTOR(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
-#define LOONGSON_HT1_INTN_EN(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
-
-#define LOONGSON_INT_ROUTER_OFFSET 0x1400
-#define LOONGSON_INT_ROUTER_INTEN \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
-#define LOONGSON_INT_ROUTER_INTENSET \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
-#define LOONGSON_INT_ROUTER_INTENCLR \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
-#define LOONGSON_INT_ROUTER_ENTRY(n) \
- LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
-#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
-#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
-
-#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
-
-extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(struct pt_regs *regs);
-
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 7821891bc5d0..b7f40b179c71 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -2,7 +2,7 @@
#
# Makefile for Loongson-3 family machines
#
-obj-$(CONFIG_MACH_LOONGSON64) += irq.o cop2-ex.o platform.o acpi_init.o dma.o \
+obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \
setup.o init.o env.o time.o reset.o \
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index 5ac1a0f35ca4..da38944471f4 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -4,6 +4,7 @@
* Author: Wu Zhangjin, [email protected]
*/
+#include <linux/irqchip.h>
#include <linux/memblock.h>
#include <asm/bootinfo.h>
#include <asm/traps.h>
@@ -44,3 +45,8 @@ void __init prom_init(void)
void __init prom_free_prom_memory(void)
{
}
+
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c
deleted file mode 100644
index 79ad797497e4..000000000000
--- a/arch/mips/loongson64/irq.c
+++ /dev/null
@@ -1,162 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <loongson.h>
-#include <irq.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/i8259.h>
-#include <asm/mipsregs.h>
-
-#include "smp.h"
-
-extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
-
-unsigned int irq_cpu[16] = {[0 ... 15] = -1};
-unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
-unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
-
-int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
- bool force)
-{
- unsigned int cpu;
- struct cpumask new_affinity;
-
- /* I/O devices are connected on package-0 */
- cpumask_copy(&new_affinity, affinity);
- for_each_cpu(cpu, affinity)
- if (cpu_data[cpu].package > 0)
- cpumask_clear_cpu(cpu, &new_affinity);
-
- if (cpumask_empty(&new_affinity))
- return -EINVAL;
-
- cpumask_copy(d->common->affinity, &new_affinity);
-
- return IRQ_SET_MASK_OK_NOCOPY;
-}
-
-static void ht_irqdispatch(void)
-{
- unsigned int i, irq;
- struct irq_data *irqd;
- struct cpumask affinity;
-
- irq = LOONGSON_HT1_INT_VECTOR(0);
- LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
-
- for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
- if (!(irq & (0x1 << ht_irq[i])))
- continue;
-
- /* handled by local core */
- if (local_irq & (0x1 << ht_irq[i])) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irqd = irq_get_irq_data(ht_irq[i]);
- cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
- if (cpumask_empty(&affinity)) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
- if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
- irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
-
- if (irq_cpu[ht_irq[i]] == 0) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- /* balanced by other cores */
- loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
- }
-}
-
-#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & CAUSEF_IP7)
- do_IRQ(LOONGSON_TIMER_IRQ);
-#if defined(CONFIG_SMP)
- if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt(NULL);
-#endif
- if (pending & CAUSEF_IP3)
- ht_irqdispatch();
- if (pending & CAUSEF_IP2)
- do_IRQ(LOONGSON_UART_IRQ);
- if (pending & UNUSED_IPS) {
- pr_err("%s : spurious interrupt\n", __func__);
- spurious_interrupt();
- }
-}
-
-static inline void mask_loongson_irq(struct irq_data *d) { }
-static inline void unmask_loongson_irq(struct irq_data *d) { }
-
- /* For MIPS IRQs which shared by all cores */
-static struct irq_chip loongson_irq_chip = {
- .name = "Loongson",
- .irq_ack = mask_loongson_irq,
- .irq_mask = mask_loongson_irq,
- .irq_mask_ack = mask_loongson_irq,
- .irq_unmask = unmask_loongson_irq,
- .irq_eoi = unmask_loongson_irq,
-};
-
-void irq_router_init(void)
-{
- int i;
-
- /* route LPC int to cpu core0 int 0 */
- LOONGSON_INT_ROUTER_LPC =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
- /* route HT1 int0 ~ int7 to cpu core0 INT1*/
- for (i = 0; i < 8; i++)
- LOONGSON_INT_ROUTER_HT1(i) =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
- /* enable HT1 interrupt */
- LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
- /* enable router interrupt intenset */
- LOONGSON_INT_ROUTER_INTENSET =
- LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
-}
-
-void __init arch_init_irq(void)
-{
- struct irq_chip *chip;
-
- clear_c0_status(ST0_IM | ST0_BEV);
-
- irq_router_init();
- mips_cpu_irq_init();
- init_i8259_irqs();
- chip = irq_get_chip(I8259A_IRQ_BASE);
- chip->irq_set_affinity = plat_set_irq_affinity;
-
- irq_set_chip_and_handler(LOONGSON_UART_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
- irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
-
- set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-
-void fixup_irqs(void)
-{
- irq_cpu_offline();
- clear_c0_status(ST0_IM);
-}
-
-#endif
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index de8e0741ce2d..e1fe8bbb377d 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -4,6 +4,7 @@
* Author: Chen Huacai, [email protected]
*/
+#include <irq.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/sched.h>
@@ -25,6 +26,8 @@
DEFINE_PER_CPU(int, cpu_state);
+#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
+
static void *ipi_set0_regs[16];
static void *ipi_clear0_regs[16];
static void *ipi_status0_regs[16];
@@ -302,20 +305,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
ipi_write_action(cpu_logical_map(i), (u32)action);
}
-#define IPI_IRQ_OFFSET 6
-
-void loongson3_send_irq_by_ipi(int cpu, int irqs)
-{
- ipi_write_action(cpu_logical_map(cpu), irqs << IPI_IRQ_OFFSET);
-}
-void loongson3_ipi_interrupt(struct pt_regs *regs)
+static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
{
int i, cpu = smp_processor_id();
- unsigned int action, c0count, irqs;
+ unsigned int action, c0count;
action = ipi_read_clear(cpu);
- irqs = action >> IPI_IRQ_OFFSET;
if (action & SMP_RESCHEDULE_YOURSELF)
scheduler_ipi();
@@ -335,13 +331,7 @@ void loongson3_ipi_interrupt(struct pt_regs *regs)
__wbflush(); /* Let others see the result ASAP */
}
- if (irqs) {
- int irq;
- while ((irq = ffs(irqs))) {
- do_IRQ(irq-1);
- irqs &= ~(1<<(irq-1));
- }
- }
+ return IRQ_HANDLED;
}
#define MAX_LOOPS 800
@@ -438,6 +428,9 @@ static void __init loongson3_smp_setup(void)
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
{
+ if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
+ pr_err("Failed to request IPI IRQ\n");
init_cpu_present(cpu_possible_mask);
per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
}
@@ -484,7 +477,8 @@ static int loongson3_cpu_disable(void)
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
local_irq_save(flags);
- fixup_irqs();
+ irq_cpu_offline();
+ clear_c0_status(ST0_IM);
local_irq_restore(flags);
local_flush_tlb_all();
--
2.25.0
The old code is using legacy domain to setup irq_domain for CPU interrupts
which requires irq_desc to be preallocated.
However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up
unallocated and lead to incorrect behavior.
Thus we convert the legacy domain to simple domain which can allocate irq_desc
during initialization.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..c3cf7fa76424 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+ irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
&mips_cpu_intc_irq_domain_ops,
NULL);
if (!irq_domain)
--
2.25.0
To prevent CPU IRQ collide with PCH IRQ, we move down
CPU IRQ BASE to 16.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 12208119aac0..1ce2e0bbe305 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -5,7 +5,7 @@
#include <boot_param.h>
/* cpu core interrupt numbers */
-#define MIPS_CPU_IRQ_BASE 56
+#define MIPS_CPU_IRQ_BASE 16
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
--
2.25.0
Add generic device dts for Loongson-3 devices.
They are currently almost identical but will be different later.
Some PCH devices like PCI Host Bridge is still enabled by platform
code for now.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 ++
.../boot/dts/loongson/loongson3-package.dtsi | 62 +++++++++++++++++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++
7 files changed, 147 insertions(+), 2 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 797d7f1ad5fe..c3aefb49c61a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -486,9 +486,11 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
- select LOONGSON_MC146818
select ZONE_DMA32
select NUMA
+ select COMMON_CLK
+ select USE_OF
+ select BUILTIN_DTB
help
This enables the support of Loongson-2/3 family of machines.
@@ -3070,7 +3072,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && \
+ !MACH_LOONGSON64 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..d429a69bfe30 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
+subdir-y += loongson
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000000..56d379471262
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,4 @@
+# SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
new file mode 100644
index 000000000000..d09c313603f1
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package0: bus@1fe00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 /* 3A HT Config Space */
+ 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000 /* 3B HT Config Space */>;
+
+ liointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&liointc>;
+ no-loopback-test;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
new file mode 100644
index 000000000000..6b5694ca0f95
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-4core-rs780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
new file mode 100644
index 000000000000..ffefa2f829b0
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-8core-rs780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@1efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0x1efd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
new file mode 100644
index 000000000000..45c54d555fa4
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x10000000 0 0x10000000 0 0x10000000
+ 0 0x40000000 0 0x40000000 0 0x40000000
+ 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
+
+ isa {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0 0x1000>;
+
+ rtc0: rtc@70 {
+ compatible = "motorola,mc146818";
+ reg = <1 0x70 0x8>;
+ interrupts = <8>;
+ interrupt-parent = <&htpic>;
+ };
+ };
+ };
+};
--
2.25.0
Load proper dtb according to firmware passed parameters and
CPU PRID.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../asm/mach-loongson64/builtin_dtbs.h | 13 +++++++++++
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/env.c | 23 +++++++++++++++++++
arch/mips/loongson64/setup.c | 16 +++++++++++++
4 files changed, 53 insertions(+)
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
new file mode 100644
index 000000000000..853c6d80887b
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Built-in Generic dtbs for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+
+extern u32 __dtb_loongson3_4core_rs780e_begin[];
+extern u32 __dtb_loongson3_8core_rs780e_begin[];
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index a8fce112a9b0..fde1b75c45ea 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -25,6 +25,7 @@ extern const struct plat_smp_ops loongson3_smp_ops;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
extern void __init prom_init_env(void);
+extern void *loongson_fdt_blob;
/* irq operation functions */
extern void mach_irq_dispatch(unsigned int pending);
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 0daeb7bcf023..2554ef11170d 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -17,6 +17,7 @@
#include <asm/bootinfo.h>
#include <loongson.h>
#include <boot_param.h>
+#include <builtin_dtbs.h>
#include <workarounds.h>
u32 cpu_clock_freq;
@@ -120,6 +121,28 @@ void __init prom_init_env(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
+ break;
+ default:
+ break;
+ }
+ }
+
+
+ if (!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
+
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
index 4fd27f4f90ed..6fe3ffffcaa6 100644
--- a/arch/mips/loongson64/setup.c
+++ b/arch/mips/loongson64/setup.c
@@ -8,9 +8,15 @@
#include <asm/wbflush.h>
#include <asm/bootinfo.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
#include <loongson.h>
+void *loongson_fdt_blob;
+
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
@@ -27,4 +33,14 @@ EXPORT_SYMBOL(__wbflush);
void __init plat_mem_setup(void)
{
+ if (loongson_fdt_blob)
+ __dt_setup_arch(loongson_fdt_blob);
+}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
}
--
2.25.0
On Fri, Feb 21, 2020 at 01:09:22PM +0800, Jiaxun Yang wrote:
> Prepare for later dts.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> .../bindings/mips/loongson/devices.yaml | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
>
> diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> new file mode 100644
> index 000000000000..32bec784da87
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> @@ -0,0 +1,29 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson based Platforms Device Tree Bindings
> +
> +maintainers:
> + - Jiaxun Yang <[email protected]>
> +description: |
> + Devices with a Loongson CPU shall have the following properties.
Perhaps some details about the platform.
> + Note that generic device is used for built-in dtbs and will be
> + patched during boot on firmware without OF support.
That's a kernel detail that doesn't belong here. (BTW, built-in dtb
support is intended as a transition step for bootloaders without dtb
knowledge. It's not the recommended way and shouldn't be used on new
platforms).
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> +
> + - description: Generic Loongson3 4Core + RS780E
> + items:
> + - const: loongson,loongson3-4core-rs780e
> +
> + - description: Generic Loongson3 8Core + RS780E
> + items:
> + - const: loongson,loongson3-8core-rs780e
> +...
> --
> 2.25.0
>
>
---- 在 星期四, 2020-02-27 00:52:11 Rob Herring <[email protected]> 撰写 ----
> On Fri, Feb 21, 2020 at 01:09:22PM +0800, Jiaxun Yang wrote:
> > Prepare for later dts.
> >
> > Signed-off-by: Jiaxun Yang <[email protected]>
> > ---
> > .../bindings/mips/loongson/devices.yaml | 29 +++++++++++++++++++
> > 1 file changed, 29 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> > new file mode 100644
> > index 000000000000..32bec784da87
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> > @@ -0,0 +1,29 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Loongson based Platforms Device Tree Bindings
> > +
> > +maintainers:
> > + - Jiaxun Yang <[email protected]>
> > +description: |
> > + Devices with a Loongson CPU shall have the following properties.
>
> Perhaps some details about the platform.
>
> > + Note that generic device is used for built-in dtbs and will be
> > + patched during boot on firmware without OF support.
>
> That's a kernel detail that doesn't belong here. (BTW, built-in dtb
> support is intended as a transition step for bootloaders without dtb
> knowledge. It's not the recommended way and shouldn't be used on new
> platforms).
Yes, it's used to deal with legacy platforms.
Will drop this line in next version.
Thanks.
>
> > +
> > +properties:
> > + $nodename:
> > + const: '/'
> > + compatible:
> > + oneOf:
> > +
> > + - description: Generic Loongson3 4Core + RS780E
> > + items:
> > + - const: loongson,loongson3-4core-rs780e
> > +
> > + - description: Generic Loongson3 8Core + RS780E
> > + items:
> > + - const: loongson,loongson3-8core-rs780e
> > +...
> > --
> > 2.25.0
> >
> >
>
Loongson have a long history of contributing their code to mainline kernel.
However, it seems like recent years, they are focusing on maintain a kernel by themselves
rather than contribute there code to the community.
Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
maintainance and became outdated.
This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
Loongson 2e/f alone since they are too legacy to touch.
PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
v1:
- dt-bindings fixup according to Rob's comments
- irqchip fixup according to Marc's comments
- ls3-iointc: Make Core&IP map per-IRQ
- Regenerate kconfigs
- Typo & style improvements
v2:
- dt-bindings: Fix IOINTC, collect Rob's review tag
- dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
v3:
- Split code have been merged
- Fix IOINTC binding to allow map any child IRQ to and parent
- Convert "HTINTC" into "HTPIC", which mixed HT vectors processing and i8259
- Naming style fix according to Huacai's suggestions
v4:
- More naming related fixes
v5:
- irqchip fixes thanks to maz (see per file changelog)
- Remove unnecessary details in dt-bindings
- Credit Huacai with Co-developed-by
Jiaxun Yang (11):
irqchip: Add driver for Loongson I/O Local Interrupt Controller
irqchip: loongson-liointc: Workaround LPC IRQ Errata
dt-bindings: interrupt-controller: Add Loongson LIOINTC
irqchip: Add driver for Loongson-3 HyperTransport PIC controller
dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson boards
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE
.../interrupt-controller/loongson,htpic.yaml | 59 ++++
.../loongson,liointc.yaml | 93 ++++++
.../bindings/mips/loongson/devices.yaml | 27 ++
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 +
.../boot/dts/loongson/loongson3-package.dtsi | 62 ++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++
arch/mips/include/asm/i8259.h | 1 +
.../include/asm/mach-loongson64/boot_param.h | 2 +
.../asm/mach-loongson64/builtin_dtbs.h | 13 +
arch/mips/include/asm/mach-loongson64/irq.h | 31 +-
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/env.c | 23 ++
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 -----------
arch/mips/loongson64/setup.c | 16 ++
arch/mips/loongson64/smp.c | 28 +-
drivers/irqchip/Kconfig | 19 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-loongson-htpic.c | 149 ++++++++++
drivers/irqchip/irq-loongson-liointc.c | 271 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
26 files changed, 843 insertions(+), 213 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/loongson64/irq.c
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
--
2.26.0.rc2
Document Loongson I/O Interrupt controller.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../loongson,liointc.yaml | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
new file mode 100644
index 000000000000..9c6b91fee477
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson Local I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt controller which can route local I/O interrupt to interrupt lines
+ of cores.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,liointc-1.0
+ - const: loongson,liointc-1.0a
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ description:
+ Interrupt source of the CPU interrupts.
+ minItems: 1
+ maxItems: 4
+
+ interrupt-names:
+ description: List of names for the parent interrupts.
+ items:
+ - const: int0
+ - const: int1
+ - const: int2
+ - const: int3
+ minItems: 1
+ maxItems: 4
+
+ '#interrupt-cells':
+ const: 2
+
+ 'loongson,parent_int_map':
+ description: |
+ This property points how the children interrupts will be mapped into CPU
+ interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
+ and each bit in the cell refers to a children interrupt fron 0 to 31.
+ If a CPU interrupt line didn't connected with liointc, then keep it's
+ cell with zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - items:
+ minItems: 4
+ maxItems: 4
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - 'loongson,parent_int_map'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+...
--
2.26.0.rc2
The 1.0 version of that controller has a bug that status bit
of LPC IRQ sometimes doesn't get set correctly.
So we can always blame LPC IRQ when spurious interrupt happens
at the parent interrupt line which LPC IRQ supposed to route
to.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-loongson-liointc.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 8b6d7b8ddaca..d5054e90eab8 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -32,6 +32,8 @@
#define LIOINTC_SHIFT_INTx 4
+#define LIOINTC_ERRATA_IRQ 10
+
struct liointc_handler_data {
struct liointc_priv *priv;
u32 parent_int_map;
@@ -41,6 +43,7 @@ struct liointc_priv {
struct irq_chip_generic *gc;
struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
u8 map_cache[LIOINTC_CHIP_IRQ];
+ bool have_lpc_irq_errata;
};
static void liointc_chained_handle_irq(struct irq_desc *desc)
@@ -54,8 +57,14 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
- if (!pending)
- spurious_interrupt();
+ if (!pending) {
+ /* Always blame LPC IRQ if we have that bug and LPC IRQ is enabled */
+ if (handler->priv->have_lpc_irq_errata &&
+ (handler->parent_int_map & ~gc->mask_cache & BIT(LIOINTC_ERRATA_IRQ)))
+ pending = BIT(LIOINTC_ERRATA_IRQ);
+ else
+ spurious_interrupt();
+ }
while (pending) {
int bit = __ffs(pending);
@@ -164,6 +173,9 @@ int __init liointc_of_init(struct device_node *node,
goto out_iounmap;
}
+ if (of_device_is_compatible(node, "loongson,liointc-1.0"))
+ priv->have_lpc_irq_errata = true;
+
sz = of_property_read_variable_u32_array(node, "loongson,parent_int_map",
&of_parent_int_map[0], LIOINTC_NUM_PARENT,
LIOINTC_NUM_PARENT);
--
2.26.0.rc2
This controller appeared on Loongson-3 family of chips to receive interrupts
from PCH PIC.
It is a I8259 with optimized interrupt polling flow. We can poll interrupt number
from HT vector directly but still have to follow standard I8259 routines to mask,
unmask and EOI.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
v4-v5:
Enhancements according to maz's suggestions:
- Add static for private struct
- Drop pointless rename
- Fix DT parse bug
- Clarifications in comments and commit message
---
arch/mips/include/asm/i8259.h | 1 +
drivers/irqchip/Kconfig | 10 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-htpic.c | 149 +++++++++++++++++++++++++++
4 files changed, 161 insertions(+)
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index 97a5e41ed1ab..a54b9649de22 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -36,6 +36,7 @@ extern raw_spinlock_t i8259A_lock;
extern void make_8259A_irq(unsigned int irq);
extern void init_i8259_irqs(void);
+extern struct irq_domain *__init_i8259_irqs(struct device_node *node);
/**
* i8159_set_poll() - Override the i8259 polling function
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c609eaa319d2..cae6f480c987 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -522,4 +522,14 @@ config LOONGSON_LIOINTC
help
Support for the Loongson Local I/O Interrupt Controller.
+config LOONGSON_HTPIC
+ bool "Loongson3 HyperTransport PIC Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ select I8259
+ help
+ Support for the Loongson-3 HyperTransport PIC Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 5e7678efdfe6..37bbe39bf909 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -106,3 +106,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
+obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c
new file mode 100644
index 000000000000..3391e472766d
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-htpic.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <[email protected]>
+ * Loongson HTPIC IRQ support
+ */
+
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <asm/i8259.h>
+
+#define HTPIC_MAX_PARENT_IRQ 4
+#define HTINT_NUM_VECTORS 8
+#define HTINT_EN_OFF 0x20
+
+struct loongson_htpic {
+ void __iomem *base;
+ struct irq_domain *domain;
+};
+
+static struct loongson_htpic *htpic;
+
+static void htpic_irq_dispatch(struct irq_desc *desc)
+{
+ struct loongson_htpic *priv = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ uint32_t pending;
+
+ chained_irq_enter(chip, desc);
+ pending = readl(priv->base);
+ /* Ack all IRQs at once, otherwise IRQ flood might happen */
+ writel(pending, priv->base);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ if (unlikely(bit > 15)) {
+ spurious_interrupt();
+ break;
+ }
+
+ generic_handle_irq(irq_linear_revmap(priv->domain, bit));
+ pending &= ~BIT(bit);
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static void htpic_reg_init(void)
+{
+ int i;
+
+ for (i = 0; i < HTINT_NUM_VECTORS; i++) {
+ uint32_t val;
+
+ /* Disable all HT Vectors */
+ writel(0x0, htpic->base + HTINT_EN_OFF + i * 0x4);
+ val = readl(htpic->base + i * 0x4);
+ /* Ack all possible pending IRQs */
+ writel(GENMASK(31, 0), htpic->base + i * 0x4);
+ }
+
+ /* Enable 16 vectors for PIC */
+ writel(0xffff, htpic->base + HTINT_EN_OFF);
+}
+
+static void htpic_resume(void)
+{
+ htpic_reg_init();
+}
+
+struct syscore_ops htpic_syscore_ops = {
+ .resume = htpic_resume,
+};
+
+int __init htpic_of_init(struct device_node *node, struct device_node *parent)
+{
+ unsigned int parent_irq[4];
+ int i, err;
+ int num_parents = 0;
+
+ if (htpic) {
+ pr_err("loongson-htpic: Only one HTPIC is allowed in the system\n");
+ return -ENODEV;
+ }
+
+ htpic = kzalloc(sizeof(*htpic), GFP_KERNEL);
+ if (!htpic) {
+ err = -ENOMEM;
+ goto out_free;
+ }
+
+ htpic->base = of_iomap(node, 0);
+ if (!htpic->base) {
+ err = -ENODEV;
+ goto out_free;
+ }
+
+ htpic->domain = __init_i8259_irqs(node);
+ if (!htpic->domain) {
+ pr_err("loongson-htpic: Failed to initialize i8259 IRQs\n");
+ err = -ENOMEM;
+ goto out_iounmap;
+ }
+
+ /* Interrupt may come from any of the 4 interrupt line */
+ for (i = 0; i < HTPIC_MAX_PARENT_IRQ; i++) {
+ parent_irq[i] = irq_of_parse_and_map(node, i);
+ if (parent_irq[i] < 0)
+ break;
+
+ num_parents++;
+ }
+
+ if (!num_parents) {
+ pr_err("loongson-htpic: Failed to get parent irqs\n");
+ err = -ENODEV;
+ goto out_remove_domain;
+ }
+
+ htpic_reg_init();
+
+ for (i = 0; i < num_parents; i++) {
+ irq_set_chained_handler_and_data(parent_irq[i],
+ htpic_irq_dispatch, htpic);
+ }
+
+ register_syscore_ops(&htpic_syscore_ops);
+
+ return 0;
+
+out_remove_domain:
+ irq_domain_remove(htpic->domain);
+out_iounmap:
+ iounmap(htpic->base);
+out_free:
+ kfree(htpic);
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_htpic, "loongson,htpic-1.0", htpic_of_init);
--
2.26.0.rc2
This controller appeared on Loongson family of chips as the primary
package interrupt source.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
v4-v5:
Resolve suggestions from maz:
- Remove DT validation
- Simplify unnucessary functions & variables
---
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-liointc.c | 259 +++++++++++++++++++++++++
3 files changed, 269 insertions(+)
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 6d397732138d..c609eaa319d2 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER
Say yes here to add support for the IRQ combiner devices embedded
in Samsung Exynos chips.
+config LOONGSON_LIOINTC
+ bool "Loongson Local I/O Interrupt Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson Local I/O Interrupt Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index eae0d78cbf22..5e7678efdfe6 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
+obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
new file mode 100644
index 000000000000..8b6d7b8ddaca
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <[email protected]>
+ * Loongson Local IO Interrupt Controller support
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/irqchip/chained_irq.h>
+
+#include <boot_param.h>
+
+#define LIOINTC_CHIP_IRQ 32
+#define LIOINTC_NUM_PARENT 4
+
+#define LIOINTC_INTC_CHIP_START 0x20
+
+#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
+#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
+#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
+#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
+#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
+#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
+
+#define LIOINTC_SHIFT_INTx 4
+
+struct liointc_handler_data {
+ struct liointc_priv *priv;
+ u32 parent_int_map;
+};
+
+struct liointc_priv {
+ struct irq_chip_generic *gc;
+ struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
+ u8 map_cache[LIOINTC_CHIP_IRQ];
+};
+
+static void liointc_chained_handle_irq(struct irq_desc *desc)
+{
+ struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct irq_chip_generic *gc = handler->priv->gc;
+ u32 pending;
+
+ chained_irq_enter(chip, desc);
+
+ pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ generic_handle_irq(irq_find_mapping(gc->domain, bit));
+ pending &= ~BIT(bit);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void liointc_set_bit(struct irq_chip_generic *gc,
+ unsigned int offset,
+ u32 mask, bool set)
+{
+ if (set)
+ writel(readl(gc->reg_base + offset) | mask,
+ gc->reg_base + offset);
+ else
+ writel(readl(gc->reg_base + offset) & ~mask,
+ gc->reg_base + offset);
+}
+
+static int liointc_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ u32 mask = data->mask;
+ unsigned long flags;
+
+ irq_gc_lock_irqsave(gc, flags);
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ default:
+ return -EINVAL;
+ }
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ irqd_set_trigger_type(data, type);
+ return 0;
+}
+
+static void liointc_resume(struct irq_chip_generic *gc)
+{
+ struct liointc_priv *priv = gc->private;
+ unsigned long flags;
+ int i;
+
+ irq_gc_lock_irqsave(gc, flags);
+ /* Disable all at first */
+ writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
+ /* Revert map cache */
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
+ writeb(priv->map_cache[i], gc->reg_base + i);
+ /* Revert mask cache */
+ writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
+ irq_gc_unlock_irqrestore(gc, flags);
+}
+
+static const char const *parent_names[] = {"int0", "int1", "int2", "int3"};
+
+int __init liointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_domain *domain;
+ struct irq_chip_type *ct;
+ struct liointc_priv *priv;
+ void __iomem *base;
+ u32 of_parent_int_map[LIOINTC_NUM_PARENT];
+ int parent_irq[LIOINTC_NUM_PARENT];
+ bool have_parent = FALSE;
+ int sz, i, err = 0;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
+ if (parent_irq[i] > 0)
+ have_parent = TRUE;
+ }
+ if (!have_parent) {
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ sz = of_property_read_variable_u32_array(node, "loongson,parent_int_map",
+ &of_parent_int_map[0], LIOINTC_NUM_PARENT,
+ LIOINTC_NUM_PARENT);
+ if (sz < 4) {
+ pr_err("loongson-liointc: No parent_int_map\n");
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++)
+ priv->handler[i].parent_int_map = of_parent_int_map[i];
+
+ /* Setup IRQ domain */
+ domain = irq_domain_add_linear(node, 32,
+ &irq_generic_chip_ops, priv);
+ if (!domain) {
+ pr_err("loongson-liointc: cannot add IRQ domain\n");
+ err = -EINVAL;
+ goto out_iounmap;
+ }
+
+ err = irq_alloc_domain_generic_chips(domain, 32, 1,
+ node->full_name, handle_level_irq,
+ IRQ_NOPROBE, 0, 0);
+ if (err) {
+ pr_err("loongson-liointc: unable to register IRQ domain\n");
+ goto out_free_domain;
+ }
+
+
+ /* Disable all IRQs */
+ writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
+ /* Set to level triggered */
+ writel(0x0, base + LIOINTC_REG_INTC_EDGE);
+
+ /* Generate parent INT part of map cache */
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ u32 pending = priv->handler[i].parent_int_map;
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
+ pending &= ~BIT(bit);
+ }
+ }
+
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
+ /* Generate core part of map cache */
+ priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
+ writeb(priv->map_cache[i], base + i);
+ }
+
+ gc = irq_get_domain_generic_chip(domain, 0);
+ gc->private = priv;
+ gc->reg_base = base;
+ gc->domain = domain;
+ gc->resume = liointc_resume;
+
+ ct = gc->chip_types;
+ ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
+ ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
+ ct->chip.irq_set_type = liointc_set_type;
+
+ gc->mask_cache = 0xffffffff;
+ priv->gc = gc;
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ if (parent_irq[i] <= 0)
+ continue;
+
+ priv->handler[i].priv = priv;
+ irq_set_chained_handler_and_data(parent_irq[i],
+ liointc_chained_handle_irq, &priv->handler[i]);
+ }
+
+ return 0;
+
+out_free_domain:
+ irq_domain_remove(domain);
+out_iounmap:
+ iounmap(base);
+out_free_priv:
+ kfree(priv);
+
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
+IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
--
2.26.0.rc2
Document Loongson-3 HyperTransport PIC controller.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../interrupt-controller/loongson,htpic.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
new file mode 100644
index 000000000000..c8861cbbb8b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 HyperTransport Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips to transmit
+ interrupts from PCH PIC connected on HyperTransport bus.
+
+properties:
+ compatible:
+ const: loongson,htpic-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ description: |
+ Four parent interrupts that receive chained interrupts.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ htintc: interrupt-controller@1fb000080 {
+ compatible = "loongson,htintc-1.0";
+ reg = <0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.26.0.rc2
Add generic device dts for Loongson-3 devices.
They are currently almost identical but will be different later.
Some PCH devices like PCI Host Bridge is still enabled by platform
code for now.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 ++
.../boot/dts/loongson/loongson3-package.dtsi | 62 +++++++++++++++++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++
7 files changed, 147 insertions(+), 2 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 797d7f1ad5fe..c3aefb49c61a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -486,9 +486,11 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
- select LOONGSON_MC146818
select ZONE_DMA32
select NUMA
+ select COMMON_CLK
+ select USE_OF
+ select BUILTIN_DTB
help
This enables the support of Loongson-2/3 family of machines.
@@ -3070,7 +3072,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && \
+ !MACH_LOONGSON64 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..d429a69bfe30 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
+subdir-y += loongson
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000000..56d379471262
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,4 @@
+# SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
new file mode 100644
index 000000000000..d09c313603f1
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package0: bus@1fe00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 /* 3A HT Config Space */
+ 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000 /* 3B HT Config Space */>;
+
+ liointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&liointc>;
+ no-loopback-test;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
new file mode 100644
index 000000000000..6b5694ca0f95
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-4core-rs780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
new file mode 100644
index 000000000000..ffefa2f829b0
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-8core-rs780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@1efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0x1efd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
new file mode 100644
index 000000000000..45c54d555fa4
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x10000000 0 0x10000000 0 0x10000000
+ 0 0x40000000 0 0x40000000 0 0x40000000
+ 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
+
+ isa {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0 0x1000>;
+
+ rtc0: rtc@70 {
+ compatible = "motorola,mc146818";
+ reg = <1 0x70 0x8>;
+ interrupts = <8>;
+ interrupt-parent = <&htpic>;
+ };
+ };
+ };
+};
--
2.26.0.rc2
We've made generic irqchip drivers for Loongson-3 platform, it's time
to say goodbye to these legacy code.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../include/asm/mach-loongson64/boot_param.h | 2 +
arch/mips/include/asm/mach-loongson64/irq.h | 29 ----
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 ------------------
arch/mips/loongson64/smp.c | 28 ++-
6 files changed, 20 insertions(+), 209 deletions(-)
delete mode 100644 arch/mips/loongson64/irq.c
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index 8c286bedff3e..2ed483e32d8c 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -2,6 +2,8 @@
#ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
#define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
+#include <linux/types.h>
+
#define SYSTEM_RAM_LOW 1
#define SYSTEM_RAM_HIGH 2
#define SYSTEM_RAM_RESERVED 3
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 73a89913dc38..12208119aac0 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -7,34 +7,5 @@
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
-#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
-#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
-#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
-
-#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
-#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80)
-#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0)
-#define LOONGSON_HT1_INT_VECTOR(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
-#define LOONGSON_HT1_INTN_EN(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
-
-#define LOONGSON_INT_ROUTER_OFFSET 0x1400
-#define LOONGSON_INT_ROUTER_INTEN \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
-#define LOONGSON_INT_ROUTER_INTENSET \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
-#define LOONGSON_INT_ROUTER_INTENCLR \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
-#define LOONGSON_INT_ROUTER_ENTRY(n) \
- LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
-#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
-#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
-
-#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
-
-extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(struct pt_regs *regs);
-
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 7821891bc5d0..b7f40b179c71 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -2,7 +2,7 @@
#
# Makefile for Loongson-3 family machines
#
-obj-$(CONFIG_MACH_LOONGSON64) += irq.o cop2-ex.o platform.o acpi_init.o dma.o \
+obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \
setup.o init.o env.o time.o reset.o \
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index 5ac1a0f35ca4..da38944471f4 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -4,6 +4,7 @@
* Author: Wu Zhangjin, [email protected]
*/
+#include <linux/irqchip.h>
#include <linux/memblock.h>
#include <asm/bootinfo.h>
#include <asm/traps.h>
@@ -44,3 +45,8 @@ void __init prom_init(void)
void __init prom_free_prom_memory(void)
{
}
+
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c
deleted file mode 100644
index 79ad797497e4..000000000000
--- a/arch/mips/loongson64/irq.c
+++ /dev/null
@@ -1,162 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <loongson.h>
-#include <irq.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/i8259.h>
-#include <asm/mipsregs.h>
-
-#include "smp.h"
-
-extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
-
-unsigned int irq_cpu[16] = {[0 ... 15] = -1};
-unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
-unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
-
-int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
- bool force)
-{
- unsigned int cpu;
- struct cpumask new_affinity;
-
- /* I/O devices are connected on package-0 */
- cpumask_copy(&new_affinity, affinity);
- for_each_cpu(cpu, affinity)
- if (cpu_data[cpu].package > 0)
- cpumask_clear_cpu(cpu, &new_affinity);
-
- if (cpumask_empty(&new_affinity))
- return -EINVAL;
-
- cpumask_copy(d->common->affinity, &new_affinity);
-
- return IRQ_SET_MASK_OK_NOCOPY;
-}
-
-static void ht_irqdispatch(void)
-{
- unsigned int i, irq;
- struct irq_data *irqd;
- struct cpumask affinity;
-
- irq = LOONGSON_HT1_INT_VECTOR(0);
- LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
-
- for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
- if (!(irq & (0x1 << ht_irq[i])))
- continue;
-
- /* handled by local core */
- if (local_irq & (0x1 << ht_irq[i])) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irqd = irq_get_irq_data(ht_irq[i]);
- cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
- if (cpumask_empty(&affinity)) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
- if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
- irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
-
- if (irq_cpu[ht_irq[i]] == 0) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- /* balanced by other cores */
- loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
- }
-}
-
-#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & CAUSEF_IP7)
- do_IRQ(LOONGSON_TIMER_IRQ);
-#if defined(CONFIG_SMP)
- if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt(NULL);
-#endif
- if (pending & CAUSEF_IP3)
- ht_irqdispatch();
- if (pending & CAUSEF_IP2)
- do_IRQ(LOONGSON_UART_IRQ);
- if (pending & UNUSED_IPS) {
- pr_err("%s : spurious interrupt\n", __func__);
- spurious_interrupt();
- }
-}
-
-static inline void mask_loongson_irq(struct irq_data *d) { }
-static inline void unmask_loongson_irq(struct irq_data *d) { }
-
- /* For MIPS IRQs which shared by all cores */
-static struct irq_chip loongson_irq_chip = {
- .name = "Loongson",
- .irq_ack = mask_loongson_irq,
- .irq_mask = mask_loongson_irq,
- .irq_mask_ack = mask_loongson_irq,
- .irq_unmask = unmask_loongson_irq,
- .irq_eoi = unmask_loongson_irq,
-};
-
-void irq_router_init(void)
-{
- int i;
-
- /* route LPC int to cpu core0 int 0 */
- LOONGSON_INT_ROUTER_LPC =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
- /* route HT1 int0 ~ int7 to cpu core0 INT1*/
- for (i = 0; i < 8; i++)
- LOONGSON_INT_ROUTER_HT1(i) =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
- /* enable HT1 interrupt */
- LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
- /* enable router interrupt intenset */
- LOONGSON_INT_ROUTER_INTENSET =
- LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
-}
-
-void __init arch_init_irq(void)
-{
- struct irq_chip *chip;
-
- clear_c0_status(ST0_IM | ST0_BEV);
-
- irq_router_init();
- mips_cpu_irq_init();
- init_i8259_irqs();
- chip = irq_get_chip(I8259A_IRQ_BASE);
- chip->irq_set_affinity = plat_set_irq_affinity;
-
- irq_set_chip_and_handler(LOONGSON_UART_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
- irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
-
- set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-
-void fixup_irqs(void)
-{
- irq_cpu_offline();
- clear_c0_status(ST0_IM);
-}
-
-#endif
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index de8e0741ce2d..e1fe8bbb377d 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -4,6 +4,7 @@
* Author: Chen Huacai, [email protected]
*/
+#include <irq.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/sched.h>
@@ -25,6 +26,8 @@
DEFINE_PER_CPU(int, cpu_state);
+#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
+
static void *ipi_set0_regs[16];
static void *ipi_clear0_regs[16];
static void *ipi_status0_regs[16];
@@ -302,20 +305,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
ipi_write_action(cpu_logical_map(i), (u32)action);
}
-#define IPI_IRQ_OFFSET 6
-
-void loongson3_send_irq_by_ipi(int cpu, int irqs)
-{
- ipi_write_action(cpu_logical_map(cpu), irqs << IPI_IRQ_OFFSET);
-}
-void loongson3_ipi_interrupt(struct pt_regs *regs)
+static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
{
int i, cpu = smp_processor_id();
- unsigned int action, c0count, irqs;
+ unsigned int action, c0count;
action = ipi_read_clear(cpu);
- irqs = action >> IPI_IRQ_OFFSET;
if (action & SMP_RESCHEDULE_YOURSELF)
scheduler_ipi();
@@ -335,13 +331,7 @@ void loongson3_ipi_interrupt(struct pt_regs *regs)
__wbflush(); /* Let others see the result ASAP */
}
- if (irqs) {
- int irq;
- while ((irq = ffs(irqs))) {
- do_IRQ(irq-1);
- irqs &= ~(1<<(irq-1));
- }
- }
+ return IRQ_HANDLED;
}
#define MAX_LOOPS 800
@@ -438,6 +428,9 @@ static void __init loongson3_smp_setup(void)
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
{
+ if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
+ pr_err("Failed to request IPI IRQ\n");
init_cpu_present(cpu_possible_mask);
per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
}
@@ -484,7 +477,8 @@ static int loongson3_cpu_disable(void)
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
local_irq_save(flags);
- fixup_irqs();
+ irq_cpu_offline();
+ clear_c0_status(ST0_IM);
local_irq_restore(flags);
local_flush_tlb_all();
--
2.26.0.rc2
Prepare for later dts.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
--
v4-v5:
Remove unnecessary kernel details.
---
.../bindings/mips/loongson/devices.yaml | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
new file mode 100644
index 000000000000..b1f811e251f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson based Platforms Device Tree Bindings
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+description: |
+ Devices with a Loongson CPU shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Generic Loongson3 4Core + RS780E
+ items:
+ - const: loongson,loongson3-4core-rs780e
+
+ - description: Generic Loongson3 8Core + RS780E
+ items:
+ - const: loongson,loongson3-8core-rs780e
+...
--
2.26.0.rc2
To prevent CPU IRQ collide with PCH IRQ, we move down
CPU IRQ BASE to 16.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 12208119aac0..1ce2e0bbe305 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -5,7 +5,7 @@
#include <boot_param.h>
/* cpu core interrupt numbers */
-#define MIPS_CPU_IRQ_BASE 56
+#define MIPS_CPU_IRQ_BASE 16
#include_next <irq.h>
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
--
2.26.0.rc2
Load proper dtb according to firmware passed parameters and
CPU PRID.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../asm/mach-loongson64/builtin_dtbs.h | 13 +++++++++++
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/env.c | 23 +++++++++++++++++++
arch/mips/loongson64/setup.c | 16 +++++++++++++
4 files changed, 53 insertions(+)
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
new file mode 100644
index 000000000000..853c6d80887b
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Built-in Generic dtbs for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+
+extern u32 __dtb_loongson3_4core_rs780e_begin[];
+extern u32 __dtb_loongson3_8core_rs780e_begin[];
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index a8fce112a9b0..fde1b75c45ea 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -25,6 +25,7 @@ extern const struct plat_smp_ops loongson3_smp_ops;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
extern void __init prom_init_env(void);
+extern void *loongson_fdt_blob;
/* irq operation functions */
extern void mach_irq_dispatch(unsigned int pending);
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 0daeb7bcf023..2554ef11170d 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -17,6 +17,7 @@
#include <asm/bootinfo.h>
#include <loongson.h>
#include <boot_param.h>
+#include <builtin_dtbs.h>
#include <workarounds.h>
u32 cpu_clock_freq;
@@ -120,6 +121,28 @@ void __init prom_init_env(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
+ break;
+ default:
+ break;
+ }
+ }
+
+
+ if (!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
+
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
index 4fd27f4f90ed..6fe3ffffcaa6 100644
--- a/arch/mips/loongson64/setup.c
+++ b/arch/mips/loongson64/setup.c
@@ -8,9 +8,15 @@
#include <asm/wbflush.h>
#include <asm/bootinfo.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
#include <loongson.h>
+void *loongson_fdt_blob;
+
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
@@ -27,4 +33,14 @@ EXPORT_SYMBOL(__wbflush);
void __init plat_mem_setup(void)
{
+ if (loongson_fdt_blob)
+ __dt_setup_arch(loongson_fdt_blob);
+}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
}
--
2.26.0.rc2
The old code is using legacy domain to setup irq_domain for CPU interrupts
which requires irq_desc to be preallocated.
However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up
unallocated and lead to incorrect behavior.
Thus we convert the legacy domain to simple domain which can allocate irq_desc
during initialization.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..c3cf7fa76424 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+ irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
&mips_cpu_intc_irq_domain_ops,
NULL);
if (!irq_domain)
--
2.26.0.rc2
On Wed, 18 Mar 2020 14:20:36 +0800, Jiaxun Yang wrote:
>
> Prepare for later dts.
>
> Co-developed-by: Huacai Chen <[email protected]>
> Signed-off-by: Jiaxun Yang <[email protected]>
>
> --
> v4-v5:
> Remove unnecessary kernel details.
> ---
> .../bindings/mips/loongson/devices.yaml | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On 2020-03-18 06:20, Jiaxun Yang wrote:
> This controller appeared on Loongson-3 family of chips to receive
> interrupts
> from PCH PIC.
> It is a I8259 with optimized interrupt polling flow. We can poll
> interrupt number
> from HT vector directly but still have to follow standard I8259
> routines to mask,
> unmask and EOI.
>
> Co-developed-by: Huacai Chen <[email protected]>
> Signed-off-by: Jiaxun Yang <[email protected]>
>
> ---
> v4-v5:
> Enhancements according to maz's suggestions:
> - Add static for private struct
> - Drop pointless rename
> - Fix DT parse bug
> - Clarifications in comments and commit message
> ---
> arch/mips/include/asm/i8259.h | 1 +
> drivers/irqchip/Kconfig | 10 ++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-loongson-htpic.c | 149 +++++++++++++++++++++++++++
> 4 files changed, 161 insertions(+)
> create mode 100644 drivers/irqchip/irq-loongson-htpic.c
[...]
> +int __init htpic_of_init(struct device_node *node, struct device_node
> *parent)
> +{
> + unsigned int parent_irq[4];
> + int i, err;
> + int num_parents = 0;
> +
> + if (htpic) {
> + pr_err("loongson-htpic: Only one HTPIC is allowed in the system\n");
> + return -ENODEV;
> + }
> +
> + htpic = kzalloc(sizeof(*htpic), GFP_KERNEL);
> + if (!htpic) {
> + err = -ENOMEM;
> + goto out_free;
> + }
> +
> + htpic->base = of_iomap(node, 0);
> + if (!htpic->base) {
> + err = -ENODEV;
> + goto out_free;
> + }
> +
> + htpic->domain = __init_i8259_irqs(node);
> + if (!htpic->domain) {
> + pr_err("loongson-htpic: Failed to initialize i8259 IRQs\n");
> + err = -ENOMEM;
> + goto out_iounmap;
> + }
> +
> + /* Interrupt may come from any of the 4 interrupt line */
> + for (i = 0; i < HTPIC_MAX_PARENT_IRQ; i++) {
> + parent_irq[i] = irq_of_parse_and_map(node, i);
> + if (parent_irq[i] < 0)
irq_of_parse_and_map() returns 0 when there is no interrupt to be
mapped. You should probably test for that too.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
Hi Jiaxun,
On 2020年03月18日 14:20, Jiaxun Yang wrote:
> Prepare for later dts.
>
> Co-developed-by: Huacai Chen <[email protected]>
> Signed-off-by: Jiaxun Yang <[email protected]>
>
> --
> v4-v5:
> Remove unnecessary kernel details.
> ---
> .../bindings/mips/loongson/devices.yaml | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
>
> diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> new file mode 100644
> index 000000000000..b1f811e251f1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
> @@ -0,0 +1,27 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson based Platforms Device Tree Bindings
> +
> +maintainers:
> + - Jiaxun Yang <[email protected]>
> +description: |
> + Devices with a Loongson CPU shall have the following properties.
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> +
> + - description: Generic Loongson3 4Core + RS780E
Maybe "Quad Core" and "Octal Core" are better.
> + items:
> + - const: loongson,loongson3-4core-rs780e
> +
> + - description: Generic Loongson3 8Core + RS780E
> + items:
> + - const: loongson,loongson3-8core-rs780e
> +...
Loongson have a long history of contributing their code to mainline kernel.
However, it seems like recent years, they are focusing on maintain a kernel by themselves
rather than contribute there code to the community.
Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
maintainance and became outdated.
This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
Loongson 2e/f alone since they are too legacy to touch.
PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
v1:
- dt-bindings fixup according to Rob's comments
- irqchip fixup according to Marc's comments
- ls3-iointc: Make Core&IP map per-IRQ
- Regenerate kconfigs
- Typo & style improvements
v2:
- dt-bindings: Fix IOINTC, collect Rob's review tag
- dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
v3:
- Split code have been merged
- Fix IOINTC binding to allow map any child IRQ to and parent
- Convert "HTINTC" into "HTPIC", which mixed HT vectors processing and i8259
- Naming style fix according to Huacai's suggestions
v4:
- More naming related fixes
v5:
- irqchip fixes thanks to maz (see per file changelog)
- Remove unnecessary details in dt-bindings
- Credit Huacai with Co-developed-by
v6:
- HTPIC minor fix
- device binding naming fix
---
Jiaxun Yang (11):
irqchip: Add driver for Loongson I/O Local Interrupt Controller
irqchip: loongson-liointc: Workaround LPC IRQ Errata
dt-bindings: interrupt-controller: Add Loongson LIOINTC
irqchip: Add driver for Loongson-3 HyperTransport PIC controller
dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson boards
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE
.../interrupt-controller/loongson,htpic.yaml | 59 ++++
.../loongson,liointc.yaml | 93 ++++++
.../bindings/mips/loongson/devices.yaml | 27 ++
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 +
.../boot/dts/loongson/loongson3-package.dtsi | 62 ++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++
arch/mips/include/asm/i8259.h | 1 +
.../include/asm/mach-loongson64/boot_param.h | 2 +
.../asm/mach-loongson64/builtin_dtbs.h | 13 +
arch/mips/include/asm/mach-loongson64/irq.h | 32 +--
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/env.c | 23 ++
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 -----------
arch/mips/loongson64/setup.c | 16 ++
arch/mips/loongson64/smp.c | 28 +-
drivers/irqchip/Kconfig | 19 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-loongson-htpic.c | 149 ++++++++++
drivers/irqchip/irq-loongson-liointc.c | 271 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
26 files changed, 844 insertions(+), 213 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/loongson64/irq.c
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
--
2.26.0.rc2
Document Loongson I/O Interrupt controller.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../loongson,liointc.yaml | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
new file mode 100644
index 000000000000..9c6b91fee477
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson Local I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt controller which can route local I/O interrupt to interrupt lines
+ of cores.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,liointc-1.0
+ - const: loongson,liointc-1.0a
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ description:
+ Interrupt source of the CPU interrupts.
+ minItems: 1
+ maxItems: 4
+
+ interrupt-names:
+ description: List of names for the parent interrupts.
+ items:
+ - const: int0
+ - const: int1
+ - const: int2
+ - const: int3
+ minItems: 1
+ maxItems: 4
+
+ '#interrupt-cells':
+ const: 2
+
+ 'loongson,parent_int_map':
+ description: |
+ This property points how the children interrupts will be mapped into CPU
+ interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
+ and each bit in the cell refers to a children interrupt fron 0 to 31.
+ If a CPU interrupt line didn't connected with liointc, then keep it's
+ cell with zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - items:
+ minItems: 4
+ maxItems: 4
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - 'loongson,parent_int_map'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+...
--
2.26.0.rc2
This controller appeared on Loongson family of chips as the primary
package interrupt source.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
v4-v5:
Resolve suggestions from maz:
- Remove DT validation
- Simplify unnucessary functions & variables
---
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-liointc.c | 259 +++++++++++++++++++++++++
3 files changed, 269 insertions(+)
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 6d397732138d..c609eaa319d2 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER
Say yes here to add support for the IRQ combiner devices embedded
in Samsung Exynos chips.
+config LOONGSON_LIOINTC
+ bool "Loongson Local I/O Interrupt Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson Local I/O Interrupt Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index eae0d78cbf22..5e7678efdfe6 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
+obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
new file mode 100644
index 000000000000..8b6d7b8ddaca
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <[email protected]>
+ * Loongson Local IO Interrupt Controller support
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/irqchip/chained_irq.h>
+
+#include <boot_param.h>
+
+#define LIOINTC_CHIP_IRQ 32
+#define LIOINTC_NUM_PARENT 4
+
+#define LIOINTC_INTC_CHIP_START 0x20
+
+#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
+#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
+#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
+#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
+#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
+#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
+
+#define LIOINTC_SHIFT_INTx 4
+
+struct liointc_handler_data {
+ struct liointc_priv *priv;
+ u32 parent_int_map;
+};
+
+struct liointc_priv {
+ struct irq_chip_generic *gc;
+ struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
+ u8 map_cache[LIOINTC_CHIP_IRQ];
+};
+
+static void liointc_chained_handle_irq(struct irq_desc *desc)
+{
+ struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct irq_chip_generic *gc = handler->priv->gc;
+ u32 pending;
+
+ chained_irq_enter(chip, desc);
+
+ pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ generic_handle_irq(irq_find_mapping(gc->domain, bit));
+ pending &= ~BIT(bit);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void liointc_set_bit(struct irq_chip_generic *gc,
+ unsigned int offset,
+ u32 mask, bool set)
+{
+ if (set)
+ writel(readl(gc->reg_base + offset) | mask,
+ gc->reg_base + offset);
+ else
+ writel(readl(gc->reg_base + offset) & ~mask,
+ gc->reg_base + offset);
+}
+
+static int liointc_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ u32 mask = data->mask;
+ unsigned long flags;
+
+ irq_gc_lock_irqsave(gc, flags);
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ default:
+ return -EINVAL;
+ }
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ irqd_set_trigger_type(data, type);
+ return 0;
+}
+
+static void liointc_resume(struct irq_chip_generic *gc)
+{
+ struct liointc_priv *priv = gc->private;
+ unsigned long flags;
+ int i;
+
+ irq_gc_lock_irqsave(gc, flags);
+ /* Disable all at first */
+ writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
+ /* Revert map cache */
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
+ writeb(priv->map_cache[i], gc->reg_base + i);
+ /* Revert mask cache */
+ writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
+ irq_gc_unlock_irqrestore(gc, flags);
+}
+
+static const char const *parent_names[] = {"int0", "int1", "int2", "int3"};
+
+int __init liointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_domain *domain;
+ struct irq_chip_type *ct;
+ struct liointc_priv *priv;
+ void __iomem *base;
+ u32 of_parent_int_map[LIOINTC_NUM_PARENT];
+ int parent_irq[LIOINTC_NUM_PARENT];
+ bool have_parent = FALSE;
+ int sz, i, err = 0;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
+ if (parent_irq[i] > 0)
+ have_parent = TRUE;
+ }
+ if (!have_parent) {
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ sz = of_property_read_variable_u32_array(node, "loongson,parent_int_map",
+ &of_parent_int_map[0], LIOINTC_NUM_PARENT,
+ LIOINTC_NUM_PARENT);
+ if (sz < 4) {
+ pr_err("loongson-liointc: No parent_int_map\n");
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++)
+ priv->handler[i].parent_int_map = of_parent_int_map[i];
+
+ /* Setup IRQ domain */
+ domain = irq_domain_add_linear(node, 32,
+ &irq_generic_chip_ops, priv);
+ if (!domain) {
+ pr_err("loongson-liointc: cannot add IRQ domain\n");
+ err = -EINVAL;
+ goto out_iounmap;
+ }
+
+ err = irq_alloc_domain_generic_chips(domain, 32, 1,
+ node->full_name, handle_level_irq,
+ IRQ_NOPROBE, 0, 0);
+ if (err) {
+ pr_err("loongson-liointc: unable to register IRQ domain\n");
+ goto out_free_domain;
+ }
+
+
+ /* Disable all IRQs */
+ writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
+ /* Set to level triggered */
+ writel(0x0, base + LIOINTC_REG_INTC_EDGE);
+
+ /* Generate parent INT part of map cache */
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ u32 pending = priv->handler[i].parent_int_map;
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
+ pending &= ~BIT(bit);
+ }
+ }
+
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
+ /* Generate core part of map cache */
+ priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
+ writeb(priv->map_cache[i], base + i);
+ }
+
+ gc = irq_get_domain_generic_chip(domain, 0);
+ gc->private = priv;
+ gc->reg_base = base;
+ gc->domain = domain;
+ gc->resume = liointc_resume;
+
+ ct = gc->chip_types;
+ ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
+ ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
+ ct->chip.irq_set_type = liointc_set_type;
+
+ gc->mask_cache = 0xffffffff;
+ priv->gc = gc;
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ if (parent_irq[i] <= 0)
+ continue;
+
+ priv->handler[i].priv = priv;
+ irq_set_chained_handler_and_data(parent_irq[i],
+ liointc_chained_handle_irq, &priv->handler[i]);
+ }
+
+ return 0;
+
+out_free_domain:
+ irq_domain_remove(domain);
+out_iounmap:
+ iounmap(base);
+out_free_priv:
+ kfree(priv);
+
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
+IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
--
2.26.0.rc2
The 1.0 version of that controller has a bug that status bit
of LPC IRQ sometimes doesn't get set correctly.
So we can always blame LPC IRQ when spurious interrupt happens
at the parent interrupt line which LPC IRQ supposed to route
to.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-loongson-liointc.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 8b6d7b8ddaca..d5054e90eab8 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -32,6 +32,8 @@
#define LIOINTC_SHIFT_INTx 4
+#define LIOINTC_ERRATA_IRQ 10
+
struct liointc_handler_data {
struct liointc_priv *priv;
u32 parent_int_map;
@@ -41,6 +43,7 @@ struct liointc_priv {
struct irq_chip_generic *gc;
struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
u8 map_cache[LIOINTC_CHIP_IRQ];
+ bool have_lpc_irq_errata;
};
static void liointc_chained_handle_irq(struct irq_desc *desc)
@@ -54,8 +57,14 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
- if (!pending)
- spurious_interrupt();
+ if (!pending) {
+ /* Always blame LPC IRQ if we have that bug and LPC IRQ is enabled */
+ if (handler->priv->have_lpc_irq_errata &&
+ (handler->parent_int_map & ~gc->mask_cache & BIT(LIOINTC_ERRATA_IRQ)))
+ pending = BIT(LIOINTC_ERRATA_IRQ);
+ else
+ spurious_interrupt();
+ }
while (pending) {
int bit = __ffs(pending);
@@ -164,6 +173,9 @@ int __init liointc_of_init(struct device_node *node,
goto out_iounmap;
}
+ if (of_device_is_compatible(node, "loongson,liointc-1.0"))
+ priv->have_lpc_irq_errata = true;
+
sz = of_property_read_variable_u32_array(node, "loongson,parent_int_map",
&of_parent_int_map[0], LIOINTC_NUM_PARENT,
LIOINTC_NUM_PARENT);
--
2.26.0.rc2
Prepare for later dts.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
--
v4-v5:
Remove unnecessary kernel details.
v5-v6:
Use quad & octa instead of 4 and 8.
---
.../bindings/mips/loongson/devices.yaml | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
new file mode 100644
index 000000000000..74ed4e397a78
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson based Platforms Device Tree Bindings
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+description: |
+ Devices with a Loongson CPU shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Generic Loongson3 Quad Core + RS780E
+ items:
+ - const: loongson,loongson3-4core-rs780e
+
+ - description: Generic Loongson3 Octa Core + RS780E
+ items:
+ - const: loongson,loongson3-8core-rs780e
+...
--
2.26.0.rc2
Document Loongson-3 HyperTransport PIC controller.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../interrupt-controller/loongson,htpic.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
new file mode 100644
index 000000000000..c8861cbbb8b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 HyperTransport Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips to transmit
+ interrupts from PCH PIC connected on HyperTransport bus.
+
+properties:
+ compatible:
+ const: loongson,htpic-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ description: |
+ Four parent interrupts that receive chained interrupts.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ htintc: interrupt-controller@1fb000080 {
+ compatible = "loongson,htintc-1.0";
+ reg = <0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.26.0.rc2
We've made generic irqchip drivers for Loongson-3 platform, it's time
to say goodbye to these legacy code.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../include/asm/mach-loongson64/boot_param.h | 2 +
arch/mips/include/asm/mach-loongson64/irq.h | 30 +---
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 ------------------
arch/mips/loongson64/smp.c | 28 ++-
6 files changed, 21 insertions(+), 209 deletions(-)
delete mode 100644 arch/mips/loongson64/irq.c
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index 8c286bedff3e..2ed483e32d8c 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -2,6 +2,8 @@
#ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
#define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
+#include <linux/types.h>
+
#define SYSTEM_RAM_LOW 1
#define SYSTEM_RAM_HIGH 2
#define SYSTEM_RAM_RESERVED 3
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 0d3955616e42..d41dc4a76e6d 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -7,34 +7,6 @@
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
-#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
-#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
-#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
-
-#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
-#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80)
-#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0)
-#define LOONGSON_HT1_INT_VECTOR(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
-#define LOONGSON_HT1_INTN_EN(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
-
-#define LOONGSON_INT_ROUTER_OFFSET 0x1400
-#define LOONGSON_INT_ROUTER_INTEN \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
-#define LOONGSON_INT_ROUTER_INTENSET \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
-#define LOONGSON_INT_ROUTER_INTENCLR \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
-#define LOONGSON_INT_ROUTER_ENTRY(n) \
- LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
-#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
-#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
-
-#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
-
-extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(struct pt_regs *regs);
-
#include <asm/mach-generic/irq.h>
+
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 7821891bc5d0..b7f40b179c71 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -2,7 +2,7 @@
#
# Makefile for Loongson-3 family machines
#
-obj-$(CONFIG_MACH_LOONGSON64) += irq.o cop2-ex.o platform.o acpi_init.o dma.o \
+obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \
setup.o init.o env.o time.o reset.o \
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index 5ac1a0f35ca4..da38944471f4 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -4,6 +4,7 @@
* Author: Wu Zhangjin, [email protected]
*/
+#include <linux/irqchip.h>
#include <linux/memblock.h>
#include <asm/bootinfo.h>
#include <asm/traps.h>
@@ -44,3 +45,8 @@ void __init prom_init(void)
void __init prom_free_prom_memory(void)
{
}
+
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c
deleted file mode 100644
index 79ad797497e4..000000000000
--- a/arch/mips/loongson64/irq.c
+++ /dev/null
@@ -1,162 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <loongson.h>
-#include <irq.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/i8259.h>
-#include <asm/mipsregs.h>
-
-#include "smp.h"
-
-extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
-
-unsigned int irq_cpu[16] = {[0 ... 15] = -1};
-unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
-unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
-
-int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
- bool force)
-{
- unsigned int cpu;
- struct cpumask new_affinity;
-
- /* I/O devices are connected on package-0 */
- cpumask_copy(&new_affinity, affinity);
- for_each_cpu(cpu, affinity)
- if (cpu_data[cpu].package > 0)
- cpumask_clear_cpu(cpu, &new_affinity);
-
- if (cpumask_empty(&new_affinity))
- return -EINVAL;
-
- cpumask_copy(d->common->affinity, &new_affinity);
-
- return IRQ_SET_MASK_OK_NOCOPY;
-}
-
-static void ht_irqdispatch(void)
-{
- unsigned int i, irq;
- struct irq_data *irqd;
- struct cpumask affinity;
-
- irq = LOONGSON_HT1_INT_VECTOR(0);
- LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
-
- for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
- if (!(irq & (0x1 << ht_irq[i])))
- continue;
-
- /* handled by local core */
- if (local_irq & (0x1 << ht_irq[i])) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irqd = irq_get_irq_data(ht_irq[i]);
- cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
- if (cpumask_empty(&affinity)) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
- if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
- irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
-
- if (irq_cpu[ht_irq[i]] == 0) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- /* balanced by other cores */
- loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
- }
-}
-
-#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & CAUSEF_IP7)
- do_IRQ(LOONGSON_TIMER_IRQ);
-#if defined(CONFIG_SMP)
- if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt(NULL);
-#endif
- if (pending & CAUSEF_IP3)
- ht_irqdispatch();
- if (pending & CAUSEF_IP2)
- do_IRQ(LOONGSON_UART_IRQ);
- if (pending & UNUSED_IPS) {
- pr_err("%s : spurious interrupt\n", __func__);
- spurious_interrupt();
- }
-}
-
-static inline void mask_loongson_irq(struct irq_data *d) { }
-static inline void unmask_loongson_irq(struct irq_data *d) { }
-
- /* For MIPS IRQs which shared by all cores */
-static struct irq_chip loongson_irq_chip = {
- .name = "Loongson",
- .irq_ack = mask_loongson_irq,
- .irq_mask = mask_loongson_irq,
- .irq_mask_ack = mask_loongson_irq,
- .irq_unmask = unmask_loongson_irq,
- .irq_eoi = unmask_loongson_irq,
-};
-
-void irq_router_init(void)
-{
- int i;
-
- /* route LPC int to cpu core0 int 0 */
- LOONGSON_INT_ROUTER_LPC =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
- /* route HT1 int0 ~ int7 to cpu core0 INT1*/
- for (i = 0; i < 8; i++)
- LOONGSON_INT_ROUTER_HT1(i) =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
- /* enable HT1 interrupt */
- LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
- /* enable router interrupt intenset */
- LOONGSON_INT_ROUTER_INTENSET =
- LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
-}
-
-void __init arch_init_irq(void)
-{
- struct irq_chip *chip;
-
- clear_c0_status(ST0_IM | ST0_BEV);
-
- irq_router_init();
- mips_cpu_irq_init();
- init_i8259_irqs();
- chip = irq_get_chip(I8259A_IRQ_BASE);
- chip->irq_set_affinity = plat_set_irq_affinity;
-
- irq_set_chip_and_handler(LOONGSON_UART_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
- irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
-
- set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-
-void fixup_irqs(void)
-{
- irq_cpu_offline();
- clear_c0_status(ST0_IM);
-}
-
-#endif
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index de8e0741ce2d..e1fe8bbb377d 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -4,6 +4,7 @@
* Author: Chen Huacai, [email protected]
*/
+#include <irq.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/sched.h>
@@ -25,6 +26,8 @@
DEFINE_PER_CPU(int, cpu_state);
+#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
+
static void *ipi_set0_regs[16];
static void *ipi_clear0_regs[16];
static void *ipi_status0_regs[16];
@@ -302,20 +305,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
ipi_write_action(cpu_logical_map(i), (u32)action);
}
-#define IPI_IRQ_OFFSET 6
-
-void loongson3_send_irq_by_ipi(int cpu, int irqs)
-{
- ipi_write_action(cpu_logical_map(cpu), irqs << IPI_IRQ_OFFSET);
-}
-void loongson3_ipi_interrupt(struct pt_regs *regs)
+static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
{
int i, cpu = smp_processor_id();
- unsigned int action, c0count, irqs;
+ unsigned int action, c0count;
action = ipi_read_clear(cpu);
- irqs = action >> IPI_IRQ_OFFSET;
if (action & SMP_RESCHEDULE_YOURSELF)
scheduler_ipi();
@@ -335,13 +331,7 @@ void loongson3_ipi_interrupt(struct pt_regs *regs)
__wbflush(); /* Let others see the result ASAP */
}
- if (irqs) {
- int irq;
- while ((irq = ffs(irqs))) {
- do_IRQ(irq-1);
- irqs &= ~(1<<(irq-1));
- }
- }
+ return IRQ_HANDLED;
}
#define MAX_LOOPS 800
@@ -438,6 +428,9 @@ static void __init loongson3_smp_setup(void)
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
{
+ if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
+ pr_err("Failed to request IPI IRQ\n");
init_cpu_present(cpu_possible_mask);
per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
}
@@ -484,7 +477,8 @@ static int loongson3_cpu_disable(void)
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
local_irq_save(flags);
- fixup_irqs();
+ irq_cpu_offline();
+ clear_c0_status(ST0_IM);
local_irq_restore(flags);
local_flush_tlb_all();
--
2.26.0.rc2
Add generic device dts for Loongson-3 devices.
They are currently almost identical but will be different later.
Some PCH devices like PCI Host Bridge is still enabled by platform
code for now.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 ++
.../boot/dts/loongson/loongson3-package.dtsi | 62 +++++++++++++++++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++
7 files changed, 147 insertions(+), 2 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ca3045b2a2d9..4a0b2f494d79 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -486,9 +486,11 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
- select LOONGSON_MC146818
select ZONE_DMA32
select NUMA
+ select COMMON_CLK
+ select USE_OF
+ select BUILTIN_DTB
help
This enables the support of Loongson-2/3 family of machines.
@@ -3081,7 +3083,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && \
+ !MACH_LOONGSON64 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..d429a69bfe30 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
+subdir-y += loongson
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000000..56d379471262
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,4 @@
+# SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
new file mode 100644
index 000000000000..d09c313603f1
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package0: bus@1fe00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 /* 3A HT Config Space */
+ 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000 /* 3B HT Config Space */>;
+
+ liointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&liointc>;
+ no-loopback-test;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
new file mode 100644
index 000000000000..6b5694ca0f95
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-4core-rs780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
new file mode 100644
index 000000000000..ffefa2f829b0
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-8core-rs780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@1efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0x1efd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
new file mode 100644
index 000000000000..45c54d555fa4
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x10000000 0 0x10000000 0 0x10000000
+ 0 0x40000000 0 0x40000000 0 0x40000000
+ 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
+
+ isa {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0 0x1000>;
+
+ rtc0: rtc@70 {
+ compatible = "motorola,mc146818";
+ reg = <1 0x70 0x8>;
+ interrupts = <8>;
+ interrupt-parent = <&htpic>;
+ };
+ };
+ };
+};
--
2.26.0.rc2
The old code is using legacy domain to setup irq_domain for CPU interrupts
which requires irq_desc to be preallocated.
However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up
unallocated and lead to incorrect behavior.
Thus we convert the legacy domain to simple domain which can allocate irq_desc
during initialization.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..c3cf7fa76424 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+ irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
&mips_cpu_intc_irq_domain_ops,
NULL);
if (!irq_domain)
--
2.26.0.rc2
Load proper dtb according to firmware passed parameters and
CPU PRID.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../asm/mach-loongson64/builtin_dtbs.h | 13 +++++++++++
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/env.c | 23 +++++++++++++++++++
arch/mips/loongson64/setup.c | 16 +++++++++++++
4 files changed, 53 insertions(+)
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
new file mode 100644
index 000000000000..853c6d80887b
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Built-in Generic dtbs for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+
+extern u32 __dtb_loongson3_4core_rs780e_begin[];
+extern u32 __dtb_loongson3_8core_rs780e_begin[];
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index a8fce112a9b0..fde1b75c45ea 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -25,6 +25,7 @@ extern const struct plat_smp_ops loongson3_smp_ops;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
extern void __init prom_init_env(void);
+extern void *loongson_fdt_blob;
/* irq operation functions */
extern void mach_irq_dispatch(unsigned int pending);
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 0daeb7bcf023..2554ef11170d 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -17,6 +17,7 @@
#include <asm/bootinfo.h>
#include <loongson.h>
#include <boot_param.h>
+#include <builtin_dtbs.h>
#include <workarounds.h>
u32 cpu_clock_freq;
@@ -120,6 +121,28 @@ void __init prom_init_env(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
+ break;
+ default:
+ break;
+ }
+ }
+
+
+ if (!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
+
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
index 4fd27f4f90ed..6fe3ffffcaa6 100644
--- a/arch/mips/loongson64/setup.c
+++ b/arch/mips/loongson64/setup.c
@@ -8,9 +8,15 @@
#include <asm/wbflush.h>
#include <asm/bootinfo.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
#include <loongson.h>
+void *loongson_fdt_blob;
+
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
@@ -27,4 +33,14 @@ EXPORT_SYMBOL(__wbflush);
void __init plat_mem_setup(void)
{
+ if (loongson_fdt_blob)
+ __dt_setup_arch(loongson_fdt_blob);
+}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
}
--
2.26.0.rc2
This controller appeared on Loongson-3 family of chips to receive interrupts
from PCH PIC.
It is a I8259 with optimized interrupt polling flow. We can poll interrupt number
from HT vector directly but still have to follow standard I8259 routines to mask,
unmask and EOI.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
v4-v5:
Enhancements according to maz's suggestions:
- Add static for private struct
- Drop pointless rename
- Fix DT parse bug
- Clarifications in comments and commit message
v5-v6:
Check parent_irq = 0 case.
---
arch/mips/include/asm/i8259.h | 1 +
drivers/irqchip/Kconfig | 10 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-htpic.c | 149 +++++++++++++++++++++++++++
4 files changed, 161 insertions(+)
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index 97a5e41ed1ab..a54b9649de22 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -36,6 +36,7 @@ extern raw_spinlock_t i8259A_lock;
extern void make_8259A_irq(unsigned int irq);
extern void init_i8259_irqs(void);
+extern struct irq_domain *__init_i8259_irqs(struct device_node *node);
/**
* i8159_set_poll() - Override the i8259 polling function
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c609eaa319d2..cae6f480c987 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -522,4 +522,14 @@ config LOONGSON_LIOINTC
help
Support for the Loongson Local I/O Interrupt Controller.
+config LOONGSON_HTPIC
+ bool "Loongson3 HyperTransport PIC Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ select I8259
+ help
+ Support for the Loongson-3 HyperTransport PIC Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 5e7678efdfe6..37bbe39bf909 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -106,3 +106,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
+obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c
new file mode 100644
index 000000000000..dd018c22ea83
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-htpic.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <[email protected]>
+ * Loongson HTPIC IRQ support
+ */
+
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <asm/i8259.h>
+
+#define HTPIC_MAX_PARENT_IRQ 4
+#define HTINT_NUM_VECTORS 8
+#define HTINT_EN_OFF 0x20
+
+struct loongson_htpic {
+ void __iomem *base;
+ struct irq_domain *domain;
+};
+
+static struct loongson_htpic *htpic;
+
+static void htpic_irq_dispatch(struct irq_desc *desc)
+{
+ struct loongson_htpic *priv = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ uint32_t pending;
+
+ chained_irq_enter(chip, desc);
+ pending = readl(priv->base);
+ /* Ack all IRQs at once, otherwise IRQ flood might happen */
+ writel(pending, priv->base);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ if (unlikely(bit > 15)) {
+ spurious_interrupt();
+ break;
+ }
+
+ generic_handle_irq(irq_linear_revmap(priv->domain, bit));
+ pending &= ~BIT(bit);
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static void htpic_reg_init(void)
+{
+ int i;
+
+ for (i = 0; i < HTINT_NUM_VECTORS; i++) {
+ uint32_t val;
+
+ /* Disable all HT Vectors */
+ writel(0x0, htpic->base + HTINT_EN_OFF + i * 0x4);
+ val = readl(htpic->base + i * 0x4);
+ /* Ack all possible pending IRQs */
+ writel(GENMASK(31, 0), htpic->base + i * 0x4);
+ }
+
+ /* Enable 16 vectors for PIC */
+ writel(0xffff, htpic->base + HTINT_EN_OFF);
+}
+
+static void htpic_resume(void)
+{
+ htpic_reg_init();
+}
+
+struct syscore_ops htpic_syscore_ops = {
+ .resume = htpic_resume,
+};
+
+int __init htpic_of_init(struct device_node *node, struct device_node *parent)
+{
+ unsigned int parent_irq[4];
+ int i, err;
+ int num_parents = 0;
+
+ if (htpic) {
+ pr_err("loongson-htpic: Only one HTPIC is allowed in the system\n");
+ return -ENODEV;
+ }
+
+ htpic = kzalloc(sizeof(*htpic), GFP_KERNEL);
+ if (!htpic) {
+ err = -ENOMEM;
+ goto out_free;
+ }
+
+ htpic->base = of_iomap(node, 0);
+ if (!htpic->base) {
+ err = -ENODEV;
+ goto out_free;
+ }
+
+ htpic->domain = __init_i8259_irqs(node);
+ if (!htpic->domain) {
+ pr_err("loongson-htpic: Failed to initialize i8259 IRQs\n");
+ err = -ENOMEM;
+ goto out_iounmap;
+ }
+
+ /* Interrupt may come from any of the 4 interrupt line */
+ for (i = 0; i < HTPIC_MAX_PARENT_IRQ; i++) {
+ parent_irq[i] = irq_of_parse_and_map(node, i);
+ if (parent_irq[i] <= 0)
+ break;
+
+ num_parents++;
+ }
+
+ if (!num_parents) {
+ pr_err("loongson-htpic: Failed to get parent irqs\n");
+ err = -ENODEV;
+ goto out_remove_domain;
+ }
+
+ htpic_reg_init();
+
+ for (i = 0; i < num_parents; i++) {
+ irq_set_chained_handler_and_data(parent_irq[i],
+ htpic_irq_dispatch, htpic);
+ }
+
+ register_syscore_ops(&htpic_syscore_ops);
+
+ return 0;
+
+out_remove_domain:
+ irq_domain_remove(htpic->domain);
+out_iounmap:
+ iounmap(htpic->base);
+out_free:
+ kfree(htpic);
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_htpic, "loongson,htpic-1.0", htpic_of_init);
--
2.26.0.rc2
Jiaxun,
On Tue, 24 Mar 2020 23:35:57 +0800
Jiaxun Yang <[email protected]> wrote:
> Loongson have a long history of contributing their code to mainline kernel.
> However, it seems like recent years, they are focusing on maintain a kernel by themselves
> rather than contribute there code to the community.
>
> Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
> maintainance and became outdated.
>
> This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
> Loongson 2e/f alone since they are too legacy to touch.
>
> PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
>
> v1:
> - dt-bindings fixup according to Rob's comments
> - irqchip fixup according to Marc's comments
> - ls3-iointc: Make Core&IP map per-IRQ
> - Regenerate kconfigs
> - Typo & style improvements
>
> v2:
> - dt-bindings: Fix IOINTC, collect Rob's review tag
> - dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
>
> v3:
> - Split code have been merged
> - Fix IOINTC binding to allow map any child IRQ to and parent
> - Convert "HTINTC" into "HTPIC", which mixed HT vectors processing and i8259
> - Naming style fix according to Huacai's suggestions
>
> v4:
> - More naming related fixes
>
> v5:
> - irqchip fixes thanks to maz (see per file changelog)
> - Remove unnecessary details in dt-bindings
> - Credit Huacai with Co-developed-by
>
> v6:
> - HTPIC minor fix
> - device binding naming fix
>
> ---
> Jiaxun Yang (11):
> irqchip: Add driver for Loongson I/O Local Interrupt Controller
> irqchip: loongson-liointc: Workaround LPC IRQ Errata
> dt-bindings: interrupt-controller: Add Loongson LIOINTC
> irqchip: Add driver for Loongson-3 HyperTransport PIC controller
> dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
> irqchip: mips-cpu: Convert to simple domain
> MIPS: Loongson64: Drop legacy IRQ code
> dt-bindings: mips: Add loongson boards
> MIPS: Loongson64: Add generic dts
> MIPS: Loongson64: Load built-in dtbs
> MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE
[...]
How do you want to get these merged? I can take the first 6 patches
through the irqchip tree, and leave the rest to go via the MIPS tree.
Otherwise, if you plan to have the whole thing go via the MIPS tree,
please add my:
Reviewed-by: Marc Zyngier <[email protected]>
to patches 1, 2, 4 and 6.
Please let me know quickly, as I'd like to close the irqchip tree
tomorrow.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
To prevent CPU IRQ collide with PCH IRQ, we move down
CPU IRQ BASE to 16.
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index d41dc4a76e6d..0041bd490ab8 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -5,7 +5,7 @@
#include <boot_param.h>
/* cpu core interrupt numbers */
-#define MIPS_CPU_IRQ_BASE 56
+#define MIPS_CPU_IRQ_BASE 16
#include <asm/mach-generic/irq.h>
--
2.26.0.rc2
于 2020年3月24日 GMT+08:00 下午11:47:47, Marc Zyngier <[email protected]> 写到:
>Jiaxun,
>
>On Tue, 24 Mar 2020 23:35:57 +0800
>Jiaxun Yang <[email protected]> wrote:
>
>> Loongson have a long history of contributing their code to mainline
>kernel.
>> However, it seems like recent years, they are focusing on maintain a
>kernel by themselves
>> rather than contribute there code to the community.
>>
>> Kernel is progress rapidly too. Their code slept in mainline for a
>long peroid without proper
>> maintainance and became outdated.
>>
>> This patchset brings modern DeviceTree and irqchip support to the
>Loongson64 machine, and leaves
>> Loongson 2e/f alone since they are too legacy to touch.
>>
>> PCI and some legacy I/O device will be converted later, together with
>LS7A PCH support.
>>
>> v1:
>> - dt-bindings fixup according to Rob's comments
>> - irqchip fixup according to Marc's comments
>> - ls3-iointc: Make Core&IP map per-IRQ
>> - Regenerate kconfigs
>> - Typo & style improvements
>>
>> v2:
>> - dt-bindings: Fix IOINTC, collect Rob's review tag
>> - dtbs: Drop CPU Node, merge different ways according to Huacai and
>Paul's comments
>>
>> v3:
>> - Split code have been merged
>> - Fix IOINTC binding to allow map any child IRQ to and parent
>> - Convert "HTINTC" into "HTPIC", which mixed HT vectors processing
>and i8259
>> - Naming style fix according to Huacai's suggestions
>>
>> v4:
>> - More naming related fixes
>>
>> v5:
>> - irqchip fixes thanks to maz (see per file changelog)
>> - Remove unnecessary details in dt-bindings
>> - Credit Huacai with Co-developed-by
>>
>> v6:
>> - HTPIC minor fix
>> - device binding naming fix
>>
>> ---
>> Jiaxun Yang (11):
>> irqchip: Add driver for Loongson I/O Local Interrupt Controller
>> irqchip: loongson-liointc: Workaround LPC IRQ Errata
>> dt-bindings: interrupt-controller: Add Loongson LIOINTC
>> irqchip: Add driver for Loongson-3 HyperTransport PIC controller
>> dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
>> irqchip: mips-cpu: Convert to simple domain
>> MIPS: Loongson64: Drop legacy IRQ code
>> dt-bindings: mips: Add loongson boards
>> MIPS: Loongson64: Add generic dts
>> MIPS: Loongson64: Load built-in dtbs
>> MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE
>
>[...]
>
>How do you want to get these merged? I can take the first 6 patches
>through the irqchip tree, and leave the rest to go via the MIPS tree.
>
>Otherwise, if you plan to have the whole thing go via the MIPS tree,
>please add my:
>
>Reviewed-by: Marc Zyngier <[email protected]>
>
>to patches 1, 2, 4 and 6.
>
>Please let me know quickly, as I'd like to close the irqchip tree
>tomorrow.
I'd prefer all go through MIPS tree.
Thomas, could you please help with that?
Thanks.
>
>Thanks,
>
> M.
--
Jiaxun Yang
On Tue, Mar 24, 2020 at 11:51:18PM +0800, Jiaxun Yang wrote:
> >How do you want to get these merged? I can take the first 6 patches
> >through the irqchip tree, and leave the rest to go via the MIPS tree.
> >
> >Otherwise, if you plan to have the whole thing go via the MIPS tree,
> >please add my:
> >
> >Reviewed-by: Marc Zyngier <[email protected]>
> >
> >to patches 1, 2, 4 and 6.
> >
> >Please let me know quickly, as I'd like to close the irqchip tree
> >tomorrow.
>
> I'd prefer all go through MIPS tree.
>
> Thomas, could you please help with that?
I'm fine taking them. Could you please add Signed-offs from your
co-developer and look at the remaining checkpatch warnings ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
Hi, Jiaxun,
On Tue, Mar 24, 2020 at 11:39 PM Jiaxun Yang <[email protected]> wrote:
>
> The 1.0 version of that controller has a bug that status bit
> of LPC IRQ sometimes doesn't get set correctly.
>
> So we can always blame LPC IRQ when spurious interrupt happens
> at the parent interrupt line which LPC IRQ supposed to route
> to.
>
> Co-developed-by: Huacai Chen <[email protected]>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> drivers/irqchip/irq-loongson-liointc.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 8b6d7b8ddaca..d5054e90eab8 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -32,6 +32,8 @@
>
> #define LIOINTC_SHIFT_INTx 4
>
> +#define LIOINTC_ERRATA_IRQ 10
> +
> struct liointc_handler_data {
> struct liointc_priv *priv;
> u32 parent_int_map;
> @@ -41,6 +43,7 @@ struct liointc_priv {
> struct irq_chip_generic *gc;
> struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
> u8 map_cache[LIOINTC_CHIP_IRQ];
> + bool have_lpc_irq_errata;
Maybe has_lpc_irq_errata?
> };
>
> static void liointc_chained_handle_irq(struct irq_desc *desc)
> @@ -54,8 +57,14 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
>
> pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
>
> - if (!pending)
> - spurious_interrupt();
> + if (!pending) {
> + /* Always blame LPC IRQ if we have that bug and LPC IRQ is enabled */
> + if (handler->priv->have_lpc_irq_errata &&
> + (handler->parent_int_map & ~gc->mask_cache & BIT(LIOINTC_ERRATA_IRQ)))
> + pending = BIT(LIOINTC_ERRATA_IRQ);
> + else
> + spurious_interrupt();
> + }
>
> while (pending) {
> int bit = __ffs(pending);
> @@ -164,6 +173,9 @@ int __init liointc_of_init(struct device_node *node,
> goto out_iounmap;
> }
>
> + if (of_device_is_compatible(node, "loongson,liointc-1.0"))
> + priv->have_lpc_irq_errata = true;
> +
> sz = of_property_read_variable_u32_array(node, "loongson,parent_int_map",
> &of_parent_int_map[0], LIOINTC_NUM_PARENT,
> LIOINTC_NUM_PARENT);
> --
> 2.26.0.rc2
>
>
Regards,
Huacai Chen
Hi, Jiaxun,
On Tue, Mar 24, 2020 at 11:40 PM Jiaxun Yang <[email protected]> wrote:
>
> Add generic device dts for Loongson-3 devices.
> They are currently almost identical but will be different later.
> Some PCH devices like PCI Host Bridge is still enabled by platform
> code for now.
>
> Co-developed-by: Huacai Chen <[email protected]>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> arch/mips/Kconfig | 6 +-
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/loongson/Makefile | 4 ++
> .../boot/dts/loongson/loongson3-package.dtsi | 62 +++++++++++++++++++
> .../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++
> .../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++
> arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++
> 7 files changed, 147 insertions(+), 2 deletions(-)
> create mode 100644 arch/mips/boot/dts/loongson/Makefile
> create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
> create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index ca3045b2a2d9..4a0b2f494d79 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -486,9 +486,11 @@ config MACH_LOONGSON64
> select SYS_SUPPORTS_HIGHMEM
> select SYS_SUPPORTS_LITTLE_ENDIAN
> select SYS_SUPPORTS_ZBOOT
> - select LOONGSON_MC146818
> select ZONE_DMA32
> select NUMA
> + select COMMON_CLK
> + select USE_OF
> + select BUILTIN_DTB
> help
> This enables the support of Loongson-2/3 family of machines.
>
> @@ -3081,7 +3083,7 @@ endchoice
> choice
> prompt "Kernel command line type" if !CMDLINE_OVERRIDE
> default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
> - !MIPS_MALTA && \
> + !MACH_LOONGSON64 && !MIPS_MALTA && \
> !CAVIUM_OCTEON_SOC
> default MIPS_CMDLINE_FROM_BOOTLOADER
>
> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> index 1e79cab8e269..d429a69bfe30 100644
> --- a/arch/mips/boot/dts/Makefile
> +++ b/arch/mips/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += cavium-octeon
> subdir-y += img
> subdir-y += ingenic
> subdir-y += lantiq
> +subdir-y += loongson
> subdir-y += mscc
> subdir-y += mti
> subdir-y += netlogic
> diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
> new file mode 100644
> index 000000000000..56d379471262
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX_License_Identifier: GPL_2.0
> +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb
> +
> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
> new file mode 100644
> index 000000000000..d09c313603f1
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
> @@ -0,0 +1,62 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
I still add something like this here:
cpu@0 {
compatible = "loongson,loongson3";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&scache0>;
};
Because it at least solve the problem of cache hierarchy, which cause
"lscpu" crash.
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + package0: bus@1fe00000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
> + 0 0x3ff00000 0 0x3ff00000 0x100000
> + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 /* 3A HT Config Space */
> + 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000 /* 3B HT Config Space */>;
> +
> + liointc: interrupt-controller@3ff01400 {
> + compatible = "loongson,liointc-1.0";
> + reg = <0 0x3ff01400 0x64>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>, <3>;
> + interrupt-names = "int0", "int1";
> +
> + loongson,parent_int_map = <0xf0ffffff>, /* int0 */
> + <0x0f000000>, /* int1 */
> + <0x00000000>, /* int2 */
> + <0x00000000>; /* int3 */
> +
> + };
> +
> + cpu_uart0: serial@1fe001e0 {
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e0 0x8>;
> + clock-frequency = <33000000>;
> + interrupt-parent = <&liointc>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + no-loopback-test;
> + };
> +
> + cpu_uart1: serial@1fe001e8 {
> + status = "disabled";
Why disable UART1 by default, is it cause problems?
> + compatible = "ns16550a";
> + reg = <0 0x1fe001e8 0x8>;
> + clock-frequency = <33000000>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&liointc>;
> + no-loopback-test;
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
> new file mode 100644
> index 000000000000..6b5694ca0f95
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "loongson3-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,loongson3-4core-rs780e";
> +};
> +
> +&package0 {
> + htpic: interrupt-controller@efdfb000080 {
> + compatible = "loongson,htpic-1.0";
> + reg = <0xefd 0xfb000080 0x40>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&liointc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> + <25 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
> new file mode 100644
> index 000000000000..ffefa2f829b0
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "loongson3-package.dtsi"
> +#include "rs780e-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,loongson3-8core-rs780e";
> +};
> +
> +&package0 {
> + htpic: interrupt-controller@1efdfb000080 {
> + compatible = "loongson,htpic-1.0";
> + reg = <0x1efd 0xfb000080 0x40>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&liointc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> + <25 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> new file mode 100644
> index 000000000000..45c54d555fa4
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> @@ -0,0 +1,26 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/ {
> + bus@10000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0x10000000 0 0x10000000 0 0x10000000
> + 0 0x40000000 0 0x40000000 0 0x40000000
> + 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
> +
> + isa {
> + compatible = "isa";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <1 0 0 0 0x1000>;
> +
> + rtc0: rtc@70 {
> + compatible = "motorola,mc146818";
> + reg = <1 0x70 0x8>;
> + interrupts = <8>;
> + interrupt-parent = <&htpic>;
> + };
> + };
> + };
> +};
> --
> 2.26.0.rc2
>
>
Regards,
Huacai
于 2020年3月25日 GMT+08:00 上午10:11:05, Huacai Chen <[email protected]> 写到:
>Hi, Jiaxun,
>
>On Tue, Mar 24, 2020 at 11:40 PM Jiaxun Yang <[email protected]>
>wrote:
>>
>> Add generic device dts for Loongson-3 devices.
>> They are currently almost identical but will be different later.
>> Some PCH devices like PCI Host Bridge is still enabled by platform
>> code for now.
>>
>> Co-developed-by: Huacai Chen <[email protected]>
>> Signed-off-by: Jiaxun Yang <[email protected]>
>> ---
>> arch/mips/Kconfig | 6 +-
>> arch/mips/boot/dts/Makefile | 1 +
>> arch/mips/boot/dts/loongson/Makefile | 4 ++
>> .../boot/dts/loongson/loongson3-package.dtsi | 62
>+++++++++++++++++++
>> .../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++
>> .../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++
>> arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++
>> 7 files changed, 147 insertions(+), 2 deletions(-)
>> create mode 100644 arch/mips/boot/dts/loongson/Makefile
>> create mode 100644
>arch/mips/boot/dts/loongson/loongson3-package.dtsi
>> create mode 100644
>arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
>> create mode 100644
>arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
>> create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index ca3045b2a2d9..4a0b2f494d79 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -486,9 +486,11 @@ config MACH_LOONGSON64
>> select SYS_SUPPORTS_HIGHMEM
>> select SYS_SUPPORTS_LITTLE_ENDIAN
>> select SYS_SUPPORTS_ZBOOT
>> - select LOONGSON_MC146818
>> select ZONE_DMA32
>> select NUMA
>> + select COMMON_CLK
>> + select USE_OF
>> + select BUILTIN_DTB
>> help
>> This enables the support of Loongson-2/3 family of
>machines.
>>
>> @@ -3081,7 +3083,7 @@ endchoice
>> choice
>> prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 &&
>!MACH_INGENIC && \
>> - !MIPS_MALTA && \
>> + !MACH_LOONGSON64 &&
>!MIPS_MALTA && \
>> !CAVIUM_OCTEON_SOC
>> default MIPS_CMDLINE_FROM_BOOTLOADER
>>
>> diff --git a/arch/mips/boot/dts/Makefile
>b/arch/mips/boot/dts/Makefile
>> index 1e79cab8e269..d429a69bfe30 100644
>> --- a/arch/mips/boot/dts/Makefile
>> +++ b/arch/mips/boot/dts/Makefile
>> @@ -4,6 +4,7 @@ subdir-y += cavium-octeon
>> subdir-y += img
>> subdir-y += ingenic
>> subdir-y += lantiq
>> +subdir-y += loongson
>> subdir-y += mscc
>> subdir-y += mti
>> subdir-y += netlogic
>> diff --git a/arch/mips/boot/dts/loongson/Makefile
>b/arch/mips/boot/dts/loongson/Makefile
>> new file mode 100644
>> index 000000000000..56d379471262
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/loongson/Makefile
>> @@ -0,0 +1,4 @@
>> +# SPDX_License_Identifier: GPL_2.0
>> +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb
>loongson3_8core_rs780e.dtb
>> +
>> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
>> diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi
>b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
>> new file mode 100644
>> index 000000000000..d09c313603f1
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
>> @@ -0,0 +1,62 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>I still add something like this here:
>
> cpu@0 {
> compatible = "loongson,loongson3";
> device_type = "cpu";
> reg = <0x0>;
> next-level-cache = <&scache0>;
> };
>
>Because it at least solve the problem of cache hierarchy, which cause
>"lscpu" crash.
That's another problem.
Previous discussion with rob and Paul all suggested that we shouldn't add cpu node.
At least for now.
>
>> + cpuintc: interrupt-controller {
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + interrupt-controller;
>> + compatible = "mti,cpu-interrupt-controller";
>> + };
>> +
>> + package0: bus@1fe00000 {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
>> + 0 0x3ff00000 0 0x3ff00000 0x100000
>> + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
>/* 3A HT Config Space */
>> + 0x1efd 0xfb000000 0x1efd 0xfb000000
>0x10000000 /* 3B HT Config Space */>;
>> +
>> + liointc: interrupt-controller@3ff01400 {
>> + compatible = "loongson,liointc-1.0";
>> + reg = <0 0x3ff01400 0x64>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <2>, <3>;
>> + interrupt-names = "int0", "int1";
>> +
>> + loongson,parent_int_map = <0xf0ffffff>, /*
>int0 */
>> + <0x0f000000>, /* int1
>*/
>> + <0x00000000>, /* int2
>*/
>> + <0x00000000>; /* int3
>*/
>> +
>> + };
>> +
>> + cpu_uart0: serial@1fe001e0 {
>> + compatible = "ns16550a";
>> + reg = <0 0x1fe001e0 0x8>;
>> + clock-frequency = <33000000>;
>> + interrupt-parent = <&liointc>;
>> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
>> + no-loopback-test;
>> + };
>> +
>> + cpu_uart1: serial@1fe001e8 {
>> + status = "disabled";
>Why disable UART1 by default, is it cause problems?
Yes. It would cause endless suprious interrupt.
And most machine didn't exposed that port.
So I'd prefer disable it.
>
>> + compatible = "ns16550a";
>> + reg = <0 0x1fe001e8 0x8>;
>> + clock-frequency = <33000000>;
>> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-parent = <&liointc>;
>> + no-loopback-test;
>> + };
>> + };
>> +};
>> diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
>b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
>> new file mode 100644
>> index 000000000000..6b5694ca0f95
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
>> @@ -0,0 +1,25 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +
>> +/dts-v1/;
>> +
>> +#include "loongson3-package.dtsi"
>> +#include "rs780e-pch.dtsi"
>> +
>> +/ {
>> + compatible = "loongson,loongson3-4core-rs780e";
>> +};
>> +
>> +&package0 {
>> + htpic: interrupt-controller@efdfb000080 {
>> + compatible = "loongson,htpic-1.0";
>> + reg = <0xefd 0xfb000080 0x40>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + interrupt-parent = <&liointc>;
>> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
>> + <25 IRQ_TYPE_LEVEL_HIGH>,
>> + <26 IRQ_TYPE_LEVEL_HIGH>,
>> + <27 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +};
>> diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
>b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
>> new file mode 100644
>> index 000000000000..ffefa2f829b0
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
>> @@ -0,0 +1,25 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +
>> +/dts-v1/;
>> +
>> +#include "loongson3-package.dtsi"
>> +#include "rs780e-pch.dtsi"
>> +
>> +/ {
>> + compatible = "loongson,loongson3-8core-rs780e";
>> +};
>> +
>> +&package0 {
>> + htpic: interrupt-controller@1efdfb000080 {
>> + compatible = "loongson,htpic-1.0";
>> + reg = <0x1efd 0xfb000080 0x40>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + interrupt-parent = <&liointc>;
>> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
>> + <25 IRQ_TYPE_LEVEL_HIGH>,
>> + <26 IRQ_TYPE_LEVEL_HIGH>,
>> + <27 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +};
>> diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
>b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
>> new file mode 100644
>> index 000000000000..45c54d555fa4
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
>> @@ -0,0 +1,26 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +
>> +/ {
>> + bus@10000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0x10000000 0 0x10000000 0 0x10000000
>> + 0 0x40000000 0 0x40000000 0
>0x40000000
>> + 0xfd 0xfe000000 0xfd 0xfe000000 0
>0x2000000 /* PCI Config Space */>;
>> +
>> + isa {
>> + compatible = "isa";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges = <1 0 0 0 0x1000>;
>> +
>> + rtc0: rtc@70 {
>> + compatible = "motorola,mc146818";
>> + reg = <1 0x70 0x8>;
>> + interrupts = <8>;
>> + interrupt-parent = <&htpic>;
>> + };
>> + };
>> + };
>> +};
>> --
>> 2.26.0.rc2
>>
>>
>
>Regards,
>Huacai
--
Jiaxun Yang
于 2020年3月25日 GMT+08:00 上午9:52:26, Huacai Chen <[email protected]> 写到:
>Hi, Jiaxun,
>
>On Tue, Mar 24, 2020 at 11:39 PM Jiaxun Yang <[email protected]>
>wrote:
>>
>> The 1.0 version of that controller has a bug that status bit
>> of LPC IRQ sometimes doesn't get set correctly.
>>
>> So we can always blame LPC IRQ when spurious interrupt happens
>> at the parent interrupt line which LPC IRQ supposed to route
>> to.
>>
>> Co-developed-by: Huacai Chen <[email protected]>
>> Signed-off-by: Jiaxun Yang <[email protected]>
>> ---
>> drivers/irqchip/irq-loongson-liointc.c | 16 ++++++++++++++--
>> 1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-loongson-liointc.c
>b/drivers/irqchip/irq-loongson-liointc.c
>> index 8b6d7b8ddaca..d5054e90eab8 100644
>> --- a/drivers/irqchip/irq-loongson-liointc.c
>> +++ b/drivers/irqchip/irq-loongson-liointc.c
>> @@ -32,6 +32,8 @@
>>
>> #define LIOINTC_SHIFT_INTx 4
>>
>> +#define LIOINTC_ERRATA_IRQ 10
>> +
>> struct liointc_handler_data {
>> struct liointc_priv *priv;
>> u32 parent_int_map;
>> @@ -41,6 +43,7 @@ struct liointc_priv {
>> struct irq_chip_generic *gc;
>> struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
>> u8 map_cache[LIOINTC_CHIP_IRQ];
>> + bool have_lpc_irq_errata;
>Maybe has_lpc_irq_errata?
Fixed, thanks.
>
>> };
>>
>> static void liointc_chained_handle_irq(struct irq_desc *desc)
>> @@ -54,8 +57,14 @@ static void liointc_chained_handle_irq(struct
>irq_desc *desc)
>>
>> pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
>>
>> - if (!pending)
>> - spurious_interrupt();
>> + if (!pending) {
>> + /* Always blame LPC IRQ if we have that bug and LPC
>IRQ is enabled */
>> + if (handler->priv->have_lpc_irq_errata &&
>> + (handler->parent_int_map & ~gc->mask_cache &
>BIT(LIOINTC_ERRATA_IRQ)))
>> + pending = BIT(LIOINTC_ERRATA_IRQ);
>> + else
>> + spurious_interrupt();
>> + }
>>
>> while (pending) {
>> int bit = __ffs(pending);
>> @@ -164,6 +173,9 @@ int __init liointc_of_init(struct device_node
>*node,
>> goto out_iounmap;
>> }
>>
>> + if (of_device_is_compatible(node, "loongson,liointc-1.0"))
>> + priv->have_lpc_irq_errata = true;
>> +
>> sz = of_property_read_variable_u32_array(node,
>"loongson,parent_int_map",
>>
>&of_parent_int_map[0], LIOINTC_NUM_PARENT,
>> LIOINTC_NUM_PARENT);
>> --
>> 2.26.0.rc2
>>
>>
>
>Regards,
>Huacai Chen
--
Jiaxun Yang
Loongson have a long history of contributing their code to mainline kernel.
However, it seems like recent years, they are focusing on maintain a kernel by themselves
rather than contribute there code to the community.
Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
maintainance and became outdated.
This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
Loongson 2e/f alone since they are too legacy to touch.
PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
v1:
- dt-bindings fixup according to Rob's comments
- irqchip fixup according to Marc's comments
- ls3-iointc: Make Core&IP map per-IRQ
- Regenerate kconfigs
- Typo & style improvements
v2:
- dt-bindings: Fix IOINTC, collect Rob's review tag
- dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
v3:
- Split code have been merged
- Fix IOINTC binding to allow map any child IRQ to and parent
- Convert "HTINTC" into "HTPIC", which mixed HT vectors processing and i8259
- Naming style fix according to Huacai's suggestions
v4:
- More naming related fixes
v5:
- irqchip fixes thanks to maz (see per file changelog)
- Remove unnecessary details in dt-bindings
- Credit Huacai with Co-developed-by
v6:
- HTPIC minor fix
- device binding naming fix
v7:
- Add Huacai's sign-off
- Fix all reasonable checkpatch warnings
Jiaxun Yang (12):
irqchip: Add driver for Loongson I/O Local Interrupt Controller
irqchip: loongson-liointc: Workaround LPC IRQ Errata
dt-bindings: interrupt-controller: Add Loongson LIOINTC
irqchip: Add driver for Loongson-3 HyperTransport PIC controller
dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson boards
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE
MAINTAINERS: Update Loongson64 entry
.../interrupt-controller/loongson,htpic.yaml | 59 ++++
.../loongson,liointc.yaml | 93 ++++++
.../bindings/mips/loongson/devices.yaml | 27 ++
MAINTAINERS | 1 +
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 +
.../boot/dts/loongson/loongson3-package.dtsi | 64 +++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++
arch/mips/include/asm/i8259.h | 1 +
.../include/asm/mach-loongson64/boot_param.h | 2 +
.../asm/mach-loongson64/builtin_dtbs.h | 13 +
arch/mips/include/asm/mach-loongson64/irq.h | 32 +--
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/env.c | 23 ++
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 -----------
arch/mips/loongson64/setup.c | 16 ++
arch/mips/loongson64/smp.c | 28 +-
drivers/irqchip/Kconfig | 19 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-loongson-htpic.c | 149 ++++++++++
drivers/irqchip/irq-loongson-liointc.c | 270 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
27 files changed, 846 insertions(+), 213 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/loongson64/irq.c
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
--
2.26.0.rc2
This controller appeared on Loongson family of chips as the primary
package interrupt source.
Signed-off-by: Jiaxun Yang <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
---
v4-v5:
Resolve suggestions from maz:
- Remove DT validation
- Simplify unnucessary functions & variables
---
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-liointc.c | 261 +++++++++++++++++++++++++
3 files changed, 271 insertions(+)
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 6d397732138d..c609eaa319d2 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER
Say yes here to add support for the IRQ combiner devices embedded
in Samsung Exynos chips.
+config LOONGSON_LIOINTC
+ bool "Loongson Local I/O Interrupt Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson Local I/O Interrupt Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index eae0d78cbf22..5e7678efdfe6 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
+obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
new file mode 100644
index 000000000000..18de2c09ece4
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <[email protected]>
+ * Loongson Local IO Interrupt Controller support
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/irqchip/chained_irq.h>
+
+#include <boot_param.h>
+
+#define LIOINTC_CHIP_IRQ 32
+#define LIOINTC_NUM_PARENT 4
+
+#define LIOINTC_INTC_CHIP_START 0x20
+
+#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
+#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
+#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
+#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
+#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
+#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
+
+#define LIOINTC_SHIFT_INTx 4
+
+struct liointc_handler_data {
+ struct liointc_priv *priv;
+ u32 parent_int_map;
+};
+
+struct liointc_priv {
+ struct irq_chip_generic *gc;
+ struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
+ u8 map_cache[LIOINTC_CHIP_IRQ];
+};
+
+static void liointc_chained_handle_irq(struct irq_desc *desc)
+{
+ struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct irq_chip_generic *gc = handler->priv->gc;
+ u32 pending;
+
+ chained_irq_enter(chip, desc);
+
+ pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ generic_handle_irq(irq_find_mapping(gc->domain, bit));
+ pending &= ~BIT(bit);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void liointc_set_bit(struct irq_chip_generic *gc,
+ unsigned int offset,
+ u32 mask, bool set)
+{
+ if (set)
+ writel(readl(gc->reg_base + offset) | mask,
+ gc->reg_base + offset);
+ else
+ writel(readl(gc->reg_base + offset) & ~mask,
+ gc->reg_base + offset);
+}
+
+static int liointc_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ u32 mask = data->mask;
+ unsigned long flags;
+
+ irq_gc_lock_irqsave(gc, flags);
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ default:
+ return -EINVAL;
+ }
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ irqd_set_trigger_type(data, type);
+ return 0;
+}
+
+static void liointc_resume(struct irq_chip_generic *gc)
+{
+ struct liointc_priv *priv = gc->private;
+ unsigned long flags;
+ int i;
+
+ irq_gc_lock_irqsave(gc, flags);
+ /* Disable all at first */
+ writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
+ /* Revert map cache */
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
+ writeb(priv->map_cache[i], gc->reg_base + i);
+ /* Revert mask cache */
+ writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
+ irq_gc_unlock_irqrestore(gc, flags);
+}
+
+static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
+
+int __init liointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_domain *domain;
+ struct irq_chip_type *ct;
+ struct liointc_priv *priv;
+ void __iomem *base;
+ u32 of_parent_int_map[LIOINTC_NUM_PARENT];
+ int parent_irq[LIOINTC_NUM_PARENT];
+ bool have_parent = FALSE;
+ int sz, i, err = 0;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
+ if (parent_irq[i] > 0)
+ have_parent = TRUE;
+ }
+ if (!have_parent) {
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ sz = of_property_read_variable_u32_array(node,
+ "loongson,parent_int_map",
+ &of_parent_int_map[0],
+ LIOINTC_NUM_PARENT,
+ LIOINTC_NUM_PARENT);
+ if (sz < 4) {
+ pr_err("loongson-liointc: No parent_int_map\n");
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++)
+ priv->handler[i].parent_int_map = of_parent_int_map[i];
+
+ /* Setup IRQ domain */
+ domain = irq_domain_add_linear(node, 32,
+ &irq_generic_chip_ops, priv);
+ if (!domain) {
+ pr_err("loongson-liointc: cannot add IRQ domain\n");
+ err = -EINVAL;
+ goto out_iounmap;
+ }
+
+ err = irq_alloc_domain_generic_chips(domain, 32, 1,
+ node->full_name, handle_level_irq,
+ IRQ_NOPROBE, 0, 0);
+ if (err) {
+ pr_err("loongson-liointc: unable to register IRQ domain\n");
+ goto out_free_domain;
+ }
+
+
+ /* Disable all IRQs */
+ writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
+ /* Set to level triggered */
+ writel(0x0, base + LIOINTC_REG_INTC_EDGE);
+
+ /* Generate parent INT part of map cache */
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ u32 pending = priv->handler[i].parent_int_map;
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
+ pending &= ~BIT(bit);
+ }
+ }
+
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
+ /* Generate core part of map cache */
+ priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
+ writeb(priv->map_cache[i], base + i);
+ }
+
+ gc = irq_get_domain_generic_chip(domain, 0);
+ gc->private = priv;
+ gc->reg_base = base;
+ gc->domain = domain;
+ gc->resume = liointc_resume;
+
+ ct = gc->chip_types;
+ ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
+ ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
+ ct->chip.irq_set_type = liointc_set_type;
+
+ gc->mask_cache = 0xffffffff;
+ priv->gc = gc;
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ if (parent_irq[i] <= 0)
+ continue;
+
+ priv->handler[i].priv = priv;
+ irq_set_chained_handler_and_data(parent_irq[i],
+ liointc_chained_handle_irq, &priv->handler[i]);
+ }
+
+ return 0;
+
+out_free_domain:
+ irq_domain_remove(domain);
+out_iounmap:
+ iounmap(base);
+out_free_priv:
+ kfree(priv);
+
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
+IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
--
2.26.0.rc2
From: Tiezhu Yang <[email protected]>
Fix the following checkpatch error:
ERROR: do not initialise statics to 0
#125: FILE: loongson64/numa.c:125:
+ static unsigned long num_physpages = 0;
Signed-off-by: Tiezhu Yang <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>
---
arch/mips/loongson64/numa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
index e5b40c5e3296..1ae072df4831 100644
--- a/arch/mips/loongson64/numa.c
+++ b/arch/mips/loongson64/numa.c
@@ -122,7 +122,7 @@ static unsigned long nid_to_addroffset(unsigned int nid)
static void __init szmem(unsigned int node)
{
u32 i, mem_type;
- static unsigned long num_physpages = 0;
+ static unsigned long num_physpages;
u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size;
/* Parse memory information and activate */
--
2.26.0.rc2
Document Loongson I/O Interrupt controller.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
---
.../loongson,liointc.yaml | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
new file mode 100644
index 000000000000..9c6b91fee477
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson Local I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt controller which can route local I/O interrupt to interrupt lines
+ of cores.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,liointc-1.0
+ - const: loongson,liointc-1.0a
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ description:
+ Interrupt source of the CPU interrupts.
+ minItems: 1
+ maxItems: 4
+
+ interrupt-names:
+ description: List of names for the parent interrupts.
+ items:
+ - const: int0
+ - const: int1
+ - const: int2
+ - const: int3
+ minItems: 1
+ maxItems: 4
+
+ '#interrupt-cells':
+ const: 2
+
+ 'loongson,parent_int_map':
+ description: |
+ This property points how the children interrupts will be mapped into CPU
+ interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
+ and each bit in the cell refers to a children interrupt fron 0 to 31.
+ If a CPU interrupt line didn't connected with liointc, then keep it's
+ cell with zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - items:
+ minItems: 4
+ maxItems: 4
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - 'loongson,parent_int_map'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+...
--
2.26.0.rc2
The 1.0 version of that controller has a bug that status bit
of LPC IRQ sometimes doesn't get set correctly.
So we can always blame LPC IRQ when spurious interrupt happens
at the parent interrupt line which LPC IRQ supposed to route
to.
Signed-off-by: Jiaxun Yang <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
---
drivers/irqchip/irq-loongson-liointc.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 18de2c09ece4..7d2339e638db 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -32,6 +32,8 @@
#define LIOINTC_SHIFT_INTx 4
+#define LIOINTC_ERRATA_IRQ 10
+
struct liointc_handler_data {
struct liointc_priv *priv;
u32 parent_int_map;
@@ -41,6 +43,7 @@ struct liointc_priv {
struct irq_chip_generic *gc;
struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
u8 map_cache[LIOINTC_CHIP_IRQ];
+ bool have_lpc_irq_errata;
};
static void liointc_chained_handle_irq(struct irq_desc *desc)
@@ -54,8 +57,15 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
- if (!pending)
- spurious_interrupt();
+ if (!pending) {
+ /* Always blame LPC IRQ if we have that bug */
+ if (handler->priv->have_lpc_irq_errata &&
+ (handler->parent_int_map & ~gc->mask_cache &
+ BIT(LIOINTC_ERRATA_IRQ)))
+ pending = BIT(LIOINTC_ERRATA_IRQ);
+ else
+ spurious_interrupt();
+ }
while (pending) {
int bit = __ffs(pending);
--
2.26.0.rc2
From: Alex Smith <[email protected]>
The infrared sensor on the CI20 board is connected to a GPIO and can
be operated by using the gpio-ir-recv driver. Add a DT node for the
sensor to allow that driver to be used.
Signed-off-by: Alex Smith <[email protected]>
Signed-off-by: H. Nikolaus Schaller <[email protected]>
Reviewed-by: Paul Cercueil <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>
---
arch/mips/boot/dts/ingenic/ci20.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index c340f947baa0..fc4e64200c3d 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -62,6 +62,11 @@ eth0_power: fixedregulator@0 {
enable-active-high;
};
+ ir: ir {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
+ };
+
wlan0_power: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "wlan0_power";
--
2.26.0.rc2
Hi, Jiaxun,
On Wed, Mar 25, 2020 at 10:09 AM Jiaxun Yang <[email protected]> wrote:
>
>
>
> 于 2020年3月25日 GMT+08:00 上午10:11:05, Huacai Chen <[email protected]> 写到:
> >Hi, Jiaxun,
> >
> >On Tue, Mar 24, 2020 at 11:40 PM Jiaxun Yang <[email protected]>
> >wrote:
> >>
> >> Add generic device dts for Loongson-3 devices.
> >> They are currently almost identical but will be different later.
> >> Some PCH devices like PCI Host Bridge is still enabled by platform
> >> code for now.
> >>
> >> Co-developed-by: Huacai Chen <[email protected]>
> >> Signed-off-by: Jiaxun Yang <[email protected]>
> >> ---
> >> arch/mips/Kconfig | 6 +-
> >> arch/mips/boot/dts/Makefile | 1 +
> >> arch/mips/boot/dts/loongson/Makefile | 4 ++
> >> .../boot/dts/loongson/loongson3-package.dtsi | 62
> >+++++++++++++++++++
> >> .../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++
> >> .../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++
> >> arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++
> >> 7 files changed, 147 insertions(+), 2 deletions(-)
> >> create mode 100644 arch/mips/boot/dts/loongson/Makefile
> >> create mode 100644
> >arch/mips/boot/dts/loongson/loongson3-package.dtsi
> >> create mode 100644
> >arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
> >> create mode 100644
> >arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
> >> create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> >>
> >> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> >> index ca3045b2a2d9..4a0b2f494d79 100644
> >> --- a/arch/mips/Kconfig
> >> +++ b/arch/mips/Kconfig
> >> @@ -486,9 +486,11 @@ config MACH_LOONGSON64
> >> select SYS_SUPPORTS_HIGHMEM
> >> select SYS_SUPPORTS_LITTLE_ENDIAN
> >> select SYS_SUPPORTS_ZBOOT
> >> - select LOONGSON_MC146818
> >> select ZONE_DMA32
> >> select NUMA
> >> + select COMMON_CLK
> >> + select USE_OF
> >> + select BUILTIN_DTB
> >> help
> >> This enables the support of Loongson-2/3 family of
> >machines.
> >>
> >> @@ -3081,7 +3083,7 @@ endchoice
> >> choice
> >> prompt "Kernel command line type" if !CMDLINE_OVERRIDE
> >> default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 &&
> >!MACH_INGENIC && \
> >> - !MIPS_MALTA && \
> >> + !MACH_LOONGSON64 &&
> >!MIPS_MALTA && \
> >> !CAVIUM_OCTEON_SOC
> >> default MIPS_CMDLINE_FROM_BOOTLOADER
> >>
> >> diff --git a/arch/mips/boot/dts/Makefile
> >b/arch/mips/boot/dts/Makefile
> >> index 1e79cab8e269..d429a69bfe30 100644
> >> --- a/arch/mips/boot/dts/Makefile
> >> +++ b/arch/mips/boot/dts/Makefile
> >> @@ -4,6 +4,7 @@ subdir-y += cavium-octeon
> >> subdir-y += img
> >> subdir-y += ingenic
> >> subdir-y += lantiq
> >> +subdir-y += loongson
> >> subdir-y += mscc
> >> subdir-y += mti
> >> subdir-y += netlogic
> >> diff --git a/arch/mips/boot/dts/loongson/Makefile
> >b/arch/mips/boot/dts/loongson/Makefile
> >> new file mode 100644
> >> index 000000000000..56d379471262
> >> --- /dev/null
> >> +++ b/arch/mips/boot/dts/loongson/Makefile
> >> @@ -0,0 +1,4 @@
> >> +# SPDX_License_Identifier: GPL_2.0
> >> +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb
> >loongson3_8core_rs780e.dtb
> >> +
> >> +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> >> diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi
> >b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
> >> new file mode 100644
> >> index 000000000000..d09c313603f1
> >> --- /dev/null
> >> +++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
> >> @@ -0,0 +1,62 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >> +
> >> +/ {
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> +
> >I still add something like this here:
> >
> > cpu@0 {
> > compatible = "loongson,loongson3";
> > device_type = "cpu";
> > reg = <0x0>;
> > next-level-cache = <&scache0>;
> > };
> >
> >Because it at least solve the problem of cache hierarchy, which cause
> >"lscpu" crash.
>
> That's another problem.
> Previous discussion with rob and Paul all suggested that we shouldn't add cpu node.
> At least for now.
>
Maybe Rob and Paul had never care about the cache hierarchy problem?
And I think the generic .dts files should not be modified from time to
time.
> >
> >> + cpuintc: interrupt-controller {
> >> + #address-cells = <0>;
> >> + #interrupt-cells = <1>;
> >> + interrupt-controller;
> >> + compatible = "mti,cpu-interrupt-controller";
> >> + };
> >> +
> >> + package0: bus@1fe00000 {
> >> + compatible = "simple-bus";
> >> + #address-cells = <2>;
> >> + #size-cells = <1>;
> >> + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
> >> + 0 0x3ff00000 0 0x3ff00000 0x100000
> >> + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
> >/* 3A HT Config Space */
> >> + 0x1efd 0xfb000000 0x1efd 0xfb000000
> >0x10000000 /* 3B HT Config Space */>;
> >> +
> >> + liointc: interrupt-controller@3ff01400 {
> >> + compatible = "loongson,liointc-1.0";
> >> + reg = <0 0x3ff01400 0x64>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> +
> >> + interrupt-parent = <&cpuintc>;
> >> + interrupts = <2>, <3>;
> >> + interrupt-names = "int0", "int1";
> >> +
> >> + loongson,parent_int_map = <0xf0ffffff>, /*
> >int0 */
> >> + <0x0f000000>, /* int1
> >*/
> >> + <0x00000000>, /* int2
> >*/
> >> + <0x00000000>; /* int3
> >*/
> >> +
> >> + };
> >> +
> >> + cpu_uart0: serial@1fe001e0 {
> >> + compatible = "ns16550a";
> >> + reg = <0 0x1fe001e0 0x8>;
> >> + clock-frequency = <33000000>;
> >> + interrupt-parent = <&liointc>;
> >> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> >> + no-loopback-test;
> >> + };
> >> +
> >> + cpu_uart1: serial@1fe001e8 {
> >> + status = "disabled";
> >Why disable UART1 by default, is it cause problems?
>
> Yes. It would cause endless suprious interrupt.
> And most machine didn't exposed that port.
> So I'd prefer disable it.
I think the default .dts file should enable devices as many as
possible, and suprious interrupts have not cause serious problems.
>
> >
> >> + compatible = "ns16550a";
> >> + reg = <0 0x1fe001e8 0x8>;
> >> + clock-frequency = <33000000>;
> >> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> >> + interrupt-parent = <&liointc>;
> >> + no-loopback-test;
> >> + };
> >> + };
> >> +};
> >> diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
> >b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
> >> new file mode 100644
> >> index 000000000000..6b5694ca0f95
> >> --- /dev/null
> >> +++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
> >> @@ -0,0 +1,25 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "loongson3-package.dtsi"
> >> +#include "rs780e-pch.dtsi"
> >> +
> >> +/ {
> >> + compatible = "loongson,loongson3-4core-rs780e";
> >> +};
> >> +
> >> +&package0 {
> >> + htpic: interrupt-controller@efdfb000080 {
> >> + compatible = "loongson,htpic-1.0";
> >> + reg = <0xefd 0xfb000080 0x40>;
> >> + interrupt-controller;
> >> + #interrupt-cells = <1>;
> >> +
> >> + interrupt-parent = <&liointc>;
> >> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> >> + <25 IRQ_TYPE_LEVEL_HIGH>,
> >> + <26 IRQ_TYPE_LEVEL_HIGH>,
> >> + <27 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +};
> >> diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
> >b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
> >> new file mode 100644
> >> index 000000000000..ffefa2f829b0
> >> --- /dev/null
> >> +++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
> >> @@ -0,0 +1,25 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "loongson3-package.dtsi"
> >> +#include "rs780e-pch.dtsi"
> >> +
> >> +/ {
> >> + compatible = "loongson,loongson3-8core-rs780e";
> >> +};
> >> +
> >> +&package0 {
> >> + htpic: interrupt-controller@1efdfb000080 {
> >> + compatible = "loongson,htpic-1.0";
> >> + reg = <0x1efd 0xfb000080 0x40>;
> >> + interrupt-controller;
> >> + #interrupt-cells = <1>;
> >> +
> >> + interrupt-parent = <&liointc>;
> >> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> >> + <25 IRQ_TYPE_LEVEL_HIGH>,
> >> + <26 IRQ_TYPE_LEVEL_HIGH>,
> >> + <27 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +};
> >> diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> >b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> >> new file mode 100644
> >> index 000000000000..45c54d555fa4
> >> --- /dev/null
> >> +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> >> @@ -0,0 +1,26 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +
> >> +/ {
> >> + bus@10000000 {
> >> + compatible = "simple-bus";
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + ranges = <0 0x10000000 0 0x10000000 0 0x10000000
> >> + 0 0x40000000 0 0x40000000 0
> >0x40000000
> >> + 0xfd 0xfe000000 0xfd 0xfe000000 0
> >0x2000000 /* PCI Config Space */>;
> >> +
> >> + isa {
> >> + compatible = "isa";
> >> + #address-cells = <2>;
> >> + #size-cells = <1>;
> >> + ranges = <1 0 0 0 0x1000>;
> >> +
> >> + rtc0: rtc@70 {
> >> + compatible = "motorola,mc146818";
> >> + reg = <1 0x70 0x8>;
> >> + interrupts = <8>;
> >> + interrupt-parent = <&htpic>;
> >> + };
> >> + };
> >> + };
> >> +};
> >> --
> >> 2.26.0.rc2
> >>
> >>
> >
> >Regards,
> >Huacai
>
> --
> Jiaxun Yang
Regards,
Huacai
Loongson have a long history of contributing their code to mainline kernel.
However, it seems like recent years, they are focusing on maintain a kernel by themselves
rather than contribute there code to the community.
Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
maintainance and became outdated.
This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
Loongson 2e/f alone since they are too legacy to touch.
PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
v1:
- dt-bindings fixup according to Rob's comments
- irqchip fixup according to Marc's comments
- ls3-iointc: Make Core&IP map per-IRQ
- Regenerate kconfigs
- Typo & style improvements
v2:
- dt-bindings: Fix IOINTC, collect Rob's review tag
- dtbs: Drop CPU Node, merge different ways according to Huacai and Paul's comments
v3:
- Split code have been merged
- Fix IOINTC binding to allow map any child IRQ to and parent
- Convert "HTINTC" into "HTPIC", which mixed HT vectors processing and i8259
- Naming style fix according to Huacai's suggestions
v4:
- More naming related fixes
v5:
- irqchip fixes thanks to maz (see per file changelog)
- Remove unnecessary details in dt-bindings
- Credit Huacai with Co-developed-by
v6:
- HTPIC minor fix
- device binding naming fix
v7:
- Messed up, please ignore it.
v8:
- Naming fix from Huacai
- fix all reasonable checkpatch warnings
Jiaxun Yang (11):
irqchip: Add driver for Loongson I/O Local Interrupt Controller
irqchip: loongson-liointc: Workaround LPC IRQ Errata
dt-bindings: interrupt-controller: Add Loongson LIOINTC
irqchip: Add driver for Loongson-3 HyperTransport PIC controller
dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
irqchip: mips-cpu: Convert to simple domain
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: mips: Add loongson boards
MIPS: Loongson64: Add generic dts
MIPS: Loongson64: Load built-in dtbs
MAINTAINERS: Update Loongson64 entry
.../interrupt-controller/loongson,htpic.yaml | 59 ++++
.../loongson,liointc.yaml | 93 ++++++
.../bindings/mips/loongson/devices.yaml | 27 ++
MAINTAINERS | 1 +
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 +
.../boot/dts/loongson/loongson3-package.dtsi | 64 +++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++
arch/mips/include/asm/i8259.h | 1 +
.../include/asm/mach-loongson64/boot_param.h | 2 +
.../asm/mach-loongson64/builtin_dtbs.h | 13 +
arch/mips/include/asm/mach-loongson64/irq.h | 30 +-
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/env.c | 23 ++
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 -----------
arch/mips/loongson64/setup.c | 16 ++
arch/mips/loongson64/smp.c | 28 +-
drivers/irqchip/Kconfig | 19 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-loongson-htpic.c | 149 ++++++++++
drivers/irqchip/irq-loongson-liointc.c | 271 ++++++++++++++++++
drivers/irqchip/irq-mips-cpu.c | 2 +-
27 files changed, 846 insertions(+), 212 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
delete mode 100644 arch/mips/loongson64/irq.c
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
--
2.26.0.rc2
This controller appeared on Loongson family of chips as the primary
package interrupt source.
Signed-off-by: Jiaxun Yang <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
---
v4-v5:
Resolve suggestions from maz:
- Remove DT validation
- Simplify unnucessary functions & variables
---
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-liointc.c | 261 +++++++++++++++++++++++++
3 files changed, 271 insertions(+)
create mode 100644 drivers/irqchip/irq-loongson-liointc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 6d397732138d..c609eaa319d2 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER
Say yes here to add support for the IRQ combiner devices embedded
in Samsung Exynos chips.
+config LOONGSON_LIOINTC
+ bool "Loongson Local I/O Interrupt Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ help
+ Support for the Loongson Local I/O Interrupt Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index eae0d78cbf22..5e7678efdfe6 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
+obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
new file mode 100644
index 000000000000..18de2c09ece4
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <[email protected]>
+ * Loongson Local IO Interrupt Controller support
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/irqchip/chained_irq.h>
+
+#include <boot_param.h>
+
+#define LIOINTC_CHIP_IRQ 32
+#define LIOINTC_NUM_PARENT 4
+
+#define LIOINTC_INTC_CHIP_START 0x20
+
+#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
+#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
+#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
+#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
+#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
+#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
+
+#define LIOINTC_SHIFT_INTx 4
+
+struct liointc_handler_data {
+ struct liointc_priv *priv;
+ u32 parent_int_map;
+};
+
+struct liointc_priv {
+ struct irq_chip_generic *gc;
+ struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
+ u8 map_cache[LIOINTC_CHIP_IRQ];
+};
+
+static void liointc_chained_handle_irq(struct irq_desc *desc)
+{
+ struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct irq_chip_generic *gc = handler->priv->gc;
+ u32 pending;
+
+ chained_irq_enter(chip, desc);
+
+ pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ generic_handle_irq(irq_find_mapping(gc->domain, bit));
+ pending &= ~BIT(bit);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void liointc_set_bit(struct irq_chip_generic *gc,
+ unsigned int offset,
+ u32 mask, bool set)
+{
+ if (set)
+ writel(readl(gc->reg_base + offset) | mask,
+ gc->reg_base + offset);
+ else
+ writel(readl(gc->reg_base + offset) & ~mask,
+ gc->reg_base + offset);
+}
+
+static int liointc_set_type(struct irq_data *data, unsigned int type)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ u32 mask = data->mask;
+ unsigned long flags;
+
+ irq_gc_lock_irqsave(gc, flags);
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
+ liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
+ break;
+ default:
+ return -EINVAL;
+ }
+ irq_gc_unlock_irqrestore(gc, flags);
+
+ irqd_set_trigger_type(data, type);
+ return 0;
+}
+
+static void liointc_resume(struct irq_chip_generic *gc)
+{
+ struct liointc_priv *priv = gc->private;
+ unsigned long flags;
+ int i;
+
+ irq_gc_lock_irqsave(gc, flags);
+ /* Disable all at first */
+ writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
+ /* Revert map cache */
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
+ writeb(priv->map_cache[i], gc->reg_base + i);
+ /* Revert mask cache */
+ writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
+ irq_gc_unlock_irqrestore(gc, flags);
+}
+
+static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
+
+int __init liointc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_chip_generic *gc;
+ struct irq_domain *domain;
+ struct irq_chip_type *ct;
+ struct liointc_priv *priv;
+ void __iomem *base;
+ u32 of_parent_int_map[LIOINTC_NUM_PARENT];
+ int parent_irq[LIOINTC_NUM_PARENT];
+ bool have_parent = FALSE;
+ int sz, i, err = 0;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
+ if (parent_irq[i] > 0)
+ have_parent = TRUE;
+ }
+ if (!have_parent) {
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ sz = of_property_read_variable_u32_array(node,
+ "loongson,parent_int_map",
+ &of_parent_int_map[0],
+ LIOINTC_NUM_PARENT,
+ LIOINTC_NUM_PARENT);
+ if (sz < 4) {
+ pr_err("loongson-liointc: No parent_int_map\n");
+ err = -ENODEV;
+ goto out_iounmap;
+ }
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++)
+ priv->handler[i].parent_int_map = of_parent_int_map[i];
+
+ /* Setup IRQ domain */
+ domain = irq_domain_add_linear(node, 32,
+ &irq_generic_chip_ops, priv);
+ if (!domain) {
+ pr_err("loongson-liointc: cannot add IRQ domain\n");
+ err = -EINVAL;
+ goto out_iounmap;
+ }
+
+ err = irq_alloc_domain_generic_chips(domain, 32, 1,
+ node->full_name, handle_level_irq,
+ IRQ_NOPROBE, 0, 0);
+ if (err) {
+ pr_err("loongson-liointc: unable to register IRQ domain\n");
+ goto out_free_domain;
+ }
+
+
+ /* Disable all IRQs */
+ writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
+ /* Set to level triggered */
+ writel(0x0, base + LIOINTC_REG_INTC_EDGE);
+
+ /* Generate parent INT part of map cache */
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ u32 pending = priv->handler[i].parent_int_map;
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
+ pending &= ~BIT(bit);
+ }
+ }
+
+ for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
+ /* Generate core part of map cache */
+ priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
+ writeb(priv->map_cache[i], base + i);
+ }
+
+ gc = irq_get_domain_generic_chip(domain, 0);
+ gc->private = priv;
+ gc->reg_base = base;
+ gc->domain = domain;
+ gc->resume = liointc_resume;
+
+ ct = gc->chip_types;
+ ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
+ ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
+ ct->chip.irq_set_type = liointc_set_type;
+
+ gc->mask_cache = 0xffffffff;
+ priv->gc = gc;
+
+ for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+ if (parent_irq[i] <= 0)
+ continue;
+
+ priv->handler[i].priv = priv;
+ irq_set_chained_handler_and_data(parent_irq[i],
+ liointc_chained_handle_irq, &priv->handler[i]);
+ }
+
+ return 0;
+
+out_free_domain:
+ irq_domain_remove(domain);
+out_iounmap:
+ iounmap(base);
+out_free_priv:
+ kfree(priv);
+
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
+IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
--
2.26.0.rc2
Document Loongson I/O Interrupt controller.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
---
.../loongson,liointc.yaml | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
new file mode 100644
index 000000000000..9c6b91fee477
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson Local I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt controller which can route local I/O interrupt to interrupt lines
+ of cores.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,liointc-1.0
+ - const: loongson,liointc-1.0a
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ description:
+ Interrupt source of the CPU interrupts.
+ minItems: 1
+ maxItems: 4
+
+ interrupt-names:
+ description: List of names for the parent interrupts.
+ items:
+ - const: int0
+ - const: int1
+ - const: int2
+ - const: int3
+ minItems: 1
+ maxItems: 4
+
+ '#interrupt-cells':
+ const: 2
+
+ 'loongson,parent_int_map':
+ description: |
+ This property points how the children interrupts will be mapped into CPU
+ interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
+ and each bit in the cell refers to a children interrupt fron 0 to 31.
+ If a CPU interrupt line didn't connected with liointc, then keep it's
+ cell with zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - items:
+ minItems: 4
+ maxItems: 4
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - 'loongson,parent_int_map'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+...
--
2.26.0.rc2
This controller appeared on Loongson-3 family of chips to receive
interrupts from PCH PIC.
It is a I8259 with optimized interrupt polling flow. We can poll
interrupt number from HT vector directly but still have to follow
standard I8259 routines to mask, unmask and EOI.
Signed-off-by: Jiaxun Yang <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
---
v4-v5:
Enhancements according to maz's suggestions:
- Add static for private struct
- Drop pointless rename
- Fix DT parse bug
- Clarifications in comments and commit message
v5-v6:
Check parent_irq = 0 case.
---
arch/mips/include/asm/i8259.h | 1 +
drivers/irqchip/Kconfig | 10 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-loongson-htpic.c | 149 +++++++++++++++++++++++++++
4 files changed, 161 insertions(+)
create mode 100644 drivers/irqchip/irq-loongson-htpic.c
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index 97a5e41ed1ab..a54b9649de22 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -36,6 +36,7 @@ extern raw_spinlock_t i8259A_lock;
extern void make_8259A_irq(unsigned int irq);
extern void init_i8259_irqs(void);
+extern struct irq_domain *__init_i8259_irqs(struct device_node *node);
/**
* i8159_set_poll() - Override the i8259 polling function
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c609eaa319d2..cae6f480c987 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -522,4 +522,14 @@ config LOONGSON_LIOINTC
help
Support for the Loongson Local I/O Interrupt Controller.
+config LOONGSON_HTPIC
+ bool "Loongson3 HyperTransport PIC Controller"
+ depends on MACH_LOONGSON64
+ default y
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
+ select I8259
+ help
+ Support for the Loongson-3 HyperTransport PIC Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 5e7678efdfe6..37bbe39bf909 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -106,3 +106,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
+obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c
new file mode 100644
index 000000000000..dd018c22ea83
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-htpic.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Jiaxun Yang <[email protected]>
+ * Loongson HTPIC IRQ support
+ */
+
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <asm/i8259.h>
+
+#define HTPIC_MAX_PARENT_IRQ 4
+#define HTINT_NUM_VECTORS 8
+#define HTINT_EN_OFF 0x20
+
+struct loongson_htpic {
+ void __iomem *base;
+ struct irq_domain *domain;
+};
+
+static struct loongson_htpic *htpic;
+
+static void htpic_irq_dispatch(struct irq_desc *desc)
+{
+ struct loongson_htpic *priv = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ uint32_t pending;
+
+ chained_irq_enter(chip, desc);
+ pending = readl(priv->base);
+ /* Ack all IRQs at once, otherwise IRQ flood might happen */
+ writel(pending, priv->base);
+
+ if (!pending)
+ spurious_interrupt();
+
+ while (pending) {
+ int bit = __ffs(pending);
+
+ if (unlikely(bit > 15)) {
+ spurious_interrupt();
+ break;
+ }
+
+ generic_handle_irq(irq_linear_revmap(priv->domain, bit));
+ pending &= ~BIT(bit);
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static void htpic_reg_init(void)
+{
+ int i;
+
+ for (i = 0; i < HTINT_NUM_VECTORS; i++) {
+ uint32_t val;
+
+ /* Disable all HT Vectors */
+ writel(0x0, htpic->base + HTINT_EN_OFF + i * 0x4);
+ val = readl(htpic->base + i * 0x4);
+ /* Ack all possible pending IRQs */
+ writel(GENMASK(31, 0), htpic->base + i * 0x4);
+ }
+
+ /* Enable 16 vectors for PIC */
+ writel(0xffff, htpic->base + HTINT_EN_OFF);
+}
+
+static void htpic_resume(void)
+{
+ htpic_reg_init();
+}
+
+struct syscore_ops htpic_syscore_ops = {
+ .resume = htpic_resume,
+};
+
+int __init htpic_of_init(struct device_node *node, struct device_node *parent)
+{
+ unsigned int parent_irq[4];
+ int i, err;
+ int num_parents = 0;
+
+ if (htpic) {
+ pr_err("loongson-htpic: Only one HTPIC is allowed in the system\n");
+ return -ENODEV;
+ }
+
+ htpic = kzalloc(sizeof(*htpic), GFP_KERNEL);
+ if (!htpic) {
+ err = -ENOMEM;
+ goto out_free;
+ }
+
+ htpic->base = of_iomap(node, 0);
+ if (!htpic->base) {
+ err = -ENODEV;
+ goto out_free;
+ }
+
+ htpic->domain = __init_i8259_irqs(node);
+ if (!htpic->domain) {
+ pr_err("loongson-htpic: Failed to initialize i8259 IRQs\n");
+ err = -ENOMEM;
+ goto out_iounmap;
+ }
+
+ /* Interrupt may come from any of the 4 interrupt line */
+ for (i = 0; i < HTPIC_MAX_PARENT_IRQ; i++) {
+ parent_irq[i] = irq_of_parse_and_map(node, i);
+ if (parent_irq[i] <= 0)
+ break;
+
+ num_parents++;
+ }
+
+ if (!num_parents) {
+ pr_err("loongson-htpic: Failed to get parent irqs\n");
+ err = -ENODEV;
+ goto out_remove_domain;
+ }
+
+ htpic_reg_init();
+
+ for (i = 0; i < num_parents; i++) {
+ irq_set_chained_handler_and_data(parent_irq[i],
+ htpic_irq_dispatch, htpic);
+ }
+
+ register_syscore_ops(&htpic_syscore_ops);
+
+ return 0;
+
+out_remove_domain:
+ irq_domain_remove(htpic->domain);
+out_iounmap:
+ iounmap(htpic->base);
+out_free:
+ kfree(htpic);
+ return err;
+}
+
+IRQCHIP_DECLARE(loongson_htpic, "loongson,htpic-1.0", htpic_of_init);
--
2.26.0.rc2
Document Loongson-3 HyperTransport PIC controller.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
---
.../interrupt-controller/loongson,htpic.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
new file mode 100644
index 000000000000..c8861cbbb8b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 HyperTransport Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips to transmit
+ interrupts from PCH PIC connected on HyperTransport bus.
+
+properties:
+ compatible:
+ const: loongson,htpic-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ description: |
+ Four parent interrupts that receive chained interrupts.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ htintc: interrupt-controller@1fb000080 {
+ compatible = "loongson,htintc-1.0";
+ reg = <0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.26.0.rc2
The old code is using legacy domain to setup irq_domain for CPU interrupts
which requires irq_desc to be preallocated.
However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up
unallocated and lead to incorrect behavior.
Thus we convert the legacy domain to simple domain which can allocate
irq_desc during initialization.
Signed-off-by: Jiaxun Yang <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..c3cf7fa76424 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
- irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+ irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
&mips_cpu_intc_irq_domain_ops,
NULL);
if (!irq_domain)
--
2.26.0.rc2
We've made generic irqchip drivers for Loongson-3 platform, it's time
to say goodbye to these legacy code.
Signed-off-by: Jiaxun Yang <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
---
.../include/asm/mach-loongson64/boot_param.h | 2 +
arch/mips/include/asm/mach-loongson64/irq.h | 30 +---
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/init.c | 6 +
arch/mips/loongson64/irq.c | 162 ------------------
arch/mips/loongson64/smp.c | 28 ++-
6 files changed, 21 insertions(+), 209 deletions(-)
delete mode 100644 arch/mips/loongson64/irq.c
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index 8c286bedff3e..2ed483e32d8c 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -2,6 +2,8 @@
#ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
#define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_
+#include <linux/types.h>
+
#define SYSTEM_RAM_LOW 1
#define SYSTEM_RAM_HIGH 2
#define SYSTEM_RAM_RESERVED 3
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 0d3955616e42..d41dc4a76e6d 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -7,34 +7,6 @@
/* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56
-#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
-#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
-#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
-
-#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
-#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80)
-#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0)
-#define LOONGSON_HT1_INT_VECTOR(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
-#define LOONGSON_HT1_INTN_EN(n) \
- LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
-
-#define LOONGSON_INT_ROUTER_OFFSET 0x1400
-#define LOONGSON_INT_ROUTER_INTEN \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
-#define LOONGSON_INT_ROUTER_INTENSET \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
-#define LOONGSON_INT_ROUTER_INTENCLR \
- LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
-#define LOONGSON_INT_ROUTER_ENTRY(n) \
- LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
-#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
-#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
-
-#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
-
-extern void fixup_irqs(void);
-extern void loongson3_ipi_interrupt(struct pt_regs *regs);
-
#include <asm/mach-generic/irq.h>
+
#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 7821891bc5d0..b7f40b179c71 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -2,7 +2,7 @@
#
# Makefile for Loongson-3 family machines
#
-obj-$(CONFIG_MACH_LOONGSON64) += irq.o cop2-ex.o platform.o acpi_init.o dma.o \
+obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \
setup.o init.o env.o time.o reset.o \
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index 5ac1a0f35ca4..da38944471f4 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -4,6 +4,7 @@
* Author: Wu Zhangjin, [email protected]
*/
+#include <linux/irqchip.h>
#include <linux/memblock.h>
#include <asm/bootinfo.h>
#include <asm/traps.h>
@@ -44,3 +45,8 @@ void __init prom_init(void)
void __init prom_free_prom_memory(void)
{
}
+
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c
deleted file mode 100644
index 79ad797497e4..000000000000
--- a/arch/mips/loongson64/irq.c
+++ /dev/null
@@ -1,162 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <loongson.h>
-#include <irq.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/i8259.h>
-#include <asm/mipsregs.h>
-
-#include "smp.h"
-
-extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
-
-unsigned int irq_cpu[16] = {[0 ... 15] = -1};
-unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
-unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
-
-int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
- bool force)
-{
- unsigned int cpu;
- struct cpumask new_affinity;
-
- /* I/O devices are connected on package-0 */
- cpumask_copy(&new_affinity, affinity);
- for_each_cpu(cpu, affinity)
- if (cpu_data[cpu].package > 0)
- cpumask_clear_cpu(cpu, &new_affinity);
-
- if (cpumask_empty(&new_affinity))
- return -EINVAL;
-
- cpumask_copy(d->common->affinity, &new_affinity);
-
- return IRQ_SET_MASK_OK_NOCOPY;
-}
-
-static void ht_irqdispatch(void)
-{
- unsigned int i, irq;
- struct irq_data *irqd;
- struct cpumask affinity;
-
- irq = LOONGSON_HT1_INT_VECTOR(0);
- LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
-
- for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
- if (!(irq & (0x1 << ht_irq[i])))
- continue;
-
- /* handled by local core */
- if (local_irq & (0x1 << ht_irq[i])) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irqd = irq_get_irq_data(ht_irq[i]);
- cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
- if (cpumask_empty(&affinity)) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
- if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
- irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
-
- if (irq_cpu[ht_irq[i]] == 0) {
- do_IRQ(ht_irq[i]);
- continue;
- }
-
- /* balanced by other cores */
- loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
- }
-}
-
-#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
-
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending;
-
- pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
- if (pending & CAUSEF_IP7)
- do_IRQ(LOONGSON_TIMER_IRQ);
-#if defined(CONFIG_SMP)
- if (pending & CAUSEF_IP6)
- loongson3_ipi_interrupt(NULL);
-#endif
- if (pending & CAUSEF_IP3)
- ht_irqdispatch();
- if (pending & CAUSEF_IP2)
- do_IRQ(LOONGSON_UART_IRQ);
- if (pending & UNUSED_IPS) {
- pr_err("%s : spurious interrupt\n", __func__);
- spurious_interrupt();
- }
-}
-
-static inline void mask_loongson_irq(struct irq_data *d) { }
-static inline void unmask_loongson_irq(struct irq_data *d) { }
-
- /* For MIPS IRQs which shared by all cores */
-static struct irq_chip loongson_irq_chip = {
- .name = "Loongson",
- .irq_ack = mask_loongson_irq,
- .irq_mask = mask_loongson_irq,
- .irq_mask_ack = mask_loongson_irq,
- .irq_unmask = unmask_loongson_irq,
- .irq_eoi = unmask_loongson_irq,
-};
-
-void irq_router_init(void)
-{
- int i;
-
- /* route LPC int to cpu core0 int 0 */
- LOONGSON_INT_ROUTER_LPC =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
- /* route HT1 int0 ~ int7 to cpu core0 INT1*/
- for (i = 0; i < 8; i++)
- LOONGSON_INT_ROUTER_HT1(i) =
- LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
- /* enable HT1 interrupt */
- LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
- /* enable router interrupt intenset */
- LOONGSON_INT_ROUTER_INTENSET =
- LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
-}
-
-void __init arch_init_irq(void)
-{
- struct irq_chip *chip;
-
- clear_c0_status(ST0_IM | ST0_BEV);
-
- irq_router_init();
- mips_cpu_irq_init();
- init_i8259_irqs();
- chip = irq_get_chip(I8259A_IRQ_BASE);
- chip->irq_set_affinity = plat_set_irq_affinity;
-
- irq_set_chip_and_handler(LOONGSON_UART_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
- irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
- &loongson_irq_chip, handle_percpu_irq);
-
- set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-
-void fixup_irqs(void)
-{
- irq_cpu_offline();
- clear_c0_status(ST0_IM);
-}
-
-#endif
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index de8e0741ce2d..e1fe8bbb377d 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -4,6 +4,7 @@
* Author: Chen Huacai, [email protected]
*/
+#include <irq.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/sched.h>
@@ -25,6 +26,8 @@
DEFINE_PER_CPU(int, cpu_state);
+#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
+
static void *ipi_set0_regs[16];
static void *ipi_clear0_regs[16];
static void *ipi_status0_regs[16];
@@ -302,20 +305,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
ipi_write_action(cpu_logical_map(i), (u32)action);
}
-#define IPI_IRQ_OFFSET 6
-
-void loongson3_send_irq_by_ipi(int cpu, int irqs)
-{
- ipi_write_action(cpu_logical_map(cpu), irqs << IPI_IRQ_OFFSET);
-}
-void loongson3_ipi_interrupt(struct pt_regs *regs)
+static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
{
int i, cpu = smp_processor_id();
- unsigned int action, c0count, irqs;
+ unsigned int action, c0count;
action = ipi_read_clear(cpu);
- irqs = action >> IPI_IRQ_OFFSET;
if (action & SMP_RESCHEDULE_YOURSELF)
scheduler_ipi();
@@ -335,13 +331,7 @@ void loongson3_ipi_interrupt(struct pt_regs *regs)
__wbflush(); /* Let others see the result ASAP */
}
- if (irqs) {
- int irq;
- while ((irq = ffs(irqs))) {
- do_IRQ(irq-1);
- irqs &= ~(1<<(irq-1));
- }
- }
+ return IRQ_HANDLED;
}
#define MAX_LOOPS 800
@@ -438,6 +428,9 @@ static void __init loongson3_smp_setup(void)
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
{
+ if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
+ pr_err("Failed to request IPI IRQ\n");
init_cpu_present(cpu_possible_mask);
per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
}
@@ -484,7 +477,8 @@ static int loongson3_cpu_disable(void)
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
local_irq_save(flags);
- fixup_irqs();
+ irq_cpu_offline();
+ clear_c0_status(ST0_IM);
local_irq_restore(flags);
local_flush_tlb_all();
--
2.26.0.rc2
Prepare for later dts.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
--
v4-v5:
Remove unnecessary kernel details.
v5-v6:
Use quad & octa instead of 4 and 8.
---
.../bindings/mips/loongson/devices.yaml | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
new file mode 100644
index 000000000000..74ed4e397a78
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson based Platforms Device Tree Bindings
+
+maintainers:
+ - Jiaxun Yang <[email protected]>
+description: |
+ Devices with a Loongson CPU shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Generic Loongson3 Quad Core + RS780E
+ items:
+ - const: loongson,loongson3-4core-rs780e
+
+ - description: Generic Loongson3 Octa Core + RS780E
+ items:
+ - const: loongson,loongson3-8core-rs780e
+...
--
2.26.0.rc2
Add generic device dts for Loongson-3 devices.
They are currently almost identical but will be different later.
Some PCH devices like PCI Host Bridge is still enabled by platform
code for now.
Signed-off-by: Jiaxun Yang <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
---
arch/mips/Kconfig | 6 +-
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/loongson/Makefile | 4 ++
.../boot/dts/loongson/loongson3-package.dtsi | 64 +++++++++++++++++++
.../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++
.../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++
7 files changed, 149 insertions(+), 2 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/Makefile
create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ca3045b2a2d9..4a0b2f494d79 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -486,9 +486,11 @@ config MACH_LOONGSON64
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
- select LOONGSON_MC146818
select ZONE_DMA32
select NUMA
+ select COMMON_CLK
+ select USE_OF
+ select BUILTIN_DTB
help
This enables the support of Loongson-2/3 family of machines.
@@ -3081,7 +3083,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && \
+ !MACH_LOONGSON64 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..d429a69bfe30 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
subdir-y += lantiq
+subdir-y += loongson
subdir-y += mscc
subdir-y += mti
subdir-y += netlogic
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
new file mode 100644
index 000000000000..56d379471262
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -0,0 +1,4 @@
+# SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
new file mode 100644
index 000000000000..5bb876a4de52
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package0: bus@1fe00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ /* 3A HT Config Space */
+ 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
+ /* 3B HT Config Space */
+ 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
+
+ liointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e0 0x8>;
+ clock-frequency = <33000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x1fe001e8 0x8>;
+ clock-frequency = <33000000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&liointc>;
+ no-loopback-test;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
new file mode 100644
index 000000000000..6b5694ca0f95
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-4core-rs780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
new file mode 100644
index 000000000000..ffefa2f829b0
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "rs780e-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-8core-rs780e";
+};
+
+&package0 {
+ htpic: interrupt-controller@1efdfb000080 {
+ compatible = "loongson,htpic-1.0";
+ reg = <0x1efd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
new file mode 100644
index 000000000000..45c54d555fa4
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x10000000 0 0x10000000 0 0x10000000
+ 0 0x40000000 0 0x40000000 0 0x40000000
+ 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
+
+ isa {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0 0x1000>;
+
+ rtc0: rtc@70 {
+ compatible = "motorola,mc146818";
+ reg = <1 0x70 0x8>;
+ interrupts = <8>;
+ interrupt-parent = <&htpic>;
+ };
+ };
+ };
+};
--
2.26.0.rc2
Load proper dtb according to firmware passed parameters and
CPU PRID.
Signed-off-by: Jiaxun Yang <[email protected]>
Co-developed-by: Huacai Chen <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
---
.../asm/mach-loongson64/builtin_dtbs.h | 13 +++++++++++
.../include/asm/mach-loongson64/loongson.h | 1 +
arch/mips/loongson64/env.c | 23 +++++++++++++++++++
arch/mips/loongson64/setup.c | 16 +++++++++++++
4 files changed, 53 insertions(+)
create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
new file mode 100644
index 000000000000..853c6d80887b
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019 Jiaxun Yang <[email protected]>
+ *
+ * Built-in Generic dtbs for MACH_LOONGSON64
+ */
+
+#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+
+extern u32 __dtb_loongson3_4core_rs780e_begin[];
+extern u32 __dtb_loongson3_8core_rs780e_begin[];
+#endif
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index a8fce112a9b0..fde1b75c45ea 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -25,6 +25,7 @@ extern const struct plat_smp_ops loongson3_smp_ops;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
extern void __init prom_init_env(void);
+extern void *loongson_fdt_blob;
/* irq operation functions */
extern void mach_irq_dispatch(unsigned int pending);
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 0daeb7bcf023..2554ef11170d 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -17,6 +17,7 @@
#include <asm/bootinfo.h>
#include <loongson.h>
#include <boot_param.h>
+#include <builtin_dtbs.h>
#include <workarounds.h>
u32 cpu_clock_freq;
@@ -120,6 +121,28 @@ void __init prom_init_env(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
+ break;
+ default:
+ break;
+ }
+ }
+
+
+ if (!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
+
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c
index 4fd27f4f90ed..6fe3ffffcaa6 100644
--- a/arch/mips/loongson64/setup.c
+++ b/arch/mips/loongson64/setup.c
@@ -8,9 +8,15 @@
#include <asm/wbflush.h>
#include <asm/bootinfo.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
#include <loongson.h>
+void *loongson_fdt_blob;
+
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
@@ -27,4 +33,14 @@ EXPORT_SYMBOL(__wbflush);
void __init plat_mem_setup(void)
{
+ if (loongson_fdt_blob)
+ __dt_setup_arch(loongson_fdt_blob);
+}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
}
--
2.26.0.rc2
To include newly added irqchip drivers.
Signed-off-by: Jiaxun Yang <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 53d6ba9f7029..ba1ab3bfe18b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11169,6 +11169,7 @@ S: Maintained
F: arch/mips/loongson64/
F: arch/mips/include/asm/mach-loongson64/
F: drivers/platform/mips/cpu_hwmon.c
+F: drivers/irqchip/irq-loongson*
F: drivers/*/*loongson3*
F: drivers/*/*/*loongson3*
--
2.26.0.rc2
Hi Jiaxun,
Le mer. 25 mars 2020 ? 10:28, Jiaxun Yang <[email protected]> a
?crit :
> This controller appeared on Loongson family of chips as the primary
> package interrupt source.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Co-developed-by: Huacai Chen <[email protected]>
> Signed-off-by: Huacai Chen <[email protected]>
> Reviewed-by: Marc Zyngier <[email protected]>
> ---
> v4-v5:
> Resolve suggestions from maz:
> - Remove DT validation
> - Simplify unnucessary functions & variables
> ---
> drivers/irqchip/Kconfig | 9 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-loongson-liointc.c | 261
> +++++++++++++++++++++++++
> 3 files changed, 271 insertions(+)
> create mode 100644 drivers/irqchip/irq-loongson-liointc.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 6d397732138d..c609eaa319d2 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER
> Say yes here to add support for the IRQ combiner devices embedded
> in Samsung Exynos chips.
>
> +config LOONGSON_LIOINTC
> + bool "Loongson Local I/O Interrupt Controller"
> + depends on MACH_LOONGSON64
> + default y
> + select IRQ_DOMAIN
> + select GENERIC_IRQ_CHIP
> + help
> + Support for the Loongson Local I/O Interrupt Controller.
> +
> endmenu
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index eae0d78cbf22..5e7678efdfe6 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
> obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
> obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
> obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
> +obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
> diff --git a/drivers/irqchip/irq-loongson-liointc.c
> b/drivers/irqchip/irq-loongson-liointc.c
> new file mode 100644
> index 000000000000..18de2c09ece4
> --- /dev/null
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -0,0 +1,261 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020, Jiaxun Yang <[email protected]>
> + * Loongson Local IO Interrupt Controller support
> + */
> +
> +#include <linux/errno.h>
> +#include <linux/init.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/ioport.h>
> +#include <linux/irqchip.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/io.h>
> +#include <linux/smp.h>
> +#include <linux/irqchip/chained_irq.h>
> +
> +#include <boot_param.h>
> +
> +#define LIOINTC_CHIP_IRQ 32
> +#define LIOINTC_NUM_PARENT 4
> +
> +#define LIOINTC_INTC_CHIP_START 0x20
> +
> +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
> +#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
> +#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
> +#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
> +#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
> +#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
> +
> +#define LIOINTC_SHIFT_INTx 4
> +
> +struct liointc_handler_data {
> + struct liointc_priv *priv;
> + u32 parent_int_map;
> +};
> +
> +struct liointc_priv {
> + struct irq_chip_generic *gc;
> + struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
> + u8 map_cache[LIOINTC_CHIP_IRQ];
> +};
> +
> +static void liointc_chained_handle_irq(struct irq_desc *desc)
> +{
> + struct liointc_handler_data *handler =
> irq_desc_get_handler_data(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + struct irq_chip_generic *gc = handler->priv->gc;
> + u32 pending;
> +
> + chained_irq_enter(chip, desc);
> +
> + pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
> +
> + if (!pending)
> + spurious_interrupt();
> +
> + while (pending) {
> + int bit = __ffs(pending);
> +
> + generic_handle_irq(irq_find_mapping(gc->domain, bit));
> + pending &= ~BIT(bit);
> + }
Consider using the for_each_set_bit() macro from <linux/bitops.h>.
See drivers/irqchip/irq-ingenic-tcu.c for instance.
> +
> + chained_irq_exit(chip, desc);
> +}
> +
> +static void liointc_set_bit(struct irq_chip_generic *gc,
> + unsigned int offset,
> + u32 mask, bool set)
> +{
> + if (set)
> + writel(readl(gc->reg_base + offset) | mask,
> + gc->reg_base + offset);
> + else
> + writel(readl(gc->reg_base + offset) & ~mask,
> + gc->reg_base + offset);
> +}
> +
> +static int liointc_set_type(struct irq_data *data, unsigned int type)
> +{
> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
> + u32 mask = data->mask;
> + unsigned long flags;
> +
> + irq_gc_lock_irqsave(gc, flags);
> + switch (type) {
> + case IRQ_TYPE_LEVEL_HIGH:
> + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
> + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
> + break;
> + case IRQ_TYPE_LEVEL_LOW:
> + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
> + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
> + break;
> + case IRQ_TYPE_EDGE_RISING:
> + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
> + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
> + break;
> + case IRQ_TYPE_EDGE_FALLING:
> + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
> + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
> + break;
> + default:
> + return -EINVAL;
> + }
> + irq_gc_unlock_irqrestore(gc, flags);
> +
> + irqd_set_trigger_type(data, type);
> + return 0;
> +}
> +
> +static void liointc_resume(struct irq_chip_generic *gc)
> +{
> + struct liointc_priv *priv = gc->private;
> + unsigned long flags;
> + int i;
> +
> + irq_gc_lock_irqsave(gc, flags);
> + /* Disable all at first */
> + writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
> + /* Revert map cache */
> + for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
> + writeb(priv->map_cache[i], gc->reg_base + i);
> + /* Revert mask cache */
> + writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
> + irq_gc_unlock_irqrestore(gc, flags);
> +}
> +
> +static const char * const parent_names[] = {"int0", "int1", "int2",
> "int3"};
> +
> +int __init liointc_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct irq_chip_generic *gc;
> + struct irq_domain *domain;
> + struct irq_chip_type *ct;
> + struct liointc_priv *priv;
> + void __iomem *base;
> + u32 of_parent_int_map[LIOINTC_NUM_PARENT];
> + int parent_irq[LIOINTC_NUM_PARENT];
> + bool have_parent = FALSE;
> + int sz, i, err = 0;
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + base = of_iomap(node, 0);
> + if (!base) {
> + err = -ENODEV;
> + goto out_free_priv;
> + }
> +
> + for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
> + parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
> + if (parent_irq[i] > 0)
> + have_parent = TRUE;
> + }
> + if (!have_parent) {
> + err = -ENODEV;
> + goto out_iounmap;
> + }
> +
> + sz = of_property_read_variable_u32_array(node,
> + "loongson,parent_int_map",
> + &of_parent_int_map[0],
> + LIOINTC_NUM_PARENT,
> + LIOINTC_NUM_PARENT);
> + if (sz < 4) {
> + pr_err("loongson-liointc: No parent_int_map\n");
> + err = -ENODEV;
> + goto out_iounmap;
> + }
> +
> + for (i = 0; i < LIOINTC_NUM_PARENT; i++)
> + priv->handler[i].parent_int_map = of_parent_int_map[i];
> +
> + /* Setup IRQ domain */
> + domain = irq_domain_add_linear(node, 32,
> + &irq_generic_chip_ops, priv);
> + if (!domain) {
> + pr_err("loongson-liointc: cannot add IRQ domain\n");
> + err = -EINVAL;
> + goto out_iounmap;
> + }
> +
> + err = irq_alloc_domain_generic_chips(domain, 32, 1,
> + node->full_name, handle_level_irq,
> + IRQ_NOPROBE, 0, 0);
> + if (err) {
> + pr_err("loongson-liointc: unable to register IRQ domain\n");
> + goto out_free_domain;
> + }
> +
> +
> + /* Disable all IRQs */
> + writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
> + /* Set to level triggered */
> + writel(0x0, base + LIOINTC_REG_INTC_EDGE);
> +
> + /* Generate parent INT part of map cache */
> + for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
> + u32 pending = priv->handler[i].parent_int_map;
> +
> + while (pending) {
> + int bit = __ffs(pending);
> +
> + priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
> + pending &= ~BIT(bit);
> + }
Same here.
-Paul
> + }
> +
> + for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
> + /* Generate core part of map cache */
> + priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
> + writeb(priv->map_cache[i], base + i);
> + }
> +
> + gc = irq_get_domain_generic_chip(domain, 0);
> + gc->private = priv;
> + gc->reg_base = base;
> + gc->domain = domain;
> + gc->resume = liointc_resume;
> +
> + ct = gc->chip_types;
> + ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
> + ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
> + ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
> + ct->chip.irq_mask = irq_gc_mask_disable_reg;
> + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
> + ct->chip.irq_set_type = liointc_set_type;
> +
> + gc->mask_cache = 0xffffffff;
> + priv->gc = gc;
> +
> + for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
> + if (parent_irq[i] <= 0)
> + continue;
> +
> + priv->handler[i].priv = priv;
> + irq_set_chained_handler_and_data(parent_irq[i],
> + liointc_chained_handle_irq, &priv->handler[i]);
> + }
> +
> + return 0;
> +
> +out_free_domain:
> + irq_domain_remove(domain);
> +out_iounmap:
> + iounmap(base);
> +out_free_priv:
> + kfree(priv);
> +
> + return err;
> +}
> +
> +IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0",
> liointc_of_init);
> +IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a",
> liointc_of_init);
> --
> 2.26.0.rc2
>
>
On 2020-03-25 11:25, Paul Cercueil wrote:
> Hi Jiaxun,
>
>
> Le mer. 25 mars 2020 à 10:28, Jiaxun Yang <[email protected]> a
> écrit :
>> This controller appeared on Loongson family of chips as the primary
>> package interrupt source.
>>
>> Signed-off-by: Jiaxun Yang <[email protected]>
>> Co-developed-by: Huacai Chen <[email protected]>
>> Signed-off-by: Huacai Chen <[email protected]>
>> Reviewed-by: Marc Zyngier <[email protected]>
>> ---
>> v4-v5:
>> Resolve suggestions from maz:
>> - Remove DT validation
>> - Simplify unnucessary functions & variables
>> ---
>> drivers/irqchip/Kconfig | 9 +
>> drivers/irqchip/Makefile | 1 +
>> drivers/irqchip/irq-loongson-liointc.c | 261
>> +++++++++++++++++++++++++
>> 3 files changed, 271 insertions(+)
>> create mode 100644 drivers/irqchip/irq-loongson-liointc.c
>>
>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>> index 6d397732138d..c609eaa319d2 100644
>> --- a/drivers/irqchip/Kconfig
>> +++ b/drivers/irqchip/Kconfig
>> @@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER
>> Say yes here to add support for the IRQ combiner devices embedded
>> in Samsung Exynos chips.
>>
>> +config LOONGSON_LIOINTC
>> + bool "Loongson Local I/O Interrupt Controller"
>> + depends on MACH_LOONGSON64
>> + default y
>> + select IRQ_DOMAIN
>> + select GENERIC_IRQ_CHIP
>> + help
>> + Support for the Loongson Local I/O Interrupt Controller.
>> +
>> endmenu
>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> index eae0d78cbf22..5e7678efdfe6 100644
>> --- a/drivers/irqchip/Makefile
>> +++ b/drivers/irqchip/Makefile
>> @@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
>> obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
>> obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
>> obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
>> +obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o
>> diff --git a/drivers/irqchip/irq-loongson-liointc.c
>> b/drivers/irqchip/irq-loongson-liointc.c
>> new file mode 100644
>> index 000000000000..18de2c09ece4
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-loongson-liointc.c
>> @@ -0,0 +1,261 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020, Jiaxun Yang <[email protected]>
>> + * Loongson Local IO Interrupt Controller support
>> + */
>> +
>> +#include <linux/errno.h>
>> +#include <linux/init.h>
>> +#include <linux/types.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/ioport.h>
>> +#include <linux/irqchip.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/io.h>
>> +#include <linux/smp.h>
>> +#include <linux/irqchip/chained_irq.h>
>> +
>> +#include <boot_param.h>
>> +
>> +#define LIOINTC_CHIP_IRQ 32
>> +#define LIOINTC_NUM_PARENT 4
>> +
>> +#define LIOINTC_INTC_CHIP_START 0x20
>> +
>> +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
>> +#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
>> +#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
>> +#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
>> +#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
>> +#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
>> +
>> +#define LIOINTC_SHIFT_INTx 4
>> +
>> +struct liointc_handler_data {
>> + struct liointc_priv *priv;
>> + u32 parent_int_map;
>> +};
>> +
>> +struct liointc_priv {
>> + struct irq_chip_generic *gc;
>> + struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
>> + u8 map_cache[LIOINTC_CHIP_IRQ];
>> +};
>> +
>> +static void liointc_chained_handle_irq(struct irq_desc *desc)
>> +{
>> + struct liointc_handler_data *handler =
>> irq_desc_get_handler_data(desc);
>> + struct irq_chip *chip = irq_desc_get_chip(desc);
>> + struct irq_chip_generic *gc = handler->priv->gc;
>> + u32 pending;
>> +
>> + chained_irq_enter(chip, desc);
>> +
>> + pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
>> +
>> + if (!pending)
>> + spurious_interrupt();
>> +
>> + while (pending) {
>> + int bit = __ffs(pending);
>> +
>> + generic_handle_irq(irq_find_mapping(gc->domain, bit));
>> + pending &= ~BIT(bit);
>> + }
>
> Consider using the for_each_set_bit() macro from <linux/bitops.h>.
> See drivers/irqchip/irq-ingenic-tcu.c for instance.
which would require changing the pending type to be unsigned long.
Open-coding these if fine if it helps keeping the type system
consistent.
M.
--
Jazz is not dead. It just smells funny...
On Wed, Mar 25, 2020 at 11:54:59AM +0800, Jiaxun Yang wrote:
> The old code is using legacy domain to setup irq_domain for CPU interrupts
> which requires irq_desc to be preallocated.
>
> However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up
> unallocated and lead to incorrect behavior.
>
> Thus we convert the legacy domain to simple domain which can allocate
> irq_desc during initialization.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Co-developed-by: Huacai Chen <[email protected]>
> Signed-off-by: Huacai Chen <[email protected]>
> Reviewed-by: Marc Zyngier <[email protected]>
> ---
> drivers/irqchip/irq-mips-cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
> index 95d4fd8f7a96..c3cf7fa76424 100644
> --- a/drivers/irqchip/irq-mips-cpu.c
> +++ b/drivers/irqchip/irq-mips-cpu.c
> @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
> clear_c0_status(ST0_IM);
> clear_c0_cause(CAUSEF_IP);
>
> - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
> + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
> &mips_cpu_intc_irq_domain_ops,
> NULL);
this breaks at least IP30 and guess it will break every platform where
MIPS_CPU_IRQ_BASE == 0. add_legacy will always do irq_domain_associate_many(),
while add_simple doesn't do it, if first_irq == 0.
Marc, what is the reason not doing it all the time ? What's the correct
way here to work with irq_domain_add_simple() in this case ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
于 2020年3月25日 GMT+08:00 下午8:37:42, Thomas Bogendoerfer <[email protected]> 写到:
>On Wed, Mar 25, 2020 at 11:54:59AM +0800, Jiaxun Yang wrote:
>> The old code is using legacy domain to setup irq_domain for CPU
>interrupts
>> which requires irq_desc to be preallocated.
>>
>> However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end
>up
>> unallocated and lead to incorrect behavior.
>>
>> Thus we convert the legacy domain to simple domain which can allocate
>> irq_desc during initialization.
>>
>> Signed-off-by: Jiaxun Yang <[email protected]>
>> Co-developed-by: Huacai Chen <[email protected]>
>> Signed-off-by: Huacai Chen <[email protected]>
>> Reviewed-by: Marc Zyngier <[email protected]>
>> ---
>> drivers/irqchip/irq-mips-cpu.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/irqchip/irq-mips-cpu.c
>b/drivers/irqchip/irq-mips-cpu.c
>> index 95d4fd8f7a96..c3cf7fa76424 100644
>> --- a/drivers/irqchip/irq-mips-cpu.c
>> +++ b/drivers/irqchip/irq-mips-cpu.c
>> @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct
>device_node *of_node)
>> clear_c0_status(ST0_IM);
>> clear_c0_cause(CAUSEF_IP);
>>
>> - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE,
>0,
>> + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
>> &mips_cpu_intc_irq_domain_ops,
>> NULL);
>
>this breaks at least IP30 and guess it will break every platform where
>MIPS_CPU_IRQ_BASE == 0. add_legacy will always do
>irq_domain_associate_many(),
>while add_simple doesn't do it, if first_irq == 0.
>
>Marc, what is the reason not doing it all the time ? What's the correct
>way here to work with irq_domain_add_simple() in this case ?
I guess there is a inconsistent about whether IRQ 0 is a valid IRQ.
In many places we consider IRQ 0 is invalid but here it should be valid.
Thanks.
>
>Thomas.
--
Jiaxun Yang
On 2020-03-25 12:37, Thomas Bogendoerfer wrote:
> On Wed, Mar 25, 2020 at 11:54:59AM +0800, Jiaxun Yang wrote:
>> The old code is using legacy domain to setup irq_domain for CPU
>> interrupts
>> which requires irq_desc to be preallocated.
>>
>> However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end
>> up
>> unallocated and lead to incorrect behavior.
>>
>> Thus we convert the legacy domain to simple domain which can allocate
>> irq_desc during initialization.
>>
>> Signed-off-by: Jiaxun Yang <[email protected]>
>> Co-developed-by: Huacai Chen <[email protected]>
>> Signed-off-by: Huacai Chen <[email protected]>
>> Reviewed-by: Marc Zyngier <[email protected]>
>> ---
>> drivers/irqchip/irq-mips-cpu.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/irqchip/irq-mips-cpu.c
>> b/drivers/irqchip/irq-mips-cpu.c
>> index 95d4fd8f7a96..c3cf7fa76424 100644
>> --- a/drivers/irqchip/irq-mips-cpu.c
>> +++ b/drivers/irqchip/irq-mips-cpu.c
>> @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct
>> device_node *of_node)
>> clear_c0_status(ST0_IM);
>> clear_c0_cause(CAUSEF_IP);
>>
>> - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
>> + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
>> &mips_cpu_intc_irq_domain_ops,
>> NULL);
>
> this breaks at least IP30 and guess it will break every platform where
> MIPS_CPU_IRQ_BASE == 0. add_legacy will always do
> irq_domain_associate_many(),
> while add_simple doesn't do it, if first_irq == 0.
>
> Marc, what is the reason not doing it all the time ? What's the correct
> way here to work with irq_domain_add_simple() in this case ?
On a fully DT-ified platform, using non-legacy irqdomains, virtual
interrupts
are allocated as a "random" number, depending on the order of
allocation,
and on demand.
The first_irq hack in irq_domain_add_simple() is just a way to still
allocate
descriptors upfront (and I wish we could drop it...).
If you have legacy code that "knows" about the relationship between
Linux's
virtual interrupt and the hwirq (that is only meaningful to the
interrupt
controller), you're screwed, and need to stick to the legacy irqdomain.
It feels like the MIPS code is squarely in the latter case, so I guess
this
patch is probably the wrong thing to do for this architecture.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
于 2020年3月25日 GMT+08:00 下午9:00:01, Marc Zyngier <[email protected]> 写到:
>On 2020-03-25 12:37, Thomas Bogendoerfer wrote:
>> On Wed, Mar 25, 2020 at 11:54:59AM +0800, Jiaxun Yang wrote:
>>> The old code is using legacy domain to setup irq_domain for CPU
>>> interrupts
>>> which requires irq_desc to be preallocated.
>>>
>>> However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end
>
>>> up
>>> unallocated and lead to incorrect behavior.
>>>
>>> Thus we convert the legacy domain to simple domain which can
>allocate
>>> irq_desc during initialization.
>>>
>>> Signed-off-by: Jiaxun Yang <[email protected]>
>>> Co-developed-by: Huacai Chen <[email protected]>
>>> Signed-off-by: Huacai Chen <[email protected]>
>>> Reviewed-by: Marc Zyngier <[email protected]>
>>> ---
>>> drivers/irqchip/irq-mips-cpu.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/irqchip/irq-mips-cpu.c
>>> b/drivers/irqchip/irq-mips-cpu.c
>>> index 95d4fd8f7a96..c3cf7fa76424 100644
>>> --- a/drivers/irqchip/irq-mips-cpu.c
>>> +++ b/drivers/irqchip/irq-mips-cpu.c
>>> @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct
>>> device_node *of_node)
>>> clear_c0_status(ST0_IM);
>>> clear_c0_cause(CAUSEF_IP);
>>>
>>> - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE,
>0,
>>> + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
>>> &mips_cpu_intc_irq_domain_ops,
>>> NULL);
>>
>> this breaks at least IP30 and guess it will break every platform
>where
>> MIPS_CPU_IRQ_BASE == 0. add_legacy will always do
>> irq_domain_associate_many(),
>> while add_simple doesn't do it, if first_irq == 0.
>>
>> Marc, what is the reason not doing it all the time ? What's the
>correct
>> way here to work with irq_domain_add_simple() in this case ?
>
>On a fully DT-ified platform, using non-legacy irqdomains, virtual
>interrupts
>are allocated as a "random" number, depending on the order of
>allocation,
>and on demand.
>
>The first_irq hack in irq_domain_add_simple() is just a way to still
>allocate
>descriptors upfront (and I wish we could drop it...).
>
>If you have legacy code that "knows" about the relationship between
>Linux's
>virtual interrupt and the hwirq (that is only meaningful to the
>interrupt
>controller), you're screwed, and need to stick to the legacy irqdomain.
>
>It feels like the MIPS code is squarely in the latter case, so I guess
>this
>patch is probably the wrong thing to do for this architecture.
So probably we can use legacy domain when MIPS IRQ BASE is in the range of legacy IRQ
and switch to simple domain when it's not in that range?
Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did this hack.
Thanks.
>
>Thanks,
>
> M.
--
Jiaxun Yang
On 2020-03-25 13:07, Jiaxun Yang wrote:
> 于 2020年3月25日 GMT+08:00 下午9:00:01, Marc Zyngier <[email protected]> 写到:
>> On 2020-03-25 12:37, Thomas Bogendoerfer wrote:
>>> On Wed, Mar 25, 2020 at 11:54:59AM +0800, Jiaxun Yang wrote:
>>>> The old code is using legacy domain to setup irq_domain for CPU
>>>> interrupts
>>>> which requires irq_desc to be preallocated.
>>>>
>>>> However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end
>>
>>>> up
>>>> unallocated and lead to incorrect behavior.
>>>>
>>>> Thus we convert the legacy domain to simple domain which can
>> allocate
>>>> irq_desc during initialization.
>>>>
>>>> Signed-off-by: Jiaxun Yang <[email protected]>
>>>> Co-developed-by: Huacai Chen <[email protected]>
>>>> Signed-off-by: Huacai Chen <[email protected]>
>>>> Reviewed-by: Marc Zyngier <[email protected]>
>>>> ---
>>>> drivers/irqchip/irq-mips-cpu.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/irqchip/irq-mips-cpu.c
>>>> b/drivers/irqchip/irq-mips-cpu.c
>>>> index 95d4fd8f7a96..c3cf7fa76424 100644
>>>> --- a/drivers/irqchip/irq-mips-cpu.c
>>>> +++ b/drivers/irqchip/irq-mips-cpu.c
>>>> @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct
>>>> device_node *of_node)
>>>> clear_c0_status(ST0_IM);
>>>> clear_c0_cause(CAUSEF_IP);
>>>>
>>>> - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE,
>> 0,
>>>> + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE,
>>>> &mips_cpu_intc_irq_domain_ops,
>>>> NULL);
>>>
>>> this breaks at least IP30 and guess it will break every platform
>> where
>>> MIPS_CPU_IRQ_BASE == 0. add_legacy will always do
>>> irq_domain_associate_many(),
>>> while add_simple doesn't do it, if first_irq == 0.
>>>
>>> Marc, what is the reason not doing it all the time ? What's the
>> correct
>>> way here to work with irq_domain_add_simple() in this case ?
>>
>> On a fully DT-ified platform, using non-legacy irqdomains, virtual
>> interrupts
>> are allocated as a "random" number, depending on the order of
>> allocation,
>> and on demand.
>>
>> The first_irq hack in irq_domain_add_simple() is just a way to still
>> allocate
>> descriptors upfront (and I wish we could drop it...).
>>
>> If you have legacy code that "knows" about the relationship between
>> Linux's
>> virtual interrupt and the hwirq (that is only meaningful to the
>> interrupt
>> controller), you're screwed, and need to stick to the legacy
>> irqdomain.
>>
>> It feels like the MIPS code is squarely in the latter case, so I guess
>> this
>> patch is probably the wrong thing to do for this architecture.
>
> So probably we can use legacy domain when MIPS IRQ BASE is in the
> range of legacy IRQ
> and switch to simple domain when it's not in that range?
No, see below.
> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did this
> hack.
Well, if you have to consider which Linux IRQ gets assigned,
then your platform is definitely not ready for non-legacy
irqdomains. Just stick to legacy for now until you have removed
all the code that knows the hwirq mapping.
M.
--
Jazz is not dead. It just smells funny...
于 2020年3月25日 GMT+08:00 下午9:57:49, Marc Zyngier <[email protected]> 写到:
>On 2020-03-25 13:07, Jiaxun Yang wrote:
>> 于 2020年3月25日 GMT+08:00 下午9:00:01, Marc Zyngier <[email protected]> 写到:
>>> On 2020-03-25 12:37, Thomas Bogendoerfer wrote:
>>>> On Wed, Mar 25, 2020 at 11:54:59AM +0800, Jiaxun Yang wrote:
>>>>> The old code is using legacy domain to setup irq_domain for CPU
>>>>> interrupts
>>>>> which requires irq_desc to be preallocated.
>>>>>
>>>>> However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may
>end
>>>
>>>>> up
>>>>> unallocated and lead to incorrect behavior.
>>>>>
>>>>> Thus we convert the legacy domain to simple domain which can
>>> allocate
>>>>> irq_desc during initialization.
>>>>>
>>>>> Signed-off-by: Jiaxun Yang <[email protected]>
>>>>> Co-developed-by: Huacai Chen <[email protected]>
>>>>> Signed-off-by: Huacai Chen <[email protected]>
>>>>> Reviewed-by: Marc Zyngier <[email protected]>
>>>>> ---
>>>>> drivers/irqchip/irq-mips-cpu.c | 2 +-
>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/irqchip/irq-mips-cpu.c
>>>>> b/drivers/irqchip/irq-mips-cpu.c
>>>>> index 95d4fd8f7a96..c3cf7fa76424 100644
>>>>> --- a/drivers/irqchip/irq-mips-cpu.c
>>>>> +++ b/drivers/irqchip/irq-mips-cpu.c
>>>>> @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct
>>>>> device_node *of_node)
>>>>> clear_c0_status(ST0_IM);
>>>>> clear_c0_cause(CAUSEF_IP);
>>>>>
>>>>> - irq_domain = irq_domain_add_legacy(of_node, 8,
>MIPS_CPU_IRQ_BASE,
>>> 0,
>>>>> + irq_domain = irq_domain_add_simple(of_node, 8,
>MIPS_CPU_IRQ_BASE,
>>>>> &mips_cpu_intc_irq_domain_ops,
>>>>> NULL);
>>>>
>>>> this breaks at least IP30 and guess it will break every platform
>>> where
>>>> MIPS_CPU_IRQ_BASE == 0. add_legacy will always do
>>>> irq_domain_associate_many(),
>>>> while add_simple doesn't do it, if first_irq == 0.
>>>>
>>>> Marc, what is the reason not doing it all the time ? What's the
>>> correct
>>>> way here to work with irq_domain_add_simple() in this case ?
>>>
>>> On a fully DT-ified platform, using non-legacy irqdomains, virtual
>>> interrupts
>>> are allocated as a "random" number, depending on the order of
>>> allocation,
>>> and on demand.
>>>
>>> The first_irq hack in irq_domain_add_simple() is just a way to still
>>> allocate
>>> descriptors upfront (and I wish we could drop it...).
>>>
>>> If you have legacy code that "knows" about the relationship between
>>> Linux's
>>> virtual interrupt and the hwirq (that is only meaningful to the
>>> interrupt
>>> controller), you're screwed, and need to stick to the legacy
>>> irqdomain.
>>>
>>> It feels like the MIPS code is squarely in the latter case, so I
>guess
>>> this
>>> patch is probably the wrong thing to do for this architecture.
>>
>> So probably we can use legacy domain when MIPS IRQ BASE is in the
>> range of legacy IRQ
>> and switch to simple domain when it's not in that range?
>
>No, see below.
>
>> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did this
>> hack.
>
>Well, if you have to consider which Linux IRQ gets assigned,
>then your platform is definitely not ready for non-legacy
>irqdomains. Just stick to legacy for now until you have removed
>all the code that knows the hwirq mapping.
Thanks.
So I have to allocate irq_desc here in driver manually?
>
> M.
--
Jiaxun Yang
On 2020-03-25 13:59, Jiaxun Yang wrote:
[...]
>>> So probably we can use legacy domain when MIPS IRQ BASE is in the
>>> range of legacy IRQ
>>> and switch to simple domain when it's not in that range?
>>
>> No, see below.
>>
>>> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did this
>>> hack.
>>
>> Well, if you have to consider which Linux IRQ gets assigned,
>> then your platform is definitely not ready for non-legacy
>> irqdomains. Just stick to legacy for now until you have removed
>> all the code that knows the hwirq mapping.
>
> Thanks.
>
> So I have to allocate irq_desc here in driver manually?
No, you are probably better off just dropping this patch, as MIPS
doesn't seem to be ready for a wholesale switch to virtual interrupts.
M.
--
Jazz is not dead. It just smells funny...
于 2020年3月25日 GMT+08:00 下午10:15:16, Marc Zyngier <[email protected]> 写到:
>On 2020-03-25 13:59, Jiaxun Yang wrote:
>
>[...]
>
>>>> So probably we can use legacy domain when MIPS IRQ BASE is in the
>>>> range of legacy IRQ
>>>> and switch to simple domain when it's not in that range?
>>>
>>> No, see below.
>>>
>>>> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did
>this
>>>> hack.
>>>
>>> Well, if you have to consider which Linux IRQ gets assigned,
>>> then your platform is definitely not ready for non-legacy
>>> irqdomains. Just stick to legacy for now until you have removed
>>> all the code that knows the hwirq mapping.
>>
>> Thanks.
>>
>> So I have to allocate irq_desc here in driver manually?
>
>No, you are probably better off just dropping this patch, as MIPS
>doesn't seem to be ready for a wholesale switch to virtual interrupts.
It can't work without this patch.
Legacy domain require IRQ number within 0-15
however it's already occupied by i8259 or "HTPIC" driver.
Previously Loongson even didn't enable IRQ domain so it's not a problem.
>
> M.
--
Jiaxun Yang
On 2020-03-25 14:31, Jiaxun Yang wrote:
> 于 2020年3月25日 GMT+08:00 下午10:15:16, Marc Zyngier <[email protected]> 写到:
>> On 2020-03-25 13:59, Jiaxun Yang wrote:
>>
>> [...]
>>
>>>>> So probably we can use legacy domain when MIPS IRQ BASE is in the
>>>>> range of legacy IRQ
>>>>> and switch to simple domain when it's not in that range?
>>>>
>>>> No, see below.
>>>>
>>>>> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did
>> this
>>>>> hack.
>>>>
>>>> Well, if you have to consider which Linux IRQ gets assigned,
>>>> then your platform is definitely not ready for non-legacy
>>>> irqdomains. Just stick to legacy for now until you have removed
>>>> all the code that knows the hwirq mapping.
>>>
>>> Thanks.
>>>
>>> So I have to allocate irq_desc here in driver manually?
>>
>> No, you are probably better off just dropping this patch, as MIPS
>> doesn't seem to be ready for a wholesale switch to virtual interrupts.
>
> It can't work without this patch.
>
> Legacy domain require IRQ number within 0-15
> however it's already occupied by i8259 or "HTPIC" driver.
>
> Previously Loongson even didn't enable IRQ domain so it's not a
> problem.
Then your platform is breaking some fundamental assumption that the rest
of the MIPS architecture seem to rely on. You could test for the base
IRQ being 0 and create a legacy domain in this case, but that's really
a horrible hack.
I'm pretty worried about having to address this just 4 days away from
the merge window TBH, as this code hasn't been in -next at all.
That's really Thomas' call, but I'm not very enthusiastic.
M.
--
Jazz is not dead. It just smells funny...
On Wed, Mar 25, 2020 at 10:31:21PM +0800, Jiaxun Yang wrote:
>
>
> 于 2020年3月25日 GMT+08:00 下午10:15:16, Marc Zyngier <[email protected]> 写到:
> >On 2020-03-25 13:59, Jiaxun Yang wrote:
> >
> >[...]
> >
> >>>> So probably we can use legacy domain when MIPS IRQ BASE is in the
> >>>> range of legacy IRQ
> >>>> and switch to simple domain when it's not in that range?
> >>>
> >>> No, see below.
> >>>
> >>>> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did
> >this
> >>>> hack.
> >>>
> >>> Well, if you have to consider which Linux IRQ gets assigned,
> >>> then your platform is definitely not ready for non-legacy
> >>> irqdomains. Just stick to legacy for now until you have removed
> >>> all the code that knows the hwirq mapping.
> >>
> >> Thanks.
> >>
> >> So I have to allocate irq_desc here in driver manually?
> >
> >No, you are probably better off just dropping this patch, as MIPS
> >doesn't seem to be ready for a wholesale switch to virtual interrupts.
>
> It can't work without this patch.
>
> Legacy domain require IRQ number within 0-15
> however it's already occupied by i8259 or "HTPIC" driver.
what's the problem here ? AFAIK there could be more than one
legacy domain, at least that's what at least IP22/SNI in MIPS world
are doing.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
于 2020年3月25日 GMT+08:00 下午11:04:37, Thomas Bogendoerfer <[email protected]> 写到:
>On Wed, Mar 25, 2020 at 10:31:21PM +0800, Jiaxun Yang wrote:
>>
>>
>> 于 2020年3月25日 GMT+08:00 下午10:15:16, Marc Zyngier <[email protected]> 写到:
>> >On 2020-03-25 13:59, Jiaxun Yang wrote:
>> >
>> >[...]
>> >
>> >>>> So probably we can use legacy domain when MIPS IRQ BASE is in
>the
>> >>>> range of legacy IRQ
>> >>>> and switch to simple domain when it's not in that range?
>> >>>
>> >>> No, see below.
>> >>>
>> >>>> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did
>> >this
>> >>>> hack.
>> >>>
>> >>> Well, if you have to consider which Linux IRQ gets assigned,
>> >>> then your platform is definitely not ready for non-legacy
>> >>> irqdomains. Just stick to legacy for now until you have removed
>> >>> all the code that knows the hwirq mapping.
>> >>
>> >> Thanks.
>> >>
>> >> So I have to allocate irq_desc here in driver manually?
>> >
>> >No, you are probably better off just dropping this patch, as MIPS
>> >doesn't seem to be ready for a wholesale switch to virtual
>interrupts.
>>
>> It can't work without this patch.
>>
>> Legacy domain require IRQ number within 0-15
>> however it's already occupied by i8259 or "HTPIC" driver.
>
>what's the problem here ? AFAIK there could be more than one
>legacy domain, at least that's what at least IP22/SNI in MIPS world
>are doing.
MIPS_IRQ_BASE must be higher than 15, otherwise it will conflict with i8259.
However we have only preallocated irq_desc for 0-15.
And legacy domain require irq_desc being preallocated.
>
>Thomas.
--
Jiaxun Yang
On Wed, Mar 25, 2020 at 11:09:10PM +0800, Jiaxun Yang wrote:
>
>
> 于 2020年3月25日 GMT+08:00 下午11:04:37, Thomas Bogendoerfer <[email protected]> 写到:
> >On Wed, Mar 25, 2020 at 10:31:21PM +0800, Jiaxun Yang wrote:
> >>
> >>
> >> 于 2020年3月25日 GMT+08:00 下午10:15:16, Marc Zyngier <[email protected]> 写到:
> >> >On 2020-03-25 13:59, Jiaxun Yang wrote:
> >> >
> >> >[...]
> >> >
> >> >>>> So probably we can use legacy domain when MIPS IRQ BASE is in
> >the
> >> >>>> range of legacy IRQ
> >> >>>> and switch to simple domain when it's not in that range?
> >> >>>
> >> >>> No, see below.
> >> >>>
> >> >>>> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I did
> >> >this
> >> >>>> hack.
> >> >>>
> >> >>> Well, if you have to consider which Linux IRQ gets assigned,
> >> >>> then your platform is definitely not ready for non-legacy
> >> >>> irqdomains. Just stick to legacy for now until you have removed
> >> >>> all the code that knows the hwirq mapping.
> >> >>
> >> >> Thanks.
> >> >>
> >> >> So I have to allocate irq_desc here in driver manually?
> >> >
> >> >No, you are probably better off just dropping this patch, as MIPS
> >> >doesn't seem to be ready for a wholesale switch to virtual
> >interrupts.
> >>
> >> It can't work without this patch.
> >>
> >> Legacy domain require IRQ number within 0-15
> >> however it's already occupied by i8259 or "HTPIC" driver.
> >
> >what's the problem here ? AFAIK there could be more than one
> >legacy domain, at least that's what at least IP22/SNI in MIPS world
> >are doing.
>
> MIPS_IRQ_BASE must be higher than 15, otherwise it will conflict with i8259.
I still don't get it.
We have following in arch/mips/include/asm/mach-generic/irq.h:
#ifndef MIPS_CPU_IRQ_BASE
#ifdef CONFIG_I8259
#define MIPS_CPU_IRQ_BASE 16
#else
#define MIPS_CPU_IRQ_BASE 0
#endif /* CONFIG_I8259 */
#endif
So every legacy platform with i8259 has MIPS_CPU_IRQ_BASE = 16.
> However we have only preallocated irq_desc for 0-15.
> And legacy domain require irq_desc being preallocated.
maybe I'm too fast by judging the irq code, but without CONFIG_SPARSE_IRQ
the whole irq_desc is pre-allocated.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
于 2020年3月25日 GMT+08:00 下午11:46:00, Thomas Bogendoerfer <[email protected]> 写到:
>On Wed, Mar 25, 2020 at 11:09:10PM +0800, Jiaxun Yang wrote:
>>
>>
>> 于 2020年3月25日 GMT+08:00 下午11:04:37, Thomas Bogendoerfer
><[email protected]> 写到:
>> >On Wed, Mar 25, 2020 at 10:31:21PM +0800, Jiaxun Yang wrote:
>> >>
>> >>
>> >> 于 2020年3月25日 GMT+08:00 下午10:15:16, Marc Zyngier <[email protected]>
>写到:
>> >> >On 2020-03-25 13:59, Jiaxun Yang wrote:
>> >> >
>> >> >[...]
>> >> >
>> >> >>>> So probably we can use legacy domain when MIPS IRQ BASE is
>in
>> >the
>> >> >>>> range of legacy IRQ
>> >> >>>> and switch to simple domain when it's not in that range?
>> >> >>>
>> >> >>> No, see below.
>> >> >>>
>> >> >>>> Here in Loongson systems IRQ 0-15 is occupied by I8259 so I
>did
>> >> >this
>> >> >>>> hack.
>> >> >>>
>> >> >>> Well, if you have to consider which Linux IRQ gets assigned,
>> >> >>> then your platform is definitely not ready for non-legacy
>> >> >>> irqdomains. Just stick to legacy for now until you have
>removed
>> >> >>> all the code that knows the hwirq mapping.
>> >> >>
>> >> >> Thanks.
>> >> >>
>> >> >> So I have to allocate irq_desc here in driver manually?
>> >> >
>> >> >No, you are probably better off just dropping this patch, as MIPS
>> >> >doesn't seem to be ready for a wholesale switch to virtual
>> >interrupts.
>> >>
>> >> It can't work without this patch.
>> >>
>> >> Legacy domain require IRQ number within 0-15
>> >> however it's already occupied by i8259 or "HTPIC" driver.
>> >
>> >what's the problem here ? AFAIK there could be more than one
>> >legacy domain, at least that's what at least IP22/SNI in MIPS world
>> >are doing.
>>
>> MIPS_IRQ_BASE must be higher than 15, otherwise it will conflict with
>i8259.
>
>I still don't get it.
>
>We have following in arch/mips/include/asm/mach-generic/irq.h:
>
>#ifndef MIPS_CPU_IRQ_BASE
>#ifdef CONFIG_I8259
>#define MIPS_CPU_IRQ_BASE 16
>#else
>#define MIPS_CPU_IRQ_BASE 0
>#endif /* CONFIG_I8259 */
>#endif
>
>So every legacy platform with i8259 has MIPS_CPU_IRQ_BASE = 16.
>
>> However we have only preallocated irq_desc for 0-15.
>> And legacy domain require irq_desc being preallocated.
>
>maybe I'm too fast by judging the irq code, but without
>CONFIG_SPARSE_IRQ
>the whole irq_desc is pre-allocated.
Sorry. You're right.
I found the problem is CONFIG_SPARSE_IRQ is accidentally enabled in my config due to another out-of-tree patch
during my initial test and I always consider it as a problem.
So we can drop this patch safely for now.
But just need to consider how to deal with it when we want to enable SPARSE_IRQ.
Thanks.
>
>Thomas.
--
Jiaxun Yang
On Thu, Mar 26, 2020 at 12:02:28AM +0800, Jiaxun Yang wrote:
> >maybe I'm too fast by judging the irq code, but without
> >CONFIG_SPARSE_IRQ
> >the whole irq_desc is pre-allocated.
>
> Sorry. You're right.
> I found the problem is CONFIG_SPARSE_IRQ is accidentally enabled in my config due to another out-of-tree patch
ok, that explains it.
> during my initial test and I always consider it as a problem.
>
> So we can drop this patch safely for now.
already dropped in my test branch. If nothing shows up, I'll push
it to mips-next.
> But just need to consider how to deal with it when we want to enable SPARSE_IRQ.
setting NR_IRQS_LEGACY so a sensible value should do the trick then.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
On Wed, Mar 25, 2020 at 11:54:53AM +0800, Jiaxun Yang wrote:
> Loongson have a long history of contributing their code to mainline kernel.
> However, it seems like recent years, they are focusing on maintain a kernel by themselves
> rather than contribute there code to the community.
>
> Kernel is progress rapidly too. Their code slept in mainline for a long peroid without proper
> maintainance and became outdated.
>
> This patchset brings modern DeviceTree and irqchip support to the Loongson64 machine, and leaves
> Loongson 2e/f alone since they are too legacy to touch.
>
> PCI and some legacy I/O device will be converted later, together with LS7A PCH support.
applied series minus patch 6 to mips-next.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]