LinuxLists.cc - [PATCH 0/4] Add support for Agilex5 SoCFPGA platform

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Subject: [PATCH 3/4] clk: socfpga: agilex5: Add clock driver for Agilex5 platform

From: Niravkumar L Rabara <[email protected]>

The clock manager driver for Agilex5 is very similar to the Agilex
platform. This patch makes the necessary changes for the driver to
differentiate between the Agilex and the Agilex5 platforms.

Signed-off-by: Teh Wen Ping <[email protected]>
Signed-off-by: Niravkumar L Rabara <[email protected]>
---
drivers/clk/socfpga/Kconfig | 4 +-
drivers/clk/socfpga/Makefile | 2 +-
drivers/clk/socfpga/clk-agilex5.c | 843 ++++++++++++++++++++++++++++
drivers/clk/socfpga/clk-pll-s10.c | 48 ++
drivers/clk/socfpga/stratix10-clk.h | 2 +
5 files changed, 896 insertions(+), 3 deletions(-)
create mode 100644 drivers/clk/socfpga/clk-agilex5.c

diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig
index 0cf16b894efb..e82c0cda3245 100644
--- a/drivers/clk/socfpga/Kconfig
+++ b/drivers/clk/socfpga/Kconfig
@@ -4,7 +4,7 @@ config CLK_INTEL_SOCFPGA
default ARCH_INTEL_SOCFPGA
help
Support for the clock controllers present on Intel SoCFPGA and eASIC
- devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC.
+ devices like Aria, Cyclone, Stratix 10, Agilex, N5X eASIC and Agilex5.

if CLK_INTEL_SOCFPGA

@@ -13,7 +13,7 @@ config CLK_INTEL_SOCFPGA32
default ARM && ARCH_INTEL_SOCFPGA

config CLK_INTEL_SOCFPGA64
- bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
+ bool "Intel Stratix / Agilex / N5X clock / Agilex5 controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
default ARM64 && ARCH_INTEL_SOCFPGA

endif # CLK_INTEL_SOCFPGA
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index e8dfce339c91..a1ea2b988eaf 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -3,4 +3,4 @@ obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \
clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \
clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \
- clk-agilex.o
+ clk-agilex.o clk-agilex5.o
diff --git a/drivers/clk/socfpga/clk-agilex5.c b/drivers/clk/socfpga/clk-agilex5.c
new file mode 100644
index 000000000000..2d597176a98d
--- /dev/null
+++ b/drivers/clk/socfpga/clk-agilex5.c
@@ -0,0 +1,843 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022, Intel Corporation
+ */
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/agilex5-clock.h>
+
+#include "stratix10-clk.h"
+
+static const struct clk_parent_data pll_mux[] = {
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data boot_mux[] = {
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+};
+
+static const struct clk_parent_data core0_free_mux[] = {
+ {
+ .fw_name = "main_pll_c1",
+ .name = "main_pll_c1",
+ },
+ {
+ .fw_name = "peri_pll_c0",
+ .name = "peri_pll_c0",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data core1_free_mux[] = {
+ {
+ .fw_name = "main_pll_c1",
+ .name = "main_pll_c1",
+ },
+ {
+ .fw_name = "peri_pll_c0",
+ .name = "peri_pll_c0",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data core2_free_mux[] = {
+ {
+ .fw_name = "main_pll_c0",
+ .name = "main_pll_c0",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data core3_free_mux[] = {
+ {
+ .fw_name = "main_pll_c0",
+ .name = "main_pll_c0",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data dsu_free_mux[] = {
+ {
+ .fw_name = "main_pll_c2",
+ .name = "main_pll_c2",
+ },
+ {
+ .fw_name = "peri_pll_c0",
+ .name = "peri_pll_c0",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data noc_free_mux[] = {
+ {
+ .fw_name = "main_pll_c3",
+ .name = "main_pll_c3",
+ },
+ {
+ .fw_name = "peri_pll_c1",
+ .name = "peri_pll_c1",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data emaca_free_mux[] = {
+ {
+ .fw_name = "main_pll_c1",
+ .name = "main_pll_c1",
+ },
+ {
+ .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data emacb_free_mux[] = {
+ {
+ .fw_name = "main_pll_c1",
+ .name = "main_pll_c1",
+ },
+ {
+ .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data emac_ptp_free_mux[] = {
+ {
+ .fw_name = "main_pll_c1",
+ .name = "main_pll_c1",
+ },
+ {
+ .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data gpio_db_free_mux[] = {
+ {
+ .fw_name = "main_pll_c3",
+ .name = "main_pll_c3",
+ },
+ {
+ .fw_name = "peri_pll_c1",
+ .name = "peri_pll_c1",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data psi_ref_free_mux[] = {
+ {
+ .fw_name = "main_pll_c1",
+ .name = "main_pll_c1",
+ },
+ {
+ .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data usb31_free_mux[] = {
+ {
+ .fw_name = "main_pll_c3",
+ .name = "main_pll_c3",
+ },
+ {
+ .fw_name = "peri_pll_c2",
+ .name = "peri_pll_c2",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data s2f_usr0_free_mux[] = {
+ {
+ .fw_name = "main_pll_c1",
+ .name = "main_pll_c1",
+ },
+ {
+ .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data s2f_usr1_free_mux[] = {
+ {
+ .fw_name = "main_pll_c1",
+ .name = "main_pll_c1",
+ },
+ {
+ .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3",
+ },
+ {
+ .fw_name = "osc1",
+ .name = "osc1",
+ },
+ {
+ .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk",
+ },
+ {
+ .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk",
+ },
+};
+
+static const struct clk_parent_data core0_mux[] = {
+ {
+ .fw_name = "core0_free_clk",
+ .name = "core0_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data core1_mux[] = {
+ {
+ .fw_name = "core1_free_clk",
+ .name = "core1_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data core2_mux[] = {
+ {
+ .fw_name = "core2_free_clk",
+ .name = "core2_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data core3_mux[] = {
+ {
+ .fw_name = "core3_free_clk",
+ .name = "core3_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data dsu_mux[] = {
+ {
+ .fw_name = "dsu_free_clk",
+ .name = "dsu_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data emac_mux[] = {
+ {
+ .fw_name = "emaca_free_clk",
+ .name = "emaca_free_clk",
+ },
+ {
+ .fw_name = "emacb_free_clk",
+ .name = "emacb_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data noc_mux[] = {
+ {
+ .fw_name = "noc_free_clk",
+ .name = "noc_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data s2f_user0_mux[] = {
+ {
+ .fw_name = "s2f_user0_free_clk",
+ .name = "s2f_user0_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data s2f_user1_mux[] = {
+ {
+ .fw_name = "s2f_user1_free_clk",
+ .name = "s2f_user1_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data psi_mux[] = {
+ {
+ .fw_name = "psi_ref_free_clk",
+ .name = "psi_ref_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data gpio_db_mux[] = {
+ {
+ .fw_name = "gpio_db_free_clk",
+ .name = "gpio_db_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data emac_ptp_mux[] = {
+ {
+ .fw_name = "emac_ptp_free_clk",
+ .name = "emac_ptp_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+static const struct clk_parent_data usb31_mux[] = {
+ {
+ .fw_name = "usb31_free_clk",
+ .name = "usb31_free_clk",
+ },
+ {
+ .fw_name = "boot_clk",
+ .name = "boot_clk",
+ },
+};
+
+/*
+ * TODO - Clocks in AO (always on) controller
+ * 2 main PLLs only
+ */
+static const struct stratix10_pll_clock agilex5_pll_clks[] = {
+ { AGILEX5_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
+ 0x0 },
+ { AGILEX5_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux), 0,
+ 0x48 },
+ { AGILEX5_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux), 0,
+ 0x9C },
+};
+
+static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = {
+ { AGILEX5_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0,
+ 0x5C },
+ { AGILEX5_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0,
+ 0x60 },
+ { AGILEX5_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0,
+ 0x64 },
+ { AGILEX5_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0,
+ 0x68 },
+ { AGILEX5_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0,
+ 0xB0 },
+ { AGILEX5_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0,
+ 0xB4 },
+ { AGILEX5_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0,
+ 0xB8 },
+ { AGILEX5_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0,
+ 0xBC },
+};
+
+/* Non-SW clock-gated enabled clocks */
+static const struct stratix10_perip_cnt_clock agilex5_main_perip_cnt_clks[] = {
+ { AGILEX5_CORE0_FREE_CLK, "core0_free_clk", NULL, core0_free_mux,
+ ARRAY_SIZE(core0_free_mux), 0, 0x0104, 0, 0, 0},
+ { AGILEX5_CORE1_FREE_CLK, "core1_free_clk", NULL, core1_free_mux,
+ ARRAY_SIZE(core1_free_mux), 0, 0x0104, 0, 0, 0},
+ { AGILEX5_CORE2_FREE_CLK, "core2_free_clk", NULL, core2_free_mux,
+ ARRAY_SIZE(core2_free_mux), 0, 0x010C, 0, 0, 0},
+ { AGILEX5_CORE3_FREE_CLK, "core3_free_clk", NULL, core3_free_mux,
+ ARRAY_SIZE(core3_free_mux), 0, 0x0110, 0, 0, 0},
+ { AGILEX5_DSU_FREE_CLK, "dsu_free_clk", NULL, dsu_free_mux,
+ ARRAY_SIZE(dsu_free_mux), 0, 0x0100, 0, 0, 0},
+ { AGILEX5_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux,
+ ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 },
+ { AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux,
+ ARRAY_SIZE(emaca_free_mux), 0, 0xD4, 0, 0x88, 0 },
+ { AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux,
+ ARRAY_SIZE(emacb_free_mux), 0, 0xD8, 0, 0x88, 1 },
+ { AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL,
+ emac_ptp_free_mux, ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88,
+ 2 },
+ { AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
+ ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3 },
+ { AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL,
+ s2f_usr0_free_mux, ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30,
+ 2 },
+ { AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL,
+ s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88,
+ 5 },
+ { AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
+ ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6 },
+ { AGILEX5_USB31_FREE_CLK, "usb31_free_clk", NULL, usb31_free_mux,
+ ARRAY_SIZE(usb31_free_mux), 0, 0xF8, 0, 0x88, 7},
+};
+
+/* SW Clock gate enabled clocks */
+static const struct stratix10_gate_clock agilex5_gate_clks[] = {
+ /* Main PLL0 Begin */
+ /* MPU clocks */
+ { AGILEX5_CORE0_CLK, "core0_clk", NULL, core0_mux,
+ ARRAY_SIZE(core0_mux), 0, 0x24, 8, 0, 0, 0, 0x30, 5, 0 },
+ { AGILEX5_CORE1_CLK, "core1_clk", NULL, core1_mux,
+ ARRAY_SIZE(core1_mux), 0, 0x24, 9, 0, 0, 0, 0x30, 5, 0 },
+ { AGILEX5_CORE2_CLK, "core2_clk", NULL, core2_mux,
+ ARRAY_SIZE(core2_mux), 0, 0x24, 10, 0, 0, 0, 0x30, 6, 0 },
+ { AGILEX5_CORE3_CLK, "core3_clk", NULL, core3_mux,
+ ARRAY_SIZE(core3_mux), 0, 0x24, 11, 0, 0, 0, 0x30, 7, 0 },
+ { AGILEX5_MPU_CLK, "dsu_clk", NULL, dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0,
+ 0, 0, 0, 0, 0x34, 4, 0 },
+ { AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", NULL, dsu_mux,
+ ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 20, 2, 0x34, 4, 0 },
+ { AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", NULL, dsu_mux,
+ ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 18, 2, 0x34, 4, 0 },
+
+ /* l4 main clk has no divider now */
+ { AGILEX5_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux,
+ ARRAY_SIZE(noc_mux), 0, 0x24, 1, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
+ 0x24, 2, 0x44, 4, 2, 0x30, 1, 0 },
+ { AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux,
+ ARRAY_SIZE(noc_mux), 0, 0, 0, 0x44, 2, 2, 0x30, 1, 0 },
+ { AGILEX5_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
+ CLK_IS_CRITICAL, 0x24, 3, 0x44, 6, 2, 0x30, 1, 0 },
+
+ /* Core sight clocks*/
+ { AGILEX5_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
+ 0x24, 4, 0x44, 24, 2, 0x30, 1, 0 },
+ { AGILEX5_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux,
+ ARRAY_SIZE(noc_mux), 0, 0x24, 4, 0x44, 26, 2, 0x30, 1, 0 },
+ { AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, 4,
+ 0x44, 28, 1, 0, 0, 0 },
+ /* Main PLL0 End */
+
+ /* Main Peripheral PLL1 Begin */
+ { AGILEX5_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+ 0, 0x7C, 0, 0, 0, 0, 0x94, 26, 0 },
+ { AGILEX5_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+ 0, 0x7C, 1, 0, 0, 0, 0x94, 27, 0 },
+ { AGILEX5_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+ 0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0 },
+ { AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux,
+ ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, 3, 0, 0, 0, 0x88, 2, 0 },
+ { AGILEX5_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux,
+ ARRAY_SIZE(gpio_db_mux), 0, 0x7C, 4, 0x98, 0, 16, 0x88, 3, 0 },
+ /* Main Peripheral PLL1 End */
+
+ /* Peripheral clocks */
+ { AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux,
+ ARRAY_SIZE(s2f_user0_mux), 0, 0x24, 6, 0, 0, 0, 0x30, 2, 0 },
+ { AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux,
+ ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0 },
+ { AGILEX5_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux,
+ ARRAY_SIZE(psi_mux), 0, 0x7C, 7, 0, 0, 0, 0x88, 6, 0 },
+ { AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", NULL, usb31_mux,
+ ARRAY_SIZE(usb31_mux), 0, 0x7C, 25, 0, 0, 0, 0x88, 7, 0 },
+ { AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", "l4_main_clk",
+ NULL, 1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+ 8, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPIM_0_CLK, "spim_0_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 9,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPIM_1_CLK, "spim_1_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 11,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPIS_0_CLK, "spis_0_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 12,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPIS_1_CLK, "spis_1_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 13,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_DMA_CORE_CLK, "dma_core_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+ 14, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_DMA_HS_CLK, "dma_hs_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 14,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", "l4_mp_clk", NULL, 1, 0,
+ 0x7C, 18, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", "l4_mp_clk", NULL, 1, 0,
+ 0x7C, 19, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_0_PCLK, "i2c_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 15,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_1_PCLK, "i2c_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 16,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 17, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 22, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 27, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_UART_0_PCLK, "uart_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 20,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_UART_1_PCLK, "uart_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 21,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 23, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 24, 0, 0, 0, 0, 0, 0 },
+
+ /*NAND, SD/MMC and SoftPHY overall clocking*/
+ { AGILEX5_DFI_CLK, "dfi_clk", "l4_mp_clk", NULL, 1, 0, 0, 0, 0x44, 16,
+ 2, 0, 0, 0 },
+ { AGILEX5_NAND_NF_CLK, "nand_nf_clk", "dfi_clk", NULL, 1, 0, 0x7C, 10,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_NAND_BCH_CLK, "nand_bch_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+ 10, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", "l4_mp_clk", NULL,
+ 1, 0, 0x7C, 5, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SDMCLK, "sdmclk", "dfi_clk", NULL, 1, 0, 0x7C, 5, 0, 0, 0, 0,
+ 0, 0 },
+ { AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", "l4_mp_clk", NULL, 1, 0,
+ 0x7C, 26, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", "l4_mp_clk", NULL, 1, 0,
+ 0x7C, 26, 0x44, 16, 2, 0, 0, 0 },
+ { AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", "dfi_clk", NULL, 1, 0,
+ 0x7C, 26, 0, 0, 0, 0, 0, 0 },
+};
+
+static int
+agilex5_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
+ int nums, struct stratix10_clock_data *data)
+{
+ struct clk_hw *hw_clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ hw_clk = s10_register_periph(&clks[i], base);
+ if (IS_ERR(hw_clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ clks[i].name);
+ continue;
+ }
+ data->clk_data.hws[clks[i].id] = hw_clk;
+ }
+ return 0;
+}
+
+static int
+agilex5_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
+ int nums, struct stratix10_clock_data *data)
+{
+ struct clk_hw *hw_clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ hw_clk = s10_register_cnt_periph(&clks[i], base);
+ if (IS_ERR(hw_clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ clks[i].name);
+ continue;
+ }
+ data->clk_data.hws[clks[i].id] = hw_clk;
+ }
+
+ return 0;
+}
+
+static int agilex5_clk_register_gate(const struct stratix10_gate_clock *clks,
+ int nums,
+ struct stratix10_clock_data *data)
+{
+ struct clk_hw *hw_clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ hw_clk = agilex_register_gate(&clks[i], base);
+ if (IS_ERR(hw_clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ clks[i].name);
+ continue;
+ }
+ data->clk_data.hws[clks[i].id] = hw_clk;
+ }
+
+ return 0;
+}
+
+static int agilex5_clk_register_pll(const struct stratix10_pll_clock *clks,
+ int nums, struct stratix10_clock_data *data)
+{
+ struct clk_hw *hw_clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ hw_clk = agilex5_register_pll(&clks[i], base);
+ if (IS_ERR(hw_clk)) {
+ pr_err("%s: failed to register clock %s\n", __func__,
+ clks[i].name);
+ continue;
+ }
+ data->clk_data.hws[clks[i].id] = hw_clk;
+ }
+
+ return 0;
+}
+
+static int agilex5_clkmgr_init(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct stratix10_clock_data *clk_data;
+ struct resource *res;
+ void __iomem *base;
+ int i, num_clks;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ num_clks = AGILEX5_NUM_CLKS;
+
+ clk_data = devm_kzalloc(dev,
+ struct_size(clk_data, clk_data.hws, num_clks),
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ for (i = 0; i < num_clks; i++)
+ clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
+
+ clk_data->base = base;
+ clk_data->clk_data.num = num_clks;
+
+ agilex5_clk_register_pll(agilex5_pll_clks, ARRAY_SIZE(agilex5_pll_clks),
+ clk_data);
+
+ agilex5_clk_register_c_perip(agilex5_main_perip_c_clks,
+ ARRAY_SIZE(agilex5_main_perip_c_clks),
+ clk_data);
+
+ agilex5_clk_register_cnt_perip(agilex5_main_perip_cnt_clks,
+ ARRAY_SIZE(agilex5_main_perip_cnt_clks),
+ clk_data);
+
+ agilex5_clk_register_gate(agilex5_gate_clks,
+ ARRAY_SIZE(agilex5_gate_clks), clk_data);
+
+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
+ return 0;
+}
+
+static int agilex5_clkmgr_probe(struct platform_device *pdev)
+{
+ int (*probe_func)(struct platform_device *init_func);
+
+ probe_func = of_device_get_match_data(&pdev->dev);
+ if (!probe_func)
+ return -ENODEV;
+ return probe_func(pdev);
+}
+
+static const struct of_device_id agilex5_clkmgr_match_table[] = {
+ { .compatible = "intel,agilex5-clkmgr", .data = agilex5_clkmgr_init },
+ {}
+};
+
+static struct platform_driver agilex5_clkmgr_driver = {
+ .probe = agilex5_clkmgr_probe,
+ .driver = {
+ .name = "agilex5-clkmgr",
+ .suppress_bind_attrs = true,
+ .of_match_table = agilex5_clkmgr_match_table,
+ },
+};
+
+static int __init agilex5_clk_init(void)
+{
+ return platform_driver_register(&agilex5_clkmgr_driver);
+}
+core_initcall(agilex5_clk_init);
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index 1d82737befd3..e3367d34bc55 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -175,6 +175,14 @@ static const struct clk_ops agilex_clk_pll_ops = {
.prepare = clk_pll_prepare,
};

+/* TODO need to fix, Agilex5 SM requires change */
+static const struct clk_ops agilex5_clk_pll_ops = {
+ /* TODO This may require a custom Agilex5 implementation */
+ .recalc_rate = agilex_clk_pll_recalc_rate,
+ .get_parent = clk_pll_get_parent,
+ .prepare = clk_pll_prepare,
+};
+
static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
@@ -304,3 +312,43 @@ struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
}
return hw_clk;
}
+
+struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
+ void __iomem *reg)
+{
+ struct clk_hw *hw_clk;
+ struct socfpga_pll *pll_clk;
+ struct clk_init_data init;
+ const char *name = clks->name;
+ int ret;
+
+ pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
+ if (WARN_ON(!pll_clk))
+ return NULL;
+
+ pll_clk->hw.reg = reg + clks->offset;
+
+ if (streq(name, SOCFPGA_BOOT_CLK))
+ init.ops = &clk_boot_ops;
+ else
+ init.ops = &agilex5_clk_pll_ops;
+
+ init.name = name;
+ init.flags = clks->flags;
+
+ init.num_parents = clks->num_parents;
+ init.parent_names = NULL;
+ init.parent_data = clks->parent_data;
+ pll_clk->hw.hw.init = &init;
+
+ pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
+ hw_clk = &pll_clk->hw.hw;
+
+ ret = clk_hw_register(NULL, hw_clk);
+ if (ret) {
+ kfree(pll_clk);
+ return ERR_PTR(ret);
+ }
+ return hw_clk;
+}
+
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index 75234e0783e1..468e0f0ab4ab 100644
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -77,6 +77,8 @@ struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
void __iomem *reg);
struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
void __iomem *reg);
+struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
+ void __iomem *reg);
struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
void __iomem *reg);
struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
--
2.25.1

2023-06-20 14:50:39

[permalink] [raw]

Subject: Re: [PATCH 3/4] clk: socfpga: agilex5: Add clock driver for Agilex5 platform

On 6/18/23 08:22, [email protected] wrote:
> From: Niravkumar L Rabara <[email protected]>
>
> The clock manager driver for Agilex5 is very similar to the Agilex

Then why create a whole new driver? Surely there's alot of re-use you
can do?

> platform. This patch makes the necessary changes for the driver to
> differentiate between the Agilex and the Agilex5 platforms.
>
> Signed-off-by: Teh Wen Ping <[email protected]>
> Signed-off-by: Niravkumar L Rabara <[email protected]>
> ---
> drivers/clk/socfpga/Kconfig | 4 +-
> drivers/clk/socfpga/Makefile | 2 +-
> drivers/clk/socfpga/clk-agilex5.c | 843 ++++++++++++++++++++++++++++
> drivers/clk/socfpga/clk-pll-s10.c | 48 ++
> drivers/clk/socfpga/stratix10-clk.h | 2 +
> 5 files changed, 896 insertions(+), 3 deletions(-)
> create mode 100644 drivers/clk/socfpga/clk-agilex5.c
>
> diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig
> index 0cf16b894efb..e82c0cda3245 100644
> --- a/drivers/clk/socfpga/Kconfig
> +++ b/drivers/clk/socfpga/Kconfig
> @@ -4,7 +4,7 @@ config CLK_INTEL_SOCFPGA
> default ARCH_INTEL_SOCFPGA
> help
> Support for the clock controllers present on Intel SoCFPGA and eASIC
> - devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC.
> + devices like Aria, Cyclone, Stratix 10, Agilex, N5X eASIC and Agilex5.
>
> if CLK_INTEL_SOCFPGA
>
> @@ -13,7 +13,7 @@ config CLK_INTEL_SOCFPGA32
> default ARM && ARCH_INTEL_SOCFPGA
>
> config CLK_INTEL_SOCFPGA64
> - bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
> + bool "Intel Stratix / Agilex / N5X clock / Agilex5 controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
> default ARM64 && ARCH_INTEL_SOCFPGA
>
> endif # CLK_INTEL_SOCFPGA
> diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
> index e8dfce339c91..a1ea2b988eaf 100644
> --- a/drivers/clk/socfpga/Makefile
> +++ b/drivers/clk/socfpga/Makefile
> @@ -3,4 +3,4 @@ obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \
> clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
> obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \
> clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \
> - clk-agilex.o
> + clk-agilex.o clk-agilex5.o
> diff --git a/drivers/clk/socfpga/clk-agilex5.c b/drivers/clk/socfpga/clk-agilex5.c
> new file mode 100644
> index 000000000000..2d597176a98d
> --- /dev/null
> +++ b/drivers/clk/socfpga/clk-agilex5.c
> @@ -0,0 +1,843 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022, Intel Corporation

It's 2023 now!
> + */
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/agilex5-clock.h>
> +
> +#include "stratix10-clk.h"
> +
> +static const struct clk_parent_data pll_mux[] = {
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data boot_mux[] = {
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> +};
> +
> +static const struct clk_parent_data core0_free_mux[] = {
> + {
> + .fw_name = "main_pll_c1",
> + .name = "main_pll_c1",
> + },
> + {
> + .fw_name = "peri_pll_c0",
> + .name = "peri_pll_c0",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data core1_free_mux[] = {
> + {
> + .fw_name = "main_pll_c1",
> + .name = "main_pll_c1",
> + },
> + {
> + .fw_name = "peri_pll_c0",
> + .name = "peri_pll_c0",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data core2_free_mux[] = {
> + {
> + .fw_name = "main_pll_c0",
> + .name = "main_pll_c0",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data core3_free_mux[] = {
> + {
> + .fw_name = "main_pll_c0",
> + .name = "main_pll_c0",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data dsu_free_mux[] = {
> + {
> + .fw_name = "main_pll_c2",
> + .name = "main_pll_c2",
> + },
> + {
> + .fw_name = "peri_pll_c0",
> + .name = "peri_pll_c0",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data noc_free_mux[] = {
> + {
> + .fw_name = "main_pll_c3",
> + .name = "main_pll_c3",
> + },
> + {
> + .fw_name = "peri_pll_c1",
> + .name = "peri_pll_c1",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data emaca_free_mux[] = {
> + {
> + .fw_name = "main_pll_c1",
> + .name = "main_pll_c1",
> + },
> + {
> + .fw_name = "peri_pll_c3",
> + .name = "peri_pll_c3",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data emacb_free_mux[] = {
> + {
> + .fw_name = "main_pll_c1",
> + .name = "main_pll_c1",
> + },
> + {
> + .fw_name = "peri_pll_c3",
> + .name = "peri_pll_c3",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data emac_ptp_free_mux[] = {
> + {
> + .fw_name = "main_pll_c1",
> + .name = "main_pll_c1",
> + },
> + {
> + .fw_name = "peri_pll_c3",
> + .name = "peri_pll_c3",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data gpio_db_free_mux[] = {
> + {
> + .fw_name = "main_pll_c3",
> + .name = "main_pll_c3",
> + },
> + {
> + .fw_name = "peri_pll_c1",
> + .name = "peri_pll_c1",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data psi_ref_free_mux[] = {
> + {
> + .fw_name = "main_pll_c1",
> + .name = "main_pll_c1",
> + },
> + {
> + .fw_name = "peri_pll_c3",
> + .name = "peri_pll_c3",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data usb31_free_mux[] = {
> + {
> + .fw_name = "main_pll_c3",
> + .name = "main_pll_c3",
> + },
> + {
> + .fw_name = "peri_pll_c2",
> + .name = "peri_pll_c2",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data s2f_usr0_free_mux[] = {
> + {
> + .fw_name = "main_pll_c1",
> + .name = "main_pll_c1",
> + },
> + {
> + .fw_name = "peri_pll_c3",
> + .name = "peri_pll_c3",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data s2f_usr1_free_mux[] = {
> + {
> + .fw_name = "main_pll_c1",
> + .name = "main_pll_c1",
> + },
> + {
> + .fw_name = "peri_pll_c3",
> + .name = "peri_pll_c3",
> + },
> + {
> + .fw_name = "osc1",
> + .name = "osc1",
> + },
> + {
> + .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk",
> + },
> + {
> + .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk",
> + },
> +};
> +
> +static const struct clk_parent_data core0_mux[] = {
> + {
> + .fw_name = "core0_free_clk",
> + .name = "core0_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data core1_mux[] = {
> + {
> + .fw_name = "core1_free_clk",
> + .name = "core1_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data core2_mux[] = {
> + {
> + .fw_name = "core2_free_clk",
> + .name = "core2_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data core3_mux[] = {
> + {
> + .fw_name = "core3_free_clk",
> + .name = "core3_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data dsu_mux[] = {
> + {
> + .fw_name = "dsu_free_clk",
> + .name = "dsu_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data emac_mux[] = {
> + {
> + .fw_name = "emaca_free_clk",
> + .name = "emaca_free_clk",
> + },
> + {
> + .fw_name = "emacb_free_clk",
> + .name = "emacb_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data noc_mux[] = {
> + {
> + .fw_name = "noc_free_clk",
> + .name = "noc_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data s2f_user0_mux[] = {
> + {
> + .fw_name = "s2f_user0_free_clk",
> + .name = "s2f_user0_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data s2f_user1_mux[] = {
> + {
> + .fw_name = "s2f_user1_free_clk",
> + .name = "s2f_user1_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data psi_mux[] = {
> + {
> + .fw_name = "psi_ref_free_clk",
> + .name = "psi_ref_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data gpio_db_mux[] = {
> + {
> + .fw_name = "gpio_db_free_clk",
> + .name = "gpio_db_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data emac_ptp_mux[] = {
> + {
> + .fw_name = "emac_ptp_free_clk",
> + .name = "emac_ptp_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +static const struct clk_parent_data usb31_mux[] = {
> + {
> + .fw_name = "usb31_free_clk",
> + .name = "usb31_free_clk",
> + },
> + {
> + .fw_name = "boot_clk",
> + .name = "boot_clk",
> + },
> +};
> +
> +/*
> + * TODO - Clocks in AO (always on) controller

Remove your TODO, so did you do it already?

> + * 2 main PLLs only
> + */
> +static const struct stratix10_pll_clock agilex5_pll_clks[] = {
> + { AGILEX5_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
> + 0x0 },
> + { AGILEX5_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux), 0,
> + 0x48 },
> + { AGILEX5_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux), 0,
> + 0x9C },
> +};
> +
> +static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = {
> + { AGILEX5_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0,
> + 0x5C },
> + { AGILEX5_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0,
> + 0x60 },
> + { AGILEX5_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0,
> + 0x64 },
> + { AGILEX5_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0,
> + 0x68 },
> + { AGILEX5_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0,
> + 0xB0 },
> + { AGILEX5_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0,
> + 0xB4 },
> + { AGILEX5_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0,
> + 0xB8 },
> + { AGILEX5_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0,
> + 0xBC },
> +};
> +
> +/* Non-SW clock-gated enabled clocks */
> +static const struct stratix10_perip_cnt_clock agilex5_main_perip_cnt_clks[] = {
> + { AGILEX5_CORE0_FREE_CLK, "core0_free_clk", NULL, core0_free_mux,
> + ARRAY_SIZE(core0_free_mux), 0, 0x0104, 0, 0, 0},
> + { AGILEX5_CORE1_FREE_CLK, "core1_free_clk", NULL, core1_free_mux,
> + ARRAY_SIZE(core1_free_mux), 0, 0x0104, 0, 0, 0},
> + { AGILEX5_CORE2_FREE_CLK, "core2_free_clk", NULL, core2_free_mux,
> + ARRAY_SIZE(core2_free_mux), 0, 0x010C, 0, 0, 0},
> + { AGILEX5_CORE3_FREE_CLK, "core3_free_clk", NULL, core3_free_mux,
> + ARRAY_SIZE(core3_free_mux), 0, 0x0110, 0, 0, 0},
> + { AGILEX5_DSU_FREE_CLK, "dsu_free_clk", NULL, dsu_free_mux,
> + ARRAY_SIZE(dsu_free_mux), 0, 0x0100, 0, 0, 0},
> + { AGILEX5_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux,
> + ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 },
> + { AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux,
> + ARRAY_SIZE(emaca_free_mux), 0, 0xD4, 0, 0x88, 0 },
> + { AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux,
> + ARRAY_SIZE(emacb_free_mux), 0, 0xD8, 0, 0x88, 1 },
> + { AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL,
> + emac_ptp_free_mux, ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88,
> + 2 },
> + { AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
> + ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3 },
> + { AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL,
> + s2f_usr0_free_mux, ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30,
> + 2 },
> + { AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL,
> + s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88,
> + 5 },
> + { AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
> + ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6 },
> + { AGILEX5_USB31_FREE_CLK, "usb31_free_clk", NULL, usb31_free_mux,
> + ARRAY_SIZE(usb31_free_mux), 0, 0xF8, 0, 0x88, 7},
> +};
> +
> +/* SW Clock gate enabled clocks */
> +static const struct stratix10_gate_clock agilex5_gate_clks[] = {
> + /* Main PLL0 Begin */
> + /* MPU clocks */
> + { AGILEX5_CORE0_CLK, "core0_clk", NULL, core0_mux,
> + ARRAY_SIZE(core0_mux), 0, 0x24, 8, 0, 0, 0, 0x30, 5, 0 },
> + { AGILEX5_CORE1_CLK, "core1_clk", NULL, core1_mux,
> + ARRAY_SIZE(core1_mux), 0, 0x24, 9, 0, 0, 0, 0x30, 5, 0 },
> + { AGILEX5_CORE2_CLK, "core2_clk", NULL, core2_mux,
> + ARRAY_SIZE(core2_mux), 0, 0x24, 10, 0, 0, 0, 0x30, 6, 0 },
> + { AGILEX5_CORE3_CLK, "core3_clk", NULL, core3_mux,
> + ARRAY_SIZE(core3_mux), 0, 0x24, 11, 0, 0, 0, 0x30, 7, 0 },
> + { AGILEX5_MPU_CLK, "dsu_clk", NULL, dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0,
> + 0, 0, 0, 0, 0x34, 4, 0 },
> + { AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", NULL, dsu_mux,
> + ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 20, 2, 0x34, 4, 0 },
> + { AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", NULL, dsu_mux,
> + ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 18, 2, 0x34, 4, 0 },
> +
> + /* l4 main clk has no divider now */
> + { AGILEX5_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux,
> + ARRAY_SIZE(noc_mux), 0, 0x24, 1, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
> + 0x24, 2, 0x44, 4, 2, 0x30, 1, 0 },
> + { AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux,
> + ARRAY_SIZE(noc_mux), 0, 0, 0, 0x44, 2, 2, 0x30, 1, 0 },
> + { AGILEX5_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
> + CLK_IS_CRITICAL, 0x24, 3, 0x44, 6, 2, 0x30, 1, 0 },
> +
> + /* Core sight clocks*/
> + { AGILEX5_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
> + 0x24, 4, 0x44, 24, 2, 0x30, 1, 0 },
> + { AGILEX5_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux,
> + ARRAY_SIZE(noc_mux), 0, 0x24, 4, 0x44, 26, 2, 0x30, 1, 0 },
> + { AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, 4,
> + 0x44, 28, 1, 0, 0, 0 },
> + /* Main PLL0 End */
> +
> + /* Main Peripheral PLL1 Begin */
> + { AGILEX5_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
> + 0, 0x7C, 0, 0, 0, 0, 0x94, 26, 0 },
> + { AGILEX5_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
> + 0, 0x7C, 1, 0, 0, 0, 0x94, 27, 0 },
> + { AGILEX5_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
> + 0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0 },
> + { AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux,
> + ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, 3, 0, 0, 0, 0x88, 2, 0 },
> + { AGILEX5_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux,
> + ARRAY_SIZE(gpio_db_mux), 0, 0x7C, 4, 0x98, 0, 16, 0x88, 3, 0 },
> + /* Main Peripheral PLL1 End */
> +
> + /* Peripheral clocks */
> + { AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux,
> + ARRAY_SIZE(s2f_user0_mux), 0, 0x24, 6, 0, 0, 0, 0x30, 2, 0 },
> + { AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux,
> + ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0 },
> + { AGILEX5_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux,
> + ARRAY_SIZE(psi_mux), 0, 0x7C, 7, 0, 0, 0, 0x88, 6, 0 },
> + { AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", NULL, usb31_mux,
> + ARRAY_SIZE(usb31_mux), 0, 0x7C, 25, 0, 0, 0, 0x88, 7, 0 },
> + { AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", "l4_main_clk",
> + NULL, 1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", "l4_mp_clk", NULL, 1, 0, 0x7C,
> + 8, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SPIM_0_CLK, "spim_0_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 9,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SPIM_1_CLK, "spim_1_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 11,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SPIS_0_CLK, "spis_0_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 12,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SPIS_1_CLK, "spis_1_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 13,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_DMA_CORE_CLK, "dma_core_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
> + 14, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_DMA_HS_CLK, "dma_hs_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 14,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", "l4_mp_clk", NULL, 1, 0,
> + 0x7C, 18, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", "l4_mp_clk", NULL, 1, 0,
> + 0x7C, 19, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_I2C_0_PCLK, "i2c_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 15,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_I2C_1_PCLK, "i2c_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 16,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", "l4_sp_clk", NULL, 1, 0,
> + 0x7C, 17, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", "l4_sp_clk", NULL, 1, 0,
> + 0x7C, 22, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", "l4_sp_clk", NULL, 1, 0,
> + 0x7C, 27, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_UART_0_PCLK, "uart_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 20,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_UART_1_PCLK, "uart_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 21,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", "l4_sp_clk", NULL, 1, 0,
> + 0x7C, 23, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", "l4_sp_clk", NULL, 1, 0,
> + 0x7C, 24, 0, 0, 0, 0, 0, 0 },
> +
> + /*NAND, SD/MMC and SoftPHY overall clocking*/
> + { AGILEX5_DFI_CLK, "dfi_clk", "l4_mp_clk", NULL, 1, 0, 0, 0, 0x44, 16,
> + 2, 0, 0, 0 },
> + { AGILEX5_NAND_NF_CLK, "nand_nf_clk", "dfi_clk", NULL, 1, 0, 0x7C, 10,
> + 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_NAND_BCH_CLK, "nand_bch_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
> + 10, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", "l4_mp_clk", NULL,
> + 1, 0, 0x7C, 5, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SDMCLK, "sdmclk", "dfi_clk", NULL, 1, 0, 0x7C, 5, 0, 0, 0, 0,
> + 0, 0 },
> + { AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", "l4_mp_clk", NULL, 1, 0,
> + 0x7C, 26, 0, 0, 0, 0, 0, 0 },
> + { AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", "l4_mp_clk", NULL, 1, 0,
> + 0x7C, 26, 0x44, 16, 2, 0, 0, 0 },
> + { AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", "dfi_clk", NULL, 1, 0,
> + 0x7C, 26, 0, 0, 0, 0, 0, 0 },
> +};
> +

As far as I can tell, there are very little differences between this and
Agilex! Please reuse!

> +static int
> +agilex5_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
> + int nums, struct stratix10_clock_data *data)
> +{
> + struct clk_hw *hw_clk;
> + void __iomem *base = data->base;
> + int i;
> +
> + for (i = 0; i < nums; i++) {
> + hw_clk = s10_register_periph(&clks[i], base);
> + if (IS_ERR(hw_clk)) {
> + pr_err("%s: failed to register clock %s\n", __func__,
> + clks[i].name);
> + continue;
> + }
> + data->clk_data.hws[clks[i].id] = hw_clk;
> + }
> + return 0;
> +}
> +
> +static int
> +agilex5_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
> + int nums, struct stratix10_clock_data *data)
> +{
> + struct clk_hw *hw_clk;
> + void __iomem *base = data->base;
> + int i;
> +
> + for (i = 0; i < nums; i++) {
> + hw_clk = s10_register_cnt_periph(&clks[i], base);
> + if (IS_ERR(hw_clk)) {
> + pr_err("%s: failed to register clock %s\n", __func__,
> + clks[i].name);
> + continue;
> + }
> + data->clk_data.hws[clks[i].id] = hw_clk;
> + }
> +
> + return 0;
> +}
> +
> +static int agilex5_clk_register_gate(const struct stratix10_gate_clock *clks,
> + int nums,
> + struct stratix10_clock_data *data)
> +{
> + struct clk_hw *hw_clk;
> + void __iomem *base = data->base;
> + int i;
> +
> + for (i = 0; i < nums; i++) {
> + hw_clk = agilex_register_gate(&clks[i], base);
> + if (IS_ERR(hw_clk)) {
> + pr_err("%s: failed to register clock %s\n", __func__,
> + clks[i].name);
> + continue;
> + }
> + data->clk_data.hws[clks[i].id] = hw_clk;
> + }
> +
> + return 0;
> +}
> +
> +static int agilex5_clk_register_pll(const struct stratix10_pll_clock *clks,
> + int nums, struct stratix10_clock_data *data)
> +{
> + struct clk_hw *hw_clk;
> + void __iomem *base = data->base;
> + int i;
> +
> + for (i = 0; i < nums; i++) {
> + hw_clk = agilex5_register_pll(&clks[i], base);
> + if (IS_ERR(hw_clk)) {
> + pr_err("%s: failed to register clock %s\n", __func__,
> + clks[i].name);
> + continue;
> + }
> + data->clk_data.hws[clks[i].id] = hw_clk;
> + }
> +
> + return 0;
> +}
> +
> +static int agilex5_clkmgr_init(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct stratix10_clock_data *clk_data;
> + struct resource *res;
> + void __iomem *base;
> + int i, num_clks;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + num_clks = AGILEX5_NUM_CLKS;
> +
> + clk_data = devm_kzalloc(dev,
> + struct_size(clk_data, clk_data.hws, num_clks),
> + GFP_KERNEL);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + for (i = 0; i < num_clks; i++)
> + clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
> +
> + clk_data->base = base;
> + clk_data->clk_data.num = num_clks;
> +
> + agilex5_clk_register_pll(agilex5_pll_clks, ARRAY_SIZE(agilex5_pll_clks),
> + clk_data);
> +
> + agilex5_clk_register_c_perip(agilex5_main_perip_c_clks,
> + ARRAY_SIZE(agilex5_main_perip_c_clks),
> + clk_data);
> +
> + agilex5_clk_register_cnt_perip(agilex5_main_perip_cnt_clks,
> + ARRAY_SIZE(agilex5_main_perip_cnt_clks),
> + clk_data);
> +
> + agilex5_clk_register_gate(agilex5_gate_clks,
> + ARRAY_SIZE(agilex5_gate_clks), clk_data);
> +
> + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
> + return 0;
> +}
> +
> +static int agilex5_clkmgr_probe(struct platform_device *pdev)
> +{
> + int (*probe_func)(struct platform_device *init_func);
> +
> + probe_func = of_device_get_match_data(&pdev->dev);
> + if (!probe_func)
> + return -ENODEV;
> + return probe_func(pdev);
> +}
> +
> +static const struct of_device_id agilex5_clkmgr_match_table[] = {
> + { .compatible = "intel,agilex5-clkmgr", .data = agilex5_clkmgr_init },
> + {}
> +};
> +
> +static struct platform_driver agilex5_clkmgr_driver = {
> + .probe = agilex5_clkmgr_probe,
> + .driver = {
> + .name = "agilex5-clkmgr",
> + .suppress_bind_attrs = true,
> + .of_match_table = agilex5_clkmgr_match_table,
> + },
> +};
> +
> +static int __init agilex5_clk_init(void)
> +{
> + return platform_driver_register(&agilex5_clkmgr_driver);
> +}
> +core_initcall(agilex5_clk_init);
> diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
> index 1d82737befd3..e3367d34bc55 100644
> --- a/drivers/clk/socfpga/clk-pll-s10.c
> +++ b/drivers/clk/socfpga/clk-pll-s10.c
> @@ -175,6 +175,14 @@ static const struct clk_ops agilex_clk_pll_ops = {
> .prepare = clk_pll_prepare,
> };
>
> +/* TODO need to fix, Agilex5 SM requires change */
> +static const struct clk_ops agilex5_clk_pll_ops = {
> + /* TODO This may require a custom Agilex5 implementation */
> + .recalc_rate = agilex_clk_pll_recalc_rate,
> + .get_parent = clk_pll_get_parent,
> + .prepare = clk_pll_prepare,
> +};
> +
> static const struct clk_ops clk_pll_ops = {
> .recalc_rate = clk_pll_recalc_rate,
> .get_parent = clk_pll_get_parent,
> @@ -304,3 +312,43 @@ struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
> }
> return hw_clk;
> }
> +
> +struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
> + void __iomem *reg)
> +{
> + struct clk_hw *hw_clk;
> + struct socfpga_pll *pll_clk;
> + struct clk_init_data init;
> + const char *name = clks->name;
> + int ret;
> +
> + pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
> + if (WARN_ON(!pll_clk))
> + return NULL;
> +
> + pll_clk->hw.reg = reg + clks->offset;
> +
> + if (streq(name, SOCFPGA_BOOT_CLK))
> + init.ops = &clk_boot_ops;
> + else
> + init.ops = &agilex5_clk_pll_ops;
> +
> + init.name = name;
> + init.flags = clks->flags;
> +
> + init.num_parents = clks->num_parents;
> + init.parent_names = NULL;
> + init.parent_data = clks->parent_data;
> + pll_clk->hw.hw.init = &init;
> +
> + pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
> + hw_clk = &pll_clk->hw.hw;
> +
> + ret = clk_hw_register(NULL, hw_clk);
> + if (ret) {
> + kfree(pll_clk);
> + return ERR_PTR(ret);
> + }
> + return hw_clk;
> +}

Both functions are identical to Agilex, so why the need to recreate?

> +
> diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
> index 75234e0783e1..468e0f0ab4ab 100644
> --- a/drivers/clk/socfpga/stratix10-clk.h
> +++ b/drivers/clk/socfpga/stratix10-clk.h
> @@ -77,6 +77,8 @@ struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
> void __iomem *reg);
> struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
> void __iomem *reg);
> +struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
> + void __iomem *reg);
> struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
> void __iomem *reg);
> struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,

I'd like for you to send this whole patchset for my internal review
before you send out a V2!

Dinh

2023-08-01 02:13:19

[permalink] [raw]

Subject: [PATCH v2 0/5] Add support for Agilex5 SoCFPGA platform

From: Niravkumar L Rabara <[email protected]>

patch [1/5] - Introduced compatible string for Agilex5 board.
patch [2/5] - Add Agilex5 reset ID definitions.
patch [3/5] - Add Agilex5 clock manager header and yaml file.
patch [4/5] - Reused and modified Agilex clock manager driver for
Agilex5 to avoid code duplication. This patch depends on patch 4.
patch [5/5] - Add device tree files for Agilex5 platform. This patch
depends on patch 1,2,3 & 4.

patch v2 changes:-
- Add separate discription and const for Agilex5 board in yaml file.
- Add reset ID definitions required for Agilex5 and reused
altr,rst-mgr-s10 bindings similar to Agilex.
- Instead of creating separate clock manager driver, re-use agilex clock
manager driver and modified it for agilex5 changes to avoid code
duplicate.
- Fixed device tree alignment issues and other build warnings.
Removed ethernet nodes as it will be included in a separate patch.

Niravkumar L Rabara (5):
dt-bindings: intel: Add Intel Agilex5 compatible
dt-bindings: reset: add reset IDs for Agilex5
dt-bindings: clock: add Intel Agilex5 clock manager
clk: socfpga: agilex: add clock driver for the Agilex5
arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA

.../bindings/arm/intel,socfpga.yaml | 5 +
.../bindings/clock/intel,agilex5-clkmgr.yaml | 41 ++
arch/arm64/boot/dts/intel/Makefile | 1 +
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 468 ++++++++++++++++++
.../boot/dts/intel/socfpga_agilex5_socdk.dts | 39 ++
drivers/clk/socfpga/clk-agilex.c | 433 +++++++++++++++-
.../dt-bindings/clock/intel,agilex5-clkmgr.h | 100 ++++
include/dt-bindings/reset/altr,rst-mgr-s10.h | 5 +-
8 files changed, 1089 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h

--
2.25.1

2023-08-01 02:17:09

[permalink] [raw]

Subject: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

From: Niravkumar L Rabara <[email protected]>

Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.

Signed-off-by: Teh Wen Ping <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
Signed-off-by: Niravkumar L Rabara <[email protected]>
---
.../bindings/clock/intel,agilex5-clkmgr.yaml | 41 +++++++
.../dt-bindings/clock/intel,agilex5-clkmgr.h | 100 ++++++++++++++++++
2 files changed, 141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h

diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
new file mode 100644
index 000000000000..60e57a9fb939
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Agilex5 clock manager
+
+maintainers:
+ - Dinh Nguyen <[email protected]>
+
+description:
+ The Intel Agilex5 Clock Manager is an integrated clock controller, which
+ generates and supplies clock to all the modules.
+
+properties:
+ compatible:
+ const: intel,agilex5-clkmgr
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock controller node:
+ - |
+ clkmgr: clock-controller@10d10000 {
+ compatible = "intel,agilex5-clkmgr";
+ reg = <0x10d10000 0x1000>;
+ #clock-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/intel,agilex5-clkmgr.h b/include/dt-bindings/clock/intel,agilex5-clkmgr.h
new file mode 100644
index 000000000000..2f3a23b31c5c
--- /dev/null
+++ b/include/dt-bindings/clock/intel,agilex5-clkmgr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023, Intel Corporation
+ */
+
+#ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
+#define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
+
+/* fixed rate clocks */
+#define AGILEX5_OSC1 0
+#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1
+#define AGILEX5_CB_INTOSC_LS_CLK 2
+#define AGILEX5_F2S_FREE_CLK 3
+
+/* PLL clocks */
+#define AGILEX5_MAIN_PLL_CLK 4
+#define AGILEX5_MAIN_PLL_C0_CLK 5
+#define AGILEX5_MAIN_PLL_C1_CLK 6
+#define AGILEX5_MAIN_PLL_C2_CLK 7
+#define AGILEX5_MAIN_PLL_C3_CLK 8
+#define AGILEX5_PERIPH_PLL_CLK 9
+#define AGILEX5_PERIPH_PLL_C0_CLK 10
+#define AGILEX5_PERIPH_PLL_C1_CLK 11
+#define AGILEX5_PERIPH_PLL_C2_CLK 12
+#define AGILEX5_PERIPH_PLL_C3_CLK 13
+#define AGILEX5_CORE0_FREE_CLK 14
+#define AGILEX5_CORE1_FREE_CLK 15
+#define AGILEX5_CORE2_FREE_CLK 16
+#define AGILEX5_CORE3_FREE_CLK 17
+#define AGILEX5_DSU_FREE_CLK 18
+#define AGILEX5_BOOT_CLK 19
+
+/* fixed factor clocks */
+#define AGILEX5_L3_MAIN_FREE_CLK 20
+#define AGILEX5_NOC_FREE_CLK 21
+#define AGILEX5_S2F_USR0_CLK 22
+#define AGILEX5_NOC_CLK 23
+#define AGILEX5_EMAC_A_FREE_CLK 24
+#define AGILEX5_EMAC_B_FREE_CLK 25
+#define AGILEX5_EMAC_PTP_FREE_CLK 26
+#define AGILEX5_GPIO_DB_FREE_CLK 27
+#define AGILEX5_S2F_USER0_FREE_CLK 28
+#define AGILEX5_S2F_USER1_FREE_CLK 29
+#define AGILEX5_PSI_REF_FREE_CLK 30
+#define AGILEX5_USB31_FREE_CLK 31
+
+/* Gate clocks */
+#define AGILEX5_CORE0_CLK 32
+#define AGILEX5_CORE1_CLK 33
+#define AGILEX5_CORE2_CLK 34
+#define AGILEX5_CORE3_CLK 35
+#define AGILEX5_MPU_CLK 36
+#define AGILEX5_MPU_PERIPH_CLK 37
+#define AGILEX5_MPU_CCU_CLK 38
+#define AGILEX5_L4_MAIN_CLK 39
+#define AGILEX5_L4_MP_CLK 40
+#define AGILEX5_L4_SYS_FREE_CLK 41
+#define AGILEX5_L4_SP_CLK 42
+#define AGILEX5_CS_AT_CLK 43
+#define AGILEX5_CS_TRACE_CLK 44
+#define AGILEX5_CS_PDBG_CLK 45
+#define AGILEX5_EMAC1_CLK 47
+#define AGILEX5_EMAC2_CLK 48
+#define AGILEX5_EMAC_PTP_CLK 49
+#define AGILEX5_GPIO_DB_CLK 50
+#define AGILEX5_S2F_USER0_CLK 51
+#define AGILEX5_S2F_USER1_CLK 52
+#define AGILEX5_PSI_REF_CLK 53
+#define AGILEX5_USB31_SUSPEND_CLK 54
+#define AGILEX5_EMAC0_CLK 46
+#define AGILEX5_USB31_BUS_CLK_EARLY 55
+#define AGILEX5_USB2OTG_HCLK 56
+#define AGILEX5_SPIM_0_CLK 57
+#define AGILEX5_SPIM_1_CLK 58
+#define AGILEX5_SPIS_0_CLK 59
+#define AGILEX5_SPIS_1_CLK 60
+#define AGILEX5_DMA_CORE_CLK 61
+#define AGILEX5_DMA_HS_CLK 62
+#define AGILEX5_I3C_0_CORE_CLK 63
+#define AGILEX5_I3C_1_CORE_CLK 64
+#define AGILEX5_I2C_0_PCLK 65
+#define AGILEX5_I2C_1_PCLK 66
+#define AGILEX5_I2C_EMAC0_PCLK 67
+#define AGILEX5_I2C_EMAC1_PCLK 68
+#define AGILEX5_I2C_EMAC2_PCLK 69
+#define AGILEX5_UART_0_PCLK 70
+#define AGILEX5_UART_1_PCLK 71
+#define AGILEX5_SPTIMER_0_PCLK 72
+#define AGILEX5_SPTIMER_1_PCLK 73
+#define AGILEX5_DFI_CLK 74
+#define AGILEX5_NAND_NF_CLK 75
+#define AGILEX5_NAND_BCH_CLK 76
+#define AGILEX5_SDMMC_SDPHY_REG_CLK 77
+#define AGILEX5_SDMCLK 78
+#define AGILEX5_SOFTPHY_REG_PCLK 79
+#define AGILEX5_SOFTPHY_PHY_CLK 80
+#define AGILEX5_SOFTPHY_CTRL_CLK 81
+#define AGILEX5_NUM_CLKS 82
+
+#endif /* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */
--
2.25.1

2023-08-01 02:44:35

[permalink] [raw]

Subject: [PATCH v2 5/5] arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA

From: Niravkumar L Rabara <[email protected]>

Add the initial device tree files for Intel Agilex5 SoCFPGA platform.

Reviewed-by: Dinh Nguyen <[email protected]>
Signed-off-by: Niravkumar L Rabara <[email protected]>
---
arch/arm64/boot/dts/intel/Makefile | 1 +
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 468 ++++++++++++++++++
.../boot/dts/intel/socfpga_agilex5_socdk.dts | 39 ++
3 files changed, 508 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index c2a723838344..d39cfb723f5b 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -2,5 +2,6 @@
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
+ socfpga_agilex5_socdk.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
new file mode 100644
index 000000000000..dcdaf7064953
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, Intel Corporation
+ */
+
+/dts-v1/;
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/intel,agilex5-clkmgr.h>
+
+/ {
+ compatible = "intel,socfpga-agilex5";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ service_reserved: svcbuffer@0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80000000 0x0 0x2000000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a76";
+ reg = <0x200>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a76";
+ reg = <0x300>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ intc: interrupt-controller@1d000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x1d000000 0 0x10000>,
+ <0x0 0x1d060000 0 0x100000>;
+ ranges;
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells =<2>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+
+ its: msi-controller@1d040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x1d040000 0x0 0x20000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ /* Clock tree 5 main sources*/
+ clocks {
+ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ cb_intosc_ls_clk: cb-intosc-ls-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ f2s_free_clk: f2s-free-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ qspi_clk: qspi-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ usbphy0: usbphy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ ranges = <0 0 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+
+ clkmgr: clock-controller@10d10000 {
+ compatible = "intel,agilex5-clkmgr";
+ reg = <0x10d10000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ i2c0: i2c@10c02800 {
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst I2C0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10c02900 {
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst I2C1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10c02a00 {
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02a00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst I2C2_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@10c02b00 {
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02b00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst I2C3_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@10c02c00 {
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02c00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst I2C4_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i3c0: i3c-master@10da0000 {
+ compatible = "snps,dw-i3c-master-1.00a";
+ reg = <0x10da0000 0x1000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
+ status = "disabled";
+ };
+
+ i3c1: i3c-master@10da1000 {
+ compatible = "snps,dw-i3c-master-1.00a";
+ reg = <0x10da1000 0x1000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@10c03300 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x10c03300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&rst GPIO1_RESET>;
+ status = "disabled";
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ nand: nand-controller@10b80000 {
+ compatible = "cdns,hp-nfc";
+ reg = <0x10b80000 0x10000>,
+ <0x10840000 0x10000>;
+ reg-names = "reg", "sdma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
+ cdns,board-delay-ps = <4830>;
+ status = "disabled";
+ };
+
+ ocram: sram@0 {
+ compatible = "mmio-sram";
+ reg = <0x00000000 0x80000>;
+ ranges = <0 0 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ dmac0: dma-controller@10db0000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x10db0000 0x500>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
+ <&clkmgr AGILEX5_L4_MP_CLK>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <2>;
+ snps,block-size = <32767 32767 32767 32767>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <8>;
+ };
+
+ dmac1: dma-controller@10dc0000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x10dc0000 0x500>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
+ <&clkmgr AGILEX5_L4_MP_CLK>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <2>;
+ snps,block-size = <32767 32767 32767 32767>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <8>;
+ };
+
+ rst: rstmgr@10d11000 {
+ compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
+ reg = <0x10d11000 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ spi0: spi@10da4000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x10da4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst SPIM0_RESET>;
+ reset-names = "spi";
+ reg-io-width = <4>;
+ num-cs = <4>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+ dmas = <&dmac0 2>, <&dmac0 3>;
+ dma-names ="tx", "rx";
+ status = "disabled";
+
+ };
+
+ spi1: spi@10da5000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x10da5000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst SPIM1_RESET>;
+ reset-names = "spi";
+ reg-io-width = <4>;
+ num-cs = <4>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+ status = "disabled";
+ };
+
+ sysmgr: sysmgr@10d12000 {
+ compatible = "altr,sys-mgr-s10","altr,sys-mgr";
+ reg = <0x10d12000 0x500>;
+ };
+
+ timer0: timer0@10c03000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x10c03000 0x100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-names = "timer";
+ };
+
+ timer1: timer1@10c03100 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x10c03100 0x100>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-names = "timer";
+ };
+
+ timer2: timer2@10d00000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x10d00000 0x100>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-names = "timer";
+ };
+
+ timer3: timer3@10d00100 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x10d00100 0x100>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-names = "timer";
+ };
+
+ uart0: serial@10c02000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10c02000 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART0_RESET>;
+ status = "disabled";
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ };
+
+ uart1: serial@10c02100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10c02100 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART1_RESET>;
+ status = "disabled";
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ };
+
+ usb0: usb@10b00000 {
+ compatible = "snps,dwc2";
+ reg = <0x10b00000 0x40000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
+ reset-names = "dwc2", "dwc2-ecc";
+ clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@10d00200 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00200 0x100>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst WATCHDOG0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog1: watchdog@10d00300 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00300 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst WATCHDOG1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog2: watchdog@10d00400 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00400 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst WATCHDOG2_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog3: watchdog@10d00500 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00500 0x100>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst WATCHDOG3_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog4: watchdog@10d00600 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00600 0x100>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst WATCHDOG4_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ qspi: spi@108d2000 {
+ compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
+ reg = <0x108d2000 0x100>,
+ <0x10900000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
new file mode 100644
index 000000000000..c533e5a3a610
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, Intel Corporation
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex5 SoCDK";
+ compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
2.25.1

2023-08-01 02:54:37

[permalink] [raw]

Subject: [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible

From: Niravkumar L Rabara <[email protected]>

Agilex5 is a new SoCFPGA in Intel Agilex SoCFPGA Family,
include compatible string for Agilex5 SoCFPGA board.

Reviewed-by: Dinh Nguyen <[email protected]>
Signed-off-by: Niravkumar L Rabara <[email protected]>
---
Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
index 4b4dcf551eb6..2ee0c740eb56 100644
--- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
+++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
@@ -21,6 +21,11 @@ properties:
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
+ - description: Agilex5 boards
+ items:
+ - enum:
+ - intel,socfpga-agilex5-socdk
+ - const: intel,socfpga-agilex5

additionalProperties: true

--
2.25.1

2023-08-01 03:22:32

[permalink] [raw]

Subject: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5

From: Niravkumar L Rabara <[email protected]>

Add support for Intel's SoCFPGA Agilex5 platform. The clock manager
driver for the Agilex5 is very similar to the Agilex platform,we can
re-use most of the Agilex clock driver.

Signed-off-by: Teh Wen Ping <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
Signed-off-by: Niravkumar L Rabara <[email protected]>
---
drivers/clk/socfpga/clk-agilex.c | 433 ++++++++++++++++++++++++++++++-
1 file changed, 431 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 74d21bd82710..3dcd0f233c17 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019, Intel Corporation
+ * Copyright (C) 2019-2023, Intel Corporation
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
@@ -9,6 +9,7 @@
#include <linux/platform_device.h>

#include <dt-bindings/clock/agilex-clock.h>
+#include <dt-bindings/clock/intel,agilex5-clkmgr.h>

#include "stratix10-clk.h"

@@ -41,6 +42,67 @@ static const struct clk_parent_data mpu_free_mux[] = {
.name = "f2s-free-clk", },
};

+static const struct clk_parent_data core0_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c0",
+ .name = "peri_pll_c0", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data core1_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c0",
+ .name = "peri_pll_c0", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data core2_free_mux[] = {
+ { .fw_name = "main_pll_c0",
+ .name = "main_pll_c0", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data core3_free_mux[] = {
+ { .fw_name = "main_pll_c0",
+ .name = "main_pll_c0", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data dsu_free_mux[] = {
+ { .fw_name = "main_pll_c2",
+ .name = "main_pll_c2", },
+ { .fw_name = "peri_pll_c0",
+ .name = "peri_pll_c0", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
static const struct clk_parent_data noc_free_mux[] = {
{ .fw_name = "main_pll_c1",
.name = "main_pll_c1", },
@@ -53,7 +115,6 @@ static const struct clk_parent_data noc_free_mux[] = {
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
-
static const struct clk_parent_data emaca_free_mux[] = {
{ .fw_name = "main_pll_c2",
.name = "main_pll_c2", },
@@ -158,6 +219,110 @@ static const struct clk_parent_data s2f_usr1_free_mux[] = {
.name = "f2s-free-clk", },
};

+static const struct clk_parent_data agilex5_emaca_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data agilex5_emacb_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data agilex5_emac_ptp_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data agilex5_gpio_db_free_mux[] = {
+ { .fw_name = "main_pll_c3",
+ .name = "main_pll_c3", },
+ { .fw_name = "peri_pll_c1",
+ .name = "peri_pll_c1", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data agilex5_psi_ref_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data agilex5_usb31_free_mux[] = {
+ { .fw_name = "main_pll_c3",
+ .name = "main_pll_c3", },
+ { .fw_name = "peri_pll_c2",
+ .name = "peri_pll_c2", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data agilex5_s2f_usr0_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data agilex5_s2f_usr1_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
static const struct clk_parent_data mpu_mux[] = {
{ .fw_name = "mpu_free_clk",
.name = "mpu_free_clk", },
@@ -165,6 +330,41 @@ static const struct clk_parent_data mpu_mux[] = {
.name = "boot_clk", },
};

+static const struct clk_parent_data core0_mux[] = {
+ { .fw_name = "core0_free_clk",
+ .name = "core0_free_clk", },
+ { .fw_name = "boot_clk",
+ .name = "boot_clk", },
+};
+
+static const struct clk_parent_data core1_mux[] = {
+ { .fw_name = "core1_free_clk",
+ .name = "core1_free_clk", },
+ { .fw_name = "boot_clk",
+ .name = "boot_clk", },
+};
+
+static const struct clk_parent_data core2_mux[] = {
+ { .fw_name = "core2_free_clk",
+ .name = "core2_free_clk", },
+ { .fw_name = "boot_clk",
+ .name = "boot_clk", },
+};
+
+static const struct clk_parent_data core3_mux[] = {
+ { .fw_name = "core3_free_clk",
+ .name = "core3_free_clk", },
+ { .fw_name = "boot_clk",
+ .name = "boot_clk", },
+};
+
+static const struct clk_parent_data dsu_mux[] = {
+ { .fw_name = "dsu_free_clk",
+ .name = "dsu_free_clk", },
+ { .fw_name = "boot_clk",
+ .name = "boot_clk", },
+};
+
static const struct clk_parent_data emac_mux[] = {
{ .fw_name = "emaca_free_clk",
.name = "emaca_free_clk", },
@@ -223,6 +423,13 @@ static const struct clk_parent_data emac_ptp_mux[] = {
.name = "boot_clk", },
};

+static const struct clk_parent_data usb31_mux[] = {
+ { .fw_name = "usb31_free_clk",
+ .name = "usb31_free_clk", },
+ { .fw_name = "boot_clk",
+ .name = "boot_clk", },
+};
+
/* clocks in AO (always on) controller */
static const struct stratix10_pll_clock agilex_pll_clks[] = {
{ AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
@@ -255,6 +462,25 @@ static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
{ AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
};

+static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = {
+ { AGILEX5_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0,
+ 0x5C },
+ { AGILEX5_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0,
+ 0x60 },
+ { AGILEX5_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0,
+ 0x64 },
+ { AGILEX5_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0,
+ 0x68 },
+ { AGILEX5_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0,
+ 0xB0 },
+ { AGILEX5_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0,
+ 0xB4 },
+ { AGILEX5_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0,
+ 0xB8 },
+ { AGILEX5_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0,
+ 0xBC },
+};
+
static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
{ AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
0, 0x3C, 0, 0, 0},
@@ -280,6 +506,46 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
};

+/* Non-SW clock-gated enabled clocks */
+static const struct stratix10_perip_cnt_clock agilex5_main_perip_cnt_clks[] = {
+ { AGILEX5_CORE0_FREE_CLK, "core0_free_clk", NULL, core0_free_mux,
+ ARRAY_SIZE(core0_free_mux), 0, 0x0104, 0, 0, 0 },
+ { AGILEX5_CORE1_FREE_CLK, "core1_free_clk", NULL, core1_free_mux,
+ ARRAY_SIZE(core1_free_mux), 0, 0x0104, 0, 0, 0 },
+ { AGILEX5_CORE2_FREE_CLK, "core2_free_clk", NULL, core2_free_mux,
+ ARRAY_SIZE(core2_free_mux), 0, 0x010C, 0, 0, 0 },
+ { AGILEX5_CORE3_FREE_CLK, "core3_free_clk", NULL, core3_free_mux,
+ ARRAY_SIZE(core3_free_mux), 0, 0x0110, 0, 0, 0 },
+ { AGILEX5_DSU_FREE_CLK, "dsu_free_clk", NULL, dsu_free_mux,
+ ARRAY_SIZE(dsu_free_mux), 0, 0x0100, 0, 0, 0 },
+ { AGILEX5_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux,
+ ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 },
+ { AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", NULL,
+ agilex5_emaca_free_mux, ARRAY_SIZE(agilex5_emaca_free_mux), 0, 0xD4,
+ 0, 0x88, 0 },
+ { AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", NULL,
+ agilex5_emacb_free_mux, ARRAY_SIZE(agilex5_emacb_free_mux), 0, 0xD8,
+ 0, 0x88, 1 },
+ { AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL,
+ agilex5_emac_ptp_free_mux, ARRAY_SIZE(agilex5_emac_ptp_free_mux), 0,
+ 0xDC, 0, 0x88, 2 },
+ { AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL,
+ agilex5_gpio_db_free_mux, ARRAY_SIZE(agilex5_gpio_db_free_mux), 0,
+ 0xE0, 0, 0x88, 3 },
+ { AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL,
+ agilex5_s2f_usr0_free_mux, ARRAY_SIZE(agilex5_s2f_usr0_free_mux), 0,
+ 0xE8, 0, 0x30, 2 },
+ { AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL,
+ agilex5_s2f_usr1_free_mux, ARRAY_SIZE(agilex5_s2f_usr1_free_mux), 0,
+ 0xEC, 0, 0x88, 5 },
+ { AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL,
+ agilex5_psi_ref_free_mux, ARRAY_SIZE(agilex5_psi_ref_free_mux), 0,
+ 0xF0, 0, 0x88, 6 },
+ { AGILEX5_USB31_FREE_CLK, "usb31_free_clk", NULL,
+ agilex5_usb31_free_mux, ARRAY_SIZE(agilex5_usb31_free_mux), 0, 0xF8,
+ 0, 0x88, 7 },
+};
+
static const struct stratix10_gate_clock agilex_gate_clks[] = {
{ AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
0, 0, 0, 0, 0x30, 0, 0},
@@ -335,6 +601,122 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
10, 0, 0, 0, 0, 0, 4},
};

+/* SW Clock gate enabled clocks */
+static const struct stratix10_gate_clock agilex5_gate_clks[] = {
+ /* Main PLL0 Begin */
+ /* MPU clocks */
+ { AGILEX5_CORE0_CLK, "core0_clk", NULL, core0_mux,
+ ARRAY_SIZE(core0_mux), 0, 0x24, 8, 0, 0, 0, 0x30, 5, 0 },
+ { AGILEX5_CORE1_CLK, "core1_clk", NULL, core1_mux,
+ ARRAY_SIZE(core1_mux), 0, 0x24, 9, 0, 0, 0, 0x30, 5, 0 },
+ { AGILEX5_CORE2_CLK, "core2_clk", NULL, core2_mux,
+ ARRAY_SIZE(core2_mux), 0, 0x24, 10, 0, 0, 0, 0x30, 6, 0 },
+ { AGILEX5_CORE3_CLK, "core3_clk", NULL, core3_mux,
+ ARRAY_SIZE(core3_mux), 0, 0x24, 11, 0, 0, 0, 0x30, 7, 0 },
+ { AGILEX5_MPU_CLK, "dsu_clk", NULL, dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0,
+ 0, 0, 0, 0, 0x34, 4, 0 },
+ { AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", NULL, dsu_mux,
+ ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 20, 2, 0x34, 4, 0 },
+ { AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", NULL, dsu_mux,
+ ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 18, 2, 0x34, 4, 0 },
+ { AGILEX5_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux,
+ ARRAY_SIZE(noc_mux), 0, 0x24, 1, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
+ 0x24, 2, 0x44, 4, 2, 0x30, 1, 0 },
+ { AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux,
+ ARRAY_SIZE(noc_mux), 0, 0, 0, 0x44, 2, 2, 0x30, 1, 0 },
+ { AGILEX5_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
+ CLK_IS_CRITICAL, 0x24, 3, 0x44, 6, 2, 0x30, 1, 0 },
+
+ /* Core sight clocks*/
+ { AGILEX5_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
+ 0x24, 4, 0x44, 24, 2, 0x30, 1, 0 },
+ { AGILEX5_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux,
+ ARRAY_SIZE(noc_mux), 0, 0x24, 4, 0x44, 26, 2, 0x30, 1, 0 },
+ { AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, 4,
+ 0x44, 28, 1, 0, 0, 0 },
+ /* Main PLL0 End */
+
+ /* Main Peripheral PLL1 Begin */
+ { AGILEX5_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+ 0, 0x7C, 0, 0, 0, 0, 0x94, 26, 0 },
+ { AGILEX5_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+ 0, 0x7C, 1, 0, 0, 0, 0x94, 27, 0 },
+ { AGILEX5_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+ 0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0 },
+ { AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux,
+ ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, 3, 0, 0, 0, 0x88, 2, 0 },
+ { AGILEX5_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux,
+ ARRAY_SIZE(gpio_db_mux), 0, 0x7C, 4, 0x98, 0, 16, 0x88, 3, 1 },
+ /* Main Peripheral PLL1 End */
+
+ /* Peripheral clocks */
+ { AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux,
+ ARRAY_SIZE(s2f_user0_mux), 0, 0x24, 6, 0, 0, 0, 0x30, 2, 0 },
+ { AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux,
+ ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0 },
+ { AGILEX5_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux,
+ ARRAY_SIZE(psi_mux), 0, 0x7C, 7, 0, 0, 0, 0x88, 6, 0 },
+ { AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", NULL, usb31_mux,
+ ARRAY_SIZE(usb31_mux), 0, 0x7C, 25, 0, 0, 0, 0x88, 7, 0 },
+ { AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", "l4_main_clk",
+ NULL, 1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+ 8, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPIM_0_CLK, "spim_0_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 9,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPIM_1_CLK, "spim_1_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 11,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPIS_0_CLK, "spis_0_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 12,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPIS_1_CLK, "spis_1_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 13,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_DMA_CORE_CLK, "dma_core_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+ 14, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_DMA_HS_CLK, "dma_hs_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 14,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", "l4_mp_clk", NULL, 1, 0,
+ 0x7C, 18, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", "l4_mp_clk", NULL, 1, 0,
+ 0x7C, 19, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_0_PCLK, "i2c_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 15,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_1_PCLK, "i2c_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 16,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 17, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 22, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 27, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_UART_0_PCLK, "uart_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 20,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_UART_1_PCLK, "uart_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 21,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 23, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", "l4_sp_clk", NULL, 1, 0,
+ 0x7C, 24, 0, 0, 0, 0, 0, 0 },
+
+ /* NAND, SD/MMC and SoftPHY overall clocking */
+ { AGILEX5_DFI_CLK, "dfi_clk", "l4_mp_clk", NULL, 1, 0, 0, 0, 0x44, 16,
+ 2, 0, 0, 0 },
+ { AGILEX5_NAND_NF_CLK, "nand_nf_clk", "dfi_clk", NULL, 1, 0, 0x7C, 10,
+ 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_NAND_BCH_CLK, "nand_bch_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+ 10, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", "l4_mp_clk", NULL,
+ 1, 0, 0x7C, 5, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SDMCLK, "sdmclk", "dfi_clk", NULL, 1, 0, 0x7C, 5, 0, 0, 0, 0,
+ 0, 0 },
+ { AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", "l4_mp_clk", NULL, 1, 0,
+ 0x7C, 26, 0, 0, 0, 0, 0, 0 },
+ { AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", "l4_mp_clk", NULL, 1, 0,
+ 0x7C, 26, 0x44, 16, 2, 0, 0, 0 },
+ { AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", "dfi_clk", NULL, 1, 0,
+ 0x7C, 26, 0, 0, 0, 0, 0, 0 },
+};
+
static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
int nums, struct stratix10_clock_data *data)
{
@@ -535,6 +917,51 @@ static int n5x_clkmgr_init(struct platform_device *pdev)
return 0;
}

+static int agilex5_clkmgr_init(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct stratix10_clock_data *clk_data;
+ struct resource *res;
+ void __iomem *base;
+ int i, num_clks;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ num_clks = AGILEX5_NUM_CLKS;
+
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
+ num_clks), GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ for (i = 0; i < num_clks; i++)
+ clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
+
+ clk_data->base = base;
+ clk_data->clk_data.num = num_clks;
+
+ agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks),
+ clk_data);
+
+ agilex_clk_register_c_perip(agilex5_main_perip_c_clks,
+ ARRAY_SIZE(agilex5_main_perip_c_clks),
+ clk_data);
+
+ agilex_clk_register_cnt_perip(agilex5_main_perip_cnt_clks,
+ ARRAY_SIZE(agilex5_main_perip_cnt_clks),
+ clk_data);
+
+ agilex_clk_register_gate(agilex5_gate_clks,
+ ARRAY_SIZE(agilex5_gate_clks), clk_data);
+
+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
+ return 0;
+}
+
static int agilex_clkmgr_probe(struct platform_device *pdev)
{
int (*probe_func)(struct platform_device *init_func);
@@ -550,6 +977,8 @@ static const struct of_device_id agilex_clkmgr_match_table[] = {
.data = agilex_clkmgr_init },
{ .compatible = "intel,easic-n5x-clkmgr",
.data = n5x_clkmgr_init },
+ { .compatible = "intel,agilex5-clkmgr",
+ .data = agilex5_clkmgr_init },
{ }
};

--
2.25.1

2023-08-01 21:26:08

[permalink] [raw]

Subject: Re: [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible

On Tue, Aug 01, 2023 at 09:02:30AM +0800, [email protected] wrote:
> From: Niravkumar L Rabara <[email protected]>
>
> Agilex5 is a new SoCFPGA in Intel Agilex SoCFPGA Family,
> include compatible string for Agilex5 SoCFPGA board.
>
> Reviewed-by: Dinh Nguyen <[email protected]>
> Signed-off-by: Niravkumar L Rabara <[email protected]>

Acked-by: Conor Dooley <[email protected]>

Cheers,
Conor.

> ---
> Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> index 4b4dcf551eb6..2ee0c740eb56 100644
> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
> @@ -21,6 +21,11 @@ properties:
> - intel,socfpga-agilex-n6000
> - intel,socfpga-agilex-socdk
> - const: intel,socfpga-agilex
> + - description: Agilex5 boards
> + items:
> + - enum:
> + - intel,socfpga-agilex5-socdk
> + - const: intel,socfpga-agilex5
>
> additionalProperties: true
>
> --
> 2.25.1
>

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2023-08-01 21:26:23

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Subject: Re: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

On Tue, Aug 01, 2023 at 09:02:32AM +0800, [email protected] wrote:
> From: Niravkumar L Rabara <[email protected]>
>
> Add clock ID definitions for Intel Agilex5 SoCFPGA.
> The registers in Agilex5 handling the clock is named as clock manager.
>
> Signed-off-by: Teh Wen Ping <[email protected]>
> Reviewed-by: Dinh Nguyen <[email protected]>
> Signed-off-by: Niravkumar L Rabara <[email protected]>
> ---
> .../bindings/clock/intel,agilex5-clkmgr.yaml | 41 +++++++
> .../dt-bindings/clock/intel,agilex5-clkmgr.h | 100 ++++++++++++++++++
> 2 files changed, 141 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h
>
> diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> new file mode 100644
> index 000000000000..60e57a9fb939
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel SoCFPGA Agilex5 clock manager
> +
> +maintainers:
> + - Dinh Nguyen <[email protected]>
> +
> +description:
> + The Intel Agilex5 Clock Manager is an integrated clock controller, which
> + generates and supplies clock to all the modules.
> +
> +properties:
> + compatible:
> + const: intel,agilex5-clkmgr
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:

> + # Clock controller node:

This comment seems utterly pointless.
Otherwise this looks okay to me.

Reviewed-by: Conor Dooley <[email protected]>

Thanks,
Conor.

> + - |
> + clkmgr: clock-controller@10d10000 {
> + compatible = "intel,agilex5-clkmgr";
> + reg = <0x10d10000 0x1000>;
> + #clock-cells = <1>;
> + };
> +...

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2023-08-02 04:12:13

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Subject: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

From: Niravkumar L Rabara <[email protected]>

Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.

Signed-off-by: Teh Wen Ping <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Niravkumar L Rabara <[email protected]>
---
.../bindings/clock/intel,agilex5-clkmgr.yaml | 40 +++++++
.../dt-bindings/clock/intel,agilex5-clkmgr.h | 100 ++++++++++++++++++
2 files changed, 140 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h

diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
new file mode 100644
index 000000000000..d120b0da7f3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Agilex5 clock manager
+
+maintainers:
+ - Dinh Nguyen <[email protected]>
+
+description:
+ The Intel Agilex5 Clock Manager is an integrated clock controller, which
+ generates and supplies clock to all the modules.
+
+properties:
+ compatible:
+ const: intel,agilex5-clkmgr
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clkmgr: clock-controller@10d10000 {
+ compatible = "intel,agilex5-clkmgr";
+ reg = <0x10d10000 0x1000>;
+ #clock-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/intel,agilex5-clkmgr.h b/include/dt-bindings/clock/intel,agilex5-clkmgr.h
new file mode 100644
index 000000000000..2f3a23b31c5c
--- /dev/null
+++ b/include/dt-bindings/clock/intel,agilex5-clkmgr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023, Intel Corporation
+ */
+
+#ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
+#define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
+
+/* fixed rate clocks */
+#define AGILEX5_OSC1 0
+#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1
+#define AGILEX5_CB_INTOSC_LS_CLK 2
+#define AGILEX5_F2S_FREE_CLK 3
+
+/* PLL clocks */
+#define AGILEX5_MAIN_PLL_CLK 4
+#define AGILEX5_MAIN_PLL_C0_CLK 5
+#define AGILEX5_MAIN_PLL_C1_CLK 6
+#define AGILEX5_MAIN_PLL_C2_CLK 7
+#define AGILEX5_MAIN_PLL_C3_CLK 8
+#define AGILEX5_PERIPH_PLL_CLK 9
+#define AGILEX5_PERIPH_PLL_C0_CLK 10
+#define AGILEX5_PERIPH_PLL_C1_CLK 11
+#define AGILEX5_PERIPH_PLL_C2_CLK 12
+#define AGILEX5_PERIPH_PLL_C3_CLK 13
+#define AGILEX5_CORE0_FREE_CLK 14
+#define AGILEX5_CORE1_FREE_CLK 15
+#define AGILEX5_CORE2_FREE_CLK 16
+#define AGILEX5_CORE3_FREE_CLK 17
+#define AGILEX5_DSU_FREE_CLK 18
+#define AGILEX5_BOOT_CLK 19
+
+/* fixed factor clocks */
+#define AGILEX5_L3_MAIN_FREE_CLK 20
+#define AGILEX5_NOC_FREE_CLK 21
+#define AGILEX5_S2F_USR0_CLK 22
+#define AGILEX5_NOC_CLK 23
+#define AGILEX5_EMAC_A_FREE_CLK 24
+#define AGILEX5_EMAC_B_FREE_CLK 25
+#define AGILEX5_EMAC_PTP_FREE_CLK 26
+#define AGILEX5_GPIO_DB_FREE_CLK 27
+#define AGILEX5_S2F_USER0_FREE_CLK 28
+#define AGILEX5_S2F_USER1_FREE_CLK 29
+#define AGILEX5_PSI_REF_FREE_CLK 30
+#define AGILEX5_USB31_FREE_CLK 31
+
+/* Gate clocks */
+#define AGILEX5_CORE0_CLK 32
+#define AGILEX5_CORE1_CLK 33
+#define AGILEX5_CORE2_CLK 34
+#define AGILEX5_CORE3_CLK 35
+#define AGILEX5_MPU_CLK 36
+#define AGILEX5_MPU_PERIPH_CLK 37
+#define AGILEX5_MPU_CCU_CLK 38
+#define AGILEX5_L4_MAIN_CLK 39
+#define AGILEX5_L4_MP_CLK 40
+#define AGILEX5_L4_SYS_FREE_CLK 41
+#define AGILEX5_L4_SP_CLK 42
+#define AGILEX5_CS_AT_CLK 43
+#define AGILEX5_CS_TRACE_CLK 44
+#define AGILEX5_CS_PDBG_CLK 45
+#define AGILEX5_EMAC1_CLK 47
+#define AGILEX5_EMAC2_CLK 48
+#define AGILEX5_EMAC_PTP_CLK 49
+#define AGILEX5_GPIO_DB_CLK 50
+#define AGILEX5_S2F_USER0_CLK 51
+#define AGILEX5_S2F_USER1_CLK 52
+#define AGILEX5_PSI_REF_CLK 53
+#define AGILEX5_USB31_SUSPEND_CLK 54
+#define AGILEX5_EMAC0_CLK 46
+#define AGILEX5_USB31_BUS_CLK_EARLY 55
+#define AGILEX5_USB2OTG_HCLK 56
+#define AGILEX5_SPIM_0_CLK 57
+#define AGILEX5_SPIM_1_CLK 58
+#define AGILEX5_SPIS_0_CLK 59
+#define AGILEX5_SPIS_1_CLK 60
+#define AGILEX5_DMA_CORE_CLK 61
+#define AGILEX5_DMA_HS_CLK 62
+#define AGILEX5_I3C_0_CORE_CLK 63
+#define AGILEX5_I3C_1_CORE_CLK 64
+#define AGILEX5_I2C_0_PCLK 65
+#define AGILEX5_I2C_1_PCLK 66
+#define AGILEX5_I2C_EMAC0_PCLK 67
+#define AGILEX5_I2C_EMAC1_PCLK 68
+#define AGILEX5_I2C_EMAC2_PCLK 69
+#define AGILEX5_UART_0_PCLK 70
+#define AGILEX5_UART_1_PCLK 71
+#define AGILEX5_SPTIMER_0_PCLK 72
+#define AGILEX5_SPTIMER_1_PCLK 73
+#define AGILEX5_DFI_CLK 74
+#define AGILEX5_NAND_NF_CLK 75
+#define AGILEX5_NAND_BCH_CLK 76
+#define AGILEX5_SDMMC_SDPHY_REG_CLK 77
+#define AGILEX5_SDMCLK 78
+#define AGILEX5_SOFTPHY_REG_PCLK 79
+#define AGILEX5_SOFTPHY_PHY_CLK 80
+#define AGILEX5_SOFTPHY_CTRL_CLK 81
+#define AGILEX5_NUM_CLKS 82
+
+#endif /* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */
--
2.25.1

2023-08-02 04:22:44

[permalink] [raw]

Subject: RE: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

> -----Original Message-----
> From: Conor Dooley <[email protected]>
> Sent: Wednesday, 2 August, 2023 4:58 AM
> To: Rabara, Niravkumar L <[email protected]>
> Cc: Ng, Adrian Ho Yin <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; Turquette, Mike <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: Re: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager
>
> On Tue, Aug 01, 2023 at 09:02:32AM +0800, [email protected]
> wrote:
> > From: Niravkumar L Rabara <[email protected]>
> >
> > Add clock ID definitions for Intel Agilex5 SoCFPGA.
> > The registers in Agilex5 handling the clock is named as clock manager.
> >
> > Signed-off-by: Teh Wen Ping <[email protected]>
> > Reviewed-by: Dinh Nguyen <[email protected]>
> > Signed-off-by: Niravkumar L Rabara <[email protected]>
> > ---
> > .../bindings/clock/intel,agilex5-clkmgr.yaml | 41 +++++++
> > .../dt-bindings/clock/intel,agilex5-clkmgr.h | 100 ++++++++++++++++++
> > 2 files changed, 141 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> > create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h
> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> > b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> > new file mode 100644
> > index 000000000000..60e57a9fb939
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yam
> > +++ l
> > @@ -0,0 +1,41 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Intel SoCFPGA Agilex5 clock manager
> > +
> > +maintainers:
> > + - Dinh Nguyen <[email protected]>
> > +
> > +description:
> > + The Intel Agilex5 Clock Manager is an integrated clock controller,
> > +which
> > + generates and supplies clock to all the modules.
> > +
> > +properties:
> > + compatible:
> > + const: intel,agilex5-clkmgr
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
>
> > + # Clock controller node:
>
> This comment seems utterly pointless.
> Otherwise this looks okay to me.
>
> Reviewed-by: Conor Dooley <[email protected]>
>
> Thanks,
> Conor.
>

Removed in [PATCH v3 3/5].

Thanks,
Nirav

> > + - |
> > + clkmgr: clock-controller@10d10000 {
> > + compatible = "intel,agilex5-clkmgr";
> > + reg = <0x10d10000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +...

2023-08-02 07:23:57

[permalink] [raw]

Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

On Wed, Aug 02, 2023 at 10:58:42AM +0800, [email protected] wrote:
> From: Niravkumar L Rabara <[email protected]>
>
> Add clock ID definitions for Intel Agilex5 SoCFPGA.
> The registers in Agilex5 handling the clock is named as clock manager.
>
> Signed-off-by: Teh Wen Ping <[email protected]>
> Reviewed-by: Dinh Nguyen <[email protected]>
> Reviewed-by: Conor Dooley <[email protected]>
> Signed-off-by: Niravkumar L Rabara <[email protected]>

Damn, I was too late - you already sent a v3 :/

However, there only seems to be a v3 of this one patch and it was sent
in reply to the v2 series? The normal thing to do is resend the entire
series, not just one patch, as a new thread. Not using a new thread may
make it harder to apply & will also bury the email in people's mailboxes
that use things like mutt. A single patch as a reply is also confusing,
as the rest of the v3 looks like it is missing!

Thanks,
Conor.

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2023-08-02 07:47:13

[permalink] [raw]

Subject: Re: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

On Wed, Aug 02, 2023 at 03:06:51AM +0000, Rabara, Niravkumar L wrote:
> > From: Conor Dooley <[email protected]>
> > On Tue, Aug 01, 2023 at 09:02:32AM +0800, [email protected]
> > wrote:

> > > +examples:
> >
> > > + # Clock controller node:
> >
> > This comment seems utterly pointless.
> > Otherwise this looks okay to me.
> >
> > Reviewed-by: Conor Dooley <[email protected]>
> >
> > Thanks,
> > Conor.
> >
>
> Removed in [PATCH v3 3/5].

To be clear, you don't need to send a v3 just for that - I gave you the
reviewed-by after all.

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2023-08-02 07:58:41

[permalink] [raw]

Subject: RE: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

> -----Original Message-----
> From: Conor Dooley <[email protected]>
> Sent: Wednesday, 2 August, 2023 3:02 PM
> To: Rabara, Niravkumar L <[email protected]>
> Cc: Ng, Adrian Ho Yin <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; Turquette, Mike <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock
> manager
>
> On Wed, Aug 02, 2023 at 10:58:42AM +0800, [email protected]
> wrote:
> > From: Niravkumar L Rabara <[email protected]>
> >
> > Add clock ID definitions for Intel Agilex5 SoCFPGA.
> > The registers in Agilex5 handling the clock is named as clock manager.
> >
> > Signed-off-by: Teh Wen Ping <[email protected]>
> > Reviewed-by: Dinh Nguyen <[email protected]>
> > Reviewed-by: Conor Dooley <[email protected]>
> > Signed-off-by: Niravkumar L Rabara <[email protected]>
>
> Damn, I was too late - you already sent a v3 :/
>
> However, there only seems to be a v3 of this one patch and it was sent in
> reply to the v2 series? The normal thing to do is resend the entire series, not
> just one patch, as a new thread. Not using a new thread may make it harder
> to apply & will also bury the email in people's mailboxes that use things like
> mutt. A single patch as a reply is also confusing, as the rest of the v3 looks like
> it is missing!
>
> Thanks,
> Conor.

Sorry I made a mistake.
Should I send out entire series with PATCH v3 subject? Or should I wait for review comment on remaining patches and then send entire series with rework and subject prefix PATCH v3?

Thanks,
Nirav

2023-08-06 19:14:15

[permalink] [raw]

Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

On 8/2/23 02:14, Rabara, Niravkumar L wrote:
>
>
>> -----Original Message-----
>> From: Conor Dooley <[email protected]>
>> Sent: Wednesday, 2 August, 2023 3:02 PM
>> To: Rabara, Niravkumar L <[email protected]>
>> Cc: Ng, Adrian Ho Yin <[email protected]>; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; linux-
>> [email protected]; Turquette, Mike <[email protected]>;
>> [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock
>> manager
>>
>> On Wed, Aug 02, 2023 at 10:58:42AM +0800, [email protected]
>> wrote:
>>> From: Niravkumar L Rabara <[email protected]>
>>>
>>> Add clock ID definitions for Intel Agilex5 SoCFPGA.
>>> The registers in Agilex5 handling the clock is named as clock manager.
>>>
>>> Signed-off-by: Teh Wen Ping <[email protected]>
>>> Reviewed-by: Dinh Nguyen <[email protected]>
>>> Reviewed-by: Conor Dooley <[email protected]>
>>> Signed-off-by: Niravkumar L Rabara <[email protected]>
>>
>> Damn, I was too late - you already sent a v3 :/
>>
>> However, there only seems to be a v3 of this one patch and it was sent in
>> reply to the v2 series? The normal thing to do is resend the entire series, not
>> just one patch, as a new thread. Not using a new thread may make it harder
>> to apply & will also bury the email in people's mailboxes that use things like
>> mutt. A single patch as a reply is also confusing, as the rest of the v3 looks like
>> it is missing!
>>
>> Thanks,
>> Conor.
>
> Sorry I made a mistake.
> Should I send out entire series with PATCH v3 subject? Or should I wait for review comment on remaining patches and then send entire series with rework and subject prefix PATCH v3?
>

No need to send out a V3. I've applied patches 1-3 and 5. Will give a
little more time for the clk patch.

Dinh

2023-08-06 21:24:37

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

On 01/08/2023 03:02, [email protected] wrote:
> From: Niravkumar L Rabara <[email protected]>
>
> Add clock ID definitions for Intel Agilex5 SoCFPGA.
> The registers in Agilex5 handling the clock is named as clock manager.
>
> Signed-off-by: Teh Wen Ping <[email protected]>
> Reviewed-by: Dinh Nguyen <[email protected]>
> Signed-off-by: Niravkumar L Rabara <[email protected]>
> ---

Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets.

Best regards,
Krzysztof

2023-08-07 05:25:19

[permalink] [raw]

Subject: RE: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager

> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Monday, 7 August, 2023 3:35 AM
> To: Rabara, Niravkumar L <[email protected]>
> Cc: Ng, Adrian Ho Yin <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; Turquette, Mike <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock
> manager
>
> On 01/08/2023 03:02, [email protected] wrote:
> > From: Niravkumar L Rabara <[email protected]>
> >
> > Add clock ID definitions for Intel Agilex5 SoCFPGA.
> > The registers in Agilex5 handling the clock is named as clock manager.
> >
> > Signed-off-by: Teh Wen Ping <[email protected]>
> > Reviewed-by: Dinh Nguyen <[email protected]>
> > Signed-off-by: Niravkumar L Rabara <[email protected]>
> > ---
>
> Do not attach (thread) your patchsets to some other threads (unrelated or
> older versions). This buries them deep in the mailbox and might interfere
> with applying entire sets.
>
> Best regards,
> Krzysztof

Sorry it was a mistake.
Will be careful now onwards.

Thanks,
Nirav

2023-08-08 17:54:31

[permalink] [raw]

Subject: Re: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5

Hi Stephen/Mike,

On 7/31/23 20:02, [email protected] wrote:
> From: Niravkumar L Rabara <[email protected]>
>
> Add support for Intel's SoCFPGA Agilex5 platform. The clock manager
> driver for the Agilex5 is very similar to the Agilex platform,we can
> re-use most of the Agilex clock driver.
>
> Signed-off-by: Teh Wen Ping <[email protected]>
> Reviewed-by: Dinh Nguyen <[email protected]>
> Signed-off-by: Niravkumar L Rabara <[email protected]>
> ---
> drivers/clk/socfpga/clk-agilex.c | 433 ++++++++++++++++++++++++++++++-
> 1 file changed, 431 insertions(+), 2 deletions(-)
>

If you're ok with this patch, can I take this through armsoc?

Dinh

2023-08-09 22:24:36

by Stephen Boyd

[permalink] [raw]

Subject: Re: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5

Quoting Dinh Nguyen (2023-08-08 04:03:47)
> Hi Stephen/Mike,
>
> On 7/31/23 20:02, [email protected] wrote:
> > From: Niravkumar L Rabara <[email protected]>
> >
> > Add support for Intel's SoCFPGA Agilex5 platform. The clock manager
> > driver for the Agilex5 is very similar to the Agilex platform,we can
> > re-use most of the Agilex clock driver.
> >
> > Signed-off-by: Teh Wen Ping <[email protected]>
> > Reviewed-by: Dinh Nguyen <[email protected]>
> > Signed-off-by: Niravkumar L Rabara <[email protected]>
> > ---
> > drivers/clk/socfpga/clk-agilex.c | 433 ++++++++++++++++++++++++++++++-
> > 1 file changed, 431 insertions(+), 2 deletions(-)
> >
>
> If you're ok with this patch, can I take this through armsoc?
>

Usually any binding files go through arm-soc and clk tree but the driver
only goes through clk tree via a PR. Is that possible here?

2023-08-09 22:50:07

by Stephen Boyd

[permalink] [raw]

Subject: Re: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5

Quoting [email protected] (2023-07-31 18:02:33)
> diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
> index 74d21bd82710..3dcd0f233c17 100644
> --- a/drivers/clk/socfpga/clk-agilex.c
> +++ b/drivers/clk/socfpga/clk-agilex.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2019, Intel Corporation
> + * Copyright (C) 2019-2023, Intel Corporation
> */
> #include <linux/slab.h>
> #include <linux/clk-provider.h>
> @@ -9,6 +9,7 @@
> #include <linux/platform_device.h>
>
> #include <dt-bindings/clock/agilex-clock.h>
> +#include <dt-bindings/clock/intel,agilex5-clkmgr.h>
>
> #include "stratix10-clk.h"
>
> @@ -41,6 +42,67 @@ static const struct clk_parent_data mpu_free_mux[] = {
> .name = "f2s-free-clk", },
> };
>
> +static const struct clk_parent_data core0_free_mux[] = {
> + { .fw_name = "main_pll_c1",
> + .name = "main_pll_c1", },

We're adding support for something new? Only set .fw_name in that case,
as .name will never be used. To do even better, set only .index so that
we don't do any string comparisons.

> + { .fw_name = "peri_pll_c0",
> + .name = "peri_pll_c0", },
> + { .fw_name = "osc1",
> + .name = "osc1", },
> + { .fw_name = "cb-intosc-hs-div2-clk",
> + .name = "cb-intosc-hs-div2-clk", },
> + { .fw_name = "f2s-free-clk",
> + .name = "f2s-free-clk", },
> +};
> +
[...]
> +
> static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
> int nums, struct stratix10_clock_data *data)
> {
> @@ -535,6 +917,51 @@ static int n5x_clkmgr_init(struct platform_device *pdev)
> return 0;
> }
>
> +static int agilex5_clkmgr_init(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct stratix10_clock_data *clk_data;

Maybe call this stratix_data so that clk_data.clk_data is
stratix_data.clk_data.

> + struct resource *res;
> + void __iomem *base;
> + int i, num_clks;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);

This is a single function call, devm_platform_ioremap_resource().

> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + num_clks = AGILEX5_NUM_CLKS;
> +
> + clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> + num_clks), GFP_KERNEL);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + for (i = 0; i < num_clks; i++)
> + clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
> +
> + clk_data->base = base;
> + clk_data->clk_data.num = num_clks;
> +
> + agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks),
> + clk_data);
> +
> + agilex_clk_register_c_perip(agilex5_main_perip_c_clks,
> + ARRAY_SIZE(agilex5_main_perip_c_clks),
> + clk_data);
> +
> + agilex_clk_register_cnt_perip(agilex5_main_perip_cnt_clks,
> + ARRAY_SIZE(agilex5_main_perip_cnt_clks),
> + clk_data);
> +
> + agilex_clk_register_gate(agilex5_gate_clks,
> + ARRAY_SIZE(agilex5_gate_clks), clk_data);
> +
> + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);

devm? Or when is this provider removed?

> + return 0;
> +}
> +
> static int agilex_clkmgr_probe(struct platform_device *pdev)
> {
> int (*probe_func)(struct platform_device *init_func);

2023-08-10 11:21:14

[permalink] [raw]

Subject: Re: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5

On 8/9/23 16:28, Stephen Boyd wrote:
> Quoting Dinh Nguyen (2023-08-08 04:03:47)
>> Hi Stephen/Mike,
>>
>> On 7/31/23 20:02, [email protected] wrote:
>>> From: Niravkumar L Rabara <[email protected]>
>>>
>>> Add support for Intel's SoCFPGA Agilex5 platform. The clock manager
>>> driver for the Agilex5 is very similar to the Agilex platform,we can
>>> re-use most of the Agilex clock driver.
>>>
>>> Signed-off-by: Teh Wen Ping <[email protected]>
>>> Reviewed-by: Dinh Nguyen <[email protected]>
>>> Signed-off-by: Niravkumar L Rabara <[email protected]>
>>> ---
>>> drivers/clk/socfpga/clk-agilex.c | 433 ++++++++++++++++++++++++++++++-
>>> 1 file changed, 431 insertions(+), 2 deletions(-)
>>>
>>
>> If you're ok with this patch, can I take this through armsoc?
>>
>
> Usually any binding files go through arm-soc and clk tree but the driver
> only goes through clk tree via a PR. Is that possible here?

Ok. Should be fine in this case.

Thanks,
Dinh

2023-08-13 14:46:35

[permalink] [raw]

Subject: RE: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5

> -----Original Message-----
> From: Stephen Boyd <[email protected]>
> Sent: Thursday, 10 August, 2023 5:27 AM
> To: Rabara, Niravkumar L <[email protected]>
> Cc: Ng, Adrian Ho Yin <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; Turquette, Mike <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5
>
> Quoting [email protected] (2023-07-31 18:02:33)
> > diff --git a/drivers/clk/socfpga/clk-agilex.c
> > b/drivers/clk/socfpga/clk-agilex.c
> > index 74d21bd82710..3dcd0f233c17 100644
> > --- a/drivers/clk/socfpga/clk-agilex.c
> > +++ b/drivers/clk/socfpga/clk-agilex.c
> > @@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0
> > /*
> > - * Copyright (C) 2019, Intel Corporation
> > + * Copyright (C) 2019-2023, Intel Corporation
> > */
> > #include <linux/slab.h>
> > #include <linux/clk-provider.h>
> > @@ -9,6 +9,7 @@
> > #include <linux/platform_device.h>
> >
> > #include <dt-bindings/clock/agilex-clock.h>
> > +#include <dt-bindings/clock/intel,agilex5-clkmgr.h>
> >
> > #include "stratix10-clk.h"
> >
> > @@ -41,6 +42,67 @@ static const struct clk_parent_data mpu_free_mux[] = {
> > .name = "f2s-free-clk", },
> > };
> >
> > +static const struct clk_parent_data core0_free_mux[] = {
> > + { .fw_name = "main_pll_c1",
> > + .name = "main_pll_c1", },
>
> We're adding support for something new? Only set .fw_name in that case, as
> .name will never be used. To do even better, set only .index so that we don't do
> any string comparisons.
>
Yes we are adding Agilex5 SoCFPGA platform specific clocks.
I will remove .name and only keep .fw_name in next version of this patch.

> > + { .fw_name = "peri_pll_c0",
> > + .name = "peri_pll_c0", },
> > + { .fw_name = "osc1",
> > + .name = "osc1", },
> > + { .fw_name = "cb-intosc-hs-div2-clk",
> > + .name = "cb-intosc-hs-div2-clk", },
> > + { .fw_name = "f2s-free-clk",
> > + .name = "f2s-free-clk", },
> > +};
> > +
> [...]
> > +
> > static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
> > int nums, struct
> > stratix10_clock_data *data) { @@ -535,6 +917,51 @@ static int
> > n5x_clkmgr_init(struct platform_device *pdev)
> > return 0;
> > }
> >
> > +static int agilex5_clkmgr_init(struct platform_device *pdev) {
> > + struct device_node *np = pdev->dev.of_node;
> > + struct device *dev = &pdev->dev;
> > + struct stratix10_clock_data *clk_data;
>
> Maybe call this stratix_data so that clk_data.clk_data is stratix_data.clk_data.

Will fix this in next version.

>
> > + struct resource *res;
> > + void __iomem *base;
> > + int i, num_clks;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + base = devm_ioremap_resource(dev, res);
>
> This is a single function call, devm_platform_ioremap_resource().i

Noted. Will fix in next version.

>
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> > +
> > + num_clks = AGILEX5_NUM_CLKS;
> > +
> > + clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> > + num_clks), GFP_KERNEL);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < num_clks; i++)
> > + clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
> > +
> > + clk_data->base = base;
> > + clk_data->clk_data.num = num_clks;
> > +
> > + agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks),
> > + clk_data);
> > +
> > + agilex_clk_register_c_perip(agilex5_main_perip_c_clks,
> > + ARRAY_SIZE(agilex5_main_perip_c_clks),
> > + clk_data);
> > +
> > + agilex_clk_register_cnt_perip(agilex5_main_perip_cnt_clks,
> > + ARRAY_SIZE(agilex5_main_perip_cnt_clks),
> > + clk_data);
> > +
> > + agilex_clk_register_gate(agilex5_gate_clks,
> > + ARRAY_SIZE(agilex5_gate_clks),
> > + clk_data);
> > +
> > + of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
> > + &clk_data->clk_data);
>
> devm? Or when is this provider removed?

Will fix in next version.

>
> > + return 0;
> > +}
> > +
> > static int agilex_clkmgr_probe(struct platform_device *pdev) {
> > int (*probe_func)(struct platform_device *init_func);

2023-08-14 03:01:30

[permalink] [raw]

Subject: Re: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5

On 8/13/23 07:53, Rabara, Niravkumar L wrote:
>
>
>> -----Original Message-----
>> From: Stephen Boyd <[email protected]>
>> Sent: Thursday, 10 August, 2023 5:27 AM
>> To: Rabara, Niravkumar L <[email protected]>
>> Cc: Ng, Adrian Ho Yin <[email protected]>; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; linux-
>> [email protected]; Turquette, Mike <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]
>> Subject: Re: [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5
>>
>> Quoting [email protected] (2023-07-31 18:02:33)
>>> diff --git a/drivers/clk/socfpga/clk-agilex.c
>>> b/drivers/clk/socfpga/clk-agilex.c
>>> index 74d21bd82710..3dcd0f233c17 100644
>>> --- a/drivers/clk/socfpga/clk-agilex.c
>>> +++ b/drivers/clk/socfpga/clk-agilex.c
>>> @@ -1,6 +1,6 @@
>>> // SPDX-License-Identifier: GPL-2.0
>>> /*
>>> - * Copyright (C) 2019, Intel Corporation
>>> + * Copyright (C) 2019-2023, Intel Corporation
>>> */
>>> #include <linux/slab.h>
>>> #include <linux/clk-provider.h>
>>> @@ -9,6 +9,7 @@
>>> #include <linux/platform_device.h>
>>>
>>> #include <dt-bindings/clock/agilex-clock.h>
>>> +#include <dt-bindings/clock/intel,agilex5-clkmgr.h>
>>>
>>> #include "stratix10-clk.h"
>>>
>>> @@ -41,6 +42,67 @@ static const struct clk_parent_data mpu_free_mux[] = {
>>> .name = "f2s-free-clk", },
>>> };
>>>
>>> +static const struct clk_parent_data core0_free_mux[] = {
>>> + { .fw_name = "main_pll_c1",
>>> + .name = "main_pll_c1", },
>>
>> We're adding support for something new? Only set .fw_name in that case, as
>> .name will never be used. To do even better, set only .index so that we don't do
>> any string comparisons.
>>
> Yes we are adding Agilex5 SoCFPGA platform specific clocks.
> I will remove .name and only keep .fw_name in next version of this patch.
>
>>> + { .fw_name = "peri_pll_c0",
>>> + .name = "peri_pll_c0", },
>>> + { .fw_name = "osc1",
>>> + .name = "osc1", },
>>> + { .fw_name = "cb-intosc-hs-div2-clk",
>>> + .name = "cb-intosc-hs-div2-clk", },
>>> + { .fw_name = "f2s-free-clk",
>>> + .name = "f2s-free-clk", },
>>> +};
>>> +
>> [...]
>>> +
>>> static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
>>> int nums, struct
>>> stratix10_clock_data *data) { @@ -535,6 +917,51 @@ static int
>>> n5x_clkmgr_init(struct platform_device *pdev)
>>> return 0;
>>> }
>>>
>>> +static int agilex5_clkmgr_init(struct platform_device *pdev) {
>>> + struct device_node *np = pdev->dev.of_node;
>>> + struct device *dev = &pdev->dev;
>>> + struct stratix10_clock_data *clk_data;
>>
>> Maybe call this stratix_data so that clk_data.clk_data is stratix_data.clk_data.
>
> Will fix this in next version.
>
>>
>>> + struct resource *res;
>>> + void __iomem *base;
>>> + int i, num_clks;
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + base = devm_ioremap_resource(dev, res);
>>
>> This is a single function call, devm_platform_ioremap_resource().i
>
> Noted. Will fix in next version.
>

When you resend a V3, just send this patch. I've already applied the
other 4 patches.

Dinh

2023-08-14 06:05:03